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qla2xxx: Schedule board_disable only once
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
e881a172 239static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 240static int qla2x00_change_queue_type(struct scsi_device *, int);
1a2fbf18 241static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 242static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 243
a5326f86 244struct scsi_host_template qla2xxx_driver_template = {
1da177e4 245 .module = THIS_MODULE,
cb63067a 246 .name = QLA2XXX_DRIVER_NAME,
a5326f86 247 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 248
249 .eh_abort_handler = qla2xxx_eh_abort,
250 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 251 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 252 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
253 .eh_host_reset_handler = qla2xxx_eh_host_reset,
254
255 .slave_configure = qla2xxx_slave_configure,
256
257 .slave_alloc = qla2xxx_slave_alloc,
258 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 259 .scan_finished = qla2xxx_scan_finished,
260 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 261 .change_queue_depth = qla2x00_change_queue_depth,
262 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 263 .this_id = -1,
264 .cmd_per_lun = 3,
265 .use_clustering = ENABLE_CLUSTERING,
266 .sg_tablesize = SG_ALL,
267
268 .max_sectors = 0xFFFF,
afb046e2 269 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 270
271 .supported_mode = MODE_INITIATOR,
fca29703
AV		 272};
273
1da177e4 274static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 275struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 276
1da177e4
LT		 277/* TODO Convert to inlines
278 *
279 * Timer routines
280 */
1da177e4 281
2c3dfe3f 282__inline__ void
e315cd28 283qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 284{
e315cd28
AC		 285 init_timer(&vha->timer);
286 vha->timer.expires = jiffies + interval * HZ;
287 vha->timer.data = (unsigned long)vha;
288 vha->timer.function = (void (*)(unsigned long))func;
289 add_timer(&vha->timer);
290 vha->timer_active = 1;
1da177e4
LT		 291}
292
293static inline void
e315cd28 294qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 295{
a9083016 296 /* Currently used for 82XX only. */
7c3df132
SK		 297 if (vha->device_flags & DFLG_DEV_FAILED) {
298 ql_dbg(ql_dbg_timer, vha, 0x600d,
299 "Device in a failed state, returning.\n");
a9083016 300 return;
7c3df132 301 }
a9083016 302
e315cd28 303 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 304}
305
a824ebb3 306static __inline__ void
e315cd28 307qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 308{
e315cd28
AC		 309 del_timer_sync(&vha->timer);
310 vha->timer_active = 0;
1da177e4
LT		 311}
312
1da177e4
LT		 313static int qla2x00_do_dpc(void *data);
314
315static void qla2x00_rst_aen(scsi_qla_host_t *);
316
73208dfd
AC		 317static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
318 struct req_que **, struct rsp_que **);
e30d1756 319static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 320static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 321
1da177e4 322/* -------------------------------------------------------------------------- */
9a347ff4
CD		 323static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
324 struct rsp_que *rsp)
73208dfd 325{
7c3df132 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 328 GFP_KERNEL);
329 if (!ha->req_q_map) {
7c3df132
SK		 330 ql_log(ql_log_fatal, vha, 0x003b,
331 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 332 goto fail_req_map;
333 }
334
2afa19a9 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 336 GFP_KERNEL);
337 if (!ha->rsp_q_map) {
7c3df132
SK		 338 ql_log(ql_log_fatal, vha, 0x003c,
339 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 340 goto fail_rsp_map;
341 }
9a347ff4
CD		 342 /*
343 * Make sure we record at least the request and response queue zero in
344 * case we need to free them if part of the probe fails.
345 */
346 ha->rsp_q_map[0] = rsp;
347 ha->req_q_map[0] = req;
73208dfd
AC		 348 set_bit(0, ha->rsp_qid_map);
349 set_bit(0, ha->req_qid_map);
350 return 1;
351
352fail_rsp_map:
353 kfree(ha->req_q_map);
354 ha->req_q_map = NULL;
355fail_req_map:
356 return -ENOMEM;
357}
358
2afa19a9 359static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 360{
8ae6d9c7
GM		 361 if (IS_QLAFX00(ha)) {
362 if (req && req->ring_fx00)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length_fx00 + 1) * sizeof(request_t),
365 req->ring_fx00, req->dma_fx00);
366 } else if (req && req->ring)
73208dfd
AC		 367 dma_free_coherent(&ha->pdev->dev,
368 (req->length + 1) * sizeof(request_t),
369 req->ring, req->dma);
370
8d93f550
CD		 371 if (req)
372 kfree(req->outstanding_cmds);
373
73208dfd
AC		 374 kfree(req);
375 req = NULL;
376}
377
2afa19a9
AC		 378static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
379{
8ae6d9c7
GM		 380 if (IS_QLAFX00(ha)) {
381 if (rsp && rsp->ring)
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length_fx00 + 1) * sizeof(request_t),
384 rsp->ring_fx00, rsp->dma_fx00);
385 } else if (rsp && rsp->ring) {
2afa19a9
AC		 386 dma_free_coherent(&ha->pdev->dev,
387 (rsp->length + 1) * sizeof(response_t),
388 rsp->ring, rsp->dma);
8ae6d9c7 389 }
2afa19a9
AC		 390 kfree(rsp);
391 rsp = NULL;
392}
393
73208dfd
AC		 394static void qla2x00_free_queues(struct qla_hw_data *ha)
395{
396 struct req_que *req;
397 struct rsp_que *rsp;
398 int cnt;
399
2afa19a9 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 401 req = ha->req_q_map[cnt];
2afa19a9 402 qla2x00_free_req_que(ha, req);
73208dfd 403 }
73208dfd
AC		 404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
2afa19a9
AC		 406
407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
408 rsp = ha->rsp_q_map[cnt];
409 qla2x00_free_rsp_que(ha, rsp);
410 }
411 kfree(ha->rsp_q_map);
412 ha->rsp_q_map = NULL;
73208dfd
AC		 413}
414
68ca949c
AC		 415static int qla25xx_setup_mode(struct scsi_qla_host *vha)
416{
417 uint16_t options = 0;
418 int ques, req, ret;
419 struct qla_hw_data *ha = vha->hw;
420
7163ea81 421 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 422 ql_log(ql_log_warn, vha, 0x00d8,
423 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 424 goto fail;
425 }
68ca949c 426 if (ql2xmultique_tag) {
68ca949c
AC		 427 /* create a request queue for IO */
428 options |= BIT_7;
429 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
430 QLA_DEFAULT_QUE_QOS);
431 if (!req) {
7c3df132
SK		 432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to create request queue.\n");
68ca949c
AC		 434 goto fail;
435 }
278274d5 436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 437 vha->req = ha->req_q_map[req];
438 options |= BIT_1;
439 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
441 if (!ret) {
7c3df132
SK		 442 ql_log(ql_log_warn, vha, 0x00e8,
443 "Failed to create response queue.\n");
68ca949c
AC		 444 goto fail2;
445 }
446 }
7163ea81 447 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 448 ql_dbg(ql_dbg_multiq, vha, 0xc007,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 ql_dbg(ql_dbg_init, vha, 0x00e9,
453 "CPU affinity mode enalbed, "
454 "no. of response queues:%d no. of request queues:%d.\n",
455 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 456 }
457 return 0;
458fail2:
459 qla25xx_delete_queues(vha);
7163ea81
AC		 460 destroy_workqueue(ha->wq);
461 ha->wq = NULL;
0cd33fcf 462 vha->req = ha->req_q_map[0];
68ca949c
AC		 463fail:
464 ha->mqenable = 0;
7163ea81
AC		 465 kfree(ha->req_q_map);
466 kfree(ha->rsp_q_map);
467 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 468 return 1;
469}
470
1da177e4 471static char *
e315cd28 472qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 473{
e315cd28 474 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 475 static char *pci_bus_modes[] = {
476 "33", "66", "100", "133",
477 };
478 uint16_t pci_bus;
479
480 strcpy(str, "PCI");
481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
482 if (pci_bus) {
483 strcat(str, "-X (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 } else {
486 pci_bus = (ha->pci_attr & BIT_8) >> 8;
487 strcat(str, " (");
488 strcat(str, pci_bus_modes[pci_bus]);
489 }
490 strcat(str, " MHz)");
491
492 return (str);
493}
494
fca29703 495static char *
e315cd28 496qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 497{
498 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 499 struct qla_hw_data *ha = vha->hw;
fca29703 500 uint32_t pci_bus;
fca29703 501
62a276f8 502 if (pci_is_pcie(ha->pdev)) {
fca29703 503 char lwstr[6];
62a276f8 504 uint32_t lstat, lspeed, lwidth;
fca29703 505
62a276f8
BH		 506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
507 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 509
510 strcpy(str, "PCIe (");
49300af7
SK		 511 switch (lspeed) {
512 case 1:
c87a0d8c 513 strcat(str, "2.5GT/s ");
49300af7
SK		 514 break;
515 case 2:
c87a0d8c 516 strcat(str, "5.0GT/s ");
49300af7
SK		 517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
fca29703 522 strcat(str, "<unknown> ");
49300af7
SK		 523 break;
524 }
fca29703
AV		 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548}
549
e5f82ab8 550static char *
e315cd28 551qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 552{
553 char un_str[10];
e315cd28 554 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 555
1da177e4
LT		 556 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version,
558 ha->fw_subminor_version);
559
560 if (ha->fw_attributes & BIT_9) {
561 strcat(str, "FLX");
562 return (str);
563 }
564
565 switch (ha->fw_attributes & 0xFF) {
566 case 0x7:
567 strcat(str, "EF");
568 break;
569 case 0x17:
570 strcat(str, "TP");
571 break;
572 case 0x37:
573 strcat(str, "IP");
574 break;
575 case 0x77:
576 strcat(str, "VI");
577 break;
578 default:
579 sprintf(un_str, "(%x)", ha->fw_attributes);
580 strcat(str, un_str);
581 break;
582 }
583 if (ha->fw_attributes & 0x100)
584 strcat(str, "X");
585
586 return (str);
587}
588
e5f82ab8 589static char *
e315cd28 590qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 591{
e315cd28 592 struct qla_hw_data *ha = vha->hw;
f0883ac6 593
3a03eb79
AV		 594 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 596 return str;
fca29703
AV		 597}
598
9ba56b95
GM		 599void
600qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 601{
9ba56b95
GM		 602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 606
9ba56b95
GM		 607 if (sp->flags & SRB_DMA_VALID) {
608 scsi_dma_unmap(cmd);
609 sp->flags &= ~SRB_DMA_VALID;
7c3df132 610 }
fca29703 611
9ba56b95
GM		 612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
616 }
617
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
f83adb61 620 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
622 }
623
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
628 }
629
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 632
9ba56b95
GM		 633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
634 ctx1->fcp_cmnd_dma);
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
639 ctx1 = NULL;
640 }
641
642 CMD_SP(cmd) = NULL;
b00ee7d7 643 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 644}
645
14b06808 646static void
9ba56b95
GM		 647qla2x00_sp_compl(void *data, void *ptr, int res)
648{
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
652
653 cmd->result = res;
654
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
658 sp, GET_CMD_SP(sp));
659 if (ql2xextended_error_logging & ql_dbg_io)
660 BUG();
661 return;
662 }
663 if (!atomic_dec_and_test(&sp->ref_count))
664 return;
665
666 qla2x00_sp_free_dma(ha, sp);
667 cmd->scsi_done(cmd);
fca29703
AV		 668}
669
8ae6d9c7
GM		 670/* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
672 */
1da177e4 673static int
f5e3e40b 674qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 675{
134ae078 676 scsi_qla_host_t *vha = shost_priv(host);
fca29703 677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 681 srb_t *sp;
682 int rval;
683
85880801 684 if (ha->flags.eeh_busy) {
7c3df132 685 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 686 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 687 "PCI Channel IO permanent failure, exiting "
688 "cmd=%p.\n", cmd);
b9b12f73 689 cmd->result = DID_NO_CONNECT << 16;
7c3df132 690 } else {
5f28d2d7 691 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 693 cmd->result = DID_REQUEUE << 16;
7c3df132 694 }
14e660e6
SJ		 695 goto qc24_fail_command;
696 }
697
19a7b4ae
JSEC		 698 rval = fc_remote_port_chkready(rport);
699 if (rval) {
700 cmd->result = rval;
5f28d2d7 701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
703 cmd, rval);
fca29703
AV		 704 goto qc24_fail_command;
705 }
706
bad75002
AE		 707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
711 cmd);
bad75002
AE		 712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
714 }
aa651be8
CD		 715
716 if (!fcport) {
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
719 }
720
fca29703
AV		 721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
fca29703
AV		 728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
730 }
7b594131 731 goto qc24_target_busy;
fca29703
AV		 732 }
733
b00ee7d7 734 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 735 if (!sp)
f5e3e40b 736 goto qc24_host_busy;
fca29703 737
9ba56b95
GM		 738 sp->u.scmd.cmd = cmd;
739 sp->type = SRB_SCSI_CMD;
740 atomic_set(&sp->ref_count, 1);
741 CMD_SP(cmd) = (void *)sp;
742 sp->free = qla2x00_sp_free_dma;
743 sp->done = qla2x00_sp_compl;
744
e315cd28 745 rval = ha->isp_ops->start_scsi(sp);
7c3df132 746 if (rval != QLA_SUCCESS) {
53016ed3 747 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 748 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 749 goto qc24_host_busy_free_sp;
7c3df132 750 }
fca29703 751
fca29703
AV		 752 return 0;
753
754qc24_host_busy_free_sp:
9ba56b95 755 qla2x00_sp_free_dma(ha, sp);
fca29703 756
f5e3e40b 757qc24_host_busy:
fca29703
AV		 758 return SCSI_MLQUEUE_HOST_BUSY;
759
7b594131
MC		 760qc24_target_busy:
761 return SCSI_MLQUEUE_TARGET_BUSY;
762
fca29703 763qc24_fail_command:
f5e3e40b 764 cmd->scsi_done(cmd);
fca29703
AV		 765
766 return 0;
767}
768
1da177e4
LT		 769/*
770 * qla2x00_eh_wait_on_command
771 * Waits for the command to be returned by the Firmware for some
772 * max time.
773 *
774 * Input:
1da177e4 775 * cmd = Scsi Command to wait on.
1da177e4
LT		 776 *
777 * Return:
778 * Not Found : 0
779 * Found : 1
780 */
781static int
e315cd28 782qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 783{
fe74c71f 784#define ABORT_POLLING_PERIOD 1000
478c3b03 785#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 786 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 787 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
788 struct qla_hw_data *ha = vha->hw;
f4f051eb 789 int ret = QLA_SUCCESS;
1da177e4 790
85880801 791 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 792 ql_dbg(ql_dbg_taskm, vha, 0x8005,
793 "Return:eh_wait.\n");
85880801
AV		 794 return ret;
795 }
796
d970432c 797 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 798 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 799 }
800 if (CMD_SP(cmd))
801 ret = QLA_FUNCTION_FAILED;
1da177e4 802
f4f051eb 803 return ret;
1da177e4
LT		 804}
805
806/*
807 * qla2x00_wait_for_hba_online
fa2a1ce5 808 * Wait till the HBA is online after going through
1da177e4
LT		 809 * <= MAX_RETRIES_OF_ISP_ABORT or
810 * finally HBA is disabled ie marked offline
811 *
812 * Input:
813 * ha - pointer to host adapter structure
fa2a1ce5
AV		 814 *
815 * Note:
1da177e4
LT		 816 * Does context switching-Release SPIN_LOCK
817 * (if any) before calling this routine.
818 *
819 * Return:
820 * Success (Adapter is online) : 0
821 * Failed (Adapter is offline/disabled) : 1
822 */
854165f4 823int
e315cd28 824qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 825{
fca29703
AV		 826 int return_status;
827 unsigned long wait_online;
e315cd28
AC		 828 struct qla_hw_data *ha = vha->hw;
829 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 830
fa2a1ce5 831 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 832 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
833 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
834 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
835 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 836
837 msleep(1000);
838 }
e315cd28 839 if (base_vha->flags.online)
fa2a1ce5 840 return_status = QLA_SUCCESS;
1da177e4
LT		 841 else
842 return_status = QLA_FUNCTION_FAILED;
843
1da177e4
LT		 844 return (return_status);
845}
846
86fbee86 847/*
638a1a01
SC		 848 * qla2x00_wait_for_hba_ready
849 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 850 *
851 * Input:
852 * ha - pointer to host adapter structure
853 *
854 * Note:
855 * Does context switching-Release SPIN_LOCK
856 * (if any) before calling this routine.
857 *
86fbee86 858 */
638a1a01
SC		 859static void
860qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 861{
86fbee86 862 struct qla_hw_data *ha = vha->hw;
86fbee86 863
638a1a01
SC		 864 while ((!(vha->flags.online) || ha->dpc_active ||
865 ha->flags.mbox_busy))
86fbee86 866 msleep(1000);
86fbee86
LC		 867}
868
2533cf67
LC		 869int
870qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
871{
872 int return_status;
873 unsigned long wait_reset;
874 struct qla_hw_data *ha = vha->hw;
875 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
876
877 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
878 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
879 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
880 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
881 ha->dpc_active) && time_before(jiffies, wait_reset)) {
882
883 msleep(1000);
884
885 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
886 ha->flags.chip_reset_done)
887 break;
888 }
889 if (ha->flags.chip_reset_done)
890 return_status = QLA_SUCCESS;
891 else
892 return_status = QLA_FUNCTION_FAILED;
893
894 return return_status;
895}
896
083a469d
GM		 897static void
898sp_get(struct srb *sp)
899{
900 atomic_inc(&sp->ref_count);
901}
902
1da177e4
LT		 903/**************************************************************************
904* qla2xxx_eh_abort
905*
906* Description:
907* The abort function will abort the specified command.
908*
909* Input:
910* cmd = Linux SCSI command packet to be aborted.
911*
912* Returns:
913* Either SUCCESS or FAILED.
914*
915* Note:
2ea00202 916* Only return FAILED if command not returned by firmware.
1da177e4 917**************************************************************************/
e5f82ab8 918static int
1da177e4
LT		 919qla2xxx_eh_abort(struct scsi_cmnd *cmd)
920{
e315cd28 921 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 922 srb_t *sp;
4e98d3b8 923 int ret;
9cb78c16
HR		 924 unsigned int id;
925 uint64_t lun;
18e144d3 926 unsigned long flags;
f934c9d0 927 int rval, wait = 0;
e315cd28 928 struct qla_hw_data *ha = vha->hw;
1da177e4 929
f4f051eb 930 if (!CMD_SP(cmd))
2ea00202 931 return SUCCESS;
1da177e4 932
4e98d3b8
AV		 933 ret = fc_block_scsi_eh(cmd);
934 if (ret != 0)
935 return ret;
936 ret = SUCCESS;
937
f4f051eb
AV		 938 id = cmd->device->id;
939 lun = cmd->device->lun;
1da177e4 940
e315cd28 941 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 942 sp = (srb_t *) CMD_SP(cmd);
943 if (!sp) {
944 spin_unlock_irqrestore(&ha->hardware_lock, flags);
945 return SUCCESS;
946 }
1da177e4 947
7c3df132 948 ql_dbg(ql_dbg_taskm, vha, 0x8002,
9cb78c16 949 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
cfb0919c 950 vha->host_no, id, lun, sp, cmd);
17d98630 951
170babc3
MC		 952 /* Get a reference to the sp and drop the lock.*/
953 sp_get(sp);
083a469d 954
e315cd28 955 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 956 rval = ha->isp_ops->abort_command(sp);
957 if (rval) {
958 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
959 /*
960 * Decrement the ref_count since we can't find the
961 * command
962 */
963 atomic_dec(&sp->ref_count);
964 ret = SUCCESS;
965 } else
966 ret = FAILED;
967
7c3df132 968 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 969 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 970 } else {
7c3df132 971 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 972 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 973 wait = 1;
974 }
75942064
SK		 975
976 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 977 /*
978 * Clear the slot in the oustanding_cmds array if we can't find the
979 * command to reclaim the resources.
980 */
981 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
982 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 983 sp->done(ha, sp, 0);
75942064 984 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 985
bc91ade9
CD		 986 /* Did the command return during mailbox execution? */
987 if (ret == FAILED && !CMD_SP(cmd))
988 ret = SUCCESS;
989
f4f051eb 990 /* Wait for the command to be returned. */
2ea00202 991 if (wait) {
e315cd28 992 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 993 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 994 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 995 ret = FAILED;
f4f051eb 996 }
1da177e4 997 }
1da177e4 998
7c3df132 999 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1000 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1001 vha->host_no, id, lun, wait, ret);
1da177e4 1002
f4f051eb
AV		 1003 return ret;
1004}
1da177e4 1005
4d78c973 1006int
e315cd28 1007qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1008 uint64_t l, enum nexus_wait_type type)
f4f051eb 1009{
17d98630 1010 int cnt, match, status;
18e144d3 1011 unsigned long flags;
e315cd28 1012 struct qla_hw_data *ha = vha->hw;
73208dfd 1013 struct req_que *req;
4d78c973 1014 srb_t *sp;
9ba56b95 1015 struct scsi_cmnd *cmd;
1da177e4 1016
523ec773 1017 status = QLA_SUCCESS;
17d98630 1018
e315cd28 1019 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1020 req = vha->req;
17d98630 1021 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1022 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1023 sp = req->outstanding_cmds[cnt];
1024 if (!sp)
523ec773 1025 continue;
9ba56b95 1026 if (sp->type != SRB_SCSI_CMD)
cf53b069 1027 continue;
17d98630
AC		 1028 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1029 continue;
1030 match = 0;
9ba56b95 1031 cmd = GET_CMD_SP(sp);
17d98630
AC		 1032 switch (type) {
1033 case WAIT_HOST:
1034 match = 1;
1035 break;
1036 case WAIT_TARGET:
9ba56b95 1037 match = cmd->device->id == t;
17d98630
AC		 1038 break;
1039 case WAIT_LUN:
9ba56b95
GM		 1040 match = (cmd->device->id == t &&
1041 cmd->device->lun == l);
17d98630 1042 break;
73208dfd 1043 }
17d98630
AC		 1044 if (!match)
1045 continue;
1046
1047 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1048 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1049 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1050 }
e315cd28 1051 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1052
1053 return status;
1da177e4
LT		 1054}
1055
523ec773
AV		 1056static char *reset_errors[] = {
1057 "HBA not online",
1058 "HBA not ready",
1059 "Task management failed",
1060 "Waiting for command completions",
1061};
1da177e4 1062
e5f82ab8 1063static int
523ec773 1064__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1065 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1066{
e315cd28 1067 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1068 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1069 int err;
1da177e4 1070
7c3df132 1071 if (!fcport) {
523ec773 1072 return FAILED;
7c3df132 1073 }
1da177e4 1074
4e98d3b8
AV		 1075 err = fc_block_scsi_eh(cmd);
1076 if (err != 0)
1077 return err;
1078
7c3df132 1079 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1080 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1081 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1082
523ec773 1083 err = 0;
7c3df132
SK		 1084 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1085 ql_log(ql_log_warn, vha, 0x800a,
1086 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1087 goto eh_reset_failed;
7c3df132 1088 }
523ec773 1089 err = 2;
2afa19a9 1090 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1091 != QLA_SUCCESS) {
1092 ql_log(ql_log_warn, vha, 0x800c,
1093 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1094 goto eh_reset_failed;
7c3df132 1095 }
523ec773 1096 err = 3;
e315cd28 1097 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1098 cmd->device->lun, type) != QLA_SUCCESS) {
1099 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1100 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1101 goto eh_reset_failed;
7c3df132 1102 }
523ec773 1103
7c3df132 1104 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1105 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1106 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1107
1108 return SUCCESS;
1109
4d78c973 1110eh_reset_failed:
7c3df132 1111 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1112 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1113 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1114 cmd);
523ec773
AV		 1115 return FAILED;
1116}
1da177e4 1117
523ec773
AV		 1118static int
1119qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1120{
e315cd28
AC		 1121 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1122 struct qla_hw_data *ha = vha->hw;
1da177e4 1123
523ec773
AV		 1124 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1125 ha->isp_ops->lun_reset);
1da177e4
LT		 1126}
1127
1da177e4 1128static int
523ec773 1129qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1130{
e315cd28
AC		 1131 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1132 struct qla_hw_data *ha = vha->hw;
1da177e4 1133
523ec773
AV		 1134 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1135 ha->isp_ops->target_reset);
1da177e4
LT		 1136}
1137
1da177e4
LT		 1138/**************************************************************************
1139* qla2xxx_eh_bus_reset
1140*
1141* Description:
1142* The bus reset function will reset the bus and abort any executing
1143* commands.
1144*
1145* Input:
1146* cmd = Linux SCSI command packet of the command that cause the
1147* bus reset.
1148*
1149* Returns:
1150* SUCCESS/FAILURE (defined as macro in scsi.h).
1151*
1152**************************************************************************/
e5f82ab8 1153static int
1da177e4
LT		 1154qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1155{
e315cd28 1156 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1157 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1158 int ret = FAILED;
9cb78c16
HR		 1159 unsigned int id;
1160 uint64_t lun;
f4f051eb 1161
f4f051eb
AV		 1162 id = cmd->device->id;
1163 lun = cmd->device->lun;
1da177e4 1164
7c3df132 1165 if (!fcport) {
f4f051eb 1166 return ret;
7c3df132 1167 }
1da177e4 1168
4e98d3b8
AV		 1169 ret = fc_block_scsi_eh(cmd);
1170 if (ret != 0)
1171 return ret;
1172 ret = FAILED;
1173
7c3df132 1174 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1175 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1176
e315cd28 1177 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1178 ql_log(ql_log_fatal, vha, 0x8013,
1179 "Wait for hba online failed board disabled.\n");
f4f051eb 1180 goto eh_bus_reset_done;
1da177e4
LT		 1181 }
1182
ad537689
SK		 1183 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1184 ret = SUCCESS;
1185
f4f051eb
AV		 1186 if (ret == FAILED)
1187 goto eh_bus_reset_done;
1da177e4 1188
9a41a62b 1189 /* Flush outstanding commands. */
4d78c973 1190 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1191 QLA_SUCCESS) {
1192 ql_log(ql_log_warn, vha, 0x8014,
1193 "Wait for pending commands failed.\n");
9a41a62b 1194 ret = FAILED;
7c3df132 1195 }
1da177e4 1196
f4f051eb 1197eh_bus_reset_done:
7c3df132 1198 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1199 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1200 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1201
f4f051eb 1202 return ret;
1da177e4
LT		 1203}
1204
1205/**************************************************************************
1206* qla2xxx_eh_host_reset
1207*
1208* Description:
1209* The reset function will reset the Adapter.
1210*
1211* Input:
1212* cmd = Linux SCSI command packet of the command that cause the
1213* adapter reset.
1214*
1215* Returns:
1216* Either SUCCESS or FAILED.
1217*
1218* Note:
1219**************************************************************************/
e5f82ab8 1220static int
1da177e4
LT		 1221qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1222{
e315cd28 1223 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1224 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1225 int ret = FAILED;
9cb78c16
HR		 1226 unsigned int id;
1227 uint64_t lun;
e315cd28 1228 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1229
f4f051eb
AV		 1230 id = cmd->device->id;
1231 lun = cmd->device->lun;
f4f051eb 1232
7c3df132 1233 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1234 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1235
63ee7072
CD		 1236 /*
1237 * No point in issuing another reset if one is active. Also do not
1238 * attempt a reset if we are updating flash.
1239 */
1240 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1241 goto eh_host_reset_lock;
1da177e4 1242
e315cd28
AC		 1243 if (vha != base_vha) {
1244 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1245 goto eh_host_reset_lock;
e315cd28 1246 } else {
7ec0effd 1247 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1248 if (!qla82xx_fcoe_ctx_reset(vha)) {
1249 /* Ctx reset success */
1250 ret = SUCCESS;
1251 goto eh_host_reset_lock;
1252 }
1253 /* fall thru if ctx reset failed */
1254 }
68ca949c
AC		 1255 if (ha->wq)
1256 flush_workqueue(ha->wq);
1257
e315cd28 1258 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1259 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1260 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1261 /* failed. schedule dpc to try */
1262 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1263
7c3df132
SK		 1264 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1265 ql_log(ql_log_warn, vha, 0x802a,
1266 "wait for hba online failed.\n");
e315cd28 1267 goto eh_host_reset_lock;
7c3df132 1268 }
e315cd28
AC		 1269 }
1270 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1271 }
1da177e4 1272
e315cd28 1273 /* Waiting for command to be returned to OS.*/
4d78c973 1274 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1275 QLA_SUCCESS)
f4f051eb 1276 ret = SUCCESS;
1da177e4 1277
f4f051eb 1278eh_host_reset_lock:
cfb0919c 1279 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1280 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1281 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1282
f4f051eb
AV		 1283 return ret;
1284}
1da177e4
LT		 1285
1286/*
1287* qla2x00_loop_reset
1288* Issue loop reset.
1289*
1290* Input:
1291* ha = adapter block pointer.
1292*
1293* Returns:
1294* 0 = success
1295*/
a4722cf2 1296int
e315cd28 1297qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1298{
0c8c39af 1299 int ret;
bdf79621 1300 struct fc_port *fcport;
e315cd28 1301 struct qla_hw_data *ha = vha->hw;
1da177e4 1302
5854771e
AB		 1303 if (IS_QLAFX00(ha)) {
1304 return qlafx00_loop_reset(vha);
1305 }
1306
f4c496c1 1307 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1308 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1309 if (fcport->port_type != FCT_TARGET)
1310 continue;
1311
1312 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1313 if (ret != QLA_SUCCESS) {
7c3df132 1314 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1315 "Bus Reset failed: Reset=%d "
7c3df132 1316 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1317 }
1318 }
1319 }
1320
8ae6d9c7 1321
6246b8a1 1322 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1323 atomic_set(&vha->loop_state, LOOP_DOWN);
1324 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1325 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1326 ret = qla2x00_full_login_lip(vha);
0c8c39af 1327 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1328 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1329 "full_login_lip=%d.\n", ret);
749af3d5 1330 }
0c8c39af
AV		 1331 }
1332
0d6e61bc 1333 if (ha->flags.enable_lip_reset) {
e315cd28 1334 ret = qla2x00_lip_reset(vha);
ad537689 1335 if (ret != QLA_SUCCESS)
7c3df132
SK		 1336 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1337 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1338 }
1339
1da177e4 1340 /* Issue marker command only when we are going to start the I/O */
e315cd28 1341 vha->marker_needed = 1;
1da177e4 1342
0c8c39af 1343 return QLA_SUCCESS;
1da177e4
LT		 1344}
1345
df4bf0bb 1346void
e315cd28 1347qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1348{
73208dfd 1349 int que, cnt;
df4bf0bb
AV		 1350 unsigned long flags;
1351 srb_t *sp;
e315cd28 1352 struct qla_hw_data *ha = vha->hw;
73208dfd 1353 struct req_que *req;
df4bf0bb
AV		 1354
1355 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1356 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1357 req = ha->req_q_map[que];
73208dfd
AC		 1358 if (!req)
1359 continue;
8d93f550
CD		 1360 if (!req->outstanding_cmds)
1361 continue;
1362 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1363 sp = req->outstanding_cmds[cnt];
e612d465 1364 if (sp) {
73208dfd 1365 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1366 sp->done(vha, sp, res);
73208dfd 1367 }
df4bf0bb
AV		 1368 }
1369 }
1370 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1371}
1372
f4f051eb
AV		 1373static int
1374qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1375{
bdf79621 1376 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1377
19a7b4ae 1378 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1379 return -ENXIO;
bdf79621 1380
19a7b4ae 1381 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1382
f4f051eb
AV		 1383 return 0;
1384}
1da177e4 1385
f4f051eb
AV		 1386static int
1387qla2xxx_slave_configure(struct scsi_device *sdev)
1388{
e315cd28 1389 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1390 struct req_que *req = vha->req;
8482e118 1391
9e522cd8
AE		 1392 if (IS_T10_PI_CAPABLE(vha->hw))
1393 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1394
f4f051eb 1395 if (sdev->tagged_supported)
73208dfd 1396 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1397 else
73208dfd 1398 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1399 return 0;
1400}
1da177e4 1401
f4f051eb
AV		 1402static void
1403qla2xxx_slave_destroy(struct scsi_device *sdev)
1404{
1405 sdev->hostdata = NULL;
1da177e4
LT		 1406}
1407
c45dd305
GM		 1408static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1409{
1410 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1411
1412 if (!scsi_track_queue_full(sdev, qdepth))
1413 return;
1414
7c3df132 1415 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
9cb78c16 1416 "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1417 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1418}
1419
1420static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1421{
1422 fc_port_t *fcport = sdev->hostdata;
1423 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1424 struct req_que *req = NULL;
1425
1426 req = vha->req;
1427 if (!req)
1428 return;
1429
1430 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1431 return;
1432
1433 if (sdev->ordered_tags)
1434 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1435 else
1436 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1437
7c3df132 1438 ql_dbg(ql_dbg_io, vha, 0x302a,
9cb78c16 1439 "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1440 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1441}
1442
ce7e4af7 1443static int
e881a172 1444qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1445{
c45dd305
GM		 1446 switch (reason) {
1447 case SCSI_QDEPTH_DEFAULT:
1448 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1449 break;
1450 case SCSI_QDEPTH_QFULL:
1451 qla2x00_handle_queue_full(sdev, qdepth);
1452 break;
1453 case SCSI_QDEPTH_RAMP_UP:
1454 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1455 break;
1456 default:
08002af2 1457 return -EOPNOTSUPP;
c45dd305 1458 }
e881a172 1459
ce7e4af7
AV		 1460 return sdev->queue_depth;
1461}
1462
1463static int
1464qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1465{
1466 if (sdev->tagged_supported) {
1467 scsi_set_tag_type(sdev, tag_type);
1468 if (tag_type)
1469 scsi_activate_tcq(sdev, sdev->queue_depth);
1470 else
1471 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1472 } else
1473 tag_type = 0;
1474
1475 return tag_type;
1476}
1477
1da177e4
LT		 1478/**
1479 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1480 * @ha: HA context
1481 *
1482 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1483 * supported addressing method.
1484 */
1485static void
53303c42 1486qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1487{
7524f9b9 1488 /* Assume a 32bit DMA mask. */
1da177e4 1489 ha->flags.enable_64bit_addressing = 0;
1da177e4 1490
6a35528a 1491 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1492 /* Any upper-dword bits set? */
1493 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1494 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1495 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1496 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1497 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1498 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1499 return;
1da177e4 1500 }
1da177e4 1501 }
7524f9b9 1502
284901a9
YH		 1503 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1504 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1505}
1506
fd34f556 1507static void
e315cd28 1508qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1509{
1510 unsigned long flags = 0;
1511 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1512
1513 spin_lock_irqsave(&ha->hardware_lock, flags);
1514 ha->interrupts_on = 1;
1515 /* enable risc and host interrupts */
1516 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1517 RD_REG_WORD(&reg->ictrl);
1518 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1519
1520}
1521
1522static void
e315cd28 1523qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1524{
1525 unsigned long flags = 0;
1526 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1527
1528 spin_lock_irqsave(&ha->hardware_lock, flags);
1529 ha->interrupts_on = 0;
1530 /* disable risc and host interrupts */
1531 WRT_REG_WORD(&reg->ictrl, 0);
1532 RD_REG_WORD(&reg->ictrl);
1533 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1534}
1535
1536static void
e315cd28 1537qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1538{
1539 unsigned long flags = 0;
1540 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1541
1542 spin_lock_irqsave(&ha->hardware_lock, flags);
1543 ha->interrupts_on = 1;
1544 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1545 RD_REG_DWORD(&reg->ictrl);
1546 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1547}
1548
1549static void
e315cd28 1550qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1551{
1552 unsigned long flags = 0;
1553 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1554
124f85e6
AV		 1555 if (IS_NOPOLLING_TYPE(ha))
1556 return;
fd34f556
AV		 1557 spin_lock_irqsave(&ha->hardware_lock, flags);
1558 ha->interrupts_on = 0;
1559 WRT_REG_DWORD(&reg->ictrl, 0);
1560 RD_REG_DWORD(&reg->ictrl);
1561 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1562}
1563
706f457d
GM		 1564static int
1565qla2x00_iospace_config(struct qla_hw_data *ha)
1566{
1567 resource_size_t pio;
1568 uint16_t msix;
1569 int cpus;
1570
706f457d
GM		 1571 if (pci_request_selected_regions(ha->pdev, ha->bars,
1572 QLA2XXX_DRIVER_NAME)) {
1573 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1574 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1575 pci_name(ha->pdev));
1576 goto iospace_error_exit;
1577 }
1578 if (!(ha->bars & 1))
1579 goto skip_pio;
1580
1581 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1582 pio = pci_resource_start(ha->pdev, 0);
1583 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1584 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1585 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1586 "Invalid pci I/O region size (%s).\n",
1587 pci_name(ha->pdev));
1588 pio = 0;
1589 }
1590 } else {
1591 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1592 "Region #0 no a PIO resource (%s).\n",
1593 pci_name(ha->pdev));
1594 pio = 0;
1595 }
1596 ha->pio_address = pio;
1597 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1598 "PIO address=%llu.\n",
1599 (unsigned long long)ha->pio_address);
1600
1601skip_pio:
1602 /* Use MMIO operations for all accesses. */
1603 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1604 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1605 "Region #1 not an MMIO resource (%s), aborting.\n",
1606 pci_name(ha->pdev));
1607 goto iospace_error_exit;
1608 }
1609 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1610 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1611 "Invalid PCI mem region size (%s), aborting.\n",
1612 pci_name(ha->pdev));
1613 goto iospace_error_exit;
1614 }
1615
1616 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1617 if (!ha->iobase) {
1618 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1619 "Cannot remap MMIO (%s), aborting.\n",
1620 pci_name(ha->pdev));
1621 goto iospace_error_exit;
1622 }
1623
1624 /* Determine queue resources */
1625 ha->max_req_queues = ha->max_rsp_queues = 1;
1626 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1627 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1628 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1629 goto mqiobase_exit;
1630
1631 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1632 pci_resource_len(ha->pdev, 3));
1633 if (ha->mqiobase) {
1634 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1635 "MQIO Base=%p.\n", ha->mqiobase);
1636 /* Read MSIX vector size of the board */
1637 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1638 ha->msix_count = msix;
1639 /* Max queues are bounded by available msix vectors */
1640 /* queue 0 uses two msix vectors */
1641 if (ql2xmultique_tag) {
1642 cpus = num_online_cpus();
1643 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1644 (cpus + 1) : (ha->msix_count - 1);
1645 ha->max_req_queues = 2;
1646 } else if (ql2xmaxqueues > 1) {
1647 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1648 QLA_MQ_SIZE : ql2xmaxqueues;
1649 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1650 "QoS mode set, max no of request queues:%d.\n",
1651 ha->max_req_queues);
1652 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1653 "QoS mode set, max no of request queues:%d.\n",
1654 ha->max_req_queues);
1655 }
1656 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1657 "MSI-X vector count: %d.\n", msix);
1658 } else
1659 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1660 "BAR 3 not enabled.\n");
1661
1662mqiobase_exit:
1663 ha->msix_count = ha->max_rsp_queues + 1;
1664 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1665 "MSIX Count:%d.\n", ha->msix_count);
1666 return (0);
1667
1668iospace_error_exit:
1669 return (-ENOMEM);
1670}
1671
1672
6246b8a1
GM		 1673static int
1674qla83xx_iospace_config(struct qla_hw_data *ha)
1675{
1676 uint16_t msix;
1677 int cpus;
1678
1679 if (pci_request_selected_regions(ha->pdev, ha->bars,
1680 QLA2XXX_DRIVER_NAME)) {
1681 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1682 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1683 pci_name(ha->pdev));
1684
1685 goto iospace_error_exit;
1686 }
1687
1688 /* Use MMIO operations for all accesses. */
1689 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1690 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1691 "Invalid pci I/O region size (%s).\n",
1692 pci_name(ha->pdev));
1693 goto iospace_error_exit;
1694 }
1695 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1696 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1697 "Invalid PCI mem region size (%s), aborting\n",
1698 pci_name(ha->pdev));
1699 goto iospace_error_exit;
1700 }
1701
1702 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1703 if (!ha->iobase) {
1704 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1705 "Cannot remap MMIO (%s), aborting.\n",
1706 pci_name(ha->pdev));
1707 goto iospace_error_exit;
1708 }
1709
1710 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1711 /* 83XX 26XX always use MQ type access for queues
1712 * - mbar 2, a.k.a region 4 */
1713 ha->max_req_queues = ha->max_rsp_queues = 1;
1714 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1715 pci_resource_len(ha->pdev, 4));
1716
1717 if (!ha->mqiobase) {
1718 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1719 "BAR2/region4 not enabled\n");
1720 goto mqiobase_exit;
1721 }
1722
1723 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1724 pci_resource_len(ha->pdev, 2));
1725 if (ha->msixbase) {
1726 /* Read MSIX vector size of the board */
1727 pci_read_config_word(ha->pdev,
1728 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1729 ha->msix_count = msix;
1730 /* Max queues are bounded by available msix vectors */
1731 /* queue 0 uses two msix vectors */
1732 if (ql2xmultique_tag) {
1733 cpus = num_online_cpus();
1734 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1735 (cpus + 1) : (ha->msix_count - 1);
1736 ha->max_req_queues = 2;
1737 } else if (ql2xmaxqueues > 1) {
1738 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1739 QLA_MQ_SIZE : ql2xmaxqueues;
1740 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1741 "QoS mode set, max no of request queues:%d.\n",
1742 ha->max_req_queues);
1743 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1744 "QoS mode set, max no of request queues:%d.\n",
1745 ha->max_req_queues);
1746 }
1747 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1748 "MSI-X vector count: %d.\n", msix);
1749 } else
1750 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1751 "BAR 1 not enabled.\n");
1752
1753mqiobase_exit:
1754 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1755
1756 qlt_83xx_iospace_config(ha);
1757
6246b8a1
GM		 1758 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1759 "MSIX Count:%d.\n", ha->msix_count);
1760 return 0;
1761
1762iospace_error_exit:
1763 return -ENOMEM;
1764}
1765
fd34f556
AV		 1766static struct isp_operations qla2100_isp_ops = {
1767 .pci_config = qla2100_pci_config,
1768 .reset_chip = qla2x00_reset_chip,
1769 .chip_diag = qla2x00_chip_diag,
1770 .config_rings = qla2x00_config_rings,
1771 .reset_adapter = qla2x00_reset_adapter,
1772 .nvram_config = qla2x00_nvram_config,
1773 .update_fw_options = qla2x00_update_fw_options,
1774 .load_risc = qla2x00_load_risc,
1775 .pci_info_str = qla2x00_pci_info_str,
1776 .fw_version_str = qla2x00_fw_version_str,
1777 .intr_handler = qla2100_intr_handler,
1778 .enable_intrs = qla2x00_enable_intrs,
1779 .disable_intrs = qla2x00_disable_intrs,
1780 .abort_command = qla2x00_abort_command,
523ec773
AV		 1781 .target_reset = qla2x00_abort_target,
1782 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1783 .fabric_login = qla2x00_login_fabric,
1784 .fabric_logout = qla2x00_fabric_logout,
1785 .calc_req_entries = qla2x00_calc_iocbs_32,
1786 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1787 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1788 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1789 .read_nvram = qla2x00_read_nvram_data,
1790 .write_nvram = qla2x00_write_nvram_data,
1791 .fw_dump = qla2100_fw_dump,
1792 .beacon_on = NULL,
1793 .beacon_off = NULL,
1794 .beacon_blink = NULL,
1795 .read_optrom = qla2x00_read_optrom_data,
1796 .write_optrom = qla2x00_write_optrom_data,
1797 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1798 .start_scsi = qla2x00_start_scsi,
a9083016 1799 .abort_isp = qla2x00_abort_isp,
706f457d 1800 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1801 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1802};
1803
1804static struct isp_operations qla2300_isp_ops = {
1805 .pci_config = qla2300_pci_config,
1806 .reset_chip = qla2x00_reset_chip,
1807 .chip_diag = qla2x00_chip_diag,
1808 .config_rings = qla2x00_config_rings,
1809 .reset_adapter = qla2x00_reset_adapter,
1810 .nvram_config = qla2x00_nvram_config,
1811 .update_fw_options = qla2x00_update_fw_options,
1812 .load_risc = qla2x00_load_risc,
1813 .pci_info_str = qla2x00_pci_info_str,
1814 .fw_version_str = qla2x00_fw_version_str,
1815 .intr_handler = qla2300_intr_handler,
1816 .enable_intrs = qla2x00_enable_intrs,
1817 .disable_intrs = qla2x00_disable_intrs,
1818 .abort_command = qla2x00_abort_command,
523ec773
AV		 1819 .target_reset = qla2x00_abort_target,
1820 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1821 .fabric_login = qla2x00_login_fabric,
1822 .fabric_logout = qla2x00_fabric_logout,
1823 .calc_req_entries = qla2x00_calc_iocbs_32,
1824 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1825 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1826 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1827 .read_nvram = qla2x00_read_nvram_data,
1828 .write_nvram = qla2x00_write_nvram_data,
1829 .fw_dump = qla2300_fw_dump,
1830 .beacon_on = qla2x00_beacon_on,
1831 .beacon_off = qla2x00_beacon_off,
1832 .beacon_blink = qla2x00_beacon_blink,
1833 .read_optrom = qla2x00_read_optrom_data,
1834 .write_optrom = qla2x00_write_optrom_data,
1835 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1836 .start_scsi = qla2x00_start_scsi,
a9083016 1837 .abort_isp = qla2x00_abort_isp,
7ec0effd 1838 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1839 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1840};
1841
1842static struct isp_operations qla24xx_isp_ops = {
1843 .pci_config = qla24xx_pci_config,
1844 .reset_chip = qla24xx_reset_chip,
1845 .chip_diag = qla24xx_chip_diag,
1846 .config_rings = qla24xx_config_rings,
1847 .reset_adapter = qla24xx_reset_adapter,
1848 .nvram_config = qla24xx_nvram_config,
1849 .update_fw_options = qla24xx_update_fw_options,
1850 .load_risc = qla24xx_load_risc,
1851 .pci_info_str = qla24xx_pci_info_str,
1852 .fw_version_str = qla24xx_fw_version_str,
1853 .intr_handler = qla24xx_intr_handler,
1854 .enable_intrs = qla24xx_enable_intrs,
1855 .disable_intrs = qla24xx_disable_intrs,
1856 .abort_command = qla24xx_abort_command,
523ec773
AV		 1857 .target_reset = qla24xx_abort_target,
1858 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1859 .fabric_login = qla24xx_login_fabric,
1860 .fabric_logout = qla24xx_fabric_logout,
1861 .calc_req_entries = NULL,
1862 .build_iocbs = NULL,
1863 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1864 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1865 .read_nvram = qla24xx_read_nvram_data,
1866 .write_nvram = qla24xx_write_nvram_data,
1867 .fw_dump = qla24xx_fw_dump,
1868 .beacon_on = qla24xx_beacon_on,
1869 .beacon_off = qla24xx_beacon_off,
1870 .beacon_blink = qla24xx_beacon_blink,
1871 .read_optrom = qla24xx_read_optrom_data,
1872 .write_optrom = qla24xx_write_optrom_data,
1873 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1874 .start_scsi = qla24xx_start_scsi,
a9083016 1875 .abort_isp = qla2x00_abort_isp,
7ec0effd 1876 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1877 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1878};
1879
c3a2f0df
AV		 1880static struct isp_operations qla25xx_isp_ops = {
1881 .pci_config = qla25xx_pci_config,
1882 .reset_chip = qla24xx_reset_chip,
1883 .chip_diag = qla24xx_chip_diag,
1884 .config_rings = qla24xx_config_rings,
1885 .reset_adapter = qla24xx_reset_adapter,
1886 .nvram_config = qla24xx_nvram_config,
1887 .update_fw_options = qla24xx_update_fw_options,
1888 .load_risc = qla24xx_load_risc,
1889 .pci_info_str = qla24xx_pci_info_str,
1890 .fw_version_str = qla24xx_fw_version_str,
1891 .intr_handler = qla24xx_intr_handler,
1892 .enable_intrs = qla24xx_enable_intrs,
1893 .disable_intrs = qla24xx_disable_intrs,
1894 .abort_command = qla24xx_abort_command,
523ec773
AV		 1895 .target_reset = qla24xx_abort_target,
1896 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1897 .fabric_login = qla24xx_login_fabric,
1898 .fabric_logout = qla24xx_fabric_logout,
1899 .calc_req_entries = NULL,
1900 .build_iocbs = NULL,
1901 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1902 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1903 .read_nvram = qla25xx_read_nvram_data,
1904 .write_nvram = qla25xx_write_nvram_data,
1905 .fw_dump = qla25xx_fw_dump,
1906 .beacon_on = qla24xx_beacon_on,
1907 .beacon_off = qla24xx_beacon_off,
1908 .beacon_blink = qla24xx_beacon_blink,
338c9161 1909 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1910 .write_optrom = qla24xx_write_optrom_data,
1911 .get_flash_version = qla24xx_get_flash_version,
bad75002 1912 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1913 .abort_isp = qla2x00_abort_isp,
7ec0effd 1914 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1915 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1916};
1917
3a03eb79
AV		 1918static struct isp_operations qla81xx_isp_ops = {
1919 .pci_config = qla25xx_pci_config,
1920 .reset_chip = qla24xx_reset_chip,
1921 .chip_diag = qla24xx_chip_diag,
1922 .config_rings = qla24xx_config_rings,
1923 .reset_adapter = qla24xx_reset_adapter,
1924 .nvram_config = qla81xx_nvram_config,
1925 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1926 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1927 .pci_info_str = qla24xx_pci_info_str,
1928 .fw_version_str = qla24xx_fw_version_str,
1929 .intr_handler = qla24xx_intr_handler,
1930 .enable_intrs = qla24xx_enable_intrs,
1931 .disable_intrs = qla24xx_disable_intrs,
1932 .abort_command = qla24xx_abort_command,
1933 .target_reset = qla24xx_abort_target,
1934 .lun_reset = qla24xx_lun_reset,
1935 .fabric_login = qla24xx_login_fabric,
1936 .fabric_logout = qla24xx_fabric_logout,
1937 .calc_req_entries = NULL,
1938 .build_iocbs = NULL,
1939 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1940 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1941 .read_nvram = NULL,
1942 .write_nvram = NULL,
3a03eb79
AV		 1943 .fw_dump = qla81xx_fw_dump,
1944 .beacon_on = qla24xx_beacon_on,
1945 .beacon_off = qla24xx_beacon_off,
6246b8a1 1946 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1947 .read_optrom = qla25xx_read_optrom_data,
1948 .write_optrom = qla24xx_write_optrom_data,
1949 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1950 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1951 .abort_isp = qla2x00_abort_isp,
7ec0effd 1952 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1953 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1954};
1955
1956static struct isp_operations qla82xx_isp_ops = {
1957 .pci_config = qla82xx_pci_config,
1958 .reset_chip = qla82xx_reset_chip,
1959 .chip_diag = qla24xx_chip_diag,
1960 .config_rings = qla82xx_config_rings,
1961 .reset_adapter = qla24xx_reset_adapter,
1962 .nvram_config = qla81xx_nvram_config,
1963 .update_fw_options = qla24xx_update_fw_options,
1964 .load_risc = qla82xx_load_risc,
9d55ca66 1965 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1966 .fw_version_str = qla24xx_fw_version_str,
1967 .intr_handler = qla82xx_intr_handler,
1968 .enable_intrs = qla82xx_enable_intrs,
1969 .disable_intrs = qla82xx_disable_intrs,
1970 .abort_command = qla24xx_abort_command,
1971 .target_reset = qla24xx_abort_target,
1972 .lun_reset = qla24xx_lun_reset,
1973 .fabric_login = qla24xx_login_fabric,
1974 .fabric_logout = qla24xx_fabric_logout,
1975 .calc_req_entries = NULL,
1976 .build_iocbs = NULL,
1977 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1978 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1979 .read_nvram = qla24xx_read_nvram_data,
1980 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1981 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1982 .beacon_on = qla82xx_beacon_on,
1983 .beacon_off = qla82xx_beacon_off,
1984 .beacon_blink = NULL,
a9083016
GM		 1985 .read_optrom = qla82xx_read_optrom_data,
1986 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1987 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1988 .start_scsi = qla82xx_start_scsi,
1989 .abort_isp = qla82xx_abort_isp,
706f457d 1990 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1991 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1992};
1993
7ec0effd
AD		 1994static struct isp_operations qla8044_isp_ops = {
1995 .pci_config = qla82xx_pci_config,
1996 .reset_chip = qla82xx_reset_chip,
1997 .chip_diag = qla24xx_chip_diag,
1998 .config_rings = qla82xx_config_rings,
1999 .reset_adapter = qla24xx_reset_adapter,
2000 .nvram_config = qla81xx_nvram_config,
2001 .update_fw_options = qla24xx_update_fw_options,
2002 .load_risc = qla82xx_load_risc,
2003 .pci_info_str = qla24xx_pci_info_str,
2004 .fw_version_str = qla24xx_fw_version_str,
2005 .intr_handler = qla8044_intr_handler,
2006 .enable_intrs = qla82xx_enable_intrs,
2007 .disable_intrs = qla82xx_disable_intrs,
2008 .abort_command = qla24xx_abort_command,
2009 .target_reset = qla24xx_abort_target,
2010 .lun_reset = qla24xx_lun_reset,
2011 .fabric_login = qla24xx_login_fabric,
2012 .fabric_logout = qla24xx_fabric_logout,
2013 .calc_req_entries = NULL,
2014 .build_iocbs = NULL,
2015 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2016 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2017 .read_nvram = NULL,
2018 .write_nvram = NULL,
a1b23c5a 2019 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2020 .beacon_on = qla82xx_beacon_on,
2021 .beacon_off = qla82xx_beacon_off,
2022 .beacon_blink = NULL,
888e639d 2023 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2024 .write_optrom = qla8044_write_optrom_data,
2025 .get_flash_version = qla82xx_get_flash_version,
2026 .start_scsi = qla82xx_start_scsi,
2027 .abort_isp = qla8044_abort_isp,
2028 .iospace_config = qla82xx_iospace_config,
2029 .initialize_adapter = qla2x00_initialize_adapter,
2030};
2031
6246b8a1
GM		 2032static struct isp_operations qla83xx_isp_ops = {
2033 .pci_config = qla25xx_pci_config,
2034 .reset_chip = qla24xx_reset_chip,
2035 .chip_diag = qla24xx_chip_diag,
2036 .config_rings = qla24xx_config_rings,
2037 .reset_adapter = qla24xx_reset_adapter,
2038 .nvram_config = qla81xx_nvram_config,
2039 .update_fw_options = qla81xx_update_fw_options,
2040 .load_risc = qla81xx_load_risc,
2041 .pci_info_str = qla24xx_pci_info_str,
2042 .fw_version_str = qla24xx_fw_version_str,
2043 .intr_handler = qla24xx_intr_handler,
2044 .enable_intrs = qla24xx_enable_intrs,
2045 .disable_intrs = qla24xx_disable_intrs,
2046 .abort_command = qla24xx_abort_command,
2047 .target_reset = qla24xx_abort_target,
2048 .lun_reset = qla24xx_lun_reset,
2049 .fabric_login = qla24xx_login_fabric,
2050 .fabric_logout = qla24xx_fabric_logout,
2051 .calc_req_entries = NULL,
2052 .build_iocbs = NULL,
2053 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2054 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2055 .read_nvram = NULL,
2056 .write_nvram = NULL,
2057 .fw_dump = qla83xx_fw_dump,
2058 .beacon_on = qla24xx_beacon_on,
2059 .beacon_off = qla24xx_beacon_off,
2060 .beacon_blink = qla83xx_beacon_blink,
2061 .read_optrom = qla25xx_read_optrom_data,
2062 .write_optrom = qla24xx_write_optrom_data,
2063 .get_flash_version = qla24xx_get_flash_version,
2064 .start_scsi = qla24xx_dif_start_scsi,
2065 .abort_isp = qla2x00_abort_isp,
2066 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2067 .initialize_adapter = qla2x00_initialize_adapter,
2068};
2069
2070static struct isp_operations qlafx00_isp_ops = {
2071 .pci_config = qlafx00_pci_config,
2072 .reset_chip = qlafx00_soft_reset,
2073 .chip_diag = qlafx00_chip_diag,
2074 .config_rings = qlafx00_config_rings,
2075 .reset_adapter = qlafx00_soft_reset,
2076 .nvram_config = NULL,
2077 .update_fw_options = NULL,
2078 .load_risc = NULL,
2079 .pci_info_str = qlafx00_pci_info_str,
2080 .fw_version_str = qlafx00_fw_version_str,
2081 .intr_handler = qlafx00_intr_handler,
2082 .enable_intrs = qlafx00_enable_intrs,
2083 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2084 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2085 .target_reset = qlafx00_abort_target,
2086 .lun_reset = qlafx00_lun_reset,
2087 .fabric_login = NULL,
2088 .fabric_logout = NULL,
2089 .calc_req_entries = NULL,
2090 .build_iocbs = NULL,
2091 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2092 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2093 .read_nvram = qla24xx_read_nvram_data,
2094 .write_nvram = qla24xx_write_nvram_data,
2095 .fw_dump = NULL,
2096 .beacon_on = qla24xx_beacon_on,
2097 .beacon_off = qla24xx_beacon_off,
2098 .beacon_blink = NULL,
2099 .read_optrom = qla24xx_read_optrom_data,
2100 .write_optrom = qla24xx_write_optrom_data,
2101 .get_flash_version = qla24xx_get_flash_version,
2102 .start_scsi = qlafx00_start_scsi,
2103 .abort_isp = qlafx00_abort_isp,
2104 .iospace_config = qlafx00_iospace_config,
2105 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2106};
2107
f73cb695
CD		 2108static struct isp_operations qla27xx_isp_ops = {
2109 .pci_config = qla25xx_pci_config,
2110 .reset_chip = qla24xx_reset_chip,
2111 .chip_diag = qla24xx_chip_diag,
2112 .config_rings = qla24xx_config_rings,
2113 .reset_adapter = qla24xx_reset_adapter,
2114 .nvram_config = qla81xx_nvram_config,
2115 .update_fw_options = qla81xx_update_fw_options,
2116 .load_risc = qla81xx_load_risc,
2117 .pci_info_str = qla24xx_pci_info_str,
2118 .fw_version_str = qla24xx_fw_version_str,
2119 .intr_handler = qla24xx_intr_handler,
2120 .enable_intrs = qla24xx_enable_intrs,
2121 .disable_intrs = qla24xx_disable_intrs,
2122 .abort_command = qla24xx_abort_command,
2123 .target_reset = qla24xx_abort_target,
2124 .lun_reset = qla24xx_lun_reset,
2125 .fabric_login = qla24xx_login_fabric,
2126 .fabric_logout = qla24xx_fabric_logout,
2127 .calc_req_entries = NULL,
2128 .build_iocbs = NULL,
2129 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2130 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2131 .read_nvram = NULL,
2132 .write_nvram = NULL,
2133 .fw_dump = qla27xx_fwdump,
2134 .beacon_on = qla24xx_beacon_on,
2135 .beacon_off = qla24xx_beacon_off,
2136 .beacon_blink = qla83xx_beacon_blink,
2137 .read_optrom = qla25xx_read_optrom_data,
2138 .write_optrom = qla24xx_write_optrom_data,
2139 .get_flash_version = qla24xx_get_flash_version,
2140 .start_scsi = qla24xx_dif_start_scsi,
2141 .abort_isp = qla2x00_abort_isp,
2142 .iospace_config = qla83xx_iospace_config,
2143 .initialize_adapter = qla2x00_initialize_adapter,
2144};
2145
ea5b6382 2146static inline void
e315cd28 2147qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2148{
2149 ha->device_type = DT_EXTENDED_IDS;
2150 switch (ha->pdev->device) {
2151 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2152 ha->device_type |= DT_ISP2100;
2153 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2154 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2155 break;
2156 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2157 ha->device_type |= DT_ISP2200;
2158 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2159 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2160 break;
2161 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2162 ha->device_type |= DT_ISP2300;
4a59f71d 2163 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2164 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2165 break;
2166 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2167 ha->device_type |= DT_ISP2312;
4a59f71d 2168 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2169 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2170 break;
2171 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2172 ha->device_type |= DT_ISP2322;
4a59f71d 2173 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2174 if (ha->pdev->subsystem_vendor == 0x1028 &&
2175 ha->pdev->subsystem_device == 0x0170)
2176 ha->device_type |= DT_OEM_001;
441d1072 2177 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2178 break;
2179 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2180 ha->device_type |= DT_ISP6312;
441d1072 2181 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2182 break;
2183 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2184 ha->device_type |= DT_ISP6322;
441d1072 2185 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2186 break;
2187 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2188 ha->device_type |= DT_ISP2422;
4a59f71d 2189 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2190 ha->device_type |= DT_FWI2;
c76f2c01 2191 ha->device_type |= DT_IIDMA;
441d1072 2192 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2193 break;
2194 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2195 ha->device_type |= DT_ISP2432;
4a59f71d 2196 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2197 ha->device_type |= DT_FWI2;
c76f2c01 2198 ha->device_type |= DT_IIDMA;
441d1072 2199 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2200 break;
4d4df193
HK		 2201 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2202 ha->device_type |= DT_ISP8432;
2203 ha->device_type |= DT_ZIO_SUPPORTED;
2204 ha->device_type |= DT_FWI2;
2205 ha->device_type |= DT_IIDMA;
2206 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2207 break;
044cc6c8
AV		 2208 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2209 ha->device_type |= DT_ISP5422;
e428924c 2210 ha->device_type |= DT_FWI2;
441d1072 2211 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2212 break;
044cc6c8
AV		 2213 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2214 ha->device_type |= DT_ISP5432;
e428924c 2215 ha->device_type |= DT_FWI2;
441d1072 2216 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2217 break;
c3a2f0df
AV		 2218 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2219 ha->device_type |= DT_ISP2532;
2220 ha->device_type |= DT_ZIO_SUPPORTED;
2221 ha->device_type |= DT_FWI2;
2222 ha->device_type |= DT_IIDMA;
441d1072 2223 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2224 break;
3a03eb79
AV		 2225 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2226 ha->device_type |= DT_ISP8001;
2227 ha->device_type |= DT_ZIO_SUPPORTED;
2228 ha->device_type |= DT_FWI2;
2229 ha->device_type |= DT_IIDMA;
2230 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2231 break;
a9083016
GM		 2232 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2233 ha->device_type |= DT_ISP8021;
2234 ha->device_type |= DT_ZIO_SUPPORTED;
2235 ha->device_type |= DT_FWI2;
2236 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2237 /* Initialize 82XX ISP flags */
2238 qla82xx_init_flags(ha);
2239 break;
7ec0effd
AD		 2240 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2241 ha->device_type |= DT_ISP8044;
2242 ha->device_type |= DT_ZIO_SUPPORTED;
2243 ha->device_type |= DT_FWI2;
2244 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2245 /* Initialize 82XX ISP flags */
2246 qla82xx_init_flags(ha);
2247 break;
6246b8a1
GM		 2248 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2249 ha->device_type |= DT_ISP2031;
2250 ha->device_type |= DT_ZIO_SUPPORTED;
2251 ha->device_type |= DT_FWI2;
2252 ha->device_type |= DT_IIDMA;
2253 ha->device_type |= DT_T10_PI;
2254 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2255 break;
2256 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2257 ha->device_type |= DT_ISP8031;
2258 ha->device_type |= DT_ZIO_SUPPORTED;
2259 ha->device_type |= DT_FWI2;
2260 ha->device_type |= DT_IIDMA;
2261 ha->device_type |= DT_T10_PI;
2262 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2263 break;
8ae6d9c7
GM		 2264 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2265 ha->device_type |= DT_ISPFX00;
2266 break;
f73cb695
CD		 2267 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2268 ha->device_type |= DT_ISP2071;
2269 ha->device_type |= DT_ZIO_SUPPORTED;
2270 ha->device_type |= DT_FWI2;
2271 ha->device_type |= DT_IIDMA;
2272 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2273 break;
2c5bbbb2
JC		 2274 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2275 ha->device_type |= DT_ISP2271;
2276 ha->device_type |= DT_ZIO_SUPPORTED;
2277 ha->device_type |= DT_FWI2;
2278 ha->device_type |= DT_IIDMA;
2279 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2280 break;
ea5b6382 2281 }
e5b68a61 2282
a9083016 2283 if (IS_QLA82XX(ha))
43a9c38b 2284 ha->port_no = ha->portnum & 1;
f73cb695 2285 else {
a9083016
GM		 2286 /* Get adapter physical port no from interrupt pin register. */
2287 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2288 if (IS_QLA27XX(ha))
2289 ha->port_no--;
2290 else
2291 ha->port_no = !(ha->port_no & 1);
2292 }
a9083016 2293
7c3df132 2294 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2295 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2296 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2297}
2298
1e99e33a
AV		 2299static void
2300qla2xxx_scan_start(struct Scsi_Host *shost)
2301{
e315cd28 2302 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2303
cbc8eb67
AV		 2304 if (vha->hw->flags.running_gold_fw)
2305 return;
2306
e315cd28
AC		 2307 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2308 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2309 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2310 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2311}
2312
2313static int
2314qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2315{
e315cd28 2316 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2317
e315cd28 2318 if (!vha->host)
1e99e33a 2319 return 1;
e315cd28 2320 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2321 return 1;
2322
e315cd28 2323 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2324}
2325
1da177e4
LT		 2326/*
2327 * PCI driver interface
2328 */
6f039790 2329static int
7ee61397 2330qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2331{
a1541d5a 2332 int ret = -ENODEV;
1da177e4 2333 struct Scsi_Host *host;
e315cd28
AC		 2334 scsi_qla_host_t *base_vha = NULL;
2335 struct qla_hw_data *ha;
29856e28 2336 char pci_info[30];
7d613ac6 2337 char fw_str[30], wq_name[30];
5433383e 2338 struct scsi_host_template *sht;
642ef983 2339 int bars, mem_only = 0;
e315cd28 2340 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2341 struct req_que *req = NULL;
2342 struct rsp_que *rsp = NULL;
285d0321 2343 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2344 sht = &qla2xxx_driver_template;
5433383e 2345 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2346 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2348 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2349 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2350 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2351 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2352 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2353 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2354 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2355 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2356 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2357 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2358 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2359 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2360 mem_only = 1;
7c3df132
SK		 2361 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2362 "Mem only adapter.\n");
285d0321 2363 }
7c3df132
SK		 2364 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2365 "Bars=%d.\n", bars);
285d0321 2366
09483916
BH		 2367 if (mem_only) {
2368 if (pci_enable_device_mem(pdev))
2369 goto probe_out;
2370 } else {
2371 if (pci_enable_device(pdev))
2372 goto probe_out;
2373 }
285d0321 2374
0927678f
JB		 2375 /* This may fail but that's ok */
2376 pci_enable_pcie_error_reporting(pdev);
285d0321 2377
e315cd28
AC		 2378 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2379 if (!ha) {
7c3df132
SK		 2380 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2381 "Unable to allocate memory for ha.\n");
e315cd28 2382 goto probe_out;
1da177e4 2383 }
7c3df132
SK		 2384 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2385 "Memory allocated for ha=%p.\n", ha);
e315cd28 2386 ha->pdev = pdev;
2d70c103 2387 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2388
2389 /* Clear our data area */
285d0321 2390 ha->bars = bars;
09483916 2391 ha->mem_only = mem_only;
df4bf0bb 2392 spin_lock_init(&ha->hardware_lock);
339aa70e 2393 spin_lock_init(&ha->vport_slock);
a9b6f722 2394 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2395 mutex_init(&ha->optrom_mutex);
1da177e4 2396
ea5b6382
AV		 2397 /* Set ISP-type information. */
2398 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2399
2400 /* Set EEH reset type to fundamental if required by hba */
95676112 2401 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2402 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2403 pdev->needs_freset = 1;
ca79cf66 2404
cba1e47f
CD		 2405 ha->prev_topology = 0;
2406 ha->init_cb_size = sizeof(init_cb_t);
2407 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2408 ha->optrom_size = OPTROM_SIZE_2300;
2409
abbd8870 2410 /* Assign ISP specific operations. */
1da177e4 2411 if (IS_QLA2100(ha)) {
642ef983 2412 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2413 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2414 req_length = REQUEST_ENTRY_CNT_2100;
2415 rsp_length = RESPONSE_ENTRY_CNT_2100;
2416 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2417 ha->gid_list_info_size = 4;
3a03eb79
AV		 2418 ha->flash_conf_off = ~0;
2419 ha->flash_data_off = ~0;
2420 ha->nvram_conf_off = ~0;
2421 ha->nvram_data_off = ~0;
fd34f556 2422 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2423 } else if (IS_QLA2200(ha)) {
642ef983 2424 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2425 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2426 req_length = REQUEST_ENTRY_CNT_2200;
2427 rsp_length = RESPONSE_ENTRY_CNT_2100;
2428 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2429 ha->gid_list_info_size = 4;
3a03eb79
AV		 2430 ha->flash_conf_off = ~0;
2431 ha->flash_data_off = ~0;
2432 ha->nvram_conf_off = ~0;
2433 ha->nvram_data_off = ~0;
fd34f556 2434 ha->isp_ops = &qla2100_isp_ops;
fca29703 2435 } else if (IS_QLA23XX(ha)) {
642ef983 2436 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2437 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2438 req_length = REQUEST_ENTRY_CNT_2200;
2439 rsp_length = RESPONSE_ENTRY_CNT_2300;
2440 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2441 ha->gid_list_info_size = 6;
854165f4
AV		 2442 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2443 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2444 ha->flash_conf_off = ~0;
2445 ha->flash_data_off = ~0;
2446 ha->nvram_conf_off = ~0;
2447 ha->nvram_data_off = ~0;
fd34f556 2448 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2449 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2450 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2451 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2452 req_length = REQUEST_ENTRY_CNT_24XX;
2453 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2454 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2455 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2456 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2457 ha->gid_list_info_size = 8;
854165f4 2458 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2459 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2460 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2461 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2462 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2463 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2464 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2465 } else if (IS_QLA25XX(ha)) {
642ef983 2466 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2467 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2468 req_length = REQUEST_ENTRY_CNT_24XX;
2469 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2470 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2471 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2472 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2473 ha->gid_list_info_size = 8;
2474 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2475 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2476 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2477 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2478 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2479 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2480 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2481 } else if (IS_QLA81XX(ha)) {
642ef983 2482 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2483 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2484 req_length = REQUEST_ENTRY_CNT_24XX;
2485 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2486 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2487 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2488 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2489 ha->gid_list_info_size = 8;
2490 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2491 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2492 ha->isp_ops = &qla81xx_isp_ops;
2493 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2494 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2495 ha->nvram_conf_off = ~0;
2496 ha->nvram_data_off = ~0;
a9083016 2497 } else if (IS_QLA82XX(ha)) {
642ef983 2498 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2499 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2500 req_length = REQUEST_ENTRY_CNT_82XX;
2501 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2502 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2503 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2504 ha->gid_list_info_size = 8;
2505 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2506 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2507 ha->isp_ops = &qla82xx_isp_ops;
2508 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2509 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2510 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2511 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2512 } else if (IS_QLA8044(ha)) {
2513 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2514 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2515 req_length = REQUEST_ENTRY_CNT_82XX;
2516 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2517 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2518 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2519 ha->gid_list_info_size = 8;
2520 ha->optrom_size = OPTROM_SIZE_83XX;
2521 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2522 ha->isp_ops = &qla8044_isp_ops;
2523 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2524 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2525 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2526 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2527 } else if (IS_QLA83XX(ha)) {
7d613ac6 2528 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2529 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2530 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2531 req_length = REQUEST_ENTRY_CNT_24XX;
2532 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2533 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2534 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2535 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2536 ha->gid_list_info_size = 8;
2537 ha->optrom_size = OPTROM_SIZE_83XX;
2538 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2539 ha->isp_ops = &qla83xx_isp_ops;
2540 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2541 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2542 ha->nvram_conf_off = ~0;
2543 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2544 } else if (IS_QLAFX00(ha)) {
2545 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2546 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2547 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2548 req_length = REQUEST_ENTRY_CNT_FX00;
2549 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2550 ha->isp_ops = &qlafx00_isp_ops;
2551 ha->port_down_retry_count = 30; /* default value */
2552 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2553 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2554 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2555 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2556 ha->mr.host_info_resend = false;
2557 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2558 } else if (IS_QLA27XX(ha)) {
2559 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2560 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2561 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2562 req_length = REQUEST_ENTRY_CNT_24XX;
2563 rsp_length = RESPONSE_ENTRY_CNT_2300;
2564 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2565 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2566 ha->gid_list_info_size = 8;
2567 ha->optrom_size = OPTROM_SIZE_83XX;
2568 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2569 ha->isp_ops = &qla27xx_isp_ops;
2570 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2571 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2572 ha->nvram_conf_off = ~0;
2573 ha->nvram_data_off = ~0;
1da177e4 2574 }
6246b8a1 2575
7c3df132
SK		 2576 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2577 "mbx_count=%d, req_length=%d, "
2578 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2579 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2580 "max_fibre_devices=%d.\n",
7c3df132
SK		 2581 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2582 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2583 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2584 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2585 "isp_ops=%p, flash_conf_off=%d, "
2586 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2587 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2588 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2589
2590 /* Configure PCI I/O space */
2591 ret = ha->isp_ops->iospace_config(ha);
2592 if (ret)
0a63ad12 2593 goto iospace_config_failed;
706f457d
GM		 2594
2595 ql_log_pci(ql_log_info, pdev, 0x001d,
2596 "Found an ISP%04X irq %d iobase 0x%p.\n",
2597 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2598 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2599 init_completion(&ha->mbx_cmd_comp);
2600 complete(&ha->mbx_cmd_comp);
2601 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2602 init_completion(&ha->dcbx_comp);
f356bef1 2603 init_completion(&ha->lb_portup_comp);
1da177e4 2604
2c3dfe3f 2605 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2606
53303c42 2607 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2608 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2609 "64 Bit addressing is %s.\n",
2610 ha->flags.enable_64bit_addressing ? "enable" :
2611 "disable");
73208dfd 2612 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2613 if (ret) {
7c3df132
SK		 2614 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2615 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2616
e315cd28
AC		 2617 goto probe_hw_failed;
2618 }
2619
73208dfd 2620 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2621 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2622 req->max_q_depth = ql2xmaxqdepth;
2623
e315cd28
AC		 2624
2625 base_vha = qla2x00_create_host(sht, ha);
2626 if (!base_vha) {
a1541d5a 2627 ret = -ENOMEM;
6e9f21f3 2628 qla2x00_mem_free(ha);
2afa19a9
AC		 2629 qla2x00_free_req_que(ha, req);
2630 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2631 goto probe_hw_failed;
1da177e4
LT		 2632 }
2633
e315cd28
AC		 2634 pci_set_drvdata(pdev, base_vha);
2635
e315cd28 2636 host = base_vha->host;
2afa19a9 2637 base_vha->req = req;
73208dfd 2638 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2639 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2640 else
e315cd28
AC		 2641 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2642 base_vha->vp_idx;
58548cb5 2643
8ae6d9c7
GM		 2644 /* Setup fcport template structure. */
2645 ha->mr.fcport.vha = base_vha;
2646 ha->mr.fcport.port_type = FCT_UNKNOWN;
2647 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2648 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2649 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2650 ha->mr.fcport.scan_state = 1;
2651
58548cb5
GM		 2652 /* Set the SG table size based on ISP type */
2653 if (!IS_FWI2_CAPABLE(ha)) {
2654 if (IS_QLA2100(ha))
2655 host->sg_tablesize = 32;
2656 } else {
2657 if (!IS_QLA82XX(ha))
2658 host->sg_tablesize = QLA_SG_ALL;
2659 }
642ef983 2660 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2661 host->cmd_per_lun = 3;
2662 host->unique_id = host->host_no;
e02587d7 2663 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2664 host->max_cmd_len = 32;
2665 else
2666 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2667 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2668 /* Older HBAs support only 16-bit LUNs */
2669 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2670 ql2xmaxlun > 0xffff)
2671 host->max_lun = 0xffff;
2672 else
2673 host->max_lun = ql2xmaxlun;
e315cd28 2674 host->transportt = qla2xxx_transport_template;
9a069e19 2675 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2676
7c3df132
SK		 2677 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2678 "max_id=%d this_id=%d "
2679 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2680 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2681 host->this_id, host->cmd_per_lun, host->unique_id,
2682 host->max_cmd_len, host->max_channel, host->max_lun,
2683 host->transportt, sht->vendor_id);
2684
9a347ff4
CD		 2685que_init:
2686 /* Alloc arrays of request and response ring ptrs */
2687 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2688 ql_log(ql_log_fatal, base_vha, 0x003d,
2689 "Failed to allocate memory for queue pointers..."
2690 "aborting.\n");
2691 goto probe_init_failed;
2692 }
2693
2d70c103 2694 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2695
73208dfd
AC		 2696 /* Set up the irqs */
2697 ret = qla2x00_request_irqs(ha, rsp);
2698 if (ret)
6e9f21f3 2699 goto probe_init_failed;
90a86fc0
JC		 2700
2701 pci_save_state(pdev);
2702
9a347ff4 2703 /* Assign back pointers */
2afa19a9
AC		 2704 rsp->req = req;
2705 req->rsp = rsp;
9a347ff4 2706
8ae6d9c7
GM		 2707 if (IS_QLAFX00(ha)) {
2708 ha->rsp_q_map[0] = rsp;
2709 ha->req_q_map[0] = req;
2710 set_bit(0, ha->req_qid_map);
2711 set_bit(0, ha->rsp_qid_map);
2712 }
2713
08029990
AV		 2714 /* FWI2-capable only. */
2715 req->req_q_in = &ha->iobase->isp24.req_q_in;
2716 req->req_q_out = &ha->iobase->isp24.req_q_out;
2717 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2718 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2719 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2720 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2721 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2722 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2723 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2724 }
2725
8ae6d9c7
GM		 2726 if (IS_QLAFX00(ha)) {
2727 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2728 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2729 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2730 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2731 }
2732
7ec0effd 2733 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2734 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2735 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2736 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2737 }
2738
7c3df132
SK		 2739 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2740 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2741 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2742 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2743 "req->req_q_in=%p req->req_q_out=%p "
2744 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2745 req->req_q_in, req->req_q_out,
2746 rsp->rsp_q_in, rsp->rsp_q_out);
2747 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2748 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2749 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2750 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2751 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2752 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2753
8ae6d9c7 2754 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2755 ql_log(ql_log_fatal, base_vha, 0x00d6,
2756 "Failed to initialize adapter - Adapter flags %x.\n",
2757 base_vha->device_flags);
1da177e4 2758
a9083016
GM		 2759 if (IS_QLA82XX(ha)) {
2760 qla82xx_idc_lock(ha);
2761 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2762 QLA8XXX_DEV_FAILED);
a9083016 2763 qla82xx_idc_unlock(ha);
7c3df132
SK		 2764 ql_log(ql_log_fatal, base_vha, 0x00d7,
2765 "HW State: FAILED.\n");
7ec0effd
AD		 2766 } else if (IS_QLA8044(ha)) {
2767 qla8044_idc_lock(ha);
2768 qla8044_wr_direct(base_vha,
2769 QLA8044_CRB_DEV_STATE_INDEX,
2770 QLA8XXX_DEV_FAILED);
2771 qla8044_idc_unlock(ha);
2772 ql_log(ql_log_fatal, base_vha, 0x0150,
2773 "HW State: FAILED.\n");
a9083016
GM		 2774 }
2775
a1541d5a 2776 ret = -ENODEV;
1da177e4
LT		 2777 goto probe_failed;
2778 }
2779
3b1bef64
CD		 2780 if (IS_QLAFX00(ha))
2781 host->can_queue = QLAFX00_MAX_CANQUEUE;
2782 else
2783 host->can_queue = req->num_outstanding_cmds - 10;
2784
2785 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2786 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2787 host->can_queue, base_vha->req,
2788 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2789
7163ea81
AC		 2790 if (ha->mqenable) {
2791 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2792 ql_log(ql_log_warn, base_vha, 0x00ec,
2793 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2794 goto que_init;
2795 }
2796 }
68ca949c 2797
cbc8eb67
AV		 2798 if (ha->flags.running_gold_fw)
2799 goto skip_dpc;
2800
1da177e4
LT		 2801 /*
2802 * Startup the kernel thread for this host adapter
2803 */
39a11240 2804 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2805 "%s_dpc", base_vha->host_str);
39a11240 2806 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2807 ql_log(ql_log_fatal, base_vha, 0x00ed,
2808 "Failed to start DPC thread.\n");
39a11240 2809 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2810 goto probe_failed;
2811 }
7c3df132
SK		 2812 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2813 "DPC thread started successfully.\n");
1da177e4 2814
2d70c103
NB		 2815 /*
2816 * If we're not coming up in initiator mode, we might sit for
2817 * a while without waking up the dpc thread, which leads to a
2818 * stuck process warning. So just kick the dpc once here and
2819 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2820 */
2821 qla2xxx_wake_dpc(base_vha);
2822
f3ddac19
CD		 2823 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2824
81178772
SK		 2825 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2826 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2827 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2828 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2829
2830 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2831 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2832 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2833 INIT_WORK(&ha->idc_state_handler,
2834 qla83xx_idc_state_handler_work);
2835 INIT_WORK(&ha->nic_core_unrecoverable,
2836 qla83xx_nic_core_unrecoverable_work);
2837 }
2838
cbc8eb67 2839skip_dpc:
e315cd28
AC		 2840 list_add_tail(&base_vha->list, &ha->vp_list);
2841 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2842
2843 /* Initialized the timer */
e315cd28 2844 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2845 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2846 "Started qla2x00_timer with "
2847 "interval=%d.\n", WATCH_INTERVAL);
2848 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2849 "Detected hba at address=%p.\n",
2850 ha);
d19044c3 2851
e02587d7 2852 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2853 if (ha->fw_attributes & BIT_4) {
9e522cd8 2854 int prot = 0, guard;
bad75002 2855 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2856 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2857 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2858 if (ql2xenabledif == 1)
2859 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2860 scsi_host_set_prot(host,
8cb2049c 2861 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2862 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2863 | SHOST_DIF_TYPE3_PROTECTION
2864 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2865 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2866 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2867
2868 guard = SHOST_DIX_GUARD_CRC;
2869
2870 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2871 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2872 guard |= SHOST_DIX_GUARD_IP;
2873
2874 scsi_host_set_guard(host, guard);
bad75002
AE		 2875 } else
2876 base_vha->flags.difdix_supported = 0;
2877 }
2878
a9083016
GM		 2879 ha->isp_ops->enable_intrs(ha);
2880
1fe19ee4
AB		 2881 if (IS_QLAFX00(ha)) {
2882 ret = qlafx00_fx_disc(base_vha,
2883 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2884 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2885 QLA_SG_ALL : 128;
2886 }
2887
a1541d5a
AV		 2888 ret = scsi_add_host(host, &pdev->dev);
2889 if (ret)
2890 goto probe_failed;
2891
1486400f
MR		 2892 base_vha->flags.init_done = 1;
2893 base_vha->flags.online = 1;
edaa5c74 2894 ha->prev_minidump_failed = 0;
1486400f 2895
7c3df132
SK		 2896 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2897 "Init done and hba is online.\n");
2898
2d70c103
NB		 2899 if (qla_ini_mode_enabled(base_vha))
2900 scsi_scan_host(host);
2901 else
2902 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2903 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2904
e315cd28 2905 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2906
8ae6d9c7 2907 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2908 ret = qlafx00_fx_disc(base_vha,
2909 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2910
2911 /* Register system information */
2912 ret = qlafx00_fx_disc(base_vha,
2913 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2914 }
2915
e315cd28 2916 qla2x00_init_host_attr(base_vha);
a1541d5a 2917
e315cd28 2918 qla2x00_dfs_setup(base_vha);
df613b96 2919
03eb912a
AB		 2920 ql_log(ql_log_info, base_vha, 0x00fb,
2921 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2922 ql_log(ql_log_info, base_vha, 0x00fc,
2923 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2924 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2925 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2926 base_vha->host_no,
e315cd28 2927 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2928
2d70c103
NB		 2929 qlt_add_target(ha, base_vha);
2930
1da177e4
LT		 2931 return 0;
2932
6e9f21f3 2933probe_init_failed:
2afa19a9 2934 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2935 ha->req_q_map[0] = NULL;
2936 clear_bit(0, ha->req_qid_map);
2afa19a9 2937 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2938 ha->rsp_q_map[0] = NULL;
2939 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2940 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2941
1da177e4 2942probe_failed:
b9978769
AV		 2943 if (base_vha->timer_active)
2944 qla2x00_stop_timer(base_vha);
2945 base_vha->flags.online = 0;
2946 if (ha->dpc_thread) {
2947 struct task_struct *t = ha->dpc_thread;
2948
2949 ha->dpc_thread = NULL;
2950 kthread_stop(t);
2951 }
2952
e315cd28 2953 qla2x00_free_device(base_vha);
1da177e4 2954
e315cd28 2955 scsi_host_put(base_vha->host);
1da177e4 2956
e315cd28 2957probe_hw_failed:
1a2fbf18
JL		 2958 qla2x00_clear_drv_active(ha);
2959
0a63ad12 2960iospace_config_failed:
7ec0effd 2961 if (IS_P3P_TYPE(ha)) {
0a63ad12 2962 if (!ha->nx_pcibase)
f73cb695 2963 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2964 if (!ql2xdbwr)
f73cb695 2965 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2966 } else {
2967 if (ha->iobase)
2968 iounmap(ha->iobase);
8ae6d9c7
GM		 2969 if (ha->cregbase)
2970 iounmap(ha->cregbase);
a9083016 2971 }
e315cd28
AC		 2972 pci_release_selected_regions(ha->pdev, ha->bars);
2973 kfree(ha);
2974 ha = NULL;
1da177e4 2975
a1541d5a 2976probe_out:
e315cd28 2977 pci_disable_device(pdev);
a1541d5a 2978 return ret;
1da177e4 2979}
1da177e4 2980
e30d1756
MI		 2981static void
2982qla2x00_shutdown(struct pci_dev *pdev)
2983{
2984 scsi_qla_host_t *vha;
2985 struct qla_hw_data *ha;
2986
552f3f9a
MI		 2987 if (!atomic_read(&pdev->enable_cnt))
2988 return;
2989
e30d1756
MI		 2990 vha = pci_get_drvdata(pdev);
2991 ha = vha->hw;
2992
42479343
AB		 2993 /* Notify ISPFX00 firmware */
2994 if (IS_QLAFX00(ha))
2995 qlafx00_driver_shutdown(vha, 20);
2996
e30d1756
MI		 2997 /* Turn-off FCE trace */
2998 if (ha->flags.fce_enabled) {
2999 qla2x00_disable_fce_trace(vha, NULL, NULL);
3000 ha->flags.fce_enabled = 0;
3001 }
3002
3003 /* Turn-off EFT trace */
3004 if (ha->eft)
3005 qla2x00_disable_eft_trace(vha);
3006
3007 /* Stop currently executing firmware. */
3008 qla2x00_try_to_stop_firmware(vha);
3009
3010 /* Turn adapter off line */
3011 vha->flags.online = 0;
3012
3013 /* turn-off interrupts on the card */
3014 if (ha->interrupts_on) {
3015 vha->flags.init_done = 0;
3016 ha->isp_ops->disable_intrs(ha);
3017 }
3018
3019 qla2x00_free_irqs(vha);
3020
3021 qla2x00_free_fw_dump(ha);
3022}
3023
fe1b806f 3024/* Deletes all the virtual ports for a given ha */
4c993f76 3025static void
fe1b806f 3026qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3027{
fe1b806f
CD		 3028 struct Scsi_Host *scsi_host;
3029 scsi_qla_host_t *vha;
feafb7b1 3030 unsigned long flags;
e315cd28 3031
43ebf16d
AE		 3032 mutex_lock(&ha->vport_lock);
3033 while (ha->cur_vport_count) {
43ebf16d 3034 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3035
43ebf16d
AE		 3036 BUG_ON(base_vha->list.next == &ha->vp_list);
3037 /* This assumes first entry in ha->vp_list is always base vha */
3038 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 3039 scsi_host = scsi_host_get(vha->host);
feafb7b1 3040
43ebf16d
AE		 3041 spin_unlock_irqrestore(&ha->vport_slock, flags);
3042 mutex_unlock(&ha->vport_lock);
3043
3044 fc_vport_terminate(vha->fc_vport);
3045 scsi_host_put(vha->host);
feafb7b1 3046
43ebf16d 3047 mutex_lock(&ha->vport_lock);
e315cd28 3048 }
43ebf16d 3049 mutex_unlock(&ha->vport_lock);
fe1b806f 3050}
1da177e4 3051
fe1b806f
CD		 3052/* Stops all deferred work threads */
3053static void
3054qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3055{
68ca949c
AC		 3056 /* Flush the work queue and remove it */
3057 if (ha->wq) {
3058 flush_workqueue(ha->wq);
3059 destroy_workqueue(ha->wq);
3060 ha->wq = NULL;
3061 }
3062
7d613ac6
SV		 3063 /* Cancel all work and destroy DPC workqueues */
3064 if (ha->dpc_lp_wq) {
3065 cancel_work_sync(&ha->idc_aen);
3066 destroy_workqueue(ha->dpc_lp_wq);
3067 ha->dpc_lp_wq = NULL;
3068 }
3069
3070 if (ha->dpc_hp_wq) {
3071 cancel_work_sync(&ha->nic_core_reset);
3072 cancel_work_sync(&ha->idc_state_handler);
3073 cancel_work_sync(&ha->nic_core_unrecoverable);
3074 destroy_workqueue(ha->dpc_hp_wq);
3075 ha->dpc_hp_wq = NULL;
3076 }
3077
b9978769
AV		 3078 /* Kill the kernel thread for this host */
3079 if (ha->dpc_thread) {
3080 struct task_struct *t = ha->dpc_thread;
3081
3082 /*
3083 * qla2xxx_wake_dpc checks for ->dpc_thread
3084 * so we need to zero it out.
3085 */
3086 ha->dpc_thread = NULL;
3087 kthread_stop(t);
3088 }
fe1b806f 3089}
1da177e4 3090
fe1b806f
CD		 3091static void
3092qla2x00_unmap_iobases(struct qla_hw_data *ha)
3093{
a9083016 3094 if (IS_QLA82XX(ha)) {
b963752f 3095
f73cb695 3096 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3097 if (!ql2xdbwr)
f73cb695 3098 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3099 } else {
3100 if (ha->iobase)
3101 iounmap(ha->iobase);
1da177e4 3102
8ae6d9c7
GM		 3103 if (ha->cregbase)
3104 iounmap(ha->cregbase);
3105
a9083016
GM		 3106 if (ha->mqiobase)
3107 iounmap(ha->mqiobase);
6246b8a1 3108
f73cb695 3109 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3110 iounmap(ha->msixbase);
a9083016 3111 }
fe1b806f
CD		 3112}
3113
3114static void
db7157d4 3115qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3116{
fe1b806f
CD		 3117 if (IS_QLA8044(ha)) {
3118 qla8044_idc_lock(ha);
c41afc9a 3119 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3120 qla8044_idc_unlock(ha);
3121 } else if (IS_QLA82XX(ha)) {
3122 qla82xx_idc_lock(ha);
3123 qla82xx_clear_drv_active(ha);
3124 qla82xx_idc_unlock(ha);
3125 }
3126}
3127
3128static void
3129qla2x00_remove_one(struct pci_dev *pdev)
3130{
3131 scsi_qla_host_t *base_vha;
3132 struct qla_hw_data *ha;
3133
3134 /*
3135 * If the PCI device is disabled that means that probe failed and any
3136 * resources should be have cleaned up on probe exit.
3137 */
3138 if (!atomic_read(&pdev->enable_cnt))
3139 return;
3140
3141 base_vha = pci_get_drvdata(pdev);
3142 ha = base_vha->hw;
3143
638a1a01
SC		 3144 qla2x00_wait_for_hba_ready(base_vha);
3145
fe1b806f
CD		 3146 set_bit(UNLOADING, &base_vha->dpc_flags);
3147
3148 if (IS_QLAFX00(ha))
3149 qlafx00_driver_shutdown(base_vha, 20);
3150
3151 qla2x00_delete_all_vps(ha, base_vha);
3152
3153 if (IS_QLA8031(ha)) {
3154 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3155 "Clearing fcoe driver presence.\n");
3156 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3157 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3158 "Error while clearing DRV-Presence.\n");
3159 }
3160
3161 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3162
3163 qla2x00_dfs_remove(base_vha);
3164
3165 qla84xx_put_chip(base_vha);
3166
3167 /* Disable timer */
3168 if (base_vha->timer_active)
3169 qla2x00_stop_timer(base_vha);
3170
3171 base_vha->flags.online = 0;
3172
3173 qla2x00_destroy_deferred_work(ha);
3174
3175 qlt_remove_target(ha, base_vha);
3176
3177 qla2x00_free_sysfs_attr(base_vha, true);
3178
3179 fc_remove_host(base_vha->host);
3180
3181 scsi_remove_host(base_vha->host);
3182
3183 qla2x00_free_device(base_vha);
3184
3185 scsi_host_put(base_vha->host);
3186
db7157d4 3187 qla2x00_clear_drv_active(ha);
fe1b806f
CD		 3188
3189 qla2x00_unmap_iobases(ha);
73208dfd 3190
e315cd28
AC		 3191 pci_release_selected_regions(ha->pdev, ha->bars);
3192 kfree(ha);
3193 ha = NULL;
1da177e4 3194
90a86fc0
JC		 3195 pci_disable_pcie_error_reporting(pdev);
3196
665db93b 3197 pci_disable_device(pdev);
1da177e4 3198}
1da177e4
LT		 3199
3200static void
e315cd28 3201qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3202{
e315cd28 3203 struct qla_hw_data *ha = vha->hw;
1da177e4 3204
85880801
AV		 3205 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3206
3207 /* Disable timer */
3208 if (vha->timer_active)
3209 qla2x00_stop_timer(vha);
3210
2afa19a9 3211 qla25xx_delete_queues(vha);
fe1b806f 3212
df613b96 3213 if (ha->flags.fce_enabled)
e315cd28 3214 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3215
a7a167bf 3216 if (ha->eft)
e315cd28 3217 qla2x00_disable_eft_trace(vha);
a7a167bf 3218
f6ef3b18 3219 /* Stop currently executing firmware. */
e315cd28 3220 qla2x00_try_to_stop_firmware(vha);
1da177e4 3221
85880801
AV		 3222 vha->flags.online = 0;
3223
f6ef3b18 3224 /* turn-off interrupts on the card */
a9083016
GM		 3225 if (ha->interrupts_on) {
3226 vha->flags.init_done = 0;
fd34f556 3227 ha->isp_ops->disable_intrs(ha);
a9083016 3228 }
f6ef3b18 3229
e315cd28 3230 qla2x00_free_irqs(vha);
1da177e4 3231
8867048b
CD		 3232 qla2x00_free_fcports(vha);
3233
e315cd28 3234 qla2x00_mem_free(ha);
73208dfd 3235
08de2844
GM		 3236 qla82xx_md_free(vha);
3237
73208dfd 3238 qla2x00_free_queues(ha);
1da177e4
LT		 3239}
3240
8867048b
CD		 3241void qla2x00_free_fcports(struct scsi_qla_host *vha)
3242{
3243 fc_port_t *fcport, *tfcport;
3244
3245 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3246 list_del(&fcport->list);
5f16b331 3247 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3248 kfree(fcport);
3249 fcport = NULL;
3250 }
3251}
3252
d97994dc 3253static inline void
e315cd28 3254qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3255 int defer)
3256{
d97994dc 3257 struct fc_rport *rport;
67becc00 3258 scsi_qla_host_t *base_vha;
044d78e1 3259 unsigned long flags;
d97994dc
AV		 3260
3261 if (!fcport->rport)
3262 return;
3263
3264 rport = fcport->rport;
3265 if (defer) {
67becc00 3266 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3267 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3268 fcport->drport = rport;
044d78e1 3269 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3270 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3271 qla2xxx_wake_dpc(base_vha);
2d70c103 3272 } else {
d97994dc 3273 fc_remote_port_delete(rport);
2d70c103
NB		 3274 qlt_fc_port_deleted(vha, fcport);
3275 }
d97994dc
AV		 3276}
3277
1da177e4
LT		 3278/*
3279 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3280 *
3281 * Input: ha = adapter block pointer. fcport = port structure pointer.
3282 *
3283 * Return: None.
3284 *
3285 * Context:
3286 */
e315cd28 3287void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3288 int do_login, int defer)
1da177e4 3289{
8ae6d9c7
GM		 3290 if (IS_QLAFX00(vha->hw)) {
3291 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3292 qla2x00_schedule_rport_del(vha, fcport, defer);
3293 return;
3294 }
3295
2c3dfe3f 3296 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3297 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3298 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3299 qla2x00_schedule_rport_del(vha, fcport, defer);
3300 }
fa2a1ce5 3301 /*
1da177e4
LT		 3302 * We may need to retry the login, so don't change the state of the
3303 * port but do the retries.
3304 */
3305 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3306 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3307
3308 if (!do_login)
3309 return;
3310
3311 if (fcport->login_retry == 0) {
e315cd28
AC		 3312 fcport->login_retry = vha->hw->login_retry_count;
3313 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3314
7c3df132 3315 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3316 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3317 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3318 }
3319}
3320
3321/*
3322 * qla2x00_mark_all_devices_lost
3323 * Updates fcport state when device goes offline.
3324 *
3325 * Input:
3326 * ha = adapter block pointer.
3327 * fcport = port structure pointer.
3328 *
3329 * Return:
3330 * None.
3331 *
3332 * Context:
3333 */
3334void
e315cd28 3335qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3336{
3337 fc_port_t *fcport;
3338
e315cd28 3339 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3340 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3341 continue;
0d6e61bc 3342
1da177e4
LT		 3343 /*
3344 * No point in marking the device as lost, if the device is
3345 * already DEAD.
3346 */
3347 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3348 continue;
e315cd28 3349 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3350 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3351 if (defer)
3352 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3353 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3354 qla2x00_schedule_rport_del(vha, fcport, defer);
3355 }
1da177e4
LT		 3356 }
3357}
3358
3359/*
3360* qla2x00_mem_alloc
3361* Allocates adapter memory.
3362*
3363* Returns:
3364* 0 = success.
e8711085 3365* !0 = failure.
1da177e4 3366*/
e8711085 3367static int
73208dfd
AC		 3368qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3369 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3370{
3371 char name[16];
1da177e4 3372
e8711085 3373 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3374 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3375 if (!ha->init_cb)
e315cd28 3376 goto fail;
e8711085 3377
2d70c103
NB		 3378 if (qlt_mem_alloc(ha) < 0)
3379 goto fail_free_init_cb;
3380
642ef983
CD		 3381 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3382 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3383 if (!ha->gid_list)
2d70c103 3384 goto fail_free_tgt_mem;
1da177e4 3385
e8711085
AV		 3386 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3387 if (!ha->srb_mempool)
e315cd28 3388 goto fail_free_gid_list;
e8711085 3389
7ec0effd 3390 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3391 /* Allocate cache for CT6 Ctx. */
3392 if (!ctx_cachep) {
3393 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3394 sizeof(struct ct6_dsd), 0,
3395 SLAB_HWCACHE_ALIGN, NULL);
3396 if (!ctx_cachep)
3397 goto fail_free_gid_list;
3398 }
3399 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3400 ctx_cachep);
3401 if (!ha->ctx_mempool)
3402 goto fail_free_srb_mempool;
7c3df132
SK		 3403 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3404 "ctx_cachep=%p ctx_mempool=%p.\n",
3405 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3406 }
3407
e8711085
AV		 3408 /* Get memory for cached NVRAM */
3409 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3410 if (!ha->nvram)
a9083016 3411 goto fail_free_ctx_mempool;
e8711085 3412
e315cd28
AC		 3413 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3414 ha->pdev->device);
3415 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3416 DMA_POOL_SIZE, 8, 0);
3417 if (!ha->s_dma_pool)
3418 goto fail_free_nvram;
3419
7c3df132
SK		 3420 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3421 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3422 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3423
7ec0effd 3424 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3425 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3426 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3427 if (!ha->dl_dma_pool) {
7c3df132
SK		 3428 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3429 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3430 goto fail_s_dma_pool;
3431 }
3432
3433 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3434 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3435 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3436 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3437 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3438 goto fail_dl_dma_pool;
3439 }
7c3df132
SK		 3440 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3441 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3442 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3443 }
3444
e8711085
AV		 3445 /* Allocate memory for SNS commands */
3446 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3447 /* Get consistent memory allocated for SNS commands */
e8711085 3448 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3449 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3450 if (!ha->sns_cmd)
e315cd28 3451 goto fail_dma_pool;
7c3df132 3452 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3453 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3454 } else {
e315cd28 3455 /* Get consistent memory allocated for MS IOCB */
e8711085 3456 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3457 &ha->ms_iocb_dma);
e8711085 3458 if (!ha->ms_iocb)
e315cd28
AC		 3459 goto fail_dma_pool;
3460 /* Get consistent memory allocated for CT SNS commands */
e8711085 3461 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3462 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3463 if (!ha->ct_sns)
3464 goto fail_free_ms_iocb;
7c3df132
SK		 3465 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3466 "ms_iocb=%p ct_sns=%p.\n",
3467 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3468 }
3469
e315cd28 3470 /* Allocate memory for request ring */
73208dfd
AC		 3471 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3472 if (!*req) {
7c3df132
SK		 3473 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3474 "Failed to allocate memory for req.\n");
e315cd28
AC		 3475 goto fail_req;
3476 }
73208dfd
AC		 3477 (*req)->length = req_len;
3478 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3479 ((*req)->length + 1) * sizeof(request_t),
3480 &(*req)->dma, GFP_KERNEL);
3481 if (!(*req)->ring) {
7c3df132
SK		 3482 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3483 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3484 goto fail_req_ring;
3485 }
3486 /* Allocate memory for response ring */
73208dfd
AC		 3487 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3488 if (!*rsp) {
7c3df132
SK		 3489 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3490 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3491 goto fail_rsp;
3492 }
73208dfd
AC		 3493 (*rsp)->hw = ha;
3494 (*rsp)->length = rsp_len;
3495 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3496 ((*rsp)->length + 1) * sizeof(response_t),
3497 &(*rsp)->dma, GFP_KERNEL);
3498 if (!(*rsp)->ring) {
7c3df132
SK		 3499 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3500 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3501 goto fail_rsp_ring;
3502 }
73208dfd
AC		 3503 (*req)->rsp = *rsp;
3504 (*rsp)->req = *req;
7c3df132
SK		 3505 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3506 "req=%p req->length=%d req->ring=%p rsp=%p "
3507 "rsp->length=%d rsp->ring=%p.\n",
3508 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3509 (*rsp)->ring);
73208dfd
AC		 3510 /* Allocate memory for NVRAM data for vports */
3511 if (ha->nvram_npiv_size) {
3512 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3513 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3514 if (!ha->npiv_info) {
7c3df132
SK		 3515 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3516 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3517 goto fail_npiv_info;
3518 }
3519 } else
3520 ha->npiv_info = NULL;
e8711085 3521
b64b0e8f 3522 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3523 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3524 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3525 &ha->ex_init_cb_dma);
3526 if (!ha->ex_init_cb)
3527 goto fail_ex_init_cb;
7c3df132
SK		 3528 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3529 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3530 }
3531
a9083016
GM		 3532 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3533
5ff1d584
AV		 3534 /* Get consistent memory allocated for Async Port-Database. */
3535 if (!IS_FWI2_CAPABLE(ha)) {
3536 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3537 &ha->async_pd_dma);
3538 if (!ha->async_pd)
3539 goto fail_async_pd;
7c3df132
SK		 3540 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3541 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3542 }
3543
e315cd28 3544 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3545
3546 /* Allocate memory for our loop_id bitmap */
3547 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3548 GFP_KERNEL);
3549 if (!ha->loop_id_map)
3550 goto fail_async_pd;
3551 else {
3552 qla2x00_set_reserved_loop_ids(ha);
3553 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3554 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3555 }
3556
b2a72ec3 3557 return 0;
e315cd28 3558
5ff1d584
AV		 3559fail_async_pd:
3560 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3561fail_ex_init_cb:
3562 kfree(ha->npiv_info);
73208dfd
AC		 3563fail_npiv_info:
3564 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3565 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3566 (*rsp)->ring = NULL;
3567 (*rsp)->dma = 0;
e315cd28 3568fail_rsp_ring:
73208dfd 3569 kfree(*rsp);
e315cd28 3570fail_rsp:
73208dfd
AC		 3571 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3572 sizeof(request_t), (*req)->ring, (*req)->dma);
3573 (*req)->ring = NULL;
3574 (*req)->dma = 0;
e315cd28 3575fail_req_ring:
73208dfd 3576 kfree(*req);
e315cd28
AC		 3577fail_req:
3578 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3579 ha->ct_sns, ha->ct_sns_dma);
3580 ha->ct_sns = NULL;
3581 ha->ct_sns_dma = 0;
e8711085
AV		 3582fail_free_ms_iocb:
3583 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3584 ha->ms_iocb = NULL;
3585 ha->ms_iocb_dma = 0;
e315cd28 3586fail_dma_pool:
bad75002 3587 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3588 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3589 ha->fcp_cmnd_dma_pool = NULL;
3590 }
3591fail_dl_dma_pool:
bad75002 3592 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3593 dma_pool_destroy(ha->dl_dma_pool);
3594 ha->dl_dma_pool = NULL;
3595 }
3596fail_s_dma_pool:
e315cd28
AC		 3597 dma_pool_destroy(ha->s_dma_pool);
3598 ha->s_dma_pool = NULL;
e8711085
AV		 3599fail_free_nvram:
3600 kfree(ha->nvram);
3601 ha->nvram = NULL;
a9083016
GM		 3602fail_free_ctx_mempool:
3603 mempool_destroy(ha->ctx_mempool);
3604 ha->ctx_mempool = NULL;
e8711085
AV		 3605fail_free_srb_mempool:
3606 mempool_destroy(ha->srb_mempool);
3607 ha->srb_mempool = NULL;
e8711085 3608fail_free_gid_list:
642ef983
CD		 3609 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3610 ha->gid_list,
e315cd28 3611 ha->gid_list_dma);
e8711085
AV		 3612 ha->gid_list = NULL;
3613 ha->gid_list_dma = 0;
2d70c103
NB		 3614fail_free_tgt_mem:
3615 qlt_mem_free(ha);
e315cd28
AC		 3616fail_free_init_cb:
3617 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3618 ha->init_cb_dma);
3619 ha->init_cb = NULL;
3620 ha->init_cb_dma = 0;
e8711085 3621fail:
7c3df132
SK		 3622 ql_log(ql_log_fatal, NULL, 0x0030,
3623 "Memory allocation failure.\n");
e8711085 3624 return -ENOMEM;
1da177e4
LT		 3625}
3626
3627/*
e30d1756
MI		 3628* qla2x00_free_fw_dump
3629* Frees fw dump stuff.
1da177e4
LT		 3630*
3631* Input:
7ec0effd 3632* ha = adapter block pointer
1da177e4 3633*/
a824ebb3 3634static void
e30d1756 3635qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3636{
df613b96 3637 if (ha->fce)
f73cb695
CD		 3638 dma_free_coherent(&ha->pdev->dev,
3639 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3640
f73cb695
CD		 3641 if (ha->eft)
3642 dma_free_coherent(&ha->pdev->dev,
3643 EFT_SIZE, ha->eft, ha->eft_dma);
3644
3645 if (ha->fw_dump)
a7a167bf 3646 vfree(ha->fw_dump);
f73cb695
CD		 3647 if (ha->fw_dump_template)
3648 vfree(ha->fw_dump_template);
3649
e30d1756
MI		 3650 ha->fce = NULL;
3651 ha->fce_dma = 0;
3652 ha->eft = NULL;
3653 ha->eft_dma = 0;
e30d1756 3654 ha->fw_dumped = 0;
61f098dd 3655 ha->fw_dump_cap_flags = 0;
e30d1756 3656 ha->fw_dump_reading = 0;
f73cb695
CD		 3657 ha->fw_dump = NULL;
3658 ha->fw_dump_len = 0;
3659 ha->fw_dump_template = NULL;
3660 ha->fw_dump_template_len = 0;
e30d1756
MI		 3661}
3662
3663/*
3664* qla2x00_mem_free
3665* Frees all adapter allocated memory.
3666*
3667* Input:
3668* ha = adapter block pointer.
3669*/
3670static void
3671qla2x00_mem_free(struct qla_hw_data *ha)
3672{
3673 qla2x00_free_fw_dump(ha);
3674
81178772
SK		 3675 if (ha->mctp_dump)
3676 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3677 ha->mctp_dump_dma);
3678
e30d1756
MI		 3679 if (ha->srb_mempool)
3680 mempool_destroy(ha->srb_mempool);
a7a167bf 3681
11bbc1d8
AV		 3682 if (ha->dcbx_tlv)
3683 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3684 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3685
ce0423f4
AV		 3686 if (ha->xgmac_data)
3687 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3688 ha->xgmac_data, ha->xgmac_data_dma);
3689
1da177e4
LT		 3690 if (ha->sns_cmd)
3691 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3692 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3693
3694 if (ha->ct_sns)
3695 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3696 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3697
88729e53
AV		 3698 if (ha->sfp_data)
3699 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3700
1da177e4
LT		 3701 if (ha->ms_iocb)
3702 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3703
b64b0e8f 3704 if (ha->ex_init_cb)
a9083016
GM		 3705 dma_pool_free(ha->s_dma_pool,
3706 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3707
5ff1d584
AV		 3708 if (ha->async_pd)
3709 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3710
1da177e4
LT		 3711 if (ha->s_dma_pool)
3712 dma_pool_destroy(ha->s_dma_pool);
3713
1da177e4 3714 if (ha->gid_list)
642ef983
CD		 3715 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3716 ha->gid_list, ha->gid_list_dma);
1da177e4 3717
a9083016
GM		 3718 if (IS_QLA82XX(ha)) {
3719 if (!list_empty(&ha->gbl_dsd_list)) {
3720 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3721
3722 /* clean up allocated prev pool */
3723 list_for_each_entry_safe(dsd_ptr,
3724 tdsd_ptr, &ha->gbl_dsd_list, list) {
3725 dma_pool_free(ha->dl_dma_pool,
3726 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3727 list_del(&dsd_ptr->list);
3728 kfree(dsd_ptr);
3729 }
3730 }
3731 }
3732
3733 if (ha->dl_dma_pool)
3734 dma_pool_destroy(ha->dl_dma_pool);
3735
3736 if (ha->fcp_cmnd_dma_pool)
3737 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3738
3739 if (ha->ctx_mempool)
3740 mempool_destroy(ha->ctx_mempool);
3741
2d70c103
NB		 3742 qlt_mem_free(ha);
3743
e315cd28
AC		 3744 if (ha->init_cb)
3745 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3746 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3747 vfree(ha->optrom_buffer);
3748 kfree(ha->nvram);
73208dfd 3749 kfree(ha->npiv_info);
7a67735b 3750 kfree(ha->swl);
5f16b331 3751 kfree(ha->loop_id_map);
1da177e4 3752
e8711085 3753 ha->srb_mempool = NULL;
a9083016 3754 ha->ctx_mempool = NULL;
1da177e4
LT		 3755 ha->sns_cmd = NULL;
3756 ha->sns_cmd_dma = 0;
3757 ha->ct_sns = NULL;
3758 ha->ct_sns_dma = 0;
3759 ha->ms_iocb = NULL;
3760 ha->ms_iocb_dma = 0;
1da177e4
LT		 3761 ha->init_cb = NULL;
3762 ha->init_cb_dma = 0;
b64b0e8f
AV		 3763 ha->ex_init_cb = NULL;
3764 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3765 ha->async_pd = NULL;
3766 ha->async_pd_dma = 0;
1da177e4
LT		 3767
3768 ha->s_dma_pool = NULL;
a9083016
GM		 3769 ha->dl_dma_pool = NULL;
3770 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3771
1da177e4
LT		 3772 ha->gid_list = NULL;
3773 ha->gid_list_dma = 0;
2d70c103
NB		 3774
3775 ha->tgt.atio_ring = NULL;
3776 ha->tgt.atio_dma = 0;
3777 ha->tgt.tgt_vp_map = NULL;
e315cd28 3778}
1da177e4 3779
e315cd28
AC		 3780struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3781 struct qla_hw_data *ha)
3782{
3783 struct Scsi_Host *host;
3784 struct scsi_qla_host *vha = NULL;
854165f4 3785
e315cd28
AC		 3786 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3787 if (host == NULL) {
7c3df132
SK		 3788 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3789 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3790 goto fail;
3791 }
3792
3793 /* Clear our data area */
3794 vha = shost_priv(host);
3795 memset(vha, 0, sizeof(scsi_qla_host_t));
3796
3797 vha->host = host;
3798 vha->host_no = host->host_no;
3799 vha->hw = ha;
3800
3801 INIT_LIST_HEAD(&vha->vp_fcports);
3802 INIT_LIST_HEAD(&vha->work_list);
3803 INIT_LIST_HEAD(&vha->list);
3804
f999f4c1
AV		 3805 spin_lock_init(&vha->work_lock);
3806
e315cd28 3807 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3808 ql_dbg(ql_dbg_init, vha, 0x0041,
3809 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3810 vha->host, vha->hw, vha,
3811 dev_name(&(ha->pdev->dev)));
3812
e315cd28
AC		 3813 return vha;
3814
3815fail:
3816 return vha;
1da177e4
LT		 3817}
3818
01ef66bb 3819static struct qla_work_evt *
f999f4c1 3820qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3821{
3822 struct qla_work_evt *e;
feafb7b1
AE		 3823 uint8_t bail;
3824
3825 QLA_VHA_MARK_BUSY(vha, bail);
3826 if (bail)
3827 return NULL;
0971de7f 3828
f999f4c1 3829 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3830 if (!e) {
3831 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3832 return NULL;
feafb7b1 3833 }
0971de7f
AV		 3834
3835 INIT_LIST_HEAD(&e->list);
3836 e->type = type;
3837 e->flags = QLA_EVT_FLAG_FREE;
3838 return e;
3839}
3840
01ef66bb 3841static int
f999f4c1 3842qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3843{
f999f4c1 3844 unsigned long flags;
0971de7f 3845
f999f4c1 3846 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3847 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3848 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3849 qla2xxx_wake_dpc(vha);
f999f4c1 3850
0971de7f
AV		 3851 return QLA_SUCCESS;
3852}
3853
3854int
e315cd28 3855qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3856 u32 data)
3857{
3858 struct qla_work_evt *e;
3859
f999f4c1 3860 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3861 if (!e)
3862 return QLA_FUNCTION_FAILED;
3863
3864 e->u.aen.code = code;
3865 e->u.aen.data = data;
f999f4c1 3866 return qla2x00_post_work(vha, e);
0971de7f
AV		 3867}
3868
8a659571
AV		 3869int
3870qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3871{
3872 struct qla_work_evt *e;
3873
f999f4c1 3874 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3875 if (!e)
3876 return QLA_FUNCTION_FAILED;
3877
3878 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3879 return qla2x00_post_work(vha, e);
8a659571
AV		 3880}
3881
ac280b67
AV		 3882#define qla2x00_post_async_work(name, type) \
3883int qla2x00_post_async_##name##_work( \
3884 struct scsi_qla_host *vha, \
3885 fc_port_t *fcport, uint16_t *data) \
3886{ \
3887 struct qla_work_evt *e; \
3888 \
3889 e = qla2x00_alloc_work(vha, type); \
3890 if (!e) \
3891 return QLA_FUNCTION_FAILED; \
3892 \
3893 e->u.logio.fcport = fcport; \
3894 if (data) { \
3895 e->u.logio.data[0] = data[0]; \
3896 e->u.logio.data[1] = data[1]; \
3897 } \
3898 return qla2x00_post_work(vha, e); \
3899}
3900
3901qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3902qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3903qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3904qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3905qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3906qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3907
3420d36c
AV		 3908int
3909qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3910{
3911 struct qla_work_evt *e;
3912
3913 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3914 if (!e)
3915 return QLA_FUNCTION_FAILED;
3916
3917 e->u.uevent.code = code;
3918 return qla2x00_post_work(vha, e);
3919}
3920
3921static void
3922qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3923{
3924 char event_string[40];
3925 char *envp[] = { event_string, NULL };
3926
3927 switch (code) {
3928 case QLA_UEVENT_CODE_FW_DUMP:
3929 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3930 vha->host_no);
3931 break;
3932 default:
3933 /* do nothing */
3934 break;
3935 }
3936 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3937}
3938
8ae6d9c7
GM		 3939int
3940qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3941 uint32_t *data, int cnt)
3942{
3943 struct qla_work_evt *e;
3944
3945 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3946 if (!e)
3947 return QLA_FUNCTION_FAILED;
3948
3949 e->u.aenfx.evtcode = evtcode;
3950 e->u.aenfx.count = cnt;
3951 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3952 return qla2x00_post_work(vha, e);
3953}
3954
ac280b67 3955void
e315cd28 3956qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3957{
f999f4c1
AV		 3958 struct qla_work_evt *e, *tmp;
3959 unsigned long flags;
3960 LIST_HEAD(work);
0971de7f 3961
f999f4c1
AV		 3962 spin_lock_irqsave(&vha->work_lock, flags);
3963 list_splice_init(&vha->work_list, &work);
3964 spin_unlock_irqrestore(&vha->work_lock, flags);
3965
3966 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3967 list_del_init(&e->list);
0971de7f
AV		 3968
3969 switch (e->type) {
3970 case QLA_EVT_AEN:
e315cd28 3971 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3972 e->u.aen.code, e->u.aen.data);
3973 break;
8a659571
AV		 3974 case QLA_EVT_IDC_ACK:
3975 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3976 break;
ac280b67
AV		 3977 case QLA_EVT_ASYNC_LOGIN:
3978 qla2x00_async_login(vha, e->u.logio.fcport,
3979 e->u.logio.data);
3980 break;
3981 case QLA_EVT_ASYNC_LOGIN_DONE:
3982 qla2x00_async_login_done(vha, e->u.logio.fcport,
3983 e->u.logio.data);
3984 break;
3985 case QLA_EVT_ASYNC_LOGOUT:
3986 qla2x00_async_logout(vha, e->u.logio.fcport);
3987 break;
3988 case QLA_EVT_ASYNC_LOGOUT_DONE:
3989 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3990 e->u.logio.data);
3991 break;
5ff1d584
AV		 3992 case QLA_EVT_ASYNC_ADISC:
3993 qla2x00_async_adisc(vha, e->u.logio.fcport,
3994 e->u.logio.data);
3995 break;
3996 case QLA_EVT_ASYNC_ADISC_DONE:
3997 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3998 e->u.logio.data);
3999 break;
3420d36c
AV		 4000 case QLA_EVT_UEVENT:
4001 qla2x00_uevent_emit(vha, e->u.uevent.code);
4002 break;
8ae6d9c7
GM		 4003 case QLA_EVT_AENFX:
4004 qlafx00_process_aen(vha, e);
4005 break;
0971de7f
AV		 4006 }
4007 if (e->flags & QLA_EVT_FLAG_FREE)
4008 kfree(e);
feafb7b1
AE		 4009
4010 /* For each work completed decrement vha ref count */
4011 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4012 }
e315cd28 4013}
f999f4c1 4014
e315cd28
AC		 4015/* Relogins all the fcports of a vport
4016 * Context: dpc thread
4017 */
4018void qla2x00_relogin(struct scsi_qla_host *vha)
4019{
4020 fc_port_t *fcport;
c6b2fca8 4021 int status;
e315cd28
AC		 4022 uint16_t next_loopid = 0;
4023 struct qla_hw_data *ha = vha->hw;
ac280b67 4024 uint16_t data[2];
e315cd28
AC		 4025
4026 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4027 /*
4028 * If the port is not ONLINE then try to login
4029 * to it if we haven't run out of retries.
4030 */
5ff1d584
AV		 4031 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4032 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4033 fcport->login_retry--;
e315cd28 4034 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4035 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4036 ha->isp_ops->fabric_logout(vha,
4037 fcport->loop_id,
4038 fcport->d_id.b.domain,
4039 fcport->d_id.b.area,
4040 fcport->d_id.b.al_pa);
4041
03bcfb57
JC		 4042 if (fcport->loop_id == FC_NO_LOOP_ID) {
4043 fcport->loop_id = next_loopid =
4044 ha->min_external_loopid;
4045 status = qla2x00_find_new_loop_id(
4046 vha, fcport);
4047 if (status != QLA_SUCCESS) {
4048 /* Ran out of IDs to use */
4049 break;
4050 }
4051 }
4052
ac280b67 4053 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4054 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4055 data[0] = 0;
4056 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4057 status = qla2x00_post_async_login_work(
4058 vha, fcport, data);
4059 if (status == QLA_SUCCESS)
4060 continue;
4061 /* Attempt a retry. */
4062 status = 1;
aaf4d3e2 4063 } else {
ac280b67
AV		 4064 status = qla2x00_fabric_login(vha,
4065 fcport, &next_loopid);
aaf4d3e2
SK		 4066 if (status == QLA_SUCCESS) {
4067 int status2;
4068 uint8_t opts;
4069
4070 opts = 0;
4071 if (fcport->flags &
4072 FCF_FCP2_DEVICE)
4073 opts |= BIT_1;
03003960
SK		 4074 status2 =
4075 qla2x00_get_port_database(
4076 vha, fcport, opts);
aaf4d3e2
SK		 4077 if (status2 != QLA_SUCCESS)
4078 status = 1;
4079 }
4080 }
e315cd28
AC		 4081 } else
4082 status = qla2x00_local_device_login(vha,
4083 fcport);
4084
e315cd28
AC		 4085 if (status == QLA_SUCCESS) {
4086 fcport->old_loop_id = fcport->loop_id;
4087
7c3df132
SK		 4088 ql_dbg(ql_dbg_disc, vha, 0x2003,
4089 "Port login OK: logged in ID 0x%x.\n",
4090 fcport->loop_id);
e315cd28
AC		 4091
4092 qla2x00_update_fcport(vha, fcport);
4093
4094 } else if (status == 1) {
4095 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4096 /* retry the login again */
7c3df132
SK		 4097 ql_dbg(ql_dbg_disc, vha, 0x2007,
4098 "Retrying %d login again loop_id 0x%x.\n",
4099 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4100 } else {
4101 fcport->login_retry = 0;
4102 }
4103
4104 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4105 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4106 }
4107 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4108 break;
0971de7f 4109 }
0971de7f
AV		 4110}
4111
7d613ac6
SV		 4112/* Schedule work on any of the dpc-workqueues */
4113void
4114qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4115{
4116 struct qla_hw_data *ha = base_vha->hw;
4117
4118 switch (work_code) {
4119 case MBA_IDC_AEN: /* 0x8200 */
4120 if (ha->dpc_lp_wq)
4121 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4122 break;
4123
4124 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4125 if (!ha->flags.nic_core_reset_hdlr_active) {
4126 if (ha->dpc_hp_wq)
4127 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4128 } else
4129 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4130 "NIC Core reset is already active. Skip "
4131 "scheduling it again.\n");
4132 break;
4133 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4134 if (ha->dpc_hp_wq)
4135 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4136 break;
4137 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4138 if (ha->dpc_hp_wq)
4139 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4140 break;
4141 default:
4142 ql_log(ql_log_warn, base_vha, 0xb05f,
4143 "Unknow work-code=0x%x.\n", work_code);
4144 }
4145
4146 return;
4147}
4148
4149/* Work: Perform NIC Core Unrecoverable state handling */
4150void
4151qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4152{
4153 struct qla_hw_data *ha =
2ad1b67c 4154 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4155 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4156 uint32_t dev_state = 0;
4157
4158 qla83xx_idc_lock(base_vha, 0);
4159 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4160 qla83xx_reset_ownership(base_vha);
4161 if (ha->flags.nic_core_reset_owner) {
4162 ha->flags.nic_core_reset_owner = 0;
4163 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4164 QLA8XXX_DEV_FAILED);
4165 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4166 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4167 }
4168 qla83xx_idc_unlock(base_vha, 0);
4169}
4170
4171/* Work: Execute IDC state handler */
4172void
4173qla83xx_idc_state_handler_work(struct work_struct *work)
4174{
4175 struct qla_hw_data *ha =
2ad1b67c 4176 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4177 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4178 uint32_t dev_state = 0;
4179
4180 qla83xx_idc_lock(base_vha, 0);
4181 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4182 if (dev_state == QLA8XXX_DEV_FAILED ||
4183 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4184 qla83xx_idc_state_handler(base_vha);
4185 qla83xx_idc_unlock(base_vha, 0);
4186}
4187
fa492630 4188static int
7d613ac6
SV		 4189qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4190{
4191 int rval = QLA_SUCCESS;
4192 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4193 uint32_t heart_beat_counter1, heart_beat_counter2;
4194
4195 do {
4196 if (time_after(jiffies, heart_beat_wait)) {
4197 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4198 "Nic Core f/w is not alive.\n");
4199 rval = QLA_FUNCTION_FAILED;
4200 break;
4201 }
4202
4203 qla83xx_idc_lock(base_vha, 0);
4204 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4205 &heart_beat_counter1);
4206 qla83xx_idc_unlock(base_vha, 0);
4207 msleep(100);
4208 qla83xx_idc_lock(base_vha, 0);
4209 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4210 &heart_beat_counter2);
4211 qla83xx_idc_unlock(base_vha, 0);
4212 } while (heart_beat_counter1 == heart_beat_counter2);
4213
4214 return rval;
4215}
4216
4217/* Work: Perform NIC Core Reset handling */
4218void
4219qla83xx_nic_core_reset_work(struct work_struct *work)
4220{
4221 struct qla_hw_data *ha =
4222 container_of(work, struct qla_hw_data, nic_core_reset);
4223 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4224 uint32_t dev_state = 0;
4225
81178772
SK		 4226 if (IS_QLA2031(ha)) {
4227 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4228 ql_log(ql_log_warn, base_vha, 0xb081,
4229 "Failed to dump mctp\n");
4230 return;
4231 }
4232
7d613ac6
SV		 4233 if (!ha->flags.nic_core_reset_hdlr_active) {
4234 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4235 qla83xx_idc_lock(base_vha, 0);
4236 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4237 &dev_state);
4238 qla83xx_idc_unlock(base_vha, 0);
4239 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4240 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4241 "Nic Core f/w is alive.\n");
4242 return;
4243 }
4244 }
4245
4246 ha->flags.nic_core_reset_hdlr_active = 1;
4247 if (qla83xx_nic_core_reset(base_vha)) {
4248 /* NIC Core reset failed. */
4249 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4250 "NIC Core reset failed.\n");
4251 }
4252 ha->flags.nic_core_reset_hdlr_active = 0;
4253 }
4254}
4255
4256/* Work: Handle 8200 IDC aens */
4257void
4258qla83xx_service_idc_aen(struct work_struct *work)
4259{
4260 struct qla_hw_data *ha =
4261 container_of(work, struct qla_hw_data, idc_aen);
4262 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4263 uint32_t dev_state, idc_control;
4264
4265 qla83xx_idc_lock(base_vha, 0);
4266 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4267 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4268 qla83xx_idc_unlock(base_vha, 0);
4269 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4270 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4271 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4272 "Application requested NIC Core Reset.\n");
4273 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4274 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4275 QLA_SUCCESS) {
4276 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4277 "Other protocol driver requested NIC Core Reset.\n");
4278 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4279 }
4280 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4281 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4282 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4283 }
4284}
4285
4286static void
4287qla83xx_wait_logic(void)
4288{
4289 int i;
4290
4291 /* Yield CPU */
4292 if (!in_interrupt()) {
4293 /*
4294 * Wait about 200ms before retrying again.
4295 * This controls the number of retries for single
4296 * lock operation.
4297 */
4298 msleep(100);
4299 schedule();
4300 } else {
4301 for (i = 0; i < 20; i++)
4302 cpu_relax(); /* This a nop instr on i386 */
4303 }
4304}
4305
fa492630 4306static int
7d613ac6
SV		 4307qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4308{
4309 int rval;
4310 uint32_t data;
4311 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4312 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4313 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4314 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4315 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4316
4317 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4318 if (rval)
4319 return rval;
4320
4321 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4322 return QLA_SUCCESS;
4323 } else {
4324 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4325 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4326 data);
4327 if (rval)
4328 return rval;
4329
4330 msleep(200);
4331
4332 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4333 &data);
4334 if (rval)
4335 return rval;
4336
4337 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4338 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4339 ~(idc_lck_rcvry_stage_mask));
4340 rval = qla83xx_wr_reg(base_vha,
4341 QLA83XX_IDC_LOCK_RECOVERY, data);
4342 if (rval)
4343 return rval;
4344
4345 /* Forcefully perform IDC UnLock */
4346 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4347 &data);
4348 if (rval)
4349 return rval;
4350 /* Clear lock-id by setting 0xff */
4351 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4352 0xff);
4353 if (rval)
4354 return rval;
4355 /* Clear lock-recovery by setting 0x0 */
4356 rval = qla83xx_wr_reg(base_vha,
4357 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4358 if (rval)
4359 return rval;
4360 } else
4361 return QLA_SUCCESS;
4362 }
4363
4364 return rval;
4365}
4366
fa492630 4367static int
7d613ac6
SV		 4368qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4369{
4370 int rval = QLA_SUCCESS;
4371 uint32_t o_drv_lockid, n_drv_lockid;
4372 unsigned long lock_recovery_timeout;
4373
4374 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4375retry_lockid:
4376 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4377 if (rval)
4378 goto exit;
4379
4380 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4381 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4382 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4383 return QLA_SUCCESS;
4384 else
4385 return QLA_FUNCTION_FAILED;
4386 }
4387
4388 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4389 if (rval)
4390 goto exit;
4391
4392 if (o_drv_lockid == n_drv_lockid) {
4393 qla83xx_wait_logic();
4394 goto retry_lockid;
4395 } else
4396 return QLA_SUCCESS;
4397
4398exit:
4399 return rval;
4400}
4401
4402void
4403qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4404{
4405 uint16_t options = (requester_id << 15) | BIT_6;
4406 uint32_t data;
6c315553 4407 uint32_t lock_owner;
7d613ac6
SV		 4408 struct qla_hw_data *ha = base_vha->hw;
4409
4410 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4411retry_lock:
4412 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4413 == QLA_SUCCESS) {
4414 if (data) {
4415 /* Setting lock-id to our function-number */
4416 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4417 ha->portnum);
4418 } else {
6c315553
SK		 4419 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4420 &lock_owner);
7d613ac6 4421 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4422 "Failed to acquire IDC lock, acquired by %d, "
4423 "retrying...\n", lock_owner);
7d613ac6
SV		 4424
4425 /* Retry/Perform IDC-Lock recovery */
4426 if (qla83xx_idc_lock_recovery(base_vha)
4427 == QLA_SUCCESS) {
4428 qla83xx_wait_logic();
4429 goto retry_lock;
4430 } else
4431 ql_log(ql_log_warn, base_vha, 0xb075,
4432 "IDC Lock recovery FAILED.\n");
4433 }
4434
4435 }
4436
4437 return;
4438
4439 /* XXX: IDC-lock implementation using access-control mbx */
4440retry_lock2:
4441 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4442 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4443 "Failed to acquire IDC lock. retrying...\n");
4444 /* Retry/Perform IDC-Lock recovery */
4445 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4446 qla83xx_wait_logic();
4447 goto retry_lock2;
4448 } else
4449 ql_log(ql_log_warn, base_vha, 0xb076,
4450 "IDC Lock recovery FAILED.\n");
4451 }
4452
4453 return;
4454}
4455
4456void
4457qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4458{
4459 uint16_t options = (requester_id << 15) | BIT_7, retry;
4460 uint32_t data;
4461 struct qla_hw_data *ha = base_vha->hw;
4462
4463 /* IDC-unlock implementation using driver-unlock/lock-id
4464 * remote registers
4465 */
4466 retry = 0;
4467retry_unlock:
4468 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4469 == QLA_SUCCESS) {
4470 if (data == ha->portnum) {
4471 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4472 /* Clearing lock-id by setting 0xff */
4473 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4474 } else if (retry < 10) {
4475 /* SV: XXX: IDC unlock retrying needed here? */
4476
4477 /* Retry for IDC-unlock */
4478 qla83xx_wait_logic();
4479 retry++;
4480 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4481 "Failed to release IDC lock, retyring=%d\n", retry);
4482 goto retry_unlock;
4483 }
4484 } else if (retry < 10) {
4485 /* Retry for IDC-unlock */
4486 qla83xx_wait_logic();
4487 retry++;
4488 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4489 "Failed to read drv-lockid, retyring=%d\n", retry);
4490 goto retry_unlock;
4491 }
4492
4493 return;
4494
4495 /* XXX: IDC-unlock implementation using access-control mbx */
4496 retry = 0;
4497retry_unlock2:
4498 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4499 if (retry < 10) {
4500 /* Retry for IDC-unlock */
4501 qla83xx_wait_logic();
4502 retry++;
4503 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4504 "Failed to release IDC lock, retyring=%d\n", retry);
4505 goto retry_unlock2;
4506 }
4507 }
4508
4509 return;
4510}
4511
4512int
4513__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4514{
4515 int rval = QLA_SUCCESS;
4516 struct qla_hw_data *ha = vha->hw;
4517 uint32_t drv_presence;
4518
4519 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4520 if (rval == QLA_SUCCESS) {
4521 drv_presence |= (1 << ha->portnum);
4522 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4523 drv_presence);
4524 }
4525
4526 return rval;
4527}
4528
4529int
4530qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4531{
4532 int rval = QLA_SUCCESS;
4533
4534 qla83xx_idc_lock(vha, 0);
4535 rval = __qla83xx_set_drv_presence(vha);
4536 qla83xx_idc_unlock(vha, 0);
4537
4538 return rval;
4539}
4540
4541int
4542__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4543{
4544 int rval = QLA_SUCCESS;
4545 struct qla_hw_data *ha = vha->hw;
4546 uint32_t drv_presence;
4547
4548 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4549 if (rval == QLA_SUCCESS) {
4550 drv_presence &= ~(1 << ha->portnum);
4551 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4552 drv_presence);
4553 }
4554
4555 return rval;
4556}
4557
4558int
4559qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4560{
4561 int rval = QLA_SUCCESS;
4562
4563 qla83xx_idc_lock(vha, 0);
4564 rval = __qla83xx_clear_drv_presence(vha);
4565 qla83xx_idc_unlock(vha, 0);
4566
4567 return rval;
4568}
4569
fa492630 4570static void
7d613ac6
SV		 4571qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4572{
4573 struct qla_hw_data *ha = vha->hw;
4574 uint32_t drv_ack, drv_presence;
4575 unsigned long ack_timeout;
4576
4577 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4578 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4579 while (1) {
4580 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4581 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4582 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4583 break;
4584
4585 if (time_after_eq(jiffies, ack_timeout)) {
4586 ql_log(ql_log_warn, vha, 0xb067,
4587 "RESET ACK TIMEOUT! drv_presence=0x%x "
4588 "drv_ack=0x%x\n", drv_presence, drv_ack);
4589 /*
4590 * The function(s) which did not ack in time are forced
4591 * to withdraw any further participation in the IDC
4592 * reset.
4593 */
4594 if (drv_ack != drv_presence)
4595 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4596 drv_ack);
4597 break;
4598 }
4599
4600 qla83xx_idc_unlock(vha, 0);
4601 msleep(1000);
4602 qla83xx_idc_lock(vha, 0);
4603 }
4604
4605 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4606 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4607}
4608
fa492630 4609static int
7d613ac6
SV		 4610qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4611{
4612 int rval = QLA_SUCCESS;
4613 uint32_t idc_control;
4614
4615 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4616 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4617
4618 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4619 __qla83xx_get_idc_control(vha, &idc_control);
4620 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4621 __qla83xx_set_idc_control(vha, 0);
4622
4623 qla83xx_idc_unlock(vha, 0);
4624 rval = qla83xx_restart_nic_firmware(vha);
4625 qla83xx_idc_lock(vha, 0);
4626
4627 if (rval != QLA_SUCCESS) {
4628 ql_log(ql_log_fatal, vha, 0xb06a,
4629 "Failed to restart NIC f/w.\n");
4630 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4631 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4632 } else {
4633 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4634 "Success in restarting nic f/w.\n");
4635 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4636 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4637 }
4638
4639 return rval;
4640}
4641
4642/* Assumes idc_lock always held on entry */
4643int
4644qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4645{
4646 struct qla_hw_data *ha = base_vha->hw;
4647 int rval = QLA_SUCCESS;
4648 unsigned long dev_init_timeout;
4649 uint32_t dev_state;
4650
4651 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4652 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4653
4654 while (1) {
4655
4656 if (time_after_eq(jiffies, dev_init_timeout)) {
4657 ql_log(ql_log_warn, base_vha, 0xb06e,
4658 "Initialization TIMEOUT!\n");
4659 /* Init timeout. Disable further NIC Core
4660 * communication.
4661 */
4662 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4663 QLA8XXX_DEV_FAILED);
4664 ql_log(ql_log_info, base_vha, 0xb06f,
4665 "HW State: FAILED.\n");
4666 }
4667
4668 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4669 switch (dev_state) {
4670 case QLA8XXX_DEV_READY:
4671 if (ha->flags.nic_core_reset_owner)
4672 qla83xx_idc_audit(base_vha,
4673 IDC_AUDIT_COMPLETION);
4674 ha->flags.nic_core_reset_owner = 0;
4675 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4676 "Reset_owner reset by 0x%x.\n",
4677 ha->portnum);
4678 goto exit;
4679 case QLA8XXX_DEV_COLD:
4680 if (ha->flags.nic_core_reset_owner)
4681 rval = qla83xx_device_bootstrap(base_vha);
4682 else {
4683 /* Wait for AEN to change device-state */
4684 qla83xx_idc_unlock(base_vha, 0);
4685 msleep(1000);
4686 qla83xx_idc_lock(base_vha, 0);
4687 }
4688 break;
4689 case QLA8XXX_DEV_INITIALIZING:
4690 /* Wait for AEN to change device-state */
4691 qla83xx_idc_unlock(base_vha, 0);
4692 msleep(1000);
4693 qla83xx_idc_lock(base_vha, 0);
4694 break;
4695 case QLA8XXX_DEV_NEED_RESET:
4696 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4697 qla83xx_need_reset_handler(base_vha);
4698 else {
4699 /* Wait for AEN to change device-state */
4700 qla83xx_idc_unlock(base_vha, 0);
4701 msleep(1000);
4702 qla83xx_idc_lock(base_vha, 0);
4703 }
4704 /* reset timeout value after need reset handler */
4705 dev_init_timeout = jiffies +
4706 (ha->fcoe_dev_init_timeout * HZ);
4707 break;
4708 case QLA8XXX_DEV_NEED_QUIESCENT:
4709 /* XXX: DEBUG for now */
4710 qla83xx_idc_unlock(base_vha, 0);
4711 msleep(1000);
4712 qla83xx_idc_lock(base_vha, 0);
4713 break;
4714 case QLA8XXX_DEV_QUIESCENT:
4715 /* XXX: DEBUG for now */
4716 if (ha->flags.quiesce_owner)
4717 goto exit;
4718
4719 qla83xx_idc_unlock(base_vha, 0);
4720 msleep(1000);
4721 qla83xx_idc_lock(base_vha, 0);
4722 dev_init_timeout = jiffies +
4723 (ha->fcoe_dev_init_timeout * HZ);
4724 break;
4725 case QLA8XXX_DEV_FAILED:
4726 if (ha->flags.nic_core_reset_owner)
4727 qla83xx_idc_audit(base_vha,
4728 IDC_AUDIT_COMPLETION);
4729 ha->flags.nic_core_reset_owner = 0;
4730 __qla83xx_clear_drv_presence(base_vha);
4731 qla83xx_idc_unlock(base_vha, 0);
4732 qla8xxx_dev_failed_handler(base_vha);
4733 rval = QLA_FUNCTION_FAILED;
4734 qla83xx_idc_lock(base_vha, 0);
4735 goto exit;
4736 case QLA8XXX_BAD_VALUE:
4737 qla83xx_idc_unlock(base_vha, 0);
4738 msleep(1000);
4739 qla83xx_idc_lock(base_vha, 0);
4740 break;
4741 default:
4742 ql_log(ql_log_warn, base_vha, 0xb071,
4743 "Unknow Device State: %x.\n", dev_state);
4744 qla83xx_idc_unlock(base_vha, 0);
4745 qla8xxx_dev_failed_handler(base_vha);
4746 rval = QLA_FUNCTION_FAILED;
4747 qla83xx_idc_lock(base_vha, 0);
4748 goto exit;
4749 }
4750 }
4751
4752exit:
4753 return rval;
4754}
4755
f3ddac19
CD		 4756void
4757qla2x00_disable_board_on_pci_error(struct work_struct *work)
4758{
4759 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4760 board_disable);
4761 struct pci_dev *pdev = ha->pdev;
4762 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4763
4764 ql_log(ql_log_warn, base_vha, 0x015b,
4765 "Disabling adapter.\n");
4766
4767 set_bit(UNLOADING, &base_vha->dpc_flags);
4768
4769 qla2x00_delete_all_vps(ha, base_vha);
4770
4771 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4772
4773 qla2x00_dfs_remove(base_vha);
4774
4775 qla84xx_put_chip(base_vha);
4776
4777 if (base_vha->timer_active)
4778 qla2x00_stop_timer(base_vha);
4779
4780 base_vha->flags.online = 0;
4781
4782 qla2x00_destroy_deferred_work(ha);
4783
4784 /*
4785 * Do not try to stop beacon blink as it will issue a mailbox
4786 * command.
4787 */
4788 qla2x00_free_sysfs_attr(base_vha, false);
4789
4790 fc_remove_host(base_vha->host);
4791
4792 scsi_remove_host(base_vha->host);
4793
4794 base_vha->flags.init_done = 0;
4795 qla25xx_delete_queues(base_vha);
4796 qla2x00_free_irqs(base_vha);
4797 qla2x00_free_fcports(base_vha);
4798 qla2x00_mem_free(ha);
4799 qla82xx_md_free(base_vha);
4800 qla2x00_free_queues(ha);
4801
4802 scsi_host_put(base_vha->host);
4803
4804 qla2x00_unmap_iobases(ha);
4805
4806 pci_release_selected_regions(ha->pdev, ha->bars);
4807 kfree(ha);
4808 ha = NULL;
4809
4810 pci_disable_pcie_error_reporting(pdev);
4811 pci_disable_device(pdev);
4812 pci_set_drvdata(pdev, NULL);
4813
4814}
4815
1da177e4
LT		 4816/**************************************************************************
4817* qla2x00_do_dpc
4818* This kernel thread is a task that is schedule by the interrupt handler
4819* to perform the background processing for interrupts.
4820*
4821* Notes:
4822* This task always run in the context of a kernel thread. It
4823* is kick-off by the driver's detect code and starts up
4824* up one per adapter. It immediately goes to sleep and waits for
4825* some fibre event. When either the interrupt handler or
4826* the timer routine detects a event it will one of the task
4827* bits then wake us up.
4828**************************************************************************/
4829static int
4830qla2x00_do_dpc(void *data)
4831{
2c3dfe3f 4832 int rval;
e315cd28
AC		 4833 scsi_qla_host_t *base_vha;
4834 struct qla_hw_data *ha;
1da177e4 4835
e315cd28
AC		 4836 ha = (struct qla_hw_data *)data;
4837 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4838
8698a745 4839 set_user_nice(current, MIN_NICE);
1da177e4 4840
563585ec 4841 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4842 while (!kthread_should_stop()) {
7c3df132
SK		 4843 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4844 "DPC handler sleeping.\n");
1da177e4 4845
39a11240
CH		 4846 schedule();
4847 __set_current_state(TASK_RUNNING);
1da177e4 4848
c142caf0
AV		 4849 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4850 goto end_loop;
1da177e4 4851
85880801 4852 if (ha->flags.eeh_busy) {
7c3df132
SK		 4853 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4854 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4855 goto end_loop;
85880801
AV		 4856 }
4857
1da177e4
LT		 4858 ha->dpc_active = 1;
4859
5f28d2d7
SK		 4860 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4861 "DPC handler waking up, dpc_flags=0x%lx.\n",
4862 base_vha->dpc_flags);
1da177e4 4863
e315cd28 4864 qla2x00_do_work(base_vha);
0971de7f 4865
7ec0effd
AD		 4866 if (IS_P3P_TYPE(ha)) {
4867 if (IS_QLA8044(ha)) {
4868 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4869 &base_vha->dpc_flags)) {
4870 qla8044_idc_lock(ha);
4871 qla8044_wr_direct(base_vha,
4872 QLA8044_CRB_DEV_STATE_INDEX,
4873 QLA8XXX_DEV_FAILED);
4874 qla8044_idc_unlock(ha);
4875 ql_log(ql_log_info, base_vha, 0x4004,
4876 "HW State: FAILED.\n");
4877 qla8044_device_state_handler(base_vha);
4878 continue;
4879 }
4880
4881 } else {
4882 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4883 &base_vha->dpc_flags)) {
4884 qla82xx_idc_lock(ha);
4885 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4886 QLA8XXX_DEV_FAILED);
4887 qla82xx_idc_unlock(ha);
4888 ql_log(ql_log_info, base_vha, 0x0151,
4889 "HW State: FAILED.\n");
4890 qla82xx_device_state_handler(base_vha);
4891 continue;
4892 }
a9083016
GM		 4893 }
4894
4895 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4896 &base_vha->dpc_flags)) {
4897
7c3df132
SK		 4898 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4899 "FCoE context reset scheduled.\n");
a9083016
GM		 4900 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4901 &base_vha->dpc_flags))) {
4902 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4903 /* FCoE-ctx reset failed.
4904 * Escalate to chip-reset
4905 */
4906 set_bit(ISP_ABORT_NEEDED,
4907 &base_vha->dpc_flags);
4908 }
4909 clear_bit(ABORT_ISP_ACTIVE,
4910 &base_vha->dpc_flags);
4911 }
4912
7c3df132
SK		 4913 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4914 "FCoE context reset end.\n");
a9083016 4915 }
8ae6d9c7
GM		 4916 } else if (IS_QLAFX00(ha)) {
4917 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4918 &base_vha->dpc_flags)) {
4919 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4920 "Firmware Reset Recovery\n");
4921 if (qlafx00_reset_initialize(base_vha)) {
4922 /* Failed. Abort isp later. */
4923 if (!test_bit(UNLOADING,
f92f82d6 4924 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4925 set_bit(ISP_UNRECOVERABLE,
4926 &base_vha->dpc_flags);
4927 ql_dbg(ql_dbg_dpc, base_vha,
4928 0x4021,
4929 "Reset Recovery Failed\n");
f92f82d6 4930 }
8ae6d9c7
GM		 4931 }
4932 }
4933
4934 if (test_and_clear_bit(FX00_TARGET_SCAN,
4935 &base_vha->dpc_flags)) {
4936 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4937 "ISPFx00 Target Scan scheduled\n");
4938 if (qlafx00_rescan_isp(base_vha)) {
4939 if (!test_bit(UNLOADING,
4940 &base_vha->dpc_flags))
4941 set_bit(ISP_UNRECOVERABLE,
4942 &base_vha->dpc_flags);
4943 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4944 "ISPFx00 Target Scan Failed\n");
4945 }
4946 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4947 "ISPFx00 Target Scan End\n");
4948 }
e8f5e95d
AB		 4949 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4950 &base_vha->dpc_flags)) {
4951 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4952 "ISPFx00 Host Info resend scheduled\n");
4953 qlafx00_fx_disc(base_vha,
4954 &base_vha->hw->mr.fcport,
4955 FXDISC_REG_HOST_INFO);
4956 }
a9083016
GM		 4957 }
4958
e315cd28
AC		 4959 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4960 &base_vha->dpc_flags)) {
1da177e4 4961
7c3df132
SK		 4962 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4963 "ISP abort scheduled.\n");
1da177e4 4964 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4965 &base_vha->dpc_flags))) {
1da177e4 4966
a9083016 4967 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4968 /* failed. retry later */
4969 set_bit(ISP_ABORT_NEEDED,
e315cd28 4970 &base_vha->dpc_flags);
99363ef8 4971 }
e315cd28
AC		 4972 clear_bit(ABORT_ISP_ACTIVE,
4973 &base_vha->dpc_flags);
99363ef8
SJ		 4974 }
4975
7c3df132
SK		 4976 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4977 "ISP abort end.\n");
1da177e4
LT		 4978 }
4979
a394aac8
DJ		 4980 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4981 &base_vha->dpc_flags)) {
e315cd28 4982 qla2x00_update_fcports(base_vha);
c9c5ced9 4983 }
d97994dc 4984
2d70c103
NB		 4985 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4986 int ret;
4987 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4988 if (ret != QLA_SUCCESS)
4989 ql_log(ql_log_warn, base_vha, 0x121,
4990 "Failed to enable receiving of RSCN "
4991 "requests: 0x%x.\n", ret);
4992 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4993 }
4994
8ae6d9c7
GM		 4995 if (IS_QLAFX00(ha))
4996 goto loop_resync_check;
4997
579d12b5 4998 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4999 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5000 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5001 if (IS_P3P_TYPE(ha)) {
5002 if (IS_QLA82XX(ha))
5003 qla82xx_device_state_handler(base_vha);
5004 if (IS_QLA8044(ha))
5005 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5006 clear_bit(ISP_QUIESCE_NEEDED,
5007 &base_vha->dpc_flags);
5008 if (!ha->flags.quiesce_owner) {
5009 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5010 if (IS_QLA82XX(ha)) {
5011 qla82xx_idc_lock(ha);
5012 qla82xx_clear_qsnt_ready(
5013 base_vha);
5014 qla82xx_idc_unlock(ha);
5015 } else if (IS_QLA8044(ha)) {
5016 qla8044_idc_lock(ha);
5017 qla8044_clear_qsnt_ready(
5018 base_vha);
5019 qla8044_idc_unlock(ha);
5020 }
8fcd6b8b
CD		 5021 }
5022 } else {
5023 clear_bit(ISP_QUIESCE_NEEDED,
5024 &base_vha->dpc_flags);
5025 qla2x00_quiesce_io(base_vha);
579d12b5 5026 }
7c3df132
SK		 5027 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5028 "Quiescence mode end.\n");
579d12b5
SK		 5029 }
5030
e315cd28 5031 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5032 &base_vha->dpc_flags) &&
e315cd28 5033 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5034
7c3df132
SK		 5035 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5036 "Reset marker scheduled.\n");
e315cd28
AC		 5037 qla2x00_rst_aen(base_vha);
5038 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5039 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5040 "Reset marker end.\n");
1da177e4
LT		 5041 }
5042
5043 /* Retry each device up to login retry count */
e315cd28
AC		 5044 if ((test_and_clear_bit(RELOGIN_NEEDED,
5045 &base_vha->dpc_flags)) &&
5046 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5047 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5048
7c3df132
SK		 5049 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5050 "Relogin scheduled.\n");
e315cd28 5051 qla2x00_relogin(base_vha);
7c3df132
SK		 5052 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5053 "Relogin end.\n");
1da177e4 5054 }
8ae6d9c7 5055loop_resync_check:
e315cd28 5056 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5057 &base_vha->dpc_flags)) {
1da177e4 5058
7c3df132
SK		 5059 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5060 "Loop resync scheduled.\n");
1da177e4
LT		 5061
5062 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5063 &base_vha->dpc_flags))) {
1da177e4 5064
e315cd28 5065 rval = qla2x00_loop_resync(base_vha);
1da177e4 5066
e315cd28
AC		 5067 clear_bit(LOOP_RESYNC_ACTIVE,
5068 &base_vha->dpc_flags);
1da177e4
LT		 5069 }
5070
7c3df132
SK		 5071 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5072 "Loop resync end.\n");
1da177e4
LT		 5073 }
5074
8ae6d9c7
GM		 5075 if (IS_QLAFX00(ha))
5076 goto intr_on_check;
5077
e315cd28
AC		 5078 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5079 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5080 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5081 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5082 }
5083
8ae6d9c7 5084intr_on_check:
1da177e4 5085 if (!ha->interrupts_on)
fd34f556 5086 ha->isp_ops->enable_intrs(ha);
1da177e4 5087
e315cd28 5088 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5089 &base_vha->dpc_flags)) {
5090 if (ha->beacon_blink_led == 1)
5091 ha->isp_ops->beacon_blink(base_vha);
5092 }
f6df144c 5093
8ae6d9c7
GM		 5094 if (!IS_QLAFX00(ha))
5095 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5096
1da177e4 5097 ha->dpc_active = 0;
c142caf0 5098end_loop:
563585ec 5099 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5100 } /* End of while(1) */
563585ec 5101 __set_current_state(TASK_RUNNING);
1da177e4 5102
7c3df132
SK		 5103 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5104 "DPC handler exiting.\n");
1da177e4
LT		 5105
5106 /*
5107 * Make sure that nobody tries to wake us up again.
5108 */
1da177e4
LT		 5109 ha->dpc_active = 0;
5110
ac280b67
AV		 5111 /* Cleanup any residual CTX SRBs. */
5112 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5113
39a11240
CH		 5114 return 0;
5115}
5116
5117void
e315cd28 5118qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5119{
e315cd28 5120 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5121 struct task_struct *t = ha->dpc_thread;
5122
e315cd28 5123 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5124 wake_up_process(t);
1da177e4
LT		 5125}
5126
1da177e4
LT		 5127/*
5128* qla2x00_rst_aen
5129* Processes asynchronous reset.
5130*
5131* Input:
5132* ha = adapter block pointer.
5133*/
5134static void
e315cd28 5135qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5136{
e315cd28
AC		 5137 if (vha->flags.online && !vha->flags.reset_active &&
5138 !atomic_read(&vha->loop_down_timer) &&
5139 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5140 do {
e315cd28 5141 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5142
5143 /*
5144 * Issue marker command only when we are going to start
5145 * the I/O.
5146 */
e315cd28
AC		 5147 vha->marker_needed = 1;
5148 } while (!atomic_read(&vha->loop_down_timer) &&
5149 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5150 }
5151}
5152
1da177e4
LT		 5153/**************************************************************************
5154* qla2x00_timer
5155*
5156* Description:
5157* One second timer
5158*
5159* Context: Interrupt
5160***************************************************************************/
2c3dfe3f 5161void
e315cd28 5162qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5163{
1da177e4 5164 unsigned long cpu_flags = 0;
1da177e4
LT		 5165 int start_dpc = 0;
5166 int index;
5167 srb_t *sp;
85880801 5168 uint16_t w;
e315cd28 5169 struct qla_hw_data *ha = vha->hw;
73208dfd 5170 struct req_que *req;
85880801 5171
a5b36321 5172 if (ha->flags.eeh_busy) {
7c3df132
SK		 5173 ql_dbg(ql_dbg_timer, vha, 0x6000,
5174 "EEH = %d, restarting timer.\n",
5175 ha->flags.eeh_busy);
a5b36321
LC		 5176 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5177 return;
5178 }
5179
f3ddac19
CD		 5180 /*
5181 * Hardware read to raise pending EEH errors during mailbox waits. If
5182 * the read returns -1 then disable the board.
5183 */
5184 if (!pci_channel_offline(ha->pdev)) {
85880801 5185 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5186 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5187 }
1da177e4 5188
cefcaba6 5189 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5190 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5191 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5192 start_dpc++;
7ec0effd
AD		 5193 if (IS_QLA82XX(ha))
5194 qla82xx_watchdog(vha);
5195 else if (IS_QLA8044(ha))
5196 qla8044_watchdog(vha);
579d12b5
SK		 5197 }
5198
8ae6d9c7
GM		 5199 if (!vha->vp_idx && IS_QLAFX00(ha))
5200 qlafx00_timer_routine(vha);
5201
1da177e4 5202 /* Loop down handler. */
e315cd28 5203 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5204 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5205 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5206 && vha->flags.online) {
1da177e4 5207
e315cd28
AC		 5208 if (atomic_read(&vha->loop_down_timer) ==
5209 vha->loop_down_abort_time) {
1da177e4 5210
7c3df132
SK		 5211 ql_log(ql_log_info, vha, 0x6008,
5212 "Loop down - aborting the queues before time expires.\n");
1da177e4 5213
e315cd28
AC		 5214 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5215 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5216
f08b7251
AV		 5217 /*
5218 * Schedule an ISP abort to return any FCP2-device
5219 * commands.
5220 */
2c3dfe3f 5221 /* NPIV - scan physical port only */
e315cd28 5222 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5223 spin_lock_irqsave(&ha->hardware_lock,
5224 cpu_flags);
73208dfd 5225 req = ha->req_q_map[0];
2c3dfe3f 5226 for (index = 1;
8d93f550 5227 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5228 index++) {
5229 fc_port_t *sfcp;
5230
e315cd28 5231 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5232 if (!sp)
5233 continue;
9ba56b95 5234 if (sp->type != SRB_SCSI_CMD)
cf53b069 5235 continue;
2c3dfe3f 5236 sfcp = sp->fcport;
f08b7251 5237 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5238 continue;
bdf79621 5239
8f7daead
GM		 5240 if (IS_QLA82XX(ha))
5241 set_bit(FCOE_CTX_RESET_NEEDED,
5242 &vha->dpc_flags);
5243 else
5244 set_bit(ISP_ABORT_NEEDED,
e315cd28 5245 &vha->dpc_flags);
2c3dfe3f
SJ		 5246 break;
5247 }
5248 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5249 cpu_flags);
1da177e4 5250 }
1da177e4
LT		 5251 start_dpc++;
5252 }
5253
5254 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5255 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5256 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5257 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5258 "Loop down - aborting ISP.\n");
5259
8f7daead
GM		 5260 if (IS_QLA82XX(ha))
5261 set_bit(FCOE_CTX_RESET_NEEDED,
5262 &vha->dpc_flags);
5263 else
5264 set_bit(ISP_ABORT_NEEDED,
5265 &vha->dpc_flags);
1da177e4
LT		 5266 }
5267 }
7c3df132
SK		 5268 ql_dbg(ql_dbg_timer, vha, 0x600a,
5269 "Loop down - seconds remaining %d.\n",
5270 atomic_read(&vha->loop_down_timer));
1da177e4 5271 }
cefcaba6
SK		 5272 /* Check if beacon LED needs to be blinked for physical host only */
5273 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5274 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5275 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5276 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5277 start_dpc++;
5278 }
f6df144c
AV		 5279 }
5280
550bf57d 5281 /* Process any deferred work. */
e315cd28 5282 if (!list_empty(&vha->work_list))
550bf57d
AV		 5283 start_dpc++;
5284
1da177e4 5285 /* Schedule the DPC routine if needed */
e315cd28
AC		 5286 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5287 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5288 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5289 start_dpc ||
e315cd28
AC		 5290 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5291 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5292 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5293 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5294 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5295 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5296 ql_dbg(ql_dbg_timer, vha, 0x600b,
5297 "isp_abort_needed=%d loop_resync_needed=%d "
5298 "fcport_update_needed=%d start_dpc=%d "
5299 "reset_marker_needed=%d",
5300 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5301 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5302 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5303 start_dpc,
5304 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5305 ql_dbg(ql_dbg_timer, vha, 0x600c,
5306 "beacon_blink_needed=%d isp_unrecoverable=%d "
5307 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5308 "relogin_needed=%d.\n",
7c3df132
SK		 5309 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5310 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5311 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5312 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5313 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5314 qla2xxx_wake_dpc(vha);
7c3df132 5315 }
1da177e4 5316
e315cd28 5317 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5318}
5319
5433383e
AV		 5320/* Firmware interface routines. */
5321
f73cb695 5322#define FW_BLOBS 11
5433383e
AV		 5323#define FW_ISP21XX 0
5324#define FW_ISP22XX 1
5325#define FW_ISP2300 2
5326#define FW_ISP2322 3
48c02fde 5327#define FW_ISP24XX 4
c3a2f0df 5328#define FW_ISP25XX 5
3a03eb79 5329#define FW_ISP81XX 6
a9083016 5330#define FW_ISP82XX 7
6246b8a1
GM		 5331#define FW_ISP2031 8
5332#define FW_ISP8031 9
2c5bbbb2 5333#define FW_ISP27XX 10
5433383e 5334
bb8ee499
AV		 5335#define FW_FILE_ISP21XX "ql2100_fw.bin"
5336#define FW_FILE_ISP22XX "ql2200_fw.bin"
5337#define FW_FILE_ISP2300 "ql2300_fw.bin"
5338#define FW_FILE_ISP2322 "ql2322_fw.bin"
5339#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5340#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5341#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5342#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5343#define FW_FILE_ISP2031 "ql2600_fw.bin"
5344#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5345#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5346
bb8ee499 5347
e1e82b6f 5348static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5349
5350static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5351 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5352 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5353 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5354 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5355 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5356 { .name = FW_FILE_ISP25XX, },
3a03eb79 5357 { .name = FW_FILE_ISP81XX, },
a9083016 5358 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5359 { .name = FW_FILE_ISP2031, },
5360 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5361 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5362};
5363
5364struct fw_blob *
e315cd28 5365qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5366{
e315cd28 5367 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5368 struct fw_blob *blob;
5369
5433383e
AV		 5370 if (IS_QLA2100(ha)) {
5371 blob = &qla_fw_blobs[FW_ISP21XX];
5372 } else if (IS_QLA2200(ha)) {
5373 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5374 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5375 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5376 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5377 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5378 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5379 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5380 } else if (IS_QLA25XX(ha)) {
5381 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5382 } else if (IS_QLA81XX(ha)) {
5383 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5384 } else if (IS_QLA82XX(ha)) {
5385 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5386 } else if (IS_QLA2031(ha)) {
5387 blob = &qla_fw_blobs[FW_ISP2031];
5388 } else if (IS_QLA8031(ha)) {
5389 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5390 } else if (IS_QLA27XX(ha)) {
5391 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5392 } else {
5393 return NULL;
5433383e
AV		 5394 }
5395
e1e82b6f 5396 mutex_lock(&qla_fw_lock);
5433383e
AV		 5397 if (blob->fw)
5398 goto out;
5399
5400 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5401 ql_log(ql_log_warn, vha, 0x0063,
5402 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5403 blob->fw = NULL;
5404 blob = NULL;
5405 goto out;
5406 }
5407
5408out:
e1e82b6f 5409 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5410 return blob;
5411}
5412
5413static void
5414qla2x00_release_firmware(void)
5415{
5416 int idx;
5417
e1e82b6f 5418 mutex_lock(&qla_fw_lock);
5433383e 5419 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5420 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5421 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5422}
5423
14e660e6
SJ		 5424static pci_ers_result_t
5425qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5426{
85880801
AV		 5427 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5428 struct qla_hw_data *ha = vha->hw;
5429
7c3df132
SK		 5430 ql_dbg(ql_dbg_aer, vha, 0x9000,
5431 "PCI error detected, state %x.\n", state);
b9b12f73 5432
14e660e6
SJ		 5433 switch (state) {
5434 case pci_channel_io_normal:
85880801 5435 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5436 return PCI_ERS_RESULT_CAN_RECOVER;
5437 case pci_channel_io_frozen:
85880801 5438 ha->flags.eeh_busy = 1;
a5b36321
LC		 5439 /* For ISP82XX complete any pending mailbox cmd */
5440 if (IS_QLA82XX(ha)) {
7190575f 5441 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5442 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5443 qla82xx_clear_pending_mbx(vha);
a5b36321 5444 }
90a86fc0 5445 qla2x00_free_irqs(vha);
14e660e6 5446 pci_disable_device(pdev);
bddd2d65
LC		 5447 /* Return back all IOs */
5448 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5449 return PCI_ERS_RESULT_NEED_RESET;
5450 case pci_channel_io_perm_failure:
85880801
AV		 5451 ha->flags.pci_channel_io_perm_failure = 1;
5452 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5453 return PCI_ERS_RESULT_DISCONNECT;
5454 }
5455 return PCI_ERS_RESULT_NEED_RESET;
5456}
5457
5458static pci_ers_result_t
5459qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5460{
5461 int risc_paused = 0;
5462 uint32_t stat;
5463 unsigned long flags;
e315cd28
AC		 5464 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5465 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5466 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5467 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5468
bcc5b6d3
SK		 5469 if (IS_QLA82XX(ha))
5470 return PCI_ERS_RESULT_RECOVERED;
5471
14e660e6
SJ		 5472 spin_lock_irqsave(&ha->hardware_lock, flags);
5473 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5474 stat = RD_REG_DWORD(&reg->hccr);
5475 if (stat & HCCR_RISC_PAUSE)
5476 risc_paused = 1;
5477 } else if (IS_QLA23XX(ha)) {
5478 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5479 if (stat & HSR_RISC_PAUSED)
5480 risc_paused = 1;
5481 } else if (IS_FWI2_CAPABLE(ha)) {
5482 stat = RD_REG_DWORD(&reg24->host_status);
5483 if (stat & HSRX_RISC_PAUSED)
5484 risc_paused = 1;
5485 }
5486 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5487
5488 if (risc_paused) {
7c3df132
SK		 5489 ql_log(ql_log_info, base_vha, 0x9003,
5490 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5491 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5492
5493 return PCI_ERS_RESULT_NEED_RESET;
5494 } else
5495 return PCI_ERS_RESULT_RECOVERED;
5496}
5497
fa492630
SK		 5498static uint32_t
5499qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5500{
5501 uint32_t rval = QLA_FUNCTION_FAILED;
5502 uint32_t drv_active = 0;
5503 struct qla_hw_data *ha = base_vha->hw;
5504 int fn;
5505 struct pci_dev *other_pdev = NULL;
5506
7c3df132
SK		 5507 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5508 "Entered %s.\n", __func__);
a5b36321
LC		 5509
5510 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5511
5512 if (base_vha->flags.online) {
5513 /* Abort all outstanding commands,
5514 * so as to be requeued later */
5515 qla2x00_abort_isp_cleanup(base_vha);
5516 }
5517
5518
5519 fn = PCI_FUNC(ha->pdev->devfn);
5520 while (fn > 0) {
5521 fn--;
7c3df132
SK		 5522 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5523 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5524 other_pdev =
5525 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5526 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5527 fn));
5528
5529 if (!other_pdev)
5530 continue;
5531 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5532 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5533 "Found PCI func available and enable at 0x%x.\n",
5534 fn);
a5b36321
LC		 5535 pci_dev_put(other_pdev);
5536 break;
5537 }
5538 pci_dev_put(other_pdev);
5539 }
5540
5541 if (!fn) {
5542 /* Reset owner */
7c3df132
SK		 5543 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5544 "This devfn is reset owner = 0x%x.\n",
5545 ha->pdev->devfn);
a5b36321
LC		 5546 qla82xx_idc_lock(ha);
5547
5548 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5549 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5550
5551 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5552 QLA82XX_IDC_VERSION);
5553
5554 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5555 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5556 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5557
5558 qla82xx_idc_unlock(ha);
5559 /* Reset if device is not already reset
5560 * drv_active would be 0 if a reset has already been done
5561 */
5562 if (drv_active)
5563 rval = qla82xx_start_firmware(base_vha);
5564 else
5565 rval = QLA_SUCCESS;
5566 qla82xx_idc_lock(ha);
5567
5568 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5569 ql_log(ql_log_info, base_vha, 0x900b,
5570 "HW State: FAILED.\n");
a5b36321
LC		 5571 qla82xx_clear_drv_active(ha);
5572 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5573 QLA8XXX_DEV_FAILED);
a5b36321 5574 } else {
7c3df132
SK		 5575 ql_log(ql_log_info, base_vha, 0x900c,
5576 "HW State: READY.\n");
a5b36321 5577 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5578 QLA8XXX_DEV_READY);
a5b36321 5579 qla82xx_idc_unlock(ha);
7190575f 5580 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5581 rval = qla82xx_restart_isp(base_vha);
5582 qla82xx_idc_lock(ha);
5583 /* Clear driver state register */
5584 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5585 qla82xx_set_drv_active(base_vha);
5586 }
5587 qla82xx_idc_unlock(ha);
5588 } else {
7c3df132
SK		 5589 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5590 "This devfn is not reset owner = 0x%x.\n",
5591 ha->pdev->devfn);
a5b36321 5592 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5593 QLA8XXX_DEV_READY)) {
7190575f 5594 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5595 rval = qla82xx_restart_isp(base_vha);
5596 qla82xx_idc_lock(ha);
5597 qla82xx_set_drv_active(base_vha);
5598 qla82xx_idc_unlock(ha);
5599 }
5600 }
5601 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5602
5603 return rval;
5604}
5605
14e660e6
SJ		 5606static pci_ers_result_t
5607qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5608{
5609 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5610 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5611 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5612 struct rsp_que *rsp;
5613 int rc, retries = 10;
09483916 5614
7c3df132
SK		 5615 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5616 "Slot Reset.\n");
85880801 5617
90a86fc0
JC		 5618 /* Workaround: qla2xxx driver which access hardware earlier
5619 * needs error state to be pci_channel_io_online.
5620 * Otherwise mailbox command timesout.
5621 */
5622 pdev->error_state = pci_channel_io_normal;
5623
5624 pci_restore_state(pdev);
5625
8c1496bd
RL		 5626 /* pci_restore_state() clears the saved_state flag of the device
5627 * save restored state which resets saved_state flag
5628 */
5629 pci_save_state(pdev);
5630
09483916
BH		 5631 if (ha->mem_only)
5632 rc = pci_enable_device_mem(pdev);
5633 else
5634 rc = pci_enable_device(pdev);
14e660e6 5635
09483916 5636 if (rc) {
7c3df132 5637 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5638 "Can't re-enable PCI device after reset.\n");
a5b36321 5639 goto exit_slot_reset;
14e660e6 5640 }
14e660e6 5641
90a86fc0
JC		 5642 rsp = ha->rsp_q_map[0];
5643 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5644 goto exit_slot_reset;
90a86fc0 5645
e315cd28 5646 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5647 goto exit_slot_reset;
5648
5649 if (IS_QLA82XX(ha)) {
5650 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5651 ret = PCI_ERS_RESULT_RECOVERED;
5652 goto exit_slot_reset;
5653 } else
5654 goto exit_slot_reset;
5655 }
14e660e6 5656
90a86fc0
JC		 5657 while (ha->flags.mbox_busy && retries--)
5658 msleep(1000);
85880801 5659
e315cd28 5660 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5661 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5662 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5663 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5664
90a86fc0 5665
a5b36321 5666exit_slot_reset:
7c3df132
SK		 5667 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5668 "slot_reset return %x.\n", ret);
85880801 5669
14e660e6
SJ		 5670 return ret;
5671}
5672
5673static void
5674qla2xxx_pci_resume(struct pci_dev *pdev)
5675{
e315cd28
AC		 5676 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5677 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5678 int ret;
5679
7c3df132
SK		 5680 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5681 "pci_resume.\n");
85880801 5682
e315cd28 5683 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5684 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5685 ql_log(ql_log_fatal, base_vha, 0x9002,
5686 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5687 }
85880801 5688
3e46f031
LC		 5689 pci_cleanup_aer_uncorrect_error_status(pdev);
5690
85880801 5691 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5692}
5693
a55b2d21 5694static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5695 .error_detected = qla2xxx_pci_error_detected,
5696 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5697 .slot_reset = qla2xxx_pci_slot_reset,
5698 .resume = qla2xxx_pci_resume,
5699};
5700
5433383e 5701static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5702 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5703 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5704 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5705 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5706 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5707 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5708 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5709 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5710 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5711 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5723 { 0 },
5724};
5725MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5726
fca29703 5727static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5728 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5729 .driver = {
5730 .owner = THIS_MODULE,
5731 },
fca29703 5732 .id_table = qla2xxx_pci_tbl,
7ee61397 5733 .probe = qla2x00_probe_one,
4c993f76 5734 .remove = qla2x00_remove_one,
e30d1756 5735 .shutdown = qla2x00_shutdown,
14e660e6 5736 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5737};
5738
75ef9de1 5739static const struct file_operations apidev_fops = {
6a03b4cd 5740 .owner = THIS_MODULE,
6038f373 5741 .llseek = noop_llseek,
6a03b4cd
HZ		 5742};
5743
1da177e4
LT		 5744/**
5745 * qla2x00_module_init - Module initialization.
5746 **/
5747static int __init
5748qla2x00_module_init(void)
5749{
fca29703
AV		 5750 int ret = 0;
5751
1da177e4 5752 /* Allocate cache for SRBs. */
354d6b21 5753 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5754 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5755 if (srb_cachep == NULL) {
7c3df132
SK		 5756 ql_log(ql_log_fatal, NULL, 0x0001,
5757 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5758 return -ENOMEM;
5759 }
5760
2d70c103
NB		 5761 /* Initialize target kmem_cache and mem_pools */
5762 ret = qlt_init();
5763 if (ret < 0) {
5764 kmem_cache_destroy(srb_cachep);
5765 return ret;
5766 } else if (ret > 0) {
5767 /*
5768 * If initiator mode is explictly disabled by qlt_init(),
5769 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5770 * performing scsi_scan_target() during LOOP UP event.
5771 */
5772 qla2xxx_transport_functions.disable_target_scan = 1;
5773 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5774 }
5775
1da177e4
LT		 5776 /* Derive version string. */
5777 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5778 if (ql2xextended_error_logging)
0181944f
AV		 5779 strcat(qla2x00_version_str, "-debug");
5780
1c97a12a
AV		 5781 qla2xxx_transport_template =
5782 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5783 if (!qla2xxx_transport_template) {
5784 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5785 ql_log(ql_log_fatal, NULL, 0x0002,
5786 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5787 qlt_exit();
1da177e4 5788 return -ENODEV;
2c3dfe3f 5789 }
6a03b4cd
HZ		 5790
5791 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5792 if (apidev_major < 0) {
7c3df132
SK		 5793 ql_log(ql_log_fatal, NULL, 0x0003,
5794 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5795 }
5796
2c3dfe3f
SJ		 5797 qla2xxx_transport_vport_template =
5798 fc_attach_transport(&qla2xxx_transport_vport_functions);
5799 if (!qla2xxx_transport_vport_template) {
5800 kmem_cache_destroy(srb_cachep);
2d70c103 5801 qlt_exit();
2c3dfe3f 5802 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5803 ql_log(ql_log_fatal, NULL, 0x0004,
5804 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5805 return -ENODEV;
2c3dfe3f 5806 }
7c3df132
SK		 5807 ql_log(ql_log_info, NULL, 0x0005,
5808 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5809 qla2x00_version_str);
7ee61397 5810 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5811 if (ret) {
5812 kmem_cache_destroy(srb_cachep);
2d70c103 5813 qlt_exit();
fca29703 5814 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5815 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5816 ql_log(ql_log_fatal, NULL, 0x0006,
5817 "pci_register_driver failed...ret=%d Failing load!.\n",
5818 ret);
fca29703
AV		 5819 }
5820 return ret;
1da177e4
LT		 5821}
5822
5823/**
5824 * qla2x00_module_exit - Module cleanup.
5825 **/
5826static void __exit
5827qla2x00_module_exit(void)
5828{
6a03b4cd 5829 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5830 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5831 qla2x00_release_firmware();
354d6b21 5832 kmem_cache_destroy(srb_cachep);
2d70c103 5833 qlt_exit();
a9083016
GM		 5834 if (ctx_cachep)
5835 kmem_cache_destroy(ctx_cachep);
1da177e4 5836 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5837 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5838}
5839
5840module_init(qla2x00_module_init);
5841module_exit(qla2x00_module_exit);
5842
5843MODULE_AUTHOR("QLogic Corporation");
5844MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5845MODULE_LICENSE("GPL");
5846MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5847MODULE_FIRMWARE(FW_FILE_ISP21XX);
5848MODULE_FIRMWARE(FW_FILE_ISP22XX);
5849MODULE_FIRMWARE(FW_FILE_ISP2300);
5850MODULE_FIRMWARE(FW_FILE_ISP2322);
5851MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5852MODULE_FIRMWARE(FW_FILE_ISP25XX);
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