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qla2xxx: Enable diagnostic port using NVRAM parameters.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
de187df8 108module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002 122MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 123 " Enable T10-CRC-DIF:\n"
124 " Default is 2.\n"
125 " 0 -- No DIF Support\n"
126 " 1 -- Enable DIF for all types\n"
127 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 128
8cb2049c 129int ql2xenablehba_err_chk = 2;
bad75002
AE		 130module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
131MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 132 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 133 " Default is 2.\n"
8cb2049c
AE		 134 " 0 -- Error isolation disabled\n"
135 " 1 -- Error isolation enabled only for DIX Type 0\n"
136 " 2 -- Error isolation enabled for all Types\n");
bad75002 137
e5896bd5 138int ql2xiidmaenable=1;
f2019cb1 139module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 140MODULE_PARM_DESC(ql2xiidmaenable,
141 "Enables iIDMA settings "
142 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
143
73208dfd 144int ql2xmaxqueues = 1;
f2019cb1 145module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 146MODULE_PARM_DESC(ql2xmaxqueues,
147 "Enables MQ settings "
ae68230c
JP		 148 "Default is 1 for single queue. Set it to number "
149 "of queues in MQ mode.");
68ca949c
AC		 150
151int ql2xmultique_tag;
f2019cb1 152module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 153MODULE_PARM_DESC(ql2xmultique_tag,
154 "Enables CPU affinity settings for the driver "
155 "Default is 0 for no affinity of request and response IO. "
156 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 157
158int ql2xfwloadbin;
86e45bf6 159module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 160MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 161 "Option to specify location from which to load ISP firmware:.\n"
162 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 163 " interface.\n"
164 " 1 -- load firmware from flash.\n"
165 " 0 -- use default semantics.\n");
166
ae97c91e 167int ql2xetsenable;
f2019cb1 168module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 169MODULE_PARM_DESC(ql2xetsenable,
170 "Enables firmware ETS burst."
171 "Default is 0 - skip ETS enablement.");
172
6907869d 173int ql2xdbwr = 1;
86e45bf6 174module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 175MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 176 "Option to specify scheme for request queue posting.\n"
177 " 0 -- Regular doorbell.\n"
178 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 179
f4c496c1 180int ql2xtargetreset = 1;
f2019cb1 181module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 182MODULE_PARM_DESC(ql2xtargetreset,
183 "Enable target reset."
184 "Default is 1 - use hw defaults.");
185
4da26e16 186int ql2xgffidenable;
f2019cb1 187module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 188MODULE_PARM_DESC(ql2xgffidenable,
189 "Enables GFF_ID checks of port type. "
190 "Default is 0 - Do not use GFF_ID information.");
a9083016 191
3822263e 192int ql2xasynctmfenable;
f2019cb1 193module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 194MODULE_PARM_DESC(ql2xasynctmfenable,
195 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
196 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 197
198int ql2xdontresethba;
86e45bf6 199module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 200MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 201 "Option to specify reset behaviour.\n"
202 " 0 (Default) -- Reset on failure.\n"
203 " 1 -- Do not reset on failure.\n");
ed0de87c 204
1abf635d
HR		 205uint64_t ql2xmaxlun = MAX_LUNS;
206module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 207MODULE_PARM_DESC(ql2xmaxlun,
208 "Defines the maximum LU number to register with the SCSI "
209 "midlayer. Default is 65535.");
210
08de2844
GM		 211int ql2xmdcapmask = 0x1F;
212module_param(ql2xmdcapmask, int, S_IRUGO);
213MODULE_PARM_DESC(ql2xmdcapmask,
214 "Set the Minidump driver capture mask level. "
6e96fa7b 215 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 216
3aadff35 217int ql2xmdenable = 1;
08de2844
GM		 218module_param(ql2xmdenable, int, S_IRUGO);
219MODULE_PARM_DESC(ql2xmdenable,
220 "Enable/disable MiniDump. "
3aadff35
GM		 221 "0 - MiniDump disabled. "
222 "1 (Default) - MiniDump enabled.");
08de2844 223
1da177e4 224/*
fa2a1ce5 225 * SCSI host template entry points
1da177e4
LT		 226 */
227static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 228static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 229static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
230static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 231static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 232static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 233static int qla2xxx_eh_abort(struct scsi_cmnd *);
234static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 235static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 236static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
237static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 238
e881a172 239static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 240static int qla2x00_change_queue_type(struct scsi_device *, int);
1a2fbf18 241static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 242static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 243
a5326f86 244struct scsi_host_template qla2xxx_driver_template = {
1da177e4 245 .module = THIS_MODULE,
cb63067a 246 .name = QLA2XXX_DRIVER_NAME,
a5326f86 247 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 248
249 .eh_abort_handler = qla2xxx_eh_abort,
250 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 251 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 252 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
253 .eh_host_reset_handler = qla2xxx_eh_host_reset,
254
255 .slave_configure = qla2xxx_slave_configure,
256
257 .slave_alloc = qla2xxx_slave_alloc,
258 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 259 .scan_finished = qla2xxx_scan_finished,
260 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 261 .change_queue_depth = qla2x00_change_queue_depth,
262 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 263 .this_id = -1,
264 .cmd_per_lun = 3,
265 .use_clustering = ENABLE_CLUSTERING,
266 .sg_tablesize = SG_ALL,
267
268 .max_sectors = 0xFFFF,
afb046e2 269 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 270
271 .supported_mode = MODE_INITIATOR,
fca29703
AV		 272};
273
1da177e4 274static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 275struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 276
1da177e4
LT		 277/* TODO Convert to inlines
278 *
279 * Timer routines
280 */
1da177e4 281
2c3dfe3f 282__inline__ void
e315cd28 283qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 284{
e315cd28
AC		 285 init_timer(&vha->timer);
286 vha->timer.expires = jiffies + interval * HZ;
287 vha->timer.data = (unsigned long)vha;
288 vha->timer.function = (void (*)(unsigned long))func;
289 add_timer(&vha->timer);
290 vha->timer_active = 1;
1da177e4
LT		 291}
292
293static inline void
e315cd28 294qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 295{
a9083016 296 /* Currently used for 82XX only. */
7c3df132
SK		 297 if (vha->device_flags & DFLG_DEV_FAILED) {
298 ql_dbg(ql_dbg_timer, vha, 0x600d,
299 "Device in a failed state, returning.\n");
a9083016 300 return;
7c3df132 301 }
a9083016 302
e315cd28 303 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 304}
305
a824ebb3 306static __inline__ void
e315cd28 307qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 308{
e315cd28
AC		 309 del_timer_sync(&vha->timer);
310 vha->timer_active = 0;
1da177e4
LT		 311}
312
1da177e4
LT		 313static int qla2x00_do_dpc(void *data);
314
315static void qla2x00_rst_aen(scsi_qla_host_t *);
316
73208dfd
AC		 317static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
318 struct req_que **, struct rsp_que **);
e30d1756 319static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 320static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 321
1da177e4 322/* -------------------------------------------------------------------------- */
9a347ff4
CD		 323static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
324 struct rsp_que *rsp)
73208dfd 325{
7c3df132 326 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 327 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 328 GFP_KERNEL);
329 if (!ha->req_q_map) {
7c3df132
SK		 330 ql_log(ql_log_fatal, vha, 0x003b,
331 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 332 goto fail_req_map;
333 }
334
2afa19a9 335 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 336 GFP_KERNEL);
337 if (!ha->rsp_q_map) {
7c3df132
SK		 338 ql_log(ql_log_fatal, vha, 0x003c,
339 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 340 goto fail_rsp_map;
341 }
9a347ff4
CD		 342 /*
343 * Make sure we record at least the request and response queue zero in
344 * case we need to free them if part of the probe fails.
345 */
346 ha->rsp_q_map[0] = rsp;
347 ha->req_q_map[0] = req;
73208dfd
AC		 348 set_bit(0, ha->rsp_qid_map);
349 set_bit(0, ha->req_qid_map);
350 return 1;
351
352fail_rsp_map:
353 kfree(ha->req_q_map);
354 ha->req_q_map = NULL;
355fail_req_map:
356 return -ENOMEM;
357}
358
2afa19a9 359static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 360{
8ae6d9c7
GM		 361 if (IS_QLAFX00(ha)) {
362 if (req && req->ring_fx00)
363 dma_free_coherent(&ha->pdev->dev,
364 (req->length_fx00 + 1) * sizeof(request_t),
365 req->ring_fx00, req->dma_fx00);
366 } else if (req && req->ring)
73208dfd
AC		 367 dma_free_coherent(&ha->pdev->dev,
368 (req->length + 1) * sizeof(request_t),
369 req->ring, req->dma);
370
8d93f550
CD		 371 if (req)
372 kfree(req->outstanding_cmds);
373
73208dfd
AC		 374 kfree(req);
375 req = NULL;
376}
377
2afa19a9
AC		 378static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
379{
8ae6d9c7
GM		 380 if (IS_QLAFX00(ha)) {
381 if (rsp && rsp->ring)
382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length_fx00 + 1) * sizeof(request_t),
384 rsp->ring_fx00, rsp->dma_fx00);
385 } else if (rsp && rsp->ring) {
2afa19a9
AC		 386 dma_free_coherent(&ha->pdev->dev,
387 (rsp->length + 1) * sizeof(response_t),
388 rsp->ring, rsp->dma);
8ae6d9c7 389 }
2afa19a9
AC		 390 kfree(rsp);
391 rsp = NULL;
392}
393
73208dfd
AC		 394static void qla2x00_free_queues(struct qla_hw_data *ha)
395{
396 struct req_que *req;
397 struct rsp_que *rsp;
398 int cnt;
399
2afa19a9 400 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 401 req = ha->req_q_map[cnt];
2afa19a9 402 qla2x00_free_req_que(ha, req);
73208dfd 403 }
73208dfd
AC		 404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
2afa19a9
AC		 406
407 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
408 rsp = ha->rsp_q_map[cnt];
409 qla2x00_free_rsp_que(ha, rsp);
410 }
411 kfree(ha->rsp_q_map);
412 ha->rsp_q_map = NULL;
73208dfd
AC		 413}
414
68ca949c
AC		 415static int qla25xx_setup_mode(struct scsi_qla_host *vha)
416{
417 uint16_t options = 0;
418 int ques, req, ret;
419 struct qla_hw_data *ha = vha->hw;
420
7163ea81 421 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 422 ql_log(ql_log_warn, vha, 0x00d8,
423 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 424 goto fail;
425 }
68ca949c 426 if (ql2xmultique_tag) {
68ca949c
AC		 427 /* create a request queue for IO */
428 options |= BIT_7;
429 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
430 QLA_DEFAULT_QUE_QOS);
431 if (!req) {
7c3df132
SK		 432 ql_log(ql_log_warn, vha, 0x00e0,
433 "Failed to create request queue.\n");
68ca949c
AC		 434 goto fail;
435 }
278274d5 436 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 437 vha->req = ha->req_q_map[req];
438 options |= BIT_1;
439 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
440 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
441 if (!ret) {
7c3df132
SK		 442 ql_log(ql_log_warn, vha, 0x00e8,
443 "Failed to create response queue.\n");
68ca949c
AC		 444 goto fail2;
445 }
446 }
7163ea81 447 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 448 ql_dbg(ql_dbg_multiq, vha, 0xc007,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
452 ql_dbg(ql_dbg_init, vha, 0x00e9,
453 "CPU affinity mode enalbed, "
454 "no. of response queues:%d no. of request queues:%d.\n",
455 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 456 }
457 return 0;
458fail2:
459 qla25xx_delete_queues(vha);
7163ea81
AC		 460 destroy_workqueue(ha->wq);
461 ha->wq = NULL;
0cd33fcf 462 vha->req = ha->req_q_map[0];
68ca949c
AC		 463fail:
464 ha->mqenable = 0;
7163ea81
AC		 465 kfree(ha->req_q_map);
466 kfree(ha->rsp_q_map);
467 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 468 return 1;
469}
470
1da177e4 471static char *
e315cd28 472qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 473{
e315cd28 474 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 475 static char *pci_bus_modes[] = {
476 "33", "66", "100", "133",
477 };
478 uint16_t pci_bus;
479
480 strcpy(str, "PCI");
481 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
482 if (pci_bus) {
483 strcat(str, "-X (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 } else {
486 pci_bus = (ha->pci_attr & BIT_8) >> 8;
487 strcat(str, " (");
488 strcat(str, pci_bus_modes[pci_bus]);
489 }
490 strcat(str, " MHz)");
491
492 return (str);
493}
494
fca29703 495static char *
e315cd28 496qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 497{
498 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 499 struct qla_hw_data *ha = vha->hw;
fca29703 500 uint32_t pci_bus;
fca29703 501
62a276f8 502 if (pci_is_pcie(ha->pdev)) {
fca29703 503 char lwstr[6];
62a276f8 504 uint32_t lstat, lspeed, lwidth;
fca29703 505
62a276f8
BH		 506 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
507 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
508 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 509
510 strcpy(str, "PCIe (");
49300af7
SK		 511 switch (lspeed) {
512 case 1:
c87a0d8c 513 strcat(str, "2.5GT/s ");
49300af7
SK		 514 break;
515 case 2:
c87a0d8c 516 strcat(str, "5.0GT/s ");
49300af7
SK		 517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
fca29703 522 strcat(str, "<unknown> ");
49300af7
SK		 523 break;
524 }
fca29703
AV		 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548}
549
e5f82ab8 550static char *
df57caba 551qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 552{
553 char un_str[10];
e315cd28 554 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 555
df57caba
HM		 556 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 558
559 if (ha->fw_attributes & BIT_9) {
560 strcat(str, "FLX");
561 return (str);
562 }
563
564 switch (ha->fw_attributes & 0xFF) {
565 case 0x7:
566 strcat(str, "EF");
567 break;
568 case 0x17:
569 strcat(str, "TP");
570 break;
571 case 0x37:
572 strcat(str, "IP");
573 break;
574 case 0x77:
575 strcat(str, "VI");
576 break;
577 default:
578 sprintf(un_str, "(%x)", ha->fw_attributes);
579 strcat(str, un_str);
580 break;
581 }
582 if (ha->fw_attributes & 0x100)
583 strcat(str, "X");
584
585 return (str);
586}
587
e5f82ab8 588static char *
df57caba 589qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 590{
e315cd28 591 struct qla_hw_data *ha = vha->hw;
f0883ac6 592
df57caba 593 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 594 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 595 return str;
fca29703
AV		 596}
597
9ba56b95
GM		 598void
599qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 600{
9ba56b95
GM		 601 srb_t *sp = (srb_t *)ptr;
602 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
603 struct qla_hw_data *ha = sp->fcport->vha->hw;
604 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 605
9ba56b95
GM		 606 if (sp->flags & SRB_DMA_VALID) {
607 scsi_dma_unmap(cmd);
608 sp->flags &= ~SRB_DMA_VALID;
7c3df132 609 }
fca29703 610
9ba56b95
GM		 611 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
612 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
613 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
614 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
615 }
616
617 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
618 /* List assured to be having elements */
f83adb61 619 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 620 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
621 }
622
623 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
624 dma_pool_free(ha->dl_dma_pool, ctx,
625 ((struct crc_context *)ctx)->crc_ctx_dma);
626 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
627 }
628
629 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
630 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 631
9ba56b95
GM		 632 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
633 ctx1->fcp_cmnd_dma);
634 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
635 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
636 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
637 mempool_free(ctx1, ha->ctx_mempool);
638 ctx1 = NULL;
639 }
640
641 CMD_SP(cmd) = NULL;
b00ee7d7 642 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 643}
644
14b06808 645static void
9ba56b95
GM		 646qla2x00_sp_compl(void *data, void *ptr, int res)
647{
648 struct qla_hw_data *ha = (struct qla_hw_data *)data;
649 srb_t *sp = (srb_t *)ptr;
650 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
651
652 cmd->result = res;
653
654 if (atomic_read(&sp->ref_count) == 0) {
655 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
656 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
657 sp, GET_CMD_SP(sp));
658 if (ql2xextended_error_logging & ql_dbg_io)
659 BUG();
660 return;
661 }
662 if (!atomic_dec_and_test(&sp->ref_count))
663 return;
664
665 qla2x00_sp_free_dma(ha, sp);
666 cmd->scsi_done(cmd);
fca29703
AV		 667}
668
8ae6d9c7
GM		 669/* If we are SP1 here, we need to still take and release the host_lock as SP1
670 * does not have the changes necessary to avoid taking host->host_lock.
671 */
1da177e4 672static int
f5e3e40b 673qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 674{
134ae078 675 scsi_qla_host_t *vha = shost_priv(host);
fca29703 676 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 677 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 678 struct qla_hw_data *ha = vha->hw;
679 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 680 srb_t *sp;
681 int rval;
682
85880801 683 if (ha->flags.eeh_busy) {
7c3df132 684 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 685 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 686 "PCI Channel IO permanent failure, exiting "
687 "cmd=%p.\n", cmd);
b9b12f73 688 cmd->result = DID_NO_CONNECT << 16;
7c3df132 689 } else {
5f28d2d7 690 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 691 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 692 cmd->result = DID_REQUEUE << 16;
7c3df132 693 }
14e660e6
SJ		 694 goto qc24_fail_command;
695 }
696
19a7b4ae
JSEC		 697 rval = fc_remote_port_chkready(rport);
698 if (rval) {
699 cmd->result = rval;
5f28d2d7 700 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 701 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
702 cmd, rval);
fca29703
AV		 703 goto qc24_fail_command;
704 }
705
bad75002
AE		 706 if (!vha->flags.difdix_supported &&
707 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 708 ql_dbg(ql_dbg_io, vha, 0x3004,
709 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
710 cmd);
bad75002
AE		 711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
aa651be8
CD		 714
715 if (!fcport) {
716 cmd->result = DID_NO_CONNECT << 16;
717 goto qc24_fail_command;
718 }
719
fca29703
AV		 720 if (atomic_read(&fcport->state) != FCS_ONLINE) {
721 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 722 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 723 ql_dbg(ql_dbg_io, vha, 0x3005,
724 "Returning DNC, fcport_state=%d loop_state=%d.\n",
725 atomic_read(&fcport->state),
726 atomic_read(&base_vha->loop_state));
fca29703
AV		 727 cmd->result = DID_NO_CONNECT << 16;
728 goto qc24_fail_command;
729 }
7b594131 730 goto qc24_target_busy;
fca29703
AV		 731 }
732
b00ee7d7 733 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 734 if (!sp)
f5e3e40b 735 goto qc24_host_busy;
fca29703 736
9ba56b95
GM		 737 sp->u.scmd.cmd = cmd;
738 sp->type = SRB_SCSI_CMD;
739 atomic_set(&sp->ref_count, 1);
740 CMD_SP(cmd) = (void *)sp;
741 sp->free = qla2x00_sp_free_dma;
742 sp->done = qla2x00_sp_compl;
743
e315cd28 744 rval = ha->isp_ops->start_scsi(sp);
7c3df132 745 if (rval != QLA_SUCCESS) {
53016ed3 746 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 747 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 748 goto qc24_host_busy_free_sp;
7c3df132 749 }
fca29703 750
fca29703
AV		 751 return 0;
752
753qc24_host_busy_free_sp:
9ba56b95 754 qla2x00_sp_free_dma(ha, sp);
fca29703 755
f5e3e40b 756qc24_host_busy:
fca29703
AV		 757 return SCSI_MLQUEUE_HOST_BUSY;
758
7b594131
MC		 759qc24_target_busy:
760 return SCSI_MLQUEUE_TARGET_BUSY;
761
fca29703 762qc24_fail_command:
f5e3e40b 763 cmd->scsi_done(cmd);
fca29703
AV		 764
765 return 0;
766}
767
1da177e4
LT		 768/*
769 * qla2x00_eh_wait_on_command
770 * Waits for the command to be returned by the Firmware for some
771 * max time.
772 *
773 * Input:
1da177e4 774 * cmd = Scsi Command to wait on.
1da177e4
LT		 775 *
776 * Return:
777 * Not Found : 0
778 * Found : 1
779 */
780static int
e315cd28 781qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 782{
fe74c71f 783#define ABORT_POLLING_PERIOD 1000
478c3b03 784#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 785 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 786 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
787 struct qla_hw_data *ha = vha->hw;
f4f051eb 788 int ret = QLA_SUCCESS;
1da177e4 789
85880801 790 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 791 ql_dbg(ql_dbg_taskm, vha, 0x8005,
792 "Return:eh_wait.\n");
85880801
AV		 793 return ret;
794 }
795
d970432c 796 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 797 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 798 }
799 if (CMD_SP(cmd))
800 ret = QLA_FUNCTION_FAILED;
1da177e4 801
f4f051eb 802 return ret;
1da177e4
LT		 803}
804
805/*
806 * qla2x00_wait_for_hba_online
fa2a1ce5 807 * Wait till the HBA is online after going through
1da177e4
LT		 808 * <= MAX_RETRIES_OF_ISP_ABORT or
809 * finally HBA is disabled ie marked offline
810 *
811 * Input:
812 * ha - pointer to host adapter structure
fa2a1ce5
AV		 813 *
814 * Note:
1da177e4
LT		 815 * Does context switching-Release SPIN_LOCK
816 * (if any) before calling this routine.
817 *
818 * Return:
819 * Success (Adapter is online) : 0
820 * Failed (Adapter is offline/disabled) : 1
821 */
854165f4 822int
e315cd28 823qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 824{
fca29703
AV		 825 int return_status;
826 unsigned long wait_online;
e315cd28
AC		 827 struct qla_hw_data *ha = vha->hw;
828 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 829
fa2a1ce5 830 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 831 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
832 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
833 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
834 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 835
836 msleep(1000);
837 }
e315cd28 838 if (base_vha->flags.online)
fa2a1ce5 839 return_status = QLA_SUCCESS;
1da177e4
LT		 840 else
841 return_status = QLA_FUNCTION_FAILED;
842
1da177e4
LT		 843 return (return_status);
844}
845
86fbee86 846/*
638a1a01
SC		 847 * qla2x00_wait_for_hba_ready
848 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 849 *
850 * Input:
851 * ha - pointer to host adapter structure
852 *
853 * Note:
854 * Does context switching-Release SPIN_LOCK
855 * (if any) before calling this routine.
856 *
86fbee86 857 */
638a1a01
SC		 858static void
859qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 860{
86fbee86 861 struct qla_hw_data *ha = vha->hw;
86fbee86 862
9d35894d
SC		 863 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
864 ha->flags.mbox_busy) ||
865 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
866 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags))
86fbee86 867 msleep(1000);
86fbee86
LC		 868}
869
2533cf67
LC		 870int
871qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
872{
873 int return_status;
874 unsigned long wait_reset;
875 struct qla_hw_data *ha = vha->hw;
876 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
877
878 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
879 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
880 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
881 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
882 ha->dpc_active) && time_before(jiffies, wait_reset)) {
883
884 msleep(1000);
885
886 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
887 ha->flags.chip_reset_done)
888 break;
889 }
890 if (ha->flags.chip_reset_done)
891 return_status = QLA_SUCCESS;
892 else
893 return_status = QLA_FUNCTION_FAILED;
894
895 return return_status;
896}
897
083a469d
GM		 898static void
899sp_get(struct srb *sp)
900{
901 atomic_inc(&sp->ref_count);
902}
903
1da177e4
LT		 904/**************************************************************************
905* qla2xxx_eh_abort
906*
907* Description:
908* The abort function will abort the specified command.
909*
910* Input:
911* cmd = Linux SCSI command packet to be aborted.
912*
913* Returns:
914* Either SUCCESS or FAILED.
915*
916* Note:
2ea00202 917* Only return FAILED if command not returned by firmware.
1da177e4 918**************************************************************************/
e5f82ab8 919static int
1da177e4
LT		 920qla2xxx_eh_abort(struct scsi_cmnd *cmd)
921{
e315cd28 922 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 923 srb_t *sp;
4e98d3b8 924 int ret;
9cb78c16
HR		 925 unsigned int id;
926 uint64_t lun;
18e144d3 927 unsigned long flags;
f934c9d0 928 int rval, wait = 0;
e315cd28 929 struct qla_hw_data *ha = vha->hw;
1da177e4 930
f4f051eb 931 if (!CMD_SP(cmd))
2ea00202 932 return SUCCESS;
1da177e4 933
4e98d3b8
AV		 934 ret = fc_block_scsi_eh(cmd);
935 if (ret != 0)
936 return ret;
937 ret = SUCCESS;
938
f4f051eb
AV		 939 id = cmd->device->id;
940 lun = cmd->device->lun;
1da177e4 941
e315cd28 942 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 943 sp = (srb_t *) CMD_SP(cmd);
944 if (!sp) {
945 spin_unlock_irqrestore(&ha->hardware_lock, flags);
946 return SUCCESS;
947 }
1da177e4 948
7c3df132 949 ql_dbg(ql_dbg_taskm, vha, 0x8002,
9cb78c16 950 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n",
cfb0919c 951 vha->host_no, id, lun, sp, cmd);
17d98630 952
170babc3
MC		 953 /* Get a reference to the sp and drop the lock.*/
954 sp_get(sp);
083a469d 955
e315cd28 956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 957 rval = ha->isp_ops->abort_command(sp);
958 if (rval) {
959 if (rval == QLA_FUNCTION_PARAMETER_ERROR) {
960 /*
961 * Decrement the ref_count since we can't find the
962 * command
963 */
964 atomic_dec(&sp->ref_count);
965 ret = SUCCESS;
966 } else
967 ret = FAILED;
968
7c3df132 969 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 970 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 971 } else {
7c3df132 972 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 973 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 974 wait = 1;
975 }
75942064
SK		 976
977 spin_lock_irqsave(&ha->hardware_lock, flags);
f934c9d0
CD		 978 /*
979 * Clear the slot in the oustanding_cmds array if we can't find the
980 * command to reclaim the resources.
981 */
982 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
983 vha->req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 984 sp->done(ha, sp, 0);
75942064 985 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 986
bc91ade9
CD		 987 /* Did the command return during mailbox execution? */
988 if (ret == FAILED && !CMD_SP(cmd))
989 ret = SUCCESS;
990
f4f051eb 991 /* Wait for the command to be returned. */
2ea00202 992 if (wait) {
e315cd28 993 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 994 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 995 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 996 ret = FAILED;
f4f051eb 997 }
1da177e4 998 }
1da177e4 999
7c3df132 1000 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1001 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1002 vha->host_no, id, lun, wait, ret);
1da177e4 1003
f4f051eb
AV		 1004 return ret;
1005}
1da177e4 1006
4d78c973 1007int
e315cd28 1008qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1009 uint64_t l, enum nexus_wait_type type)
f4f051eb 1010{
17d98630 1011 int cnt, match, status;
18e144d3 1012 unsigned long flags;
e315cd28 1013 struct qla_hw_data *ha = vha->hw;
73208dfd 1014 struct req_que *req;
4d78c973 1015 srb_t *sp;
9ba56b95 1016 struct scsi_cmnd *cmd;
1da177e4 1017
523ec773 1018 status = QLA_SUCCESS;
17d98630 1019
e315cd28 1020 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1021 req = vha->req;
17d98630 1022 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1023 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1024 sp = req->outstanding_cmds[cnt];
1025 if (!sp)
523ec773 1026 continue;
9ba56b95 1027 if (sp->type != SRB_SCSI_CMD)
cf53b069 1028 continue;
17d98630
AC		 1029 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1030 continue;
1031 match = 0;
9ba56b95 1032 cmd = GET_CMD_SP(sp);
17d98630
AC		 1033 switch (type) {
1034 case WAIT_HOST:
1035 match = 1;
1036 break;
1037 case WAIT_TARGET:
9ba56b95 1038 match = cmd->device->id == t;
17d98630
AC		 1039 break;
1040 case WAIT_LUN:
9ba56b95
GM		 1041 match = (cmd->device->id == t &&
1042 cmd->device->lun == l);
17d98630 1043 break;
73208dfd 1044 }
17d98630
AC		 1045 if (!match)
1046 continue;
1047
1048 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1049 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1050 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1051 }
e315cd28 1052 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1053
1054 return status;
1da177e4
LT		 1055}
1056
523ec773
AV		 1057static char *reset_errors[] = {
1058 "HBA not online",
1059 "HBA not ready",
1060 "Task management failed",
1061 "Waiting for command completions",
1062};
1da177e4 1063
e5f82ab8 1064static int
523ec773 1065__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1066 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1067{
e315cd28 1068 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1069 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1070 int err;
1da177e4 1071
7c3df132 1072 if (!fcport) {
523ec773 1073 return FAILED;
7c3df132 1074 }
1da177e4 1075
4e98d3b8
AV		 1076 err = fc_block_scsi_eh(cmd);
1077 if (err != 0)
1078 return err;
1079
7c3df132 1080 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1081 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1082 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1083
523ec773 1084 err = 0;
7c3df132
SK		 1085 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1086 ql_log(ql_log_warn, vha, 0x800a,
1087 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1088 goto eh_reset_failed;
7c3df132 1089 }
523ec773 1090 err = 2;
2afa19a9 1091 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1092 != QLA_SUCCESS) {
1093 ql_log(ql_log_warn, vha, 0x800c,
1094 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1095 goto eh_reset_failed;
7c3df132 1096 }
523ec773 1097 err = 3;
e315cd28 1098 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1099 cmd->device->lun, type) != QLA_SUCCESS) {
1100 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1101 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1102 goto eh_reset_failed;
7c3df132 1103 }
523ec773 1104
7c3df132 1105 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1106 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1107 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1108
1109 return SUCCESS;
1110
4d78c973 1111eh_reset_failed:
7c3df132 1112 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1113 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1114 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1115 cmd);
523ec773
AV		 1116 return FAILED;
1117}
1da177e4 1118
523ec773
AV		 1119static int
1120qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1121{
e315cd28
AC		 1122 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1123 struct qla_hw_data *ha = vha->hw;
1da177e4 1124
523ec773
AV		 1125 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1126 ha->isp_ops->lun_reset);
1da177e4
LT		 1127}
1128
1da177e4 1129static int
523ec773 1130qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1131{
e315cd28
AC		 1132 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1133 struct qla_hw_data *ha = vha->hw;
1da177e4 1134
523ec773
AV		 1135 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1136 ha->isp_ops->target_reset);
1da177e4
LT		 1137}
1138
1da177e4
LT		 1139/**************************************************************************
1140* qla2xxx_eh_bus_reset
1141*
1142* Description:
1143* The bus reset function will reset the bus and abort any executing
1144* commands.
1145*
1146* Input:
1147* cmd = Linux SCSI command packet of the command that cause the
1148* bus reset.
1149*
1150* Returns:
1151* SUCCESS/FAILURE (defined as macro in scsi.h).
1152*
1153**************************************************************************/
e5f82ab8 1154static int
1da177e4
LT		 1155qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1156{
e315cd28 1157 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1158 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1159 int ret = FAILED;
9cb78c16
HR		 1160 unsigned int id;
1161 uint64_t lun;
f4f051eb 1162
f4f051eb
AV		 1163 id = cmd->device->id;
1164 lun = cmd->device->lun;
1da177e4 1165
7c3df132 1166 if (!fcport) {
f4f051eb 1167 return ret;
7c3df132 1168 }
1da177e4 1169
4e98d3b8
AV		 1170 ret = fc_block_scsi_eh(cmd);
1171 if (ret != 0)
1172 return ret;
1173 ret = FAILED;
1174
7c3df132 1175 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1176 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1177
e315cd28 1178 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1179 ql_log(ql_log_fatal, vha, 0x8013,
1180 "Wait for hba online failed board disabled.\n");
f4f051eb 1181 goto eh_bus_reset_done;
1da177e4
LT		 1182 }
1183
ad537689
SK		 1184 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1185 ret = SUCCESS;
1186
f4f051eb
AV		 1187 if (ret == FAILED)
1188 goto eh_bus_reset_done;
1da177e4 1189
9a41a62b 1190 /* Flush outstanding commands. */
4d78c973 1191 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1192 QLA_SUCCESS) {
1193 ql_log(ql_log_warn, vha, 0x8014,
1194 "Wait for pending commands failed.\n");
9a41a62b 1195 ret = FAILED;
7c3df132 1196 }
1da177e4 1197
f4f051eb 1198eh_bus_reset_done:
7c3df132 1199 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1200 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1201 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1202
f4f051eb 1203 return ret;
1da177e4
LT		 1204}
1205
1206/**************************************************************************
1207* qla2xxx_eh_host_reset
1208*
1209* Description:
1210* The reset function will reset the Adapter.
1211*
1212* Input:
1213* cmd = Linux SCSI command packet of the command that cause the
1214* adapter reset.
1215*
1216* Returns:
1217* Either SUCCESS or FAILED.
1218*
1219* Note:
1220**************************************************************************/
e5f82ab8 1221static int
1da177e4
LT		 1222qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1223{
e315cd28 1224 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1225 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1226 int ret = FAILED;
9cb78c16
HR		 1227 unsigned int id;
1228 uint64_t lun;
e315cd28 1229 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1230
f4f051eb
AV		 1231 id = cmd->device->id;
1232 lun = cmd->device->lun;
f4f051eb 1233
7c3df132 1234 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1235 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1236
63ee7072
CD		 1237 /*
1238 * No point in issuing another reset if one is active. Also do not
1239 * attempt a reset if we are updating flash.
1240 */
1241 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1242 goto eh_host_reset_lock;
1da177e4 1243
e315cd28
AC		 1244 if (vha != base_vha) {
1245 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1246 goto eh_host_reset_lock;
e315cd28 1247 } else {
7ec0effd 1248 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1249 if (!qla82xx_fcoe_ctx_reset(vha)) {
1250 /* Ctx reset success */
1251 ret = SUCCESS;
1252 goto eh_host_reset_lock;
1253 }
1254 /* fall thru if ctx reset failed */
1255 }
68ca949c
AC		 1256 if (ha->wq)
1257 flush_workqueue(ha->wq);
1258
e315cd28 1259 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1260 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1261 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1262 /* failed. schedule dpc to try */
1263 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1264
7c3df132
SK		 1265 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1266 ql_log(ql_log_warn, vha, 0x802a,
1267 "wait for hba online failed.\n");
e315cd28 1268 goto eh_host_reset_lock;
7c3df132 1269 }
e315cd28
AC		 1270 }
1271 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1272 }
1da177e4 1273
e315cd28 1274 /* Waiting for command to be returned to OS.*/
4d78c973 1275 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1276 QLA_SUCCESS)
f4f051eb 1277 ret = SUCCESS;
1da177e4 1278
f4f051eb 1279eh_host_reset_lock:
cfb0919c 1280 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1281 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1282 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1283
f4f051eb
AV		 1284 return ret;
1285}
1da177e4
LT		 1286
1287/*
1288* qla2x00_loop_reset
1289* Issue loop reset.
1290*
1291* Input:
1292* ha = adapter block pointer.
1293*
1294* Returns:
1295* 0 = success
1296*/
a4722cf2 1297int
e315cd28 1298qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1299{
0c8c39af 1300 int ret;
bdf79621 1301 struct fc_port *fcport;
e315cd28 1302 struct qla_hw_data *ha = vha->hw;
1da177e4 1303
5854771e
AB		 1304 if (IS_QLAFX00(ha)) {
1305 return qlafx00_loop_reset(vha);
1306 }
1307
f4c496c1 1308 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1309 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1310 if (fcport->port_type != FCT_TARGET)
1311 continue;
1312
1313 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1314 if (ret != QLA_SUCCESS) {
7c3df132 1315 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1316 "Bus Reset failed: Reset=%d "
7c3df132 1317 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1318 }
1319 }
1320 }
1321
8ae6d9c7 1322
6246b8a1 1323 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1324 atomic_set(&vha->loop_state, LOOP_DOWN);
1325 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1326 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1327 ret = qla2x00_full_login_lip(vha);
0c8c39af 1328 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1329 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1330 "full_login_lip=%d.\n", ret);
749af3d5 1331 }
0c8c39af
AV		 1332 }
1333
0d6e61bc 1334 if (ha->flags.enable_lip_reset) {
e315cd28 1335 ret = qla2x00_lip_reset(vha);
ad537689 1336 if (ret != QLA_SUCCESS)
7c3df132
SK		 1337 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1338 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1339 }
1340
1da177e4 1341 /* Issue marker command only when we are going to start the I/O */
e315cd28 1342 vha->marker_needed = 1;
1da177e4 1343
0c8c39af 1344 return QLA_SUCCESS;
1da177e4
LT		 1345}
1346
df4bf0bb 1347void
e315cd28 1348qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1349{
73208dfd 1350 int que, cnt;
df4bf0bb
AV		 1351 unsigned long flags;
1352 srb_t *sp;
e315cd28 1353 struct qla_hw_data *ha = vha->hw;
73208dfd 1354 struct req_que *req;
df4bf0bb
AV		 1355
1356 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1357 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1358 req = ha->req_q_map[que];
73208dfd
AC		 1359 if (!req)
1360 continue;
8d93f550
CD		 1361 if (!req->outstanding_cmds)
1362 continue;
1363 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1364 sp = req->outstanding_cmds[cnt];
e612d465 1365 if (sp) {
73208dfd 1366 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1367 sp->done(vha, sp, res);
73208dfd 1368 }
df4bf0bb
AV		 1369 }
1370 }
1371 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1372}
1373
f4f051eb
AV		 1374static int
1375qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1376{
bdf79621 1377 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1378
19a7b4ae 1379 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1380 return -ENXIO;
bdf79621 1381
19a7b4ae 1382 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1383
f4f051eb
AV		 1384 return 0;
1385}
1da177e4 1386
f4f051eb
AV		 1387static int
1388qla2xxx_slave_configure(struct scsi_device *sdev)
1389{
e315cd28 1390 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1391 struct req_que *req = vha->req;
8482e118 1392
9e522cd8
AE		 1393 if (IS_T10_PI_CAPABLE(vha->hw))
1394 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1395
f4f051eb 1396 if (sdev->tagged_supported)
73208dfd 1397 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1398 else
73208dfd 1399 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1400 return 0;
1401}
1da177e4 1402
f4f051eb
AV		 1403static void
1404qla2xxx_slave_destroy(struct scsi_device *sdev)
1405{
1406 sdev->hostdata = NULL;
1da177e4
LT		 1407}
1408
c45dd305
GM		 1409static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1410{
1411 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1412
1413 if (!scsi_track_queue_full(sdev, qdepth))
1414 return;
1415
7c3df132 1416 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
9cb78c16 1417 "Queue depth adjusted-down to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1418 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1419}
1420
1421static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1422{
1423 fc_port_t *fcport = sdev->hostdata;
1424 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1425 struct req_que *req = NULL;
1426
1427 req = vha->req;
1428 if (!req)
1429 return;
1430
1431 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1432 return;
1433
1434 if (sdev->ordered_tags)
1435 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1436 else
1437 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1438
7c3df132 1439 ql_dbg(ql_dbg_io, vha, 0x302a,
9cb78c16 1440 "Queue depth adjusted-up to %d for nexus=%ld:%d:%llu.\n",
cfb0919c 1441 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1442}
1443
ce7e4af7 1444static int
e881a172 1445qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1446{
c45dd305
GM		 1447 switch (reason) {
1448 case SCSI_QDEPTH_DEFAULT:
1449 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1450 break;
1451 case SCSI_QDEPTH_QFULL:
1452 qla2x00_handle_queue_full(sdev, qdepth);
1453 break;
1454 case SCSI_QDEPTH_RAMP_UP:
1455 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1456 break;
1457 default:
08002af2 1458 return -EOPNOTSUPP;
c45dd305 1459 }
e881a172 1460
ce7e4af7
AV		 1461 return sdev->queue_depth;
1462}
1463
1464static int
1465qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1466{
1467 if (sdev->tagged_supported) {
1468 scsi_set_tag_type(sdev, tag_type);
1469 if (tag_type)
1470 scsi_activate_tcq(sdev, sdev->queue_depth);
1471 else
1472 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1473 } else
1474 tag_type = 0;
1475
1476 return tag_type;
1477}
1478
1da177e4
LT		 1479/**
1480 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1481 * @ha: HA context
1482 *
1483 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1484 * supported addressing method.
1485 */
1486static void
53303c42 1487qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1488{
7524f9b9 1489 /* Assume a 32bit DMA mask. */
1da177e4 1490 ha->flags.enable_64bit_addressing = 0;
1da177e4 1491
6a35528a 1492 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1493 /* Any upper-dword bits set? */
1494 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1495 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1496 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1497 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1498 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1499 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1500 return;
1da177e4 1501 }
1da177e4 1502 }
7524f9b9 1503
284901a9
YH		 1504 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1505 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1506}
1507
fd34f556 1508static void
e315cd28 1509qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1510{
1511 unsigned long flags = 0;
1512 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1513
1514 spin_lock_irqsave(&ha->hardware_lock, flags);
1515 ha->interrupts_on = 1;
1516 /* enable risc and host interrupts */
1517 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1518 RD_REG_WORD(&reg->ictrl);
1519 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1520
1521}
1522
1523static void
e315cd28 1524qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1525{
1526 unsigned long flags = 0;
1527 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1528
1529 spin_lock_irqsave(&ha->hardware_lock, flags);
1530 ha->interrupts_on = 0;
1531 /* disable risc and host interrupts */
1532 WRT_REG_WORD(&reg->ictrl, 0);
1533 RD_REG_WORD(&reg->ictrl);
1534 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1535}
1536
1537static void
e315cd28 1538qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1539{
1540 unsigned long flags = 0;
1541 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1542
1543 spin_lock_irqsave(&ha->hardware_lock, flags);
1544 ha->interrupts_on = 1;
1545 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1546 RD_REG_DWORD(&reg->ictrl);
1547 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1548}
1549
1550static void
e315cd28 1551qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1552{
1553 unsigned long flags = 0;
1554 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1555
124f85e6
AV		 1556 if (IS_NOPOLLING_TYPE(ha))
1557 return;
fd34f556
AV		 1558 spin_lock_irqsave(&ha->hardware_lock, flags);
1559 ha->interrupts_on = 0;
1560 WRT_REG_DWORD(&reg->ictrl, 0);
1561 RD_REG_DWORD(&reg->ictrl);
1562 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1563}
1564
706f457d
GM		 1565static int
1566qla2x00_iospace_config(struct qla_hw_data *ha)
1567{
1568 resource_size_t pio;
1569 uint16_t msix;
1570 int cpus;
1571
706f457d
GM		 1572 if (pci_request_selected_regions(ha->pdev, ha->bars,
1573 QLA2XXX_DRIVER_NAME)) {
1574 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1575 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1576 pci_name(ha->pdev));
1577 goto iospace_error_exit;
1578 }
1579 if (!(ha->bars & 1))
1580 goto skip_pio;
1581
1582 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1583 pio = pci_resource_start(ha->pdev, 0);
1584 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1585 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1586 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1587 "Invalid pci I/O region size (%s).\n",
1588 pci_name(ha->pdev));
1589 pio = 0;
1590 }
1591 } else {
1592 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1593 "Region #0 no a PIO resource (%s).\n",
1594 pci_name(ha->pdev));
1595 pio = 0;
1596 }
1597 ha->pio_address = pio;
1598 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1599 "PIO address=%llu.\n",
1600 (unsigned long long)ha->pio_address);
1601
1602skip_pio:
1603 /* Use MMIO operations for all accesses. */
1604 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1605 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1606 "Region #1 not an MMIO resource (%s), aborting.\n",
1607 pci_name(ha->pdev));
1608 goto iospace_error_exit;
1609 }
1610 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1611 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1612 "Invalid PCI mem region size (%s), aborting.\n",
1613 pci_name(ha->pdev));
1614 goto iospace_error_exit;
1615 }
1616
1617 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1618 if (!ha->iobase) {
1619 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1620 "Cannot remap MMIO (%s), aborting.\n",
1621 pci_name(ha->pdev));
1622 goto iospace_error_exit;
1623 }
1624
1625 /* Determine queue resources */
1626 ha->max_req_queues = ha->max_rsp_queues = 1;
1627 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1628 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1629 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1630 goto mqiobase_exit;
1631
1632 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1633 pci_resource_len(ha->pdev, 3));
1634 if (ha->mqiobase) {
1635 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1636 "MQIO Base=%p.\n", ha->mqiobase);
1637 /* Read MSIX vector size of the board */
1638 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1639 ha->msix_count = msix;
1640 /* Max queues are bounded by available msix vectors */
1641 /* queue 0 uses two msix vectors */
1642 if (ql2xmultique_tag) {
1643 cpus = num_online_cpus();
1644 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1645 (cpus + 1) : (ha->msix_count - 1);
1646 ha->max_req_queues = 2;
1647 } else if (ql2xmaxqueues > 1) {
1648 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1649 QLA_MQ_SIZE : ql2xmaxqueues;
1650 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1651 "QoS mode set, max no of request queues:%d.\n",
1652 ha->max_req_queues);
1653 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1654 "QoS mode set, max no of request queues:%d.\n",
1655 ha->max_req_queues);
1656 }
1657 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1658 "MSI-X vector count: %d.\n", msix);
1659 } else
1660 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1661 "BAR 3 not enabled.\n");
1662
1663mqiobase_exit:
1664 ha->msix_count = ha->max_rsp_queues + 1;
1665 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1666 "MSIX Count:%d.\n", ha->msix_count);
1667 return (0);
1668
1669iospace_error_exit:
1670 return (-ENOMEM);
1671}
1672
1673
6246b8a1
GM		 1674static int
1675qla83xx_iospace_config(struct qla_hw_data *ha)
1676{
1677 uint16_t msix;
1678 int cpus;
1679
1680 if (pci_request_selected_regions(ha->pdev, ha->bars,
1681 QLA2XXX_DRIVER_NAME)) {
1682 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1683 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1684 pci_name(ha->pdev));
1685
1686 goto iospace_error_exit;
1687 }
1688
1689 /* Use MMIO operations for all accesses. */
1690 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1691 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1692 "Invalid pci I/O region size (%s).\n",
1693 pci_name(ha->pdev));
1694 goto iospace_error_exit;
1695 }
1696 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1697 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1698 "Invalid PCI mem region size (%s), aborting\n",
1699 pci_name(ha->pdev));
1700 goto iospace_error_exit;
1701 }
1702
1703 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1704 if (!ha->iobase) {
1705 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1706 "Cannot remap MMIO (%s), aborting.\n",
1707 pci_name(ha->pdev));
1708 goto iospace_error_exit;
1709 }
1710
1711 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1712 /* 83XX 26XX always use MQ type access for queues
1713 * - mbar 2, a.k.a region 4 */
1714 ha->max_req_queues = ha->max_rsp_queues = 1;
1715 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1716 pci_resource_len(ha->pdev, 4));
1717
1718 if (!ha->mqiobase) {
1719 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1720 "BAR2/region4 not enabled\n");
1721 goto mqiobase_exit;
1722 }
1723
1724 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1725 pci_resource_len(ha->pdev, 2));
1726 if (ha->msixbase) {
1727 /* Read MSIX vector size of the board */
1728 pci_read_config_word(ha->pdev,
1729 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1730 ha->msix_count = msix;
1731 /* Max queues are bounded by available msix vectors */
1732 /* queue 0 uses two msix vectors */
1733 if (ql2xmultique_tag) {
1734 cpus = num_online_cpus();
1735 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1736 (cpus + 1) : (ha->msix_count - 1);
1737 ha->max_req_queues = 2;
1738 } else if (ql2xmaxqueues > 1) {
1739 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1740 QLA_MQ_SIZE : ql2xmaxqueues;
1741 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1742 "QoS mode set, max no of request queues:%d.\n",
1743 ha->max_req_queues);
1744 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1745 "QoS mode set, max no of request queues:%d.\n",
1746 ha->max_req_queues);
1747 }
1748 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1749 "MSI-X vector count: %d.\n", msix);
1750 } else
1751 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1752 "BAR 1 not enabled.\n");
1753
1754mqiobase_exit:
1755 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1756
1757 qlt_83xx_iospace_config(ha);
1758
6246b8a1
GM		 1759 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1760 "MSIX Count:%d.\n", ha->msix_count);
1761 return 0;
1762
1763iospace_error_exit:
1764 return -ENOMEM;
1765}
1766
fd34f556
AV		 1767static struct isp_operations qla2100_isp_ops = {
1768 .pci_config = qla2100_pci_config,
1769 .reset_chip = qla2x00_reset_chip,
1770 .chip_diag = qla2x00_chip_diag,
1771 .config_rings = qla2x00_config_rings,
1772 .reset_adapter = qla2x00_reset_adapter,
1773 .nvram_config = qla2x00_nvram_config,
1774 .update_fw_options = qla2x00_update_fw_options,
1775 .load_risc = qla2x00_load_risc,
1776 .pci_info_str = qla2x00_pci_info_str,
1777 .fw_version_str = qla2x00_fw_version_str,
1778 .intr_handler = qla2100_intr_handler,
1779 .enable_intrs = qla2x00_enable_intrs,
1780 .disable_intrs = qla2x00_disable_intrs,
1781 .abort_command = qla2x00_abort_command,
523ec773
AV		 1782 .target_reset = qla2x00_abort_target,
1783 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1784 .fabric_login = qla2x00_login_fabric,
1785 .fabric_logout = qla2x00_fabric_logout,
1786 .calc_req_entries = qla2x00_calc_iocbs_32,
1787 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1788 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1789 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1790 .read_nvram = qla2x00_read_nvram_data,
1791 .write_nvram = qla2x00_write_nvram_data,
1792 .fw_dump = qla2100_fw_dump,
1793 .beacon_on = NULL,
1794 .beacon_off = NULL,
1795 .beacon_blink = NULL,
1796 .read_optrom = qla2x00_read_optrom_data,
1797 .write_optrom = qla2x00_write_optrom_data,
1798 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1799 .start_scsi = qla2x00_start_scsi,
a9083016 1800 .abort_isp = qla2x00_abort_isp,
706f457d 1801 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1802 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1803};
1804
1805static struct isp_operations qla2300_isp_ops = {
1806 .pci_config = qla2300_pci_config,
1807 .reset_chip = qla2x00_reset_chip,
1808 .chip_diag = qla2x00_chip_diag,
1809 .config_rings = qla2x00_config_rings,
1810 .reset_adapter = qla2x00_reset_adapter,
1811 .nvram_config = qla2x00_nvram_config,
1812 .update_fw_options = qla2x00_update_fw_options,
1813 .load_risc = qla2x00_load_risc,
1814 .pci_info_str = qla2x00_pci_info_str,
1815 .fw_version_str = qla2x00_fw_version_str,
1816 .intr_handler = qla2300_intr_handler,
1817 .enable_intrs = qla2x00_enable_intrs,
1818 .disable_intrs = qla2x00_disable_intrs,
1819 .abort_command = qla2x00_abort_command,
523ec773
AV		 1820 .target_reset = qla2x00_abort_target,
1821 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1822 .fabric_login = qla2x00_login_fabric,
1823 .fabric_logout = qla2x00_fabric_logout,
1824 .calc_req_entries = qla2x00_calc_iocbs_32,
1825 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1826 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1827 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1828 .read_nvram = qla2x00_read_nvram_data,
1829 .write_nvram = qla2x00_write_nvram_data,
1830 .fw_dump = qla2300_fw_dump,
1831 .beacon_on = qla2x00_beacon_on,
1832 .beacon_off = qla2x00_beacon_off,
1833 .beacon_blink = qla2x00_beacon_blink,
1834 .read_optrom = qla2x00_read_optrom_data,
1835 .write_optrom = qla2x00_write_optrom_data,
1836 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1837 .start_scsi = qla2x00_start_scsi,
a9083016 1838 .abort_isp = qla2x00_abort_isp,
7ec0effd 1839 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1840 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1841};
1842
1843static struct isp_operations qla24xx_isp_ops = {
1844 .pci_config = qla24xx_pci_config,
1845 .reset_chip = qla24xx_reset_chip,
1846 .chip_diag = qla24xx_chip_diag,
1847 .config_rings = qla24xx_config_rings,
1848 .reset_adapter = qla24xx_reset_adapter,
1849 .nvram_config = qla24xx_nvram_config,
1850 .update_fw_options = qla24xx_update_fw_options,
1851 .load_risc = qla24xx_load_risc,
1852 .pci_info_str = qla24xx_pci_info_str,
1853 .fw_version_str = qla24xx_fw_version_str,
1854 .intr_handler = qla24xx_intr_handler,
1855 .enable_intrs = qla24xx_enable_intrs,
1856 .disable_intrs = qla24xx_disable_intrs,
1857 .abort_command = qla24xx_abort_command,
523ec773
AV		 1858 .target_reset = qla24xx_abort_target,
1859 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1860 .fabric_login = qla24xx_login_fabric,
1861 .fabric_logout = qla24xx_fabric_logout,
1862 .calc_req_entries = NULL,
1863 .build_iocbs = NULL,
1864 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1865 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1866 .read_nvram = qla24xx_read_nvram_data,
1867 .write_nvram = qla24xx_write_nvram_data,
1868 .fw_dump = qla24xx_fw_dump,
1869 .beacon_on = qla24xx_beacon_on,
1870 .beacon_off = qla24xx_beacon_off,
1871 .beacon_blink = qla24xx_beacon_blink,
1872 .read_optrom = qla24xx_read_optrom_data,
1873 .write_optrom = qla24xx_write_optrom_data,
1874 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1875 .start_scsi = qla24xx_start_scsi,
a9083016 1876 .abort_isp = qla2x00_abort_isp,
7ec0effd 1877 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1878 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1879};
1880
c3a2f0df
AV		 1881static struct isp_operations qla25xx_isp_ops = {
1882 .pci_config = qla25xx_pci_config,
1883 .reset_chip = qla24xx_reset_chip,
1884 .chip_diag = qla24xx_chip_diag,
1885 .config_rings = qla24xx_config_rings,
1886 .reset_adapter = qla24xx_reset_adapter,
1887 .nvram_config = qla24xx_nvram_config,
1888 .update_fw_options = qla24xx_update_fw_options,
1889 .load_risc = qla24xx_load_risc,
1890 .pci_info_str = qla24xx_pci_info_str,
1891 .fw_version_str = qla24xx_fw_version_str,
1892 .intr_handler = qla24xx_intr_handler,
1893 .enable_intrs = qla24xx_enable_intrs,
1894 .disable_intrs = qla24xx_disable_intrs,
1895 .abort_command = qla24xx_abort_command,
523ec773
AV		 1896 .target_reset = qla24xx_abort_target,
1897 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1898 .fabric_login = qla24xx_login_fabric,
1899 .fabric_logout = qla24xx_fabric_logout,
1900 .calc_req_entries = NULL,
1901 .build_iocbs = NULL,
1902 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1903 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1904 .read_nvram = qla25xx_read_nvram_data,
1905 .write_nvram = qla25xx_write_nvram_data,
1906 .fw_dump = qla25xx_fw_dump,
1907 .beacon_on = qla24xx_beacon_on,
1908 .beacon_off = qla24xx_beacon_off,
1909 .beacon_blink = qla24xx_beacon_blink,
338c9161 1910 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1911 .write_optrom = qla24xx_write_optrom_data,
1912 .get_flash_version = qla24xx_get_flash_version,
bad75002 1913 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1914 .abort_isp = qla2x00_abort_isp,
7ec0effd 1915 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1916 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1917};
1918
3a03eb79
AV		 1919static struct isp_operations qla81xx_isp_ops = {
1920 .pci_config = qla25xx_pci_config,
1921 .reset_chip = qla24xx_reset_chip,
1922 .chip_diag = qla24xx_chip_diag,
1923 .config_rings = qla24xx_config_rings,
1924 .reset_adapter = qla24xx_reset_adapter,
1925 .nvram_config = qla81xx_nvram_config,
1926 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1927 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1928 .pci_info_str = qla24xx_pci_info_str,
1929 .fw_version_str = qla24xx_fw_version_str,
1930 .intr_handler = qla24xx_intr_handler,
1931 .enable_intrs = qla24xx_enable_intrs,
1932 .disable_intrs = qla24xx_disable_intrs,
1933 .abort_command = qla24xx_abort_command,
1934 .target_reset = qla24xx_abort_target,
1935 .lun_reset = qla24xx_lun_reset,
1936 .fabric_login = qla24xx_login_fabric,
1937 .fabric_logout = qla24xx_fabric_logout,
1938 .calc_req_entries = NULL,
1939 .build_iocbs = NULL,
1940 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1941 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1942 .read_nvram = NULL,
1943 .write_nvram = NULL,
3a03eb79
AV		 1944 .fw_dump = qla81xx_fw_dump,
1945 .beacon_on = qla24xx_beacon_on,
1946 .beacon_off = qla24xx_beacon_off,
6246b8a1 1947 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1948 .read_optrom = qla25xx_read_optrom_data,
1949 .write_optrom = qla24xx_write_optrom_data,
1950 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1951 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1952 .abort_isp = qla2x00_abort_isp,
7ec0effd 1953 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1954 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1955};
1956
1957static struct isp_operations qla82xx_isp_ops = {
1958 .pci_config = qla82xx_pci_config,
1959 .reset_chip = qla82xx_reset_chip,
1960 .chip_diag = qla24xx_chip_diag,
1961 .config_rings = qla82xx_config_rings,
1962 .reset_adapter = qla24xx_reset_adapter,
1963 .nvram_config = qla81xx_nvram_config,
1964 .update_fw_options = qla24xx_update_fw_options,
1965 .load_risc = qla82xx_load_risc,
9d55ca66 1966 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1967 .fw_version_str = qla24xx_fw_version_str,
1968 .intr_handler = qla82xx_intr_handler,
1969 .enable_intrs = qla82xx_enable_intrs,
1970 .disable_intrs = qla82xx_disable_intrs,
1971 .abort_command = qla24xx_abort_command,
1972 .target_reset = qla24xx_abort_target,
1973 .lun_reset = qla24xx_lun_reset,
1974 .fabric_login = qla24xx_login_fabric,
1975 .fabric_logout = qla24xx_fabric_logout,
1976 .calc_req_entries = NULL,
1977 .build_iocbs = NULL,
1978 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1979 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1980 .read_nvram = qla24xx_read_nvram_data,
1981 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1982 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1983 .beacon_on = qla82xx_beacon_on,
1984 .beacon_off = qla82xx_beacon_off,
1985 .beacon_blink = NULL,
a9083016
GM		 1986 .read_optrom = qla82xx_read_optrom_data,
1987 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1988 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1989 .start_scsi = qla82xx_start_scsi,
1990 .abort_isp = qla82xx_abort_isp,
706f457d 1991 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1992 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1993};
1994
7ec0effd
AD		 1995static struct isp_operations qla8044_isp_ops = {
1996 .pci_config = qla82xx_pci_config,
1997 .reset_chip = qla82xx_reset_chip,
1998 .chip_diag = qla24xx_chip_diag,
1999 .config_rings = qla82xx_config_rings,
2000 .reset_adapter = qla24xx_reset_adapter,
2001 .nvram_config = qla81xx_nvram_config,
2002 .update_fw_options = qla24xx_update_fw_options,
2003 .load_risc = qla82xx_load_risc,
2004 .pci_info_str = qla24xx_pci_info_str,
2005 .fw_version_str = qla24xx_fw_version_str,
2006 .intr_handler = qla8044_intr_handler,
2007 .enable_intrs = qla82xx_enable_intrs,
2008 .disable_intrs = qla82xx_disable_intrs,
2009 .abort_command = qla24xx_abort_command,
2010 .target_reset = qla24xx_abort_target,
2011 .lun_reset = qla24xx_lun_reset,
2012 .fabric_login = qla24xx_login_fabric,
2013 .fabric_logout = qla24xx_fabric_logout,
2014 .calc_req_entries = NULL,
2015 .build_iocbs = NULL,
2016 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2017 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2018 .read_nvram = NULL,
2019 .write_nvram = NULL,
a1b23c5a 2020 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2021 .beacon_on = qla82xx_beacon_on,
2022 .beacon_off = qla82xx_beacon_off,
2023 .beacon_blink = NULL,
888e639d 2024 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2025 .write_optrom = qla8044_write_optrom_data,
2026 .get_flash_version = qla82xx_get_flash_version,
2027 .start_scsi = qla82xx_start_scsi,
2028 .abort_isp = qla8044_abort_isp,
2029 .iospace_config = qla82xx_iospace_config,
2030 .initialize_adapter = qla2x00_initialize_adapter,
2031};
2032
6246b8a1
GM		 2033static struct isp_operations qla83xx_isp_ops = {
2034 .pci_config = qla25xx_pci_config,
2035 .reset_chip = qla24xx_reset_chip,
2036 .chip_diag = qla24xx_chip_diag,
2037 .config_rings = qla24xx_config_rings,
2038 .reset_adapter = qla24xx_reset_adapter,
2039 .nvram_config = qla81xx_nvram_config,
2040 .update_fw_options = qla81xx_update_fw_options,
2041 .load_risc = qla81xx_load_risc,
2042 .pci_info_str = qla24xx_pci_info_str,
2043 .fw_version_str = qla24xx_fw_version_str,
2044 .intr_handler = qla24xx_intr_handler,
2045 .enable_intrs = qla24xx_enable_intrs,
2046 .disable_intrs = qla24xx_disable_intrs,
2047 .abort_command = qla24xx_abort_command,
2048 .target_reset = qla24xx_abort_target,
2049 .lun_reset = qla24xx_lun_reset,
2050 .fabric_login = qla24xx_login_fabric,
2051 .fabric_logout = qla24xx_fabric_logout,
2052 .calc_req_entries = NULL,
2053 .build_iocbs = NULL,
2054 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2055 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2056 .read_nvram = NULL,
2057 .write_nvram = NULL,
2058 .fw_dump = qla83xx_fw_dump,
2059 .beacon_on = qla24xx_beacon_on,
2060 .beacon_off = qla24xx_beacon_off,
2061 .beacon_blink = qla83xx_beacon_blink,
2062 .read_optrom = qla25xx_read_optrom_data,
2063 .write_optrom = qla24xx_write_optrom_data,
2064 .get_flash_version = qla24xx_get_flash_version,
2065 .start_scsi = qla24xx_dif_start_scsi,
2066 .abort_isp = qla2x00_abort_isp,
2067 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2068 .initialize_adapter = qla2x00_initialize_adapter,
2069};
2070
2071static struct isp_operations qlafx00_isp_ops = {
2072 .pci_config = qlafx00_pci_config,
2073 .reset_chip = qlafx00_soft_reset,
2074 .chip_diag = qlafx00_chip_diag,
2075 .config_rings = qlafx00_config_rings,
2076 .reset_adapter = qlafx00_soft_reset,
2077 .nvram_config = NULL,
2078 .update_fw_options = NULL,
2079 .load_risc = NULL,
2080 .pci_info_str = qlafx00_pci_info_str,
2081 .fw_version_str = qlafx00_fw_version_str,
2082 .intr_handler = qlafx00_intr_handler,
2083 .enable_intrs = qlafx00_enable_intrs,
2084 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2085 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2086 .target_reset = qlafx00_abort_target,
2087 .lun_reset = qlafx00_lun_reset,
2088 .fabric_login = NULL,
2089 .fabric_logout = NULL,
2090 .calc_req_entries = NULL,
2091 .build_iocbs = NULL,
2092 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2093 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2094 .read_nvram = qla24xx_read_nvram_data,
2095 .write_nvram = qla24xx_write_nvram_data,
2096 .fw_dump = NULL,
2097 .beacon_on = qla24xx_beacon_on,
2098 .beacon_off = qla24xx_beacon_off,
2099 .beacon_blink = NULL,
2100 .read_optrom = qla24xx_read_optrom_data,
2101 .write_optrom = qla24xx_write_optrom_data,
2102 .get_flash_version = qla24xx_get_flash_version,
2103 .start_scsi = qlafx00_start_scsi,
2104 .abort_isp = qlafx00_abort_isp,
2105 .iospace_config = qlafx00_iospace_config,
2106 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2107};
2108
f73cb695
CD		 2109static struct isp_operations qla27xx_isp_ops = {
2110 .pci_config = qla25xx_pci_config,
2111 .reset_chip = qla24xx_reset_chip,
2112 .chip_diag = qla24xx_chip_diag,
2113 .config_rings = qla24xx_config_rings,
2114 .reset_adapter = qla24xx_reset_adapter,
2115 .nvram_config = qla81xx_nvram_config,
2116 .update_fw_options = qla81xx_update_fw_options,
2117 .load_risc = qla81xx_load_risc,
2118 .pci_info_str = qla24xx_pci_info_str,
2119 .fw_version_str = qla24xx_fw_version_str,
2120 .intr_handler = qla24xx_intr_handler,
2121 .enable_intrs = qla24xx_enable_intrs,
2122 .disable_intrs = qla24xx_disable_intrs,
2123 .abort_command = qla24xx_abort_command,
2124 .target_reset = qla24xx_abort_target,
2125 .lun_reset = qla24xx_lun_reset,
2126 .fabric_login = qla24xx_login_fabric,
2127 .fabric_logout = qla24xx_fabric_logout,
2128 .calc_req_entries = NULL,
2129 .build_iocbs = NULL,
2130 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2131 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2132 .read_nvram = NULL,
2133 .write_nvram = NULL,
2134 .fw_dump = qla27xx_fwdump,
2135 .beacon_on = qla24xx_beacon_on,
2136 .beacon_off = qla24xx_beacon_off,
2137 .beacon_blink = qla83xx_beacon_blink,
2138 .read_optrom = qla25xx_read_optrom_data,
2139 .write_optrom = qla24xx_write_optrom_data,
2140 .get_flash_version = qla24xx_get_flash_version,
2141 .start_scsi = qla24xx_dif_start_scsi,
2142 .abort_isp = qla2x00_abort_isp,
2143 .iospace_config = qla83xx_iospace_config,
2144 .initialize_adapter = qla2x00_initialize_adapter,
2145};
2146
ea5b6382 2147static inline void
e315cd28 2148qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2149{
2150 ha->device_type = DT_EXTENDED_IDS;
2151 switch (ha->pdev->device) {
2152 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2153 ha->device_type |= DT_ISP2100;
2154 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2155 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2156 break;
2157 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2158 ha->device_type |= DT_ISP2200;
2159 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2160 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2161 break;
2162 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2163 ha->device_type |= DT_ISP2300;
4a59f71d 2164 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2165 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2166 break;
2167 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2168 ha->device_type |= DT_ISP2312;
4a59f71d 2169 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2170 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2171 break;
2172 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2173 ha->device_type |= DT_ISP2322;
4a59f71d 2174 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2175 if (ha->pdev->subsystem_vendor == 0x1028 &&
2176 ha->pdev->subsystem_device == 0x0170)
2177 ha->device_type |= DT_OEM_001;
441d1072 2178 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2179 break;
2180 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2181 ha->device_type |= DT_ISP6312;
441d1072 2182 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2183 break;
2184 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2185 ha->device_type |= DT_ISP6322;
441d1072 2186 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2187 break;
2188 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2189 ha->device_type |= DT_ISP2422;
4a59f71d 2190 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2191 ha->device_type |= DT_FWI2;
c76f2c01 2192 ha->device_type |= DT_IIDMA;
441d1072 2193 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2194 break;
2195 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2196 ha->device_type |= DT_ISP2432;
4a59f71d 2197 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2198 ha->device_type |= DT_FWI2;
c76f2c01 2199 ha->device_type |= DT_IIDMA;
441d1072 2200 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2201 break;
4d4df193
HK		 2202 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2203 ha->device_type |= DT_ISP8432;
2204 ha->device_type |= DT_ZIO_SUPPORTED;
2205 ha->device_type |= DT_FWI2;
2206 ha->device_type |= DT_IIDMA;
2207 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2208 break;
044cc6c8
AV		 2209 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2210 ha->device_type |= DT_ISP5422;
e428924c 2211 ha->device_type |= DT_FWI2;
441d1072 2212 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2213 break;
044cc6c8
AV		 2214 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2215 ha->device_type |= DT_ISP5432;
e428924c 2216 ha->device_type |= DT_FWI2;
441d1072 2217 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2218 break;
c3a2f0df
AV		 2219 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2220 ha->device_type |= DT_ISP2532;
2221 ha->device_type |= DT_ZIO_SUPPORTED;
2222 ha->device_type |= DT_FWI2;
2223 ha->device_type |= DT_IIDMA;
441d1072 2224 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2225 break;
3a03eb79
AV		 2226 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2227 ha->device_type |= DT_ISP8001;
2228 ha->device_type |= DT_ZIO_SUPPORTED;
2229 ha->device_type |= DT_FWI2;
2230 ha->device_type |= DT_IIDMA;
2231 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2232 break;
a9083016
GM		 2233 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2234 ha->device_type |= DT_ISP8021;
2235 ha->device_type |= DT_ZIO_SUPPORTED;
2236 ha->device_type |= DT_FWI2;
2237 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2238 /* Initialize 82XX ISP flags */
2239 qla82xx_init_flags(ha);
2240 break;
7ec0effd
AD		 2241 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2242 ha->device_type |= DT_ISP8044;
2243 ha->device_type |= DT_ZIO_SUPPORTED;
2244 ha->device_type |= DT_FWI2;
2245 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2246 /* Initialize 82XX ISP flags */
2247 qla82xx_init_flags(ha);
2248 break;
6246b8a1
GM		 2249 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2250 ha->device_type |= DT_ISP2031;
2251 ha->device_type |= DT_ZIO_SUPPORTED;
2252 ha->device_type |= DT_FWI2;
2253 ha->device_type |= DT_IIDMA;
2254 ha->device_type |= DT_T10_PI;
2255 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2256 break;
2257 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2258 ha->device_type |= DT_ISP8031;
2259 ha->device_type |= DT_ZIO_SUPPORTED;
2260 ha->device_type |= DT_FWI2;
2261 ha->device_type |= DT_IIDMA;
2262 ha->device_type |= DT_T10_PI;
2263 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2264 break;
8ae6d9c7
GM		 2265 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2266 ha->device_type |= DT_ISPFX00;
2267 break;
f73cb695
CD		 2268 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2269 ha->device_type |= DT_ISP2071;
2270 ha->device_type |= DT_ZIO_SUPPORTED;
2271 ha->device_type |= DT_FWI2;
2272 ha->device_type |= DT_IIDMA;
2273 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2274 break;
2c5bbbb2
JC		 2275 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2276 ha->device_type |= DT_ISP2271;
2277 ha->device_type |= DT_ZIO_SUPPORTED;
2278 ha->device_type |= DT_FWI2;
2279 ha->device_type |= DT_IIDMA;
2280 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2281 break;
ea5b6382 2282 }
e5b68a61 2283
a9083016 2284 if (IS_QLA82XX(ha))
43a9c38b 2285 ha->port_no = ha->portnum & 1;
f73cb695 2286 else {
a9083016
GM		 2287 /* Get adapter physical port no from interrupt pin register. */
2288 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2289 if (IS_QLA27XX(ha))
2290 ha->port_no--;
2291 else
2292 ha->port_no = !(ha->port_no & 1);
2293 }
a9083016 2294
7c3df132 2295 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2296 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2297 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2298}
2299
1e99e33a
AV		 2300static void
2301qla2xxx_scan_start(struct Scsi_Host *shost)
2302{
e315cd28 2303 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2304
cbc8eb67
AV		 2305 if (vha->hw->flags.running_gold_fw)
2306 return;
2307
e315cd28
AC		 2308 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2309 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2310 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2311 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2312}
2313
2314static int
2315qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2316{
e315cd28 2317 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2318
e315cd28 2319 if (!vha->host)
1e99e33a 2320 return 1;
e315cd28 2321 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2322 return 1;
2323
e315cd28 2324 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2325}
2326
1da177e4
LT		 2327/*
2328 * PCI driver interface
2329 */
6f039790 2330static int
7ee61397 2331qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2332{
a1541d5a 2333 int ret = -ENODEV;
1da177e4 2334 struct Scsi_Host *host;
e315cd28
AC		 2335 scsi_qla_host_t *base_vha = NULL;
2336 struct qla_hw_data *ha;
29856e28 2337 char pci_info[30];
7d613ac6 2338 char fw_str[30], wq_name[30];
5433383e 2339 struct scsi_host_template *sht;
642ef983 2340 int bars, mem_only = 0;
e315cd28 2341 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2342 struct req_que *req = NULL;
2343 struct rsp_que *rsp = NULL;
285d0321 2344 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2345 sht = &qla2xxx_driver_template;
5433383e 2346 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2347 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2348 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2349 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2350 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2351 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2352 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2353 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2354 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2355 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2356 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2357 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2
JC		 2358 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2359 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) {
285d0321 2360 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2361 mem_only = 1;
7c3df132
SK		 2362 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2363 "Mem only adapter.\n");
285d0321 2364 }
7c3df132
SK		 2365 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2366 "Bars=%d.\n", bars);
285d0321 2367
09483916
BH		 2368 if (mem_only) {
2369 if (pci_enable_device_mem(pdev))
2370 goto probe_out;
2371 } else {
2372 if (pci_enable_device(pdev))
2373 goto probe_out;
2374 }
285d0321 2375
0927678f
JB		 2376 /* This may fail but that's ok */
2377 pci_enable_pcie_error_reporting(pdev);
285d0321 2378
e315cd28
AC		 2379 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2380 if (!ha) {
7c3df132
SK		 2381 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2382 "Unable to allocate memory for ha.\n");
e315cd28 2383 goto probe_out;
1da177e4 2384 }
7c3df132
SK		 2385 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2386 "Memory allocated for ha=%p.\n", ha);
e315cd28 2387 ha->pdev = pdev;
2d70c103 2388 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2389
2390 /* Clear our data area */
285d0321 2391 ha->bars = bars;
09483916 2392 ha->mem_only = mem_only;
df4bf0bb 2393 spin_lock_init(&ha->hardware_lock);
339aa70e 2394 spin_lock_init(&ha->vport_slock);
a9b6f722 2395 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2396 mutex_init(&ha->optrom_mutex);
1da177e4 2397
ea5b6382
AV		 2398 /* Set ISP-type information. */
2399 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2400
2401 /* Set EEH reset type to fundamental if required by hba */
95676112 2402 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2403 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2404 pdev->needs_freset = 1;
ca79cf66 2405
cba1e47f
CD		 2406 ha->prev_topology = 0;
2407 ha->init_cb_size = sizeof(init_cb_t);
2408 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2409 ha->optrom_size = OPTROM_SIZE_2300;
2410
abbd8870 2411 /* Assign ISP specific operations. */
1da177e4 2412 if (IS_QLA2100(ha)) {
642ef983 2413 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2414 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2415 req_length = REQUEST_ENTRY_CNT_2100;
2416 rsp_length = RESPONSE_ENTRY_CNT_2100;
2417 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2418 ha->gid_list_info_size = 4;
3a03eb79
AV		 2419 ha->flash_conf_off = ~0;
2420 ha->flash_data_off = ~0;
2421 ha->nvram_conf_off = ~0;
2422 ha->nvram_data_off = ~0;
fd34f556 2423 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2424 } else if (IS_QLA2200(ha)) {
642ef983 2425 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2426 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2427 req_length = REQUEST_ENTRY_CNT_2200;
2428 rsp_length = RESPONSE_ENTRY_CNT_2100;
2429 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2430 ha->gid_list_info_size = 4;
3a03eb79
AV		 2431 ha->flash_conf_off = ~0;
2432 ha->flash_data_off = ~0;
2433 ha->nvram_conf_off = ~0;
2434 ha->nvram_data_off = ~0;
fd34f556 2435 ha->isp_ops = &qla2100_isp_ops;
fca29703 2436 } else if (IS_QLA23XX(ha)) {
642ef983 2437 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2438 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2439 req_length = REQUEST_ENTRY_CNT_2200;
2440 rsp_length = RESPONSE_ENTRY_CNT_2300;
2441 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2442 ha->gid_list_info_size = 6;
854165f4
AV		 2443 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2444 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2445 ha->flash_conf_off = ~0;
2446 ha->flash_data_off = ~0;
2447 ha->nvram_conf_off = ~0;
2448 ha->nvram_data_off = ~0;
fd34f556 2449 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2450 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2451 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2452 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2453 req_length = REQUEST_ENTRY_CNT_24XX;
2454 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2455 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2456 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2457 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2458 ha->gid_list_info_size = 8;
854165f4 2459 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2460 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2461 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2462 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2463 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2464 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2465 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2466 } else if (IS_QLA25XX(ha)) {
642ef983 2467 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2468 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2469 req_length = REQUEST_ENTRY_CNT_24XX;
2470 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2471 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2472 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2473 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2474 ha->gid_list_info_size = 8;
2475 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2476 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2477 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2478 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2479 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2480 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2481 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2482 } else if (IS_QLA81XX(ha)) {
642ef983 2483 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2484 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2485 req_length = REQUEST_ENTRY_CNT_24XX;
2486 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2487 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2488 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2489 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2490 ha->gid_list_info_size = 8;
2491 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2492 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2493 ha->isp_ops = &qla81xx_isp_ops;
2494 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2495 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2496 ha->nvram_conf_off = ~0;
2497 ha->nvram_data_off = ~0;
a9083016 2498 } else if (IS_QLA82XX(ha)) {
642ef983 2499 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2500 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2501 req_length = REQUEST_ENTRY_CNT_82XX;
2502 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2503 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2504 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2505 ha->gid_list_info_size = 8;
2506 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2507 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2508 ha->isp_ops = &qla82xx_isp_ops;
2509 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2510 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2511 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2512 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2513 } else if (IS_QLA8044(ha)) {
2514 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2515 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2516 req_length = REQUEST_ENTRY_CNT_82XX;
2517 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2518 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2519 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2520 ha->gid_list_info_size = 8;
2521 ha->optrom_size = OPTROM_SIZE_83XX;
2522 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2523 ha->isp_ops = &qla8044_isp_ops;
2524 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2525 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2526 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2527 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2528 } else if (IS_QLA83XX(ha)) {
7d613ac6 2529 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2530 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2531 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2532 req_length = REQUEST_ENTRY_CNT_24XX;
2533 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2534 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2535 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2536 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2537 ha->gid_list_info_size = 8;
2538 ha->optrom_size = OPTROM_SIZE_83XX;
2539 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2540 ha->isp_ops = &qla83xx_isp_ops;
2541 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2542 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2543 ha->nvram_conf_off = ~0;
2544 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2545 } else if (IS_QLAFX00(ha)) {
2546 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2547 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2548 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2549 req_length = REQUEST_ENTRY_CNT_FX00;
2550 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2551 ha->isp_ops = &qlafx00_isp_ops;
2552 ha->port_down_retry_count = 30; /* default value */
2553 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2554 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2555 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2556 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2557 ha->mr.host_info_resend = false;
2558 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2559 } else if (IS_QLA27XX(ha)) {
2560 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2561 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2562 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2563 req_length = REQUEST_ENTRY_CNT_24XX;
2564 rsp_length = RESPONSE_ENTRY_CNT_2300;
2565 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2566 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2567 ha->gid_list_info_size = 8;
2568 ha->optrom_size = OPTROM_SIZE_83XX;
2569 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2570 ha->isp_ops = &qla27xx_isp_ops;
2571 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2572 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2573 ha->nvram_conf_off = ~0;
2574 ha->nvram_data_off = ~0;
1da177e4 2575 }
6246b8a1 2576
7c3df132
SK		 2577 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2578 "mbx_count=%d, req_length=%d, "
2579 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2580 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2581 "max_fibre_devices=%d.\n",
7c3df132
SK		 2582 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2583 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2584 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2585 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2586 "isp_ops=%p, flash_conf_off=%d, "
2587 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2588 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2589 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2590
2591 /* Configure PCI I/O space */
2592 ret = ha->isp_ops->iospace_config(ha);
2593 if (ret)
0a63ad12 2594 goto iospace_config_failed;
706f457d
GM		 2595
2596 ql_log_pci(ql_log_info, pdev, 0x001d,
2597 "Found an ISP%04X irq %d iobase 0x%p.\n",
2598 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2599 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2600 init_completion(&ha->mbx_cmd_comp);
2601 complete(&ha->mbx_cmd_comp);
2602 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2603 init_completion(&ha->dcbx_comp);
f356bef1 2604 init_completion(&ha->lb_portup_comp);
1da177e4 2605
2c3dfe3f 2606 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2607
53303c42 2608 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2609 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2610 "64 Bit addressing is %s.\n",
2611 ha->flags.enable_64bit_addressing ? "enable" :
2612 "disable");
73208dfd 2613 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2614 if (ret) {
7c3df132
SK		 2615 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2616 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2617
e315cd28
AC		 2618 goto probe_hw_failed;
2619 }
2620
73208dfd 2621 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2622 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2623 req->max_q_depth = ql2xmaxqdepth;
2624
e315cd28
AC		 2625
2626 base_vha = qla2x00_create_host(sht, ha);
2627 if (!base_vha) {
a1541d5a 2628 ret = -ENOMEM;
6e9f21f3 2629 qla2x00_mem_free(ha);
2afa19a9
AC		 2630 qla2x00_free_req_que(ha, req);
2631 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2632 goto probe_hw_failed;
1da177e4
LT		 2633 }
2634
e315cd28 2635 pci_set_drvdata(pdev, base_vha);
6b383979 2636 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2637
e315cd28 2638 host = base_vha->host;
2afa19a9 2639 base_vha->req = req;
73208dfd 2640 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2641 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2642 else
e315cd28
AC		 2643 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2644 base_vha->vp_idx;
58548cb5 2645
8ae6d9c7
GM		 2646 /* Setup fcport template structure. */
2647 ha->mr.fcport.vha = base_vha;
2648 ha->mr.fcport.port_type = FCT_UNKNOWN;
2649 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2650 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2651 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2652 ha->mr.fcport.scan_state = 1;
2653
58548cb5
GM		 2654 /* Set the SG table size based on ISP type */
2655 if (!IS_FWI2_CAPABLE(ha)) {
2656 if (IS_QLA2100(ha))
2657 host->sg_tablesize = 32;
2658 } else {
2659 if (!IS_QLA82XX(ha))
2660 host->sg_tablesize = QLA_SG_ALL;
2661 }
642ef983 2662 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2663 host->cmd_per_lun = 3;
2664 host->unique_id = host->host_no;
e02587d7 2665 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2666 host->max_cmd_len = 32;
2667 else
2668 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2669 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2670 /* Older HBAs support only 16-bit LUNs */
2671 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2672 ql2xmaxlun > 0xffff)
2673 host->max_lun = 0xffff;
2674 else
2675 host->max_lun = ql2xmaxlun;
e315cd28 2676 host->transportt = qla2xxx_transport_template;
9a069e19 2677 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2678
7c3df132
SK		 2679 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2680 "max_id=%d this_id=%d "
2681 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2682 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2683 host->this_id, host->cmd_per_lun, host->unique_id,
2684 host->max_cmd_len, host->max_channel, host->max_lun,
2685 host->transportt, sht->vendor_id);
2686
9a347ff4
CD		 2687que_init:
2688 /* Alloc arrays of request and response ring ptrs */
2689 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2690 ql_log(ql_log_fatal, base_vha, 0x003d,
2691 "Failed to allocate memory for queue pointers..."
2692 "aborting.\n");
2693 goto probe_init_failed;
2694 }
2695
2d70c103 2696 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2697
73208dfd
AC		 2698 /* Set up the irqs */
2699 ret = qla2x00_request_irqs(ha, rsp);
2700 if (ret)
6e9f21f3 2701 goto probe_init_failed;
90a86fc0
JC		 2702
2703 pci_save_state(pdev);
2704
9a347ff4 2705 /* Assign back pointers */
2afa19a9
AC		 2706 rsp->req = req;
2707 req->rsp = rsp;
9a347ff4 2708
8ae6d9c7
GM		 2709 if (IS_QLAFX00(ha)) {
2710 ha->rsp_q_map[0] = rsp;
2711 ha->req_q_map[0] = req;
2712 set_bit(0, ha->req_qid_map);
2713 set_bit(0, ha->rsp_qid_map);
2714 }
2715
08029990
AV		 2716 /* FWI2-capable only. */
2717 req->req_q_in = &ha->iobase->isp24.req_q_in;
2718 req->req_q_out = &ha->iobase->isp24.req_q_out;
2719 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2720 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2721 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2722 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2723 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2724 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2725 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2726 }
2727
8ae6d9c7
GM		 2728 if (IS_QLAFX00(ha)) {
2729 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2730 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2731 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2732 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2733 }
2734
7ec0effd 2735 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2736 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2737 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2738 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2739 }
2740
7c3df132
SK		 2741 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2742 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2743 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2744 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2745 "req->req_q_in=%p req->req_q_out=%p "
2746 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2747 req->req_q_in, req->req_q_out,
2748 rsp->rsp_q_in, rsp->rsp_q_out);
2749 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2750 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2751 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2752 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2753 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2754 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2755
8ae6d9c7 2756 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2757 ql_log(ql_log_fatal, base_vha, 0x00d6,
2758 "Failed to initialize adapter - Adapter flags %x.\n",
2759 base_vha->device_flags);
1da177e4 2760
a9083016
GM		 2761 if (IS_QLA82XX(ha)) {
2762 qla82xx_idc_lock(ha);
2763 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2764 QLA8XXX_DEV_FAILED);
a9083016 2765 qla82xx_idc_unlock(ha);
7c3df132
SK		 2766 ql_log(ql_log_fatal, base_vha, 0x00d7,
2767 "HW State: FAILED.\n");
7ec0effd
AD		 2768 } else if (IS_QLA8044(ha)) {
2769 qla8044_idc_lock(ha);
2770 qla8044_wr_direct(base_vha,
2771 QLA8044_CRB_DEV_STATE_INDEX,
2772 QLA8XXX_DEV_FAILED);
2773 qla8044_idc_unlock(ha);
2774 ql_log(ql_log_fatal, base_vha, 0x0150,
2775 "HW State: FAILED.\n");
a9083016
GM		 2776 }
2777
a1541d5a 2778 ret = -ENODEV;
1da177e4
LT		 2779 goto probe_failed;
2780 }
2781
3b1bef64
CD		 2782 if (IS_QLAFX00(ha))
2783 host->can_queue = QLAFX00_MAX_CANQUEUE;
2784 else
2785 host->can_queue = req->num_outstanding_cmds - 10;
2786
2787 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2788 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2789 host->can_queue, base_vha->req,
2790 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2791
7163ea81
AC		 2792 if (ha->mqenable) {
2793 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2794 ql_log(ql_log_warn, base_vha, 0x00ec,
2795 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2796 goto que_init;
2797 }
2798 }
68ca949c 2799
cbc8eb67
AV		 2800 if (ha->flags.running_gold_fw)
2801 goto skip_dpc;
2802
1da177e4
LT		 2803 /*
2804 * Startup the kernel thread for this host adapter
2805 */
39a11240 2806 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2807 "%s_dpc", base_vha->host_str);
39a11240 2808 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2809 ql_log(ql_log_fatal, base_vha, 0x00ed,
2810 "Failed to start DPC thread.\n");
39a11240 2811 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2812 goto probe_failed;
2813 }
7c3df132
SK		 2814 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2815 "DPC thread started successfully.\n");
1da177e4 2816
2d70c103
NB		 2817 /*
2818 * If we're not coming up in initiator mode, we might sit for
2819 * a while without waking up the dpc thread, which leads to a
2820 * stuck process warning. So just kick the dpc once here and
2821 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2822 */
2823 qla2xxx_wake_dpc(base_vha);
2824
f3ddac19
CD		 2825 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2826
81178772
SK		 2827 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2828 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2829 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2830 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2831
2832 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2833 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2834 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2835 INIT_WORK(&ha->idc_state_handler,
2836 qla83xx_idc_state_handler_work);
2837 INIT_WORK(&ha->nic_core_unrecoverable,
2838 qla83xx_nic_core_unrecoverable_work);
2839 }
2840
cbc8eb67 2841skip_dpc:
e315cd28
AC		 2842 list_add_tail(&base_vha->list, &ha->vp_list);
2843 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2844
2845 /* Initialized the timer */
e315cd28 2846 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2847 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2848 "Started qla2x00_timer with "
2849 "interval=%d.\n", WATCH_INTERVAL);
2850 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2851 "Detected hba at address=%p.\n",
2852 ha);
d19044c3 2853
e02587d7 2854 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2855 if (ha->fw_attributes & BIT_4) {
9e522cd8 2856 int prot = 0, guard;
bad75002 2857 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2858 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2859 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2860 if (ql2xenabledif == 1)
2861 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2862 scsi_host_set_prot(host,
8cb2049c 2863 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2864 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2865 | SHOST_DIF_TYPE3_PROTECTION
2866 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2867 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2868 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2869
2870 guard = SHOST_DIX_GUARD_CRC;
2871
2872 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2873 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2874 guard |= SHOST_DIX_GUARD_IP;
2875
2876 scsi_host_set_guard(host, guard);
bad75002
AE		 2877 } else
2878 base_vha->flags.difdix_supported = 0;
2879 }
2880
a9083016
GM		 2881 ha->isp_ops->enable_intrs(ha);
2882
1fe19ee4
AB		 2883 if (IS_QLAFX00(ha)) {
2884 ret = qlafx00_fx_disc(base_vha,
2885 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2886 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2887 QLA_SG_ALL : 128;
2888 }
2889
a1541d5a
AV		 2890 ret = scsi_add_host(host, &pdev->dev);
2891 if (ret)
2892 goto probe_failed;
2893
1486400f
MR		 2894 base_vha->flags.init_done = 1;
2895 base_vha->flags.online = 1;
edaa5c74 2896 ha->prev_minidump_failed = 0;
1486400f 2897
7c3df132
SK		 2898 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2899 "Init done and hba is online.\n");
2900
2d70c103
NB		 2901 if (qla_ini_mode_enabled(base_vha))
2902 scsi_scan_host(host);
2903 else
2904 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2905 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2906
e315cd28 2907 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2908
8ae6d9c7 2909 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2910 ret = qlafx00_fx_disc(base_vha,
2911 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2912
2913 /* Register system information */
2914 ret = qlafx00_fx_disc(base_vha,
2915 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2916 }
2917
e315cd28 2918 qla2x00_init_host_attr(base_vha);
a1541d5a 2919
e315cd28 2920 qla2x00_dfs_setup(base_vha);
df613b96 2921
03eb912a
AB		 2922 ql_log(ql_log_info, base_vha, 0x00fb,
2923 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2924 ql_log(ql_log_info, base_vha, 0x00fc,
2925 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2926 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2927 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2928 base_vha->host_no,
df57caba 2929 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2930
2d70c103
NB		 2931 qlt_add_target(ha, base_vha);
2932
6b383979 2933 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
1da177e4
LT		 2934 return 0;
2935
6e9f21f3 2936probe_init_failed:
2afa19a9 2937 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2938 ha->req_q_map[0] = NULL;
2939 clear_bit(0, ha->req_qid_map);
2afa19a9 2940 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2941 ha->rsp_q_map[0] = NULL;
2942 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2943 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2944
1da177e4 2945probe_failed:
b9978769
AV		 2946 if (base_vha->timer_active)
2947 qla2x00_stop_timer(base_vha);
2948 base_vha->flags.online = 0;
2949 if (ha->dpc_thread) {
2950 struct task_struct *t = ha->dpc_thread;
2951
2952 ha->dpc_thread = NULL;
2953 kthread_stop(t);
2954 }
2955
e315cd28 2956 qla2x00_free_device(base_vha);
1da177e4 2957
e315cd28 2958 scsi_host_put(base_vha->host);
1da177e4 2959
e315cd28 2960probe_hw_failed:
1a2fbf18
JL		 2961 qla2x00_clear_drv_active(ha);
2962
0a63ad12 2963iospace_config_failed:
7ec0effd 2964 if (IS_P3P_TYPE(ha)) {
0a63ad12 2965 if (!ha->nx_pcibase)
f73cb695 2966 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2967 if (!ql2xdbwr)
f73cb695 2968 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2969 } else {
2970 if (ha->iobase)
2971 iounmap(ha->iobase);
8ae6d9c7
GM		 2972 if (ha->cregbase)
2973 iounmap(ha->cregbase);
a9083016 2974 }
e315cd28
AC		 2975 pci_release_selected_regions(ha->pdev, ha->bars);
2976 kfree(ha);
2977 ha = NULL;
1da177e4 2978
a1541d5a 2979probe_out:
e315cd28 2980 pci_disable_device(pdev);
a1541d5a 2981 return ret;
1da177e4 2982}
1da177e4 2983
e30d1756
MI		 2984static void
2985qla2x00_shutdown(struct pci_dev *pdev)
2986{
2987 scsi_qla_host_t *vha;
2988 struct qla_hw_data *ha;
2989
552f3f9a
MI		 2990 if (!atomic_read(&pdev->enable_cnt))
2991 return;
2992
e30d1756
MI		 2993 vha = pci_get_drvdata(pdev);
2994 ha = vha->hw;
2995
42479343
AB		 2996 /* Notify ISPFX00 firmware */
2997 if (IS_QLAFX00(ha))
2998 qlafx00_driver_shutdown(vha, 20);
2999
e30d1756
MI		 3000 /* Turn-off FCE trace */
3001 if (ha->flags.fce_enabled) {
3002 qla2x00_disable_fce_trace(vha, NULL, NULL);
3003 ha->flags.fce_enabled = 0;
3004 }
3005
3006 /* Turn-off EFT trace */
3007 if (ha->eft)
3008 qla2x00_disable_eft_trace(vha);
3009
3010 /* Stop currently executing firmware. */
3011 qla2x00_try_to_stop_firmware(vha);
3012
3013 /* Turn adapter off line */
3014 vha->flags.online = 0;
3015
3016 /* turn-off interrupts on the card */
3017 if (ha->interrupts_on) {
3018 vha->flags.init_done = 0;
3019 ha->isp_ops->disable_intrs(ha);
3020 }
3021
3022 qla2x00_free_irqs(vha);
3023
3024 qla2x00_free_fw_dump(ha);
3025}
3026
fe1b806f 3027/* Deletes all the virtual ports for a given ha */
4c993f76 3028static void
fe1b806f 3029qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3030{
fe1b806f
CD		 3031 struct Scsi_Host *scsi_host;
3032 scsi_qla_host_t *vha;
feafb7b1 3033 unsigned long flags;
e315cd28 3034
43ebf16d
AE		 3035 mutex_lock(&ha->vport_lock);
3036 while (ha->cur_vport_count) {
43ebf16d 3037 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3038
43ebf16d
AE		 3039 BUG_ON(base_vha->list.next == &ha->vp_list);
3040 /* This assumes first entry in ha->vp_list is always base vha */
3041 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 3042 scsi_host = scsi_host_get(vha->host);
feafb7b1 3043
43ebf16d
AE		 3044 spin_unlock_irqrestore(&ha->vport_slock, flags);
3045 mutex_unlock(&ha->vport_lock);
3046
3047 fc_vport_terminate(vha->fc_vport);
3048 scsi_host_put(vha->host);
feafb7b1 3049
43ebf16d 3050 mutex_lock(&ha->vport_lock);
e315cd28 3051 }
43ebf16d 3052 mutex_unlock(&ha->vport_lock);
fe1b806f 3053}
1da177e4 3054
fe1b806f
CD		 3055/* Stops all deferred work threads */
3056static void
3057qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3058{
68ca949c
AC		 3059 /* Flush the work queue and remove it */
3060 if (ha->wq) {
3061 flush_workqueue(ha->wq);
3062 destroy_workqueue(ha->wq);
3063 ha->wq = NULL;
3064 }
3065
7d613ac6
SV		 3066 /* Cancel all work and destroy DPC workqueues */
3067 if (ha->dpc_lp_wq) {
3068 cancel_work_sync(&ha->idc_aen);
3069 destroy_workqueue(ha->dpc_lp_wq);
3070 ha->dpc_lp_wq = NULL;
3071 }
3072
3073 if (ha->dpc_hp_wq) {
3074 cancel_work_sync(&ha->nic_core_reset);
3075 cancel_work_sync(&ha->idc_state_handler);
3076 cancel_work_sync(&ha->nic_core_unrecoverable);
3077 destroy_workqueue(ha->dpc_hp_wq);
3078 ha->dpc_hp_wq = NULL;
3079 }
3080
b9978769
AV		 3081 /* Kill the kernel thread for this host */
3082 if (ha->dpc_thread) {
3083 struct task_struct *t = ha->dpc_thread;
3084
3085 /*
3086 * qla2xxx_wake_dpc checks for ->dpc_thread
3087 * so we need to zero it out.
3088 */
3089 ha->dpc_thread = NULL;
3090 kthread_stop(t);
3091 }
fe1b806f 3092}
1da177e4 3093
fe1b806f
CD		 3094static void
3095qla2x00_unmap_iobases(struct qla_hw_data *ha)
3096{
a9083016 3097 if (IS_QLA82XX(ha)) {
b963752f 3098
f73cb695 3099 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3100 if (!ql2xdbwr)
f73cb695 3101 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3102 } else {
3103 if (ha->iobase)
3104 iounmap(ha->iobase);
1da177e4 3105
8ae6d9c7
GM		 3106 if (ha->cregbase)
3107 iounmap(ha->cregbase);
3108
a9083016
GM		 3109 if (ha->mqiobase)
3110 iounmap(ha->mqiobase);
6246b8a1 3111
f73cb695 3112 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3113 iounmap(ha->msixbase);
a9083016 3114 }
fe1b806f
CD		 3115}
3116
3117static void
db7157d4 3118qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3119{
fe1b806f
CD		 3120 if (IS_QLA8044(ha)) {
3121 qla8044_idc_lock(ha);
c41afc9a 3122 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3123 qla8044_idc_unlock(ha);
3124 } else if (IS_QLA82XX(ha)) {
3125 qla82xx_idc_lock(ha);
3126 qla82xx_clear_drv_active(ha);
3127 qla82xx_idc_unlock(ha);
3128 }
3129}
3130
3131static void
3132qla2x00_remove_one(struct pci_dev *pdev)
3133{
3134 scsi_qla_host_t *base_vha;
3135 struct qla_hw_data *ha;
3136
beb9e315
JL		 3137 base_vha = pci_get_drvdata(pdev);
3138 ha = base_vha->hw;
3139
3140 /* Indicate device removal to prevent future board_disable and wait
3141 * until any pending board_disable has completed. */
3142 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3143 cancel_work_sync(&ha->board_disable);
3144
fe1b806f 3145 /*
beb9e315
JL		 3146 * If the PCI device is disabled then there was a PCI-disconnect and
3147 * qla2x00_disable_board_on_pci_error has taken care of most of the
3148 * resources.
fe1b806f 3149 */
beb9e315
JL		 3150 if (!atomic_read(&pdev->enable_cnt)) {
3151 scsi_host_put(base_vha->host);
3152 kfree(ha);
3153 pci_set_drvdata(pdev, NULL);
fe1b806f 3154 return;
beb9e315 3155 }
fe1b806f 3156
638a1a01
SC		 3157 qla2x00_wait_for_hba_ready(base_vha);
3158
fe1b806f
CD		 3159 set_bit(UNLOADING, &base_vha->dpc_flags);
3160
3161 if (IS_QLAFX00(ha))
3162 qlafx00_driver_shutdown(base_vha, 20);
3163
3164 qla2x00_delete_all_vps(ha, base_vha);
3165
3166 if (IS_QLA8031(ha)) {
3167 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3168 "Clearing fcoe driver presence.\n");
3169 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3170 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3171 "Error while clearing DRV-Presence.\n");
3172 }
3173
3174 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3175
3176 qla2x00_dfs_remove(base_vha);
3177
3178 qla84xx_put_chip(base_vha);
3179
3180 /* Disable timer */
3181 if (base_vha->timer_active)
3182 qla2x00_stop_timer(base_vha);
3183
3184 base_vha->flags.online = 0;
3185
3186 qla2x00_destroy_deferred_work(ha);
3187
3188 qlt_remove_target(ha, base_vha);
3189
3190 qla2x00_free_sysfs_attr(base_vha, true);
3191
3192 fc_remove_host(base_vha->host);
3193
3194 scsi_remove_host(base_vha->host);
3195
3196 qla2x00_free_device(base_vha);
3197
db7157d4 3198 qla2x00_clear_drv_active(ha);
fe1b806f 3199
d2749ffa
AE		 3200 scsi_host_put(base_vha->host);
3201
fe1b806f 3202 qla2x00_unmap_iobases(ha);
73208dfd 3203
e315cd28
AC		 3204 pci_release_selected_regions(ha->pdev, ha->bars);
3205 kfree(ha);
3206 ha = NULL;
1da177e4 3207
90a86fc0
JC		 3208 pci_disable_pcie_error_reporting(pdev);
3209
665db93b 3210 pci_disable_device(pdev);
1da177e4 3211}
1da177e4
LT		 3212
3213static void
e315cd28 3214qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3215{
e315cd28 3216 struct qla_hw_data *ha = vha->hw;
1da177e4 3217
85880801
AV		 3218 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3219
3220 /* Disable timer */
3221 if (vha->timer_active)
3222 qla2x00_stop_timer(vha);
3223
2afa19a9 3224 qla25xx_delete_queues(vha);
fe1b806f 3225
df613b96 3226 if (ha->flags.fce_enabled)
e315cd28 3227 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3228
a7a167bf 3229 if (ha->eft)
e315cd28 3230 qla2x00_disable_eft_trace(vha);
a7a167bf 3231
f6ef3b18 3232 /* Stop currently executing firmware. */
e315cd28 3233 qla2x00_try_to_stop_firmware(vha);
1da177e4 3234
85880801
AV		 3235 vha->flags.online = 0;
3236
f6ef3b18 3237 /* turn-off interrupts on the card */
a9083016
GM		 3238 if (ha->interrupts_on) {
3239 vha->flags.init_done = 0;
fd34f556 3240 ha->isp_ops->disable_intrs(ha);
a9083016 3241 }
f6ef3b18 3242
e315cd28 3243 qla2x00_free_irqs(vha);
1da177e4 3244
8867048b
CD		 3245 qla2x00_free_fcports(vha);
3246
e315cd28 3247 qla2x00_mem_free(ha);
73208dfd 3248
08de2844
GM		 3249 qla82xx_md_free(vha);
3250
73208dfd 3251 qla2x00_free_queues(ha);
1da177e4
LT		 3252}
3253
8867048b
CD		 3254void qla2x00_free_fcports(struct scsi_qla_host *vha)
3255{
3256 fc_port_t *fcport, *tfcport;
3257
3258 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3259 list_del(&fcport->list);
5f16b331 3260 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3261 kfree(fcport);
3262 fcport = NULL;
3263 }
3264}
3265
d97994dc 3266static inline void
e315cd28 3267qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3268 int defer)
3269{
d97994dc 3270 struct fc_rport *rport;
67becc00 3271 scsi_qla_host_t *base_vha;
044d78e1 3272 unsigned long flags;
d97994dc
AV		 3273
3274 if (!fcport->rport)
3275 return;
3276
3277 rport = fcport->rport;
3278 if (defer) {
67becc00 3279 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3280 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3281 fcport->drport = rport;
044d78e1 3282 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3283 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3284 qla2xxx_wake_dpc(base_vha);
2d70c103 3285 } else {
d97994dc 3286 fc_remote_port_delete(rport);
2d70c103
NB		 3287 qlt_fc_port_deleted(vha, fcport);
3288 }
d97994dc
AV		 3289}
3290
1da177e4
LT		 3291/*
3292 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3293 *
3294 * Input: ha = adapter block pointer. fcport = port structure pointer.
3295 *
3296 * Return: None.
3297 *
3298 * Context:
3299 */
e315cd28 3300void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3301 int do_login, int defer)
1da177e4 3302{
8ae6d9c7
GM		 3303 if (IS_QLAFX00(vha->hw)) {
3304 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3305 qla2x00_schedule_rport_del(vha, fcport, defer);
3306 return;
3307 }
3308
2c3dfe3f 3309 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3310 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3311 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3312 qla2x00_schedule_rport_del(vha, fcport, defer);
3313 }
fa2a1ce5 3314 /*
1da177e4
LT		 3315 * We may need to retry the login, so don't change the state of the
3316 * port but do the retries.
3317 */
3318 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3319 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3320
3321 if (!do_login)
3322 return;
3323
3324 if (fcport->login_retry == 0) {
e315cd28
AC		 3325 fcport->login_retry = vha->hw->login_retry_count;
3326 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3327
7c3df132 3328 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3329 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3330 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3331 }
3332}
3333
3334/*
3335 * qla2x00_mark_all_devices_lost
3336 * Updates fcport state when device goes offline.
3337 *
3338 * Input:
3339 * ha = adapter block pointer.
3340 * fcport = port structure pointer.
3341 *
3342 * Return:
3343 * None.
3344 *
3345 * Context:
3346 */
3347void
e315cd28 3348qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3349{
3350 fc_port_t *fcport;
3351
e315cd28 3352 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3353 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3354 continue;
0d6e61bc 3355
1da177e4
LT		 3356 /*
3357 * No point in marking the device as lost, if the device is
3358 * already DEAD.
3359 */
3360 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3361 continue;
e315cd28 3362 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3363 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3364 if (defer)
3365 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3366 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3367 qla2x00_schedule_rport_del(vha, fcport, defer);
3368 }
1da177e4
LT		 3369 }
3370}
3371
3372/*
3373* qla2x00_mem_alloc
3374* Allocates adapter memory.
3375*
3376* Returns:
3377* 0 = success.
e8711085 3378* !0 = failure.
1da177e4 3379*/
e8711085 3380static int
73208dfd
AC		 3381qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3382 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3383{
3384 char name[16];
1da177e4 3385
e8711085 3386 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3387 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3388 if (!ha->init_cb)
e315cd28 3389 goto fail;
e8711085 3390
2d70c103
NB		 3391 if (qlt_mem_alloc(ha) < 0)
3392 goto fail_free_init_cb;
3393
642ef983
CD		 3394 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3395 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3396 if (!ha->gid_list)
2d70c103 3397 goto fail_free_tgt_mem;
1da177e4 3398
e8711085
AV		 3399 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3400 if (!ha->srb_mempool)
e315cd28 3401 goto fail_free_gid_list;
e8711085 3402
7ec0effd 3403 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3404 /* Allocate cache for CT6 Ctx. */
3405 if (!ctx_cachep) {
3406 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3407 sizeof(struct ct6_dsd), 0,
3408 SLAB_HWCACHE_ALIGN, NULL);
3409 if (!ctx_cachep)
3410 goto fail_free_gid_list;
3411 }
3412 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3413 ctx_cachep);
3414 if (!ha->ctx_mempool)
3415 goto fail_free_srb_mempool;
7c3df132
SK		 3416 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3417 "ctx_cachep=%p ctx_mempool=%p.\n",
3418 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3419 }
3420
e8711085
AV		 3421 /* Get memory for cached NVRAM */
3422 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3423 if (!ha->nvram)
a9083016 3424 goto fail_free_ctx_mempool;
e8711085 3425
e315cd28
AC		 3426 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3427 ha->pdev->device);
3428 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3429 DMA_POOL_SIZE, 8, 0);
3430 if (!ha->s_dma_pool)
3431 goto fail_free_nvram;
3432
7c3df132
SK		 3433 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3434 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3435 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3436
7ec0effd 3437 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3438 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3439 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3440 if (!ha->dl_dma_pool) {
7c3df132
SK		 3441 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3442 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3443 goto fail_s_dma_pool;
3444 }
3445
3446 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3447 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3448 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3449 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3450 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3451 goto fail_dl_dma_pool;
3452 }
7c3df132
SK		 3453 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3454 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3455 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3456 }
3457
e8711085
AV		 3458 /* Allocate memory for SNS commands */
3459 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3460 /* Get consistent memory allocated for SNS commands */
e8711085 3461 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3462 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3463 if (!ha->sns_cmd)
e315cd28 3464 goto fail_dma_pool;
7c3df132 3465 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3466 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3467 } else {
e315cd28 3468 /* Get consistent memory allocated for MS IOCB */
e8711085 3469 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3470 &ha->ms_iocb_dma);
e8711085 3471 if (!ha->ms_iocb)
e315cd28
AC		 3472 goto fail_dma_pool;
3473 /* Get consistent memory allocated for CT SNS commands */
e8711085 3474 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3475 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3476 if (!ha->ct_sns)
3477 goto fail_free_ms_iocb;
7c3df132
SK		 3478 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3479 "ms_iocb=%p ct_sns=%p.\n",
3480 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3481 }
3482
e315cd28 3483 /* Allocate memory for request ring */
73208dfd
AC		 3484 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3485 if (!*req) {
7c3df132
SK		 3486 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3487 "Failed to allocate memory for req.\n");
e315cd28
AC		 3488 goto fail_req;
3489 }
73208dfd
AC		 3490 (*req)->length = req_len;
3491 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3492 ((*req)->length + 1) * sizeof(request_t),
3493 &(*req)->dma, GFP_KERNEL);
3494 if (!(*req)->ring) {
7c3df132
SK		 3495 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3496 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3497 goto fail_req_ring;
3498 }
3499 /* Allocate memory for response ring */
73208dfd
AC		 3500 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3501 if (!*rsp) {
7c3df132
SK		 3502 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3503 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3504 goto fail_rsp;
3505 }
73208dfd
AC		 3506 (*rsp)->hw = ha;
3507 (*rsp)->length = rsp_len;
3508 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3509 ((*rsp)->length + 1) * sizeof(response_t),
3510 &(*rsp)->dma, GFP_KERNEL);
3511 if (!(*rsp)->ring) {
7c3df132
SK		 3512 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3513 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3514 goto fail_rsp_ring;
3515 }
73208dfd
AC		 3516 (*req)->rsp = *rsp;
3517 (*rsp)->req = *req;
7c3df132
SK		 3518 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3519 "req=%p req->length=%d req->ring=%p rsp=%p "
3520 "rsp->length=%d rsp->ring=%p.\n",
3521 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3522 (*rsp)->ring);
73208dfd
AC		 3523 /* Allocate memory for NVRAM data for vports */
3524 if (ha->nvram_npiv_size) {
3525 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3526 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3527 if (!ha->npiv_info) {
7c3df132
SK		 3528 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3529 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3530 goto fail_npiv_info;
3531 }
3532 } else
3533 ha->npiv_info = NULL;
e8711085 3534
b64b0e8f 3535 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3536 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3537 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3538 &ha->ex_init_cb_dma);
3539 if (!ha->ex_init_cb)
3540 goto fail_ex_init_cb;
7c3df132
SK		 3541 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3542 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3543 }
3544
a9083016
GM		 3545 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3546
5ff1d584
AV		 3547 /* Get consistent memory allocated for Async Port-Database. */
3548 if (!IS_FWI2_CAPABLE(ha)) {
3549 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3550 &ha->async_pd_dma);
3551 if (!ha->async_pd)
3552 goto fail_async_pd;
7c3df132
SK		 3553 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3554 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3555 }
3556
e315cd28 3557 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3558
3559 /* Allocate memory for our loop_id bitmap */
3560 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3561 GFP_KERNEL);
3562 if (!ha->loop_id_map)
3563 goto fail_async_pd;
3564 else {
3565 qla2x00_set_reserved_loop_ids(ha);
3566 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3567 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3568 }
3569
b2a72ec3 3570 return 0;
e315cd28 3571
5ff1d584
AV		 3572fail_async_pd:
3573 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3574fail_ex_init_cb:
3575 kfree(ha->npiv_info);
73208dfd
AC		 3576fail_npiv_info:
3577 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3578 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3579 (*rsp)->ring = NULL;
3580 (*rsp)->dma = 0;
e315cd28 3581fail_rsp_ring:
73208dfd 3582 kfree(*rsp);
e315cd28 3583fail_rsp:
73208dfd
AC		 3584 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3585 sizeof(request_t), (*req)->ring, (*req)->dma);
3586 (*req)->ring = NULL;
3587 (*req)->dma = 0;
e315cd28 3588fail_req_ring:
73208dfd 3589 kfree(*req);
e315cd28
AC		 3590fail_req:
3591 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3592 ha->ct_sns, ha->ct_sns_dma);
3593 ha->ct_sns = NULL;
3594 ha->ct_sns_dma = 0;
e8711085
AV		 3595fail_free_ms_iocb:
3596 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3597 ha->ms_iocb = NULL;
3598 ha->ms_iocb_dma = 0;
e315cd28 3599fail_dma_pool:
bad75002 3600 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3601 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3602 ha->fcp_cmnd_dma_pool = NULL;
3603 }
3604fail_dl_dma_pool:
bad75002 3605 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3606 dma_pool_destroy(ha->dl_dma_pool);
3607 ha->dl_dma_pool = NULL;
3608 }
3609fail_s_dma_pool:
e315cd28
AC		 3610 dma_pool_destroy(ha->s_dma_pool);
3611 ha->s_dma_pool = NULL;
e8711085
AV		 3612fail_free_nvram:
3613 kfree(ha->nvram);
3614 ha->nvram = NULL;
a9083016
GM		 3615fail_free_ctx_mempool:
3616 mempool_destroy(ha->ctx_mempool);
3617 ha->ctx_mempool = NULL;
e8711085
AV		 3618fail_free_srb_mempool:
3619 mempool_destroy(ha->srb_mempool);
3620 ha->srb_mempool = NULL;
e8711085 3621fail_free_gid_list:
642ef983
CD		 3622 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3623 ha->gid_list,
e315cd28 3624 ha->gid_list_dma);
e8711085
AV		 3625 ha->gid_list = NULL;
3626 ha->gid_list_dma = 0;
2d70c103
NB		 3627fail_free_tgt_mem:
3628 qlt_mem_free(ha);
e315cd28
AC		 3629fail_free_init_cb:
3630 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3631 ha->init_cb_dma);
3632 ha->init_cb = NULL;
3633 ha->init_cb_dma = 0;
e8711085 3634fail:
7c3df132
SK		 3635 ql_log(ql_log_fatal, NULL, 0x0030,
3636 "Memory allocation failure.\n");
e8711085 3637 return -ENOMEM;
1da177e4
LT		 3638}
3639
3640/*
e30d1756
MI		 3641* qla2x00_free_fw_dump
3642* Frees fw dump stuff.
1da177e4
LT		 3643*
3644* Input:
7ec0effd 3645* ha = adapter block pointer
1da177e4 3646*/
a824ebb3 3647static void
e30d1756 3648qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3649{
df613b96 3650 if (ha->fce)
f73cb695
CD		 3651 dma_free_coherent(&ha->pdev->dev,
3652 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3653
f73cb695
CD		 3654 if (ha->eft)
3655 dma_free_coherent(&ha->pdev->dev,
3656 EFT_SIZE, ha->eft, ha->eft_dma);
3657
3658 if (ha->fw_dump)
a7a167bf 3659 vfree(ha->fw_dump);
f73cb695
CD		 3660 if (ha->fw_dump_template)
3661 vfree(ha->fw_dump_template);
3662
e30d1756
MI		 3663 ha->fce = NULL;
3664 ha->fce_dma = 0;
3665 ha->eft = NULL;
3666 ha->eft_dma = 0;
e30d1756 3667 ha->fw_dumped = 0;
61f098dd 3668 ha->fw_dump_cap_flags = 0;
e30d1756 3669 ha->fw_dump_reading = 0;
f73cb695
CD		 3670 ha->fw_dump = NULL;
3671 ha->fw_dump_len = 0;
3672 ha->fw_dump_template = NULL;
3673 ha->fw_dump_template_len = 0;
e30d1756
MI		 3674}
3675
3676/*
3677* qla2x00_mem_free
3678* Frees all adapter allocated memory.
3679*
3680* Input:
3681* ha = adapter block pointer.
3682*/
3683static void
3684qla2x00_mem_free(struct qla_hw_data *ha)
3685{
3686 qla2x00_free_fw_dump(ha);
3687
81178772
SK		 3688 if (ha->mctp_dump)
3689 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3690 ha->mctp_dump_dma);
3691
e30d1756
MI		 3692 if (ha->srb_mempool)
3693 mempool_destroy(ha->srb_mempool);
a7a167bf 3694
11bbc1d8
AV		 3695 if (ha->dcbx_tlv)
3696 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3697 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3698
ce0423f4
AV		 3699 if (ha->xgmac_data)
3700 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3701 ha->xgmac_data, ha->xgmac_data_dma);
3702
1da177e4
LT		 3703 if (ha->sns_cmd)
3704 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3705 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3706
3707 if (ha->ct_sns)
3708 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3709 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3710
88729e53
AV		 3711 if (ha->sfp_data)
3712 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3713
1da177e4
LT		 3714 if (ha->ms_iocb)
3715 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3716
b64b0e8f 3717 if (ha->ex_init_cb)
a9083016
GM		 3718 dma_pool_free(ha->s_dma_pool,
3719 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3720
5ff1d584
AV		 3721 if (ha->async_pd)
3722 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3723
1da177e4
LT		 3724 if (ha->s_dma_pool)
3725 dma_pool_destroy(ha->s_dma_pool);
3726
1da177e4 3727 if (ha->gid_list)
642ef983
CD		 3728 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3729 ha->gid_list, ha->gid_list_dma);
1da177e4 3730
a9083016
GM		 3731 if (IS_QLA82XX(ha)) {
3732 if (!list_empty(&ha->gbl_dsd_list)) {
3733 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3734
3735 /* clean up allocated prev pool */
3736 list_for_each_entry_safe(dsd_ptr,
3737 tdsd_ptr, &ha->gbl_dsd_list, list) {
3738 dma_pool_free(ha->dl_dma_pool,
3739 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3740 list_del(&dsd_ptr->list);
3741 kfree(dsd_ptr);
3742 }
3743 }
3744 }
3745
3746 if (ha->dl_dma_pool)
3747 dma_pool_destroy(ha->dl_dma_pool);
3748
3749 if (ha->fcp_cmnd_dma_pool)
3750 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3751
3752 if (ha->ctx_mempool)
3753 mempool_destroy(ha->ctx_mempool);
3754
2d70c103
NB		 3755 qlt_mem_free(ha);
3756
e315cd28
AC		 3757 if (ha->init_cb)
3758 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3759 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3760 vfree(ha->optrom_buffer);
3761 kfree(ha->nvram);
73208dfd 3762 kfree(ha->npiv_info);
7a67735b 3763 kfree(ha->swl);
5f16b331 3764 kfree(ha->loop_id_map);
1da177e4 3765
e8711085 3766 ha->srb_mempool = NULL;
a9083016 3767 ha->ctx_mempool = NULL;
1da177e4
LT		 3768 ha->sns_cmd = NULL;
3769 ha->sns_cmd_dma = 0;
3770 ha->ct_sns = NULL;
3771 ha->ct_sns_dma = 0;
3772 ha->ms_iocb = NULL;
3773 ha->ms_iocb_dma = 0;
1da177e4
LT		 3774 ha->init_cb = NULL;
3775 ha->init_cb_dma = 0;
b64b0e8f
AV		 3776 ha->ex_init_cb = NULL;
3777 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3778 ha->async_pd = NULL;
3779 ha->async_pd_dma = 0;
1da177e4
LT		 3780
3781 ha->s_dma_pool = NULL;
a9083016
GM		 3782 ha->dl_dma_pool = NULL;
3783 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3784
1da177e4
LT		 3785 ha->gid_list = NULL;
3786 ha->gid_list_dma = 0;
2d70c103
NB		 3787
3788 ha->tgt.atio_ring = NULL;
3789 ha->tgt.atio_dma = 0;
3790 ha->tgt.tgt_vp_map = NULL;
e315cd28 3791}
1da177e4 3792
e315cd28
AC		 3793struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3794 struct qla_hw_data *ha)
3795{
3796 struct Scsi_Host *host;
3797 struct scsi_qla_host *vha = NULL;
854165f4 3798
e315cd28
AC		 3799 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3800 if (host == NULL) {
7c3df132
SK		 3801 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3802 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3803 goto fail;
3804 }
3805
3806 /* Clear our data area */
3807 vha = shost_priv(host);
3808 memset(vha, 0, sizeof(scsi_qla_host_t));
3809
3810 vha->host = host;
3811 vha->host_no = host->host_no;
3812 vha->hw = ha;
3813
3814 INIT_LIST_HEAD(&vha->vp_fcports);
3815 INIT_LIST_HEAD(&vha->work_list);
3816 INIT_LIST_HEAD(&vha->list);
3817
f999f4c1
AV		 3818 spin_lock_init(&vha->work_lock);
3819
e315cd28 3820 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3821 ql_dbg(ql_dbg_init, vha, 0x0041,
3822 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3823 vha->host, vha->hw, vha,
3824 dev_name(&(ha->pdev->dev)));
3825
e315cd28
AC		 3826 return vha;
3827
3828fail:
3829 return vha;
1da177e4
LT		 3830}
3831
01ef66bb 3832static struct qla_work_evt *
f999f4c1 3833qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3834{
3835 struct qla_work_evt *e;
feafb7b1
AE		 3836 uint8_t bail;
3837
3838 QLA_VHA_MARK_BUSY(vha, bail);
3839 if (bail)
3840 return NULL;
0971de7f 3841
f999f4c1 3842 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3843 if (!e) {
3844 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3845 return NULL;
feafb7b1 3846 }
0971de7f
AV		 3847
3848 INIT_LIST_HEAD(&e->list);
3849 e->type = type;
3850 e->flags = QLA_EVT_FLAG_FREE;
3851 return e;
3852}
3853
01ef66bb 3854static int
f999f4c1 3855qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3856{
f999f4c1 3857 unsigned long flags;
0971de7f 3858
f999f4c1 3859 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3860 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3861 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3862 qla2xxx_wake_dpc(vha);
f999f4c1 3863
0971de7f
AV		 3864 return QLA_SUCCESS;
3865}
3866
3867int
e315cd28 3868qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3869 u32 data)
3870{
3871 struct qla_work_evt *e;
3872
f999f4c1 3873 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3874 if (!e)
3875 return QLA_FUNCTION_FAILED;
3876
3877 e->u.aen.code = code;
3878 e->u.aen.data = data;
f999f4c1 3879 return qla2x00_post_work(vha, e);
0971de7f
AV		 3880}
3881
8a659571
AV		 3882int
3883qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3884{
3885 struct qla_work_evt *e;
3886
f999f4c1 3887 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3888 if (!e)
3889 return QLA_FUNCTION_FAILED;
3890
3891 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3892 return qla2x00_post_work(vha, e);
8a659571
AV		 3893}
3894
ac280b67
AV		 3895#define qla2x00_post_async_work(name, type) \
3896int qla2x00_post_async_##name##_work( \
3897 struct scsi_qla_host *vha, \
3898 fc_port_t *fcport, uint16_t *data) \
3899{ \
3900 struct qla_work_evt *e; \
3901 \
3902 e = qla2x00_alloc_work(vha, type); \
3903 if (!e) \
3904 return QLA_FUNCTION_FAILED; \
3905 \
3906 e->u.logio.fcport = fcport; \
3907 if (data) { \
3908 e->u.logio.data[0] = data[0]; \
3909 e->u.logio.data[1] = data[1]; \
3910 } \
3911 return qla2x00_post_work(vha, e); \
3912}
3913
3914qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3915qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3916qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3917qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3918qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3919qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3920
3420d36c
AV		 3921int
3922qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3923{
3924 struct qla_work_evt *e;
3925
3926 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3927 if (!e)
3928 return QLA_FUNCTION_FAILED;
3929
3930 e->u.uevent.code = code;
3931 return qla2x00_post_work(vha, e);
3932}
3933
3934static void
3935qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3936{
3937 char event_string[40];
3938 char *envp[] = { event_string, NULL };
3939
3940 switch (code) {
3941 case QLA_UEVENT_CODE_FW_DUMP:
3942 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3943 vha->host_no);
3944 break;
3945 default:
3946 /* do nothing */
3947 break;
3948 }
3949 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3950}
3951
8ae6d9c7
GM		 3952int
3953qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3954 uint32_t *data, int cnt)
3955{
3956 struct qla_work_evt *e;
3957
3958 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3959 if (!e)
3960 return QLA_FUNCTION_FAILED;
3961
3962 e->u.aenfx.evtcode = evtcode;
3963 e->u.aenfx.count = cnt;
3964 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3965 return qla2x00_post_work(vha, e);
3966}
3967
ac280b67 3968void
e315cd28 3969qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3970{
f999f4c1
AV		 3971 struct qla_work_evt *e, *tmp;
3972 unsigned long flags;
3973 LIST_HEAD(work);
0971de7f 3974
f999f4c1
AV		 3975 spin_lock_irqsave(&vha->work_lock, flags);
3976 list_splice_init(&vha->work_list, &work);
3977 spin_unlock_irqrestore(&vha->work_lock, flags);
3978
3979 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3980 list_del_init(&e->list);
0971de7f
AV		 3981
3982 switch (e->type) {
3983 case QLA_EVT_AEN:
e315cd28 3984 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3985 e->u.aen.code, e->u.aen.data);
3986 break;
8a659571
AV		 3987 case QLA_EVT_IDC_ACK:
3988 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3989 break;
ac280b67
AV		 3990 case QLA_EVT_ASYNC_LOGIN:
3991 qla2x00_async_login(vha, e->u.logio.fcport,
3992 e->u.logio.data);
3993 break;
3994 case QLA_EVT_ASYNC_LOGIN_DONE:
3995 qla2x00_async_login_done(vha, e->u.logio.fcport,
3996 e->u.logio.data);
3997 break;
3998 case QLA_EVT_ASYNC_LOGOUT:
3999 qla2x00_async_logout(vha, e->u.logio.fcport);
4000 break;
4001 case QLA_EVT_ASYNC_LOGOUT_DONE:
4002 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4003 e->u.logio.data);
4004 break;
5ff1d584
AV		 4005 case QLA_EVT_ASYNC_ADISC:
4006 qla2x00_async_adisc(vha, e->u.logio.fcport,
4007 e->u.logio.data);
4008 break;
4009 case QLA_EVT_ASYNC_ADISC_DONE:
4010 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4011 e->u.logio.data);
4012 break;
3420d36c
AV		 4013 case QLA_EVT_UEVENT:
4014 qla2x00_uevent_emit(vha, e->u.uevent.code);
4015 break;
8ae6d9c7
GM		 4016 case QLA_EVT_AENFX:
4017 qlafx00_process_aen(vha, e);
4018 break;
0971de7f
AV		 4019 }
4020 if (e->flags & QLA_EVT_FLAG_FREE)
4021 kfree(e);
feafb7b1
AE		 4022
4023 /* For each work completed decrement vha ref count */
4024 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4025 }
e315cd28 4026}
f999f4c1 4027
e315cd28
AC		 4028/* Relogins all the fcports of a vport
4029 * Context: dpc thread
4030 */
4031void qla2x00_relogin(struct scsi_qla_host *vha)
4032{
4033 fc_port_t *fcport;
c6b2fca8 4034 int status;
e315cd28
AC		 4035 uint16_t next_loopid = 0;
4036 struct qla_hw_data *ha = vha->hw;
ac280b67 4037 uint16_t data[2];
e315cd28
AC		 4038
4039 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4040 /*
4041 * If the port is not ONLINE then try to login
4042 * to it if we haven't run out of retries.
4043 */
5ff1d584
AV		 4044 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4045 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4046 fcport->login_retry--;
e315cd28 4047 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4048 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4049 ha->isp_ops->fabric_logout(vha,
4050 fcport->loop_id,
4051 fcport->d_id.b.domain,
4052 fcport->d_id.b.area,
4053 fcport->d_id.b.al_pa);
4054
03bcfb57
JC		 4055 if (fcport->loop_id == FC_NO_LOOP_ID) {
4056 fcport->loop_id = next_loopid =
4057 ha->min_external_loopid;
4058 status = qla2x00_find_new_loop_id(
4059 vha, fcport);
4060 if (status != QLA_SUCCESS) {
4061 /* Ran out of IDs to use */
4062 break;
4063 }
4064 }
4065
ac280b67 4066 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4067 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4068 data[0] = 0;
4069 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4070 status = qla2x00_post_async_login_work(
4071 vha, fcport, data);
4072 if (status == QLA_SUCCESS)
4073 continue;
4074 /* Attempt a retry. */
4075 status = 1;
aaf4d3e2 4076 } else {
ac280b67
AV		 4077 status = qla2x00_fabric_login(vha,
4078 fcport, &next_loopid);
aaf4d3e2
SK		 4079 if (status == QLA_SUCCESS) {
4080 int status2;
4081 uint8_t opts;
4082
4083 opts = 0;
4084 if (fcport->flags &
4085 FCF_FCP2_DEVICE)
4086 opts |= BIT_1;
03003960
SK		 4087 status2 =
4088 qla2x00_get_port_database(
4089 vha, fcport, opts);
aaf4d3e2
SK		 4090 if (status2 != QLA_SUCCESS)
4091 status = 1;
4092 }
4093 }
e315cd28
AC		 4094 } else
4095 status = qla2x00_local_device_login(vha,
4096 fcport);
4097
e315cd28
AC		 4098 if (status == QLA_SUCCESS) {
4099 fcport->old_loop_id = fcport->loop_id;
4100
7c3df132
SK		 4101 ql_dbg(ql_dbg_disc, vha, 0x2003,
4102 "Port login OK: logged in ID 0x%x.\n",
4103 fcport->loop_id);
e315cd28
AC		 4104
4105 qla2x00_update_fcport(vha, fcport);
4106
4107 } else if (status == 1) {
4108 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4109 /* retry the login again */
7c3df132
SK		 4110 ql_dbg(ql_dbg_disc, vha, 0x2007,
4111 "Retrying %d login again loop_id 0x%x.\n",
4112 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4113 } else {
4114 fcport->login_retry = 0;
4115 }
4116
4117 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4118 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4119 }
4120 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4121 break;
0971de7f 4122 }
0971de7f
AV		 4123}
4124
7d613ac6
SV		 4125/* Schedule work on any of the dpc-workqueues */
4126void
4127qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4128{
4129 struct qla_hw_data *ha = base_vha->hw;
4130
4131 switch (work_code) {
4132 case MBA_IDC_AEN: /* 0x8200 */
4133 if (ha->dpc_lp_wq)
4134 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4135 break;
4136
4137 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4138 if (!ha->flags.nic_core_reset_hdlr_active) {
4139 if (ha->dpc_hp_wq)
4140 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4141 } else
4142 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4143 "NIC Core reset is already active. Skip "
4144 "scheduling it again.\n");
4145 break;
4146 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4147 if (ha->dpc_hp_wq)
4148 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4149 break;
4150 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4151 if (ha->dpc_hp_wq)
4152 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4153 break;
4154 default:
4155 ql_log(ql_log_warn, base_vha, 0xb05f,
4156 "Unknow work-code=0x%x.\n", work_code);
4157 }
4158
4159 return;
4160}
4161
4162/* Work: Perform NIC Core Unrecoverable state handling */
4163void
4164qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4165{
4166 struct qla_hw_data *ha =
2ad1b67c 4167 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4168 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4169 uint32_t dev_state = 0;
4170
4171 qla83xx_idc_lock(base_vha, 0);
4172 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4173 qla83xx_reset_ownership(base_vha);
4174 if (ha->flags.nic_core_reset_owner) {
4175 ha->flags.nic_core_reset_owner = 0;
4176 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4177 QLA8XXX_DEV_FAILED);
4178 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4179 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4180 }
4181 qla83xx_idc_unlock(base_vha, 0);
4182}
4183
4184/* Work: Execute IDC state handler */
4185void
4186qla83xx_idc_state_handler_work(struct work_struct *work)
4187{
4188 struct qla_hw_data *ha =
2ad1b67c 4189 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4190 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4191 uint32_t dev_state = 0;
4192
4193 qla83xx_idc_lock(base_vha, 0);
4194 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4195 if (dev_state == QLA8XXX_DEV_FAILED ||
4196 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4197 qla83xx_idc_state_handler(base_vha);
4198 qla83xx_idc_unlock(base_vha, 0);
4199}
4200
fa492630 4201static int
7d613ac6
SV		 4202qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4203{
4204 int rval = QLA_SUCCESS;
4205 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4206 uint32_t heart_beat_counter1, heart_beat_counter2;
4207
4208 do {
4209 if (time_after(jiffies, heart_beat_wait)) {
4210 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4211 "Nic Core f/w is not alive.\n");
4212 rval = QLA_FUNCTION_FAILED;
4213 break;
4214 }
4215
4216 qla83xx_idc_lock(base_vha, 0);
4217 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4218 &heart_beat_counter1);
4219 qla83xx_idc_unlock(base_vha, 0);
4220 msleep(100);
4221 qla83xx_idc_lock(base_vha, 0);
4222 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4223 &heart_beat_counter2);
4224 qla83xx_idc_unlock(base_vha, 0);
4225 } while (heart_beat_counter1 == heart_beat_counter2);
4226
4227 return rval;
4228}
4229
4230/* Work: Perform NIC Core Reset handling */
4231void
4232qla83xx_nic_core_reset_work(struct work_struct *work)
4233{
4234 struct qla_hw_data *ha =
4235 container_of(work, struct qla_hw_data, nic_core_reset);
4236 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4237 uint32_t dev_state = 0;
4238
81178772
SK		 4239 if (IS_QLA2031(ha)) {
4240 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4241 ql_log(ql_log_warn, base_vha, 0xb081,
4242 "Failed to dump mctp\n");
4243 return;
4244 }
4245
7d613ac6
SV		 4246 if (!ha->flags.nic_core_reset_hdlr_active) {
4247 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4248 qla83xx_idc_lock(base_vha, 0);
4249 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4250 &dev_state);
4251 qla83xx_idc_unlock(base_vha, 0);
4252 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4253 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4254 "Nic Core f/w is alive.\n");
4255 return;
4256 }
4257 }
4258
4259 ha->flags.nic_core_reset_hdlr_active = 1;
4260 if (qla83xx_nic_core_reset(base_vha)) {
4261 /* NIC Core reset failed. */
4262 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4263 "NIC Core reset failed.\n");
4264 }
4265 ha->flags.nic_core_reset_hdlr_active = 0;
4266 }
4267}
4268
4269/* Work: Handle 8200 IDC aens */
4270void
4271qla83xx_service_idc_aen(struct work_struct *work)
4272{
4273 struct qla_hw_data *ha =
4274 container_of(work, struct qla_hw_data, idc_aen);
4275 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4276 uint32_t dev_state, idc_control;
4277
4278 qla83xx_idc_lock(base_vha, 0);
4279 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4280 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4281 qla83xx_idc_unlock(base_vha, 0);
4282 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4283 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4284 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4285 "Application requested NIC Core Reset.\n");
4286 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4287 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4288 QLA_SUCCESS) {
4289 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4290 "Other protocol driver requested NIC Core Reset.\n");
4291 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4292 }
4293 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4294 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4295 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4296 }
4297}
4298
4299static void
4300qla83xx_wait_logic(void)
4301{
4302 int i;
4303
4304 /* Yield CPU */
4305 if (!in_interrupt()) {
4306 /*
4307 * Wait about 200ms before retrying again.
4308 * This controls the number of retries for single
4309 * lock operation.
4310 */
4311 msleep(100);
4312 schedule();
4313 } else {
4314 for (i = 0; i < 20; i++)
4315 cpu_relax(); /* This a nop instr on i386 */
4316 }
4317}
4318
fa492630 4319static int
7d613ac6
SV		 4320qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4321{
4322 int rval;
4323 uint32_t data;
4324 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4325 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4326 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4327 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4328 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4329
4330 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4331 if (rval)
4332 return rval;
4333
4334 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4335 return QLA_SUCCESS;
4336 } else {
4337 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4338 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4339 data);
4340 if (rval)
4341 return rval;
4342
4343 msleep(200);
4344
4345 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4346 &data);
4347 if (rval)
4348 return rval;
4349
4350 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4351 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4352 ~(idc_lck_rcvry_stage_mask));
4353 rval = qla83xx_wr_reg(base_vha,
4354 QLA83XX_IDC_LOCK_RECOVERY, data);
4355 if (rval)
4356 return rval;
4357
4358 /* Forcefully perform IDC UnLock */
4359 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4360 &data);
4361 if (rval)
4362 return rval;
4363 /* Clear lock-id by setting 0xff */
4364 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4365 0xff);
4366 if (rval)
4367 return rval;
4368 /* Clear lock-recovery by setting 0x0 */
4369 rval = qla83xx_wr_reg(base_vha,
4370 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4371 if (rval)
4372 return rval;
4373 } else
4374 return QLA_SUCCESS;
4375 }
4376
4377 return rval;
4378}
4379
fa492630 4380static int
7d613ac6
SV		 4381qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4382{
4383 int rval = QLA_SUCCESS;
4384 uint32_t o_drv_lockid, n_drv_lockid;
4385 unsigned long lock_recovery_timeout;
4386
4387 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4388retry_lockid:
4389 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4390 if (rval)
4391 goto exit;
4392
4393 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4394 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4395 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4396 return QLA_SUCCESS;
4397 else
4398 return QLA_FUNCTION_FAILED;
4399 }
4400
4401 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4402 if (rval)
4403 goto exit;
4404
4405 if (o_drv_lockid == n_drv_lockid) {
4406 qla83xx_wait_logic();
4407 goto retry_lockid;
4408 } else
4409 return QLA_SUCCESS;
4410
4411exit:
4412 return rval;
4413}
4414
4415void
4416qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4417{
4418 uint16_t options = (requester_id << 15) | BIT_6;
4419 uint32_t data;
6c315553 4420 uint32_t lock_owner;
7d613ac6
SV		 4421 struct qla_hw_data *ha = base_vha->hw;
4422
4423 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4424retry_lock:
4425 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4426 == QLA_SUCCESS) {
4427 if (data) {
4428 /* Setting lock-id to our function-number */
4429 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4430 ha->portnum);
4431 } else {
6c315553
SK		 4432 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4433 &lock_owner);
7d613ac6 4434 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4435 "Failed to acquire IDC lock, acquired by %d, "
4436 "retrying...\n", lock_owner);
7d613ac6
SV		 4437
4438 /* Retry/Perform IDC-Lock recovery */
4439 if (qla83xx_idc_lock_recovery(base_vha)
4440 == QLA_SUCCESS) {
4441 qla83xx_wait_logic();
4442 goto retry_lock;
4443 } else
4444 ql_log(ql_log_warn, base_vha, 0xb075,
4445 "IDC Lock recovery FAILED.\n");
4446 }
4447
4448 }
4449
4450 return;
4451
4452 /* XXX: IDC-lock implementation using access-control mbx */
4453retry_lock2:
4454 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4455 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4456 "Failed to acquire IDC lock. retrying...\n");
4457 /* Retry/Perform IDC-Lock recovery */
4458 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4459 qla83xx_wait_logic();
4460 goto retry_lock2;
4461 } else
4462 ql_log(ql_log_warn, base_vha, 0xb076,
4463 "IDC Lock recovery FAILED.\n");
4464 }
4465
4466 return;
4467}
4468
4469void
4470qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4471{
4472 uint16_t options = (requester_id << 15) | BIT_7, retry;
4473 uint32_t data;
4474 struct qla_hw_data *ha = base_vha->hw;
4475
4476 /* IDC-unlock implementation using driver-unlock/lock-id
4477 * remote registers
4478 */
4479 retry = 0;
4480retry_unlock:
4481 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4482 == QLA_SUCCESS) {
4483 if (data == ha->portnum) {
4484 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4485 /* Clearing lock-id by setting 0xff */
4486 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4487 } else if (retry < 10) {
4488 /* SV: XXX: IDC unlock retrying needed here? */
4489
4490 /* Retry for IDC-unlock */
4491 qla83xx_wait_logic();
4492 retry++;
4493 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4494 "Failed to release IDC lock, retyring=%d\n", retry);
4495 goto retry_unlock;
4496 }
4497 } else if (retry < 10) {
4498 /* Retry for IDC-unlock */
4499 qla83xx_wait_logic();
4500 retry++;
4501 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4502 "Failed to read drv-lockid, retyring=%d\n", retry);
4503 goto retry_unlock;
4504 }
4505
4506 return;
4507
4508 /* XXX: IDC-unlock implementation using access-control mbx */
4509 retry = 0;
4510retry_unlock2:
4511 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4512 if (retry < 10) {
4513 /* Retry for IDC-unlock */
4514 qla83xx_wait_logic();
4515 retry++;
4516 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4517 "Failed to release IDC lock, retyring=%d\n", retry);
4518 goto retry_unlock2;
4519 }
4520 }
4521
4522 return;
4523}
4524
4525int
4526__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4527{
4528 int rval = QLA_SUCCESS;
4529 struct qla_hw_data *ha = vha->hw;
4530 uint32_t drv_presence;
4531
4532 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4533 if (rval == QLA_SUCCESS) {
4534 drv_presence |= (1 << ha->portnum);
4535 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4536 drv_presence);
4537 }
4538
4539 return rval;
4540}
4541
4542int
4543qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4544{
4545 int rval = QLA_SUCCESS;
4546
4547 qla83xx_idc_lock(vha, 0);
4548 rval = __qla83xx_set_drv_presence(vha);
4549 qla83xx_idc_unlock(vha, 0);
4550
4551 return rval;
4552}
4553
4554int
4555__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4556{
4557 int rval = QLA_SUCCESS;
4558 struct qla_hw_data *ha = vha->hw;
4559 uint32_t drv_presence;
4560
4561 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4562 if (rval == QLA_SUCCESS) {
4563 drv_presence &= ~(1 << ha->portnum);
4564 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4565 drv_presence);
4566 }
4567
4568 return rval;
4569}
4570
4571int
4572qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4573{
4574 int rval = QLA_SUCCESS;
4575
4576 qla83xx_idc_lock(vha, 0);
4577 rval = __qla83xx_clear_drv_presence(vha);
4578 qla83xx_idc_unlock(vha, 0);
4579
4580 return rval;
4581}
4582
fa492630 4583static void
7d613ac6
SV		 4584qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4585{
4586 struct qla_hw_data *ha = vha->hw;
4587 uint32_t drv_ack, drv_presence;
4588 unsigned long ack_timeout;
4589
4590 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4591 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4592 while (1) {
4593 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4594 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4595 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4596 break;
4597
4598 if (time_after_eq(jiffies, ack_timeout)) {
4599 ql_log(ql_log_warn, vha, 0xb067,
4600 "RESET ACK TIMEOUT! drv_presence=0x%x "
4601 "drv_ack=0x%x\n", drv_presence, drv_ack);
4602 /*
4603 * The function(s) which did not ack in time are forced
4604 * to withdraw any further participation in the IDC
4605 * reset.
4606 */
4607 if (drv_ack != drv_presence)
4608 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4609 drv_ack);
4610 break;
4611 }
4612
4613 qla83xx_idc_unlock(vha, 0);
4614 msleep(1000);
4615 qla83xx_idc_lock(vha, 0);
4616 }
4617
4618 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4619 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4620}
4621
fa492630 4622static int
7d613ac6
SV		 4623qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4624{
4625 int rval = QLA_SUCCESS;
4626 uint32_t idc_control;
4627
4628 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4629 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4630
4631 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4632 __qla83xx_get_idc_control(vha, &idc_control);
4633 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4634 __qla83xx_set_idc_control(vha, 0);
4635
4636 qla83xx_idc_unlock(vha, 0);
4637 rval = qla83xx_restart_nic_firmware(vha);
4638 qla83xx_idc_lock(vha, 0);
4639
4640 if (rval != QLA_SUCCESS) {
4641 ql_log(ql_log_fatal, vha, 0xb06a,
4642 "Failed to restart NIC f/w.\n");
4643 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4644 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4645 } else {
4646 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4647 "Success in restarting nic f/w.\n");
4648 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4649 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4650 }
4651
4652 return rval;
4653}
4654
4655/* Assumes idc_lock always held on entry */
4656int
4657qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4658{
4659 struct qla_hw_data *ha = base_vha->hw;
4660 int rval = QLA_SUCCESS;
4661 unsigned long dev_init_timeout;
4662 uint32_t dev_state;
4663
4664 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4665 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4666
4667 while (1) {
4668
4669 if (time_after_eq(jiffies, dev_init_timeout)) {
4670 ql_log(ql_log_warn, base_vha, 0xb06e,
4671 "Initialization TIMEOUT!\n");
4672 /* Init timeout. Disable further NIC Core
4673 * communication.
4674 */
4675 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4676 QLA8XXX_DEV_FAILED);
4677 ql_log(ql_log_info, base_vha, 0xb06f,
4678 "HW State: FAILED.\n");
4679 }
4680
4681 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4682 switch (dev_state) {
4683 case QLA8XXX_DEV_READY:
4684 if (ha->flags.nic_core_reset_owner)
4685 qla83xx_idc_audit(base_vha,
4686 IDC_AUDIT_COMPLETION);
4687 ha->flags.nic_core_reset_owner = 0;
4688 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4689 "Reset_owner reset by 0x%x.\n",
4690 ha->portnum);
4691 goto exit;
4692 case QLA8XXX_DEV_COLD:
4693 if (ha->flags.nic_core_reset_owner)
4694 rval = qla83xx_device_bootstrap(base_vha);
4695 else {
4696 /* Wait for AEN to change device-state */
4697 qla83xx_idc_unlock(base_vha, 0);
4698 msleep(1000);
4699 qla83xx_idc_lock(base_vha, 0);
4700 }
4701 break;
4702 case QLA8XXX_DEV_INITIALIZING:
4703 /* Wait for AEN to change device-state */
4704 qla83xx_idc_unlock(base_vha, 0);
4705 msleep(1000);
4706 qla83xx_idc_lock(base_vha, 0);
4707 break;
4708 case QLA8XXX_DEV_NEED_RESET:
4709 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4710 qla83xx_need_reset_handler(base_vha);
4711 else {
4712 /* Wait for AEN to change device-state */
4713 qla83xx_idc_unlock(base_vha, 0);
4714 msleep(1000);
4715 qla83xx_idc_lock(base_vha, 0);
4716 }
4717 /* reset timeout value after need reset handler */
4718 dev_init_timeout = jiffies +
4719 (ha->fcoe_dev_init_timeout * HZ);
4720 break;
4721 case QLA8XXX_DEV_NEED_QUIESCENT:
4722 /* XXX: DEBUG for now */
4723 qla83xx_idc_unlock(base_vha, 0);
4724 msleep(1000);
4725 qla83xx_idc_lock(base_vha, 0);
4726 break;
4727 case QLA8XXX_DEV_QUIESCENT:
4728 /* XXX: DEBUG for now */
4729 if (ha->flags.quiesce_owner)
4730 goto exit;
4731
4732 qla83xx_idc_unlock(base_vha, 0);
4733 msleep(1000);
4734 qla83xx_idc_lock(base_vha, 0);
4735 dev_init_timeout = jiffies +
4736 (ha->fcoe_dev_init_timeout * HZ);
4737 break;
4738 case QLA8XXX_DEV_FAILED:
4739 if (ha->flags.nic_core_reset_owner)
4740 qla83xx_idc_audit(base_vha,
4741 IDC_AUDIT_COMPLETION);
4742 ha->flags.nic_core_reset_owner = 0;
4743 __qla83xx_clear_drv_presence(base_vha);
4744 qla83xx_idc_unlock(base_vha, 0);
4745 qla8xxx_dev_failed_handler(base_vha);
4746 rval = QLA_FUNCTION_FAILED;
4747 qla83xx_idc_lock(base_vha, 0);
4748 goto exit;
4749 case QLA8XXX_BAD_VALUE:
4750 qla83xx_idc_unlock(base_vha, 0);
4751 msleep(1000);
4752 qla83xx_idc_lock(base_vha, 0);
4753 break;
4754 default:
4755 ql_log(ql_log_warn, base_vha, 0xb071,
4756 "Unknow Device State: %x.\n", dev_state);
4757 qla83xx_idc_unlock(base_vha, 0);
4758 qla8xxx_dev_failed_handler(base_vha);
4759 rval = QLA_FUNCTION_FAILED;
4760 qla83xx_idc_lock(base_vha, 0);
4761 goto exit;
4762 }
4763 }
4764
4765exit:
4766 return rval;
4767}
4768
f3ddac19
CD		 4769void
4770qla2x00_disable_board_on_pci_error(struct work_struct *work)
4771{
4772 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4773 board_disable);
4774 struct pci_dev *pdev = ha->pdev;
4775 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4776
4777 ql_log(ql_log_warn, base_vha, 0x015b,
4778 "Disabling adapter.\n");
4779
4780 set_bit(UNLOADING, &base_vha->dpc_flags);
4781
4782 qla2x00_delete_all_vps(ha, base_vha);
4783
4784 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4785
4786 qla2x00_dfs_remove(base_vha);
4787
4788 qla84xx_put_chip(base_vha);
4789
4790 if (base_vha->timer_active)
4791 qla2x00_stop_timer(base_vha);
4792
4793 base_vha->flags.online = 0;
4794
4795 qla2x00_destroy_deferred_work(ha);
4796
4797 /*
4798 * Do not try to stop beacon blink as it will issue a mailbox
4799 * command.
4800 */
4801 qla2x00_free_sysfs_attr(base_vha, false);
4802
4803 fc_remove_host(base_vha->host);
4804
4805 scsi_remove_host(base_vha->host);
4806
4807 base_vha->flags.init_done = 0;
4808 qla25xx_delete_queues(base_vha);
4809 qla2x00_free_irqs(base_vha);
4810 qla2x00_free_fcports(base_vha);
4811 qla2x00_mem_free(ha);
4812 qla82xx_md_free(base_vha);
4813 qla2x00_free_queues(ha);
4814
f3ddac19
CD		 4815 qla2x00_unmap_iobases(ha);
4816
4817 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4818 pci_disable_pcie_error_reporting(pdev);
4819 pci_disable_device(pdev);
f3ddac19 4820
beb9e315
JL		 4821 /*
4822 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4823 */
f3ddac19
CD		 4824}
4825
1da177e4
LT		 4826/**************************************************************************
4827* qla2x00_do_dpc
4828* This kernel thread is a task that is schedule by the interrupt handler
4829* to perform the background processing for interrupts.
4830*
4831* Notes:
4832* This task always run in the context of a kernel thread. It
4833* is kick-off by the driver's detect code and starts up
4834* up one per adapter. It immediately goes to sleep and waits for
4835* some fibre event. When either the interrupt handler or
4836* the timer routine detects a event it will one of the task
4837* bits then wake us up.
4838**************************************************************************/
4839static int
4840qla2x00_do_dpc(void *data)
4841{
2c3dfe3f 4842 int rval;
e315cd28
AC		 4843 scsi_qla_host_t *base_vha;
4844 struct qla_hw_data *ha;
1da177e4 4845
e315cd28
AC		 4846 ha = (struct qla_hw_data *)data;
4847 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4848
8698a745 4849 set_user_nice(current, MIN_NICE);
1da177e4 4850
563585ec 4851 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4852 while (!kthread_should_stop()) {
7c3df132
SK		 4853 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4854 "DPC handler sleeping.\n");
1da177e4 4855
39a11240
CH		 4856 schedule();
4857 __set_current_state(TASK_RUNNING);
1da177e4 4858
c142caf0
AV		 4859 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4860 goto end_loop;
1da177e4 4861
85880801 4862 if (ha->flags.eeh_busy) {
7c3df132
SK		 4863 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4864 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4865 goto end_loop;
85880801
AV		 4866 }
4867
1da177e4
LT		 4868 ha->dpc_active = 1;
4869
5f28d2d7
SK		 4870 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4871 "DPC handler waking up, dpc_flags=0x%lx.\n",
4872 base_vha->dpc_flags);
1da177e4 4873
e315cd28 4874 qla2x00_do_work(base_vha);
0971de7f 4875
7ec0effd
AD		 4876 if (IS_P3P_TYPE(ha)) {
4877 if (IS_QLA8044(ha)) {
4878 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4879 &base_vha->dpc_flags)) {
4880 qla8044_idc_lock(ha);
4881 qla8044_wr_direct(base_vha,
4882 QLA8044_CRB_DEV_STATE_INDEX,
4883 QLA8XXX_DEV_FAILED);
4884 qla8044_idc_unlock(ha);
4885 ql_log(ql_log_info, base_vha, 0x4004,
4886 "HW State: FAILED.\n");
4887 qla8044_device_state_handler(base_vha);
4888 continue;
4889 }
4890
4891 } else {
4892 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4893 &base_vha->dpc_flags)) {
4894 qla82xx_idc_lock(ha);
4895 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4896 QLA8XXX_DEV_FAILED);
4897 qla82xx_idc_unlock(ha);
4898 ql_log(ql_log_info, base_vha, 0x0151,
4899 "HW State: FAILED.\n");
4900 qla82xx_device_state_handler(base_vha);
4901 continue;
4902 }
a9083016
GM		 4903 }
4904
4905 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4906 &base_vha->dpc_flags)) {
4907
7c3df132
SK		 4908 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4909 "FCoE context reset scheduled.\n");
a9083016
GM		 4910 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4911 &base_vha->dpc_flags))) {
4912 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4913 /* FCoE-ctx reset failed.
4914 * Escalate to chip-reset
4915 */
4916 set_bit(ISP_ABORT_NEEDED,
4917 &base_vha->dpc_flags);
4918 }
4919 clear_bit(ABORT_ISP_ACTIVE,
4920 &base_vha->dpc_flags);
4921 }
4922
7c3df132
SK		 4923 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4924 "FCoE context reset end.\n");
a9083016 4925 }
8ae6d9c7
GM		 4926 } else if (IS_QLAFX00(ha)) {
4927 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4928 &base_vha->dpc_flags)) {
4929 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4930 "Firmware Reset Recovery\n");
4931 if (qlafx00_reset_initialize(base_vha)) {
4932 /* Failed. Abort isp later. */
4933 if (!test_bit(UNLOADING,
f92f82d6 4934 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 4935 set_bit(ISP_UNRECOVERABLE,
4936 &base_vha->dpc_flags);
4937 ql_dbg(ql_dbg_dpc, base_vha,
4938 0x4021,
4939 "Reset Recovery Failed\n");
f92f82d6 4940 }
8ae6d9c7
GM		 4941 }
4942 }
4943
4944 if (test_and_clear_bit(FX00_TARGET_SCAN,
4945 &base_vha->dpc_flags)) {
4946 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4947 "ISPFx00 Target Scan scheduled\n");
4948 if (qlafx00_rescan_isp(base_vha)) {
4949 if (!test_bit(UNLOADING,
4950 &base_vha->dpc_flags))
4951 set_bit(ISP_UNRECOVERABLE,
4952 &base_vha->dpc_flags);
4953 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4954 "ISPFx00 Target Scan Failed\n");
4955 }
4956 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4957 "ISPFx00 Target Scan End\n");
4958 }
e8f5e95d
AB		 4959 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4960 &base_vha->dpc_flags)) {
4961 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4962 "ISPFx00 Host Info resend scheduled\n");
4963 qlafx00_fx_disc(base_vha,
4964 &base_vha->hw->mr.fcport,
4965 FXDISC_REG_HOST_INFO);
4966 }
a9083016
GM		 4967 }
4968
e315cd28
AC		 4969 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4970 &base_vha->dpc_flags)) {
1da177e4 4971
7c3df132
SK		 4972 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4973 "ISP abort scheduled.\n");
1da177e4 4974 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4975 &base_vha->dpc_flags))) {
1da177e4 4976
a9083016 4977 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4978 /* failed. retry later */
4979 set_bit(ISP_ABORT_NEEDED,
e315cd28 4980 &base_vha->dpc_flags);
99363ef8 4981 }
e315cd28
AC		 4982 clear_bit(ABORT_ISP_ACTIVE,
4983 &base_vha->dpc_flags);
99363ef8
SJ		 4984 }
4985
7c3df132
SK		 4986 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4987 "ISP abort end.\n");
1da177e4
LT		 4988 }
4989
a394aac8
DJ		 4990 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4991 &base_vha->dpc_flags)) {
e315cd28 4992 qla2x00_update_fcports(base_vha);
c9c5ced9 4993 }
d97994dc 4994
2d70c103
NB		 4995 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4996 int ret;
4997 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4998 if (ret != QLA_SUCCESS)
4999 ql_log(ql_log_warn, base_vha, 0x121,
5000 "Failed to enable receiving of RSCN "
5001 "requests: 0x%x.\n", ret);
5002 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5003 }
5004
8ae6d9c7
GM		 5005 if (IS_QLAFX00(ha))
5006 goto loop_resync_check;
5007
579d12b5 5008 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5009 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5010 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5011 if (IS_P3P_TYPE(ha)) {
5012 if (IS_QLA82XX(ha))
5013 qla82xx_device_state_handler(base_vha);
5014 if (IS_QLA8044(ha))
5015 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5016 clear_bit(ISP_QUIESCE_NEEDED,
5017 &base_vha->dpc_flags);
5018 if (!ha->flags.quiesce_owner) {
5019 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5020 if (IS_QLA82XX(ha)) {
5021 qla82xx_idc_lock(ha);
5022 qla82xx_clear_qsnt_ready(
5023 base_vha);
5024 qla82xx_idc_unlock(ha);
5025 } else if (IS_QLA8044(ha)) {
5026 qla8044_idc_lock(ha);
5027 qla8044_clear_qsnt_ready(
5028 base_vha);
5029 qla8044_idc_unlock(ha);
5030 }
8fcd6b8b
CD		 5031 }
5032 } else {
5033 clear_bit(ISP_QUIESCE_NEEDED,
5034 &base_vha->dpc_flags);
5035 qla2x00_quiesce_io(base_vha);
579d12b5 5036 }
7c3df132
SK		 5037 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5038 "Quiescence mode end.\n");
579d12b5
SK		 5039 }
5040
e315cd28 5041 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5042 &base_vha->dpc_flags) &&
e315cd28 5043 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5044
7c3df132
SK		 5045 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5046 "Reset marker scheduled.\n");
e315cd28
AC		 5047 qla2x00_rst_aen(base_vha);
5048 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5049 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5050 "Reset marker end.\n");
1da177e4
LT		 5051 }
5052
5053 /* Retry each device up to login retry count */
e315cd28
AC		 5054 if ((test_and_clear_bit(RELOGIN_NEEDED,
5055 &base_vha->dpc_flags)) &&
5056 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5057 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5058
7c3df132
SK		 5059 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5060 "Relogin scheduled.\n");
e315cd28 5061 qla2x00_relogin(base_vha);
7c3df132
SK		 5062 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5063 "Relogin end.\n");
1da177e4 5064 }
8ae6d9c7 5065loop_resync_check:
e315cd28 5066 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5067 &base_vha->dpc_flags)) {
1da177e4 5068
7c3df132
SK		 5069 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5070 "Loop resync scheduled.\n");
1da177e4
LT		 5071
5072 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5073 &base_vha->dpc_flags))) {
1da177e4 5074
e315cd28 5075 rval = qla2x00_loop_resync(base_vha);
1da177e4 5076
e315cd28
AC		 5077 clear_bit(LOOP_RESYNC_ACTIVE,
5078 &base_vha->dpc_flags);
1da177e4
LT		 5079 }
5080
7c3df132
SK		 5081 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5082 "Loop resync end.\n");
1da177e4
LT		 5083 }
5084
8ae6d9c7
GM		 5085 if (IS_QLAFX00(ha))
5086 goto intr_on_check;
5087
e315cd28
AC		 5088 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5089 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5090 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5091 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5092 }
5093
8ae6d9c7 5094intr_on_check:
1da177e4 5095 if (!ha->interrupts_on)
fd34f556 5096 ha->isp_ops->enable_intrs(ha);
1da177e4 5097
e315cd28 5098 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5099 &base_vha->dpc_flags)) {
5100 if (ha->beacon_blink_led == 1)
5101 ha->isp_ops->beacon_blink(base_vha);
5102 }
f6df144c 5103
8ae6d9c7
GM		 5104 if (!IS_QLAFX00(ha))
5105 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5106
1da177e4 5107 ha->dpc_active = 0;
c142caf0 5108end_loop:
563585ec 5109 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5110 } /* End of while(1) */
563585ec 5111 __set_current_state(TASK_RUNNING);
1da177e4 5112
7c3df132
SK		 5113 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5114 "DPC handler exiting.\n");
1da177e4
LT		 5115
5116 /*
5117 * Make sure that nobody tries to wake us up again.
5118 */
1da177e4
LT		 5119 ha->dpc_active = 0;
5120
ac280b67
AV		 5121 /* Cleanup any residual CTX SRBs. */
5122 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5123
39a11240
CH		 5124 return 0;
5125}
5126
5127void
e315cd28 5128qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5129{
e315cd28 5130 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5131 struct task_struct *t = ha->dpc_thread;
5132
e315cd28 5133 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5134 wake_up_process(t);
1da177e4
LT		 5135}
5136
1da177e4
LT		 5137/*
5138* qla2x00_rst_aen
5139* Processes asynchronous reset.
5140*
5141* Input:
5142* ha = adapter block pointer.
5143*/
5144static void
e315cd28 5145qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5146{
e315cd28
AC		 5147 if (vha->flags.online && !vha->flags.reset_active &&
5148 !atomic_read(&vha->loop_down_timer) &&
5149 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5150 do {
e315cd28 5151 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5152
5153 /*
5154 * Issue marker command only when we are going to start
5155 * the I/O.
5156 */
e315cd28
AC		 5157 vha->marker_needed = 1;
5158 } while (!atomic_read(&vha->loop_down_timer) &&
5159 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5160 }
5161}
5162
1da177e4
LT		 5163/**************************************************************************
5164* qla2x00_timer
5165*
5166* Description:
5167* One second timer
5168*
5169* Context: Interrupt
5170***************************************************************************/
2c3dfe3f 5171void
e315cd28 5172qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5173{
1da177e4 5174 unsigned long cpu_flags = 0;
1da177e4
LT		 5175 int start_dpc = 0;
5176 int index;
5177 srb_t *sp;
85880801 5178 uint16_t w;
e315cd28 5179 struct qla_hw_data *ha = vha->hw;
73208dfd 5180 struct req_que *req;
85880801 5181
a5b36321 5182 if (ha->flags.eeh_busy) {
7c3df132
SK		 5183 ql_dbg(ql_dbg_timer, vha, 0x6000,
5184 "EEH = %d, restarting timer.\n",
5185 ha->flags.eeh_busy);
a5b36321
LC		 5186 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5187 return;
5188 }
5189
f3ddac19
CD		 5190 /*
5191 * Hardware read to raise pending EEH errors during mailbox waits. If
5192 * the read returns -1 then disable the board.
5193 */
5194 if (!pci_channel_offline(ha->pdev)) {
85880801 5195 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5196 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5197 }
1da177e4 5198
cefcaba6 5199 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5200 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5201 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5202 start_dpc++;
7ec0effd
AD		 5203 if (IS_QLA82XX(ha))
5204 qla82xx_watchdog(vha);
5205 else if (IS_QLA8044(ha))
5206 qla8044_watchdog(vha);
579d12b5
SK		 5207 }
5208
8ae6d9c7
GM		 5209 if (!vha->vp_idx && IS_QLAFX00(ha))
5210 qlafx00_timer_routine(vha);
5211
1da177e4 5212 /* Loop down handler. */
e315cd28 5213 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5214 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5215 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5216 && vha->flags.online) {
1da177e4 5217
e315cd28
AC		 5218 if (atomic_read(&vha->loop_down_timer) ==
5219 vha->loop_down_abort_time) {
1da177e4 5220
7c3df132
SK		 5221 ql_log(ql_log_info, vha, 0x6008,
5222 "Loop down - aborting the queues before time expires.\n");
1da177e4 5223
e315cd28
AC		 5224 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5225 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5226
f08b7251
AV		 5227 /*
5228 * Schedule an ISP abort to return any FCP2-device
5229 * commands.
5230 */
2c3dfe3f 5231 /* NPIV - scan physical port only */
e315cd28 5232 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5233 spin_lock_irqsave(&ha->hardware_lock,
5234 cpu_flags);
73208dfd 5235 req = ha->req_q_map[0];
2c3dfe3f 5236 for (index = 1;
8d93f550 5237 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5238 index++) {
5239 fc_port_t *sfcp;
5240
e315cd28 5241 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5242 if (!sp)
5243 continue;
9ba56b95 5244 if (sp->type != SRB_SCSI_CMD)
cf53b069 5245 continue;
2c3dfe3f 5246 sfcp = sp->fcport;
f08b7251 5247 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5248 continue;
bdf79621 5249
8f7daead
GM		 5250 if (IS_QLA82XX(ha))
5251 set_bit(FCOE_CTX_RESET_NEEDED,
5252 &vha->dpc_flags);
5253 else
5254 set_bit(ISP_ABORT_NEEDED,
e315cd28 5255 &vha->dpc_flags);
2c3dfe3f
SJ		 5256 break;
5257 }
5258 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5259 cpu_flags);
1da177e4 5260 }
1da177e4
LT		 5261 start_dpc++;
5262 }
5263
5264 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5265 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5266 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5267 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5268 "Loop down - aborting ISP.\n");
5269
8f7daead
GM		 5270 if (IS_QLA82XX(ha))
5271 set_bit(FCOE_CTX_RESET_NEEDED,
5272 &vha->dpc_flags);
5273 else
5274 set_bit(ISP_ABORT_NEEDED,
5275 &vha->dpc_flags);
1da177e4
LT		 5276 }
5277 }
7c3df132
SK		 5278 ql_dbg(ql_dbg_timer, vha, 0x600a,
5279 "Loop down - seconds remaining %d.\n",
5280 atomic_read(&vha->loop_down_timer));
1da177e4 5281 }
cefcaba6
SK		 5282 /* Check if beacon LED needs to be blinked for physical host only */
5283 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5284 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5285 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5286 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5287 start_dpc++;
5288 }
f6df144c
AV		 5289 }
5290
550bf57d 5291 /* Process any deferred work. */
e315cd28 5292 if (!list_empty(&vha->work_list))
550bf57d
AV		 5293 start_dpc++;
5294
1da177e4 5295 /* Schedule the DPC routine if needed */
e315cd28
AC		 5296 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5297 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5298 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5299 start_dpc ||
e315cd28
AC		 5300 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5301 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5302 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5303 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5304 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5305 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5306 ql_dbg(ql_dbg_timer, vha, 0x600b,
5307 "isp_abort_needed=%d loop_resync_needed=%d "
5308 "fcport_update_needed=%d start_dpc=%d "
5309 "reset_marker_needed=%d",
5310 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5311 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5312 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5313 start_dpc,
5314 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5315 ql_dbg(ql_dbg_timer, vha, 0x600c,
5316 "beacon_blink_needed=%d isp_unrecoverable=%d "
5317 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5318 "relogin_needed=%d.\n",
7c3df132
SK		 5319 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5320 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5321 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5322 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5323 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5324 qla2xxx_wake_dpc(vha);
7c3df132 5325 }
1da177e4 5326
e315cd28 5327 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5328}
5329
5433383e
AV		 5330/* Firmware interface routines. */
5331
f73cb695 5332#define FW_BLOBS 11
5433383e
AV		 5333#define FW_ISP21XX 0
5334#define FW_ISP22XX 1
5335#define FW_ISP2300 2
5336#define FW_ISP2322 3
48c02fde 5337#define FW_ISP24XX 4
c3a2f0df 5338#define FW_ISP25XX 5
3a03eb79 5339#define FW_ISP81XX 6
a9083016 5340#define FW_ISP82XX 7
6246b8a1
GM		 5341#define FW_ISP2031 8
5342#define FW_ISP8031 9
2c5bbbb2 5343#define FW_ISP27XX 10
5433383e 5344
bb8ee499
AV		 5345#define FW_FILE_ISP21XX "ql2100_fw.bin"
5346#define FW_FILE_ISP22XX "ql2200_fw.bin"
5347#define FW_FILE_ISP2300 "ql2300_fw.bin"
5348#define FW_FILE_ISP2322 "ql2322_fw.bin"
5349#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5350#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5351#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5352#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5353#define FW_FILE_ISP2031 "ql2600_fw.bin"
5354#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5355#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5356
bb8ee499 5357
e1e82b6f 5358static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5359
5360static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5361 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5362 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5363 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5364 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5365 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5366 { .name = FW_FILE_ISP25XX, },
3a03eb79 5367 { .name = FW_FILE_ISP81XX, },
a9083016 5368 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5369 { .name = FW_FILE_ISP2031, },
5370 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5371 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5372};
5373
5374struct fw_blob *
e315cd28 5375qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5376{
e315cd28 5377 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5378 struct fw_blob *blob;
5379
5433383e
AV		 5380 if (IS_QLA2100(ha)) {
5381 blob = &qla_fw_blobs[FW_ISP21XX];
5382 } else if (IS_QLA2200(ha)) {
5383 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5384 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5385 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5386 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5387 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5388 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5389 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5390 } else if (IS_QLA25XX(ha)) {
5391 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5392 } else if (IS_QLA81XX(ha)) {
5393 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5394 } else if (IS_QLA82XX(ha)) {
5395 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5396 } else if (IS_QLA2031(ha)) {
5397 blob = &qla_fw_blobs[FW_ISP2031];
5398 } else if (IS_QLA8031(ha)) {
5399 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5400 } else if (IS_QLA27XX(ha)) {
5401 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5402 } else {
5403 return NULL;
5433383e
AV		 5404 }
5405
e1e82b6f 5406 mutex_lock(&qla_fw_lock);
5433383e
AV		 5407 if (blob->fw)
5408 goto out;
5409
5410 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5411 ql_log(ql_log_warn, vha, 0x0063,
5412 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5413 blob->fw = NULL;
5414 blob = NULL;
5415 goto out;
5416 }
5417
5418out:
e1e82b6f 5419 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5420 return blob;
5421}
5422
5423static void
5424qla2x00_release_firmware(void)
5425{
5426 int idx;
5427
e1e82b6f 5428 mutex_lock(&qla_fw_lock);
5433383e 5429 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5430 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5431 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5432}
5433
14e660e6
SJ		 5434static pci_ers_result_t
5435qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5436{
85880801
AV		 5437 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5438 struct qla_hw_data *ha = vha->hw;
5439
7c3df132
SK		 5440 ql_dbg(ql_dbg_aer, vha, 0x9000,
5441 "PCI error detected, state %x.\n", state);
b9b12f73 5442
14e660e6
SJ		 5443 switch (state) {
5444 case pci_channel_io_normal:
85880801 5445 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5446 return PCI_ERS_RESULT_CAN_RECOVER;
5447 case pci_channel_io_frozen:
85880801 5448 ha->flags.eeh_busy = 1;
a5b36321
LC		 5449 /* For ISP82XX complete any pending mailbox cmd */
5450 if (IS_QLA82XX(ha)) {
7190575f 5451 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5452 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5453 qla82xx_clear_pending_mbx(vha);
a5b36321 5454 }
90a86fc0 5455 qla2x00_free_irqs(vha);
14e660e6 5456 pci_disable_device(pdev);
bddd2d65
LC		 5457 /* Return back all IOs */
5458 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5459 return PCI_ERS_RESULT_NEED_RESET;
5460 case pci_channel_io_perm_failure:
85880801
AV		 5461 ha->flags.pci_channel_io_perm_failure = 1;
5462 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5463 return PCI_ERS_RESULT_DISCONNECT;
5464 }
5465 return PCI_ERS_RESULT_NEED_RESET;
5466}
5467
5468static pci_ers_result_t
5469qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5470{
5471 int risc_paused = 0;
5472 uint32_t stat;
5473 unsigned long flags;
e315cd28
AC		 5474 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5475 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5476 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5477 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5478
bcc5b6d3
SK		 5479 if (IS_QLA82XX(ha))
5480 return PCI_ERS_RESULT_RECOVERED;
5481
14e660e6
SJ		 5482 spin_lock_irqsave(&ha->hardware_lock, flags);
5483 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5484 stat = RD_REG_DWORD(&reg->hccr);
5485 if (stat & HCCR_RISC_PAUSE)
5486 risc_paused = 1;
5487 } else if (IS_QLA23XX(ha)) {
5488 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5489 if (stat & HSR_RISC_PAUSED)
5490 risc_paused = 1;
5491 } else if (IS_FWI2_CAPABLE(ha)) {
5492 stat = RD_REG_DWORD(&reg24->host_status);
5493 if (stat & HSRX_RISC_PAUSED)
5494 risc_paused = 1;
5495 }
5496 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5497
5498 if (risc_paused) {
7c3df132
SK		 5499 ql_log(ql_log_info, base_vha, 0x9003,
5500 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5501 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5502
5503 return PCI_ERS_RESULT_NEED_RESET;
5504 } else
5505 return PCI_ERS_RESULT_RECOVERED;
5506}
5507
fa492630
SK		 5508static uint32_t
5509qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5510{
5511 uint32_t rval = QLA_FUNCTION_FAILED;
5512 uint32_t drv_active = 0;
5513 struct qla_hw_data *ha = base_vha->hw;
5514 int fn;
5515 struct pci_dev *other_pdev = NULL;
5516
7c3df132
SK		 5517 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5518 "Entered %s.\n", __func__);
a5b36321
LC		 5519
5520 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5521
5522 if (base_vha->flags.online) {
5523 /* Abort all outstanding commands,
5524 * so as to be requeued later */
5525 qla2x00_abort_isp_cleanup(base_vha);
5526 }
5527
5528
5529 fn = PCI_FUNC(ha->pdev->devfn);
5530 while (fn > 0) {
5531 fn--;
7c3df132
SK		 5532 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5533 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5534 other_pdev =
5535 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5536 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5537 fn));
5538
5539 if (!other_pdev)
5540 continue;
5541 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5542 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5543 "Found PCI func available and enable at 0x%x.\n",
5544 fn);
a5b36321
LC		 5545 pci_dev_put(other_pdev);
5546 break;
5547 }
5548 pci_dev_put(other_pdev);
5549 }
5550
5551 if (!fn) {
5552 /* Reset owner */
7c3df132
SK		 5553 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5554 "This devfn is reset owner = 0x%x.\n",
5555 ha->pdev->devfn);
a5b36321
LC		 5556 qla82xx_idc_lock(ha);
5557
5558 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5559 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5560
5561 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5562 QLA82XX_IDC_VERSION);
5563
5564 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5565 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5566 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5567
5568 qla82xx_idc_unlock(ha);
5569 /* Reset if device is not already reset
5570 * drv_active would be 0 if a reset has already been done
5571 */
5572 if (drv_active)
5573 rval = qla82xx_start_firmware(base_vha);
5574 else
5575 rval = QLA_SUCCESS;
5576 qla82xx_idc_lock(ha);
5577
5578 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5579 ql_log(ql_log_info, base_vha, 0x900b,
5580 "HW State: FAILED.\n");
a5b36321
LC		 5581 qla82xx_clear_drv_active(ha);
5582 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5583 QLA8XXX_DEV_FAILED);
a5b36321 5584 } else {
7c3df132
SK		 5585 ql_log(ql_log_info, base_vha, 0x900c,
5586 "HW State: READY.\n");
a5b36321 5587 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5588 QLA8XXX_DEV_READY);
a5b36321 5589 qla82xx_idc_unlock(ha);
7190575f 5590 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5591 rval = qla82xx_restart_isp(base_vha);
5592 qla82xx_idc_lock(ha);
5593 /* Clear driver state register */
5594 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5595 qla82xx_set_drv_active(base_vha);
5596 }
5597 qla82xx_idc_unlock(ha);
5598 } else {
7c3df132
SK		 5599 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5600 "This devfn is not reset owner = 0x%x.\n",
5601 ha->pdev->devfn);
a5b36321 5602 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5603 QLA8XXX_DEV_READY)) {
7190575f 5604 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5605 rval = qla82xx_restart_isp(base_vha);
5606 qla82xx_idc_lock(ha);
5607 qla82xx_set_drv_active(base_vha);
5608 qla82xx_idc_unlock(ha);
5609 }
5610 }
5611 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5612
5613 return rval;
5614}
5615
14e660e6
SJ		 5616static pci_ers_result_t
5617qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5618{
5619 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5620 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5621 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5622 struct rsp_que *rsp;
5623 int rc, retries = 10;
09483916 5624
7c3df132
SK		 5625 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5626 "Slot Reset.\n");
85880801 5627
90a86fc0
JC		 5628 /* Workaround: qla2xxx driver which access hardware earlier
5629 * needs error state to be pci_channel_io_online.
5630 * Otherwise mailbox command timesout.
5631 */
5632 pdev->error_state = pci_channel_io_normal;
5633
5634 pci_restore_state(pdev);
5635
8c1496bd
RL		 5636 /* pci_restore_state() clears the saved_state flag of the device
5637 * save restored state which resets saved_state flag
5638 */
5639 pci_save_state(pdev);
5640
09483916
BH		 5641 if (ha->mem_only)
5642 rc = pci_enable_device_mem(pdev);
5643 else
5644 rc = pci_enable_device(pdev);
14e660e6 5645
09483916 5646 if (rc) {
7c3df132 5647 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5648 "Can't re-enable PCI device after reset.\n");
a5b36321 5649 goto exit_slot_reset;
14e660e6 5650 }
14e660e6 5651
90a86fc0
JC		 5652 rsp = ha->rsp_q_map[0];
5653 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5654 goto exit_slot_reset;
90a86fc0 5655
e315cd28 5656 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5657 goto exit_slot_reset;
5658
5659 if (IS_QLA82XX(ha)) {
5660 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5661 ret = PCI_ERS_RESULT_RECOVERED;
5662 goto exit_slot_reset;
5663 } else
5664 goto exit_slot_reset;
5665 }
14e660e6 5666
90a86fc0
JC		 5667 while (ha->flags.mbox_busy && retries--)
5668 msleep(1000);
85880801 5669
e315cd28 5670 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5671 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5672 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5673 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5674
90a86fc0 5675
a5b36321 5676exit_slot_reset:
7c3df132
SK		 5677 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5678 "slot_reset return %x.\n", ret);
85880801 5679
14e660e6
SJ		 5680 return ret;
5681}
5682
5683static void
5684qla2xxx_pci_resume(struct pci_dev *pdev)
5685{
e315cd28
AC		 5686 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5687 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5688 int ret;
5689
7c3df132
SK		 5690 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5691 "pci_resume.\n");
85880801 5692
e315cd28 5693 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5694 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5695 ql_log(ql_log_fatal, base_vha, 0x9002,
5696 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5697 }
85880801 5698
3e46f031
LC		 5699 pci_cleanup_aer_uncorrect_error_status(pdev);
5700
85880801 5701 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5702}
5703
a55b2d21 5704static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5705 .error_detected = qla2xxx_pci_error_detected,
5706 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5707 .slot_reset = qla2xxx_pci_slot_reset,
5708 .resume = qla2xxx_pci_resume,
5709};
5710
5433383e 5711static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5712 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5713 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5714 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5715 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5716 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5717 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5718 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5719 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5720 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5721 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5722 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5723 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5724 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5725 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5726 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5727 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5728 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5729 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5730 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5731 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5732 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
5433383e
AV		 5733 { 0 },
5734};
5735MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5736
fca29703 5737static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5738 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5739 .driver = {
5740 .owner = THIS_MODULE,
5741 },
fca29703 5742 .id_table = qla2xxx_pci_tbl,
7ee61397 5743 .probe = qla2x00_probe_one,
4c993f76 5744 .remove = qla2x00_remove_one,
e30d1756 5745 .shutdown = qla2x00_shutdown,
14e660e6 5746 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5747};
5748
75ef9de1 5749static const struct file_operations apidev_fops = {
6a03b4cd 5750 .owner = THIS_MODULE,
6038f373 5751 .llseek = noop_llseek,
6a03b4cd
HZ		 5752};
5753
1da177e4
LT		 5754/**
5755 * qla2x00_module_init - Module initialization.
5756 **/
5757static int __init
5758qla2x00_module_init(void)
5759{
fca29703
AV		 5760 int ret = 0;
5761
1da177e4 5762 /* Allocate cache for SRBs. */
354d6b21 5763 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5764 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5765 if (srb_cachep == NULL) {
7c3df132
SK		 5766 ql_log(ql_log_fatal, NULL, 0x0001,
5767 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5768 return -ENOMEM;
5769 }
5770
2d70c103
NB		 5771 /* Initialize target kmem_cache and mem_pools */
5772 ret = qlt_init();
5773 if (ret < 0) {
5774 kmem_cache_destroy(srb_cachep);
5775 return ret;
5776 } else if (ret > 0) {
5777 /*
5778 * If initiator mode is explictly disabled by qlt_init(),
5779 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5780 * performing scsi_scan_target() during LOOP UP event.
5781 */
5782 qla2xxx_transport_functions.disable_target_scan = 1;
5783 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5784 }
5785
1da177e4
LT		 5786 /* Derive version string. */
5787 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5788 if (ql2xextended_error_logging)
0181944f
AV		 5789 strcat(qla2x00_version_str, "-debug");
5790
1c97a12a
AV		 5791 qla2xxx_transport_template =
5792 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5793 if (!qla2xxx_transport_template) {
5794 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5795 ql_log(ql_log_fatal, NULL, 0x0002,
5796 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5797 qlt_exit();
1da177e4 5798 return -ENODEV;
2c3dfe3f 5799 }
6a03b4cd
HZ		 5800
5801 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5802 if (apidev_major < 0) {
7c3df132
SK		 5803 ql_log(ql_log_fatal, NULL, 0x0003,
5804 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5805 }
5806
2c3dfe3f
SJ		 5807 qla2xxx_transport_vport_template =
5808 fc_attach_transport(&qla2xxx_transport_vport_functions);
5809 if (!qla2xxx_transport_vport_template) {
5810 kmem_cache_destroy(srb_cachep);
2d70c103 5811 qlt_exit();
2c3dfe3f 5812 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5813 ql_log(ql_log_fatal, NULL, 0x0004,
5814 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5815 return -ENODEV;
2c3dfe3f 5816 }
7c3df132
SK		 5817 ql_log(ql_log_info, NULL, 0x0005,
5818 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5819 qla2x00_version_str);
7ee61397 5820 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5821 if (ret) {
5822 kmem_cache_destroy(srb_cachep);
2d70c103 5823 qlt_exit();
fca29703 5824 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5825 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5826 ql_log(ql_log_fatal, NULL, 0x0006,
5827 "pci_register_driver failed...ret=%d Failing load!.\n",
5828 ret);
fca29703
AV		 5829 }
5830 return ret;
1da177e4
LT		 5831}
5832
5833/**
5834 * qla2x00_module_exit - Module cleanup.
5835 **/
5836static void __exit
5837qla2x00_module_exit(void)
5838{
6a03b4cd 5839 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5840 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5841 qla2x00_release_firmware();
354d6b21 5842 kmem_cache_destroy(srb_cachep);
2d70c103 5843 qlt_exit();
a9083016
GM		 5844 if (ctx_cachep)
5845 kmem_cache_destroy(ctx_cachep);
1da177e4 5846 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5847 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5848}
5849
5850module_init(qla2x00_module_init);
5851module_exit(qla2x00_module_exit);
5852
5853MODULE_AUTHOR("QLogic Corporation");
5854MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5855MODULE_LICENSE("GPL");
5856MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5857MODULE_FIRMWARE(FW_FILE_ISP21XX);
5858MODULE_FIRMWARE(FW_FILE_ISP22XX);
5859MODULE_FIRMWARE(FW_FILE_ISP2300);
5860MODULE_FIRMWARE(FW_FILE_ISP2322);
5861MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5862MODULE_FIRMWARE(FW_FILE_ISP25XX);
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