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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
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1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
41dc529a
QT		 240int ql2xmvasynctoatio = 1;
241module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
242MODULE_PARM_DESC(ql2xmvasynctoatio,
243 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
244 "0 (Default). Do not move IOCBs"
245 "1 - Move IOCBs.");
246
1da177e4 247/*
fa2a1ce5 248 * SCSI host template entry points
1da177e4
LT		 249 */
250static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 251static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 252static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
253static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 254static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 255static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 256static int qla2xxx_eh_abort(struct scsi_cmnd *);
257static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 258static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 259static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
260static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 261
1a2fbf18 262static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 263static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 264static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 265static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 266
a5326f86 267struct scsi_host_template qla2xxx_driver_template = {
1da177e4 268 .module = THIS_MODULE,
cb63067a 269 .name = QLA2XXX_DRIVER_NAME,
a5326f86 270 .queuecommand = qla2xxx_queuecommand,
fca29703 271
b6a05c82 272 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 273 .eh_abort_handler = qla2xxx_eh_abort,
274 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 275 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 276 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
277 .eh_host_reset_handler = qla2xxx_eh_host_reset,
278
279 .slave_configure = qla2xxx_slave_configure,
280
281 .slave_alloc = qla2xxx_slave_alloc,
282 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 283 .scan_finished = qla2xxx_scan_finished,
284 .scan_start = qla2xxx_scan_start,
db5ed4df 285 .change_queue_depth = scsi_change_queue_depth,
5601236b 286 .map_queues = qla2xxx_map_queues,
fca29703
AV		 287 .this_id = -1,
288 .cmd_per_lun = 3,
289 .use_clustering = ENABLE_CLUSTERING,
290 .sg_tablesize = SG_ALL,
291
292 .max_sectors = 0xFFFF,
afb046e2 293 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 294
295 .supported_mode = MODE_INITIATOR,
c40ecc12 296 .track_queue_depth = 1,
fca29703
AV		 297};
298
1da177e4 299static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 300struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 301
1da177e4
LT		 302/* TODO Convert to inlines
303 *
304 * Timer routines
305 */
1da177e4 306
2c3dfe3f 307__inline__ void
e315cd28 308qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 309{
e315cd28
AC		 310 init_timer(&vha->timer);
311 vha->timer.expires = jiffies + interval * HZ;
312 vha->timer.data = (unsigned long)vha;
313 vha->timer.function = (void (*)(unsigned long))func;
314 add_timer(&vha->timer);
315 vha->timer_active = 1;
1da177e4
LT		 316}
317
318static inline void
e315cd28 319qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 320{
a9083016 321 /* Currently used for 82XX only. */
7c3df132
SK		 322 if (vha->device_flags & DFLG_DEV_FAILED) {
323 ql_dbg(ql_dbg_timer, vha, 0x600d,
324 "Device in a failed state, returning.\n");
a9083016 325 return;
7c3df132 326 }
a9083016 327
e315cd28 328 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 329}
330
a824ebb3 331static __inline__ void
e315cd28 332qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 333{
e315cd28
AC		 334 del_timer_sync(&vha->timer);
335 vha->timer_active = 0;
1da177e4
LT		 336}
337
1da177e4
LT		 338static int qla2x00_do_dpc(void *data);
339
340static void qla2x00_rst_aen(scsi_qla_host_t *);
341
73208dfd
AC		 342static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
343 struct req_que **, struct rsp_que **);
e30d1756 344static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 345static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 346int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
347 struct qla_qpair *qpair);
1da177e4 348
1da177e4 349/* -------------------------------------------------------------------------- */
9a347ff4
CD		 350static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
351 struct rsp_que *rsp)
73208dfd 352{
7c3df132 353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 354 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 355 GFP_KERNEL);
356 if (!ha->req_q_map) {
7c3df132
SK		 357 ql_log(ql_log_fatal, vha, 0x003b,
358 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 359 goto fail_req_map;
360 }
361
2afa19a9 362 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 363 GFP_KERNEL);
364 if (!ha->rsp_q_map) {
7c3df132
SK		 365 ql_log(ql_log_fatal, vha, 0x003c,
366 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 367 goto fail_rsp_map;
368 }
d7459527
MH		 369
370 if (ql2xmqsupport && ha->max_qpairs) {
371 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
372 GFP_KERNEL);
373 if (!ha->queue_pair_map) {
374 ql_log(ql_log_fatal, vha, 0x0180,
375 "Unable to allocate memory for queue pair ptrs.\n");
376 goto fail_qpair_map;
377 }
378 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
379 if (ha->base_qpair == NULL) {
380 ql_log(ql_log_warn, vha, 0x0182,
381 "Failed to allocate base queue pair memory.\n");
382 goto fail_base_qpair;
383 }
384 ha->base_qpair->req = req;
385 ha->base_qpair->rsp = rsp;
386 }
387
9a347ff4
CD		 388 /*
389 * Make sure we record at least the request and response queue zero in
390 * case we need to free them if part of the probe fails.
391 */
392 ha->rsp_q_map[0] = rsp;
393 ha->req_q_map[0] = req;
73208dfd
AC		 394 set_bit(0, ha->rsp_qid_map);
395 set_bit(0, ha->req_qid_map);
396 return 1;
397
d7459527
MH		 398fail_base_qpair:
399 kfree(ha->queue_pair_map);
400fail_qpair_map:
401 kfree(ha->rsp_q_map);
402 ha->rsp_q_map = NULL;
73208dfd
AC		 403fail_rsp_map:
404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
406fail_req_map:
407 return -ENOMEM;
408}
409
2afa19a9 410static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 411{
8ae6d9c7
GM		 412 if (IS_QLAFX00(ha)) {
413 if (req && req->ring_fx00)
414 dma_free_coherent(&ha->pdev->dev,
415 (req->length_fx00 + 1) * sizeof(request_t),
416 req->ring_fx00, req->dma_fx00);
417 } else if (req && req->ring)
73208dfd
AC		 418 dma_free_coherent(&ha->pdev->dev,
419 (req->length + 1) * sizeof(request_t),
420 req->ring, req->dma);
421
8d93f550
CD		 422 if (req)
423 kfree(req->outstanding_cmds);
424
73208dfd
AC		 425 kfree(req);
426 req = NULL;
427}
428
2afa19a9
AC		 429static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
430{
8ae6d9c7
GM		 431 if (IS_QLAFX00(ha)) {
432 if (rsp && rsp->ring)
433 dma_free_coherent(&ha->pdev->dev,
434 (rsp->length_fx00 + 1) * sizeof(request_t),
435 rsp->ring_fx00, rsp->dma_fx00);
436 } else if (rsp && rsp->ring) {
2afa19a9
AC		 437 dma_free_coherent(&ha->pdev->dev,
438 (rsp->length + 1) * sizeof(response_t),
439 rsp->ring, rsp->dma);
8ae6d9c7 440 }
2afa19a9
AC		 441 kfree(rsp);
442 rsp = NULL;
443}
444
73208dfd
AC		 445static void qla2x00_free_queues(struct qla_hw_data *ha)
446{
447 struct req_que *req;
448 struct rsp_que *rsp;
449 int cnt;
093df737 450 unsigned long flags;
73208dfd 451
093df737 452 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 453 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 454 if (!test_bit(cnt, ha->req_qid_map))
455 continue;
456
73208dfd 457 req = ha->req_q_map[cnt];
093df737
QT		 458 clear_bit(cnt, ha->req_qid_map);
459 ha->req_q_map[cnt] = NULL;
460
461 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 462 qla2x00_free_req_que(ha, req);
093df737 463 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 464 }
093df737
QT		 465 spin_unlock_irqrestore(&ha->hardware_lock, flags);
466
73208dfd
AC		 467 kfree(ha->req_q_map);
468 ha->req_q_map = NULL;
2afa19a9 469
093df737
QT		 470
471 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 472 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 473 if (!test_bit(cnt, ha->rsp_qid_map))
474 continue;
475
2afa19a9 476 rsp = ha->rsp_q_map[cnt];
c3c42394 477 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 478 ha->rsp_q_map[cnt] = NULL;
479 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 480 qla2x00_free_rsp_que(ha, rsp);
093df737 481 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 482 }
093df737
QT		 483 spin_unlock_irqrestore(&ha->hardware_lock, flags);
484
2afa19a9
AC		 485 kfree(ha->rsp_q_map);
486 ha->rsp_q_map = NULL;
73208dfd
AC		 487}
488
1da177e4 489static char *
e315cd28 490qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 491{
e315cd28 492 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 493 static char *pci_bus_modes[] = {
494 "33", "66", "100", "133",
495 };
496 uint16_t pci_bus;
497
498 strcpy(str, "PCI");
499 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
500 if (pci_bus) {
501 strcat(str, "-X (");
502 strcat(str, pci_bus_modes[pci_bus]);
503 } else {
504 pci_bus = (ha->pci_attr & BIT_8) >> 8;
505 strcat(str, " (");
506 strcat(str, pci_bus_modes[pci_bus]);
507 }
508 strcat(str, " MHz)");
509
510 return (str);
511}
512
fca29703 513static char *
e315cd28 514qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 515{
516 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 517 struct qla_hw_data *ha = vha->hw;
fca29703 518 uint32_t pci_bus;
fca29703 519
62a276f8 520 if (pci_is_pcie(ha->pdev)) {
fca29703 521 char lwstr[6];
62a276f8 522 uint32_t lstat, lspeed, lwidth;
fca29703 523
62a276f8
BH		 524 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
525 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
526 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 527
528 strcpy(str, "PCIe (");
49300af7
SK		 529 switch (lspeed) {
530 case 1:
c87a0d8c 531 strcat(str, "2.5GT/s ");
49300af7
SK		 532 break;
533 case 2:
c87a0d8c 534 strcat(str, "5.0GT/s ");
49300af7
SK		 535 break;
536 case 3:
537 strcat(str, "8.0GT/s ");
538 break;
539 default:
fca29703 540 strcat(str, "<unknown> ");
49300af7
SK		 541 break;
542 }
fca29703
AV		 543 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
544 strcat(str, lwstr);
545
546 return str;
547 }
548
549 strcpy(str, "PCI");
550 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
551 if (pci_bus == 0 || pci_bus == 8) {
552 strcat(str, " (");
553 strcat(str, pci_bus_modes[pci_bus >> 3]);
554 } else {
555 strcat(str, "-X ");
556 if (pci_bus & BIT_2)
557 strcat(str, "Mode 2");
558 else
559 strcat(str, "Mode 1");
560 strcat(str, " (");
561 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
562 }
563 strcat(str, " MHz)");
564
565 return str;
566}
567
e5f82ab8 568static char *
df57caba 569qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 570{
571 char un_str[10];
e315cd28 572 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 573
df57caba
HM		 574 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
575 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 576
577 if (ha->fw_attributes & BIT_9) {
578 strcat(str, "FLX");
579 return (str);
580 }
581
582 switch (ha->fw_attributes & 0xFF) {
583 case 0x7:
584 strcat(str, "EF");
585 break;
586 case 0x17:
587 strcat(str, "TP");
588 break;
589 case 0x37:
590 strcat(str, "IP");
591 break;
592 case 0x77:
593 strcat(str, "VI");
594 break;
595 default:
596 sprintf(un_str, "(%x)", ha->fw_attributes);
597 strcat(str, un_str);
598 break;
599 }
600 if (ha->fw_attributes & 0x100)
601 strcat(str, "X");
602
603 return (str);
604}
605
e5f82ab8 606static char *
df57caba 607qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 608{
e315cd28 609 struct qla_hw_data *ha = vha->hw;
f0883ac6 610
df57caba 611 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 612 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 613 return str;
fca29703
AV		 614}
615
9ba56b95 616void
25ff6af1 617qla2x00_sp_free_dma(void *ptr)
fca29703 618{
25ff6af1
JC		 619 srb_t *sp = ptr;
620 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 621 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 622 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 623
9ba56b95
GM		 624 if (sp->flags & SRB_DMA_VALID) {
625 scsi_dma_unmap(cmd);
626 sp->flags &= ~SRB_DMA_VALID;
7c3df132 627 }
fca29703 628
9ba56b95
GM		 629 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
630 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
631 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
632 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
633 }
634
635 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
636 /* List assured to be having elements */
f83adb61 637 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 638 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
639 }
640
641 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
642 dma_pool_free(ha->dl_dma_pool, ctx,
643 ((struct crc_context *)ctx)->crc_ctx_dma);
644 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
645 }
646
647 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
648 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 649
9ba56b95
GM		 650 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
651 ctx1->fcp_cmnd_dma);
652 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
653 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
654 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
655 mempool_free(ctx1, ha->ctx_mempool);
656 ctx1 = NULL;
657 }
658
659 CMD_SP(cmd) = NULL;
25ff6af1 660 qla2x00_rel_sp(sp);
9ba56b95
GM		 661}
662
d7459527 663void
25ff6af1 664qla2x00_sp_compl(void *ptr, int res)
9ba56b95 665{
25ff6af1 666 srb_t *sp = ptr;
9ba56b95
GM		 667 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
668
669 cmd->result = res;
670
671 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 672 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 673 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
674 sp, GET_CMD_SP(sp));
675 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 676 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 677 return;
678 }
679 if (!atomic_dec_and_test(&sp->ref_count))
680 return;
681
25ff6af1 682 qla2x00_sp_free_dma(sp);
9ba56b95 683 cmd->scsi_done(cmd);
fca29703
AV		 684}
685
d7459527 686void
25ff6af1 687qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 688{
689 srb_t *sp = (srb_t *)ptr;
690 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
691 struct qla_hw_data *ha = sp->fcport->vha->hw;
692 void *ctx = GET_CMD_CTX_SP(sp);
693
694 if (sp->flags & SRB_DMA_VALID) {
695 scsi_dma_unmap(cmd);
696 sp->flags &= ~SRB_DMA_VALID;
697 }
698
699 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
700 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
701 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
702 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
703 }
704
705 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
706 /* List assured to be having elements */
707 qla2x00_clean_dsd_pool(ha, sp, NULL);
708 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
709 }
710
711 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
712 dma_pool_free(ha->dl_dma_pool, ctx,
713 ((struct crc_context *)ctx)->crc_ctx_dma);
714 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
715 }
716
717 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
718 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
719
720 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
721 ctx1->fcp_cmnd_dma);
722 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
723 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
724 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
725 mempool_free(ctx1, ha->ctx_mempool);
726 }
727
728 CMD_SP(cmd) = NULL;
729 qla2xxx_rel_qpair_sp(sp->qpair, sp);
730}
731
732void
25ff6af1 733qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 734{
25ff6af1 735 srb_t *sp = ptr;
d7459527
MH		 736 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
737
738 cmd->result = res;
739
740 if (atomic_read(&sp->ref_count) == 0) {
741 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
742 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
743 sp, GET_CMD_SP(sp));
744 if (ql2xextended_error_logging & ql_dbg_io)
745 WARN_ON(atomic_read(&sp->ref_count) == 0);
746 return;
747 }
748 if (!atomic_dec_and_test(&sp->ref_count))
749 return;
750
25ff6af1 751 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 752 cmd->scsi_done(cmd);
753}
754
8ae6d9c7
GM		 755/* If we are SP1 here, we need to still take and release the host_lock as SP1
756 * does not have the changes necessary to avoid taking host->host_lock.
757 */
1da177e4 758static int
f5e3e40b 759qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 760{
134ae078 761 scsi_qla_host_t *vha = shost_priv(host);
fca29703 762 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 763 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 764 struct qla_hw_data *ha = vha->hw;
765 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 766 srb_t *sp;
767 int rval;
5601236b
MH		 768 struct qla_qpair *qpair = NULL;
769 uint32_t tag;
770 uint16_t hwq;
fca29703 771
04dfaa53
MFO		 772 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
773 cmd->result = DID_NO_CONNECT << 16;
774 goto qc24_fail_command;
775 }
776
5601236b
MH		 777 if (ha->mqenable) {
778 if (shost_use_blk_mq(vha->host)) {
779 tag = blk_mq_unique_tag(cmd->request);
780 hwq = blk_mq_unique_tag_to_hwq(tag);
781 qpair = ha->queue_pair_map[hwq];
782 } else if (vha->vp_idx && vha->qpair) {
783 qpair = vha->qpair;
784 }
785
786 if (qpair)
787 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 788 }
789
85880801 790 if (ha->flags.eeh_busy) {
7c3df132 791 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 792 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 793 "PCI Channel IO permanent failure, exiting "
794 "cmd=%p.\n", cmd);
b9b12f73 795 cmd->result = DID_NO_CONNECT << 16;
7c3df132 796 } else {
5f28d2d7 797 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 798 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 799 cmd->result = DID_REQUEUE << 16;
7c3df132 800 }
14e660e6
SJ		 801 goto qc24_fail_command;
802 }
803
19a7b4ae
JSEC		 804 rval = fc_remote_port_chkready(rport);
805 if (rval) {
806 cmd->result = rval;
5f28d2d7 807 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 808 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
809 cmd, rval);
fca29703
AV		 810 goto qc24_fail_command;
811 }
812
bad75002
AE		 813 if (!vha->flags.difdix_supported &&
814 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 815 ql_dbg(ql_dbg_io, vha, 0x3004,
816 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
817 cmd);
bad75002
AE		 818 cmd->result = DID_NO_CONNECT << 16;
819 goto qc24_fail_command;
820 }
aa651be8
CD		 821
822 if (!fcport) {
823 cmd->result = DID_NO_CONNECT << 16;
824 goto qc24_fail_command;
825 }
826
fca29703
AV		 827 if (atomic_read(&fcport->state) != FCS_ONLINE) {
828 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 829 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 830 ql_dbg(ql_dbg_io, vha, 0x3005,
831 "Returning DNC, fcport_state=%d loop_state=%d.\n",
832 atomic_read(&fcport->state),
833 atomic_read(&base_vha->loop_state));
fca29703
AV		 834 cmd->result = DID_NO_CONNECT << 16;
835 goto qc24_fail_command;
836 }
7b594131 837 goto qc24_target_busy;
fca29703
AV		 838 }
839
e05fe292
CD		 840 /*
841 * Return target busy if we've received a non-zero retry_delay_timer
842 * in a FCP_RSP.
843 */
975f7d46
BP		 844 if (fcport->retry_delay_timestamp == 0) {
845 /* retry delay not set */
846 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 847 fcport->retry_delay_timestamp = 0;
848 else
849 goto qc24_target_busy;
850
b00ee7d7 851 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 852 if (!sp)
f5e3e40b 853 goto qc24_host_busy;
fca29703 854
9ba56b95
GM		 855 sp->u.scmd.cmd = cmd;
856 sp->type = SRB_SCSI_CMD;
857 atomic_set(&sp->ref_count, 1);
858 CMD_SP(cmd) = (void *)sp;
859 sp->free = qla2x00_sp_free_dma;
860 sp->done = qla2x00_sp_compl;
861
e315cd28 862 rval = ha->isp_ops->start_scsi(sp);
7c3df132 863 if (rval != QLA_SUCCESS) {
53016ed3 864 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 865 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 866 goto qc24_host_busy_free_sp;
7c3df132 867 }
fca29703 868
fca29703
AV		 869 return 0;
870
871qc24_host_busy_free_sp:
25ff6af1 872 qla2x00_sp_free_dma(sp);
fca29703 873
f5e3e40b 874qc24_host_busy:
fca29703
AV		 875 return SCSI_MLQUEUE_HOST_BUSY;
876
7b594131
MC		 877qc24_target_busy:
878 return SCSI_MLQUEUE_TARGET_BUSY;
879
fca29703 880qc24_fail_command:
f5e3e40b 881 cmd->scsi_done(cmd);
fca29703
AV		 882
883 return 0;
884}
885
d7459527
MH		 886/* For MQ supported I/O */
887int
888qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
889 struct qla_qpair *qpair)
890{
891 scsi_qla_host_t *vha = shost_priv(host);
892 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
893 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
894 struct qla_hw_data *ha = vha->hw;
895 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
896 srb_t *sp;
897 int rval;
898
899 rval = fc_remote_port_chkready(rport);
900 if (rval) {
901 cmd->result = rval;
902 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
903 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
904 cmd, rval);
905 goto qc24_fail_command;
906 }
907
908 if (!fcport) {
909 cmd->result = DID_NO_CONNECT << 16;
910 goto qc24_fail_command;
911 }
912
913 if (atomic_read(&fcport->state) != FCS_ONLINE) {
914 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
915 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
916 ql_dbg(ql_dbg_io, vha, 0x3077,
917 "Returning DNC, fcport_state=%d loop_state=%d.\n",
918 atomic_read(&fcport->state),
919 atomic_read(&base_vha->loop_state));
920 cmd->result = DID_NO_CONNECT << 16;
921 goto qc24_fail_command;
922 }
923 goto qc24_target_busy;
924 }
925
926 /*
927 * Return target busy if we've received a non-zero retry_delay_timer
928 * in a FCP_RSP.
929 */
930 if (fcport->retry_delay_timestamp == 0) {
931 /* retry delay not set */
932 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
933 fcport->retry_delay_timestamp = 0;
934 else
935 goto qc24_target_busy;
936
937 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
938 if (!sp)
939 goto qc24_host_busy;
940
941 sp->u.scmd.cmd = cmd;
942 sp->type = SRB_SCSI_CMD;
943 atomic_set(&sp->ref_count, 1);
944 CMD_SP(cmd) = (void *)sp;
945 sp->free = qla2xxx_qpair_sp_free_dma;
946 sp->done = qla2xxx_qpair_sp_compl;
947 sp->qpair = qpair;
948
949 rval = ha->isp_ops->start_scsi_mq(sp);
950 if (rval != QLA_SUCCESS) {
951 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
952 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
953 if (rval == QLA_INTERFACE_ERROR)
954 goto qc24_fail_command;
955 goto qc24_host_busy_free_sp;
956 }
957
958 return 0;
959
960qc24_host_busy_free_sp:
25ff6af1 961 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 962
963qc24_host_busy:
964 return SCSI_MLQUEUE_HOST_BUSY;
965
966qc24_target_busy:
967 return SCSI_MLQUEUE_TARGET_BUSY;
968
969qc24_fail_command:
970 cmd->scsi_done(cmd);
971
972 return 0;
973}
974
1da177e4
LT		 975/*
976 * qla2x00_eh_wait_on_command
977 * Waits for the command to be returned by the Firmware for some
978 * max time.
979 *
980 * Input:
1da177e4 981 * cmd = Scsi Command to wait on.
1da177e4
LT		 982 *
983 * Return:
984 * Not Found : 0
985 * Found : 1
986 */
987static int
e315cd28 988qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 989{
fe74c71f 990#define ABORT_POLLING_PERIOD 1000
478c3b03 991#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 992 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 993 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
994 struct qla_hw_data *ha = vha->hw;
f4f051eb 995 int ret = QLA_SUCCESS;
1da177e4 996
85880801 997 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 998 ql_dbg(ql_dbg_taskm, vha, 0x8005,
999 "Return:eh_wait.\n");
85880801
AV		 1000 return ret;
1001 }
1002
d970432c 1003 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1004 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1005 }
1006 if (CMD_SP(cmd))
1007 ret = QLA_FUNCTION_FAILED;
1da177e4 1008
f4f051eb 1009 return ret;
1da177e4
LT		 1010}
1011
1012/*
1013 * qla2x00_wait_for_hba_online
fa2a1ce5 1014 * Wait till the HBA is online after going through
1da177e4
LT		 1015 * <= MAX_RETRIES_OF_ISP_ABORT or
1016 * finally HBA is disabled ie marked offline
1017 *
1018 * Input:
1019 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1020 *
1021 * Note:
1da177e4
LT		 1022 * Does context switching-Release SPIN_LOCK
1023 * (if any) before calling this routine.
1024 *
1025 * Return:
1026 * Success (Adapter is online) : 0
1027 * Failed (Adapter is offline/disabled) : 1
1028 */
854165f4 1029int
e315cd28 1030qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1031{
fca29703
AV		 1032 int return_status;
1033 unsigned long wait_online;
e315cd28
AC		 1034 struct qla_hw_data *ha = vha->hw;
1035 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1036
fa2a1ce5 1037 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1038 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1039 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1040 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1041 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1042
1043 msleep(1000);
1044 }
e315cd28 1045 if (base_vha->flags.online)
fa2a1ce5 1046 return_status = QLA_SUCCESS;
1da177e4
LT		 1047 else
1048 return_status = QLA_FUNCTION_FAILED;
1049
1da177e4
LT		 1050 return (return_status);
1051}
1052
726b8548
QT		 1053static inline int test_fcport_count(scsi_qla_host_t *vha)
1054{
1055 struct qla_hw_data *ha = vha->hw;
1056 unsigned long flags;
1057 int res;
1058
1059 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1060 ql_dbg(ql_dbg_init, vha, 0xffff,
1061 "tgt %p, fcport_count=%d\n",
1062 vha, vha->fcport_count);
1063 res = (vha->fcport_count == 0);
1064 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1065
1066 return res;
1067}
1068
1069/*
1070 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1071 * it has dependency on UNLOADING flag to stop device discovery
1072 */
1073static void
1074qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1075{
1076 qla2x00_mark_all_devices_lost(vha, 0);
1077
1078 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1079}
1080
86fbee86 1081/*
638a1a01
SC		 1082 * qla2x00_wait_for_hba_ready
1083 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1084 *
1085 * Input:
1086 * ha - pointer to host adapter structure
1087 *
1088 * Note:
1089 * Does context switching-Release SPIN_LOCK
1090 * (if any) before calling this routine.
1091 *
86fbee86 1092 */
638a1a01
SC		 1093static void
1094qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1095{
86fbee86 1096 struct qla_hw_data *ha = vha->hw;
783e0dc4 1097 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1098
1d483901
DC		 1099 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1100 ha->flags.mbox_busy) ||
1101 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1102 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1103 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1104 break;
86fbee86 1105 msleep(1000);
783e0dc4 1106 }
86fbee86
LC		 1107}
1108
2533cf67
LC		 1109int
1110qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1111{
1112 int return_status;
1113 unsigned long wait_reset;
1114 struct qla_hw_data *ha = vha->hw;
1115 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1116
1117 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1118 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1119 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1120 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1121 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1122
1123 msleep(1000);
1124
1125 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1126 ha->flags.chip_reset_done)
1127 break;
1128 }
1129 if (ha->flags.chip_reset_done)
1130 return_status = QLA_SUCCESS;
1131 else
1132 return_status = QLA_FUNCTION_FAILED;
1133
1134 return return_status;
1135}
1136
083a469d
GM		 1137static void
1138sp_get(struct srb *sp)
1139{
1140 atomic_inc(&sp->ref_count);
1141}
1142
a465537a
SC		 1143#define ISP_REG_DISCONNECT 0xffffffffU
1144/**************************************************************************
1145* qla2x00_isp_reg_stat
1146*
1147* Description:
1148* Read the host status register of ISP before aborting the command.
1149*
1150* Input:
1151* ha = pointer to host adapter structure.
1152*
1153*
1154* Returns:
1155* Either true or false.
1156*
1157* Note: Return true if there is register disconnect.
1158**************************************************************************/
1159static inline
1160uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1161{
1162 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1163 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1164
bf6061b1
SC		 1165 if (IS_P3P_TYPE(ha))
1166 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1167 else
1168 return ((RD_REG_DWORD(&reg->host_status)) ==
1169 ISP_REG_DISCONNECT);
a465537a
SC		 1170}
1171
1da177e4
LT		 1172/**************************************************************************
1173* qla2xxx_eh_abort
1174*
1175* Description:
1176* The abort function will abort the specified command.
1177*
1178* Input:
1179* cmd = Linux SCSI command packet to be aborted.
1180*
1181* Returns:
1182* Either SUCCESS or FAILED.
1183*
1184* Note:
2ea00202 1185* Only return FAILED if command not returned by firmware.
1da177e4 1186**************************************************************************/
e5f82ab8 1187static int
1da177e4
LT		 1188qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1189{
e315cd28 1190 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1191 srb_t *sp;
4e98d3b8 1192 int ret;
9cb78c16
HR		 1193 unsigned int id;
1194 uint64_t lun;
18e144d3 1195 unsigned long flags;
f934c9d0 1196 int rval, wait = 0;
e315cd28 1197 struct qla_hw_data *ha = vha->hw;
1da177e4 1198
a465537a
SC		 1199 if (qla2x00_isp_reg_stat(ha)) {
1200 ql_log(ql_log_info, vha, 0x8042,
1201 "PCI/Register disconnect, exiting.\n");
1202 return FAILED;
1203 }
f4f051eb 1204 if (!CMD_SP(cmd))
2ea00202 1205 return SUCCESS;
1da177e4 1206
4e98d3b8
AV		 1207 ret = fc_block_scsi_eh(cmd);
1208 if (ret != 0)
1209 return ret;
1210 ret = SUCCESS;
1211
f4f051eb
AV		 1212 id = cmd->device->id;
1213 lun = cmd->device->lun;
1da177e4 1214
e315cd28 1215 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1216 sp = (srb_t *) CMD_SP(cmd);
1217 if (!sp) {
1218 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1219 return SUCCESS;
1220 }
1da177e4 1221
7c3df132 1222 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1223 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1224 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1225
170babc3
MC		 1226 /* Get a reference to the sp and drop the lock.*/
1227 sp_get(sp);
083a469d 1228
e315cd28 1229 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1230 rval = ha->isp_ops->abort_command(sp);
1231 if (rval) {
96219424 1232 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1233 ret = SUCCESS;
96219424 1234 else
f934c9d0
CD		 1235 ret = FAILED;
1236
7c3df132 1237 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1238 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1239 } else {
7c3df132 1240 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1241 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1242 wait = 1;
1243 }
75942064
SK		 1244
1245 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1246 sp->done(sp, 0);
75942064 1247 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1248
bc91ade9
CD		 1249 /* Did the command return during mailbox execution? */
1250 if (ret == FAILED && !CMD_SP(cmd))
1251 ret = SUCCESS;
1252
f4f051eb 1253 /* Wait for the command to be returned. */
2ea00202 1254 if (wait) {
e315cd28 1255 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1256 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1257 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1258 ret = FAILED;
f4f051eb 1259 }
1da177e4 1260 }
1da177e4 1261
7c3df132 1262 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1263 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1264 vha->host_no, id, lun, wait, ret);
1da177e4 1265
f4f051eb
AV		 1266 return ret;
1267}
1da177e4 1268
4d78c973 1269int
e315cd28 1270qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1271 uint64_t l, enum nexus_wait_type type)
f4f051eb 1272{
17d98630 1273 int cnt, match, status;
18e144d3 1274 unsigned long flags;
e315cd28 1275 struct qla_hw_data *ha = vha->hw;
73208dfd 1276 struct req_que *req;
4d78c973 1277 srb_t *sp;
9ba56b95 1278 struct scsi_cmnd *cmd;
1da177e4 1279
523ec773 1280 status = QLA_SUCCESS;
17d98630 1281
e315cd28 1282 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1283 req = vha->req;
17d98630 1284 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1285 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1286 sp = req->outstanding_cmds[cnt];
1287 if (!sp)
523ec773 1288 continue;
9ba56b95 1289 if (sp->type != SRB_SCSI_CMD)
cf53b069 1290 continue;
25ff6af1 1291 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1292 continue;
1293 match = 0;
9ba56b95 1294 cmd = GET_CMD_SP(sp);
17d98630
AC		 1295 switch (type) {
1296 case WAIT_HOST:
1297 match = 1;
1298 break;
1299 case WAIT_TARGET:
9ba56b95 1300 match = cmd->device->id == t;
17d98630
AC		 1301 break;
1302 case WAIT_LUN:
9ba56b95
GM		 1303 match = (cmd->device->id == t &&
1304 cmd->device->lun == l);
17d98630 1305 break;
73208dfd 1306 }
17d98630
AC		 1307 if (!match)
1308 continue;
1309
1310 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1311 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1312 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1313 }
e315cd28 1314 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1315
1316 return status;
1da177e4
LT		 1317}
1318
523ec773
AV		 1319static char *reset_errors[] = {
1320 "HBA not online",
1321 "HBA not ready",
1322 "Task management failed",
1323 "Waiting for command completions",
1324};
1da177e4 1325
e5f82ab8 1326static int
523ec773 1327__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1328 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1329{
e315cd28 1330 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1331 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1332 int err;
1da177e4 1333
7c3df132 1334 if (!fcport) {
523ec773 1335 return FAILED;
7c3df132 1336 }
1da177e4 1337
4e98d3b8
AV		 1338 err = fc_block_scsi_eh(cmd);
1339 if (err != 0)
1340 return err;
1341
7c3df132 1342 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1343 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1344 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1345
523ec773 1346 err = 0;
7c3df132
SK		 1347 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1348 ql_log(ql_log_warn, vha, 0x800a,
1349 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1350 goto eh_reset_failed;
7c3df132 1351 }
523ec773 1352 err = 2;
2afa19a9 1353 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1354 != QLA_SUCCESS) {
1355 ql_log(ql_log_warn, vha, 0x800c,
1356 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1357 goto eh_reset_failed;
7c3df132 1358 }
523ec773 1359 err = 3;
e315cd28 1360 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1361 cmd->device->lun, type) != QLA_SUCCESS) {
1362 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1363 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1364 goto eh_reset_failed;
7c3df132 1365 }
523ec773 1366
7c3df132 1367 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1368 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1369 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1370
1371 return SUCCESS;
1372
4d78c973 1373eh_reset_failed:
7c3df132 1374 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1375 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1376 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1377 cmd);
523ec773
AV		 1378 return FAILED;
1379}
1da177e4 1380
523ec773
AV		 1381static int
1382qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1383{
e315cd28
AC		 1384 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1385 struct qla_hw_data *ha = vha->hw;
1da177e4 1386
a465537a
SC		 1387 if (qla2x00_isp_reg_stat(ha)) {
1388 ql_log(ql_log_info, vha, 0x803e,
1389 "PCI/Register disconnect, exiting.\n");
1390 return FAILED;
1391 }
1392
523ec773
AV		 1393 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1394 ha->isp_ops->lun_reset);
1da177e4
LT		 1395}
1396
1da177e4 1397static int
523ec773 1398qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1399{
e315cd28
AC		 1400 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1401 struct qla_hw_data *ha = vha->hw;
1da177e4 1402
a465537a
SC		 1403 if (qla2x00_isp_reg_stat(ha)) {
1404 ql_log(ql_log_info, vha, 0x803f,
1405 "PCI/Register disconnect, exiting.\n");
1406 return FAILED;
1407 }
1408
523ec773
AV		 1409 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1410 ha->isp_ops->target_reset);
1da177e4
LT		 1411}
1412
1da177e4
LT		 1413/**************************************************************************
1414* qla2xxx_eh_bus_reset
1415*
1416* Description:
1417* The bus reset function will reset the bus and abort any executing
1418* commands.
1419*
1420* Input:
1421* cmd = Linux SCSI command packet of the command that cause the
1422* bus reset.
1423*
1424* Returns:
1425* SUCCESS/FAILURE (defined as macro in scsi.h).
1426*
1427**************************************************************************/
e5f82ab8 1428static int
1da177e4
LT		 1429qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1430{
e315cd28 1431 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1432 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1433 int ret = FAILED;
9cb78c16
HR		 1434 unsigned int id;
1435 uint64_t lun;
a465537a
SC		 1436 struct qla_hw_data *ha = vha->hw;
1437
1438 if (qla2x00_isp_reg_stat(ha)) {
1439 ql_log(ql_log_info, vha, 0x8040,
1440 "PCI/Register disconnect, exiting.\n");
1441 return FAILED;
1442 }
f4f051eb 1443
f4f051eb
AV		 1444 id = cmd->device->id;
1445 lun = cmd->device->lun;
1da177e4 1446
7c3df132 1447 if (!fcport) {
f4f051eb 1448 return ret;
7c3df132 1449 }
1da177e4 1450
4e98d3b8
AV		 1451 ret = fc_block_scsi_eh(cmd);
1452 if (ret != 0)
1453 return ret;
1454 ret = FAILED;
1455
7c3df132 1456 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1457 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1458
e315cd28 1459 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1460 ql_log(ql_log_fatal, vha, 0x8013,
1461 "Wait for hba online failed board disabled.\n");
f4f051eb 1462 goto eh_bus_reset_done;
1da177e4
LT		 1463 }
1464
ad537689
SK		 1465 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1466 ret = SUCCESS;
1467
f4f051eb
AV		 1468 if (ret == FAILED)
1469 goto eh_bus_reset_done;
1da177e4 1470
9a41a62b 1471 /* Flush outstanding commands. */
4d78c973 1472 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1473 QLA_SUCCESS) {
1474 ql_log(ql_log_warn, vha, 0x8014,
1475 "Wait for pending commands failed.\n");
9a41a62b 1476 ret = FAILED;
7c3df132 1477 }
1da177e4 1478
f4f051eb 1479eh_bus_reset_done:
7c3df132 1480 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1481 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1482 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1483
f4f051eb 1484 return ret;
1da177e4
LT		 1485}
1486
1487/**************************************************************************
1488* qla2xxx_eh_host_reset
1489*
1490* Description:
1491* The reset function will reset the Adapter.
1492*
1493* Input:
1494* cmd = Linux SCSI command packet of the command that cause the
1495* adapter reset.
1496*
1497* Returns:
1498* Either SUCCESS or FAILED.
1499*
1500* Note:
1501**************************************************************************/
e5f82ab8 1502static int
1da177e4
LT		 1503qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1504{
e315cd28 1505 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1506 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1507 int ret = FAILED;
9cb78c16
HR		 1508 unsigned int id;
1509 uint64_t lun;
e315cd28 1510 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1511
a465537a
SC		 1512 if (qla2x00_isp_reg_stat(ha)) {
1513 ql_log(ql_log_info, vha, 0x8041,
1514 "PCI/Register disconnect, exiting.\n");
1515 schedule_work(&ha->board_disable);
1516 return SUCCESS;
1517 }
1518
f4f051eb
AV		 1519 id = cmd->device->id;
1520 lun = cmd->device->lun;
f4f051eb 1521
7c3df132 1522 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1523 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1524
63ee7072
CD		 1525 /*
1526 * No point in issuing another reset if one is active. Also do not
1527 * attempt a reset if we are updating flash.
1528 */
1529 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1530 goto eh_host_reset_lock;
1da177e4 1531
e315cd28
AC		 1532 if (vha != base_vha) {
1533 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1534 goto eh_host_reset_lock;
e315cd28 1535 } else {
7ec0effd 1536 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1537 if (!qla82xx_fcoe_ctx_reset(vha)) {
1538 /* Ctx reset success */
1539 ret = SUCCESS;
1540 goto eh_host_reset_lock;
1541 }
1542 /* fall thru if ctx reset failed */
1543 }
68ca949c
AC		 1544 if (ha->wq)
1545 flush_workqueue(ha->wq);
1546
e315cd28 1547 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1548 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1549 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1550 /* failed. schedule dpc to try */
1551 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1552
7c3df132
SK		 1553 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1554 ql_log(ql_log_warn, vha, 0x802a,
1555 "wait for hba online failed.\n");
e315cd28 1556 goto eh_host_reset_lock;
7c3df132 1557 }
e315cd28
AC		 1558 }
1559 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1560 }
1da177e4 1561
e315cd28 1562 /* Waiting for command to be returned to OS.*/
4d78c973 1563 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1564 QLA_SUCCESS)
f4f051eb 1565 ret = SUCCESS;
1da177e4 1566
f4f051eb 1567eh_host_reset_lock:
cfb0919c 1568 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1569 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1570 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1571
f4f051eb
AV		 1572 return ret;
1573}
1da177e4
LT		 1574
1575/*
1576* qla2x00_loop_reset
1577* Issue loop reset.
1578*
1579* Input:
1580* ha = adapter block pointer.
1581*
1582* Returns:
1583* 0 = success
1584*/
a4722cf2 1585int
e315cd28 1586qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1587{
0c8c39af 1588 int ret;
bdf79621 1589 struct fc_port *fcport;
e315cd28 1590 struct qla_hw_data *ha = vha->hw;
1da177e4 1591
5854771e
AB		 1592 if (IS_QLAFX00(ha)) {
1593 return qlafx00_loop_reset(vha);
1594 }
1595
f4c496c1 1596 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1597 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1598 if (fcport->port_type != FCT_TARGET)
1599 continue;
1600
1601 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1602 if (ret != QLA_SUCCESS) {
7c3df132 1603 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1604 "Bus Reset failed: Reset=%d "
7c3df132 1605 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1606 }
1607 }
1608 }
1609
8ae6d9c7 1610
6246b8a1 1611 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1612 atomic_set(&vha->loop_state, LOOP_DOWN);
1613 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1614 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1615 ret = qla2x00_full_login_lip(vha);
0c8c39af 1616 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1617 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1618 "full_login_lip=%d.\n", ret);
749af3d5 1619 }
0c8c39af
AV		 1620 }
1621
0d6e61bc 1622 if (ha->flags.enable_lip_reset) {
e315cd28 1623 ret = qla2x00_lip_reset(vha);
ad537689 1624 if (ret != QLA_SUCCESS)
7c3df132
SK		 1625 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1626 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1627 }
1628
1da177e4 1629 /* Issue marker command only when we are going to start the I/O */
e315cd28 1630 vha->marker_needed = 1;
1da177e4 1631
0c8c39af 1632 return QLA_SUCCESS;
1da177e4
LT		 1633}
1634
df4bf0bb 1635void
e315cd28 1636qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1637{
73208dfd 1638 int que, cnt;
df4bf0bb
AV		 1639 unsigned long flags;
1640 srb_t *sp;
e315cd28 1641 struct qla_hw_data *ha = vha->hw;
73208dfd 1642 struct req_que *req;
df4bf0bb 1643
c0cb4496
AE		 1644 qlt_host_reset_handler(ha);
1645
df4bf0bb 1646 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1647 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1648 req = ha->req_q_map[que];
73208dfd
AC		 1649 if (!req)
1650 continue;
8d93f550
CD		 1651 if (!req->outstanding_cmds)
1652 continue;
1653 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1654 sp = req->outstanding_cmds[cnt];
e612d465 1655 if (sp) {
c733ab35
MFO		 1656 /* Don't abort commands in adapter during EEH
1657 * recovery as it's not accessible/responding.
1535aa75 1658 */
5f7c2bee
BK		 1659 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1660 (sp->type == SRB_SCSI_CMD)) {
c733ab35
MFO		 1661 /* Get a reference to the sp and drop the lock.
1662 * The reference ensures this sp->done() call
1663 * - and not the call in qla2xxx_eh_abort() -
1664 * ends the SCSI command (with result 'res').
1665 */
1666 sp_get(sp);
1667 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1668 qla2xxx_eh_abort(GET_CMD_SP(sp));
1669 spin_lock_irqsave(&ha->hardware_lock, flags);
1670 }
73208dfd 1671 req->outstanding_cmds[cnt] = NULL;
25ff6af1 1672 sp->done(sp, res);
73208dfd 1673 }
df4bf0bb
AV		 1674 }
1675 }
1676 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1677}
1678
f4f051eb
AV		 1679static int
1680qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1681{
bdf79621 1682 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1683
19a7b4ae 1684 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1685 return -ENXIO;
bdf79621 1686
19a7b4ae 1687 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1688
f4f051eb
AV		 1689 return 0;
1690}
1da177e4 1691
f4f051eb
AV		 1692static int
1693qla2xxx_slave_configure(struct scsi_device *sdev)
1694{
e315cd28 1695 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1696 struct req_que *req = vha->req;
8482e118 1697
9e522cd8
AE		 1698 if (IS_T10_PI_CAPABLE(vha->hw))
1699 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1700
db5ed4df 1701 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1702 return 0;
1703}
1da177e4 1704
f4f051eb
AV		 1705static void
1706qla2xxx_slave_destroy(struct scsi_device *sdev)
1707{
1708 sdev->hostdata = NULL;
1da177e4
LT		 1709}
1710
1711/**
1712 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1713 * @ha: HA context
1714 *
1715 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1716 * supported addressing method.
1717 */
1718static void
53303c42 1719qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1720{
7524f9b9 1721 /* Assume a 32bit DMA mask. */
1da177e4 1722 ha->flags.enable_64bit_addressing = 0;
1da177e4 1723
6a35528a 1724 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1725 /* Any upper-dword bits set? */
1726 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1727 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1728 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1729 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1730 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1731 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1732 return;
1da177e4 1733 }
1da177e4 1734 }
7524f9b9 1735
284901a9
YH		 1736 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1737 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1738}
1739
fd34f556 1740static void
e315cd28 1741qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1742{
1743 unsigned long flags = 0;
1744 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1745
1746 spin_lock_irqsave(&ha->hardware_lock, flags);
1747 ha->interrupts_on = 1;
1748 /* enable risc and host interrupts */
1749 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1750 RD_REG_WORD(&reg->ictrl);
1751 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1752
1753}
1754
1755static void
e315cd28 1756qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1757{
1758 unsigned long flags = 0;
1759 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1760
1761 spin_lock_irqsave(&ha->hardware_lock, flags);
1762 ha->interrupts_on = 0;
1763 /* disable risc and host interrupts */
1764 WRT_REG_WORD(&reg->ictrl, 0);
1765 RD_REG_WORD(&reg->ictrl);
1766 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1767}
1768
1769static void
e315cd28 1770qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1771{
1772 unsigned long flags = 0;
1773 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1774
1775 spin_lock_irqsave(&ha->hardware_lock, flags);
1776 ha->interrupts_on = 1;
1777 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1778 RD_REG_DWORD(&reg->ictrl);
1779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1780}
1781
1782static void
e315cd28 1783qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1784{
1785 unsigned long flags = 0;
1786 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1787
124f85e6
AV		 1788 if (IS_NOPOLLING_TYPE(ha))
1789 return;
fd34f556
AV		 1790 spin_lock_irqsave(&ha->hardware_lock, flags);
1791 ha->interrupts_on = 0;
1792 WRT_REG_DWORD(&reg->ictrl, 0);
1793 RD_REG_DWORD(&reg->ictrl);
1794 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1795}
1796
706f457d
GM		 1797static int
1798qla2x00_iospace_config(struct qla_hw_data *ha)
1799{
1800 resource_size_t pio;
1801 uint16_t msix;
706f457d 1802
706f457d
GM		 1803 if (pci_request_selected_regions(ha->pdev, ha->bars,
1804 QLA2XXX_DRIVER_NAME)) {
1805 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1806 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1807 pci_name(ha->pdev));
1808 goto iospace_error_exit;
1809 }
1810 if (!(ha->bars & 1))
1811 goto skip_pio;
1812
1813 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1814 pio = pci_resource_start(ha->pdev, 0);
1815 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1816 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1817 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1818 "Invalid pci I/O region size (%s).\n",
1819 pci_name(ha->pdev));
1820 pio = 0;
1821 }
1822 } else {
1823 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1824 "Region #0 no a PIO resource (%s).\n",
1825 pci_name(ha->pdev));
1826 pio = 0;
1827 }
1828 ha->pio_address = pio;
1829 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1830 "PIO address=%llu.\n",
1831 (unsigned long long)ha->pio_address);
1832
1833skip_pio:
1834 /* Use MMIO operations for all accesses. */
1835 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1836 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1837 "Region #1 not an MMIO resource (%s), aborting.\n",
1838 pci_name(ha->pdev));
1839 goto iospace_error_exit;
1840 }
1841 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1842 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1843 "Invalid PCI mem region size (%s), aborting.\n",
1844 pci_name(ha->pdev));
1845 goto iospace_error_exit;
1846 }
1847
1848 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1849 if (!ha->iobase) {
1850 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1851 "Cannot remap MMIO (%s), aborting.\n",
1852 pci_name(ha->pdev));
1853 goto iospace_error_exit;
1854 }
1855
1856 /* Determine queue resources */
1857 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1858 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1859 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1860 goto mqiobase_exit;
1861
1862 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1863 pci_resource_len(ha->pdev, 3));
1864 if (ha->mqiobase) {
1865 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1866 "MQIO Base=%p.\n", ha->mqiobase);
1867 /* Read MSIX vector size of the board */
1868 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1869 ha->msix_count = msix + 1;
706f457d 1870 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1871 /* MB interrupt uses 1 vector */
1872 ha->max_req_queues = ha->msix_count - 1;
1873 ha->max_rsp_queues = ha->max_req_queues;
1874 /* Queue pairs is the max value minus the base queue pair */
1875 ha->max_qpairs = ha->max_rsp_queues - 1;
1876 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1877 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1878
706f457d 1879 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1880 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1881 } else
1882 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1883 "BAR 3 not enabled.\n");
1884
1885mqiobase_exit:
706f457d 1886 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1887 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1888 return (0);
1889
1890iospace_error_exit:
1891 return (-ENOMEM);
1892}
1893
1894
6246b8a1
GM		 1895static int
1896qla83xx_iospace_config(struct qla_hw_data *ha)
1897{
1898 uint16_t msix;
6246b8a1
GM		 1899
1900 if (pci_request_selected_regions(ha->pdev, ha->bars,
1901 QLA2XXX_DRIVER_NAME)) {
1902 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1903 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1904 pci_name(ha->pdev));
1905
1906 goto iospace_error_exit;
1907 }
1908
1909 /* Use MMIO operations for all accesses. */
1910 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1911 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1912 "Invalid pci I/O region size (%s).\n",
1913 pci_name(ha->pdev));
1914 goto iospace_error_exit;
1915 }
1916 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1917 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1918 "Invalid PCI mem region size (%s), aborting\n",
1919 pci_name(ha->pdev));
1920 goto iospace_error_exit;
1921 }
1922
1923 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1924 if (!ha->iobase) {
1925 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1926 "Cannot remap MMIO (%s), aborting.\n",
1927 pci_name(ha->pdev));
1928 goto iospace_error_exit;
1929 }
1930
1931 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1932 /* 83XX 26XX always use MQ type access for queues
1933 * - mbar 2, a.k.a region 4 */
1934 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1935 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 1936 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1937 pci_resource_len(ha->pdev, 4));
1938
1939 if (!ha->mqiobase) {
1940 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1941 "BAR2/region4 not enabled\n");
1942 goto mqiobase_exit;
1943 }
1944
1945 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1946 pci_resource_len(ha->pdev, 2));
1947 if (ha->msixbase) {
1948 /* Read MSIX vector size of the board */
1949 pci_read_config_word(ha->pdev,
1950 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1951 ha->msix_count = msix + 1;
093df737
QT		 1952 /*
1953 * By default, driver uses at least two msix vectors
1954 * (default & rspq)
1955 */
d7459527
MH		 1956 if (ql2xmqsupport) {
1957 /* MB interrupt uses 1 vector */
1958 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 1959
1960 /* ATIOQ needs 1 vector. That's 1 less QPair */
1961 if (QLA_TGT_MODE_ENABLED())
1962 ha->max_req_queues--;
1963
d0d2c68b
MH		 1964 ha->max_rsp_queues = ha->max_req_queues;
1965
d7459527
MH		 1966 /* Queue pairs is the max value minus
1967 * the base queue pair */
1968 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1969 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1970 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1971 }
1972 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1973 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1974 } else
1975 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1976 "BAR 1 not enabled.\n");
1977
1978mqiobase_exit:
6246b8a1 1979 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 1980 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 1981 return 0;
1982
1983iospace_error_exit:
1984 return -ENOMEM;
1985}
1986
fd34f556
AV		 1987static struct isp_operations qla2100_isp_ops = {
1988 .pci_config = qla2100_pci_config,
1989 .reset_chip = qla2x00_reset_chip,
1990 .chip_diag = qla2x00_chip_diag,
1991 .config_rings = qla2x00_config_rings,
1992 .reset_adapter = qla2x00_reset_adapter,
1993 .nvram_config = qla2x00_nvram_config,
1994 .update_fw_options = qla2x00_update_fw_options,
1995 .load_risc = qla2x00_load_risc,
1996 .pci_info_str = qla2x00_pci_info_str,
1997 .fw_version_str = qla2x00_fw_version_str,
1998 .intr_handler = qla2100_intr_handler,
1999 .enable_intrs = qla2x00_enable_intrs,
2000 .disable_intrs = qla2x00_disable_intrs,
2001 .abort_command = qla2x00_abort_command,
523ec773
AV		 2002 .target_reset = qla2x00_abort_target,
2003 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2004 .fabric_login = qla2x00_login_fabric,
2005 .fabric_logout = qla2x00_fabric_logout,
2006 .calc_req_entries = qla2x00_calc_iocbs_32,
2007 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2008 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2009 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2010 .read_nvram = qla2x00_read_nvram_data,
2011 .write_nvram = qla2x00_write_nvram_data,
2012 .fw_dump = qla2100_fw_dump,
2013 .beacon_on = NULL,
2014 .beacon_off = NULL,
2015 .beacon_blink = NULL,
2016 .read_optrom = qla2x00_read_optrom_data,
2017 .write_optrom = qla2x00_write_optrom_data,
2018 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2019 .start_scsi = qla2x00_start_scsi,
d7459527 2020 .start_scsi_mq = NULL,
a9083016 2021 .abort_isp = qla2x00_abort_isp,
706f457d 2022 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2023 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2024};
2025
2026static struct isp_operations qla2300_isp_ops = {
2027 .pci_config = qla2300_pci_config,
2028 .reset_chip = qla2x00_reset_chip,
2029 .chip_diag = qla2x00_chip_diag,
2030 .config_rings = qla2x00_config_rings,
2031 .reset_adapter = qla2x00_reset_adapter,
2032 .nvram_config = qla2x00_nvram_config,
2033 .update_fw_options = qla2x00_update_fw_options,
2034 .load_risc = qla2x00_load_risc,
2035 .pci_info_str = qla2x00_pci_info_str,
2036 .fw_version_str = qla2x00_fw_version_str,
2037 .intr_handler = qla2300_intr_handler,
2038 .enable_intrs = qla2x00_enable_intrs,
2039 .disable_intrs = qla2x00_disable_intrs,
2040 .abort_command = qla2x00_abort_command,
523ec773
AV		 2041 .target_reset = qla2x00_abort_target,
2042 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2043 .fabric_login = qla2x00_login_fabric,
2044 .fabric_logout = qla2x00_fabric_logout,
2045 .calc_req_entries = qla2x00_calc_iocbs_32,
2046 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2047 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2048 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2049 .read_nvram = qla2x00_read_nvram_data,
2050 .write_nvram = qla2x00_write_nvram_data,
2051 .fw_dump = qla2300_fw_dump,
2052 .beacon_on = qla2x00_beacon_on,
2053 .beacon_off = qla2x00_beacon_off,
2054 .beacon_blink = qla2x00_beacon_blink,
2055 .read_optrom = qla2x00_read_optrom_data,
2056 .write_optrom = qla2x00_write_optrom_data,
2057 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2058 .start_scsi = qla2x00_start_scsi,
d7459527 2059 .start_scsi_mq = NULL,
a9083016 2060 .abort_isp = qla2x00_abort_isp,
7ec0effd 2061 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2062 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2063};
2064
2065static struct isp_operations qla24xx_isp_ops = {
2066 .pci_config = qla24xx_pci_config,
2067 .reset_chip = qla24xx_reset_chip,
2068 .chip_diag = qla24xx_chip_diag,
2069 .config_rings = qla24xx_config_rings,
2070 .reset_adapter = qla24xx_reset_adapter,
2071 .nvram_config = qla24xx_nvram_config,
2072 .update_fw_options = qla24xx_update_fw_options,
2073 .load_risc = qla24xx_load_risc,
2074 .pci_info_str = qla24xx_pci_info_str,
2075 .fw_version_str = qla24xx_fw_version_str,
2076 .intr_handler = qla24xx_intr_handler,
2077 .enable_intrs = qla24xx_enable_intrs,
2078 .disable_intrs = qla24xx_disable_intrs,
2079 .abort_command = qla24xx_abort_command,
523ec773
AV		 2080 .target_reset = qla24xx_abort_target,
2081 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2082 .fabric_login = qla24xx_login_fabric,
2083 .fabric_logout = qla24xx_fabric_logout,
2084 .calc_req_entries = NULL,
2085 .build_iocbs = NULL,
2086 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2087 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2088 .read_nvram = qla24xx_read_nvram_data,
2089 .write_nvram = qla24xx_write_nvram_data,
2090 .fw_dump = qla24xx_fw_dump,
2091 .beacon_on = qla24xx_beacon_on,
2092 .beacon_off = qla24xx_beacon_off,
2093 .beacon_blink = qla24xx_beacon_blink,
2094 .read_optrom = qla24xx_read_optrom_data,
2095 .write_optrom = qla24xx_write_optrom_data,
2096 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2097 .start_scsi = qla24xx_start_scsi,
d7459527 2098 .start_scsi_mq = NULL,
a9083016 2099 .abort_isp = qla2x00_abort_isp,
7ec0effd 2100 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2101 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2102};
2103
c3a2f0df
AV		 2104static struct isp_operations qla25xx_isp_ops = {
2105 .pci_config = qla25xx_pci_config,
2106 .reset_chip = qla24xx_reset_chip,
2107 .chip_diag = qla24xx_chip_diag,
2108 .config_rings = qla24xx_config_rings,
2109 .reset_adapter = qla24xx_reset_adapter,
2110 .nvram_config = qla24xx_nvram_config,
2111 .update_fw_options = qla24xx_update_fw_options,
2112 .load_risc = qla24xx_load_risc,
2113 .pci_info_str = qla24xx_pci_info_str,
2114 .fw_version_str = qla24xx_fw_version_str,
2115 .intr_handler = qla24xx_intr_handler,
2116 .enable_intrs = qla24xx_enable_intrs,
2117 .disable_intrs = qla24xx_disable_intrs,
2118 .abort_command = qla24xx_abort_command,
523ec773
AV		 2119 .target_reset = qla24xx_abort_target,
2120 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2121 .fabric_login = qla24xx_login_fabric,
2122 .fabric_logout = qla24xx_fabric_logout,
2123 .calc_req_entries = NULL,
2124 .build_iocbs = NULL,
2125 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2126 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2127 .read_nvram = qla25xx_read_nvram_data,
2128 .write_nvram = qla25xx_write_nvram_data,
2129 .fw_dump = qla25xx_fw_dump,
2130 .beacon_on = qla24xx_beacon_on,
2131 .beacon_off = qla24xx_beacon_off,
2132 .beacon_blink = qla24xx_beacon_blink,
338c9161 2133 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2134 .write_optrom = qla24xx_write_optrom_data,
2135 .get_flash_version = qla24xx_get_flash_version,
bad75002 2136 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2137 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2138 .abort_isp = qla2x00_abort_isp,
7ec0effd 2139 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2140 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2141};
2142
3a03eb79
AV		 2143static struct isp_operations qla81xx_isp_ops = {
2144 .pci_config = qla25xx_pci_config,
2145 .reset_chip = qla24xx_reset_chip,
2146 .chip_diag = qla24xx_chip_diag,
2147 .config_rings = qla24xx_config_rings,
2148 .reset_adapter = qla24xx_reset_adapter,
2149 .nvram_config = qla81xx_nvram_config,
2150 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2151 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2152 .pci_info_str = qla24xx_pci_info_str,
2153 .fw_version_str = qla24xx_fw_version_str,
2154 .intr_handler = qla24xx_intr_handler,
2155 .enable_intrs = qla24xx_enable_intrs,
2156 .disable_intrs = qla24xx_disable_intrs,
2157 .abort_command = qla24xx_abort_command,
2158 .target_reset = qla24xx_abort_target,
2159 .lun_reset = qla24xx_lun_reset,
2160 .fabric_login = qla24xx_login_fabric,
2161 .fabric_logout = qla24xx_fabric_logout,
2162 .calc_req_entries = NULL,
2163 .build_iocbs = NULL,
2164 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2165 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2166 .read_nvram = NULL,
2167 .write_nvram = NULL,
3a03eb79
AV		 2168 .fw_dump = qla81xx_fw_dump,
2169 .beacon_on = qla24xx_beacon_on,
2170 .beacon_off = qla24xx_beacon_off,
6246b8a1 2171 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2172 .read_optrom = qla25xx_read_optrom_data,
2173 .write_optrom = qla24xx_write_optrom_data,
2174 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2175 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2176 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2177 .abort_isp = qla2x00_abort_isp,
7ec0effd 2178 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2179 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2180};
2181
2182static struct isp_operations qla82xx_isp_ops = {
2183 .pci_config = qla82xx_pci_config,
2184 .reset_chip = qla82xx_reset_chip,
2185 .chip_diag = qla24xx_chip_diag,
2186 .config_rings = qla82xx_config_rings,
2187 .reset_adapter = qla24xx_reset_adapter,
2188 .nvram_config = qla81xx_nvram_config,
2189 .update_fw_options = qla24xx_update_fw_options,
2190 .load_risc = qla82xx_load_risc,
9d55ca66 2191 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2192 .fw_version_str = qla24xx_fw_version_str,
2193 .intr_handler = qla82xx_intr_handler,
2194 .enable_intrs = qla82xx_enable_intrs,
2195 .disable_intrs = qla82xx_disable_intrs,
2196 .abort_command = qla24xx_abort_command,
2197 .target_reset = qla24xx_abort_target,
2198 .lun_reset = qla24xx_lun_reset,
2199 .fabric_login = qla24xx_login_fabric,
2200 .fabric_logout = qla24xx_fabric_logout,
2201 .calc_req_entries = NULL,
2202 .build_iocbs = NULL,
2203 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2204 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2205 .read_nvram = qla24xx_read_nvram_data,
2206 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2207 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2208 .beacon_on = qla82xx_beacon_on,
2209 .beacon_off = qla82xx_beacon_off,
2210 .beacon_blink = NULL,
a9083016
GM		 2211 .read_optrom = qla82xx_read_optrom_data,
2212 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2213 .get_flash_version = qla82xx_get_flash_version,
a9083016 2214 .start_scsi = qla82xx_start_scsi,
d7459527 2215 .start_scsi_mq = NULL,
a9083016 2216 .abort_isp = qla82xx_abort_isp,
706f457d 2217 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2218 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2219};
2220
7ec0effd
AD		 2221static struct isp_operations qla8044_isp_ops = {
2222 .pci_config = qla82xx_pci_config,
2223 .reset_chip = qla82xx_reset_chip,
2224 .chip_diag = qla24xx_chip_diag,
2225 .config_rings = qla82xx_config_rings,
2226 .reset_adapter = qla24xx_reset_adapter,
2227 .nvram_config = qla81xx_nvram_config,
2228 .update_fw_options = qla24xx_update_fw_options,
2229 .load_risc = qla82xx_load_risc,
2230 .pci_info_str = qla24xx_pci_info_str,
2231 .fw_version_str = qla24xx_fw_version_str,
2232 .intr_handler = qla8044_intr_handler,
2233 .enable_intrs = qla82xx_enable_intrs,
2234 .disable_intrs = qla82xx_disable_intrs,
2235 .abort_command = qla24xx_abort_command,
2236 .target_reset = qla24xx_abort_target,
2237 .lun_reset = qla24xx_lun_reset,
2238 .fabric_login = qla24xx_login_fabric,
2239 .fabric_logout = qla24xx_fabric_logout,
2240 .calc_req_entries = NULL,
2241 .build_iocbs = NULL,
2242 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2243 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2244 .read_nvram = NULL,
2245 .write_nvram = NULL,
a1b23c5a 2246 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2247 .beacon_on = qla82xx_beacon_on,
2248 .beacon_off = qla82xx_beacon_off,
2249 .beacon_blink = NULL,
888e639d 2250 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2251 .write_optrom = qla8044_write_optrom_data,
2252 .get_flash_version = qla82xx_get_flash_version,
2253 .start_scsi = qla82xx_start_scsi,
d7459527 2254 .start_scsi_mq = NULL,
7ec0effd
AD		 2255 .abort_isp = qla8044_abort_isp,
2256 .iospace_config = qla82xx_iospace_config,
2257 .initialize_adapter = qla2x00_initialize_adapter,
2258};
2259
6246b8a1
GM		 2260static struct isp_operations qla83xx_isp_ops = {
2261 .pci_config = qla25xx_pci_config,
2262 .reset_chip = qla24xx_reset_chip,
2263 .chip_diag = qla24xx_chip_diag,
2264 .config_rings = qla24xx_config_rings,
2265 .reset_adapter = qla24xx_reset_adapter,
2266 .nvram_config = qla81xx_nvram_config,
2267 .update_fw_options = qla81xx_update_fw_options,
2268 .load_risc = qla81xx_load_risc,
2269 .pci_info_str = qla24xx_pci_info_str,
2270 .fw_version_str = qla24xx_fw_version_str,
2271 .intr_handler = qla24xx_intr_handler,
2272 .enable_intrs = qla24xx_enable_intrs,
2273 .disable_intrs = qla24xx_disable_intrs,
2274 .abort_command = qla24xx_abort_command,
2275 .target_reset = qla24xx_abort_target,
2276 .lun_reset = qla24xx_lun_reset,
2277 .fabric_login = qla24xx_login_fabric,
2278 .fabric_logout = qla24xx_fabric_logout,
2279 .calc_req_entries = NULL,
2280 .build_iocbs = NULL,
2281 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2282 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2283 .read_nvram = NULL,
2284 .write_nvram = NULL,
2285 .fw_dump = qla83xx_fw_dump,
2286 .beacon_on = qla24xx_beacon_on,
2287 .beacon_off = qla24xx_beacon_off,
2288 .beacon_blink = qla83xx_beacon_blink,
2289 .read_optrom = qla25xx_read_optrom_data,
2290 .write_optrom = qla24xx_write_optrom_data,
2291 .get_flash_version = qla24xx_get_flash_version,
2292 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2293 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2294 .abort_isp = qla2x00_abort_isp,
2295 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2296 .initialize_adapter = qla2x00_initialize_adapter,
2297};
2298
2299static struct isp_operations qlafx00_isp_ops = {
2300 .pci_config = qlafx00_pci_config,
2301 .reset_chip = qlafx00_soft_reset,
2302 .chip_diag = qlafx00_chip_diag,
2303 .config_rings = qlafx00_config_rings,
2304 .reset_adapter = qlafx00_soft_reset,
2305 .nvram_config = NULL,
2306 .update_fw_options = NULL,
2307 .load_risc = NULL,
2308 .pci_info_str = qlafx00_pci_info_str,
2309 .fw_version_str = qlafx00_fw_version_str,
2310 .intr_handler = qlafx00_intr_handler,
2311 .enable_intrs = qlafx00_enable_intrs,
2312 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2313 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2314 .target_reset = qlafx00_abort_target,
2315 .lun_reset = qlafx00_lun_reset,
2316 .fabric_login = NULL,
2317 .fabric_logout = NULL,
2318 .calc_req_entries = NULL,
2319 .build_iocbs = NULL,
2320 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2321 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2322 .read_nvram = qla24xx_read_nvram_data,
2323 .write_nvram = qla24xx_write_nvram_data,
2324 .fw_dump = NULL,
2325 .beacon_on = qla24xx_beacon_on,
2326 .beacon_off = qla24xx_beacon_off,
2327 .beacon_blink = NULL,
2328 .read_optrom = qla24xx_read_optrom_data,
2329 .write_optrom = qla24xx_write_optrom_data,
2330 .get_flash_version = qla24xx_get_flash_version,
2331 .start_scsi = qlafx00_start_scsi,
d7459527 2332 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2333 .abort_isp = qlafx00_abort_isp,
2334 .iospace_config = qlafx00_iospace_config,
2335 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2336};
2337
f73cb695
CD		 2338static struct isp_operations qla27xx_isp_ops = {
2339 .pci_config = qla25xx_pci_config,
2340 .reset_chip = qla24xx_reset_chip,
2341 .chip_diag = qla24xx_chip_diag,
2342 .config_rings = qla24xx_config_rings,
2343 .reset_adapter = qla24xx_reset_adapter,
2344 .nvram_config = qla81xx_nvram_config,
2345 .update_fw_options = qla81xx_update_fw_options,
2346 .load_risc = qla81xx_load_risc,
2347 .pci_info_str = qla24xx_pci_info_str,
2348 .fw_version_str = qla24xx_fw_version_str,
2349 .intr_handler = qla24xx_intr_handler,
2350 .enable_intrs = qla24xx_enable_intrs,
2351 .disable_intrs = qla24xx_disable_intrs,
2352 .abort_command = qla24xx_abort_command,
2353 .target_reset = qla24xx_abort_target,
2354 .lun_reset = qla24xx_lun_reset,
2355 .fabric_login = qla24xx_login_fabric,
2356 .fabric_logout = qla24xx_fabric_logout,
2357 .calc_req_entries = NULL,
2358 .build_iocbs = NULL,
2359 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2360 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2361 .read_nvram = NULL,
2362 .write_nvram = NULL,
2363 .fw_dump = qla27xx_fwdump,
2364 .beacon_on = qla24xx_beacon_on,
2365 .beacon_off = qla24xx_beacon_off,
2366 .beacon_blink = qla83xx_beacon_blink,
2367 .read_optrom = qla25xx_read_optrom_data,
2368 .write_optrom = qla24xx_write_optrom_data,
2369 .get_flash_version = qla24xx_get_flash_version,
2370 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2371 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2372 .abort_isp = qla2x00_abort_isp,
2373 .iospace_config = qla83xx_iospace_config,
2374 .initialize_adapter = qla2x00_initialize_adapter,
2375};
2376
ea5b6382 2377static inline void
e315cd28 2378qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2379{
2380 ha->device_type = DT_EXTENDED_IDS;
2381 switch (ha->pdev->device) {
2382 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2383 ha->isp_type |= DT_ISP2100;
ea5b6382 2384 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2385 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2386 break;
2387 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2388 ha->isp_type |= DT_ISP2200;
ea5b6382 2389 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2390 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2391 break;
2392 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2393 ha->isp_type |= DT_ISP2300;
4a59f71d 2394 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2395 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2396 break;
2397 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2398 ha->isp_type |= DT_ISP2312;
4a59f71d 2399 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2400 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2401 break;
2402 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2403 ha->isp_type |= DT_ISP2322;
4a59f71d 2404 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2405 if (ha->pdev->subsystem_vendor == 0x1028 &&
2406 ha->pdev->subsystem_device == 0x0170)
2407 ha->device_type |= DT_OEM_001;
441d1072 2408 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2409 break;
2410 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2411 ha->isp_type |= DT_ISP6312;
441d1072 2412 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2413 break;
2414 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2415 ha->isp_type |= DT_ISP6322;
441d1072 2416 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2417 break;
2418 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2419 ha->isp_type |= DT_ISP2422;
4a59f71d 2420 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2421 ha->device_type |= DT_FWI2;
c76f2c01 2422 ha->device_type |= DT_IIDMA;
441d1072 2423 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2424 break;
2425 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2426 ha->isp_type |= DT_ISP2432;
4a59f71d 2427 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2428 ha->device_type |= DT_FWI2;
c76f2c01 2429 ha->device_type |= DT_IIDMA;
441d1072 2430 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2431 break;
4d4df193 2432 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2433 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2434 ha->device_type |= DT_ZIO_SUPPORTED;
2435 ha->device_type |= DT_FWI2;
2436 ha->device_type |= DT_IIDMA;
2437 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2438 break;
044cc6c8 2439 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2440 ha->isp_type |= DT_ISP5422;
e428924c 2441 ha->device_type |= DT_FWI2;
441d1072 2442 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2443 break;
044cc6c8 2444 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2445 ha->isp_type |= DT_ISP5432;
e428924c 2446 ha->device_type |= DT_FWI2;
441d1072 2447 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2448 break;
c3a2f0df 2449 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2450 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2451 ha->device_type |= DT_ZIO_SUPPORTED;
2452 ha->device_type |= DT_FWI2;
2453 ha->device_type |= DT_IIDMA;
441d1072 2454 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2455 break;
3a03eb79 2456 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2457 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2458 ha->device_type |= DT_ZIO_SUPPORTED;
2459 ha->device_type |= DT_FWI2;
2460 ha->device_type |= DT_IIDMA;
2461 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2462 break;
a9083016 2463 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2464 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2465 ha->device_type |= DT_ZIO_SUPPORTED;
2466 ha->device_type |= DT_FWI2;
2467 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2468 /* Initialize 82XX ISP flags */
2469 qla82xx_init_flags(ha);
2470 break;
7ec0effd 2471 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2472 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2473 ha->device_type |= DT_ZIO_SUPPORTED;
2474 ha->device_type |= DT_FWI2;
2475 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2476 /* Initialize 82XX ISP flags */
2477 qla82xx_init_flags(ha);
2478 break;
6246b8a1 2479 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2480 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2481 ha->device_type |= DT_ZIO_SUPPORTED;
2482 ha->device_type |= DT_FWI2;
2483 ha->device_type |= DT_IIDMA;
2484 ha->device_type |= DT_T10_PI;
2485 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2486 break;
2487 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2488 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2489 ha->device_type |= DT_ZIO_SUPPORTED;
2490 ha->device_type |= DT_FWI2;
2491 ha->device_type |= DT_IIDMA;
2492 ha->device_type |= DT_T10_PI;
2493 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2494 break;
8ae6d9c7 2495 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2496 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2497 break;
f73cb695 2498 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2499 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2500 ha->device_type |= DT_ZIO_SUPPORTED;
2501 ha->device_type |= DT_FWI2;
2502 ha->device_type |= DT_IIDMA;
8ce3f570 2503 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2504 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2505 break;
2c5bbbb2 2506 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2507 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2508 ha->device_type |= DT_ZIO_SUPPORTED;
2509 ha->device_type |= DT_FWI2;
2510 ha->device_type |= DT_IIDMA;
8ce3f570 2511 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2512 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2513 break;
2b48992f 2514 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2515 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2516 ha->device_type |= DT_ZIO_SUPPORTED;
2517 ha->device_type |= DT_FWI2;
2518 ha->device_type |= DT_IIDMA;
8ce3f570 2519 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2520 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2521 break;
ea5b6382 2522 }
e5b68a61 2523
a9083016 2524 if (IS_QLA82XX(ha))
43a9c38b 2525 ha->port_no = ha->portnum & 1;
f73cb695 2526 else {
a9083016
GM		 2527 /* Get adapter physical port no from interrupt pin register. */
2528 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2529 if (IS_QLA27XX(ha))
2530 ha->port_no--;
2531 else
2532 ha->port_no = !(ha->port_no & 1);
2533 }
a9083016 2534
7c3df132 2535 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2536 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2537 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2538}
2539
1e99e33a
AV		 2540static void
2541qla2xxx_scan_start(struct Scsi_Host *shost)
2542{
e315cd28 2543 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2544
cbc8eb67
AV		 2545 if (vha->hw->flags.running_gold_fw)
2546 return;
2547
e315cd28
AC		 2548 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2549 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2550 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2551 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2552}
2553
2554static int
2555qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2556{
e315cd28 2557 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2558
a5dd506e
BK		 2559 if (test_bit(UNLOADING, &vha->dpc_flags))
2560 return 1;
e315cd28 2561 if (!vha->host)
1e99e33a 2562 return 1;
e315cd28 2563 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2564 return 1;
2565
e315cd28 2566 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2567}
2568
ec7193e2
QT		 2569static void qla2x00_iocb_work_fn(struct work_struct *work)
2570{
2571 struct scsi_qla_host *vha = container_of(work,
2572 struct scsi_qla_host, iocb_work);
2573 int cnt = 0;
2574
2575 while (!list_empty(&vha->work_list)) {
2576 qla2x00_do_work(vha);
2577 cnt++;
2578 if (cnt > 10)
2579 break;
2580 }
2581}
2582
1da177e4
LT		 2583/*
2584 * PCI driver interface
2585 */
6f039790 2586static int
7ee61397 2587qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2588{
a1541d5a 2589 int ret = -ENODEV;
1da177e4 2590 struct Scsi_Host *host;
e315cd28
AC		 2591 scsi_qla_host_t *base_vha = NULL;
2592 struct qla_hw_data *ha;
29856e28 2593 char pci_info[30];
7d613ac6 2594 char fw_str[30], wq_name[30];
5433383e 2595 struct scsi_host_template *sht;
642ef983 2596 int bars, mem_only = 0;
e315cd28 2597 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2598 struct req_que *req = NULL;
2599 struct rsp_que *rsp = NULL;
5601236b 2600 int i;
d7459527 2601
285d0321 2602 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2603 sht = &qla2xxx_driver_template;
5433383e 2604 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2605 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2606 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2607 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2608 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2609 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2610 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2611 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2612 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2613 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2614 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2615 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2616 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2617 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2618 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2619 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2620 mem_only = 1;
7c3df132
SK		 2621 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2622 "Mem only adapter.\n");
285d0321 2623 }
7c3df132
SK		 2624 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2625 "Bars=%d.\n", bars);
285d0321 2626
09483916
BH		 2627 if (mem_only) {
2628 if (pci_enable_device_mem(pdev))
2629 goto probe_out;
2630 } else {
2631 if (pci_enable_device(pdev))
2632 goto probe_out;
2633 }
285d0321 2634
0927678f
JB		 2635 /* This may fail but that's ok */
2636 pci_enable_pcie_error_reporting(pdev);
285d0321 2637
e315cd28
AC		 2638 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2639 if (!ha) {
7c3df132
SK		 2640 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2641 "Unable to allocate memory for ha.\n");
e315cd28 2642 goto probe_out;
1da177e4 2643 }
7c3df132
SK		 2644 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2645 "Memory allocated for ha=%p.\n", ha);
e315cd28 2646 ha->pdev = pdev;
2d70c103 2647 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2648 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2649 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2650 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2651 spin_lock_init(&ha->tgt.atio_lock);
2652
1da177e4
LT		 2653
2654 /* Clear our data area */
285d0321 2655 ha->bars = bars;
09483916 2656 ha->mem_only = mem_only;
df4bf0bb 2657 spin_lock_init(&ha->hardware_lock);
339aa70e 2658 spin_lock_init(&ha->vport_slock);
a9b6f722 2659 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2660 mutex_init(&ha->optrom_mutex);
1da177e4 2661
ea5b6382
AV		 2662 /* Set ISP-type information. */
2663 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2664
2665 /* Set EEH reset type to fundamental if required by hba */
95676112 2666 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2667 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2668 pdev->needs_freset = 1;
ca79cf66 2669
cba1e47f
CD		 2670 ha->prev_topology = 0;
2671 ha->init_cb_size = sizeof(init_cb_t);
2672 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2673 ha->optrom_size = OPTROM_SIZE_2300;
2674
abbd8870 2675 /* Assign ISP specific operations. */
1da177e4 2676 if (IS_QLA2100(ha)) {
642ef983 2677 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2678 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2679 req_length = REQUEST_ENTRY_CNT_2100;
2680 rsp_length = RESPONSE_ENTRY_CNT_2100;
2681 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2682 ha->gid_list_info_size = 4;
3a03eb79
AV		 2683 ha->flash_conf_off = ~0;
2684 ha->flash_data_off = ~0;
2685 ha->nvram_conf_off = ~0;
2686 ha->nvram_data_off = ~0;
fd34f556 2687 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2688 } else if (IS_QLA2200(ha)) {
642ef983 2689 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2690 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2691 req_length = REQUEST_ENTRY_CNT_2200;
2692 rsp_length = RESPONSE_ENTRY_CNT_2100;
2693 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2694 ha->gid_list_info_size = 4;
3a03eb79
AV		 2695 ha->flash_conf_off = ~0;
2696 ha->flash_data_off = ~0;
2697 ha->nvram_conf_off = ~0;
2698 ha->nvram_data_off = ~0;
fd34f556 2699 ha->isp_ops = &qla2100_isp_ops;
fca29703 2700 } else if (IS_QLA23XX(ha)) {
642ef983 2701 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2702 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2703 req_length = REQUEST_ENTRY_CNT_2200;
2704 rsp_length = RESPONSE_ENTRY_CNT_2300;
2705 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2706 ha->gid_list_info_size = 6;
854165f4
AV		 2707 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2708 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2709 ha->flash_conf_off = ~0;
2710 ha->flash_data_off = ~0;
2711 ha->nvram_conf_off = ~0;
2712 ha->nvram_data_off = ~0;
fd34f556 2713 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2714 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2715 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2716 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2717 req_length = REQUEST_ENTRY_CNT_24XX;
2718 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2719 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2720 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2721 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2722 ha->gid_list_info_size = 8;
854165f4 2723 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2724 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2725 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2726 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2727 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2728 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2729 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2730 } else if (IS_QLA25XX(ha)) {
642ef983 2731 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2732 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2733 req_length = REQUEST_ENTRY_CNT_24XX;
2734 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2735 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2736 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2737 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2738 ha->gid_list_info_size = 8;
2739 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2740 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2741 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2742 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2743 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2744 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2745 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2746 } else if (IS_QLA81XX(ha)) {
642ef983 2747 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2748 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2749 req_length = REQUEST_ENTRY_CNT_24XX;
2750 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2751 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2752 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2753 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2754 ha->gid_list_info_size = 8;
2755 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2756 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2757 ha->isp_ops = &qla81xx_isp_ops;
2758 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2759 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2760 ha->nvram_conf_off = ~0;
2761 ha->nvram_data_off = ~0;
a9083016 2762 } else if (IS_QLA82XX(ha)) {
642ef983 2763 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2764 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2765 req_length = REQUEST_ENTRY_CNT_82XX;
2766 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2767 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2768 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2769 ha->gid_list_info_size = 8;
2770 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2771 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2772 ha->isp_ops = &qla82xx_isp_ops;
2773 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2774 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2775 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2776 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2777 } else if (IS_QLA8044(ha)) {
2778 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2779 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2780 req_length = REQUEST_ENTRY_CNT_82XX;
2781 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2782 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2783 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2784 ha->gid_list_info_size = 8;
2785 ha->optrom_size = OPTROM_SIZE_83XX;
2786 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2787 ha->isp_ops = &qla8044_isp_ops;
2788 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2789 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2790 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2791 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2792 } else if (IS_QLA83XX(ha)) {
7d613ac6 2793 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2794 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2795 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2796 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2797 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2798 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2799 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2800 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2801 ha->gid_list_info_size = 8;
2802 ha->optrom_size = OPTROM_SIZE_83XX;
2803 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2804 ha->isp_ops = &qla83xx_isp_ops;
2805 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2806 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2807 ha->nvram_conf_off = ~0;
2808 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2809 } else if (IS_QLAFX00(ha)) {
2810 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2811 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2812 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2813 req_length = REQUEST_ENTRY_CNT_FX00;
2814 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2815 ha->isp_ops = &qlafx00_isp_ops;
2816 ha->port_down_retry_count = 30; /* default value */
2817 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2818 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2819 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2820 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2821 ha->mr.host_info_resend = false;
2822 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2823 } else if (IS_QLA27XX(ha)) {
2824 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2825 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2826 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2827 req_length = REQUEST_ENTRY_CNT_83XX;
2828 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2829 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2830 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2831 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2832 ha->gid_list_info_size = 8;
2833 ha->optrom_size = OPTROM_SIZE_83XX;
2834 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2835 ha->isp_ops = &qla27xx_isp_ops;
2836 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2837 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2838 ha->nvram_conf_off = ~0;
2839 ha->nvram_data_off = ~0;
1da177e4 2840 }
6246b8a1 2841
7c3df132
SK		 2842 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2843 "mbx_count=%d, req_length=%d, "
2844 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2845 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2846 "max_fibre_devices=%d.\n",
7c3df132
SK		 2847 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2848 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2849 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2850 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2851 "isp_ops=%p, flash_conf_off=%d, "
2852 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2853 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2854 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2855
2856 /* Configure PCI I/O space */
2857 ret = ha->isp_ops->iospace_config(ha);
2858 if (ret)
0a63ad12 2859 goto iospace_config_failed;
706f457d
GM		 2860
2861 ql_log_pci(ql_log_info, pdev, 0x001d,
2862 "Found an ISP%04X irq %d iobase 0x%p.\n",
2863 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2864 mutex_init(&ha->vport_lock);
d7459527 2865 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2866 init_completion(&ha->mbx_cmd_comp);
2867 complete(&ha->mbx_cmd_comp);
2868 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2869 init_completion(&ha->dcbx_comp);
f356bef1 2870 init_completion(&ha->lb_portup_comp);
1da177e4 2871
2c3dfe3f 2872 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2873
53303c42 2874 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2875 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2876 "64 Bit addressing is %s.\n",
2877 ha->flags.enable_64bit_addressing ? "enable" :
2878 "disable");
73208dfd 2879 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2880 if (ret) {
7c3df132
SK		 2881 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2882 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2883
e315cd28
AC		 2884 goto probe_hw_failed;
2885 }
2886
73208dfd 2887 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2888 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2889 req->max_q_depth = ql2xmaxqdepth;
2890
e315cd28
AC		 2891
2892 base_vha = qla2x00_create_host(sht, ha);
2893 if (!base_vha) {
a1541d5a 2894 ret = -ENOMEM;
6e9f21f3 2895 qla2x00_mem_free(ha);
2afa19a9
AC		 2896 qla2x00_free_req_que(ha, req);
2897 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2898 goto probe_hw_failed;
1da177e4
LT		 2899 }
2900
e315cd28 2901 pci_set_drvdata(pdev, base_vha);
6b383979 2902 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2903
e315cd28 2904 host = base_vha->host;
2afa19a9 2905 base_vha->req = req;
73208dfd 2906 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2907 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2908 else
e315cd28
AC		 2909 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2910 base_vha->vp_idx;
58548cb5 2911
8ae6d9c7
GM		 2912 /* Setup fcport template structure. */
2913 ha->mr.fcport.vha = base_vha;
2914 ha->mr.fcport.port_type = FCT_UNKNOWN;
2915 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2916 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2917 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2918 ha->mr.fcport.scan_state = 1;
2919
58548cb5
GM		 2920 /* Set the SG table size based on ISP type */
2921 if (!IS_FWI2_CAPABLE(ha)) {
2922 if (IS_QLA2100(ha))
2923 host->sg_tablesize = 32;
2924 } else {
2925 if (!IS_QLA82XX(ha))
2926 host->sg_tablesize = QLA_SG_ALL;
2927 }
642ef983 2928 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2929 host->cmd_per_lun = 3;
2930 host->unique_id = host->host_no;
e02587d7 2931 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2932 host->max_cmd_len = 32;
2933 else
2934 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2935 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2936 /* Older HBAs support only 16-bit LUNs */
2937 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2938 ql2xmaxlun > 0xffff)
2939 host->max_lun = 0xffff;
2940 else
2941 host->max_lun = ql2xmaxlun;
e315cd28 2942 host->transportt = qla2xxx_transport_template;
9a069e19 2943 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2944
7c3df132
SK		 2945 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2946 "max_id=%d this_id=%d "
2947 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2948 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2949 host->this_id, host->cmd_per_lun, host->unique_id,
2950 host->max_cmd_len, host->max_channel, host->max_lun,
2951 host->transportt, sht->vendor_id);
2952
d7459527
MH		 2953 /* Set up the irqs */
2954 ret = qla2x00_request_irqs(ha, rsp);
2955 if (ret)
2956 goto probe_init_failed;
2957
9a347ff4
CD		 2958 /* Alloc arrays of request and response ring ptrs */
2959 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2960 ql_log(ql_log_fatal, base_vha, 0x003d,
2961 "Failed to allocate memory for queue pointers..."
2962 "aborting.\n");
2963 goto probe_init_failed;
2964 }
2965
5601236b
MH		 2966 if (ha->mqenable && shost_use_blk_mq(host)) {
2967 /* number of hardware queues supported by blk/scsi-mq*/
2968 host->nr_hw_queues = ha->max_qpairs;
2969
2970 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2971 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2972 } else
2973 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2974 "blk/scsi-mq disabled.\n");
2975
2d70c103 2976 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2977
90a86fc0
JC		 2978 pci_save_state(pdev);
2979
9a347ff4 2980 /* Assign back pointers */
2afa19a9
AC		 2981 rsp->req = req;
2982 req->rsp = rsp;
9a347ff4 2983
8ae6d9c7
GM		 2984 if (IS_QLAFX00(ha)) {
2985 ha->rsp_q_map[0] = rsp;
2986 ha->req_q_map[0] = req;
2987 set_bit(0, ha->req_qid_map);
2988 set_bit(0, ha->rsp_qid_map);
2989 }
2990
08029990
AV		 2991 /* FWI2-capable only. */
2992 req->req_q_in = &ha->iobase->isp24.req_q_in;
2993 req->req_q_out = &ha->iobase->isp24.req_q_out;
2994 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2995 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2996 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2997 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2998 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2999 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3000 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3001 }
3002
8ae6d9c7
GM		 3003 if (IS_QLAFX00(ha)) {
3004 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3005 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3006 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3007 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3008 }
3009
7ec0effd 3010 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3011 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3012 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3013 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3014 }
3015
7c3df132
SK		 3016 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3017 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3018 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3019 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3020 "req->req_q_in=%p req->req_q_out=%p "
3021 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3022 req->req_q_in, req->req_q_out,
3023 rsp->rsp_q_in, rsp->rsp_q_out);
3024 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3025 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3026 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3027 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3028 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3029 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3030
8ae6d9c7 3031 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3032 ql_log(ql_log_fatal, base_vha, 0x00d6,
3033 "Failed to initialize adapter - Adapter flags %x.\n",
3034 base_vha->device_flags);
1da177e4 3035
a9083016
GM		 3036 if (IS_QLA82XX(ha)) {
3037 qla82xx_idc_lock(ha);
3038 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3039 QLA8XXX_DEV_FAILED);
a9083016 3040 qla82xx_idc_unlock(ha);
7c3df132
SK		 3041 ql_log(ql_log_fatal, base_vha, 0x00d7,
3042 "HW State: FAILED.\n");
7ec0effd
AD		 3043 } else if (IS_QLA8044(ha)) {
3044 qla8044_idc_lock(ha);
3045 qla8044_wr_direct(base_vha,
3046 QLA8044_CRB_DEV_STATE_INDEX,
3047 QLA8XXX_DEV_FAILED);
3048 qla8044_idc_unlock(ha);
3049 ql_log(ql_log_fatal, base_vha, 0x0150,
3050 "HW State: FAILED.\n");
a9083016
GM		 3051 }
3052
a1541d5a 3053 ret = -ENODEV;
1da177e4
LT		 3054 goto probe_failed;
3055 }
3056
3b1bef64
CD		 3057 if (IS_QLAFX00(ha))
3058 host->can_queue = QLAFX00_MAX_CANQUEUE;
3059 else
3060 host->can_queue = req->num_outstanding_cmds - 10;
3061
3062 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3063 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3064 host->can_queue, base_vha->req,
3065 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3066
093df737 3067 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3068 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3069 /* Create start of day qpairs for Block MQ */
3070 if (shost_use_blk_mq(host)) {
3071 for (i = 0; i < ha->max_qpairs; i++)
3072 qla2xxx_create_qpair(base_vha, 5, 0);
3073 }
3074 }
68ca949c 3075
cbc8eb67
AV		 3076 if (ha->flags.running_gold_fw)
3077 goto skip_dpc;
3078
1da177e4
LT		 3079 /*
3080 * Startup the kernel thread for this host adapter
3081 */
39a11240 3082 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3083 "%s_dpc", base_vha->host_str);
39a11240 3084 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3085 ql_log(ql_log_fatal, base_vha, 0x00ed,
3086 "Failed to start DPC thread.\n");
39a11240 3087 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3088 goto probe_failed;
3089 }
7c3df132
SK		 3090 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3091 "DPC thread started successfully.\n");
1da177e4 3092
2d70c103
NB		 3093 /*
3094 * If we're not coming up in initiator mode, we might sit for
3095 * a while without waking up the dpc thread, which leads to a
3096 * stuck process warning. So just kick the dpc once here and
3097 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3098 */
3099 qla2xxx_wake_dpc(base_vha);
3100
ec7193e2 3101 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3102 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3103
81178772
SK		 3104 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3105 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3106 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3107 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3108
3109 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3110 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3111 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3112 INIT_WORK(&ha->idc_state_handler,
3113 qla83xx_idc_state_handler_work);
3114 INIT_WORK(&ha->nic_core_unrecoverable,
3115 qla83xx_nic_core_unrecoverable_work);
3116 }
3117
cbc8eb67 3118skip_dpc:
e315cd28
AC		 3119 list_add_tail(&base_vha->list, &ha->vp_list);
3120 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3121
3122 /* Initialized the timer */
e315cd28 3123 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3124 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3125 "Started qla2x00_timer with "
3126 "interval=%d.\n", WATCH_INTERVAL);
3127 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3128 "Detected hba at address=%p.\n",
3129 ha);
d19044c3 3130
e02587d7 3131 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3132 if (ha->fw_attributes & BIT_4) {
9e522cd8 3133 int prot = 0, guard;
bad75002 3134 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3135 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3136 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3137 if (ql2xenabledif == 1)
3138 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3139 scsi_host_set_prot(host,
8cb2049c 3140 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3141 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3142 | SHOST_DIF_TYPE3_PROTECTION
3143 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3144 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3145 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3146
3147 guard = SHOST_DIX_GUARD_CRC;
3148
3149 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3150 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3151 guard |= SHOST_DIX_GUARD_IP;
3152
3153 scsi_host_set_guard(host, guard);
bad75002
AE		 3154 } else
3155 base_vha->flags.difdix_supported = 0;
3156 }
3157
a9083016
GM		 3158 ha->isp_ops->enable_intrs(ha);
3159
1fe19ee4
AB		 3160 if (IS_QLAFX00(ha)) {
3161 ret = qlafx00_fx_disc(base_vha,
3162 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3163 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3164 QLA_SG_ALL : 128;
3165 }
3166
a1541d5a
AV		 3167 ret = scsi_add_host(host, &pdev->dev);
3168 if (ret)
3169 goto probe_failed;
3170
1486400f
MR		 3171 base_vha->flags.init_done = 1;
3172 base_vha->flags.online = 1;
edaa5c74 3173 ha->prev_minidump_failed = 0;
1486400f 3174
7c3df132
SK		 3175 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3176 "Init done and hba is online.\n");
3177
726b8548
QT		 3178 if (qla_ini_mode_enabled(base_vha) ||
3179 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3180 scsi_scan_host(host);
3181 else
3182 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3183 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3184
e315cd28 3185 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3186
8ae6d9c7 3187 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3188 ret = qlafx00_fx_disc(base_vha,
3189 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3190
3191 /* Register system information */
3192 ret = qlafx00_fx_disc(base_vha,
3193 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3194 }
3195
e315cd28 3196 qla2x00_init_host_attr(base_vha);
a1541d5a 3197
e315cd28 3198 qla2x00_dfs_setup(base_vha);
df613b96 3199
03eb912a
AB		 3200 ql_log(ql_log_info, base_vha, 0x00fb,
3201 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3202 ql_log(ql_log_info, base_vha, 0x00fc,
3203 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3204 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3205 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3206 base_vha->host_no,
df57caba 3207 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3208
2d70c103
NB		 3209 qlt_add_target(ha, base_vha);
3210
6b383979 3211 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3212
3213 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3214 return -ENODEV;
3215
1da177e4
LT		 3216 return 0;
3217
6e9f21f3 3218probe_init_failed:
2afa19a9 3219 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3220 ha->req_q_map[0] = NULL;
3221 clear_bit(0, ha->req_qid_map);
2afa19a9 3222 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3223 ha->rsp_q_map[0] = NULL;
3224 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3225 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3226
1da177e4 3227probe_failed:
b9978769
AV		 3228 if (base_vha->timer_active)
3229 qla2x00_stop_timer(base_vha);
3230 base_vha->flags.online = 0;
3231 if (ha->dpc_thread) {
3232 struct task_struct *t = ha->dpc_thread;
3233
3234 ha->dpc_thread = NULL;
3235 kthread_stop(t);
3236 }
3237
e315cd28 3238 qla2x00_free_device(base_vha);
1da177e4 3239
e315cd28 3240 scsi_host_put(base_vha->host);
1da177e4 3241
e315cd28 3242probe_hw_failed:
1a2fbf18
JL		 3243 qla2x00_clear_drv_active(ha);
3244
0a63ad12 3245iospace_config_failed:
7ec0effd 3246 if (IS_P3P_TYPE(ha)) {
0a63ad12 3247 if (!ha->nx_pcibase)
f73cb695 3248 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3249 if (!ql2xdbwr)
f73cb695 3250 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3251 } else {
3252 if (ha->iobase)
3253 iounmap(ha->iobase);
8ae6d9c7
GM		 3254 if (ha->cregbase)
3255 iounmap(ha->cregbase);
a9083016 3256 }
e315cd28
AC		 3257 pci_release_selected_regions(ha->pdev, ha->bars);
3258 kfree(ha);
3259 ha = NULL;
1da177e4 3260
a1541d5a 3261probe_out:
e315cd28 3262 pci_disable_device(pdev);
a1541d5a 3263 return ret;
1da177e4 3264}
1da177e4 3265
e30d1756
MI		 3266static void
3267qla2x00_shutdown(struct pci_dev *pdev)
3268{
3269 scsi_qla_host_t *vha;
3270 struct qla_hw_data *ha;
3271
552f3f9a
MI		 3272 if (!atomic_read(&pdev->enable_cnt))
3273 return;
3274
e30d1756
MI		 3275 vha = pci_get_drvdata(pdev);
3276 ha = vha->hw;
3277
42479343
AB		 3278 /* Notify ISPFX00 firmware */
3279 if (IS_QLAFX00(ha))
3280 qlafx00_driver_shutdown(vha, 20);
3281
e30d1756
MI		 3282 /* Turn-off FCE trace */
3283 if (ha->flags.fce_enabled) {
3284 qla2x00_disable_fce_trace(vha, NULL, NULL);
3285 ha->flags.fce_enabled = 0;
3286 }
3287
3288 /* Turn-off EFT trace */
3289 if (ha->eft)
3290 qla2x00_disable_eft_trace(vha);
3291
3292 /* Stop currently executing firmware. */
3293 qla2x00_try_to_stop_firmware(vha);
3294
3295 /* Turn adapter off line */
3296 vha->flags.online = 0;
3297
3298 /* turn-off interrupts on the card */
3299 if (ha->interrupts_on) {
3300 vha->flags.init_done = 0;
3301 ha->isp_ops->disable_intrs(ha);
3302 }
3303
3304 qla2x00_free_irqs(vha);
3305
3306 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3307
3308 pci_disable_pcie_error_reporting(pdev);
3309 pci_disable_device(pdev);
e30d1756
MI		 3310}
3311
fe1b806f 3312/* Deletes all the virtual ports for a given ha */
4c993f76 3313static void
fe1b806f 3314qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3315{
fe1b806f 3316 scsi_qla_host_t *vha;
feafb7b1 3317 unsigned long flags;
e315cd28 3318
43ebf16d
AE		 3319 mutex_lock(&ha->vport_lock);
3320 while (ha->cur_vport_count) {
43ebf16d 3321 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3322
43ebf16d
AE		 3323 BUG_ON(base_vha->list.next == &ha->vp_list);
3324 /* This assumes first entry in ha->vp_list is always base vha */
3325 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3326 scsi_host_get(vha->host);
feafb7b1 3327
43ebf16d
AE		 3328 spin_unlock_irqrestore(&ha->vport_slock, flags);
3329 mutex_unlock(&ha->vport_lock);
3330
3331 fc_vport_terminate(vha->fc_vport);
3332 scsi_host_put(vha->host);
feafb7b1 3333
43ebf16d 3334 mutex_lock(&ha->vport_lock);
e315cd28 3335 }
43ebf16d 3336 mutex_unlock(&ha->vport_lock);
fe1b806f 3337}
1da177e4 3338
fe1b806f
CD		 3339/* Stops all deferred work threads */
3340static void
3341qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3342{
7d613ac6
SV		 3343 /* Cancel all work and destroy DPC workqueues */
3344 if (ha->dpc_lp_wq) {
3345 cancel_work_sync(&ha->idc_aen);
3346 destroy_workqueue(ha->dpc_lp_wq);
3347 ha->dpc_lp_wq = NULL;
3348 }
3349
3350 if (ha->dpc_hp_wq) {
3351 cancel_work_sync(&ha->nic_core_reset);
3352 cancel_work_sync(&ha->idc_state_handler);
3353 cancel_work_sync(&ha->nic_core_unrecoverable);
3354 destroy_workqueue(ha->dpc_hp_wq);
3355 ha->dpc_hp_wq = NULL;
3356 }
3357
b9978769
AV		 3358 /* Kill the kernel thread for this host */
3359 if (ha->dpc_thread) {
3360 struct task_struct *t = ha->dpc_thread;
3361
3362 /*
3363 * qla2xxx_wake_dpc checks for ->dpc_thread
3364 * so we need to zero it out.
3365 */
3366 ha->dpc_thread = NULL;
3367 kthread_stop(t);
3368 }
fe1b806f 3369}
1da177e4 3370
fe1b806f
CD		 3371static void
3372qla2x00_unmap_iobases(struct qla_hw_data *ha)
3373{
a9083016 3374 if (IS_QLA82XX(ha)) {
b963752f 3375
f73cb695 3376 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3377 if (!ql2xdbwr)
f73cb695 3378 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3379 } else {
3380 if (ha->iobase)
3381 iounmap(ha->iobase);
1da177e4 3382
8ae6d9c7
GM		 3383 if (ha->cregbase)
3384 iounmap(ha->cregbase);
3385
a9083016
GM		 3386 if (ha->mqiobase)
3387 iounmap(ha->mqiobase);
6246b8a1 3388
f73cb695 3389 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3390 iounmap(ha->msixbase);
a9083016 3391 }
fe1b806f
CD		 3392}
3393
3394static void
db7157d4 3395qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3396{
fe1b806f
CD		 3397 if (IS_QLA8044(ha)) {
3398 qla8044_idc_lock(ha);
c41afc9a 3399 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3400 qla8044_idc_unlock(ha);
3401 } else if (IS_QLA82XX(ha)) {
3402 qla82xx_idc_lock(ha);
3403 qla82xx_clear_drv_active(ha);
3404 qla82xx_idc_unlock(ha);
3405 }
3406}
3407
3408static void
3409qla2x00_remove_one(struct pci_dev *pdev)
3410{
3411 scsi_qla_host_t *base_vha;
3412 struct qla_hw_data *ha;
3413
beb9e315
JL		 3414 base_vha = pci_get_drvdata(pdev);
3415 ha = base_vha->hw;
3416
3417 /* Indicate device removal to prevent future board_disable and wait
3418 * until any pending board_disable has completed. */
3419 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3420 cancel_work_sync(&ha->board_disable);
3421
fe1b806f 3422 /*
beb9e315
JL		 3423 * If the PCI device is disabled then there was a PCI-disconnect and
3424 * qla2x00_disable_board_on_pci_error has taken care of most of the
3425 * resources.
fe1b806f 3426 */
beb9e315 3427 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3428 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3429 base_vha->gnl.l, base_vha->gnl.ldma);
3430
beb9e315
JL		 3431 scsi_host_put(base_vha->host);
3432 kfree(ha);
3433 pci_set_drvdata(pdev, NULL);
fe1b806f 3434 return;
beb9e315 3435 }
638a1a01
SC		 3436 qla2x00_wait_for_hba_ready(base_vha);
3437
726b8548
QT		 3438 /*
3439 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3440 * where it was set first.
3441 */
3442 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3443 return;
3444
fe1b806f 3445 set_bit(UNLOADING, &base_vha->dpc_flags);
726b8548
QT		 3446 dma_free_coherent(&ha->pdev->dev,
3447 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3448
3449 if (IS_QLAFX00(ha))
3450 qlafx00_driver_shutdown(base_vha, 20);
3451
3452 qla2x00_delete_all_vps(ha, base_vha);
3453
3454 if (IS_QLA8031(ha)) {
3455 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3456 "Clearing fcoe driver presence.\n");
3457 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3458 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3459 "Error while clearing DRV-Presence.\n");
3460 }
3461
3462 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3463
3464 qla2x00_dfs_remove(base_vha);
3465
3466 qla84xx_put_chip(base_vha);
3467
2d5a4c34
HM		 3468 /* Laser should be disabled only for ISP2031 */
3469 if (IS_QLA2031(ha))
3470 qla83xx_disable_laser(base_vha);
3471
fe1b806f
CD		 3472 /* Disable timer */
3473 if (base_vha->timer_active)
3474 qla2x00_stop_timer(base_vha);
3475
3476 base_vha->flags.online = 0;
3477
b0d6cabd
HM		 3478 /* free DMA memory */
3479 if (ha->exlogin_buf)
3480 qla2x00_free_exlogin_buffer(ha);
3481
2f56a7f1
HM		 3482 /* free DMA memory */
3483 if (ha->exchoffld_buf)
3484 qla2x00_free_exchoffld_buffer(ha);
3485
fe1b806f
CD		 3486 qla2x00_destroy_deferred_work(ha);
3487
3488 qlt_remove_target(ha, base_vha);
3489
3490 qla2x00_free_sysfs_attr(base_vha, true);
3491
3492 fc_remove_host(base_vha->host);
482c9dc7 3493 qlt_remove_target_resources(ha);
fe1b806f
CD		 3494
3495 scsi_remove_host(base_vha->host);
3496
3497 qla2x00_free_device(base_vha);
3498
db7157d4 3499 qla2x00_clear_drv_active(ha);
fe1b806f 3500
d2749ffa
AE		 3501 scsi_host_put(base_vha->host);
3502
fe1b806f 3503 qla2x00_unmap_iobases(ha);
73208dfd 3504
e315cd28
AC		 3505 pci_release_selected_regions(ha->pdev, ha->bars);
3506 kfree(ha);
3507 ha = NULL;
1da177e4 3508
90a86fc0
JC		 3509 pci_disable_pcie_error_reporting(pdev);
3510
665db93b 3511 pci_disable_device(pdev);
1da177e4 3512}
1da177e4
LT		 3513
3514static void
e315cd28 3515qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3516{
e315cd28 3517 struct qla_hw_data *ha = vha->hw;
1da177e4 3518
85880801
AV		 3519 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3520
3521 /* Disable timer */
3522 if (vha->timer_active)
3523 qla2x00_stop_timer(vha);
3524
2afa19a9 3525 qla25xx_delete_queues(vha);
fe1b806f 3526
df613b96 3527 if (ha->flags.fce_enabled)
e315cd28 3528 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3529
a7a167bf 3530 if (ha->eft)
e315cd28 3531 qla2x00_disable_eft_trace(vha);
a7a167bf 3532
f6ef3b18 3533 /* Stop currently executing firmware. */
e315cd28 3534 qla2x00_try_to_stop_firmware(vha);
1da177e4 3535
85880801
AV		 3536 vha->flags.online = 0;
3537
f6ef3b18 3538 /* turn-off interrupts on the card */
a9083016
GM		 3539 if (ha->interrupts_on) {
3540 vha->flags.init_done = 0;
fd34f556 3541 ha->isp_ops->disable_intrs(ha);
a9083016 3542 }
f6ef3b18 3543
093df737
QT		 3544 qla2x00_free_fcports(vha);
3545
e315cd28 3546 qla2x00_free_irqs(vha);
1da177e4 3547
093df737
QT		 3548 /* Flush the work queue and remove it */
3549 if (ha->wq) {
3550 flush_workqueue(ha->wq);
3551 destroy_workqueue(ha->wq);
3552 ha->wq = NULL;
3553 }
3554
8867048b 3555
e315cd28 3556 qla2x00_mem_free(ha);
73208dfd 3557
08de2844
GM		 3558 qla82xx_md_free(vha);
3559
73208dfd 3560 qla2x00_free_queues(ha);
1da177e4
LT		 3561}
3562
8867048b
CD		 3563void qla2x00_free_fcports(struct scsi_qla_host *vha)
3564{
3565 fc_port_t *fcport, *tfcport;
3566
3567 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3568 list_del(&fcport->list);
5f16b331 3569 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3570 kfree(fcport);
3571 fcport = NULL;
3572 }
3573}
3574
d97994dc 3575static inline void
e315cd28 3576qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3577 int defer)
3578{
d97994dc 3579 struct fc_rport *rport;
67becc00 3580 scsi_qla_host_t *base_vha;
044d78e1 3581 unsigned long flags;
d97994dc
AV		 3582
3583 if (!fcport->rport)
3584 return;
3585
3586 rport = fcport->rport;
3587 if (defer) {
67becc00 3588 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3589 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3590 fcport->drport = rport;
044d78e1 3591 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3592 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3593 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3594 qla2xxx_wake_dpc(base_vha);
2d70c103 3595 } else {
df673274 3596 int now;
726b8548
QT		 3597 if (rport) {
3598 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3599 "%s %8phN. rport %p roles %x \n",
3600 __func__, fcport->port_name, rport,
3601 rport->roles);
d20ed91b 3602 fc_remote_port_delete(rport);
726b8548 3603 }
df673274 3604 qlt_do_generation_tick(vha, &now);
2d70c103 3605 }
d97994dc
AV		 3606}
3607
1da177e4
LT		 3608/*
3609 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3610 *
3611 * Input: ha = adapter block pointer. fcport = port structure pointer.
3612 *
3613 * Return: None.
3614 *
3615 * Context:
3616 */
e315cd28 3617void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3618 int do_login, int defer)
1da177e4 3619{
8ae6d9c7
GM		 3620 if (IS_QLAFX00(vha->hw)) {
3621 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3622 qla2x00_schedule_rport_del(vha, fcport, defer);
3623 return;
3624 }
3625
2c3dfe3f 3626 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3627 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3628 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3629 qla2x00_schedule_rport_del(vha, fcport, defer);
3630 }
fa2a1ce5 3631 /*
1da177e4
LT		 3632 * We may need to retry the login, so don't change the state of the
3633 * port but do the retries.
3634 */
3635 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3636 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3637
3638 if (!do_login)
3639 return;
3640
a1d0285e
AE		 3641 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3642
1da177e4 3643 if (fcport->login_retry == 0) {
e315cd28 3644 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3645
7c3df132 3646 ql_dbg(ql_dbg_disc, vha, 0x2067,
726b8548 3647 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3648 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3649 }
3650}
3651
3652/*
3653 * qla2x00_mark_all_devices_lost
3654 * Updates fcport state when device goes offline.
3655 *
3656 * Input:
3657 * ha = adapter block pointer.
3658 * fcport = port structure pointer.
3659 *
3660 * Return:
3661 * None.
3662 *
3663 * Context:
3664 */
3665void
e315cd28 3666qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3667{
3668 fc_port_t *fcport;
3669
726b8548
QT		 3670 ql_dbg(ql_dbg_disc, vha, 0xffff,
3671 "Mark all dev lost\n");
3672
e315cd28 3673 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3674 fcport->scan_state = 0;
3675 qlt_schedule_sess_for_deletion_lock(fcport);
3676
c6d39e23 3677 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3678 continue;
0d6e61bc 3679
1da177e4
LT		 3680 /*
3681 * No point in marking the device as lost, if the device is
3682 * already DEAD.
3683 */
3684 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3685 continue;
e315cd28 3686 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3687 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3688 if (defer)
3689 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3690 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3691 qla2x00_schedule_rport_del(vha, fcport, defer);
3692 }
1da177e4
LT		 3693 }
3694}
3695
3696/*
3697* qla2x00_mem_alloc
3698* Allocates adapter memory.
3699*
3700* Returns:
3701* 0 = success.
e8711085 3702* !0 = failure.
1da177e4 3703*/
e8711085 3704static int
73208dfd
AC		 3705qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3706 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3707{
3708 char name[16];
1da177e4 3709
e8711085 3710 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3711 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3712 if (!ha->init_cb)
e315cd28 3713 goto fail;
e8711085 3714
2d70c103
NB		 3715 if (qlt_mem_alloc(ha) < 0)
3716 goto fail_free_init_cb;
3717
642ef983
CD		 3718 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3719 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3720 if (!ha->gid_list)
2d70c103 3721 goto fail_free_tgt_mem;
1da177e4 3722
e8711085
AV		 3723 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3724 if (!ha->srb_mempool)
e315cd28 3725 goto fail_free_gid_list;
e8711085 3726
7ec0effd 3727 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3728 /* Allocate cache for CT6 Ctx. */
3729 if (!ctx_cachep) {
3730 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3731 sizeof(struct ct6_dsd), 0,
3732 SLAB_HWCACHE_ALIGN, NULL);
3733 if (!ctx_cachep)
fc1ffd6c 3734 goto fail_free_srb_mempool;
a9083016
GM		 3735 }
3736 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3737 ctx_cachep);
3738 if (!ha->ctx_mempool)
3739 goto fail_free_srb_mempool;
7c3df132
SK		 3740 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3741 "ctx_cachep=%p ctx_mempool=%p.\n",
3742 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3743 }
3744
e8711085
AV		 3745 /* Get memory for cached NVRAM */
3746 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3747 if (!ha->nvram)
a9083016 3748 goto fail_free_ctx_mempool;
e8711085 3749
e315cd28
AC		 3750 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3751 ha->pdev->device);
3752 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3753 DMA_POOL_SIZE, 8, 0);
3754 if (!ha->s_dma_pool)
3755 goto fail_free_nvram;
3756
7c3df132
SK		 3757 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3758 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3759 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3760
7ec0effd 3761 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3762 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3763 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3764 if (!ha->dl_dma_pool) {
7c3df132
SK		 3765 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3766 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3767 goto fail_s_dma_pool;
3768 }
3769
3770 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3771 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3772 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3773 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3774 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3775 goto fail_dl_dma_pool;
3776 }
7c3df132
SK		 3777 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3778 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3779 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3780 }
3781
e8711085
AV		 3782 /* Allocate memory for SNS commands */
3783 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3784 /* Get consistent memory allocated for SNS commands */
e8711085 3785 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3786 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3787 if (!ha->sns_cmd)
e315cd28 3788 goto fail_dma_pool;
7c3df132 3789 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3790 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3791 } else {
e315cd28 3792 /* Get consistent memory allocated for MS IOCB */
e8711085 3793 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3794 &ha->ms_iocb_dma);
e8711085 3795 if (!ha->ms_iocb)
e315cd28
AC		 3796 goto fail_dma_pool;
3797 /* Get consistent memory allocated for CT SNS commands */
e8711085 3798 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3799 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3800 if (!ha->ct_sns)
3801 goto fail_free_ms_iocb;
7c3df132
SK		 3802 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3803 "ms_iocb=%p ct_sns=%p.\n",
3804 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3805 }
3806
e315cd28 3807 /* Allocate memory for request ring */
73208dfd
AC		 3808 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3809 if (!*req) {
7c3df132
SK		 3810 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3811 "Failed to allocate memory for req.\n");
e315cd28
AC		 3812 goto fail_req;
3813 }
73208dfd
AC		 3814 (*req)->length = req_len;
3815 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3816 ((*req)->length + 1) * sizeof(request_t),
3817 &(*req)->dma, GFP_KERNEL);
3818 if (!(*req)->ring) {
7c3df132
SK		 3819 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3820 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3821 goto fail_req_ring;
3822 }
3823 /* Allocate memory for response ring */
73208dfd
AC		 3824 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3825 if (!*rsp) {
7c3df132
SK		 3826 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3827 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3828 goto fail_rsp;
3829 }
73208dfd
AC		 3830 (*rsp)->hw = ha;
3831 (*rsp)->length = rsp_len;
3832 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3833 ((*rsp)->length + 1) * sizeof(response_t),
3834 &(*rsp)->dma, GFP_KERNEL);
3835 if (!(*rsp)->ring) {
7c3df132
SK		 3836 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3837 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3838 goto fail_rsp_ring;
3839 }
73208dfd
AC		 3840 (*req)->rsp = *rsp;
3841 (*rsp)->req = *req;
7c3df132
SK		 3842 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3843 "req=%p req->length=%d req->ring=%p rsp=%p "
3844 "rsp->length=%d rsp->ring=%p.\n",
3845 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3846 (*rsp)->ring);
73208dfd
AC		 3847 /* Allocate memory for NVRAM data for vports */
3848 if (ha->nvram_npiv_size) {
3849 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3850 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3851 if (!ha->npiv_info) {
7c3df132
SK		 3852 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3853 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3854 goto fail_npiv_info;
3855 }
3856 } else
3857 ha->npiv_info = NULL;
e8711085 3858
b64b0e8f 3859 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3860 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3861 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3862 &ha->ex_init_cb_dma);
3863 if (!ha->ex_init_cb)
3864 goto fail_ex_init_cb;
7c3df132
SK		 3865 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3866 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3867 }
3868
a9083016
GM		 3869 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3870
5ff1d584
AV		 3871 /* Get consistent memory allocated for Async Port-Database. */
3872 if (!IS_FWI2_CAPABLE(ha)) {
3873 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3874 &ha->async_pd_dma);
3875 if (!ha->async_pd)
3876 goto fail_async_pd;
7c3df132
SK		 3877 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3878 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3879 }
3880
e315cd28 3881 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3882
3883 /* Allocate memory for our loop_id bitmap */
3884 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3885 GFP_KERNEL);
3886 if (!ha->loop_id_map)
fc1ffd6c 3887 goto fail_loop_id_map;
5f16b331
CD		 3888 else {
3889 qla2x00_set_reserved_loop_ids(ha);
3890 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3891 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3892 }
3893
b2a72ec3 3894 return 0;
e315cd28 3895
fc1ffd6c
QT		 3896fail_loop_id_map:
3897 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3898fail_async_pd:
3899 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3900fail_ex_init_cb:
3901 kfree(ha->npiv_info);
73208dfd
AC		 3902fail_npiv_info:
3903 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3904 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3905 (*rsp)->ring = NULL;
3906 (*rsp)->dma = 0;
e315cd28 3907fail_rsp_ring:
73208dfd 3908 kfree(*rsp);
e315cd28 3909fail_rsp:
73208dfd
AC		 3910 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3911 sizeof(request_t), (*req)->ring, (*req)->dma);
3912 (*req)->ring = NULL;
3913 (*req)->dma = 0;
e315cd28 3914fail_req_ring:
73208dfd 3915 kfree(*req);
e315cd28
AC		 3916fail_req:
3917 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3918 ha->ct_sns, ha->ct_sns_dma);
3919 ha->ct_sns = NULL;
3920 ha->ct_sns_dma = 0;
e8711085
AV		 3921fail_free_ms_iocb:
3922 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3923 ha->ms_iocb = NULL;
3924 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3925
3926 if (ha->sns_cmd)
3927 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3928 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3929fail_dma_pool:
bad75002 3930 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3931 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3932 ha->fcp_cmnd_dma_pool = NULL;
3933 }
3934fail_dl_dma_pool:
bad75002 3935 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3936 dma_pool_destroy(ha->dl_dma_pool);
3937 ha->dl_dma_pool = NULL;
3938 }
3939fail_s_dma_pool:
e315cd28
AC		 3940 dma_pool_destroy(ha->s_dma_pool);
3941 ha->s_dma_pool = NULL;
e8711085
AV		 3942fail_free_nvram:
3943 kfree(ha->nvram);
3944 ha->nvram = NULL;
a9083016 3945fail_free_ctx_mempool:
fc1ffd6c
QT		 3946 if (ha->ctx_mempool)
3947 mempool_destroy(ha->ctx_mempool);
a9083016 3948 ha->ctx_mempool = NULL;
e8711085 3949fail_free_srb_mempool:
fc1ffd6c
QT		 3950 if (ha->srb_mempool)
3951 mempool_destroy(ha->srb_mempool);
e8711085 3952 ha->srb_mempool = NULL;
e8711085 3953fail_free_gid_list:
642ef983
CD		 3954 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3955 ha->gid_list,
e315cd28 3956 ha->gid_list_dma);
e8711085
AV		 3957 ha->gid_list = NULL;
3958 ha->gid_list_dma = 0;
2d70c103
NB		 3959fail_free_tgt_mem:
3960 qlt_mem_free(ha);
e315cd28
AC		 3961fail_free_init_cb:
3962 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3963 ha->init_cb_dma);
3964 ha->init_cb = NULL;
3965 ha->init_cb_dma = 0;
e8711085 3966fail:
7c3df132
SK		 3967 ql_log(ql_log_fatal, NULL, 0x0030,
3968 "Memory allocation failure.\n");
e8711085 3969 return -ENOMEM;
1da177e4
LT		 3970}
3971
b0d6cabd
HM		 3972int
3973qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3974{
3975 int rval;
3976 uint16_t size, max_cnt, temp;
3977 struct qla_hw_data *ha = vha->hw;
3978
3979 /* Return if we don't need to alloacate any extended logins */
3980 if (!ql2xexlogins)
3981 return QLA_SUCCESS;
3982
3983 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3984 max_cnt = 0;
3985 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3986 if (rval != QLA_SUCCESS) {
3987 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3988 "Failed to get exlogin status.\n");
3989 return rval;
3990 }
3991
3992 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3993 ha->exlogin_size = (size * temp);
3994 ql_log(ql_log_info, vha, 0xd024,
3995 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3996 max_cnt, size, temp);
3997
3998 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3999 ha->exlogin_size);
4000
4001 /* Get consistent memory for extended logins */
4002 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4003 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4004 if (!ha->exlogin_buf) {
4005 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4006 "Failed to allocate memory for exlogin_buf_dma.\n");
4007 return -ENOMEM;
4008 }
4009
4010 /* Now configure the dma buffer */
4011 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4012 if (rval) {
4013 ql_log(ql_log_fatal, vha, 0x00cf,
4014 "Setup extended login buffer ****FAILED****.\n");
4015 qla2x00_free_exlogin_buffer(ha);
4016 }
4017
4018 return rval;
4019}
4020
4021/*
4022* qla2x00_free_exlogin_buffer
4023*
4024* Input:
4025* ha = adapter block pointer
4026*/
4027void
4028qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4029{
4030 if (ha->exlogin_buf) {
4031 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4032 ha->exlogin_buf, ha->exlogin_buf_dma);
4033 ha->exlogin_buf = NULL;
4034 ha->exlogin_size = 0;
4035 }
4036}
4037
2f56a7f1
HM		 4038int
4039qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4040{
4041 int rval;
4042 uint16_t size, max_cnt, temp;
4043 struct qla_hw_data *ha = vha->hw;
4044
4045 /* Return if we don't need to alloacate any extended logins */
4046 if (!ql2xexchoffld)
4047 return QLA_SUCCESS;
4048
4049 ql_log(ql_log_info, vha, 0xd014,
4050 "Exchange offload count: %d.\n", ql2xexlogins);
4051
4052 max_cnt = 0;
4053 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4054 if (rval != QLA_SUCCESS) {
4055 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4056 "Failed to get exlogin status.\n");
4057 return rval;
4058 }
4059
4060 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
4061 ha->exchoffld_size = (size * temp);
4062 ql_log(ql_log_info, vha, 0xd016,
4063 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4064 max_cnt, size, temp);
4065
4066 ql_log(ql_log_info, vha, 0xd017,
4067 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
4068
4069 /* Get consistent memory for extended logins */
4070 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4071 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4072 if (!ha->exchoffld_buf) {
4073 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4074 "Failed to allocate memory for exchoffld_buf_dma.\n");
4075 return -ENOMEM;
4076 }
4077
4078 /* Now configure the dma buffer */
4079 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4080 if (rval) {
4081 ql_log(ql_log_fatal, vha, 0xd02e,
4082 "Setup exchange offload buffer ****FAILED****.\n");
4083 qla2x00_free_exchoffld_buffer(ha);
4084 }
4085
4086 return rval;
4087}
4088
4089/*
4090* qla2x00_free_exchoffld_buffer
4091*
4092* Input:
4093* ha = adapter block pointer
4094*/
4095void
4096qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4097{
4098 if (ha->exchoffld_buf) {
4099 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4100 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4101 ha->exchoffld_buf = NULL;
4102 ha->exchoffld_size = 0;
4103 }
4104}
4105
1da177e4 4106/*
e30d1756
MI		 4107* qla2x00_free_fw_dump
4108* Frees fw dump stuff.
1da177e4
LT		 4109*
4110* Input:
7ec0effd 4111* ha = adapter block pointer
1da177e4 4112*/
a824ebb3 4113static void
e30d1756 4114qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4115{
df613b96 4116 if (ha->fce)
f73cb695
CD		 4117 dma_free_coherent(&ha->pdev->dev,
4118 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4119
f73cb695
CD		 4120 if (ha->eft)
4121 dma_free_coherent(&ha->pdev->dev,
4122 EFT_SIZE, ha->eft, ha->eft_dma);
4123
4124 if (ha->fw_dump)
a7a167bf 4125 vfree(ha->fw_dump);
f73cb695
CD		 4126 if (ha->fw_dump_template)
4127 vfree(ha->fw_dump_template);
4128
e30d1756
MI		 4129 ha->fce = NULL;
4130 ha->fce_dma = 0;
4131 ha->eft = NULL;
4132 ha->eft_dma = 0;
e30d1756 4133 ha->fw_dumped = 0;
61f098dd 4134 ha->fw_dump_cap_flags = 0;
e30d1756 4135 ha->fw_dump_reading = 0;
f73cb695
CD		 4136 ha->fw_dump = NULL;
4137 ha->fw_dump_len = 0;
4138 ha->fw_dump_template = NULL;
4139 ha->fw_dump_template_len = 0;
e30d1756
MI		 4140}
4141
4142/*
4143* qla2x00_mem_free
4144* Frees all adapter allocated memory.
4145*
4146* Input:
4147* ha = adapter block pointer.
4148*/
4149static void
4150qla2x00_mem_free(struct qla_hw_data *ha)
4151{
4152 qla2x00_free_fw_dump(ha);
4153
81178772
SK		 4154 if (ha->mctp_dump)
4155 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4156 ha->mctp_dump_dma);
4157
e30d1756
MI		 4158 if (ha->srb_mempool)
4159 mempool_destroy(ha->srb_mempool);
a7a167bf 4160
11bbc1d8
AV		 4161 if (ha->dcbx_tlv)
4162 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4163 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4164
ce0423f4
AV		 4165 if (ha->xgmac_data)
4166 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4167 ha->xgmac_data, ha->xgmac_data_dma);
4168
1da177e4
LT		 4169 if (ha->sns_cmd)
4170 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4171 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4172
4173 if (ha->ct_sns)
4174 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4175 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4176
88729e53
AV		 4177 if (ha->sfp_data)
4178 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4179
1da177e4
LT		 4180 if (ha->ms_iocb)
4181 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4182
b64b0e8f 4183 if (ha->ex_init_cb)
a9083016
GM		 4184 dma_pool_free(ha->s_dma_pool,
4185 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4186
5ff1d584
AV		 4187 if (ha->async_pd)
4188 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4189
1da177e4
LT		 4190 if (ha->s_dma_pool)
4191 dma_pool_destroy(ha->s_dma_pool);
4192
1da177e4 4193 if (ha->gid_list)
642ef983
CD		 4194 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4195 ha->gid_list, ha->gid_list_dma);
1da177e4 4196
a9083016
GM		 4197 if (IS_QLA82XX(ha)) {
4198 if (!list_empty(&ha->gbl_dsd_list)) {
4199 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4200
4201 /* clean up allocated prev pool */
4202 list_for_each_entry_safe(dsd_ptr,
4203 tdsd_ptr, &ha->gbl_dsd_list, list) {
4204 dma_pool_free(ha->dl_dma_pool,
4205 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4206 list_del(&dsd_ptr->list);
4207 kfree(dsd_ptr);
4208 }
4209 }
4210 }
4211
4212 if (ha->dl_dma_pool)
4213 dma_pool_destroy(ha->dl_dma_pool);
4214
4215 if (ha->fcp_cmnd_dma_pool)
4216 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4217
4218 if (ha->ctx_mempool)
4219 mempool_destroy(ha->ctx_mempool);
4220
2d70c103
NB		 4221 qlt_mem_free(ha);
4222
e315cd28
AC		 4223 if (ha->init_cb)
4224 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4225 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4226 vfree(ha->optrom_buffer);
4227 kfree(ha->nvram);
73208dfd 4228 kfree(ha->npiv_info);
7a67735b 4229 kfree(ha->swl);
5f16b331 4230 kfree(ha->loop_id_map);
1da177e4 4231
e8711085 4232 ha->srb_mempool = NULL;
a9083016 4233 ha->ctx_mempool = NULL;
1da177e4
LT		 4234 ha->sns_cmd = NULL;
4235 ha->sns_cmd_dma = 0;
4236 ha->ct_sns = NULL;
4237 ha->ct_sns_dma = 0;
4238 ha->ms_iocb = NULL;
4239 ha->ms_iocb_dma = 0;
1da177e4
LT		 4240 ha->init_cb = NULL;
4241 ha->init_cb_dma = 0;
b64b0e8f
AV		 4242 ha->ex_init_cb = NULL;
4243 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4244 ha->async_pd = NULL;
4245 ha->async_pd_dma = 0;
1da177e4
LT		 4246
4247 ha->s_dma_pool = NULL;
a9083016
GM		 4248 ha->dl_dma_pool = NULL;
4249 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4250
1da177e4
LT		 4251 ha->gid_list = NULL;
4252 ha->gid_list_dma = 0;
2d70c103
NB		 4253
4254 ha->tgt.atio_ring = NULL;
4255 ha->tgt.atio_dma = 0;
4256 ha->tgt.tgt_vp_map = NULL;
e315cd28 4257}
1da177e4 4258
e315cd28
AC		 4259struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4260 struct qla_hw_data *ha)
4261{
4262 struct Scsi_Host *host;
4263 struct scsi_qla_host *vha = NULL;
854165f4 4264
e315cd28 4265 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4266 if (!host) {
7c3df132
SK		 4267 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4268 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4269 return NULL;
e315cd28
AC		 4270 }
4271
4272 /* Clear our data area */
4273 vha = shost_priv(host);
4274 memset(vha, 0, sizeof(scsi_qla_host_t));
4275
4276 vha->host = host;
4277 vha->host_no = host->host_no;
4278 vha->hw = ha;
4279
4280 INIT_LIST_HEAD(&vha->vp_fcports);
4281 INIT_LIST_HEAD(&vha->work_list);
4282 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4283 INIT_LIST_HEAD(&vha->qla_cmd_list);
4284 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4285 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4286 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4287 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4288 INIT_LIST_HEAD(&vha->gnl.fcports);
e315cd28 4289
f999f4c1 4290 spin_lock_init(&vha->work_lock);
8b2f5ff3 4291 spin_lock_init(&vha->cmd_list_lock);
726b8548 4292 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4293 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4294
2fdbc65e
BVA		 4295 vha->gnl.size = sizeof(struct get_name_list_extended) *
4296 (ha->max_loop_id + 1);
41dc529a
QT		 4297 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4298 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4299 if (!vha->gnl.l) {
4300 ql_log(ql_log_fatal, vha, 0xffff,
4301 "Alloc failed for name list.\n");
4302 scsi_remove_host(vha->host);
4303 return NULL;
4304 }
f999f4c1 4305
e315cd28 4306 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4307 ql_dbg(ql_dbg_init, vha, 0x0041,
4308 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4309 vha->host, vha->hw, vha,
4310 dev_name(&(ha->pdev->dev)));
4311
e315cd28 4312 return vha;
1da177e4
LT		 4313}
4314
726b8548 4315struct qla_work_evt *
f999f4c1 4316qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4317{
4318 struct qla_work_evt *e;
feafb7b1
AE		 4319 uint8_t bail;
4320
4321 QLA_VHA_MARK_BUSY(vha, bail);
4322 if (bail)
4323 return NULL;
0971de7f 4324
f999f4c1 4325 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4326 if (!e) {
4327 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4328 return NULL;
feafb7b1 4329 }
0971de7f
AV		 4330
4331 INIT_LIST_HEAD(&e->list);
4332 e->type = type;
4333 e->flags = QLA_EVT_FLAG_FREE;
4334 return e;
4335}
4336
726b8548 4337int
f999f4c1 4338qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4339{
f999f4c1 4340 unsigned long flags;
0971de7f 4341
f999f4c1 4342 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4343 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4344 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4345
4346 if (QLA_EARLY_LINKUP(vha->hw))
4347 schedule_work(&vha->iocb_work);
4348 else
4349 qla2xxx_wake_dpc(vha);
f999f4c1 4350
0971de7f
AV		 4351 return QLA_SUCCESS;
4352}
4353
4354int
e315cd28 4355qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4356 u32 data)
4357{
4358 struct qla_work_evt *e;
4359
f999f4c1 4360 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4361 if (!e)
4362 return QLA_FUNCTION_FAILED;
4363
4364 e->u.aen.code = code;
4365 e->u.aen.data = data;
f999f4c1 4366 return qla2x00_post_work(vha, e);
0971de7f
AV		 4367}
4368
8a659571
AV		 4369int
4370qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4371{
4372 struct qla_work_evt *e;
4373
f999f4c1 4374 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4375 if (!e)
4376 return QLA_FUNCTION_FAILED;
4377
4378 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4379 return qla2x00_post_work(vha, e);
8a659571
AV		 4380}
4381
ac280b67
AV		 4382#define qla2x00_post_async_work(name, type) \
4383int qla2x00_post_async_##name##_work( \
4384 struct scsi_qla_host *vha, \
4385 fc_port_t *fcport, uint16_t *data) \
4386{ \
4387 struct qla_work_evt *e; \
4388 \
4389 e = qla2x00_alloc_work(vha, type); \
4390 if (!e) \
4391 return QLA_FUNCTION_FAILED; \
4392 \
4393 e->u.logio.fcport = fcport; \
4394 if (data) { \
4395 e->u.logio.data[0] = data[0]; \
4396 e->u.logio.data[1] = data[1]; \
4397 } \
4398 return qla2x00_post_work(vha, e); \
4399}
4400
4401qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4402qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4403qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4404qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4405qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4406
3420d36c
AV		 4407int
4408qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4409{
4410 struct qla_work_evt *e;
4411
4412 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4413 if (!e)
4414 return QLA_FUNCTION_FAILED;
4415
4416 e->u.uevent.code = code;
4417 return qla2x00_post_work(vha, e);
4418}
4419
4420static void
4421qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4422{
4423 char event_string[40];
4424 char *envp[] = { event_string, NULL };
4425
4426 switch (code) {
4427 case QLA_UEVENT_CODE_FW_DUMP:
4428 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4429 vha->host_no);
4430 break;
4431 default:
4432 /* do nothing */
4433 break;
4434 }
4435 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4436}
4437
8ae6d9c7
GM		 4438int
4439qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4440 uint32_t *data, int cnt)
4441{
4442 struct qla_work_evt *e;
4443
4444 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4445 if (!e)
4446 return QLA_FUNCTION_FAILED;
4447
4448 e->u.aenfx.evtcode = evtcode;
4449 e->u.aenfx.count = cnt;
4450 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4451 return qla2x00_post_work(vha, e);
4452}
4453
726b8548
QT		 4454int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4455{
4456 struct qla_work_evt *e;
4457
4458 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4459 if (!e)
4460 return QLA_FUNCTION_FAILED;
4461
4462 e->u.fcport.fcport = fcport;
4463 return qla2x00_post_work(vha, e);
4464}
4465
4466static
4467void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4468{
4469 unsigned long flags;
4470 fc_port_t *fcport = NULL;
4471 struct qlt_plogi_ack_t *pla =
4472 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4473
4474 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4475 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4476 if (fcport) {
4477 fcport->d_id = e->u.new_sess.id;
4478 if (pla) {
4479 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4480 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4481 /* we took an extra ref_count to prevent PLOGI ACK when
4482 * fcport/sess has not been created.
4483 */
4484 pla->ref_count--;
4485 }
4486 } else {
4487 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4488 if (fcport) {
4489 fcport->d_id = e->u.new_sess.id;
4490 fcport->scan_state = QLA_FCPORT_FOUND;
4491 fcport->flags |= FCF_FABRIC_DEVICE;
4492 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4493
4494 memcpy(fcport->port_name, e->u.new_sess.port_name,
4495 WWN_SIZE);
4496 list_add_tail(&fcport->list, &vha->vp_fcports);
4497
4498 if (pla) {
4499 qlt_plogi_ack_link(vha, pla, fcport,
4500 QLT_PLOGI_LINK_SAME_WWN);
4501 pla->ref_count--;
4502 }
4503 }
4504 }
4505 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4506
4507 if (fcport) {
4508 if (pla)
4509 qlt_plogi_ack_unref(vha, pla);
4510 else
4511 qla24xx_async_gnl(vha, fcport);
4512 }
4513}
4514
ac280b67 4515void
e315cd28 4516qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4517{
f999f4c1
AV		 4518 struct qla_work_evt *e, *tmp;
4519 unsigned long flags;
4520 LIST_HEAD(work);
0971de7f 4521
f999f4c1
AV		 4522 spin_lock_irqsave(&vha->work_lock, flags);
4523 list_splice_init(&vha->work_list, &work);
4524 spin_unlock_irqrestore(&vha->work_lock, flags);
4525
4526 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4527 list_del_init(&e->list);
0971de7f
AV		 4528
4529 switch (e->type) {
4530 case QLA_EVT_AEN:
e315cd28 4531 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4532 e->u.aen.code, e->u.aen.data);
4533 break;
8a659571
AV		 4534 case QLA_EVT_IDC_ACK:
4535 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4536 break;
ac280b67
AV		 4537 case QLA_EVT_ASYNC_LOGIN:
4538 qla2x00_async_login(vha, e->u.logio.fcport,
4539 e->u.logio.data);
4540 break;
ac280b67
AV		 4541 case QLA_EVT_ASYNC_LOGOUT:
4542 qla2x00_async_logout(vha, e->u.logio.fcport);
4543 break;
4544 case QLA_EVT_ASYNC_LOGOUT_DONE:
4545 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4546 e->u.logio.data);
4547 break;
5ff1d584
AV		 4548 case QLA_EVT_ASYNC_ADISC:
4549 qla2x00_async_adisc(vha, e->u.logio.fcport,
4550 e->u.logio.data);
4551 break;
4552 case QLA_EVT_ASYNC_ADISC_DONE:
4553 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4554 e->u.logio.data);
4555 break;
3420d36c
AV		 4556 case QLA_EVT_UEVENT:
4557 qla2x00_uevent_emit(vha, e->u.uevent.code);
4558 break;
8ae6d9c7
GM		 4559 case QLA_EVT_AENFX:
4560 qlafx00_process_aen(vha, e);
4561 break;
726b8548
QT		 4562 case QLA_EVT_GIDPN:
4563 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4564 break;
4565 case QLA_EVT_GPNID:
4566 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4567 break;
4568 case QLA_EVT_GPNID_DONE:
4569 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4570 break;
4571 case QLA_EVT_NEW_SESS:
4572 qla24xx_create_new_sess(vha, e);
4573 break;
4574 case QLA_EVT_GPDB:
4575 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4576 e->u.fcport.opt);
4577 break;
4578 case QLA_EVT_GPSC:
4579 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4580 break;
4581 case QLA_EVT_UPD_FCPORT:
4582 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4583 break;
4584 case QLA_EVT_GNL:
4585 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4586 break;
4587 case QLA_EVT_NACK:
4588 qla24xx_do_nack_work(vha, e);
4589 break;
0971de7f
AV		 4590 }
4591 if (e->flags & QLA_EVT_FLAG_FREE)
4592 kfree(e);
feafb7b1
AE		 4593
4594 /* For each work completed decrement vha ref count */
4595 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4596 }
e315cd28 4597}
f999f4c1 4598
e315cd28
AC		 4599/* Relogins all the fcports of a vport
4600 * Context: dpc thread
4601 */
4602void qla2x00_relogin(struct scsi_qla_host *vha)
4603{
4604 fc_port_t *fcport;
c6b2fca8 4605 int status;
726b8548 4606 struct event_arg ea;
e315cd28
AC		 4607
4608 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4609 /*
4610 * If the port is not ONLINE then try to login
4611 * to it if we haven't run out of retries.
4612 */
5ff1d584
AV		 4613 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4614 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4615 fcport->login_retry--;
e315cd28 4616 if (fcport->flags & FCF_FABRIC_DEVICE) {
726b8548
QT		 4617 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
4618 "%s %8phC DS %d LS %d\n", __func__,
4619 fcport->port_name, fcport->disc_state,
4620 fcport->fw_login_state);
4621 memset(&ea, 0, sizeof(ea));
4622 ea.event = FCME_RELOGIN;
4623 ea.fcport = fcport;
4624 qla2x00_fcport_event_handler(vha, &ea);
4625 } else {
e315cd28
AC		 4626 status = qla2x00_local_device_login(vha,
4627 fcport);
726b8548
QT		 4628 if (status == QLA_SUCCESS) {
4629 fcport->old_loop_id = fcport->loop_id;
4630 ql_dbg(ql_dbg_disc, vha, 0x2003,
4631 "Port login OK: logged in ID 0x%x.\n",
4632 fcport->loop_id);
4633 qla2x00_update_fcport(vha, fcport);
4634 } else if (status == 1) {
4635 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4636 /* retry the login again */
4637 ql_dbg(ql_dbg_disc, vha, 0x2007,
4638 "Retrying %d login again loop_id 0x%x.\n",
4639 fcport->login_retry,
4640 fcport->loop_id);
4641 } else {
4642 fcport->login_retry = 0;
4643 }
e315cd28 4644
726b8548
QT		 4645 if (fcport->login_retry == 0 &&
4646 status != QLA_SUCCESS)
4647 qla2x00_clear_loop_id(fcport);
e315cd28 4648 }
e315cd28
AC		 4649 }
4650 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4651 break;
0971de7f 4652 }
0971de7f
AV		 4653}
4654
7d613ac6
SV		 4655/* Schedule work on any of the dpc-workqueues */
4656void
4657qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4658{
4659 struct qla_hw_data *ha = base_vha->hw;
4660
4661 switch (work_code) {
4662 case MBA_IDC_AEN: /* 0x8200 */
4663 if (ha->dpc_lp_wq)
4664 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4665 break;
4666
4667 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4668 if (!ha->flags.nic_core_reset_hdlr_active) {
4669 if (ha->dpc_hp_wq)
4670 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4671 } else
4672 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4673 "NIC Core reset is already active. Skip "
4674 "scheduling it again.\n");
4675 break;
4676 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4677 if (ha->dpc_hp_wq)
4678 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4679 break;
4680 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4681 if (ha->dpc_hp_wq)
4682 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4683 break;
4684 default:
4685 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4686 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4687 }
4688
4689 return;
4690}
4691
4692/* Work: Perform NIC Core Unrecoverable state handling */
4693void
4694qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4695{
4696 struct qla_hw_data *ha =
2ad1b67c 4697 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4698 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4699 uint32_t dev_state = 0;
4700
4701 qla83xx_idc_lock(base_vha, 0);
4702 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4703 qla83xx_reset_ownership(base_vha);
4704 if (ha->flags.nic_core_reset_owner) {
4705 ha->flags.nic_core_reset_owner = 0;
4706 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4707 QLA8XXX_DEV_FAILED);
4708 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4709 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4710 }
4711 qla83xx_idc_unlock(base_vha, 0);
4712}
4713
4714/* Work: Execute IDC state handler */
4715void
4716qla83xx_idc_state_handler_work(struct work_struct *work)
4717{
4718 struct qla_hw_data *ha =
2ad1b67c 4719 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4720 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4721 uint32_t dev_state = 0;
4722
4723 qla83xx_idc_lock(base_vha, 0);
4724 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4725 if (dev_state == QLA8XXX_DEV_FAILED ||
4726 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4727 qla83xx_idc_state_handler(base_vha);
4728 qla83xx_idc_unlock(base_vha, 0);
4729}
4730
fa492630 4731static int
7d613ac6
SV		 4732qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4733{
4734 int rval = QLA_SUCCESS;
4735 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4736 uint32_t heart_beat_counter1, heart_beat_counter2;
4737
4738 do {
4739 if (time_after(jiffies, heart_beat_wait)) {
4740 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4741 "Nic Core f/w is not alive.\n");
4742 rval = QLA_FUNCTION_FAILED;
4743 break;
4744 }
4745
4746 qla83xx_idc_lock(base_vha, 0);
4747 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4748 &heart_beat_counter1);
4749 qla83xx_idc_unlock(base_vha, 0);
4750 msleep(100);
4751 qla83xx_idc_lock(base_vha, 0);
4752 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4753 &heart_beat_counter2);
4754 qla83xx_idc_unlock(base_vha, 0);
4755 } while (heart_beat_counter1 == heart_beat_counter2);
4756
4757 return rval;
4758}
4759
4760/* Work: Perform NIC Core Reset handling */
4761void
4762qla83xx_nic_core_reset_work(struct work_struct *work)
4763{
4764 struct qla_hw_data *ha =
4765 container_of(work, struct qla_hw_data, nic_core_reset);
4766 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4767 uint32_t dev_state = 0;
4768
81178772
SK		 4769 if (IS_QLA2031(ha)) {
4770 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4771 ql_log(ql_log_warn, base_vha, 0xb081,
4772 "Failed to dump mctp\n");
4773 return;
4774 }
4775
7d613ac6
SV		 4776 if (!ha->flags.nic_core_reset_hdlr_active) {
4777 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4778 qla83xx_idc_lock(base_vha, 0);
4779 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4780 &dev_state);
4781 qla83xx_idc_unlock(base_vha, 0);
4782 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4783 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4784 "Nic Core f/w is alive.\n");
4785 return;
4786 }
4787 }
4788
4789 ha->flags.nic_core_reset_hdlr_active = 1;
4790 if (qla83xx_nic_core_reset(base_vha)) {
4791 /* NIC Core reset failed. */
4792 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4793 "NIC Core reset failed.\n");
4794 }
4795 ha->flags.nic_core_reset_hdlr_active = 0;
4796 }
4797}
4798
4799/* Work: Handle 8200 IDC aens */
4800void
4801qla83xx_service_idc_aen(struct work_struct *work)
4802{
4803 struct qla_hw_data *ha =
4804 container_of(work, struct qla_hw_data, idc_aen);
4805 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4806 uint32_t dev_state, idc_control;
4807
4808 qla83xx_idc_lock(base_vha, 0);
4809 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4810 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4811 qla83xx_idc_unlock(base_vha, 0);
4812 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4813 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4814 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4815 "Application requested NIC Core Reset.\n");
4816 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4817 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4818 QLA_SUCCESS) {
4819 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4820 "Other protocol driver requested NIC Core Reset.\n");
4821 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4822 }
4823 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4824 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4825 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4826 }
4827}
4828
4829static void
4830qla83xx_wait_logic(void)
4831{
4832 int i;
4833
4834 /* Yield CPU */
4835 if (!in_interrupt()) {
4836 /*
4837 * Wait about 200ms before retrying again.
4838 * This controls the number of retries for single
4839 * lock operation.
4840 */
4841 msleep(100);
4842 schedule();
4843 } else {
4844 for (i = 0; i < 20; i++)
4845 cpu_relax(); /* This a nop instr on i386 */
4846 }
4847}
4848
fa492630 4849static int
7d613ac6
SV		 4850qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4851{
4852 int rval;
4853 uint32_t data;
4854 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4855 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4856 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4857 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4858 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4859
4860 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4861 if (rval)
4862 return rval;
4863
4864 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4865 return QLA_SUCCESS;
4866 } else {
4867 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4868 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4869 data);
4870 if (rval)
4871 return rval;
4872
4873 msleep(200);
4874
4875 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4876 &data);
4877 if (rval)
4878 return rval;
4879
4880 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4881 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4882 ~(idc_lck_rcvry_stage_mask));
4883 rval = qla83xx_wr_reg(base_vha,
4884 QLA83XX_IDC_LOCK_RECOVERY, data);
4885 if (rval)
4886 return rval;
4887
4888 /* Forcefully perform IDC UnLock */
4889 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4890 &data);
4891 if (rval)
4892 return rval;
4893 /* Clear lock-id by setting 0xff */
4894 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4895 0xff);
4896 if (rval)
4897 return rval;
4898 /* Clear lock-recovery by setting 0x0 */
4899 rval = qla83xx_wr_reg(base_vha,
4900 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4901 if (rval)
4902 return rval;
4903 } else
4904 return QLA_SUCCESS;
4905 }
4906
4907 return rval;
4908}
4909
fa492630 4910static int
7d613ac6
SV		 4911qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4912{
4913 int rval = QLA_SUCCESS;
4914 uint32_t o_drv_lockid, n_drv_lockid;
4915 unsigned long lock_recovery_timeout;
4916
4917 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4918retry_lockid:
4919 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4920 if (rval)
4921 goto exit;
4922
4923 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4924 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4925 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4926 return QLA_SUCCESS;
4927 else
4928 return QLA_FUNCTION_FAILED;
4929 }
4930
4931 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4932 if (rval)
4933 goto exit;
4934
4935 if (o_drv_lockid == n_drv_lockid) {
4936 qla83xx_wait_logic();
4937 goto retry_lockid;
4938 } else
4939 return QLA_SUCCESS;
4940
4941exit:
4942 return rval;
4943}
4944
4945void
4946qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4947{
4948 uint16_t options = (requester_id << 15) | BIT_6;
4949 uint32_t data;
6c315553 4950 uint32_t lock_owner;
7d613ac6
SV		 4951 struct qla_hw_data *ha = base_vha->hw;
4952
4953 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4954retry_lock:
4955 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4956 == QLA_SUCCESS) {
4957 if (data) {
4958 /* Setting lock-id to our function-number */
4959 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4960 ha->portnum);
4961 } else {
6c315553
SK		 4962 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4963 &lock_owner);
7d613ac6 4964 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4965 "Failed to acquire IDC lock, acquired by %d, "
4966 "retrying...\n", lock_owner);
7d613ac6
SV		 4967
4968 /* Retry/Perform IDC-Lock recovery */
4969 if (qla83xx_idc_lock_recovery(base_vha)
4970 == QLA_SUCCESS) {
4971 qla83xx_wait_logic();
4972 goto retry_lock;
4973 } else
4974 ql_log(ql_log_warn, base_vha, 0xb075,
4975 "IDC Lock recovery FAILED.\n");
4976 }
4977
4978 }
4979
4980 return;
4981
4982 /* XXX: IDC-lock implementation using access-control mbx */
4983retry_lock2:
4984 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4985 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4986 "Failed to acquire IDC lock. retrying...\n");
4987 /* Retry/Perform IDC-Lock recovery */
4988 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4989 qla83xx_wait_logic();
4990 goto retry_lock2;
4991 } else
4992 ql_log(ql_log_warn, base_vha, 0xb076,
4993 "IDC Lock recovery FAILED.\n");
4994 }
4995
4996 return;
4997}
4998
4999void
5000qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5001{
5897cb2f
BVA		 5002#if 0
5003 uint16_t options = (requester_id << 15) | BIT_7;
5004#endif
5005 uint16_t retry;
7d613ac6
SV		 5006 uint32_t data;
5007 struct qla_hw_data *ha = base_vha->hw;
5008
5009 /* IDC-unlock implementation using driver-unlock/lock-id
5010 * remote registers
5011 */
5012 retry = 0;
5013retry_unlock:
5014 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5015 == QLA_SUCCESS) {
5016 if (data == ha->portnum) {
5017 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5018 /* Clearing lock-id by setting 0xff */
5019 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5020 } else if (retry < 10) {
5021 /* SV: XXX: IDC unlock retrying needed here? */
5022
5023 /* Retry for IDC-unlock */
5024 qla83xx_wait_logic();
5025 retry++;
5026 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5027 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5028 goto retry_unlock;
5029 }
5030 } else if (retry < 10) {
5031 /* Retry for IDC-unlock */
5032 qla83xx_wait_logic();
5033 retry++;
5034 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5035 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5036 goto retry_unlock;
5037 }
5038
5039 return;
5040
5897cb2f 5041#if 0
7d613ac6
SV		 5042 /* XXX: IDC-unlock implementation using access-control mbx */
5043 retry = 0;
5044retry_unlock2:
5045 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5046 if (retry < 10) {
5047 /* Retry for IDC-unlock */
5048 qla83xx_wait_logic();
5049 retry++;
5050 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5051 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5052 goto retry_unlock2;
5053 }
5054 }
5055
5056 return;
5897cb2f 5057#endif
7d613ac6
SV		 5058}
5059
5060int
5061__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5062{
5063 int rval = QLA_SUCCESS;
5064 struct qla_hw_data *ha = vha->hw;
5065 uint32_t drv_presence;
5066
5067 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5068 if (rval == QLA_SUCCESS) {
5069 drv_presence |= (1 << ha->portnum);
5070 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5071 drv_presence);
5072 }
5073
5074 return rval;
5075}
5076
5077int
5078qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5079{
5080 int rval = QLA_SUCCESS;
5081
5082 qla83xx_idc_lock(vha, 0);
5083 rval = __qla83xx_set_drv_presence(vha);
5084 qla83xx_idc_unlock(vha, 0);
5085
5086 return rval;
5087}
5088
5089int
5090__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5091{
5092 int rval = QLA_SUCCESS;
5093 struct qla_hw_data *ha = vha->hw;
5094 uint32_t drv_presence;
5095
5096 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5097 if (rval == QLA_SUCCESS) {
5098 drv_presence &= ~(1 << ha->portnum);
5099 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5100 drv_presence);
5101 }
5102
5103 return rval;
5104}
5105
5106int
5107qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5108{
5109 int rval = QLA_SUCCESS;
5110
5111 qla83xx_idc_lock(vha, 0);
5112 rval = __qla83xx_clear_drv_presence(vha);
5113 qla83xx_idc_unlock(vha, 0);
5114
5115 return rval;
5116}
5117
fa492630 5118static void
7d613ac6
SV		 5119qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5120{
5121 struct qla_hw_data *ha = vha->hw;
5122 uint32_t drv_ack, drv_presence;
5123 unsigned long ack_timeout;
5124
5125 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5126 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5127 while (1) {
5128 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5129 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5130 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5131 break;
5132
5133 if (time_after_eq(jiffies, ack_timeout)) {
5134 ql_log(ql_log_warn, vha, 0xb067,
5135 "RESET ACK TIMEOUT! drv_presence=0x%x "
5136 "drv_ack=0x%x\n", drv_presence, drv_ack);
5137 /*
5138 * The function(s) which did not ack in time are forced
5139 * to withdraw any further participation in the IDC
5140 * reset.
5141 */
5142 if (drv_ack != drv_presence)
5143 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5144 drv_ack);
5145 break;
5146 }
5147
5148 qla83xx_idc_unlock(vha, 0);
5149 msleep(1000);
5150 qla83xx_idc_lock(vha, 0);
5151 }
5152
5153 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5154 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5155}
5156
fa492630 5157static int
7d613ac6
SV		 5158qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5159{
5160 int rval = QLA_SUCCESS;
5161 uint32_t idc_control;
5162
5163 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5164 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5165
5166 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5167 __qla83xx_get_idc_control(vha, &idc_control);
5168 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5169 __qla83xx_set_idc_control(vha, 0);
5170
5171 qla83xx_idc_unlock(vha, 0);
5172 rval = qla83xx_restart_nic_firmware(vha);
5173 qla83xx_idc_lock(vha, 0);
5174
5175 if (rval != QLA_SUCCESS) {
5176 ql_log(ql_log_fatal, vha, 0xb06a,
5177 "Failed to restart NIC f/w.\n");
5178 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5179 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5180 } else {
5181 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5182 "Success in restarting nic f/w.\n");
5183 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5184 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5185 }
5186
5187 return rval;
5188}
5189
5190/* Assumes idc_lock always held on entry */
5191int
5192qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5193{
5194 struct qla_hw_data *ha = base_vha->hw;
5195 int rval = QLA_SUCCESS;
5196 unsigned long dev_init_timeout;
5197 uint32_t dev_state;
5198
5199 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5200 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5201
5202 while (1) {
5203
5204 if (time_after_eq(jiffies, dev_init_timeout)) {
5205 ql_log(ql_log_warn, base_vha, 0xb06e,
5206 "Initialization TIMEOUT!\n");
5207 /* Init timeout. Disable further NIC Core
5208 * communication.
5209 */
5210 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5211 QLA8XXX_DEV_FAILED);
5212 ql_log(ql_log_info, base_vha, 0xb06f,
5213 "HW State: FAILED.\n");
5214 }
5215
5216 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5217 switch (dev_state) {
5218 case QLA8XXX_DEV_READY:
5219 if (ha->flags.nic_core_reset_owner)
5220 qla83xx_idc_audit(base_vha,
5221 IDC_AUDIT_COMPLETION);
5222 ha->flags.nic_core_reset_owner = 0;
5223 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5224 "Reset_owner reset by 0x%x.\n",
5225 ha->portnum);
5226 goto exit;
5227 case QLA8XXX_DEV_COLD:
5228 if (ha->flags.nic_core_reset_owner)
5229 rval = qla83xx_device_bootstrap(base_vha);
5230 else {
5231 /* Wait for AEN to change device-state */
5232 qla83xx_idc_unlock(base_vha, 0);
5233 msleep(1000);
5234 qla83xx_idc_lock(base_vha, 0);
5235 }
5236 break;
5237 case QLA8XXX_DEV_INITIALIZING:
5238 /* Wait for AEN to change device-state */
5239 qla83xx_idc_unlock(base_vha, 0);
5240 msleep(1000);
5241 qla83xx_idc_lock(base_vha, 0);
5242 break;
5243 case QLA8XXX_DEV_NEED_RESET:
5244 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5245 qla83xx_need_reset_handler(base_vha);
5246 else {
5247 /* Wait for AEN to change device-state */
5248 qla83xx_idc_unlock(base_vha, 0);
5249 msleep(1000);
5250 qla83xx_idc_lock(base_vha, 0);
5251 }
5252 /* reset timeout value after need reset handler */
5253 dev_init_timeout = jiffies +
5254 (ha->fcoe_dev_init_timeout * HZ);
5255 break;
5256 case QLA8XXX_DEV_NEED_QUIESCENT:
5257 /* XXX: DEBUG for now */
5258 qla83xx_idc_unlock(base_vha, 0);
5259 msleep(1000);
5260 qla83xx_idc_lock(base_vha, 0);
5261 break;
5262 case QLA8XXX_DEV_QUIESCENT:
5263 /* XXX: DEBUG for now */
5264 if (ha->flags.quiesce_owner)
5265 goto exit;
5266
5267 qla83xx_idc_unlock(base_vha, 0);
5268 msleep(1000);
5269 qla83xx_idc_lock(base_vha, 0);
5270 dev_init_timeout = jiffies +
5271 (ha->fcoe_dev_init_timeout * HZ);
5272 break;
5273 case QLA8XXX_DEV_FAILED:
5274 if (ha->flags.nic_core_reset_owner)
5275 qla83xx_idc_audit(base_vha,
5276 IDC_AUDIT_COMPLETION);
5277 ha->flags.nic_core_reset_owner = 0;
5278 __qla83xx_clear_drv_presence(base_vha);
5279 qla83xx_idc_unlock(base_vha, 0);
5280 qla8xxx_dev_failed_handler(base_vha);
5281 rval = QLA_FUNCTION_FAILED;
5282 qla83xx_idc_lock(base_vha, 0);
5283 goto exit;
5284 case QLA8XXX_BAD_VALUE:
5285 qla83xx_idc_unlock(base_vha, 0);
5286 msleep(1000);
5287 qla83xx_idc_lock(base_vha, 0);
5288 break;
5289 default:
5290 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5291 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5292 qla83xx_idc_unlock(base_vha, 0);
5293 qla8xxx_dev_failed_handler(base_vha);
5294 rval = QLA_FUNCTION_FAILED;
5295 qla83xx_idc_lock(base_vha, 0);
5296 goto exit;
5297 }
5298 }
5299
5300exit:
5301 return rval;
5302}
5303
f3ddac19
CD		 5304void
5305qla2x00_disable_board_on_pci_error(struct work_struct *work)
5306{
5307 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5308 board_disable);
5309 struct pci_dev *pdev = ha->pdev;
5310 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5311
726b8548
QT		 5312 /*
5313 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5314 * where it was set first.
5315 */
5316 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5317 return;
5318
f3ddac19
CD		 5319 ql_log(ql_log_warn, base_vha, 0x015b,
5320 "Disabling adapter.\n");
5321
726b8548
QT		 5322 qla2x00_wait_for_sess_deletion(base_vha);
5323
f3ddac19
CD		 5324 set_bit(UNLOADING, &base_vha->dpc_flags);
5325
5326 qla2x00_delete_all_vps(ha, base_vha);
5327
5328 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5329
5330 qla2x00_dfs_remove(base_vha);
5331
5332 qla84xx_put_chip(base_vha);
5333
5334 if (base_vha->timer_active)
5335 qla2x00_stop_timer(base_vha);
5336
5337 base_vha->flags.online = 0;
5338
5339 qla2x00_destroy_deferred_work(ha);
5340
5341 /*
5342 * Do not try to stop beacon blink as it will issue a mailbox
5343 * command.
5344 */
5345 qla2x00_free_sysfs_attr(base_vha, false);
5346
5347 fc_remove_host(base_vha->host);
5348
5349 scsi_remove_host(base_vha->host);
5350
5351 base_vha->flags.init_done = 0;
5352 qla25xx_delete_queues(base_vha);
f3ddac19 5353 qla2x00_free_fcports(base_vha);
093df737 5354 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5355 qla2x00_mem_free(ha);
5356 qla82xx_md_free(base_vha);
5357 qla2x00_free_queues(ha);
5358
f3ddac19
CD		 5359 qla2x00_unmap_iobases(ha);
5360
5361 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5362 pci_disable_pcie_error_reporting(pdev);
5363 pci_disable_device(pdev);
f3ddac19 5364
beb9e315
JL		 5365 /*
5366 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5367 */
f3ddac19
CD		 5368}
5369
1da177e4
LT		 5370/**************************************************************************
5371* qla2x00_do_dpc
5372* This kernel thread is a task that is schedule by the interrupt handler
5373* to perform the background processing for interrupts.
5374*
5375* Notes:
5376* This task always run in the context of a kernel thread. It
5377* is kick-off by the driver's detect code and starts up
5378* up one per adapter. It immediately goes to sleep and waits for
5379* some fibre event. When either the interrupt handler or
5380* the timer routine detects a event it will one of the task
5381* bits then wake us up.
5382**************************************************************************/
5383static int
5384qla2x00_do_dpc(void *data)
5385{
e315cd28
AC		 5386 scsi_qla_host_t *base_vha;
5387 struct qla_hw_data *ha;
d7459527
MH		 5388 uint32_t online;
5389 struct qla_qpair *qpair;
1da177e4 5390
e315cd28
AC		 5391 ha = (struct qla_hw_data *)data;
5392 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5393
8698a745 5394 set_user_nice(current, MIN_NICE);
1da177e4 5395
563585ec 5396 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5397 while (!kthread_should_stop()) {
7c3df132
SK		 5398 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5399 "DPC handler sleeping.\n");
1da177e4 5400
39a11240 5401 schedule();
1da177e4 5402
c142caf0
AV		 5403 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5404 goto end_loop;
1da177e4 5405
85880801 5406 if (ha->flags.eeh_busy) {
7c3df132
SK		 5407 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5408 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5409 goto end_loop;
85880801
AV		 5410 }
5411
1da177e4
LT		 5412 ha->dpc_active = 1;
5413
5f28d2d7
SK		 5414 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5415 "DPC handler waking up, dpc_flags=0x%lx.\n",
5416 base_vha->dpc_flags);
1da177e4 5417
a29b3dd7
JC		 5418 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5419 break;
5420
e315cd28 5421 qla2x00_do_work(base_vha);
0971de7f 5422
7ec0effd
AD		 5423 if (IS_P3P_TYPE(ha)) {
5424 if (IS_QLA8044(ha)) {
5425 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5426 &base_vha->dpc_flags)) {
5427 qla8044_idc_lock(ha);
5428 qla8044_wr_direct(base_vha,
5429 QLA8044_CRB_DEV_STATE_INDEX,
5430 QLA8XXX_DEV_FAILED);
5431 qla8044_idc_unlock(ha);
5432 ql_log(ql_log_info, base_vha, 0x4004,
5433 "HW State: FAILED.\n");
5434 qla8044_device_state_handler(base_vha);
5435 continue;
5436 }
5437
5438 } else {
5439 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5440 &base_vha->dpc_flags)) {
5441 qla82xx_idc_lock(ha);
5442 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5443 QLA8XXX_DEV_FAILED);
5444 qla82xx_idc_unlock(ha);
5445 ql_log(ql_log_info, base_vha, 0x0151,
5446 "HW State: FAILED.\n");
5447 qla82xx_device_state_handler(base_vha);
5448 continue;
5449 }
a9083016
GM		 5450 }
5451
5452 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5453 &base_vha->dpc_flags)) {
5454
7c3df132
SK		 5455 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5456 "FCoE context reset scheduled.\n");
a9083016
GM		 5457 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5458 &base_vha->dpc_flags))) {
5459 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5460 /* FCoE-ctx reset failed.
5461 * Escalate to chip-reset
5462 */
5463 set_bit(ISP_ABORT_NEEDED,
5464 &base_vha->dpc_flags);
5465 }
5466 clear_bit(ABORT_ISP_ACTIVE,
5467 &base_vha->dpc_flags);
5468 }
5469
7c3df132
SK		 5470 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5471 "FCoE context reset end.\n");
a9083016 5472 }
8ae6d9c7
GM		 5473 } else if (IS_QLAFX00(ha)) {
5474 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5475 &base_vha->dpc_flags)) {
5476 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5477 "Firmware Reset Recovery\n");
5478 if (qlafx00_reset_initialize(base_vha)) {
5479 /* Failed. Abort isp later. */
5480 if (!test_bit(UNLOADING,
f92f82d6 5481 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5482 set_bit(ISP_UNRECOVERABLE,
5483 &base_vha->dpc_flags);
5484 ql_dbg(ql_dbg_dpc, base_vha,
5485 0x4021,
5486 "Reset Recovery Failed\n");
f92f82d6 5487 }
8ae6d9c7
GM		 5488 }
5489 }
5490
5491 if (test_and_clear_bit(FX00_TARGET_SCAN,
5492 &base_vha->dpc_flags)) {
5493 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5494 "ISPFx00 Target Scan scheduled\n");
5495 if (qlafx00_rescan_isp(base_vha)) {
5496 if (!test_bit(UNLOADING,
5497 &base_vha->dpc_flags))
5498 set_bit(ISP_UNRECOVERABLE,
5499 &base_vha->dpc_flags);
5500 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5501 "ISPFx00 Target Scan Failed\n");
5502 }
5503 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5504 "ISPFx00 Target Scan End\n");
5505 }
e8f5e95d
AB		 5506 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5507 &base_vha->dpc_flags)) {
5508 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5509 "ISPFx00 Host Info resend scheduled\n");
5510 qlafx00_fx_disc(base_vha,
5511 &base_vha->hw->mr.fcport,
5512 FXDISC_REG_HOST_INFO);
5513 }
a9083016
GM		 5514 }
5515
e315cd28
AC		 5516 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5517 &base_vha->dpc_flags)) {
1da177e4 5518
7c3df132
SK		 5519 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5520 "ISP abort scheduled.\n");
1da177e4 5521 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5522 &base_vha->dpc_flags))) {
1da177e4 5523
a9083016 5524 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5525 /* failed. retry later */
5526 set_bit(ISP_ABORT_NEEDED,
e315cd28 5527 &base_vha->dpc_flags);
99363ef8 5528 }
e315cd28
AC		 5529 clear_bit(ABORT_ISP_ACTIVE,
5530 &base_vha->dpc_flags);
99363ef8
SJ		 5531 }
5532
7c3df132
SK		 5533 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5534 "ISP abort end.\n");
1da177e4
LT		 5535 }
5536
a394aac8
DJ		 5537 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5538 &base_vha->dpc_flags)) {
e315cd28 5539 qla2x00_update_fcports(base_vha);
c9c5ced9 5540 }
d97994dc 5541
8ae6d9c7
GM		 5542 if (IS_QLAFX00(ha))
5543 goto loop_resync_check;
5544
579d12b5 5545 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5546 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5547 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5548 if (IS_P3P_TYPE(ha)) {
5549 if (IS_QLA82XX(ha))
5550 qla82xx_device_state_handler(base_vha);
5551 if (IS_QLA8044(ha))
5552 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5553 clear_bit(ISP_QUIESCE_NEEDED,
5554 &base_vha->dpc_flags);
5555 if (!ha->flags.quiesce_owner) {
5556 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5557 if (IS_QLA82XX(ha)) {
5558 qla82xx_idc_lock(ha);
5559 qla82xx_clear_qsnt_ready(
5560 base_vha);
5561 qla82xx_idc_unlock(ha);
5562 } else if (IS_QLA8044(ha)) {
5563 qla8044_idc_lock(ha);
5564 qla8044_clear_qsnt_ready(
5565 base_vha);
5566 qla8044_idc_unlock(ha);
5567 }
8fcd6b8b
CD		 5568 }
5569 } else {
5570 clear_bit(ISP_QUIESCE_NEEDED,
5571 &base_vha->dpc_flags);
5572 qla2x00_quiesce_io(base_vha);
579d12b5 5573 }
7c3df132
SK		 5574 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5575 "Quiescence mode end.\n");
579d12b5
SK		 5576 }
5577
e315cd28 5578 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5579 &base_vha->dpc_flags) &&
e315cd28 5580 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5581
7c3df132
SK		 5582 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5583 "Reset marker scheduled.\n");
e315cd28
AC		 5584 qla2x00_rst_aen(base_vha);
5585 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5586 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5587 "Reset marker end.\n");
1da177e4
LT		 5588 }
5589
5590 /* Retry each device up to login retry count */
e315cd28
AC		 5591 if ((test_and_clear_bit(RELOGIN_NEEDED,
5592 &base_vha->dpc_flags)) &&
5593 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5594 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5595
7c3df132
SK		 5596 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5597 "Relogin scheduled.\n");
e315cd28 5598 qla2x00_relogin(base_vha);
7c3df132
SK		 5599 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5600 "Relogin end.\n");
1da177e4 5601 }
8ae6d9c7 5602loop_resync_check:
e315cd28 5603 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5604 &base_vha->dpc_flags)) {
1da177e4 5605
7c3df132
SK		 5606 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5607 "Loop resync scheduled.\n");
1da177e4
LT		 5608
5609 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5610 &base_vha->dpc_flags))) {
1da177e4 5611
52c82823 5612 qla2x00_loop_resync(base_vha);
1da177e4 5613
e315cd28
AC		 5614 clear_bit(LOOP_RESYNC_ACTIVE,
5615 &base_vha->dpc_flags);
1da177e4
LT		 5616 }
5617
7c3df132
SK		 5618 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5619 "Loop resync end.\n");
1da177e4
LT		 5620 }
5621
8ae6d9c7
GM		 5622 if (IS_QLAFX00(ha))
5623 goto intr_on_check;
5624
e315cd28
AC		 5625 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5626 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5627 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5628 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5629 }
5630
8ae6d9c7 5631intr_on_check:
1da177e4 5632 if (!ha->interrupts_on)
fd34f556 5633 ha->isp_ops->enable_intrs(ha);
1da177e4 5634
e315cd28 5635 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5636 &base_vha->dpc_flags)) {
5637 if (ha->beacon_blink_led == 1)
5638 ha->isp_ops->beacon_blink(base_vha);
5639 }
f6df144c 5640
d7459527
MH		 5641 /* qpair online check */
5642 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5643 &base_vha->dpc_flags)) {
5644 if (ha->flags.eeh_busy ||
5645 ha->flags.pci_channel_io_perm_failure)
5646 online = 0;
5647 else
5648 online = 1;
5649
5650 mutex_lock(&ha->mq_lock);
5651 list_for_each_entry(qpair, &base_vha->qp_list,
5652 qp_list_elem)
5653 qpair->online = online;
5654 mutex_unlock(&ha->mq_lock);
5655 }
5656
8ae6d9c7
GM		 5657 if (!IS_QLAFX00(ha))
5658 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5659
1da177e4 5660 ha->dpc_active = 0;
c142caf0 5661end_loop:
563585ec 5662 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5663 } /* End of while(1) */
563585ec 5664 __set_current_state(TASK_RUNNING);
1da177e4 5665
7c3df132
SK		 5666 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5667 "DPC handler exiting.\n");
1da177e4
LT		 5668
5669 /*
5670 * Make sure that nobody tries to wake us up again.
5671 */
1da177e4
LT		 5672 ha->dpc_active = 0;
5673
ac280b67
AV		 5674 /* Cleanup any residual CTX SRBs. */
5675 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5676
39a11240
CH		 5677 return 0;
5678}
5679
5680void
e315cd28 5681qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5682{
e315cd28 5683 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5684 struct task_struct *t = ha->dpc_thread;
5685
e315cd28 5686 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5687 wake_up_process(t);
1da177e4
LT		 5688}
5689
1da177e4
LT		 5690/*
5691* qla2x00_rst_aen
5692* Processes asynchronous reset.
5693*
5694* Input:
5695* ha = adapter block pointer.
5696*/
5697static void
e315cd28 5698qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5699{
e315cd28
AC		 5700 if (vha->flags.online && !vha->flags.reset_active &&
5701 !atomic_read(&vha->loop_down_timer) &&
5702 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5703 do {
e315cd28 5704 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5705
5706 /*
5707 * Issue marker command only when we are going to start
5708 * the I/O.
5709 */
e315cd28
AC		 5710 vha->marker_needed = 1;
5711 } while (!atomic_read(&vha->loop_down_timer) &&
5712 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5713 }
5714}
5715
1da177e4
LT		 5716/**************************************************************************
5717* qla2x00_timer
5718*
5719* Description:
5720* One second timer
5721*
5722* Context: Interrupt
5723***************************************************************************/
2c3dfe3f 5724void
e315cd28 5725qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5726{
1da177e4 5727 unsigned long cpu_flags = 0;
1da177e4
LT		 5728 int start_dpc = 0;
5729 int index;
5730 srb_t *sp;
85880801 5731 uint16_t w;
e315cd28 5732 struct qla_hw_data *ha = vha->hw;
73208dfd 5733 struct req_que *req;
85880801 5734
a5b36321 5735 if (ha->flags.eeh_busy) {
7c3df132
SK		 5736 ql_dbg(ql_dbg_timer, vha, 0x6000,
5737 "EEH = %d, restarting timer.\n",
5738 ha->flags.eeh_busy);
a5b36321
LC		 5739 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5740 return;
5741 }
5742
f3ddac19
CD		 5743 /*
5744 * Hardware read to raise pending EEH errors during mailbox waits. If
5745 * the read returns -1 then disable the board.
5746 */
5747 if (!pci_channel_offline(ha->pdev)) {
85880801 5748 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5749 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5750 }
1da177e4 5751
cefcaba6 5752 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5753 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5754 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5755 start_dpc++;
7ec0effd
AD		 5756 if (IS_QLA82XX(ha))
5757 qla82xx_watchdog(vha);
5758 else if (IS_QLA8044(ha))
5759 qla8044_watchdog(vha);
579d12b5
SK		 5760 }
5761
8ae6d9c7
GM		 5762 if (!vha->vp_idx && IS_QLAFX00(ha))
5763 qlafx00_timer_routine(vha);
5764
1da177e4 5765 /* Loop down handler. */
e315cd28 5766 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5767 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5768 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5769 && vha->flags.online) {
1da177e4 5770
e315cd28
AC		 5771 if (atomic_read(&vha->loop_down_timer) ==
5772 vha->loop_down_abort_time) {
1da177e4 5773
7c3df132
SK		 5774 ql_log(ql_log_info, vha, 0x6008,
5775 "Loop down - aborting the queues before time expires.\n");
1da177e4 5776
e315cd28
AC		 5777 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5778 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5779
f08b7251
AV		 5780 /*
5781 * Schedule an ISP abort to return any FCP2-device
5782 * commands.
5783 */
2c3dfe3f 5784 /* NPIV - scan physical port only */
e315cd28 5785 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5786 spin_lock_irqsave(&ha->hardware_lock,
5787 cpu_flags);
73208dfd 5788 req = ha->req_q_map[0];
2c3dfe3f 5789 for (index = 1;
8d93f550 5790 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5791 index++) {
5792 fc_port_t *sfcp;
5793
e315cd28 5794 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5795 if (!sp)
5796 continue;
9ba56b95 5797 if (sp->type != SRB_SCSI_CMD)
cf53b069 5798 continue;
2c3dfe3f 5799 sfcp = sp->fcport;
f08b7251 5800 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5801 continue;
bdf79621 5802
8f7daead
GM		 5803 if (IS_QLA82XX(ha))
5804 set_bit(FCOE_CTX_RESET_NEEDED,
5805 &vha->dpc_flags);
5806 else
5807 set_bit(ISP_ABORT_NEEDED,
e315cd28 5808 &vha->dpc_flags);
2c3dfe3f
SJ		 5809 break;
5810 }
5811 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5812 cpu_flags);
1da177e4 5813 }
1da177e4
LT		 5814 start_dpc++;
5815 }
5816
5817 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5818 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5819 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5820 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5821 "Loop down - aborting ISP.\n");
5822
8f7daead
GM		 5823 if (IS_QLA82XX(ha))
5824 set_bit(FCOE_CTX_RESET_NEEDED,
5825 &vha->dpc_flags);
5826 else
5827 set_bit(ISP_ABORT_NEEDED,
5828 &vha->dpc_flags);
1da177e4
LT		 5829 }
5830 }
7c3df132
SK		 5831 ql_dbg(ql_dbg_timer, vha, 0x600a,
5832 "Loop down - seconds remaining %d.\n",
5833 atomic_read(&vha->loop_down_timer));
1da177e4 5834 }
cefcaba6
SK		 5835 /* Check if beacon LED needs to be blinked for physical host only */
5836 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5837 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5838 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5839 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5840 start_dpc++;
5841 }
f6df144c
AV		 5842 }
5843
550bf57d 5844 /* Process any deferred work. */
e315cd28 5845 if (!list_empty(&vha->work_list))
550bf57d
AV		 5846 start_dpc++;
5847
1da177e4 5848 /* Schedule the DPC routine if needed */
e315cd28
AC		 5849 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5850 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5851 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5852 start_dpc ||
e315cd28
AC		 5853 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5854 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5855 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5856 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5857 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5858 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5859 ql_dbg(ql_dbg_timer, vha, 0x600b,
5860 "isp_abort_needed=%d loop_resync_needed=%d "
5861 "fcport_update_needed=%d start_dpc=%d "
5862 "reset_marker_needed=%d",
5863 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5864 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5865 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5866 start_dpc,
5867 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5868 ql_dbg(ql_dbg_timer, vha, 0x600c,
5869 "beacon_blink_needed=%d isp_unrecoverable=%d "
5870 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5871 "relogin_needed=%d.\n",
7c3df132
SK		 5872 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5873 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5874 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5875 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5876 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5877 qla2xxx_wake_dpc(vha);
7c3df132 5878 }
1da177e4 5879
e315cd28 5880 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5881}
5882
5433383e
AV		 5883/* Firmware interface routines. */
5884
f73cb695 5885#define FW_BLOBS 11
5433383e
AV		 5886#define FW_ISP21XX 0
5887#define FW_ISP22XX 1
5888#define FW_ISP2300 2
5889#define FW_ISP2322 3
48c02fde 5890#define FW_ISP24XX 4
c3a2f0df 5891#define FW_ISP25XX 5
3a03eb79 5892#define FW_ISP81XX 6
a9083016 5893#define FW_ISP82XX 7
6246b8a1
GM		 5894#define FW_ISP2031 8
5895#define FW_ISP8031 9
2c5bbbb2 5896#define FW_ISP27XX 10
5433383e 5897
bb8ee499
AV		 5898#define FW_FILE_ISP21XX "ql2100_fw.bin"
5899#define FW_FILE_ISP22XX "ql2200_fw.bin"
5900#define FW_FILE_ISP2300 "ql2300_fw.bin"
5901#define FW_FILE_ISP2322 "ql2322_fw.bin"
5902#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5903#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5904#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5905#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5906#define FW_FILE_ISP2031 "ql2600_fw.bin"
5907#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5908#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5909
bb8ee499 5910
e1e82b6f 5911static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5912
5913static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5914 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5915 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5916 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5917 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5918 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5919 { .name = FW_FILE_ISP25XX, },
3a03eb79 5920 { .name = FW_FILE_ISP81XX, },
a9083016 5921 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5922 { .name = FW_FILE_ISP2031, },
5923 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5924 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5925};
5926
5927struct fw_blob *
e315cd28 5928qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5929{
e315cd28 5930 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5931 struct fw_blob *blob;
5932
5433383e
AV		 5933 if (IS_QLA2100(ha)) {
5934 blob = &qla_fw_blobs[FW_ISP21XX];
5935 } else if (IS_QLA2200(ha)) {
5936 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5937 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5938 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5939 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5940 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5941 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5942 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5943 } else if (IS_QLA25XX(ha)) {
5944 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5945 } else if (IS_QLA81XX(ha)) {
5946 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5947 } else if (IS_QLA82XX(ha)) {
5948 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5949 } else if (IS_QLA2031(ha)) {
5950 blob = &qla_fw_blobs[FW_ISP2031];
5951 } else if (IS_QLA8031(ha)) {
5952 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5953 } else if (IS_QLA27XX(ha)) {
5954 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5955 } else {
5956 return NULL;
5433383e
AV		 5957 }
5958
e1e82b6f 5959 mutex_lock(&qla_fw_lock);
5433383e
AV		 5960 if (blob->fw)
5961 goto out;
5962
5963 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5964 ql_log(ql_log_warn, vha, 0x0063,
5965 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5966 blob->fw = NULL;
5967 blob = NULL;
5968 goto out;
5969 }
5970
5971out:
e1e82b6f 5972 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5973 return blob;
5974}
5975
5976static void
5977qla2x00_release_firmware(void)
5978{
5979 int idx;
5980
e1e82b6f 5981 mutex_lock(&qla_fw_lock);
5433383e 5982 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5983 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5984 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5985}
5986
14e660e6
SJ		 5987static pci_ers_result_t
5988qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5989{
85880801
AV		 5990 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5991 struct qla_hw_data *ha = vha->hw;
5992
7c3df132
SK		 5993 ql_dbg(ql_dbg_aer, vha, 0x9000,
5994 "PCI error detected, state %x.\n", state);
b9b12f73 5995
14e660e6
SJ		 5996 switch (state) {
5997 case pci_channel_io_normal:
85880801 5998 ha->flags.eeh_busy = 0;
d7459527
MH		 5999 if (ql2xmqsupport) {
6000 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6001 qla2xxx_wake_dpc(vha);
6002 }
14e660e6
SJ		 6003 return PCI_ERS_RESULT_CAN_RECOVER;
6004 case pci_channel_io_frozen:
85880801 6005 ha->flags.eeh_busy = 1;
a5b36321
LC		 6006 /* For ISP82XX complete any pending mailbox cmd */
6007 if (IS_QLA82XX(ha)) {
7190575f 6008 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6009 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6010 qla82xx_clear_pending_mbx(vha);
a5b36321 6011 }
90a86fc0 6012 qla2x00_free_irqs(vha);
14e660e6 6013 pci_disable_device(pdev);
bddd2d65
LC		 6014 /* Return back all IOs */
6015 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6016 if (ql2xmqsupport) {
6017 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6018 qla2xxx_wake_dpc(vha);
6019 }
14e660e6
SJ		 6020 return PCI_ERS_RESULT_NEED_RESET;
6021 case pci_channel_io_perm_failure:
85880801
AV		 6022 ha->flags.pci_channel_io_perm_failure = 1;
6023 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6024 if (ql2xmqsupport) {
6025 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6026 qla2xxx_wake_dpc(vha);
6027 }
14e660e6
SJ		 6028 return PCI_ERS_RESULT_DISCONNECT;
6029 }
6030 return PCI_ERS_RESULT_NEED_RESET;
6031}
6032
6033static pci_ers_result_t
6034qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6035{
6036 int risc_paused = 0;
6037 uint32_t stat;
6038 unsigned long flags;
e315cd28
AC		 6039 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6040 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6041 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6042 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6043
bcc5b6d3
SK		 6044 if (IS_QLA82XX(ha))
6045 return PCI_ERS_RESULT_RECOVERED;
6046
14e660e6
SJ		 6047 spin_lock_irqsave(&ha->hardware_lock, flags);
6048 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6049 stat = RD_REG_DWORD(&reg->hccr);
6050 if (stat & HCCR_RISC_PAUSE)
6051 risc_paused = 1;
6052 } else if (IS_QLA23XX(ha)) {
6053 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6054 if (stat & HSR_RISC_PAUSED)
6055 risc_paused = 1;
6056 } else if (IS_FWI2_CAPABLE(ha)) {
6057 stat = RD_REG_DWORD(&reg24->host_status);
6058 if (stat & HSRX_RISC_PAUSED)
6059 risc_paused = 1;
6060 }
6061 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6062
6063 if (risc_paused) {
7c3df132
SK		 6064 ql_log(ql_log_info, base_vha, 0x9003,
6065 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6066 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6067
6068 return PCI_ERS_RESULT_NEED_RESET;
6069 } else
6070 return PCI_ERS_RESULT_RECOVERED;
6071}
6072
fa492630
SK		 6073static uint32_t
6074qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6075{
6076 uint32_t rval = QLA_FUNCTION_FAILED;
6077 uint32_t drv_active = 0;
6078 struct qla_hw_data *ha = base_vha->hw;
6079 int fn;
6080 struct pci_dev *other_pdev = NULL;
6081
7c3df132
SK		 6082 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6083 "Entered %s.\n", __func__);
a5b36321
LC		 6084
6085 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6086
6087 if (base_vha->flags.online) {
6088 /* Abort all outstanding commands,
6089 * so as to be requeued later */
6090 qla2x00_abort_isp_cleanup(base_vha);
6091 }
6092
6093
6094 fn = PCI_FUNC(ha->pdev->devfn);
6095 while (fn > 0) {
6096 fn--;
7c3df132
SK		 6097 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6098 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6099 other_pdev =
6100 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6101 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6102 fn));
6103
6104 if (!other_pdev)
6105 continue;
6106 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6107 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6108 "Found PCI func available and enable at 0x%x.\n",
6109 fn);
a5b36321
LC		 6110 pci_dev_put(other_pdev);
6111 break;
6112 }
6113 pci_dev_put(other_pdev);
6114 }
6115
6116 if (!fn) {
6117 /* Reset owner */
7c3df132
SK		 6118 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6119 "This devfn is reset owner = 0x%x.\n",
6120 ha->pdev->devfn);
a5b36321
LC		 6121 qla82xx_idc_lock(ha);
6122
6123 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6124 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6125
6126 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6127 QLA82XX_IDC_VERSION);
6128
6129 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6130 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6131 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6132
6133 qla82xx_idc_unlock(ha);
6134 /* Reset if device is not already reset
6135 * drv_active would be 0 if a reset has already been done
6136 */
6137 if (drv_active)
6138 rval = qla82xx_start_firmware(base_vha);
6139 else
6140 rval = QLA_SUCCESS;
6141 qla82xx_idc_lock(ha);
6142
6143 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6144 ql_log(ql_log_info, base_vha, 0x900b,
6145 "HW State: FAILED.\n");
a5b36321
LC		 6146 qla82xx_clear_drv_active(ha);
6147 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6148 QLA8XXX_DEV_FAILED);
a5b36321 6149 } else {
7c3df132
SK		 6150 ql_log(ql_log_info, base_vha, 0x900c,
6151 "HW State: READY.\n");
a5b36321 6152 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6153 QLA8XXX_DEV_READY);
a5b36321 6154 qla82xx_idc_unlock(ha);
7190575f 6155 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6156 rval = qla82xx_restart_isp(base_vha);
6157 qla82xx_idc_lock(ha);
6158 /* Clear driver state register */
6159 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6160 qla82xx_set_drv_active(base_vha);
6161 }
6162 qla82xx_idc_unlock(ha);
6163 } else {
7c3df132
SK		 6164 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6165 "This devfn is not reset owner = 0x%x.\n",
6166 ha->pdev->devfn);
a5b36321 6167 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6168 QLA8XXX_DEV_READY)) {
7190575f 6169 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6170 rval = qla82xx_restart_isp(base_vha);
6171 qla82xx_idc_lock(ha);
6172 qla82xx_set_drv_active(base_vha);
6173 qla82xx_idc_unlock(ha);
6174 }
6175 }
6176 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6177
6178 return rval;
6179}
6180
14e660e6
SJ		 6181static pci_ers_result_t
6182qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6183{
6184 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6185 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6186 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6187 struct rsp_que *rsp;
6188 int rc, retries = 10;
09483916 6189
7c3df132
SK		 6190 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6191 "Slot Reset.\n");
85880801 6192
90a86fc0
JC		 6193 /* Workaround: qla2xxx driver which access hardware earlier
6194 * needs error state to be pci_channel_io_online.
6195 * Otherwise mailbox command timesout.
6196 */
6197 pdev->error_state = pci_channel_io_normal;
6198
6199 pci_restore_state(pdev);
6200
8c1496bd
RL		 6201 /* pci_restore_state() clears the saved_state flag of the device
6202 * save restored state which resets saved_state flag
6203 */
6204 pci_save_state(pdev);
6205
09483916
BH		 6206 if (ha->mem_only)
6207 rc = pci_enable_device_mem(pdev);
6208 else
6209 rc = pci_enable_device(pdev);
14e660e6 6210
09483916 6211 if (rc) {
7c3df132 6212 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6213 "Can't re-enable PCI device after reset.\n");
a5b36321 6214 goto exit_slot_reset;
14e660e6 6215 }
14e660e6 6216
90a86fc0
JC		 6217 rsp = ha->rsp_q_map[0];
6218 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6219 goto exit_slot_reset;
90a86fc0 6220
e315cd28 6221 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6222 goto exit_slot_reset;
6223
6224 if (IS_QLA82XX(ha)) {
6225 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6226 ret = PCI_ERS_RESULT_RECOVERED;
6227 goto exit_slot_reset;
6228 } else
6229 goto exit_slot_reset;
6230 }
14e660e6 6231
90a86fc0
JC		 6232 while (ha->flags.mbox_busy && retries--)
6233 msleep(1000);
85880801 6234
e315cd28 6235 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6236 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6237 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6238 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6239
90a86fc0 6240
a5b36321 6241exit_slot_reset:
7c3df132
SK		 6242 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6243 "slot_reset return %x.\n", ret);
85880801 6244
14e660e6
SJ		 6245 return ret;
6246}
6247
6248static void
6249qla2xxx_pci_resume(struct pci_dev *pdev)
6250{
e315cd28
AC		 6251 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6252 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6253 int ret;
6254
7c3df132
SK		 6255 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6256 "pci_resume.\n");
85880801 6257
e315cd28 6258 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6259 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6260 ql_log(ql_log_fatal, base_vha, 0x9002,
6261 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6262 }
85880801 6263
3e46f031
LC		 6264 pci_cleanup_aer_uncorrect_error_status(pdev);
6265
85880801 6266 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6267}
6268
2d5a4c34
HM		 6269static void
6270qla83xx_disable_laser(scsi_qla_host_t *vha)
6271{
6272 uint32_t reg, data, fn;
6273 struct qla_hw_data *ha = vha->hw;
6274 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6275
6276 /* pci func #/port # */
6277 ql_dbg(ql_dbg_init, vha, 0x004b,
6278 "Disabling Laser for hba: %p\n", vha);
6279
6280 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6281 (BIT_15|BIT_14|BIT_13|BIT_12));
6282
6283 fn = (fn >> 12);
6284
6285 if (fn & 1)
6286 reg = PORT_1_2031;
6287 else
6288 reg = PORT_0_2031;
6289
6290 data = LASER_OFF_2031;
6291
6292 qla83xx_wr_reg(vha, reg, data);
6293}
6294
5601236b
MH		 6295static int qla2xxx_map_queues(struct Scsi_Host *shost)
6296{
6297 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6298
6299 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6300}
6301
a55b2d21 6302static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6303 .error_detected = qla2xxx_pci_error_detected,
6304 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6305 .slot_reset = qla2xxx_pci_slot_reset,
6306 .resume = qla2xxx_pci_resume,
6307};
6308
5433383e 6309static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6310 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6311 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6312 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6313 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6314 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6315 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6332 { 0 },
6333};
6334MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6335
fca29703 6336static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6337 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6338 .driver = {
6339 .owner = THIS_MODULE,
6340 },
fca29703 6341 .id_table = qla2xxx_pci_tbl,
7ee61397 6342 .probe = qla2x00_probe_one,
4c993f76 6343 .remove = qla2x00_remove_one,
e30d1756 6344 .shutdown = qla2x00_shutdown,
14e660e6 6345 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6346};
6347
75ef9de1 6348static const struct file_operations apidev_fops = {
6a03b4cd 6349 .owner = THIS_MODULE,
6038f373 6350 .llseek = noop_llseek,
6a03b4cd
HZ		 6351};
6352
1da177e4
LT		 6353/**
6354 * qla2x00_module_init - Module initialization.
6355 **/
6356static int __init
6357qla2x00_module_init(void)
6358{
fca29703
AV		 6359 int ret = 0;
6360
1da177e4 6361 /* Allocate cache for SRBs. */
354d6b21 6362 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6363 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6364 if (srb_cachep == NULL) {
7c3df132
SK		 6365 ql_log(ql_log_fatal, NULL, 0x0001,
6366 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6367 return -ENOMEM;
6368 }
6369
2d70c103
NB		 6370 /* Initialize target kmem_cache and mem_pools */
6371 ret = qlt_init();
6372 if (ret < 0) {
6373 kmem_cache_destroy(srb_cachep);
6374 return ret;
6375 } else if (ret > 0) {
6376 /*
6377 * If initiator mode is explictly disabled by qlt_init(),
6378 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6379 * performing scsi_scan_target() during LOOP UP event.
6380 */
6381 qla2xxx_transport_functions.disable_target_scan = 1;
6382 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6383 }
6384
1da177e4
LT		 6385 /* Derive version string. */
6386 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6387 if (ql2xextended_error_logging)
0181944f
AV		 6388 strcat(qla2x00_version_str, "-debug");
6389
1c97a12a
AV		 6390 qla2xxx_transport_template =
6391 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6392 if (!qla2xxx_transport_template) {
6393 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6394 ql_log(ql_log_fatal, NULL, 0x0002,
6395 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6396 qlt_exit();
1da177e4 6397 return -ENODEV;
2c3dfe3f 6398 }
6a03b4cd
HZ		 6399
6400 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6401 if (apidev_major < 0) {
7c3df132
SK		 6402 ql_log(ql_log_fatal, NULL, 0x0003,
6403 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6404 }
6405
2c3dfe3f
SJ		 6406 qla2xxx_transport_vport_template =
6407 fc_attach_transport(&qla2xxx_transport_vport_functions);
6408 if (!qla2xxx_transport_vport_template) {
6409 kmem_cache_destroy(srb_cachep);
2d70c103 6410 qlt_exit();
2c3dfe3f 6411 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6412 ql_log(ql_log_fatal, NULL, 0x0004,
6413 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6414 return -ENODEV;
2c3dfe3f 6415 }
7c3df132
SK		 6416 ql_log(ql_log_info, NULL, 0x0005,
6417 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6418 qla2x00_version_str);
7ee61397 6419 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6420 if (ret) {
6421 kmem_cache_destroy(srb_cachep);
2d70c103 6422 qlt_exit();
fca29703 6423 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6424 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6425 ql_log(ql_log_fatal, NULL, 0x0006,
6426 "pci_register_driver failed...ret=%d Failing load!.\n",
6427 ret);
fca29703
AV		 6428 }
6429 return ret;
1da177e4
LT		 6430}
6431
6432/**
6433 * qla2x00_module_exit - Module cleanup.
6434 **/
6435static void __exit
6436qla2x00_module_exit(void)
6437{
6a03b4cd 6438 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6439 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6440 qla2x00_release_firmware();
354d6b21 6441 kmem_cache_destroy(srb_cachep);
2d70c103 6442 qlt_exit();
a9083016
GM		 6443 if (ctx_cachep)
6444 kmem_cache_destroy(ctx_cachep);
1da177e4 6445 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6446 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6447}
6448
6449module_init(qla2x00_module_init);
6450module_exit(qla2x00_module_exit);
6451
6452MODULE_AUTHOR("QLogic Corporation");
6453MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6454MODULE_LICENSE("GPL");
6455MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6456MODULE_FIRMWARE(FW_FILE_ISP21XX);
6457MODULE_FIRMWARE(FW_FILE_ISP22XX);
6458MODULE_FIRMWARE(FW_FILE_ISP2300);
6459MODULE_FIRMWARE(FW_FILE_ISP2322);
6460MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6461MODULE_FIRMWARE(FW_FILE_ISP25XX);
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