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[SCSI] qla2xxx: Fix qla24xx revision check while enabling interrupts.
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16
17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
22/*
23 * Driver version
24 */
25char qla2x00_version_str[40];
26
6a03b4cd
HZ		 27static int apidev_major;
28
1da177e4
LT		 29/*
30 * SRB allocation cache
31 */
e18b890b 32static struct kmem_cache *srb_cachep;
1da177e4 33
a9083016
GM		 34/*
35 * CT6 CTX allocation cache
36 */
37static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 38/*
39 * error level for logging
40 */
41int ql_errlev = ql_log_all;
a9083016 42
1da177e4 43int ql2xlogintimeout = 20;
f2019cb1 44module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 45MODULE_PARM_DESC(ql2xlogintimeout,
46 "Login timeout value in seconds.");
47
a7b61842 48int qlport_down_retry;
f2019cb1 49module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 50MODULE_PARM_DESC(qlport_down_retry,
900d9f98 51 "Maximum number of command retries to a port that returns "
1da177e4
LT		 52 "a PORT-DOWN status.");
53
1da177e4
LT		 54int ql2xplogiabsentdevice;
55module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
56MODULE_PARM_DESC(ql2xplogiabsentdevice,
57 "Option to enable PLOGI to devices that are not present after "
900d9f98 58 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 59 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
60
1da177e4 61int ql2xloginretrycount = 0;
f2019cb1 62module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 63MODULE_PARM_DESC(ql2xloginretrycount,
64 "Specify an alternate value for the NVRAM login retry count.");
65
a7a167bf 66int ql2xallocfwdump = 1;
f2019cb1 67module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 68MODULE_PARM_DESC(ql2xallocfwdump,
69 "Option to enable allocation of memory for a firmware dump "
70 "during HBA initialization. Memory allocation requirements "
71 "vary by ISP type. Default is 1 - allocate memory.");
72
11010fec 73int ql2xextended_error_logging;
27d94035 74module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 75MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 76 "Option to enable extended error logging,\n"
77 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
78 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
79 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
80 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
81 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
82 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
83 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
84 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
85 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
86 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 87
a9083016 88int ql2xshiftctondsd = 6;
f2019cb1 89module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 90MODULE_PARM_DESC(ql2xshiftctondsd,
91 "Set to control shifting of command type processing "
92 "based on total number of SG elements.");
93
1da177e4
LT		 94static void qla2x00_free_device(scsi_qla_host_t *);
95
7e47e5ca 96int ql2xfdmienable=1;
f2019cb1 97module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 98MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 99 "Enables FDMI registrations. "
100 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 101
df7baa50
AV		 102#define MAX_Q_DEPTH 32
103static int ql2xmaxqdepth = MAX_Q_DEPTH;
104module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
105MODULE_PARM_DESC(ql2xmaxqdepth,
106 "Maximum queue depth to report for target devices.");
107
bad75002 108/* Do not change the value of this after module load */
8cb2049c 109int ql2xenabledif = 0;
bad75002
AE		 110module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR);
111MODULE_PARM_DESC(ql2xenabledif,
112 " Enable T10-CRC-DIF "
8cb2049c
AE		 113 " Default is 0 - No DIF Support. 1 - Enable it"
114 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 115
8cb2049c 116int ql2xenablehba_err_chk = 2;
bad75002
AE		 117module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 119 " Enable T10-CRC-DIF Error isolation by HBA:\n"
120 " Default is 1.\n"
121 " 0 -- Error isolation disabled\n"
122 " 1 -- Error isolation enabled only for DIX Type 0\n"
123 " 2 -- Error isolation enabled for all Types\n");
bad75002 124
e5896bd5 125int ql2xiidmaenable=1;
f2019cb1 126module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 127MODULE_PARM_DESC(ql2xiidmaenable,
128 "Enables iIDMA settings "
129 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
130
73208dfd 131int ql2xmaxqueues = 1;
f2019cb1 132module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 133MODULE_PARM_DESC(ql2xmaxqueues,
134 "Enables MQ settings "
ae68230c
JP		 135 "Default is 1 for single queue. Set it to number "
136 "of queues in MQ mode.");
68ca949c
AC		 137
138int ql2xmultique_tag;
f2019cb1 139module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 140MODULE_PARM_DESC(ql2xmultique_tag,
141 "Enables CPU affinity settings for the driver "
142 "Default is 0 for no affinity of request and response IO. "
143 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 144
145int ql2xfwloadbin;
f2019cb1 146module_param(ql2xfwloadbin, int, S_IRUGO);
e337d907 147MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 148 "Option to specify location from which to load ISP firmware:.\n"
149 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 150 " interface.\n"
151 " 1 -- load firmware from flash.\n"
152 " 0 -- use default semantics.\n");
153
ae97c91e 154int ql2xetsenable;
f2019cb1 155module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 156MODULE_PARM_DESC(ql2xetsenable,
157 "Enables firmware ETS burst."
158 "Default is 0 - skip ETS enablement.");
159
6907869d 160int ql2xdbwr = 1;
f2019cb1 161module_param(ql2xdbwr, int, S_IRUGO);
a9083016 162MODULE_PARM_DESC(ql2xdbwr,
7c3df132 163 "Option to specify scheme for request queue posting.\n"
a9083016
GM		 164 " 0 -- Regular doorbell.\n"
165 " 1 -- CAMRAM doorbell (faster).\n");
166
f4c496c1 167int ql2xtargetreset = 1;
f2019cb1 168module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 169MODULE_PARM_DESC(ql2xtargetreset,
170 "Enable target reset."
171 "Default is 1 - use hw defaults.");
172
4da26e16 173int ql2xgffidenable;
f2019cb1 174module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 175MODULE_PARM_DESC(ql2xgffidenable,
176 "Enables GFF_ID checks of port type. "
177 "Default is 0 - Do not use GFF_ID information.");
a9083016 178
3822263e 179int ql2xasynctmfenable;
f2019cb1 180module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 181MODULE_PARM_DESC(ql2xasynctmfenable,
182 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
183 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 184
185int ql2xdontresethba;
186module_param(ql2xdontresethba, int, S_IRUGO);
187MODULE_PARM_DESC(ql2xdontresethba,
7c3df132 188 "Option to specify reset behaviour.\n"
ed0de87c
GM		 189 " 0 (Default) -- Reset on failure.\n"
190 " 1 -- Do not reset on failure.\n");
191
82515920
AV		 192uint ql2xmaxlun = MAX_LUNS;
193module_param(ql2xmaxlun, uint, S_IRUGO);
194MODULE_PARM_DESC(ql2xmaxlun,
195 "Defines the maximum LU number to register with the SCSI "
196 "midlayer. Default is 65535.");
197
1da177e4 198/*
fa2a1ce5 199 * SCSI host template entry points
1da177e4
LT		 200 */
201static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 202static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 203static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
204static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 205static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 206static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 207static int qla2xxx_eh_abort(struct scsi_cmnd *);
208static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 209static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 210static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
211static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 212
e881a172 213static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 214static int qla2x00_change_queue_type(struct scsi_device *, int);
215
a5326f86 216struct scsi_host_template qla2xxx_driver_template = {
1da177e4 217 .module = THIS_MODULE,
cb63067a 218 .name = QLA2XXX_DRIVER_NAME,
a5326f86 219 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 220
221 .eh_abort_handler = qla2xxx_eh_abort,
222 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 223 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 224 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
225 .eh_host_reset_handler = qla2xxx_eh_host_reset,
226
227 .slave_configure = qla2xxx_slave_configure,
228
229 .slave_alloc = qla2xxx_slave_alloc,
230 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 231 .scan_finished = qla2xxx_scan_finished,
232 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 233 .change_queue_depth = qla2x00_change_queue_depth,
234 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 235 .this_id = -1,
236 .cmd_per_lun = 3,
237 .use_clustering = ENABLE_CLUSTERING,
238 .sg_tablesize = SG_ALL,
239
240 .max_sectors = 0xFFFF,
afb046e2 241 .shost_attrs = qla2x00_host_attrs,
fca29703
AV		 242};
243
1da177e4 244static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 245struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 246
1da177e4
LT		 247/* TODO Convert to inlines
248 *
249 * Timer routines
250 */
1da177e4 251
2c3dfe3f 252__inline__ void
e315cd28 253qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 254{
e315cd28
AC		 255 init_timer(&vha->timer);
256 vha->timer.expires = jiffies + interval * HZ;
257 vha->timer.data = (unsigned long)vha;
258 vha->timer.function = (void (*)(unsigned long))func;
259 add_timer(&vha->timer);
260 vha->timer_active = 1;
1da177e4
LT		 261}
262
263static inline void
e315cd28 264qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 265{
a9083016 266 /* Currently used for 82XX only. */
7c3df132
SK		 267 if (vha->device_flags & DFLG_DEV_FAILED) {
268 ql_dbg(ql_dbg_timer, vha, 0x600d,
269 "Device in a failed state, returning.\n");
a9083016 270 return;
7c3df132 271 }
a9083016 272
e315cd28 273 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 274}
275
a824ebb3 276static __inline__ void
e315cd28 277qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 278{
e315cd28
AC		 279 del_timer_sync(&vha->timer);
280 vha->timer_active = 0;
1da177e4
LT		 281}
282
1da177e4
LT		 283static int qla2x00_do_dpc(void *data);
284
285static void qla2x00_rst_aen(scsi_qla_host_t *);
286
73208dfd
AC		 287static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
288 struct req_que **, struct rsp_que **);
e30d1756 289static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28
AC		 290static void qla2x00_mem_free(struct qla_hw_data *);
291static void qla2x00_sp_free_dma(srb_t *);
1da177e4 292
1da177e4 293/* -------------------------------------------------------------------------- */
73208dfd
AC		 294static int qla2x00_alloc_queues(struct qla_hw_data *ha)
295{
7c3df132 296 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 297 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 298 GFP_KERNEL);
299 if (!ha->req_q_map) {
7c3df132
SK		 300 ql_log(ql_log_fatal, vha, 0x003b,
301 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 302 goto fail_req_map;
303 }
304
2afa19a9 305 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 306 GFP_KERNEL);
307 if (!ha->rsp_q_map) {
7c3df132
SK		 308 ql_log(ql_log_fatal, vha, 0x003c,
309 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 310 goto fail_rsp_map;
311 }
312 set_bit(0, ha->rsp_qid_map);
313 set_bit(0, ha->req_qid_map);
314 return 1;
315
316fail_rsp_map:
317 kfree(ha->req_q_map);
318 ha->req_q_map = NULL;
319fail_req_map:
320 return -ENOMEM;
321}
322
2afa19a9 323static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 324{
73208dfd
AC		 325 if (req && req->ring)
326 dma_free_coherent(&ha->pdev->dev,
327 (req->length + 1) * sizeof(request_t),
328 req->ring, req->dma);
329
330 kfree(req);
331 req = NULL;
332}
333
2afa19a9
AC		 334static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
335{
336 if (rsp && rsp->ring)
337 dma_free_coherent(&ha->pdev->dev,
338 (rsp->length + 1) * sizeof(response_t),
339 rsp->ring, rsp->dma);
340
341 kfree(rsp);
342 rsp = NULL;
343}
344
73208dfd
AC		 345static void qla2x00_free_queues(struct qla_hw_data *ha)
346{
347 struct req_que *req;
348 struct rsp_que *rsp;
349 int cnt;
350
2afa19a9 351 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 352 req = ha->req_q_map[cnt];
2afa19a9 353 qla2x00_free_req_que(ha, req);
73208dfd 354 }
73208dfd
AC		 355 kfree(ha->req_q_map);
356 ha->req_q_map = NULL;
2afa19a9
AC		 357
358 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
359 rsp = ha->rsp_q_map[cnt];
360 qla2x00_free_rsp_que(ha, rsp);
361 }
362 kfree(ha->rsp_q_map);
363 ha->rsp_q_map = NULL;
73208dfd
AC		 364}
365
68ca949c
AC		 366static int qla25xx_setup_mode(struct scsi_qla_host *vha)
367{
368 uint16_t options = 0;
369 int ques, req, ret;
370 struct qla_hw_data *ha = vha->hw;
371
7163ea81 372 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 373 ql_log(ql_log_warn, vha, 0x00d8,
374 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 375 goto fail;
376 }
68ca949c 377 if (ql2xmultique_tag) {
68ca949c
AC		 378 /* create a request queue for IO */
379 options |= BIT_7;
380 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
381 QLA_DEFAULT_QUE_QOS);
382 if (!req) {
7c3df132
SK		 383 ql_log(ql_log_warn, vha, 0x00e0,
384 "Failed to create request queue.\n");
68ca949c
AC		 385 goto fail;
386 }
278274d5 387 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 388 vha->req = ha->req_q_map[req];
389 options |= BIT_1;
390 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
391 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
392 if (!ret) {
7c3df132
SK		 393 ql_log(ql_log_warn, vha, 0x00e8,
394 "Failed to create response queue.\n");
68ca949c
AC		 395 goto fail2;
396 }
397 }
7163ea81 398 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 399 ql_dbg(ql_dbg_multiq, vha, 0xc007,
400 "CPU affinity mode enalbed, "
401 "no. of response queues:%d no. of request queues:%d.\n",
402 ha->max_rsp_queues, ha->max_req_queues);
403 ql_dbg(ql_dbg_init, vha, 0x00e9,
404 "CPU affinity mode enalbed, "
405 "no. of response queues:%d no. of request queues:%d.\n",
406 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 407 }
408 return 0;
409fail2:
410 qla25xx_delete_queues(vha);
7163ea81
AC		 411 destroy_workqueue(ha->wq);
412 ha->wq = NULL;
68ca949c
AC		 413fail:
414 ha->mqenable = 0;
7163ea81
AC		 415 kfree(ha->req_q_map);
416 kfree(ha->rsp_q_map);
417 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 418 return 1;
419}
420
1da177e4 421static char *
e315cd28 422qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 423{
e315cd28 424 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 425 static char *pci_bus_modes[] = {
426 "33", "66", "100", "133",
427 };
428 uint16_t pci_bus;
429
430 strcpy(str, "PCI");
431 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
432 if (pci_bus) {
433 strcat(str, "-X (");
434 strcat(str, pci_bus_modes[pci_bus]);
435 } else {
436 pci_bus = (ha->pci_attr & BIT_8) >> 8;
437 strcat(str, " (");
438 strcat(str, pci_bus_modes[pci_bus]);
439 }
440 strcat(str, " MHz)");
441
442 return (str);
443}
444
fca29703 445static char *
e315cd28 446qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 447{
448 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 449 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 450 uint32_t pci_bus;
451 int pcie_reg;
452
453 pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
454 if (pcie_reg) {
455 char lwstr[6];
456 uint16_t pcie_lstat, lspeed, lwidth;
457
458 pcie_reg += 0x12;
459 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
460 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
461 lwidth = (pcie_lstat &
462 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
463
464 strcpy(str, "PCIe (");
465 if (lspeed == 1)
c87a0d8c 466 strcat(str, "2.5GT/s ");
c3a2f0df 467 else if (lspeed == 2)
c87a0d8c 468 strcat(str, "5.0GT/s ");
fca29703
AV		 469 else
470 strcat(str, "<unknown> ");
471 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
472 strcat(str, lwstr);
473
474 return str;
475 }
476
477 strcpy(str, "PCI");
478 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
479 if (pci_bus == 0 || pci_bus == 8) {
480 strcat(str, " (");
481 strcat(str, pci_bus_modes[pci_bus >> 3]);
482 } else {
483 strcat(str, "-X ");
484 if (pci_bus & BIT_2)
485 strcat(str, "Mode 2");
486 else
487 strcat(str, "Mode 1");
488 strcat(str, " (");
489 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
490 }
491 strcat(str, " MHz)");
492
493 return str;
494}
495
e5f82ab8 496static char *
e315cd28 497qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 498{
499 char un_str[10];
e315cd28 500 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 501
1da177e4
LT		 502 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
503 ha->fw_minor_version,
504 ha->fw_subminor_version);
505
506 if (ha->fw_attributes & BIT_9) {
507 strcat(str, "FLX");
508 return (str);
509 }
510
511 switch (ha->fw_attributes & 0xFF) {
512 case 0x7:
513 strcat(str, "EF");
514 break;
515 case 0x17:
516 strcat(str, "TP");
517 break;
518 case 0x37:
519 strcat(str, "IP");
520 break;
521 case 0x77:
522 strcat(str, "VI");
523 break;
524 default:
525 sprintf(un_str, "(%x)", ha->fw_attributes);
526 strcat(str, un_str);
527 break;
528 }
529 if (ha->fw_attributes & 0x100)
530 strcat(str, "X");
531
532 return (str);
533}
534
e5f82ab8 535static char *
e315cd28 536qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 537{
e315cd28 538 struct qla_hw_data *ha = vha->hw;
f0883ac6 539
3a03eb79
AV		 540 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
541 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 542 return str;
fca29703
AV		 543}
544
545static inline srb_t *
e315cd28 546qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport,
f5e3e40b 547 struct scsi_cmnd *cmd)
fca29703
AV		 548{
549 srb_t *sp;
e315cd28 550 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 551
552 sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC);
7c3df132
SK		 553 if (!sp) {
554 ql_log(ql_log_warn, vha, 0x3006,
555 "Memory allocation failed for sp.\n");
fca29703 556 return sp;
7c3df132 557 }
fca29703 558
083a469d 559 atomic_set(&sp->ref_count, 1);
fca29703
AV		 560 sp->fcport = fcport;
561 sp->cmd = cmd;
562 sp->flags = 0;
563 CMD_SP(cmd) = (void *)sp;
cf53b069 564 sp->ctx = NULL;
fca29703
AV		 565
566 return sp;
567}
568
1da177e4 569static int
f5e3e40b 570qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 571{
134ae078 572 scsi_qla_host_t *vha = shost_priv(host);
fca29703 573 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 574 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 575 struct qla_hw_data *ha = vha->hw;
576 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 577 srb_t *sp;
578 int rval;
579
85880801 580 if (ha->flags.eeh_busy) {
7c3df132
SK		 581 if (ha->flags.pci_channel_io_perm_failure) {
582 ql_dbg(ql_dbg_io, vha, 0x3001,
583 "PCI Channel IO permanent failure, exiting "
584 "cmd=%p.\n", cmd);
b9b12f73 585 cmd->result = DID_NO_CONNECT << 16;
7c3df132
SK		 586 } else {
587 ql_dbg(ql_dbg_io, vha, 0x3002,
588 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 589 cmd->result = DID_REQUEUE << 16;
7c3df132 590 }
14e660e6
SJ		 591 goto qc24_fail_command;
592 }
593
19a7b4ae
JSEC		 594 rval = fc_remote_port_chkready(rport);
595 if (rval) {
596 cmd->result = rval;
7c3df132
SK		 597 ql_dbg(ql_dbg_io, vha, 0x3003,
598 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
599 cmd, rval);
fca29703
AV		 600 goto qc24_fail_command;
601 }
602
bad75002
AE		 603 if (!vha->flags.difdix_supported &&
604 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 605 ql_dbg(ql_dbg_io, vha, 0x3004,
606 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
607 cmd);
bad75002
AE		 608 cmd->result = DID_NO_CONNECT << 16;
609 goto qc24_fail_command;
610 }
fca29703
AV		 611 if (atomic_read(&fcport->state) != FCS_ONLINE) {
612 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 613 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 614 ql_dbg(ql_dbg_io, vha, 0x3005,
615 "Returning DNC, fcport_state=%d loop_state=%d.\n",
616 atomic_read(&fcport->state),
617 atomic_read(&base_vha->loop_state));
fca29703
AV		 618 cmd->result = DID_NO_CONNECT << 16;
619 goto qc24_fail_command;
620 }
7b594131 621 goto qc24_target_busy;
fca29703
AV		 622 }
623
f5e3e40b 624 sp = qla2x00_get_new_sp(base_vha, fcport, cmd);
fca29703 625 if (!sp)
f5e3e40b 626 goto qc24_host_busy;
fca29703 627
e315cd28 628 rval = ha->isp_ops->start_scsi(sp);
7c3df132
SK		 629 if (rval != QLA_SUCCESS) {
630 ql_dbg(ql_dbg_io, vha, 0x3013,
631 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 632 goto qc24_host_busy_free_sp;
7c3df132 633 }
fca29703 634
fca29703
AV		 635 return 0;
636
637qc24_host_busy_free_sp:
e315cd28
AC		 638 qla2x00_sp_free_dma(sp);
639 mempool_free(sp, ha->srb_mempool);
fca29703 640
f5e3e40b 641qc24_host_busy:
fca29703
AV		 642 return SCSI_MLQUEUE_HOST_BUSY;
643
7b594131
MC		 644qc24_target_busy:
645 return SCSI_MLQUEUE_TARGET_BUSY;
646
fca29703 647qc24_fail_command:
f5e3e40b 648 cmd->scsi_done(cmd);
fca29703
AV		 649
650 return 0;
651}
652
1da177e4
LT		 653/*
654 * qla2x00_eh_wait_on_command
655 * Waits for the command to be returned by the Firmware for some
656 * max time.
657 *
658 * Input:
1da177e4 659 * cmd = Scsi Command to wait on.
1da177e4
LT		 660 *
661 * Return:
662 * Not Found : 0
663 * Found : 1
664 */
665static int
e315cd28 666qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 667{
fe74c71f
AV		 668#define ABORT_POLLING_PERIOD 1000
669#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 670 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 671 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
672 struct qla_hw_data *ha = vha->hw;
f4f051eb 673 int ret = QLA_SUCCESS;
1da177e4 674
85880801 675 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 676 ql_dbg(ql_dbg_taskm, vha, 0x8005,
677 "Return:eh_wait.\n");
85880801
AV		 678 return ret;
679 }
680
d970432c 681 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 682 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 683 }
684 if (CMD_SP(cmd))
685 ret = QLA_FUNCTION_FAILED;
1da177e4 686
f4f051eb 687 return ret;
1da177e4
LT		 688}
689
690/*
691 * qla2x00_wait_for_hba_online
fa2a1ce5 692 * Wait till the HBA is online after going through
1da177e4
LT		 693 * <= MAX_RETRIES_OF_ISP_ABORT or
694 * finally HBA is disabled ie marked offline
695 *
696 * Input:
697 * ha - pointer to host adapter structure
fa2a1ce5
AV		 698 *
699 * Note:
1da177e4
LT		 700 * Does context switching-Release SPIN_LOCK
701 * (if any) before calling this routine.
702 *
703 * Return:
704 * Success (Adapter is online) : 0
705 * Failed (Adapter is offline/disabled) : 1
706 */
854165f4 707int
e315cd28 708qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 709{
fca29703
AV		 710 int return_status;
711 unsigned long wait_online;
e315cd28
AC		 712 struct qla_hw_data *ha = vha->hw;
713 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 714
fa2a1ce5 715 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 716 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
717 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
718 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
719 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 720
721 msleep(1000);
722 }
e315cd28 723 if (base_vha->flags.online)
fa2a1ce5 724 return_status = QLA_SUCCESS;
1da177e4
LT		 725 else
726 return_status = QLA_FUNCTION_FAILED;
727
1da177e4
LT		 728 return (return_status);
729}
730
86fbee86
LC		 731/*
732 * qla2x00_wait_for_reset_ready
733 * Wait till the HBA is online after going through
734 * <= MAX_RETRIES_OF_ISP_ABORT or
735 * finally HBA is disabled ie marked offline or flash
736 * operations are in progress.
737 *
738 * Input:
739 * ha - pointer to host adapter structure
740 *
741 * Note:
742 * Does context switching-Release SPIN_LOCK
743 * (if any) before calling this routine.
744 *
745 * Return:
746 * Success (Adapter is online/no flash ops) : 0
747 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
748 */
3dbe756a 749static int
86fbee86
LC		 750qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
751{
752 int return_status;
753 unsigned long wait_online;
754 struct qla_hw_data *ha = vha->hw;
755 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
756
757 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
758 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
759 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
760 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
761 ha->optrom_state != QLA_SWAITING ||
762 ha->dpc_active) && time_before(jiffies, wait_online))
763 msleep(1000);
764
765 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
766 return_status = QLA_SUCCESS;
767 else
768 return_status = QLA_FUNCTION_FAILED;
769
7c3df132
SK		 770 ql_dbg(ql_dbg_taskm, vha, 0x8019,
771 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 772
773 return return_status;
774}
775
2533cf67
LC		 776int
777qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
778{
779 int return_status;
780 unsigned long wait_reset;
781 struct qla_hw_data *ha = vha->hw;
782 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
783
784 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
785 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
786 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
787 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
788 ha->dpc_active) && time_before(jiffies, wait_reset)) {
789
790 msleep(1000);
791
792 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
793 ha->flags.chip_reset_done)
794 break;
795 }
796 if (ha->flags.chip_reset_done)
797 return_status = QLA_SUCCESS;
798 else
799 return_status = QLA_FUNCTION_FAILED;
800
801 return return_status;
802}
803
1da177e4
LT		 804/*
805 * qla2x00_wait_for_loop_ready
806 * Wait for MAX_LOOP_TIMEOUT(5 min) value for loop
fa2a1ce5 807 * to be in LOOP_READY state.
1da177e4
LT		 808 * Input:
809 * ha - pointer to host adapter structure
fa2a1ce5
AV		 810 *
811 * Note:
1da177e4
LT		 812 * Does context switching-Release SPIN_LOCK
813 * (if any) before calling this routine.
fa2a1ce5 814 *
1da177e4
LT		 815 *
816 * Return:
817 * Success (LOOP_READY) : 0
818 * Failed (LOOP_NOT_READY) : 1
819 */
fa2a1ce5 820static inline int
e315cd28 821qla2x00_wait_for_loop_ready(scsi_qla_host_t *vha)
1da177e4
LT		 822{
823 int return_status = QLA_SUCCESS;
824 unsigned long loop_timeout ;
e315cd28
AC		 825 struct qla_hw_data *ha = vha->hw;
826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 827
828 /* wait for 5 min at the max for loop to be ready */
fa2a1ce5 829 loop_timeout = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1da177e4 830
e315cd28
AC		 831 while ((!atomic_read(&base_vha->loop_down_timer) &&
832 atomic_read(&base_vha->loop_state) == LOOP_DOWN) ||
833 atomic_read(&base_vha->loop_state) != LOOP_READY) {
834 if (atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
57680080
RA		 835 return_status = QLA_FUNCTION_FAILED;
836 break;
837 }
1da177e4
LT		 838 msleep(1000);
839 if (time_after_eq(jiffies, loop_timeout)) {
840 return_status = QLA_FUNCTION_FAILED;
841 break;
842 }
843 }
fa2a1ce5 844 return (return_status);
1da177e4
LT		 845}
846
083a469d
GM		 847static void
848sp_get(struct srb *sp)
849{
850 atomic_inc(&sp->ref_count);
851}
852
1da177e4
LT		 853/**************************************************************************
854* qla2xxx_eh_abort
855*
856* Description:
857* The abort function will abort the specified command.
858*
859* Input:
860* cmd = Linux SCSI command packet to be aborted.
861*
862* Returns:
863* Either SUCCESS or FAILED.
864*
865* Note:
2ea00202 866* Only return FAILED if command not returned by firmware.
1da177e4 867**************************************************************************/
e5f82ab8 868static int
1da177e4
LT		 869qla2xxx_eh_abort(struct scsi_cmnd *cmd)
870{
e315cd28 871 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 872 srb_t *sp;
4e98d3b8 873 int ret;
f4f051eb 874 unsigned int id, lun;
18e144d3 875 unsigned long flags;
2ea00202 876 int wait = 0;
e315cd28 877 struct qla_hw_data *ha = vha->hw;
1da177e4 878
7c3df132
SK		 879 ql_dbg(ql_dbg_taskm, vha, 0x8000,
880 "Entered %s for cmd=%p.\n", __func__, cmd);
f4f051eb 881 if (!CMD_SP(cmd))
2ea00202 882 return SUCCESS;
1da177e4 883
4e98d3b8 884 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 885 ql_dbg(ql_dbg_taskm, vha, 0x8001,
886 "Return value of fc_block_scsi_eh=%d.\n", ret);
4e98d3b8
AV		 887 if (ret != 0)
888 return ret;
889 ret = SUCCESS;
890
f4f051eb
AV		 891 id = cmd->device->id;
892 lun = cmd->device->lun;
1da177e4 893
e315cd28 894 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 895 sp = (srb_t *) CMD_SP(cmd);
896 if (!sp) {
897 spin_unlock_irqrestore(&ha->hardware_lock, flags);
898 return SUCCESS;
899 }
1da177e4 900
7c3df132
SK		 901 ql_dbg(ql_dbg_taskm, vha, 0x8002,
902 "Aborting sp=%p cmd=%p from RISC ", sp, cmd);
17d98630 903
170babc3
MC		 904 /* Get a reference to the sp and drop the lock.*/
905 sp_get(sp);
083a469d 906
e315cd28 907 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 908 if (ha->isp_ops->abort_command(sp)) {
7c3df132
SK		 909 ql_dbg(ql_dbg_taskm, vha, 0x8003,
910 "Abort command mbx failed for cmd=%p.\n", cmd);
170babc3 911 } else {
7c3df132
SK		 912 ql_dbg(ql_dbg_taskm, vha, 0x8004,
913 "Abort command mbx success.\n");
170babc3
MC		 914 wait = 1;
915 }
916 qla2x00_sp_compl(ha, sp);
1da177e4 917
f4f051eb 918 /* Wait for the command to be returned. */
2ea00202 919 if (wait) {
e315cd28 920 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132
SK		 921 ql_log(ql_log_warn, vha, 0x8006,
922 "Abort handler timed out for cmd=%p.\n", cmd);
2ea00202 923 ret = FAILED;
f4f051eb 924 }
1da177e4 925 }
1da177e4 926
7c3df132
SK		 927 ql_log(ql_log_info, vha, 0x801c,
928 "Abort command issued -- %d %x.\n", wait, ret);
1da177e4 929
f4f051eb
AV		 930 return ret;
931}
1da177e4 932
4d78c973 933int
e315cd28 934qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 935 unsigned int l, enum nexus_wait_type type)
f4f051eb 936{
17d98630 937 int cnt, match, status;
18e144d3 938 unsigned long flags;
e315cd28 939 struct qla_hw_data *ha = vha->hw;
73208dfd 940 struct req_que *req;
4d78c973 941 srb_t *sp;
1da177e4 942
523ec773 943 status = QLA_SUCCESS;
17d98630 944
e315cd28 945 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 946 req = vha->req;
17d98630
AC		 947 for (cnt = 1; status == QLA_SUCCESS &&
948 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
949 sp = req->outstanding_cmds[cnt];
950 if (!sp)
523ec773 951 continue;
bad75002 952 if ((sp->ctx) && !IS_PROT_IO(sp))
cf53b069 953 continue;
17d98630
AC		 954 if (vha->vp_idx != sp->fcport->vha->vp_idx)
955 continue;
956 match = 0;
957 switch (type) {
958 case WAIT_HOST:
959 match = 1;
960 break;
961 case WAIT_TARGET:
962 match = sp->cmd->device->id == t;
963 break;
964 case WAIT_LUN:
965 match = (sp->cmd->device->id == t &&
966 sp->cmd->device->lun == l);
967 break;
73208dfd 968 }
17d98630
AC		 969 if (!match)
970 continue;
971
972 spin_unlock_irqrestore(&ha->hardware_lock, flags);
973 status = qla2x00_eh_wait_on_command(sp->cmd);
974 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 975 }
e315cd28 976 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 977
978 return status;
1da177e4
LT		 979}
980
523ec773
AV		 981static char *reset_errors[] = {
982 "HBA not online",
983 "HBA not ready",
984 "Task management failed",
985 "Waiting for command completions",
986};
1da177e4 987
e5f82ab8 988static int
523ec773 989__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 990 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 991{
e315cd28 992 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 993 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 994 int err;
1da177e4 995
7c3df132
SK		 996 if (!fcport) {
997 ql_log(ql_log_warn, vha, 0x8007,
998 "fcport is NULL.\n");
523ec773 999 return FAILED;
7c3df132 1000 }
1da177e4 1001
4e98d3b8 1002 err = fc_block_scsi_eh(cmd);
7c3df132
SK		 1003 ql_dbg(ql_dbg_taskm, vha, 0x8008,
1004 "fc_block_scsi_eh ret=%d.\n", err);
4e98d3b8
AV		 1005 if (err != 0)
1006 return err;
1007
7c3df132
SK		 1008 ql_log(ql_log_info, vha, 0x8009,
1009 "%s RESET ISSUED for id %d lun %d cmd=%p.\n", name,
1010 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1011
523ec773 1012 err = 0;
7c3df132
SK		 1013 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1014 ql_log(ql_log_warn, vha, 0x800a,
1015 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1016 goto eh_reset_failed;
7c3df132 1017 }
523ec773 1018 err = 1;
7c3df132
SK		 1019 if (qla2x00_wait_for_loop_ready(vha) != QLA_SUCCESS) {
1020 ql_log(ql_log_warn, vha, 0x800b,
1021 "Wait for loop ready failed for cmd=%p.\n", cmd);
523ec773 1022 goto eh_reset_failed;
7c3df132 1023 }
523ec773 1024 err = 2;
2afa19a9 1025 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1026 != QLA_SUCCESS) {
1027 ql_log(ql_log_warn, vha, 0x800c,
1028 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1029 goto eh_reset_failed;
7c3df132 1030 }
523ec773 1031 err = 3;
e315cd28 1032 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1033 cmd->device->lun, type) != QLA_SUCCESS) {
1034 ql_log(ql_log_warn, vha, 0x800d,
1035 "wait for peding cmds failed for cmd=%p.\n", cmd);
523ec773 1036 goto eh_reset_failed;
7c3df132 1037 }
523ec773 1038
7c3df132
SK		 1039 ql_log(ql_log_info, vha, 0x800e,
1040 "%s RESET SUCCEEDED for id %d lun %d cmd=%p.\n", name,
1041 cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1042
1043 return SUCCESS;
1044
4d78c973 1045eh_reset_failed:
7c3df132
SK		 1046 ql_log(ql_log_info, vha, 0x800f,
1047 "%s RESET FAILED: %s for id %d lun %d cmd=%p.\n", name,
1048 reset_errors[err], cmd->device->id, cmd->device->lun);
523ec773
AV		 1049 return FAILED;
1050}
1da177e4 1051
523ec773
AV		 1052static int
1053qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1054{
e315cd28
AC		 1055 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1056 struct qla_hw_data *ha = vha->hw;
1da177e4 1057
523ec773
AV		 1058 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1059 ha->isp_ops->lun_reset);
1da177e4
LT		 1060}
1061
1da177e4 1062static int
523ec773 1063qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1064{
e315cd28
AC		 1065 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1066 struct qla_hw_data *ha = vha->hw;
1da177e4 1067
523ec773
AV		 1068 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1069 ha->isp_ops->target_reset);
1da177e4
LT		 1070}
1071
1da177e4
LT		 1072/**************************************************************************
1073* qla2xxx_eh_bus_reset
1074*
1075* Description:
1076* The bus reset function will reset the bus and abort any executing
1077* commands.
1078*
1079* Input:
1080* cmd = Linux SCSI command packet of the command that cause the
1081* bus reset.
1082*
1083* Returns:
1084* SUCCESS/FAILURE (defined as macro in scsi.h).
1085*
1086**************************************************************************/
e5f82ab8 1087static int
1da177e4
LT		 1088qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1089{
e315cd28 1090 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1091 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1092 int ret = FAILED;
f4f051eb 1093 unsigned int id, lun;
f4f051eb 1094
f4f051eb
AV		 1095 id = cmd->device->id;
1096 lun = cmd->device->lun;
1da177e4 1097
7c3df132
SK		 1098 if (!fcport) {
1099 ql_log(ql_log_warn, vha, 0x8010,
1100 "fcport is NULL.\n");
f4f051eb 1101 return ret;
7c3df132 1102 }
1da177e4 1103
4e98d3b8 1104 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1105 ql_dbg(ql_dbg_taskm, vha, 0x8011,
1106 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1107 if (ret != 0)
1108 return ret;
1109 ret = FAILED;
1110
7c3df132
SK		 1111 ql_log(ql_log_info, vha, 0x8012,
1112 "BUS RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1113
e315cd28 1114 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1115 ql_log(ql_log_fatal, vha, 0x8013,
1116 "Wait for hba online failed board disabled.\n");
f4f051eb 1117 goto eh_bus_reset_done;
1da177e4
LT		 1118 }
1119
e315cd28
AC		 1120 if (qla2x00_wait_for_loop_ready(vha) == QLA_SUCCESS) {
1121 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
f4f051eb 1122 ret = SUCCESS;
1da177e4 1123 }
f4f051eb
AV		 1124 if (ret == FAILED)
1125 goto eh_bus_reset_done;
1da177e4 1126
9a41a62b 1127 /* Flush outstanding commands. */
4d78c973 1128 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1129 QLA_SUCCESS) {
1130 ql_log(ql_log_warn, vha, 0x8014,
1131 "Wait for pending commands failed.\n");
9a41a62b 1132 ret = FAILED;
7c3df132 1133 }
1da177e4 1134
f4f051eb 1135eh_bus_reset_done:
7c3df132
SK		 1136 ql_log(ql_log_warn, vha, 0x802b,
1137 "BUS RESET %s.\n", (ret == FAILED) ? "FAILED" : "SUCCEDED");
1da177e4 1138
f4f051eb 1139 return ret;
1da177e4
LT		 1140}
1141
1142/**************************************************************************
1143* qla2xxx_eh_host_reset
1144*
1145* Description:
1146* The reset function will reset the Adapter.
1147*
1148* Input:
1149* cmd = Linux SCSI command packet of the command that cause the
1150* adapter reset.
1151*
1152* Returns:
1153* Either SUCCESS or FAILED.
1154*
1155* Note:
1156**************************************************************************/
e5f82ab8 1157static int
1da177e4
LT		 1158qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1159{
e315cd28 1160 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1161 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
e315cd28 1162 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1163 int ret = FAILED;
f4f051eb 1164 unsigned int id, lun;
e315cd28 1165 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1166
f4f051eb
AV		 1167 id = cmd->device->id;
1168 lun = cmd->device->lun;
f4f051eb 1169
7c3df132
SK		 1170 if (!fcport) {
1171 ql_log(ql_log_warn, vha, 0x8016,
1172 "fcport is NULL.\n");
f4f051eb 1173 return ret;
7c3df132 1174 }
1da177e4 1175
4e98d3b8 1176 ret = fc_block_scsi_eh(cmd);
7c3df132
SK		 1177 ql_dbg(ql_dbg_taskm, vha, 0x8017,
1178 "fc_block_scsi_eh ret=%d.\n", ret);
4e98d3b8
AV		 1179 if (ret != 0)
1180 return ret;
1181 ret = FAILED;
1182
7c3df132
SK		 1183 ql_log(ql_log_info, vha, 0x8018,
1184 "ADAPTER RESET ISSUED for id %d lun %d.\n", id, lun);
1da177e4 1185
86fbee86 1186 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1187 goto eh_host_reset_lock;
1da177e4
LT		 1188
1189 /*
1190 * Fixme-may be dpc thread is active and processing
fa2a1ce5 1191 * loop_resync,so wait a while for it to
1da177e4
LT		 1192 * be completed and then issue big hammer.Otherwise
1193 * it may cause I/O failure as big hammer marks the
1194 * devices as lost kicking of the port_down_timer
1195 * while dpc is stuck for the mailbox to complete.
1196 */
e315cd28
AC		 1197 qla2x00_wait_for_loop_ready(vha);
1198 if (vha != base_vha) {
1199 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1200 goto eh_host_reset_lock;
e315cd28 1201 } else {
a9083016
GM		 1202 if (IS_QLA82XX(vha->hw)) {
1203 if (!qla82xx_fcoe_ctx_reset(vha)) {
1204 /* Ctx reset success */
1205 ret = SUCCESS;
1206 goto eh_host_reset_lock;
1207 }
1208 /* fall thru if ctx reset failed */
1209 }
68ca949c
AC		 1210 if (ha->wq)
1211 flush_workqueue(ha->wq);
1212
e315cd28 1213 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1214 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1215 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1216 /* failed. schedule dpc to try */
1217 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1218
7c3df132
SK		 1219 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1220 ql_log(ql_log_warn, vha, 0x802a,
1221 "wait for hba online failed.\n");
e315cd28 1222 goto eh_host_reset_lock;
7c3df132 1223 }
e315cd28
AC		 1224 }
1225 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1226 }
1da177e4 1227
e315cd28 1228 /* Waiting for command to be returned to OS.*/
4d78c973 1229 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1230 QLA_SUCCESS)
f4f051eb 1231 ret = SUCCESS;
1da177e4 1232
f4f051eb 1233eh_host_reset_lock:
7c3df132 1234 qla_printk(KERN_INFO, ha, "%s: reset %s.\n", __func__,
25985edc 1235 (ret == FAILED) ? "failed" : "succeeded");
1da177e4 1236
f4f051eb
AV		 1237 return ret;
1238}
1da177e4
LT		 1239
1240/*
1241* qla2x00_loop_reset
1242* Issue loop reset.
1243*
1244* Input:
1245* ha = adapter block pointer.
1246*
1247* Returns:
1248* 0 = success
1249*/
a4722cf2 1250int
e315cd28 1251qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1252{
0c8c39af 1253 int ret;
bdf79621 1254 struct fc_port *fcport;
e315cd28 1255 struct qla_hw_data *ha = vha->hw;
1da177e4 1256
f4c496c1 1257 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1258 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1259 if (fcport->port_type != FCT_TARGET)
1260 continue;
1261
1262 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1263 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1264 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1265 "Bus Reset failed: Target Reset=%d "
1266 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1267 }
1268 }
1269 }
1270
a9083016 1271 if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) {
e315cd28 1272 ret = qla2x00_full_login_lip(vha);
0c8c39af 1273 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1274 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1275 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1276 }
1277 atomic_set(&vha->loop_state, LOOP_DOWN);
1278 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1279 qla2x00_mark_all_devices_lost(vha, 0);
1280 qla2x00_wait_for_loop_ready(vha);
0c8c39af
AV		 1281 }
1282
0d6e61bc 1283 if (ha->flags.enable_lip_reset) {
e315cd28 1284 ret = qla2x00_lip_reset(vha);
0c8c39af 1285 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1286 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1287 "lip_reset failed (%d).\n", ret);
e315cd28
AC		 1288 } else
1289 qla2x00_wait_for_loop_ready(vha);
1da177e4
LT		 1290 }
1291
1da177e4 1292 /* Issue marker command only when we are going to start the I/O */
e315cd28 1293 vha->marker_needed = 1;
1da177e4 1294
0c8c39af 1295 return QLA_SUCCESS;
1da177e4
LT		 1296}
1297
df4bf0bb 1298void
e315cd28 1299qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1300{
73208dfd 1301 int que, cnt;
df4bf0bb
AV		 1302 unsigned long flags;
1303 srb_t *sp;
ac280b67 1304 struct srb_ctx *ctx;
e315cd28 1305 struct qla_hw_data *ha = vha->hw;
73208dfd 1306 struct req_que *req;
df4bf0bb
AV		 1307
1308 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1309 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1310 req = ha->req_q_map[que];
73208dfd
AC		 1311 if (!req)
1312 continue;
1313 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1314 sp = req->outstanding_cmds[cnt];
e612d465 1315 if (sp) {
73208dfd 1316 req->outstanding_cmds[cnt] = NULL;
a9083016 1317 if (!sp->ctx ||
bad75002
AE		 1318 (sp->flags & SRB_FCP_CMND_DMA_VALID) ||
1319 IS_PROT_IO(sp)) {
ac280b67
AV		 1320 sp->cmd->result = res;
1321 qla2x00_sp_compl(ha, sp);
1322 } else {
1323 ctx = sp->ctx;
6c452a45
AV		 1324 if (ctx->type == SRB_LOGIN_CMD ||
1325 ctx->type == SRB_LOGOUT_CMD) {
4916392b 1326 ctx->u.iocb_cmd->free(sp);
db3ad7f8 1327 } else {
6c452a45 1328 struct fc_bsg_job *bsg_job =
4916392b 1329 ctx->u.bsg_job;
6c452a45
AV		 1330 if (bsg_job->request->msgcode
1331 == FC_BSG_HST_CT)
db3ad7f8 1332 kfree(sp->fcport);
6c452a45
AV		 1333 bsg_job->req->errors = 0;
1334 bsg_job->reply->result = res;
4916392b 1335 bsg_job->job_done(bsg_job);
db3ad7f8 1336 kfree(sp->ctx);
6c452a45 1337 mempool_free(sp,
4916392b 1338 ha->srb_mempool);
db3ad7f8 1339 }
ac280b67 1340 }
73208dfd 1341 }
df4bf0bb
AV		 1342 }
1343 }
1344 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1345}
1346
f4f051eb
AV		 1347static int
1348qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1349{
bdf79621 1350 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1351
19a7b4ae 1352 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1353 return -ENXIO;
bdf79621 1354
19a7b4ae 1355 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1356
f4f051eb
AV		 1357 return 0;
1358}
1da177e4 1359
f4f051eb
AV		 1360static int
1361qla2xxx_slave_configure(struct scsi_device *sdev)
1362{
e315cd28 1363 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1364 struct req_que *req = vha->req;
8482e118 1365
f4f051eb 1366 if (sdev->tagged_supported)
73208dfd 1367 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1368 else
73208dfd 1369 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1370 return 0;
1371}
1da177e4 1372
f4f051eb
AV		 1373static void
1374qla2xxx_slave_destroy(struct scsi_device *sdev)
1375{
1376 sdev->hostdata = NULL;
1da177e4
LT		 1377}
1378
c45dd305
GM		 1379static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1380{
1381 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1382
1383 if (!scsi_track_queue_full(sdev, qdepth))
1384 return;
1385
7c3df132
SK		 1386 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
1387 "Queue depth adjusted-down "
1388 "to %d for scsi(%ld:%d:%d:%d).\n",
1389 sdev->queue_depth, fcport->vha->host_no,
1390 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1391}
1392
1393static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1394{
1395 fc_port_t *fcport = sdev->hostdata;
1396 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1397 struct req_que *req = NULL;
1398
1399 req = vha->req;
1400 if (!req)
1401 return;
1402
1403 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1404 return;
1405
1406 if (sdev->ordered_tags)
1407 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1408 else
1409 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1410
7c3df132
SK		 1411 ql_dbg(ql_dbg_io, vha, 0x302a,
1412 "Queue depth adjusted-up to %d for "
1413 "scsi(%ld:%d:%d:%d).\n",
1414 sdev->queue_depth, fcport->vha->host_no,
1415 sdev->channel, sdev->id, sdev->lun);
c45dd305
GM		 1416}
1417
ce7e4af7 1418static int
e881a172 1419qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1420{
c45dd305
GM		 1421 switch (reason) {
1422 case SCSI_QDEPTH_DEFAULT:
1423 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1424 break;
1425 case SCSI_QDEPTH_QFULL:
1426 qla2x00_handle_queue_full(sdev, qdepth);
1427 break;
1428 case SCSI_QDEPTH_RAMP_UP:
1429 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1430 break;
1431 default:
08002af2 1432 return -EOPNOTSUPP;
c45dd305 1433 }
e881a172 1434
ce7e4af7
AV		 1435 return sdev->queue_depth;
1436}
1437
1438static int
1439qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1440{
1441 if (sdev->tagged_supported) {
1442 scsi_set_tag_type(sdev, tag_type);
1443 if (tag_type)
1444 scsi_activate_tcq(sdev, sdev->queue_depth);
1445 else
1446 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1447 } else
1448 tag_type = 0;
1449
1450 return tag_type;
1451}
1452
1da177e4
LT		 1453/**
1454 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1455 * @ha: HA context
1456 *
1457 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1458 * supported addressing method.
1459 */
1460static void
53303c42 1461qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1462{
7524f9b9 1463 /* Assume a 32bit DMA mask. */
1da177e4 1464 ha->flags.enable_64bit_addressing = 0;
1da177e4 1465
6a35528a 1466 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1467 /* Any upper-dword bits set? */
1468 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1469 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1470 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1471 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1472 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1473 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1474 return;
1da177e4 1475 }
1da177e4 1476 }
7524f9b9 1477
284901a9
YH		 1478 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1479 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1480}
1481
fd34f556 1482static void
e315cd28 1483qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1484{
1485 unsigned long flags = 0;
1486 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1487
1488 spin_lock_irqsave(&ha->hardware_lock, flags);
1489 ha->interrupts_on = 1;
1490 /* enable risc and host interrupts */
1491 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1492 RD_REG_WORD(&reg->ictrl);
1493 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1494
1495}
1496
1497static void
e315cd28 1498qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1499{
1500 unsigned long flags = 0;
1501 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1502
1503 spin_lock_irqsave(&ha->hardware_lock, flags);
1504 ha->interrupts_on = 0;
1505 /* disable risc and host interrupts */
1506 WRT_REG_WORD(&reg->ictrl, 0);
1507 RD_REG_WORD(&reg->ictrl);
1508 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1509}
1510
1511static void
e315cd28 1512qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1513{
1514 unsigned long flags = 0;
1515 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1516
1517 spin_lock_irqsave(&ha->hardware_lock, flags);
1518 ha->interrupts_on = 1;
1519 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1520 RD_REG_DWORD(&reg->ictrl);
1521 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1522}
1523
1524static void
e315cd28 1525qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1526{
1527 unsigned long flags = 0;
1528 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1529
124f85e6
AV		 1530 if (IS_NOPOLLING_TYPE(ha))
1531 return;
fd34f556
AV		 1532 spin_lock_irqsave(&ha->hardware_lock, flags);
1533 ha->interrupts_on = 0;
1534 WRT_REG_DWORD(&reg->ictrl, 0);
1535 RD_REG_DWORD(&reg->ictrl);
1536 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1537}
1538
1539static struct isp_operations qla2100_isp_ops = {
1540 .pci_config = qla2100_pci_config,
1541 .reset_chip = qla2x00_reset_chip,
1542 .chip_diag = qla2x00_chip_diag,
1543 .config_rings = qla2x00_config_rings,
1544 .reset_adapter = qla2x00_reset_adapter,
1545 .nvram_config = qla2x00_nvram_config,
1546 .update_fw_options = qla2x00_update_fw_options,
1547 .load_risc = qla2x00_load_risc,
1548 .pci_info_str = qla2x00_pci_info_str,
1549 .fw_version_str = qla2x00_fw_version_str,
1550 .intr_handler = qla2100_intr_handler,
1551 .enable_intrs = qla2x00_enable_intrs,
1552 .disable_intrs = qla2x00_disable_intrs,
1553 .abort_command = qla2x00_abort_command,
523ec773
AV		 1554 .target_reset = qla2x00_abort_target,
1555 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1556 .fabric_login = qla2x00_login_fabric,
1557 .fabric_logout = qla2x00_fabric_logout,
1558 .calc_req_entries = qla2x00_calc_iocbs_32,
1559 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1560 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1561 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1562 .read_nvram = qla2x00_read_nvram_data,
1563 .write_nvram = qla2x00_write_nvram_data,
1564 .fw_dump = qla2100_fw_dump,
1565 .beacon_on = NULL,
1566 .beacon_off = NULL,
1567 .beacon_blink = NULL,
1568 .read_optrom = qla2x00_read_optrom_data,
1569 .write_optrom = qla2x00_write_optrom_data,
1570 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1571 .start_scsi = qla2x00_start_scsi,
a9083016 1572 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1573};
1574
1575static struct isp_operations qla2300_isp_ops = {
1576 .pci_config = qla2300_pci_config,
1577 .reset_chip = qla2x00_reset_chip,
1578 .chip_diag = qla2x00_chip_diag,
1579 .config_rings = qla2x00_config_rings,
1580 .reset_adapter = qla2x00_reset_adapter,
1581 .nvram_config = qla2x00_nvram_config,
1582 .update_fw_options = qla2x00_update_fw_options,
1583 .load_risc = qla2x00_load_risc,
1584 .pci_info_str = qla2x00_pci_info_str,
1585 .fw_version_str = qla2x00_fw_version_str,
1586 .intr_handler = qla2300_intr_handler,
1587 .enable_intrs = qla2x00_enable_intrs,
1588 .disable_intrs = qla2x00_disable_intrs,
1589 .abort_command = qla2x00_abort_command,
523ec773
AV		 1590 .target_reset = qla2x00_abort_target,
1591 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1592 .fabric_login = qla2x00_login_fabric,
1593 .fabric_logout = qla2x00_fabric_logout,
1594 .calc_req_entries = qla2x00_calc_iocbs_32,
1595 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1596 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1597 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1598 .read_nvram = qla2x00_read_nvram_data,
1599 .write_nvram = qla2x00_write_nvram_data,
1600 .fw_dump = qla2300_fw_dump,
1601 .beacon_on = qla2x00_beacon_on,
1602 .beacon_off = qla2x00_beacon_off,
1603 .beacon_blink = qla2x00_beacon_blink,
1604 .read_optrom = qla2x00_read_optrom_data,
1605 .write_optrom = qla2x00_write_optrom_data,
1606 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1607 .start_scsi = qla2x00_start_scsi,
a9083016 1608 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1609};
1610
1611static struct isp_operations qla24xx_isp_ops = {
1612 .pci_config = qla24xx_pci_config,
1613 .reset_chip = qla24xx_reset_chip,
1614 .chip_diag = qla24xx_chip_diag,
1615 .config_rings = qla24xx_config_rings,
1616 .reset_adapter = qla24xx_reset_adapter,
1617 .nvram_config = qla24xx_nvram_config,
1618 .update_fw_options = qla24xx_update_fw_options,
1619 .load_risc = qla24xx_load_risc,
1620 .pci_info_str = qla24xx_pci_info_str,
1621 .fw_version_str = qla24xx_fw_version_str,
1622 .intr_handler = qla24xx_intr_handler,
1623 .enable_intrs = qla24xx_enable_intrs,
1624 .disable_intrs = qla24xx_disable_intrs,
1625 .abort_command = qla24xx_abort_command,
523ec773
AV		 1626 .target_reset = qla24xx_abort_target,
1627 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1628 .fabric_login = qla24xx_login_fabric,
1629 .fabric_logout = qla24xx_fabric_logout,
1630 .calc_req_entries = NULL,
1631 .build_iocbs = NULL,
1632 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1633 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1634 .read_nvram = qla24xx_read_nvram_data,
1635 .write_nvram = qla24xx_write_nvram_data,
1636 .fw_dump = qla24xx_fw_dump,
1637 .beacon_on = qla24xx_beacon_on,
1638 .beacon_off = qla24xx_beacon_off,
1639 .beacon_blink = qla24xx_beacon_blink,
1640 .read_optrom = qla24xx_read_optrom_data,
1641 .write_optrom = qla24xx_write_optrom_data,
1642 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1643 .start_scsi = qla24xx_start_scsi,
a9083016 1644 .abort_isp = qla2x00_abort_isp,
fd34f556
AV		 1645};
1646
c3a2f0df
AV		 1647static struct isp_operations qla25xx_isp_ops = {
1648 .pci_config = qla25xx_pci_config,
1649 .reset_chip = qla24xx_reset_chip,
1650 .chip_diag = qla24xx_chip_diag,
1651 .config_rings = qla24xx_config_rings,
1652 .reset_adapter = qla24xx_reset_adapter,
1653 .nvram_config = qla24xx_nvram_config,
1654 .update_fw_options = qla24xx_update_fw_options,
1655 .load_risc = qla24xx_load_risc,
1656 .pci_info_str = qla24xx_pci_info_str,
1657 .fw_version_str = qla24xx_fw_version_str,
1658 .intr_handler = qla24xx_intr_handler,
1659 .enable_intrs = qla24xx_enable_intrs,
1660 .disable_intrs = qla24xx_disable_intrs,
1661 .abort_command = qla24xx_abort_command,
523ec773
AV		 1662 .target_reset = qla24xx_abort_target,
1663 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1664 .fabric_login = qla24xx_login_fabric,
1665 .fabric_logout = qla24xx_fabric_logout,
1666 .calc_req_entries = NULL,
1667 .build_iocbs = NULL,
1668 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1669 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1670 .read_nvram = qla25xx_read_nvram_data,
1671 .write_nvram = qla25xx_write_nvram_data,
1672 .fw_dump = qla25xx_fw_dump,
1673 .beacon_on = qla24xx_beacon_on,
1674 .beacon_off = qla24xx_beacon_off,
1675 .beacon_blink = qla24xx_beacon_blink,
338c9161 1676 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1677 .write_optrom = qla24xx_write_optrom_data,
1678 .get_flash_version = qla24xx_get_flash_version,
bad75002 1679 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1680 .abort_isp = qla2x00_abort_isp,
c3a2f0df
AV		 1681};
1682
3a03eb79
AV		 1683static struct isp_operations qla81xx_isp_ops = {
1684 .pci_config = qla25xx_pci_config,
1685 .reset_chip = qla24xx_reset_chip,
1686 .chip_diag = qla24xx_chip_diag,
1687 .config_rings = qla24xx_config_rings,
1688 .reset_adapter = qla24xx_reset_adapter,
1689 .nvram_config = qla81xx_nvram_config,
1690 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1691 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1692 .pci_info_str = qla24xx_pci_info_str,
1693 .fw_version_str = qla24xx_fw_version_str,
1694 .intr_handler = qla24xx_intr_handler,
1695 .enable_intrs = qla24xx_enable_intrs,
1696 .disable_intrs = qla24xx_disable_intrs,
1697 .abort_command = qla24xx_abort_command,
1698 .target_reset = qla24xx_abort_target,
1699 .lun_reset = qla24xx_lun_reset,
1700 .fabric_login = qla24xx_login_fabric,
1701 .fabric_logout = qla24xx_fabric_logout,
1702 .calc_req_entries = NULL,
1703 .build_iocbs = NULL,
1704 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1705 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1706 .read_nvram = NULL,
1707 .write_nvram = NULL,
3a03eb79
AV		 1708 .fw_dump = qla81xx_fw_dump,
1709 .beacon_on = qla24xx_beacon_on,
1710 .beacon_off = qla24xx_beacon_off,
1711 .beacon_blink = qla24xx_beacon_blink,
1712 .read_optrom = qla25xx_read_optrom_data,
1713 .write_optrom = qla24xx_write_optrom_data,
1714 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1715 .start_scsi = qla24xx_dif_start_scsi,
a9083016
GM		 1716 .abort_isp = qla2x00_abort_isp,
1717};
1718
1719static struct isp_operations qla82xx_isp_ops = {
1720 .pci_config = qla82xx_pci_config,
1721 .reset_chip = qla82xx_reset_chip,
1722 .chip_diag = qla24xx_chip_diag,
1723 .config_rings = qla82xx_config_rings,
1724 .reset_adapter = qla24xx_reset_adapter,
1725 .nvram_config = qla81xx_nvram_config,
1726 .update_fw_options = qla24xx_update_fw_options,
1727 .load_risc = qla82xx_load_risc,
1728 .pci_info_str = qla82xx_pci_info_str,
1729 .fw_version_str = qla24xx_fw_version_str,
1730 .intr_handler = qla82xx_intr_handler,
1731 .enable_intrs = qla82xx_enable_intrs,
1732 .disable_intrs = qla82xx_disable_intrs,
1733 .abort_command = qla24xx_abort_command,
1734 .target_reset = qla24xx_abort_target,
1735 .lun_reset = qla24xx_lun_reset,
1736 .fabric_login = qla24xx_login_fabric,
1737 .fabric_logout = qla24xx_fabric_logout,
1738 .calc_req_entries = NULL,
1739 .build_iocbs = NULL,
1740 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1741 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1742 .read_nvram = qla24xx_read_nvram_data,
1743 .write_nvram = qla24xx_write_nvram_data,
1744 .fw_dump = qla24xx_fw_dump,
1745 .beacon_on = qla24xx_beacon_on,
1746 .beacon_off = qla24xx_beacon_off,
1747 .beacon_blink = qla24xx_beacon_blink,
1748 .read_optrom = qla82xx_read_optrom_data,
1749 .write_optrom = qla82xx_write_optrom_data,
1750 .get_flash_version = qla24xx_get_flash_version,
1751 .start_scsi = qla82xx_start_scsi,
1752 .abort_isp = qla82xx_abort_isp,
3a03eb79
AV		 1753};
1754
ea5b6382 1755static inline void
e315cd28 1756qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 1757{
1758 ha->device_type = DT_EXTENDED_IDS;
1759 switch (ha->pdev->device) {
1760 case PCI_DEVICE_ID_QLOGIC_ISP2100:
1761 ha->device_type |= DT_ISP2100;
1762 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1763 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 1764 break;
1765 case PCI_DEVICE_ID_QLOGIC_ISP2200:
1766 ha->device_type |= DT_ISP2200;
1767 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 1768 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 1769 break;
1770 case PCI_DEVICE_ID_QLOGIC_ISP2300:
1771 ha->device_type |= DT_ISP2300;
4a59f71d 1772 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1773 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1774 break;
1775 case PCI_DEVICE_ID_QLOGIC_ISP2312:
1776 ha->device_type |= DT_ISP2312;
4a59f71d 1777 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 1778 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1779 break;
1780 case PCI_DEVICE_ID_QLOGIC_ISP2322:
1781 ha->device_type |= DT_ISP2322;
4a59f71d 1782 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 1783 if (ha->pdev->subsystem_vendor == 0x1028 &&
1784 ha->pdev->subsystem_device == 0x0170)
1785 ha->device_type |= DT_OEM_001;
441d1072 1786 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1787 break;
1788 case PCI_DEVICE_ID_QLOGIC_ISP6312:
1789 ha->device_type |= DT_ISP6312;
441d1072 1790 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1791 break;
1792 case PCI_DEVICE_ID_QLOGIC_ISP6322:
1793 ha->device_type |= DT_ISP6322;
441d1072 1794 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 1795 break;
1796 case PCI_DEVICE_ID_QLOGIC_ISP2422:
1797 ha->device_type |= DT_ISP2422;
4a59f71d 1798 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1799 ha->device_type |= DT_FWI2;
c76f2c01 1800 ha->device_type |= DT_IIDMA;
441d1072 1801 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 1802 break;
1803 case PCI_DEVICE_ID_QLOGIC_ISP2432:
1804 ha->device_type |= DT_ISP2432;
4a59f71d 1805 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 1806 ha->device_type |= DT_FWI2;
c76f2c01 1807 ha->device_type |= DT_IIDMA;
441d1072 1808 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1809 break;
4d4df193
HK		 1810 case PCI_DEVICE_ID_QLOGIC_ISP8432:
1811 ha->device_type |= DT_ISP8432;
1812 ha->device_type |= DT_ZIO_SUPPORTED;
1813 ha->device_type |= DT_FWI2;
1814 ha->device_type |= DT_IIDMA;
1815 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1816 break;
044cc6c8
AV		 1817 case PCI_DEVICE_ID_QLOGIC_ISP5422:
1818 ha->device_type |= DT_ISP5422;
e428924c 1819 ha->device_type |= DT_FWI2;
441d1072 1820 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1821 break;
044cc6c8
AV		 1822 case PCI_DEVICE_ID_QLOGIC_ISP5432:
1823 ha->device_type |= DT_ISP5432;
e428924c 1824 ha->device_type |= DT_FWI2;
441d1072 1825 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1826 break;
c3a2f0df
AV		 1827 case PCI_DEVICE_ID_QLOGIC_ISP2532:
1828 ha->device_type |= DT_ISP2532;
1829 ha->device_type |= DT_ZIO_SUPPORTED;
1830 ha->device_type |= DT_FWI2;
1831 ha->device_type |= DT_IIDMA;
441d1072 1832 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 1833 break;
3a03eb79
AV		 1834 case PCI_DEVICE_ID_QLOGIC_ISP8001:
1835 ha->device_type |= DT_ISP8001;
1836 ha->device_type |= DT_ZIO_SUPPORTED;
1837 ha->device_type |= DT_FWI2;
1838 ha->device_type |= DT_IIDMA;
1839 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1840 break;
a9083016
GM		 1841 case PCI_DEVICE_ID_QLOGIC_ISP8021:
1842 ha->device_type |= DT_ISP8021;
1843 ha->device_type |= DT_ZIO_SUPPORTED;
1844 ha->device_type |= DT_FWI2;
1845 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
1846 /* Initialize 82XX ISP flags */
1847 qla82xx_init_flags(ha);
1848 break;
ea5b6382 1849 }
e5b68a61 1850
a9083016
GM		 1851 if (IS_QLA82XX(ha))
1852 ha->port_no = !(ha->portnum & 1);
1853 else
1854 /* Get adapter physical port no from interrupt pin register. */
1855 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
1856
e5b68a61
AC		 1857 if (ha->port_no & 1)
1858 ha->flags.port0 = 1;
1859 else
1860 ha->flags.port0 = 0;
7c3df132
SK		 1861 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
1862 "device_type=0x%x port=%d fw_srisc_address=%p.\n",
1863 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 1864}
1865
1da177e4 1866static int
e315cd28 1867qla2x00_iospace_config(struct qla_hw_data *ha)
1da177e4 1868{
3776541d 1869 resource_size_t pio;
73208dfd 1870 uint16_t msix;
68ca949c 1871 int cpus;
1da177e4 1872
a9083016
GM		 1873 if (IS_QLA82XX(ha))
1874 return qla82xx_iospace_config(ha);
1875
285d0321
AV		 1876 if (pci_request_selected_regions(ha->pdev, ha->bars,
1877 QLA2XXX_DRIVER_NAME)) {
7c3df132
SK		 1878 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1879 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
285d0321 1880 pci_name(ha->pdev));
285d0321
AV		 1881 goto iospace_error_exit;
1882 }
1883 if (!(ha->bars & 1))
1884 goto skip_pio;
1885
1da177e4
LT		 1886 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1887 pio = pci_resource_start(ha->pdev, 0);
3776541d
AV		 1888 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1889 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
7c3df132
SK		 1890 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1891 "Invalid pci I/O region size (%s).\n",
1892 pci_name(ha->pdev));
1da177e4
LT		 1893 pio = 0;
1894 }
1895 } else {
7c3df132
SK		 1896 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1897 "Region #0 no a PIO resource (%s).\n",
1da177e4
LT		 1898 pci_name(ha->pdev));
1899 pio = 0;
1900 }
285d0321 1901 ha->pio_address = pio;
7c3df132
SK		 1902 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1903 "PIO address=%p.\n",
1904 ha->pio_address);
1da177e4 1905
285d0321 1906skip_pio:
1da177e4 1907 /* Use MMIO operations for all accesses. */
3776541d 1908 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
7c3df132
SK		 1909 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1910 "Region #1 not an MMIO resource (%s), aborting.\n",
1da177e4
LT		 1911 pci_name(ha->pdev));
1912 goto iospace_error_exit;
1913 }
3776541d 1914 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
7c3df132
SK		 1915 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1916 "Invalid PCI mem region size (%s), aborting.\n",
1917 pci_name(ha->pdev));
1da177e4
LT		 1918 goto iospace_error_exit;
1919 }
1920
3776541d 1921 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1da177e4 1922 if (!ha->iobase) {
7c3df132
SK		 1923 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1924 "Cannot remap MMIO (%s), aborting.\n",
1925 pci_name(ha->pdev));
1da177e4
LT		 1926 goto iospace_error_exit;
1927 }
1928
73208dfd 1929 /* Determine queue resources */
2afa19a9 1930 ha->max_req_queues = ha->max_rsp_queues = 1;
d84a47c2
MH		 1931 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1932 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
2afa19a9 1933 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
17d98630 1934 goto mqiobase_exit;
d84a47c2 1935
17d98630
AC		 1936 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1937 pci_resource_len(ha->pdev, 3));
1938 if (ha->mqiobase) {
7c3df132
SK		 1939 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1940 "MQIO Base=%p.\n", ha->mqiobase);
17d98630
AC		 1941 /* Read MSIX vector size of the board */
1942 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1943 ha->msix_count = msix;
68ca949c
AC		 1944 /* Max queues are bounded by available msix vectors */
1945 /* queue 0 uses two msix vectors */
1946 if (ql2xmultique_tag) {
1947 cpus = num_online_cpus();
27dc9c5a 1948 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
68ca949c
AC		 1949 (cpus + 1) : (ha->msix_count - 1);
1950 ha->max_req_queues = 2;
1951 } else if (ql2xmaxqueues > 1) {
2afa19a9 1952 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
7c3df132
SK		 1953 QLA_MQ_SIZE : ql2xmaxqueues;
1954 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1955 "QoS mode set, max no of request queues:%d.\n",
1956 ha->max_req_queues);
1957 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1958 "QoS mode set, max no of request queues:%d.\n",
1959 ha->max_req_queues);
2afa19a9 1960 }
7c3df132
SK		 1961 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1962 "MSI-X vector count: %d.\n", msix);
2afa19a9 1963 } else
7c3df132
SK		 1964 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1965 "BAR 3 not enabled.\n");
17d98630
AC		 1966
1967mqiobase_exit:
2afa19a9 1968 ha->msix_count = ha->max_rsp_queues + 1;
7c3df132
SK		 1969 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1970 "MSIX Count:%d.\n", ha->msix_count);
1da177e4
LT		 1971 return (0);
1972
1973iospace_error_exit:
1974 return (-ENOMEM);
1975}
1976
1e99e33a
AV		 1977static void
1978qla2xxx_scan_start(struct Scsi_Host *shost)
1979{
e315cd28 1980 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 1981
cbc8eb67
AV		 1982 if (vha->hw->flags.running_gold_fw)
1983 return;
1984
e315cd28
AC		 1985 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1986 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1987 set_bit(RSCN_UPDATE, &vha->dpc_flags);
1988 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 1989}
1990
1991static int
1992qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
1993{
e315cd28 1994 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 1995
e315cd28 1996 if (!vha->host)
1e99e33a 1997 return 1;
e315cd28 1998 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 1999 return 1;
2000
e315cd28 2001 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2002}
2003
1da177e4
LT		 2004/*
2005 * PCI driver interface
2006 */
7ee61397
AV		 2007static int __devinit
2008qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2009{
a1541d5a 2010 int ret = -ENODEV;
1da177e4 2011 struct Scsi_Host *host;
e315cd28
AC		 2012 scsi_qla_host_t *base_vha = NULL;
2013 struct qla_hw_data *ha;
29856e28 2014 char pci_info[30];
1da177e4 2015 char fw_str[30];
5433383e 2016 struct scsi_host_template *sht;
c51da4ec 2017 int bars, max_id, mem_only = 0;
e315cd28 2018 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2019 struct req_que *req = NULL;
2020 struct rsp_que *rsp = NULL;
1da177e4 2021
285d0321 2022 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2023 sht = &qla2xxx_driver_template;
5433383e 2024 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2025 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2026 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2027 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2028 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2029 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016
GM		 2030 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2031 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) {
285d0321 2032 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2033 mem_only = 1;
7c3df132
SK		 2034 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2035 "Mem only adapter.\n");
285d0321 2036 }
7c3df132
SK		 2037 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2038 "Bars=%d.\n", bars);
285d0321 2039
09483916
BH		 2040 if (mem_only) {
2041 if (pci_enable_device_mem(pdev))
2042 goto probe_out;
2043 } else {
2044 if (pci_enable_device(pdev))
2045 goto probe_out;
2046 }
285d0321 2047
0927678f
JB		 2048 /* This may fail but that's ok */
2049 pci_enable_pcie_error_reporting(pdev);
285d0321 2050
e315cd28
AC		 2051 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2052 if (!ha) {
7c3df132
SK		 2053 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2054 "Unable to allocate memory for ha.\n");
e315cd28 2055 goto probe_out;
1da177e4 2056 }
7c3df132
SK		 2057 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2058 "Memory allocated for ha=%p.\n", ha);
e315cd28 2059 ha->pdev = pdev;
1da177e4
LT		 2060
2061 /* Clear our data area */
285d0321 2062 ha->bars = bars;
09483916 2063 ha->mem_only = mem_only;
df4bf0bb 2064 spin_lock_init(&ha->hardware_lock);
339aa70e 2065 spin_lock_init(&ha->vport_slock);
1da177e4 2066
ea5b6382
AV		 2067 /* Set ISP-type information. */
2068 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2069
2070 /* Set EEH reset type to fundamental if required by hba */
2071 if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) {
2072 pdev->needs_freset = 1;
ca79cf66
DG		 2073 }
2074
1da177e4
LT		 2075 /* Configure PCI I/O space */
2076 ret = qla2x00_iospace_config(ha);
a1541d5a 2077 if (ret)
e315cd28 2078 goto probe_hw_failed;
1da177e4 2079
7c3df132
SK		 2080 ql_log_pci(ql_log_info, pdev, 0x001d,
2081 "Found an ISP%04X irq %d iobase 0x%p.\n",
2082 pdev->device, pdev->irq, ha->iobase);
1da177e4 2083 ha->prev_topology = 0;
fca29703 2084 ha->init_cb_size = sizeof(init_cb_t);
d8b45213 2085 ha->link_data_rate = PORT_SPEED_UNKNOWN;
854165f4 2086 ha->optrom_size = OPTROM_SIZE_2300;
1da177e4 2087
abbd8870 2088 /* Assign ISP specific operations. */
e315cd28 2089 max_id = MAX_TARGETS_2200;
1da177e4 2090 if (IS_QLA2100(ha)) {
e315cd28 2091 max_id = MAX_TARGETS_2100;
1da177e4 2092 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2093 req_length = REQUEST_ENTRY_CNT_2100;
2094 rsp_length = RESPONSE_ENTRY_CNT_2100;
2095 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2096 ha->gid_list_info_size = 4;
3a03eb79
AV		 2097 ha->flash_conf_off = ~0;
2098 ha->flash_data_off = ~0;
2099 ha->nvram_conf_off = ~0;
2100 ha->nvram_data_off = ~0;
fd34f556 2101 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2102 } else if (IS_QLA2200(ha)) {
1da177e4 2103 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2104 req_length = REQUEST_ENTRY_CNT_2200;
2105 rsp_length = RESPONSE_ENTRY_CNT_2100;
2106 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2107 ha->gid_list_info_size = 4;
3a03eb79
AV		 2108 ha->flash_conf_off = ~0;
2109 ha->flash_data_off = ~0;
2110 ha->nvram_conf_off = ~0;
2111 ha->nvram_data_off = ~0;
fd34f556 2112 ha->isp_ops = &qla2100_isp_ops;
fca29703 2113 } else if (IS_QLA23XX(ha)) {
1da177e4 2114 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2115 req_length = REQUEST_ENTRY_CNT_2200;
2116 rsp_length = RESPONSE_ENTRY_CNT_2300;
2117 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2118 ha->gid_list_info_size = 6;
854165f4
AV		 2119 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2120 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2121 ha->flash_conf_off = ~0;
2122 ha->flash_data_off = ~0;
2123 ha->nvram_conf_off = ~0;
2124 ha->nvram_data_off = ~0;
fd34f556 2125 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2126 } else if (IS_QLA24XX_TYPE(ha)) {
fca29703 2127 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2128 req_length = REQUEST_ENTRY_CNT_24XX;
2129 rsp_length = RESPONSE_ENTRY_CNT_2300;
2130 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2131 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2132 ha->gid_list_info_size = 8;
854165f4 2133 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2134 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2135 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2136 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2137 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2138 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2139 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2140 } else if (IS_QLA25XX(ha)) {
c3a2f0df 2141 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2142 req_length = REQUEST_ENTRY_CNT_24XX;
2143 rsp_length = RESPONSE_ENTRY_CNT_2300;
2144 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2145 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2146 ha->gid_list_info_size = 8;
2147 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2148 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2149 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2150 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2151 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2152 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2153 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2154 } else if (IS_QLA81XX(ha)) {
2155 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2156 req_length = REQUEST_ENTRY_CNT_24XX;
2157 rsp_length = RESPONSE_ENTRY_CNT_2300;
2158 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2159 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2160 ha->gid_list_info_size = 8;
2161 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2162 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2163 ha->isp_ops = &qla81xx_isp_ops;
2164 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2165 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2166 ha->nvram_conf_off = ~0;
2167 ha->nvram_data_off = ~0;
a9083016
GM		 2168 } else if (IS_QLA82XX(ha)) {
2169 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2170 req_length = REQUEST_ENTRY_CNT_82XX;
2171 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2172 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2173 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2174 ha->gid_list_info_size = 8;
2175 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2176 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2177 ha->isp_ops = &qla82xx_isp_ops;
2178 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2179 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2180 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2181 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
1da177e4 2182 }
7c3df132
SK		 2183 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2184 "mbx_count=%d, req_length=%d, "
2185 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
2186 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n",
2187 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2188 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
2189 ha->nvram_npiv_size);
2190 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2191 "isp_ops=%p, flash_conf_off=%d, "
2192 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2193 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2194 ha->nvram_conf_off, ha->nvram_data_off);
6c2f527c 2195 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2196 init_completion(&ha->mbx_cmd_comp);
2197 complete(&ha->mbx_cmd_comp);
2198 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2199 init_completion(&ha->dcbx_comp);
1da177e4 2200
2c3dfe3f 2201 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2202
53303c42 2203 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2204 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2205 "64 Bit addressing is %s.\n",
2206 ha->flags.enable_64bit_addressing ? "enable" :
2207 "disable");
73208dfd 2208 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2209 if (!ret) {
7c3df132
SK		 2210 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2211 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2212
e315cd28
AC		 2213 goto probe_hw_failed;
2214 }
2215
73208dfd 2216 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2217 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2218 req->max_q_depth = ql2xmaxqdepth;
2219
e315cd28
AC		 2220
2221 base_vha = qla2x00_create_host(sht, ha);
2222 if (!base_vha) {
a1541d5a 2223 ret = -ENOMEM;
6e9f21f3 2224 qla2x00_mem_free(ha);
2afa19a9
AC		 2225 qla2x00_free_req_que(ha, req);
2226 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2227 goto probe_hw_failed;
1da177e4
LT		 2228 }
2229
e315cd28
AC		 2230 pci_set_drvdata(pdev, base_vha);
2231
e315cd28 2232 host = base_vha->host;
2afa19a9 2233 base_vha->req = req;
73208dfd
AC		 2234 host->can_queue = req->length + 128;
2235 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2236 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2237 else
e315cd28
AC		 2238 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2239 base_vha->vp_idx;
58548cb5
GM		 2240
2241 /* Set the SG table size based on ISP type */
2242 if (!IS_FWI2_CAPABLE(ha)) {
2243 if (IS_QLA2100(ha))
2244 host->sg_tablesize = 32;
2245 } else {
2246 if (!IS_QLA82XX(ha))
2247 host->sg_tablesize = QLA_SG_ALL;
2248 }
7c3df132
SK		 2249 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2250 "can_queue=%d, req=%p, "
2251 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2252 host->can_queue, base_vha->req,
2253 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
e315cd28
AC		 2254 host->max_id = max_id;
2255 host->this_id = 255;
2256 host->cmd_per_lun = 3;
2257 host->unique_id = host->host_no;
e02587d7 2258 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2259 host->max_cmd_len = 32;
2260 else
2261 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2262 host->max_channel = MAX_BUSES - 1;
82515920 2263 host->max_lun = ql2xmaxlun;
e315cd28 2264 host->transportt = qla2xxx_transport_template;
9a069e19 2265 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2266
7c3df132
SK		 2267 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2268 "max_id=%d this_id=%d "
2269 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
2270 "max_lun=%d transportt=%p, vendor_id=%d.\n", host->max_id,
2271 host->this_id, host->cmd_per_lun, host->unique_id,
2272 host->max_cmd_len, host->max_channel, host->max_lun,
2273 host->transportt, sht->vendor_id);
2274
73208dfd
AC		 2275 /* Set up the irqs */
2276 ret = qla2x00_request_irqs(ha, rsp);
2277 if (ret)
6e9f21f3 2278 goto probe_init_failed;
90a86fc0
JC		 2279
2280 pci_save_state(pdev);
2281
73208dfd 2282 /* Alloc arrays of request and response ring ptrs */
7163ea81 2283que_init:
73208dfd 2284 if (!qla2x00_alloc_queues(ha)) {
7c3df132
SK		 2285 ql_log(ql_log_fatal, base_vha, 0x003d,
2286 "Failed to allocate memory for queue pointers.. aborting.\n");
6e9f21f3 2287 goto probe_init_failed;
73208dfd 2288 }
a9083016 2289
73208dfd
AC		 2290 ha->rsp_q_map[0] = rsp;
2291 ha->req_q_map[0] = req;
2afa19a9
AC		 2292 rsp->req = req;
2293 req->rsp = rsp;
2294 set_bit(0, ha->req_qid_map);
2295 set_bit(0, ha->rsp_qid_map);
08029990
AV		 2296 /* FWI2-capable only. */
2297 req->req_q_in = &ha->iobase->isp24.req_q_in;
2298 req->req_q_out = &ha->iobase->isp24.req_q_out;
2299 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2300 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
17d98630 2301 if (ha->mqenable) {
08029990
AV		 2302 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2303 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2304 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2305 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2306 }
2307
a9083016
GM		 2308 if (IS_QLA82XX(ha)) {
2309 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2310 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2311 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2312 }
2313
7c3df132
SK		 2314 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2315 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2316 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2317 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2318 "req->req_q_in=%p req->req_q_out=%p "
2319 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2320 req->req_q_in, req->req_q_out,
2321 rsp->rsp_q_in, rsp->rsp_q_out);
2322 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2323 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2324 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2325 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2326 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2327 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2328
7c3df132
SK		 2329 if (qla2x00_initialize_adapter(base_vha)) {
2330 ql_log(ql_log_fatal, base_vha, 0x00d6,
2331 "Failed to initialize adapter - Adapter flags %x.\n",
2332 base_vha->device_flags);
1da177e4 2333
a9083016
GM		 2334 if (IS_QLA82XX(ha)) {
2335 qla82xx_idc_lock(ha);
2336 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2337 QLA82XX_DEV_FAILED);
2338 qla82xx_idc_unlock(ha);
7c3df132
SK		 2339 ql_log(ql_log_fatal, base_vha, 0x00d7,
2340 "HW State: FAILED.\n");
a9083016
GM		 2341 }
2342
a1541d5a 2343 ret = -ENODEV;
1da177e4
LT		 2344 goto probe_failed;
2345 }
2346
7163ea81
AC		 2347 if (ha->mqenable) {
2348 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2349 ql_log(ql_log_warn, base_vha, 0x00ec,
2350 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2351 goto que_init;
2352 }
2353 }
68ca949c 2354
cbc8eb67
AV		 2355 if (ha->flags.running_gold_fw)
2356 goto skip_dpc;
2357
1da177e4
LT		 2358 /*
2359 * Startup the kernel thread for this host adapter
2360 */
39a11240 2361 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2362 "%s_dpc", base_vha->host_str);
39a11240 2363 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2364 ql_log(ql_log_fatal, base_vha, 0x00ed,
2365 "Failed to start DPC thread.\n");
39a11240 2366 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2367 goto probe_failed;
2368 }
7c3df132
SK		 2369 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2370 "DPC thread started successfully.\n");
1da177e4 2371
cbc8eb67 2372skip_dpc:
e315cd28
AC		 2373 list_add_tail(&base_vha->list, &ha->vp_list);
2374 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2375
2376 /* Initialized the timer */
e315cd28 2377 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2378 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2379 "Started qla2x00_timer with "
2380 "interval=%d.\n", WATCH_INTERVAL);
2381 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2382 "Detected hba at address=%p.\n",
2383 ha);
d19044c3 2384
e02587d7 2385 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2386 if (ha->fw_attributes & BIT_4) {
8cb2049c 2387 int prot = 0;
bad75002 2388 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2389 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2390 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2391 if (ql2xenabledif == 1)
2392 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2393 scsi_host_set_prot(host,
8cb2049c 2394 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2395 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2396 | SHOST_DIF_TYPE3_PROTECTION
2397 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2398 | SHOST_DIX_TYPE2_PROTECTION
bad75002
AE		 2399 | SHOST_DIX_TYPE3_PROTECTION);
2400 scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC);
2401 } else
2402 base_vha->flags.difdix_supported = 0;
2403 }
2404
a9083016
GM		 2405 ha->isp_ops->enable_intrs(ha);
2406
a1541d5a
AV		 2407 ret = scsi_add_host(host, &pdev->dev);
2408 if (ret)
2409 goto probe_failed;
2410
1486400f
MR		 2411 base_vha->flags.init_done = 1;
2412 base_vha->flags.online = 1;
2413
7c3df132
SK		 2414 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2415 "Init done and hba is online.\n");
2416
1e99e33a
AV		 2417 scsi_scan_host(host);
2418
e315cd28 2419 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2420
e315cd28 2421 qla2x00_init_host_attr(base_vha);
a1541d5a 2422
e315cd28 2423 qla2x00_dfs_setup(base_vha);
df613b96 2424
7c3df132
SK		 2425 ql_log(ql_log_info, base_vha, 0x00fa,
2426 "QLogic Fibre Channed HBA Driver: %s.\n",
2427 qla2x00_version_str);
2428 ql_log(ql_log_info, base_vha, 0x00fb,
2429 "QLogic %s - %s.\n",
2430 ha->model_number, ha->model_desc ? ha->model_desc : "");
2431 ql_log(ql_log_info, base_vha, 0x00fc,
2432 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2433 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2434 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2435 base_vha->host_no,
e315cd28 2436 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2437
1da177e4
LT		 2438 return 0;
2439
6e9f21f3 2440probe_init_failed:
2afa19a9
AC		 2441 qla2x00_free_req_que(ha, req);
2442 qla2x00_free_rsp_que(ha, rsp);
2443 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2444
1da177e4 2445probe_failed:
b9978769
AV		 2446 if (base_vha->timer_active)
2447 qla2x00_stop_timer(base_vha);
2448 base_vha->flags.online = 0;
2449 if (ha->dpc_thread) {
2450 struct task_struct *t = ha->dpc_thread;
2451
2452 ha->dpc_thread = NULL;
2453 kthread_stop(t);
2454 }
2455
e315cd28 2456 qla2x00_free_device(base_vha);
1da177e4 2457
e315cd28 2458 scsi_host_put(base_vha->host);
1da177e4 2459
e315cd28 2460probe_hw_failed:
a9083016
GM		 2461 if (IS_QLA82XX(ha)) {
2462 qla82xx_idc_lock(ha);
2463 qla82xx_clear_drv_active(ha);
2464 qla82xx_idc_unlock(ha);
2465 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2466 if (!ql2xdbwr)
2467 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2468 } else {
2469 if (ha->iobase)
2470 iounmap(ha->iobase);
2471 }
e315cd28
AC		 2472 pci_release_selected_regions(ha->pdev, ha->bars);
2473 kfree(ha);
2474 ha = NULL;
1da177e4 2475
a1541d5a 2476probe_out:
e315cd28 2477 pci_disable_device(pdev);
a1541d5a 2478 return ret;
1da177e4 2479}
1da177e4 2480
e30d1756
MI		 2481static void
2482qla2x00_shutdown(struct pci_dev *pdev)
2483{
2484 scsi_qla_host_t *vha;
2485 struct qla_hw_data *ha;
2486
2487 vha = pci_get_drvdata(pdev);
2488 ha = vha->hw;
2489
2490 /* Turn-off FCE trace */
2491 if (ha->flags.fce_enabled) {
2492 qla2x00_disable_fce_trace(vha, NULL, NULL);
2493 ha->flags.fce_enabled = 0;
2494 }
2495
2496 /* Turn-off EFT trace */
2497 if (ha->eft)
2498 qla2x00_disable_eft_trace(vha);
2499
2500 /* Stop currently executing firmware. */
2501 qla2x00_try_to_stop_firmware(vha);
2502
2503 /* Turn adapter off line */
2504 vha->flags.online = 0;
2505
2506 /* turn-off interrupts on the card */
2507 if (ha->interrupts_on) {
2508 vha->flags.init_done = 0;
2509 ha->isp_ops->disable_intrs(ha);
2510 }
2511
2512 qla2x00_free_irqs(vha);
2513
2514 qla2x00_free_fw_dump(ha);
2515}
2516
4c993f76 2517static void
7ee61397 2518qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2519{
feafb7b1 2520 scsi_qla_host_t *base_vha, *vha;
e315cd28 2521 struct qla_hw_data *ha;
feafb7b1 2522 unsigned long flags;
e315cd28
AC		 2523
2524 base_vha = pci_get_drvdata(pdev);
2525 ha = base_vha->hw;
2526
43ebf16d
AE		 2527 mutex_lock(&ha->vport_lock);
2528 while (ha->cur_vport_count) {
2529 struct Scsi_Host *scsi_host;
feafb7b1 2530
43ebf16d 2531 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2532
43ebf16d
AE		 2533 BUG_ON(base_vha->list.next == &ha->vp_list);
2534 /* This assumes first entry in ha->vp_list is always base vha */
2535 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2536 scsi_host = scsi_host_get(vha->host);
feafb7b1 2537
43ebf16d
AE		 2538 spin_unlock_irqrestore(&ha->vport_slock, flags);
2539 mutex_unlock(&ha->vport_lock);
2540
2541 fc_vport_terminate(vha->fc_vport);
2542 scsi_host_put(vha->host);
feafb7b1 2543
43ebf16d 2544 mutex_lock(&ha->vport_lock);
e315cd28 2545 }
43ebf16d 2546 mutex_unlock(&ha->vport_lock);
1da177e4 2547
e315cd28 2548 set_bit(UNLOADING, &base_vha->dpc_flags);
1da177e4 2549
b9978769
AV		 2550 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2551
e315cd28 2552 qla2x00_dfs_remove(base_vha);
c795c1e4 2553
e315cd28 2554 qla84xx_put_chip(base_vha);
c795c1e4 2555
b9978769
AV		 2556 /* Disable timer */
2557 if (base_vha->timer_active)
2558 qla2x00_stop_timer(base_vha);
2559
2560 base_vha->flags.online = 0;
2561
68ca949c
AC		 2562 /* Flush the work queue and remove it */
2563 if (ha->wq) {
2564 flush_workqueue(ha->wq);
2565 destroy_workqueue(ha->wq);
2566 ha->wq = NULL;
2567 }
2568
b9978769
AV		 2569 /* Kill the kernel thread for this host */
2570 if (ha->dpc_thread) {
2571 struct task_struct *t = ha->dpc_thread;
2572
2573 /*
2574 * qla2xxx_wake_dpc checks for ->dpc_thread
2575 * so we need to zero it out.
2576 */
2577 ha->dpc_thread = NULL;
2578 kthread_stop(t);
2579 }
2580
e315cd28 2581 qla2x00_free_sysfs_attr(base_vha);
df613b96 2582
e315cd28 2583 fc_remove_host(base_vha->host);
4d4df193 2584
e315cd28 2585 scsi_remove_host(base_vha->host);
1da177e4 2586
e315cd28 2587 qla2x00_free_device(base_vha);
bdf79621 2588
e315cd28 2589 scsi_host_put(base_vha->host);
1da177e4 2590
a9083016 2591 if (IS_QLA82XX(ha)) {
b963752f
GM		 2592 qla82xx_idc_lock(ha);
2593 qla82xx_clear_drv_active(ha);
2594 qla82xx_idc_unlock(ha);
2595
a9083016
GM		 2596 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2597 if (!ql2xdbwr)
2598 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2599 } else {
2600 if (ha->iobase)
2601 iounmap(ha->iobase);
1da177e4 2602
a9083016
GM		 2603 if (ha->mqiobase)
2604 iounmap(ha->mqiobase);
2605 }
73208dfd 2606
e315cd28
AC		 2607 pci_release_selected_regions(ha->pdev, ha->bars);
2608 kfree(ha);
2609 ha = NULL;
1da177e4 2610
90a86fc0
JC		 2611 pci_disable_pcie_error_reporting(pdev);
2612
665db93b 2613 pci_disable_device(pdev);
1da177e4
LT		 2614 pci_set_drvdata(pdev, NULL);
2615}
1da177e4
LT		 2616
2617static void
e315cd28 2618qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2619{
e315cd28 2620 struct qla_hw_data *ha = vha->hw;
1da177e4 2621
85880801
AV		 2622 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2623
2624 /* Disable timer */
2625 if (vha->timer_active)
2626 qla2x00_stop_timer(vha);
2627
2628 /* Kill the kernel thread for this host */
2629 if (ha->dpc_thread) {
2630 struct task_struct *t = ha->dpc_thread;
2631
2632 /*
2633 * qla2xxx_wake_dpc checks for ->dpc_thread
2634 * so we need to zero it out.
2635 */
2636 ha->dpc_thread = NULL;
2637 kthread_stop(t);
2638 }
2639
2afa19a9
AC		 2640 qla25xx_delete_queues(vha);
2641
df613b96 2642 if (ha->flags.fce_enabled)
e315cd28 2643 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2644
a7a167bf 2645 if (ha->eft)
e315cd28 2646 qla2x00_disable_eft_trace(vha);
a7a167bf 2647
f6ef3b18 2648 /* Stop currently executing firmware. */
e315cd28 2649 qla2x00_try_to_stop_firmware(vha);
1da177e4 2650
85880801
AV		 2651 vha->flags.online = 0;
2652
f6ef3b18 2653 /* turn-off interrupts on the card */
a9083016
GM		 2654 if (ha->interrupts_on) {
2655 vha->flags.init_done = 0;
fd34f556 2656 ha->isp_ops->disable_intrs(ha);
a9083016 2657 }
f6ef3b18 2658
e315cd28 2659 qla2x00_free_irqs(vha);
1da177e4 2660
8867048b
CD		 2661 qla2x00_free_fcports(vha);
2662
e315cd28 2663 qla2x00_mem_free(ha);
73208dfd
AC		 2664
2665 qla2x00_free_queues(ha);
1da177e4
LT		 2666}
2667
8867048b
CD		 2668void qla2x00_free_fcports(struct scsi_qla_host *vha)
2669{
2670 fc_port_t *fcport, *tfcport;
2671
2672 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2673 list_del(&fcport->list);
2674 kfree(fcport);
2675 fcport = NULL;
2676 }
2677}
2678
d97994dc 2679static inline void
e315cd28 2680qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 2681 int defer)
2682{
d97994dc 2683 struct fc_rport *rport;
67becc00 2684 scsi_qla_host_t *base_vha;
044d78e1 2685 unsigned long flags;
d97994dc
AV		 2686
2687 if (!fcport->rport)
2688 return;
2689
2690 rport = fcport->rport;
2691 if (defer) {
67becc00 2692 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2693 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2694 fcport->drport = rport;
044d78e1 2695 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2696 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2697 qla2xxx_wake_dpc(base_vha);
5f3a9a20 2698 } else
d97994dc 2699 fc_remote_port_delete(rport);
d97994dc
AV		 2700}
2701
1da177e4
LT		 2702/*
2703 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2704 *
2705 * Input: ha = adapter block pointer. fcport = port structure pointer.
2706 *
2707 * Return: None.
2708 *
2709 * Context:
2710 */
e315cd28 2711void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2712 int do_login, int defer)
1da177e4 2713{
2c3dfe3f 2714 if (atomic_read(&fcport->state) == FCS_ONLINE &&
e315cd28 2715 vha->vp_idx == fcport->vp_idx) {
ec426e10 2716 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2717 qla2x00_schedule_rport_del(vha, fcport, defer);
2718 }
fa2a1ce5 2719 /*
1da177e4
LT		 2720 * We may need to retry the login, so don't change the state of the
2721 * port but do the retries.
2722 */
2723 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2724 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2725
2726 if (!do_login)
2727 return;
2728
2729 if (fcport->login_retry == 0) {
e315cd28
AC		 2730 fcport->login_retry = vha->hw->login_retry_count;
2731 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2732
7c3df132
SK		 2733 ql_dbg(ql_dbg_disc, vha, 0x2067,
2734 "Port login retry "
1da177e4 2735 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2736 "id = 0x%04x retry cnt=%d.\n",
2737 fcport->port_name[0], fcport->port_name[1],
2738 fcport->port_name[2], fcport->port_name[3],
2739 fcport->port_name[4], fcport->port_name[5],
2740 fcport->port_name[6], fcport->port_name[7],
2741 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 2742 }
2743}
2744
2745/*
2746 * qla2x00_mark_all_devices_lost
2747 * Updates fcport state when device goes offline.
2748 *
2749 * Input:
2750 * ha = adapter block pointer.
2751 * fcport = port structure pointer.
2752 *
2753 * Return:
2754 * None.
2755 *
2756 * Context:
2757 */
2758void
e315cd28 2759qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 2760{
2761 fc_port_t *fcport;
2762
e315cd28 2763 list_for_each_entry(fcport, &vha->vp_fcports, list) {
0d6e61bc 2764 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx)
1da177e4 2765 continue;
0d6e61bc 2766
1da177e4
LT		 2767 /*
2768 * No point in marking the device as lost, if the device is
2769 * already DEAD.
2770 */
2771 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
2772 continue;
e315cd28 2773 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 2774 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 2775 if (defer)
2776 qla2x00_schedule_rport_del(vha, fcport, defer);
2777 else if (vha->vp_idx == fcport->vp_idx)
2778 qla2x00_schedule_rport_del(vha, fcport, defer);
2779 }
1da177e4
LT		 2780 }
2781}
2782
2783/*
2784* qla2x00_mem_alloc
2785* Allocates adapter memory.
2786*
2787* Returns:
2788* 0 = success.
e8711085 2789* !0 = failure.
1da177e4 2790*/
e8711085 2791static int
73208dfd
AC		 2792qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
2793 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 2794{
2795 char name[16];
1da177e4 2796
e8711085 2797 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 2798 &ha->init_cb_dma, GFP_KERNEL);
e8711085 2799 if (!ha->init_cb)
e315cd28 2800 goto fail;
e8711085 2801
e315cd28
AC		 2802 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE,
2803 &ha->gid_list_dma, GFP_KERNEL);
2804 if (!ha->gid_list)
e8711085 2805 goto fail_free_init_cb;
1da177e4 2806
e8711085
AV		 2807 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
2808 if (!ha->srb_mempool)
e315cd28 2809 goto fail_free_gid_list;
e8711085 2810
a9083016
GM		 2811 if (IS_QLA82XX(ha)) {
2812 /* Allocate cache for CT6 Ctx. */
2813 if (!ctx_cachep) {
2814 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
2815 sizeof(struct ct6_dsd), 0,
2816 SLAB_HWCACHE_ALIGN, NULL);
2817 if (!ctx_cachep)
2818 goto fail_free_gid_list;
2819 }
2820 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
2821 ctx_cachep);
2822 if (!ha->ctx_mempool)
2823 goto fail_free_srb_mempool;
7c3df132
SK		 2824 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
2825 "ctx_cachep=%p ctx_mempool=%p.\n",
2826 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 2827 }
2828
e8711085
AV		 2829 /* Get memory for cached NVRAM */
2830 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
2831 if (!ha->nvram)
a9083016 2832 goto fail_free_ctx_mempool;
e8711085 2833
e315cd28
AC		 2834 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
2835 ha->pdev->device);
2836 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2837 DMA_POOL_SIZE, 8, 0);
2838 if (!ha->s_dma_pool)
2839 goto fail_free_nvram;
2840
7c3df132
SK		 2841 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
2842 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
2843 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
2844
bad75002 2845 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2846 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2847 DSD_LIST_DMA_POOL_SIZE, 8, 0);
2848 if (!ha->dl_dma_pool) {
7c3df132
SK		 2849 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
2850 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 2851 goto fail_s_dma_pool;
2852 }
2853
2854 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
2855 FCP_CMND_DMA_POOL_SIZE, 8, 0);
2856 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 2857 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
2858 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 2859 goto fail_dl_dma_pool;
2860 }
7c3df132
SK		 2861 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
2862 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
2863 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 2864 }
2865
e8711085
AV		 2866 /* Allocate memory for SNS commands */
2867 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 2868 /* Get consistent memory allocated for SNS commands */
e8711085 2869 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2870 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 2871 if (!ha->sns_cmd)
e315cd28 2872 goto fail_dma_pool;
7c3df132
SK		 2873 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
2874 "sns_cmd.\n", ha->sns_cmd);
e8711085 2875 } else {
e315cd28 2876 /* Get consistent memory allocated for MS IOCB */
e8711085 2877 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 2878 &ha->ms_iocb_dma);
e8711085 2879 if (!ha->ms_iocb)
e315cd28
AC		 2880 goto fail_dma_pool;
2881 /* Get consistent memory allocated for CT SNS commands */
e8711085 2882 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 2883 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 2884 if (!ha->ct_sns)
2885 goto fail_free_ms_iocb;
7c3df132
SK		 2886 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
2887 "ms_iocb=%p ct_sns=%p.\n",
2888 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 2889 }
2890
e315cd28 2891 /* Allocate memory for request ring */
73208dfd
AC		 2892 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
2893 if (!*req) {
7c3df132
SK		 2894 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
2895 "Failed to allocate memory for req.\n");
e315cd28
AC		 2896 goto fail_req;
2897 }
73208dfd
AC		 2898 (*req)->length = req_len;
2899 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
2900 ((*req)->length + 1) * sizeof(request_t),
2901 &(*req)->dma, GFP_KERNEL);
2902 if (!(*req)->ring) {
7c3df132
SK		 2903 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
2904 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 2905 goto fail_req_ring;
2906 }
2907 /* Allocate memory for response ring */
73208dfd
AC		 2908 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
2909 if (!*rsp) {
7c3df132
SK		 2910 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
2911 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 2912 goto fail_rsp;
2913 }
73208dfd
AC		 2914 (*rsp)->hw = ha;
2915 (*rsp)->length = rsp_len;
2916 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
2917 ((*rsp)->length + 1) * sizeof(response_t),
2918 &(*rsp)->dma, GFP_KERNEL);
2919 if (!(*rsp)->ring) {
7c3df132
SK		 2920 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
2921 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 2922 goto fail_rsp_ring;
2923 }
73208dfd
AC		 2924 (*req)->rsp = *rsp;
2925 (*rsp)->req = *req;
7c3df132
SK		 2926 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
2927 "req=%p req->length=%d req->ring=%p rsp=%p "
2928 "rsp->length=%d rsp->ring=%p.\n",
2929 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
2930 (*rsp)->ring);
73208dfd
AC		 2931 /* Allocate memory for NVRAM data for vports */
2932 if (ha->nvram_npiv_size) {
2933 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 2934 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 2935 if (!ha->npiv_info) {
7c3df132
SK		 2936 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
2937 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 2938 goto fail_npiv_info;
2939 }
2940 } else
2941 ha->npiv_info = NULL;
e8711085 2942
b64b0e8f 2943 /* Get consistent memory allocated for EX-INIT-CB. */
a9083016 2944 if (IS_QLA8XXX_TYPE(ha)) {
b64b0e8f
AV		 2945 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2946 &ha->ex_init_cb_dma);
2947 if (!ha->ex_init_cb)
2948 goto fail_ex_init_cb;
7c3df132
SK		 2949 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
2950 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 2951 }
2952
a9083016
GM		 2953 INIT_LIST_HEAD(&ha->gbl_dsd_list);
2954
5ff1d584
AV		 2955 /* Get consistent memory allocated for Async Port-Database. */
2956 if (!IS_FWI2_CAPABLE(ha)) {
2957 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
2958 &ha->async_pd_dma);
2959 if (!ha->async_pd)
2960 goto fail_async_pd;
7c3df132
SK		 2961 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
2962 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 2963 }
2964
e315cd28
AC		 2965 INIT_LIST_HEAD(&ha->vp_list);
2966 return 1;
2967
5ff1d584
AV		 2968fail_async_pd:
2969 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 2970fail_ex_init_cb:
2971 kfree(ha->npiv_info);
73208dfd
AC		 2972fail_npiv_info:
2973 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
2974 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
2975 (*rsp)->ring = NULL;
2976 (*rsp)->dma = 0;
e315cd28 2977fail_rsp_ring:
73208dfd 2978 kfree(*rsp);
e315cd28 2979fail_rsp:
73208dfd
AC		 2980 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
2981 sizeof(request_t), (*req)->ring, (*req)->dma);
2982 (*req)->ring = NULL;
2983 (*req)->dma = 0;
e315cd28 2984fail_req_ring:
73208dfd 2985 kfree(*req);
e315cd28
AC		 2986fail_req:
2987 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
2988 ha->ct_sns, ha->ct_sns_dma);
2989 ha->ct_sns = NULL;
2990 ha->ct_sns_dma = 0;
e8711085
AV		 2991fail_free_ms_iocb:
2992 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
2993 ha->ms_iocb = NULL;
2994 ha->ms_iocb_dma = 0;
e315cd28 2995fail_dma_pool:
bad75002 2996 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 2997 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
2998 ha->fcp_cmnd_dma_pool = NULL;
2999 }
3000fail_dl_dma_pool:
bad75002 3001 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3002 dma_pool_destroy(ha->dl_dma_pool);
3003 ha->dl_dma_pool = NULL;
3004 }
3005fail_s_dma_pool:
e315cd28
AC		 3006 dma_pool_destroy(ha->s_dma_pool);
3007 ha->s_dma_pool = NULL;
e8711085
AV		 3008fail_free_nvram:
3009 kfree(ha->nvram);
3010 ha->nvram = NULL;
a9083016
GM		 3011fail_free_ctx_mempool:
3012 mempool_destroy(ha->ctx_mempool);
3013 ha->ctx_mempool = NULL;
e8711085
AV		 3014fail_free_srb_mempool:
3015 mempool_destroy(ha->srb_mempool);
3016 ha->srb_mempool = NULL;
e8711085
AV		 3017fail_free_gid_list:
3018 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3019 ha->gid_list_dma);
e8711085
AV		 3020 ha->gid_list = NULL;
3021 ha->gid_list_dma = 0;
e315cd28
AC		 3022fail_free_init_cb:
3023 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3024 ha->init_cb_dma);
3025 ha->init_cb = NULL;
3026 ha->init_cb_dma = 0;
e8711085 3027fail:
7c3df132
SK		 3028 ql_log(ql_log_fatal, NULL, 0x0030,
3029 "Memory allocation failure.\n");
e8711085 3030 return -ENOMEM;
1da177e4
LT		 3031}
3032
3033/*
e30d1756
MI		 3034* qla2x00_free_fw_dump
3035* Frees fw dump stuff.
1da177e4
LT		 3036*
3037* Input:
e30d1756 3038* ha = adapter block pointer.
1da177e4 3039*/
a824ebb3 3040static void
e30d1756 3041qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3042{
df613b96
AV		 3043 if (ha->fce)
3044 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3045 ha->fce_dma);
df613b96 3046
a7a167bf
AV		 3047 if (ha->fw_dump) {
3048 if (ha->eft)
3049 dma_free_coherent(&ha->pdev->dev,
e30d1756 3050 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3051 vfree(ha->fw_dump);
3052 }
e30d1756
MI		 3053 ha->fce = NULL;
3054 ha->fce_dma = 0;
3055 ha->eft = NULL;
3056 ha->eft_dma = 0;
3057 ha->fw_dump = NULL;
3058 ha->fw_dumped = 0;
3059 ha->fw_dump_reading = 0;
3060}
3061
3062/*
3063* qla2x00_mem_free
3064* Frees all adapter allocated memory.
3065*
3066* Input:
3067* ha = adapter block pointer.
3068*/
3069static void
3070qla2x00_mem_free(struct qla_hw_data *ha)
3071{
3072 qla2x00_free_fw_dump(ha);
3073
3074 if (ha->srb_mempool)
3075 mempool_destroy(ha->srb_mempool);
a7a167bf 3076
11bbc1d8
AV		 3077 if (ha->dcbx_tlv)
3078 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3079 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3080
ce0423f4
AV		 3081 if (ha->xgmac_data)
3082 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3083 ha->xgmac_data, ha->xgmac_data_dma);
3084
1da177e4
LT		 3085 if (ha->sns_cmd)
3086 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3087 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3088
3089 if (ha->ct_sns)
3090 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3091 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3092
88729e53
AV		 3093 if (ha->sfp_data)
3094 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3095
ad0ecd61
JC		 3096 if (ha->edc_data)
3097 dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma);
3098
1da177e4
LT		 3099 if (ha->ms_iocb)
3100 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3101
b64b0e8f 3102 if (ha->ex_init_cb)
a9083016
GM		 3103 dma_pool_free(ha->s_dma_pool,
3104 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3105
5ff1d584
AV		 3106 if (ha->async_pd)
3107 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3108
1da177e4
LT		 3109 if (ha->s_dma_pool)
3110 dma_pool_destroy(ha->s_dma_pool);
3111
1da177e4
LT		 3112 if (ha->gid_list)
3113 dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list,
e315cd28 3114 ha->gid_list_dma);
1da177e4 3115
a9083016
GM		 3116 if (IS_QLA82XX(ha)) {
3117 if (!list_empty(&ha->gbl_dsd_list)) {
3118 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3119
3120 /* clean up allocated prev pool */
3121 list_for_each_entry_safe(dsd_ptr,
3122 tdsd_ptr, &ha->gbl_dsd_list, list) {
3123 dma_pool_free(ha->dl_dma_pool,
3124 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3125 list_del(&dsd_ptr->list);
3126 kfree(dsd_ptr);
3127 }
3128 }
3129 }
3130
3131 if (ha->dl_dma_pool)
3132 dma_pool_destroy(ha->dl_dma_pool);
3133
3134 if (ha->fcp_cmnd_dma_pool)
3135 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3136
3137 if (ha->ctx_mempool)
3138 mempool_destroy(ha->ctx_mempool);
3139
e315cd28
AC		 3140 if (ha->init_cb)
3141 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3142 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3143 vfree(ha->optrom_buffer);
3144 kfree(ha->nvram);
73208dfd 3145 kfree(ha->npiv_info);
1da177e4 3146
e8711085 3147 ha->srb_mempool = NULL;
a9083016 3148 ha->ctx_mempool = NULL;
1da177e4
LT		 3149 ha->sns_cmd = NULL;
3150 ha->sns_cmd_dma = 0;
3151 ha->ct_sns = NULL;
3152 ha->ct_sns_dma = 0;
3153 ha->ms_iocb = NULL;
3154 ha->ms_iocb_dma = 0;
1da177e4
LT		 3155 ha->init_cb = NULL;
3156 ha->init_cb_dma = 0;
b64b0e8f
AV		 3157 ha->ex_init_cb = NULL;
3158 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3159 ha->async_pd = NULL;
3160 ha->async_pd_dma = 0;
1da177e4
LT		 3161
3162 ha->s_dma_pool = NULL;
a9083016
GM		 3163 ha->dl_dma_pool = NULL;
3164 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3165
1da177e4
LT		 3166 ha->gid_list = NULL;
3167 ha->gid_list_dma = 0;
e315cd28 3168}
1da177e4 3169
e315cd28
AC		 3170struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3171 struct qla_hw_data *ha)
3172{
3173 struct Scsi_Host *host;
3174 struct scsi_qla_host *vha = NULL;
854165f4 3175
e315cd28
AC		 3176 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3177 if (host == NULL) {
7c3df132
SK		 3178 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3179 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3180 goto fail;
3181 }
3182
3183 /* Clear our data area */
3184 vha = shost_priv(host);
3185 memset(vha, 0, sizeof(scsi_qla_host_t));
3186
3187 vha->host = host;
3188 vha->host_no = host->host_no;
3189 vha->hw = ha;
3190
3191 INIT_LIST_HEAD(&vha->vp_fcports);
3192 INIT_LIST_HEAD(&vha->work_list);
3193 INIT_LIST_HEAD(&vha->list);
3194
f999f4c1
AV		 3195 spin_lock_init(&vha->work_lock);
3196
e315cd28 3197 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3198 ql_dbg(ql_dbg_init, vha, 0x0041,
3199 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3200 vha->host, vha->hw, vha,
3201 dev_name(&(ha->pdev->dev)));
3202
e315cd28
AC		 3203 return vha;
3204
3205fail:
3206 return vha;
1da177e4
LT		 3207}
3208
01ef66bb 3209static struct qla_work_evt *
f999f4c1 3210qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3211{
3212 struct qla_work_evt *e;
feafb7b1
AE		 3213 uint8_t bail;
3214
3215 QLA_VHA_MARK_BUSY(vha, bail);
3216 if (bail)
3217 return NULL;
0971de7f 3218
f999f4c1 3219 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3220 if (!e) {
3221 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3222 return NULL;
feafb7b1 3223 }
0971de7f
AV		 3224
3225 INIT_LIST_HEAD(&e->list);
3226 e->type = type;
3227 e->flags = QLA_EVT_FLAG_FREE;
3228 return e;
3229}
3230
01ef66bb 3231static int
f999f4c1 3232qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3233{
f999f4c1 3234 unsigned long flags;
0971de7f 3235
f999f4c1 3236 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3237 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3238 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3239 qla2xxx_wake_dpc(vha);
f999f4c1 3240
0971de7f
AV		 3241 return QLA_SUCCESS;
3242}
3243
3244int
e315cd28 3245qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3246 u32 data)
3247{
3248 struct qla_work_evt *e;
3249
f999f4c1 3250 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3251 if (!e)
3252 return QLA_FUNCTION_FAILED;
3253
3254 e->u.aen.code = code;
3255 e->u.aen.data = data;
f999f4c1 3256 return qla2x00_post_work(vha, e);
0971de7f
AV		 3257}
3258
8a659571
AV		 3259int
3260qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3261{
3262 struct qla_work_evt *e;
3263
f999f4c1 3264 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3265 if (!e)
3266 return QLA_FUNCTION_FAILED;
3267
3268 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3269 return qla2x00_post_work(vha, e);
8a659571
AV		 3270}
3271
ac280b67
AV		 3272#define qla2x00_post_async_work(name, type) \
3273int qla2x00_post_async_##name##_work( \
3274 struct scsi_qla_host *vha, \
3275 fc_port_t *fcport, uint16_t *data) \
3276{ \
3277 struct qla_work_evt *e; \
3278 \
3279 e = qla2x00_alloc_work(vha, type); \
3280 if (!e) \
3281 return QLA_FUNCTION_FAILED; \
3282 \
3283 e->u.logio.fcport = fcport; \
3284 if (data) { \
3285 e->u.logio.data[0] = data[0]; \
3286 e->u.logio.data[1] = data[1]; \
3287 } \
3288 return qla2x00_post_work(vha, e); \
3289}
3290
3291qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3292qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3293qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3294qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3295qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3296qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3297
3420d36c
AV		 3298int
3299qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3300{
3301 struct qla_work_evt *e;
3302
3303 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3304 if (!e)
3305 return QLA_FUNCTION_FAILED;
3306
3307 e->u.uevent.code = code;
3308 return qla2x00_post_work(vha, e);
3309}
3310
3311static void
3312qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3313{
3314 char event_string[40];
3315 char *envp[] = { event_string, NULL };
3316
3317 switch (code) {
3318 case QLA_UEVENT_CODE_FW_DUMP:
3319 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3320 vha->host_no);
3321 break;
3322 default:
3323 /* do nothing */
3324 break;
3325 }
3326 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3327}
3328
ac280b67 3329void
e315cd28 3330qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3331{
f999f4c1
AV		 3332 struct qla_work_evt *e, *tmp;
3333 unsigned long flags;
3334 LIST_HEAD(work);
0971de7f 3335
f999f4c1
AV		 3336 spin_lock_irqsave(&vha->work_lock, flags);
3337 list_splice_init(&vha->work_list, &work);
3338 spin_unlock_irqrestore(&vha->work_lock, flags);
3339
3340 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3341 list_del_init(&e->list);
0971de7f
AV		 3342
3343 switch (e->type) {
3344 case QLA_EVT_AEN:
e315cd28 3345 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3346 e->u.aen.code, e->u.aen.data);
3347 break;
8a659571
AV		 3348 case QLA_EVT_IDC_ACK:
3349 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3350 break;
ac280b67
AV		 3351 case QLA_EVT_ASYNC_LOGIN:
3352 qla2x00_async_login(vha, e->u.logio.fcport,
3353 e->u.logio.data);
3354 break;
3355 case QLA_EVT_ASYNC_LOGIN_DONE:
3356 qla2x00_async_login_done(vha, e->u.logio.fcport,
3357 e->u.logio.data);
3358 break;
3359 case QLA_EVT_ASYNC_LOGOUT:
3360 qla2x00_async_logout(vha, e->u.logio.fcport);
3361 break;
3362 case QLA_EVT_ASYNC_LOGOUT_DONE:
3363 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3364 e->u.logio.data);
3365 break;
5ff1d584
AV		 3366 case QLA_EVT_ASYNC_ADISC:
3367 qla2x00_async_adisc(vha, e->u.logio.fcport,
3368 e->u.logio.data);
3369 break;
3370 case QLA_EVT_ASYNC_ADISC_DONE:
3371 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3372 e->u.logio.data);
3373 break;
3420d36c
AV		 3374 case QLA_EVT_UEVENT:
3375 qla2x00_uevent_emit(vha, e->u.uevent.code);
3376 break;
0971de7f
AV		 3377 }
3378 if (e->flags & QLA_EVT_FLAG_FREE)
3379 kfree(e);
feafb7b1
AE		 3380
3381 /* For each work completed decrement vha ref count */
3382 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3383 }
e315cd28 3384}
f999f4c1 3385
e315cd28
AC		 3386/* Relogins all the fcports of a vport
3387 * Context: dpc thread
3388 */
3389void qla2x00_relogin(struct scsi_qla_host *vha)
3390{
3391 fc_port_t *fcport;
c6b2fca8 3392 int status;
e315cd28
AC		 3393 uint16_t next_loopid = 0;
3394 struct qla_hw_data *ha = vha->hw;
ac280b67 3395 uint16_t data[2];
e315cd28
AC		 3396
3397 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3398 /*
3399 * If the port is not ONLINE then try to login
3400 * to it if we haven't run out of retries.
3401 */
5ff1d584
AV		 3402 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3403 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3404 fcport->login_retry--;
e315cd28 3405 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3406 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3407 ha->isp_ops->fabric_logout(vha,
3408 fcport->loop_id,
3409 fcport->d_id.b.domain,
3410 fcport->d_id.b.area,
3411 fcport->d_id.b.al_pa);
3412
03bcfb57
JC		 3413 if (fcport->loop_id == FC_NO_LOOP_ID) {
3414 fcport->loop_id = next_loopid =
3415 ha->min_external_loopid;
3416 status = qla2x00_find_new_loop_id(
3417 vha, fcport);
3418 if (status != QLA_SUCCESS) {
3419 /* Ran out of IDs to use */
3420 break;
3421 }
3422 }
3423
ac280b67 3424 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3425 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3426 data[0] = 0;
3427 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3428 status = qla2x00_post_async_login_work(
3429 vha, fcport, data);
3430 if (status == QLA_SUCCESS)
3431 continue;
3432 /* Attempt a retry. */
3433 status = 1;
3434 } else
3435 status = qla2x00_fabric_login(vha,
3436 fcport, &next_loopid);
e315cd28
AC		 3437 } else
3438 status = qla2x00_local_device_login(vha,
3439 fcport);
3440
e315cd28
AC		 3441 if (status == QLA_SUCCESS) {
3442 fcport->old_loop_id = fcport->loop_id;
3443
7c3df132
SK		 3444 ql_dbg(ql_dbg_disc, vha, 0x2003,
3445 "Port login OK: logged in ID 0x%x.\n",
3446 fcport->loop_id);
e315cd28
AC		 3447
3448 qla2x00_update_fcport(vha, fcport);
3449
3450 } else if (status == 1) {
3451 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3452 /* retry the login again */
7c3df132
SK		 3453 ql_dbg(ql_dbg_disc, vha, 0x2007,
3454 "Retrying %d login again loop_id 0x%x.\n",
3455 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3456 } else {
3457 fcport->login_retry = 0;
3458 }
3459
3460 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
3461 fcport->loop_id = FC_NO_LOOP_ID;
3462 }
3463 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3464 break;
0971de7f 3465 }
0971de7f
AV		 3466}
3467
1da177e4
LT		 3468/**************************************************************************
3469* qla2x00_do_dpc
3470* This kernel thread is a task that is schedule by the interrupt handler
3471* to perform the background processing for interrupts.
3472*
3473* Notes:
3474* This task always run in the context of a kernel thread. It
3475* is kick-off by the driver's detect code and starts up
3476* up one per adapter. It immediately goes to sleep and waits for
3477* some fibre event. When either the interrupt handler or
3478* the timer routine detects a event it will one of the task
3479* bits then wake us up.
3480**************************************************************************/
3481static int
3482qla2x00_do_dpc(void *data)
3483{
2c3dfe3f 3484 int rval;
e315cd28
AC		 3485 scsi_qla_host_t *base_vha;
3486 struct qla_hw_data *ha;
1da177e4 3487
e315cd28
AC		 3488 ha = (struct qla_hw_data *)data;
3489 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 3490
1da177e4
LT		 3491 set_user_nice(current, -20);
3492
563585ec 3493 set_current_state(TASK_INTERRUPTIBLE);
39a11240 3494 while (!kthread_should_stop()) {
7c3df132
SK		 3495 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
3496 "DPC handler sleeping.\n");
1da177e4 3497
39a11240
CH		 3498 schedule();
3499 __set_current_state(TASK_RUNNING);
1da177e4 3500
7c3df132
SK		 3501 ql_dbg(ql_dbg_dpc, base_vha, 0x4001,
3502 "DPC handler waking up.\n");
3503 ql_dbg(ql_dbg_dpc, base_vha, 0x4002,
3504 "dpc_flags=0x%lx.\n", base_vha->dpc_flags);
1da177e4
LT		 3505
3506 /* Initialization not yet finished. Don't do anything yet. */
e315cd28 3507 if (!base_vha->flags.init_done)
1da177e4
LT		 3508 continue;
3509
85880801 3510 if (ha->flags.eeh_busy) {
7c3df132
SK		 3511 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
3512 "eeh_busy=%d.\n", ha->flags.eeh_busy);
85880801
AV		 3513 continue;
3514 }
3515
1da177e4
LT		 3516 ha->dpc_active = 1;
3517
1da177e4 3518 if (ha->flags.mbox_busy) {
1da177e4
LT		 3519 ha->dpc_active = 0;
3520 continue;
3521 }
3522
e315cd28 3523 qla2x00_do_work(base_vha);
0971de7f 3524
a9083016
GM		 3525 if (IS_QLA82XX(ha)) {
3526 if (test_and_clear_bit(ISP_UNRECOVERABLE,
3527 &base_vha->dpc_flags)) {
3528 qla82xx_idc_lock(ha);
3529 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3530 QLA82XX_DEV_FAILED);
3531 qla82xx_idc_unlock(ha);
7c3df132
SK		 3532 ql_log(ql_log_info, base_vha, 0x4004,
3533 "HW State: FAILED.\n");
a9083016
GM		 3534 qla82xx_device_state_handler(base_vha);
3535 continue;
3536 }
3537
3538 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
3539 &base_vha->dpc_flags)) {
3540
7c3df132
SK		 3541 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
3542 "FCoE context reset scheduled.\n");
a9083016
GM		 3543 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
3544 &base_vha->dpc_flags))) {
3545 if (qla82xx_fcoe_ctx_reset(base_vha)) {
3546 /* FCoE-ctx reset failed.
3547 * Escalate to chip-reset
3548 */
3549 set_bit(ISP_ABORT_NEEDED,
3550 &base_vha->dpc_flags);
3551 }
3552 clear_bit(ABORT_ISP_ACTIVE,
3553 &base_vha->dpc_flags);
3554 }
3555
7c3df132
SK		 3556 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
3557 "FCoE context reset end.\n");
a9083016
GM		 3558 }
3559 }
3560
e315cd28
AC		 3561 if (test_and_clear_bit(ISP_ABORT_NEEDED,
3562 &base_vha->dpc_flags)) {
1da177e4 3563
7c3df132
SK		 3564 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
3565 "ISP abort scheduled.\n");
1da177e4 3566 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 3567 &base_vha->dpc_flags))) {
1da177e4 3568
a9083016 3569 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 3570 /* failed. retry later */
3571 set_bit(ISP_ABORT_NEEDED,
e315cd28 3572 &base_vha->dpc_flags);
99363ef8 3573 }
e315cd28
AC		 3574 clear_bit(ABORT_ISP_ACTIVE,
3575 &base_vha->dpc_flags);
99363ef8
SJ		 3576 }
3577
7c3df132
SK		 3578 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
3579 "ISP abort end.\n");
1da177e4
LT		 3580 }
3581
e315cd28
AC		 3582 if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) {
3583 qla2x00_update_fcports(base_vha);
3584 clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
c9c5ced9 3585 }
d97994dc 3586
579d12b5 3587 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 3588 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
3589 "Quiescence mode scheduled.\n");
579d12b5
SK		 3590 qla82xx_device_state_handler(base_vha);
3591 clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags);
3592 if (!ha->flags.quiesce_owner) {
3593 qla2x00_perform_loop_resync(base_vha);
3594
3595 qla82xx_idc_lock(ha);
3596 qla82xx_clear_qsnt_ready(base_vha);
3597 qla82xx_idc_unlock(ha);
3598 }
7c3df132
SK		 3599 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
3600 "Quiescence mode end.\n");
579d12b5
SK		 3601 }
3602
e315cd28
AC		 3603 if (test_and_clear_bit(RESET_MARKER_NEEDED,
3604 &base_vha->dpc_flags) &&
3605 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 3606
7c3df132
SK		 3607 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
3608 "Reset marker scheduled.\n");
e315cd28
AC		 3609 qla2x00_rst_aen(base_vha);
3610 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 3611 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
3612 "Reset marker end.\n");
1da177e4
LT		 3613 }
3614
3615 /* Retry each device up to login retry count */
e315cd28
AC		 3616 if ((test_and_clear_bit(RELOGIN_NEEDED,
3617 &base_vha->dpc_flags)) &&
3618 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
3619 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 3620
7c3df132
SK		 3621 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
3622 "Relogin scheduled.\n");
e315cd28 3623 qla2x00_relogin(base_vha);
7c3df132
SK		 3624 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
3625 "Relogin end.\n");
1da177e4
LT		 3626 }
3627
e315cd28
AC		 3628 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
3629 &base_vha->dpc_flags)) {
1da177e4 3630
7c3df132
SK		 3631 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
3632 "Loop resync scheduled.\n");
1da177e4
LT		 3633
3634 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 3635 &base_vha->dpc_flags))) {
1da177e4 3636
e315cd28 3637 rval = qla2x00_loop_resync(base_vha);
1da177e4 3638
e315cd28
AC		 3639 clear_bit(LOOP_RESYNC_ACTIVE,
3640 &base_vha->dpc_flags);
1da177e4
LT		 3641 }
3642
7c3df132
SK		 3643 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
3644 "Loop resync end.\n");
1da177e4
LT		 3645 }
3646
e315cd28
AC		 3647 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
3648 atomic_read(&base_vha->loop_state) == LOOP_READY) {
3649 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
3650 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 3651 }
3652
1da177e4 3653 if (!ha->interrupts_on)
fd34f556 3654 ha->isp_ops->enable_intrs(ha);
1da177e4 3655
e315cd28
AC		 3656 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
3657 &base_vha->dpc_flags))
3658 ha->isp_ops->beacon_blink(base_vha);
f6df144c 3659
e315cd28 3660 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 3661
1da177e4 3662 ha->dpc_active = 0;
563585ec 3663 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 3664 } /* End of while(1) */
563585ec 3665 __set_current_state(TASK_RUNNING);
1da177e4 3666
7c3df132
SK		 3667 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
3668 "DPC handler exiting.\n");
1da177e4
LT		 3669
3670 /*
3671 * Make sure that nobody tries to wake us up again.
3672 */
1da177e4
LT		 3673 ha->dpc_active = 0;
3674
ac280b67
AV		 3675 /* Cleanup any residual CTX SRBs. */
3676 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3677
39a11240
CH		 3678 return 0;
3679}
3680
3681void
e315cd28 3682qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 3683{
e315cd28 3684 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 3685 struct task_struct *t = ha->dpc_thread;
3686
e315cd28 3687 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 3688 wake_up_process(t);
1da177e4
LT		 3689}
3690
1da177e4
LT		 3691/*
3692* qla2x00_rst_aen
3693* Processes asynchronous reset.
3694*
3695* Input:
3696* ha = adapter block pointer.
3697*/
3698static void
e315cd28 3699qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 3700{
e315cd28
AC		 3701 if (vha->flags.online && !vha->flags.reset_active &&
3702 !atomic_read(&vha->loop_down_timer) &&
3703 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 3704 do {
e315cd28 3705 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3706
3707 /*
3708 * Issue marker command only when we are going to start
3709 * the I/O.
3710 */
e315cd28
AC		 3711 vha->marker_needed = 1;
3712 } while (!atomic_read(&vha->loop_down_timer) &&
3713 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 3714 }
3715}
3716
f4f051eb 3717static void
e315cd28 3718qla2x00_sp_free_dma(srb_t *sp)
f4f051eb
AV		 3719{
3720 struct scsi_cmnd *cmd = sp->cmd;
bad75002 3721 struct qla_hw_data *ha = sp->fcport->vha->hw;
f4f051eb
AV		 3722
3723 if (sp->flags & SRB_DMA_VALID) {
385d70b4 3724 scsi_dma_unmap(cmd);
f4f051eb
AV		 3725 sp->flags &= ~SRB_DMA_VALID;
3726 }
bad75002
AE		 3727
3728 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
3729 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
3730 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
3731 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
3732 }
3733
3734 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
3735 /* List assured to be having elements */
3736 qla2x00_clean_dsd_pool(ha, sp);
3737 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
3738 }
3739
3740 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
3741 dma_pool_free(ha->dl_dma_pool, sp->ctx,
3742 ((struct crc_context *)sp->ctx)->crc_ctx_dma);
3743 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
3744 }
3745
fca29703 3746 CMD_SP(cmd) = NULL;
f4f051eb
AV		 3747}
3748
3dbe756a 3749static void
083a469d 3750qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp)
f4f051eb
AV		 3751{
3752 struct scsi_cmnd *cmd = sp->cmd;
3753
e315cd28 3754 qla2x00_sp_free_dma(sp);
f4f051eb 3755
a9083016
GM		 3756 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
3757 struct ct6_dsd *ctx = sp->ctx;
3758 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd,
3759 ctx->fcp_cmnd_dma);
3760 list_splice(&ctx->dsd_list, &ha->gbl_dsd_list);
3761 ha->gbl_dsd_inuse -= ctx->dsd_use_cnt;
3762 ha->gbl_dsd_avail += ctx->dsd_use_cnt;
3763 mempool_free(sp->ctx, ha->ctx_mempool);
3764 sp->ctx = NULL;
3765 }
f4f051eb 3766
a9083016 3767 mempool_free(sp, ha->srb_mempool);
f4f051eb
AV		 3768 cmd->scsi_done(cmd);
3769}
bdf79621 3770
083a469d
GM		 3771void
3772qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp)
3773{
3774 if (atomic_read(&sp->ref_count) == 0) {
7c3df132
SK		 3775 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
3776 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
3777 sp, sp->cmd);
3778 if (ql2xextended_error_logging & ql_dbg_io)
3779 BUG();
083a469d
GM		 3780 return;
3781 }
3782 if (!atomic_dec_and_test(&sp->ref_count))
3783 return;
3784 qla2x00_sp_final_compl(ha, sp);
3785}
3786
1da177e4
LT		 3787/**************************************************************************
3788* qla2x00_timer
3789*
3790* Description:
3791* One second timer
3792*
3793* Context: Interrupt
3794***************************************************************************/
2c3dfe3f 3795void
e315cd28 3796qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 3797{
1da177e4 3798 unsigned long cpu_flags = 0;
1da177e4
LT		 3799 int start_dpc = 0;
3800 int index;
3801 srb_t *sp;
85880801 3802 uint16_t w;
e315cd28 3803 struct qla_hw_data *ha = vha->hw;
73208dfd 3804 struct req_que *req;
85880801 3805
a5b36321 3806 if (ha->flags.eeh_busy) {
7c3df132
SK		 3807 ql_dbg(ql_dbg_timer, vha, 0x6000,
3808 "EEH = %d, restarting timer.\n",
3809 ha->flags.eeh_busy);
a5b36321
LC		 3810 qla2x00_restart_timer(vha, WATCH_INTERVAL);
3811 return;
3812 }
3813
85880801
AV		 3814 /* Hardware read to raise pending EEH errors during mailbox waits. */
3815 if (!pci_channel_offline(ha->pdev))
3816 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 3817
cefcaba6
SK		 3818 /* Make sure qla82xx_watchdog is run only for physical port */
3819 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 3820 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
3821 start_dpc++;
3822 qla82xx_watchdog(vha);
3823 }
3824
1da177e4 3825 /* Loop down handler. */
e315cd28 3826 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 3827 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
3828 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 3829 && vha->flags.online) {
1da177e4 3830
e315cd28
AC		 3831 if (atomic_read(&vha->loop_down_timer) ==
3832 vha->loop_down_abort_time) {
1da177e4 3833
7c3df132
SK		 3834 ql_log(ql_log_info, vha, 0x6008,
3835 "Loop down - aborting the queues before time expires.\n");
1da177e4 3836
e315cd28
AC		 3837 if (!IS_QLA2100(ha) && vha->link_down_timeout)
3838 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 3839
f08b7251
AV		 3840 /*
3841 * Schedule an ISP abort to return any FCP2-device
3842 * commands.
3843 */
2c3dfe3f 3844 /* NPIV - scan physical port only */
e315cd28 3845 if (!vha->vp_idx) {
2c3dfe3f
SJ		 3846 spin_lock_irqsave(&ha->hardware_lock,
3847 cpu_flags);
73208dfd 3848 req = ha->req_q_map[0];
2c3dfe3f
SJ		 3849 for (index = 1;
3850 index < MAX_OUTSTANDING_COMMANDS;
3851 index++) {
3852 fc_port_t *sfcp;
3853
e315cd28 3854 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 3855 if (!sp)
3856 continue;
bad75002 3857 if (sp->ctx && !IS_PROT_IO(sp))
cf53b069 3858 continue;
2c3dfe3f 3859 sfcp = sp->fcport;
f08b7251 3860 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 3861 continue;
bdf79621 3862
8f7daead
GM		 3863 if (IS_QLA82XX(ha))
3864 set_bit(FCOE_CTX_RESET_NEEDED,
3865 &vha->dpc_flags);
3866 else
3867 set_bit(ISP_ABORT_NEEDED,
e315cd28 3868 &vha->dpc_flags);
2c3dfe3f
SJ		 3869 break;
3870 }
3871 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 3872 cpu_flags);
1da177e4 3873 }
1da177e4
LT		 3874 start_dpc++;
3875 }
3876
3877 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 3878 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 3879 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 3880 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 3881 "Loop down - aborting ISP.\n");
3882
8f7daead
GM		 3883 if (IS_QLA82XX(ha))
3884 set_bit(FCOE_CTX_RESET_NEEDED,
3885 &vha->dpc_flags);
3886 else
3887 set_bit(ISP_ABORT_NEEDED,
3888 &vha->dpc_flags);
1da177e4
LT		 3889 }
3890 }
7c3df132
SK		 3891 ql_dbg(ql_dbg_timer, vha, 0x600a,
3892 "Loop down - seconds remaining %d.\n",
3893 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 3894 }
3895
cefcaba6
SK		 3896 /* Check if beacon LED needs to be blinked for physical host only */
3897 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
e315cd28 3898 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
f6df144c
AV		 3899 start_dpc++;
3900 }
3901
550bf57d 3902 /* Process any deferred work. */
e315cd28 3903 if (!list_empty(&vha->work_list))
550bf57d
AV		 3904 start_dpc++;
3905
1da177e4 3906 /* Schedule the DPC routine if needed */
e315cd28
AC		 3907 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
3908 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
3909 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 3910 start_dpc ||
e315cd28
AC		 3911 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
3912 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 3913 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
3914 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 3915 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 3916 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
3917 ql_dbg(ql_dbg_timer, vha, 0x600b,
3918 "isp_abort_needed=%d loop_resync_needed=%d "
3919 "fcport_update_needed=%d start_dpc=%d "
3920 "reset_marker_needed=%d",
3921 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
3922 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
3923 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
3924 start_dpc,
3925 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
3926 ql_dbg(ql_dbg_timer, vha, 0x600c,
3927 "beacon_blink_needed=%d isp_unrecoverable=%d "
3928 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3929 "relogin_needed=%d.\n",
3930 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
3931 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
3932 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
3933 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3934 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 3935 qla2xxx_wake_dpc(vha);
7c3df132 3936 }
1da177e4 3937
e315cd28 3938 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 3939}
3940
5433383e
AV		 3941/* Firmware interface routines. */
3942
a9083016 3943#define FW_BLOBS 8
5433383e
AV		 3944#define FW_ISP21XX 0
3945#define FW_ISP22XX 1
3946#define FW_ISP2300 2
3947#define FW_ISP2322 3
48c02fde 3948#define FW_ISP24XX 4
c3a2f0df 3949#define FW_ISP25XX 5
3a03eb79 3950#define FW_ISP81XX 6
a9083016 3951#define FW_ISP82XX 7
5433383e 3952
bb8ee499
AV		 3953#define FW_FILE_ISP21XX "ql2100_fw.bin"
3954#define FW_FILE_ISP22XX "ql2200_fw.bin"
3955#define FW_FILE_ISP2300 "ql2300_fw.bin"
3956#define FW_FILE_ISP2322 "ql2322_fw.bin"
3957#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 3958#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 3959#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 3960#define FW_FILE_ISP82XX "ql8200_fw.bin"
bb8ee499 3961
e1e82b6f 3962static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 3963
3964static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 3965 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
3966 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
3967 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
3968 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
3969 { .name = FW_FILE_ISP24XX, },
c3a2f0df 3970 { .name = FW_FILE_ISP25XX, },
3a03eb79 3971 { .name = FW_FILE_ISP81XX, },
a9083016 3972 { .name = FW_FILE_ISP82XX, },
5433383e
AV		 3973};
3974
3975struct fw_blob *
e315cd28 3976qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 3977{
e315cd28 3978 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 3979 struct fw_blob *blob;
3980
3981 blob = NULL;
3982 if (IS_QLA2100(ha)) {
3983 blob = &qla_fw_blobs[FW_ISP21XX];
3984 } else if (IS_QLA2200(ha)) {
3985 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 3986 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 3987 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 3988 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 3989 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 3990 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 3991 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 3992 } else if (IS_QLA25XX(ha)) {
3993 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 3994 } else if (IS_QLA81XX(ha)) {
3995 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 3996 } else if (IS_QLA82XX(ha)) {
3997 blob = &qla_fw_blobs[FW_ISP82XX];
5433383e
AV		 3998 }
3999
e1e82b6f 4000 mutex_lock(&qla_fw_lock);
5433383e
AV		 4001 if (blob->fw)
4002 goto out;
4003
4004 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4005 ql_log(ql_log_warn, vha, 0x0063,
4006 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4007 blob->fw = NULL;
4008 blob = NULL;
4009 goto out;
4010 }
4011
4012out:
e1e82b6f 4013 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4014 return blob;
4015}
4016
4017static void
4018qla2x00_release_firmware(void)
4019{
4020 int idx;
4021
e1e82b6f 4022 mutex_lock(&qla_fw_lock);
5433383e
AV		 4023 for (idx = 0; idx < FW_BLOBS; idx++)
4024 if (qla_fw_blobs[idx].fw)
4025 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4026 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4027}
4028
14e660e6
SJ		 4029static pci_ers_result_t
4030qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4031{
85880801
AV		 4032 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4033 struct qla_hw_data *ha = vha->hw;
4034
7c3df132
SK		 4035 ql_dbg(ql_dbg_aer, vha, 0x9000,
4036 "PCI error detected, state %x.\n", state);
b9b12f73 4037
14e660e6
SJ		 4038 switch (state) {
4039 case pci_channel_io_normal:
85880801 4040 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4041 return PCI_ERS_RESULT_CAN_RECOVER;
4042 case pci_channel_io_frozen:
85880801 4043 ha->flags.eeh_busy = 1;
a5b36321
LC		 4044 /* For ISP82XX complete any pending mailbox cmd */
4045 if (IS_QLA82XX(ha)) {
7190575f 4046 ha->flags.isp82xx_fw_hung = 1;
a5b36321
LC		 4047 if (ha->flags.mbox_busy) {
4048 ha->flags.mbox_int = 1;
7c3df132
SK		 4049 ql_dbg(ql_dbg_aer, vha, 0x9001,
4050 "Due to pci channel io frozen, doing premature "
4051 "completion of mbx command.\n");
a5b36321
LC		 4052 complete(&ha->mbx_intr_comp);
4053 }
4054 }
90a86fc0 4055 qla2x00_free_irqs(vha);
14e660e6 4056 pci_disable_device(pdev);
bddd2d65
LC		 4057 /* Return back all IOs */
4058 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4059 return PCI_ERS_RESULT_NEED_RESET;
4060 case pci_channel_io_perm_failure:
85880801
AV		 4061 ha->flags.pci_channel_io_perm_failure = 1;
4062 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4063 return PCI_ERS_RESULT_DISCONNECT;
4064 }
4065 return PCI_ERS_RESULT_NEED_RESET;
4066}
4067
4068static pci_ers_result_t
4069qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4070{
4071 int risc_paused = 0;
4072 uint32_t stat;
4073 unsigned long flags;
e315cd28
AC		 4074 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4075 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4076 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4077 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4078
bcc5b6d3
SK		 4079 if (IS_QLA82XX(ha))
4080 return PCI_ERS_RESULT_RECOVERED;
4081
14e660e6
SJ		 4082 spin_lock_irqsave(&ha->hardware_lock, flags);
4083 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4084 stat = RD_REG_DWORD(&reg->hccr);
4085 if (stat & HCCR_RISC_PAUSE)
4086 risc_paused = 1;
4087 } else if (IS_QLA23XX(ha)) {
4088 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4089 if (stat & HSR_RISC_PAUSED)
4090 risc_paused = 1;
4091 } else if (IS_FWI2_CAPABLE(ha)) {
4092 stat = RD_REG_DWORD(&reg24->host_status);
4093 if (stat & HSRX_RISC_PAUSED)
4094 risc_paused = 1;
4095 }
4096 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4097
4098 if (risc_paused) {
7c3df132
SK		 4099 ql_log(ql_log_info, base_vha, 0x9003,
4100 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4101 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4102
4103 return PCI_ERS_RESULT_NEED_RESET;
4104 } else
4105 return PCI_ERS_RESULT_RECOVERED;
4106}
4107
a5b36321
LC		 4108uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha)
4109{
4110 uint32_t rval = QLA_FUNCTION_FAILED;
4111 uint32_t drv_active = 0;
4112 struct qla_hw_data *ha = base_vha->hw;
4113 int fn;
4114 struct pci_dev *other_pdev = NULL;
4115
7c3df132
SK		 4116 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
4117 "Entered %s.\n", __func__);
a5b36321
LC		 4118
4119 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4120
4121 if (base_vha->flags.online) {
4122 /* Abort all outstanding commands,
4123 * so as to be requeued later */
4124 qla2x00_abort_isp_cleanup(base_vha);
4125 }
4126
4127
4128 fn = PCI_FUNC(ha->pdev->devfn);
4129 while (fn > 0) {
4130 fn--;
7c3df132
SK		 4131 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
4132 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 4133 other_pdev =
4134 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
4135 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
4136 fn));
4137
4138 if (!other_pdev)
4139 continue;
4140 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 4141 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
4142 "Found PCI func available and enable at 0x%x.\n",
4143 fn);
a5b36321
LC		 4144 pci_dev_put(other_pdev);
4145 break;
4146 }
4147 pci_dev_put(other_pdev);
4148 }
4149
4150 if (!fn) {
4151 /* Reset owner */
7c3df132
SK		 4152 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
4153 "This devfn is reset owner = 0x%x.\n",
4154 ha->pdev->devfn);
a5b36321
LC		 4155 qla82xx_idc_lock(ha);
4156
4157 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4158 QLA82XX_DEV_INITIALIZING);
4159
4160 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
4161 QLA82XX_IDC_VERSION);
4162
4163 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 4164 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
4165 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 4166
4167 qla82xx_idc_unlock(ha);
4168 /* Reset if device is not already reset
4169 * drv_active would be 0 if a reset has already been done
4170 */
4171 if (drv_active)
4172 rval = qla82xx_start_firmware(base_vha);
4173 else
4174 rval = QLA_SUCCESS;
4175 qla82xx_idc_lock(ha);
4176
4177 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4178 ql_log(ql_log_info, base_vha, 0x900b,
4179 "HW State: FAILED.\n");
a5b36321
LC		 4180 qla82xx_clear_drv_active(ha);
4181 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4182 QLA82XX_DEV_FAILED);
4183 } else {
7c3df132
SK		 4184 ql_log(ql_log_info, base_vha, 0x900c,
4185 "HW State: READY.\n");
a5b36321
LC		 4186 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4187 QLA82XX_DEV_READY);
4188 qla82xx_idc_unlock(ha);
7190575f 4189 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4190 rval = qla82xx_restart_isp(base_vha);
4191 qla82xx_idc_lock(ha);
4192 /* Clear driver state register */
4193 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
4194 qla82xx_set_drv_active(base_vha);
4195 }
4196 qla82xx_idc_unlock(ha);
4197 } else {
7c3df132
SK		 4198 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
4199 "This devfn is not reset owner = 0x%x.\n",
4200 ha->pdev->devfn);
a5b36321
LC		 4201 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
4202 QLA82XX_DEV_READY)) {
7190575f 4203 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 4204 rval = qla82xx_restart_isp(base_vha);
4205 qla82xx_idc_lock(ha);
4206 qla82xx_set_drv_active(base_vha);
4207 qla82xx_idc_unlock(ha);
4208 }
4209 }
4210 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
4211
4212 return rval;
4213}
4214
14e660e6
SJ		 4215static pci_ers_result_t
4216qla2xxx_pci_slot_reset(struct pci_dev *pdev)
4217{
4218 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 4219 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4220 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 4221 struct rsp_que *rsp;
4222 int rc, retries = 10;
09483916 4223
7c3df132
SK		 4224 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
4225 "Slot Reset.\n");
85880801 4226
90a86fc0
JC		 4227 /* Workaround: qla2xxx driver which access hardware earlier
4228 * needs error state to be pci_channel_io_online.
4229 * Otherwise mailbox command timesout.
4230 */
4231 pdev->error_state = pci_channel_io_normal;
4232
4233 pci_restore_state(pdev);
4234
8c1496bd
RL		 4235 /* pci_restore_state() clears the saved_state flag of the device
4236 * save restored state which resets saved_state flag
4237 */
4238 pci_save_state(pdev);
4239
09483916
BH		 4240 if (ha->mem_only)
4241 rc = pci_enable_device_mem(pdev);
4242 else
4243 rc = pci_enable_device(pdev);
14e660e6 4244
09483916 4245 if (rc) {
7c3df132 4246 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 4247 "Can't re-enable PCI device after reset.\n");
a5b36321 4248 goto exit_slot_reset;
14e660e6 4249 }
14e660e6 4250
90a86fc0
JC		 4251 rsp = ha->rsp_q_map[0];
4252 if (qla2x00_request_irqs(ha, rsp))
a5b36321 4253 goto exit_slot_reset;
90a86fc0 4254
e315cd28 4255 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 4256 goto exit_slot_reset;
4257
4258 if (IS_QLA82XX(ha)) {
4259 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
4260 ret = PCI_ERS_RESULT_RECOVERED;
4261 goto exit_slot_reset;
4262 } else
4263 goto exit_slot_reset;
4264 }
14e660e6 4265
90a86fc0
JC		 4266 while (ha->flags.mbox_busy && retries--)
4267 msleep(1000);
85880801 4268
e315cd28 4269 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 4270 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 4271 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 4272 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 4273
90a86fc0 4274
a5b36321 4275exit_slot_reset:
7c3df132
SK		 4276 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
4277 "slot_reset return %x.\n", ret);
85880801 4278
14e660e6
SJ		 4279 return ret;
4280}
4281
4282static void
4283qla2xxx_pci_resume(struct pci_dev *pdev)
4284{
e315cd28
AC		 4285 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4286 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4287 int ret;
4288
7c3df132
SK		 4289 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
4290 "pci_resume.\n");
85880801 4291
e315cd28 4292 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 4293 if (ret != QLA_SUCCESS) {
7c3df132
SK		 4294 ql_log(ql_log_fatal, base_vha, 0x9002,
4295 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 4296 }
85880801 4297
3e46f031
LC		 4298 pci_cleanup_aer_uncorrect_error_status(pdev);
4299
85880801 4300 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4301}
4302
4303static struct pci_error_handlers qla2xxx_err_handler = {
4304 .error_detected = qla2xxx_pci_error_detected,
4305 .mmio_enabled = qla2xxx_pci_mmio_enabled,
4306 .slot_reset = qla2xxx_pci_slot_reset,
4307 .resume = qla2xxx_pci_resume,
4308};
4309
5433383e 4310static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 4311 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
4312 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
4313 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
4314 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
4315 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
4316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
4317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
4318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
4319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 4320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 4321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
4322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 4323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
3a03eb79 4324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 4325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
5433383e
AV		 4326 { 0 },
4327};
4328MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
4329
fca29703 4330static struct pci_driver qla2xxx_pci_driver = {
cb63067a 4331 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 4332 .driver = {
4333 .owner = THIS_MODULE,
4334 },
fca29703 4335 .id_table = qla2xxx_pci_tbl,
7ee61397 4336 .probe = qla2x00_probe_one,
4c993f76 4337 .remove = qla2x00_remove_one,
e30d1756 4338 .shutdown = qla2x00_shutdown,
14e660e6 4339 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 4340};
4341
6a03b4cd
HZ		 4342static struct file_operations apidev_fops = {
4343 .owner = THIS_MODULE,
6038f373 4344 .llseek = noop_llseek,
6a03b4cd
HZ		 4345};
4346
1da177e4
LT		 4347/**
4348 * qla2x00_module_init - Module initialization.
4349 **/
4350static int __init
4351qla2x00_module_init(void)
4352{
fca29703
AV		 4353 int ret = 0;
4354
1da177e4 4355 /* Allocate cache for SRBs. */
354d6b21 4356 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 4357 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 4358 if (srb_cachep == NULL) {
7c3df132
SK		 4359 ql_log(ql_log_fatal, NULL, 0x0001,
4360 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 4361 return -ENOMEM;
4362 }
4363
4364 /* Derive version string. */
4365 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 4366 if (ql2xextended_error_logging)
0181944f
AV		 4367 strcat(qla2x00_version_str, "-debug");
4368
1c97a12a
AV		 4369 qla2xxx_transport_template =
4370 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 4371 if (!qla2xxx_transport_template) {
4372 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 4373 ql_log(ql_log_fatal, NULL, 0x0002,
4374 "fc_attach_transport failed...Failing load!.\n");
1da177e4 4375 return -ENODEV;
2c3dfe3f 4376 }
6a03b4cd
HZ		 4377
4378 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
4379 if (apidev_major < 0) {
7c3df132
SK		 4380 ql_log(ql_log_fatal, NULL, 0x0003,
4381 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 4382 }
4383
2c3dfe3f
SJ		 4384 qla2xxx_transport_vport_template =
4385 fc_attach_transport(&qla2xxx_transport_vport_functions);
4386 if (!qla2xxx_transport_vport_template) {
4387 kmem_cache_destroy(srb_cachep);
4388 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 4389 ql_log(ql_log_fatal, NULL, 0x0004,
4390 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 4391 return -ENODEV;
2c3dfe3f 4392 }
7c3df132
SK		 4393 ql_log(ql_log_info, NULL, 0x0005,
4394 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 4395 qla2x00_version_str);
7ee61397 4396 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 4397 if (ret) {
4398 kmem_cache_destroy(srb_cachep);
4399 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4400 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 4401 ql_log(ql_log_fatal, NULL, 0x0006,
4402 "pci_register_driver failed...ret=%d Failing load!.\n",
4403 ret);
fca29703
AV		 4404 }
4405 return ret;
1da177e4
LT		 4406}
4407
4408/**
4409 * qla2x00_module_exit - Module cleanup.
4410 **/
4411static void __exit
4412qla2x00_module_exit(void)
4413{
6a03b4cd 4414 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 4415 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 4416 qla2x00_release_firmware();
354d6b21 4417 kmem_cache_destroy(srb_cachep);
a9083016
GM		 4418 if (ctx_cachep)
4419 kmem_cache_destroy(ctx_cachep);
1da177e4 4420 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 4421 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 4422}
4423
4424module_init(qla2x00_module_init);
4425module_exit(qla2x00_module_exit);
4426
4427MODULE_AUTHOR("QLogic Corporation");
4428MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
4429MODULE_LICENSE("GPL");
4430MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 4431MODULE_FIRMWARE(FW_FILE_ISP21XX);
4432MODULE_FIRMWARE(FW_FILE_ISP22XX);
4433MODULE_FIRMWARE(FW_FILE_ISP2300);
4434MODULE_FIRMWARE(FW_FILE_ISP2322);
4435MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 4436MODULE_FIRMWARE(FW_FILE_ISP25XX);
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