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scsi: qla2xxx: Add Block Multi Queue functionality.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
1da177e4 240/*
fa2a1ce5 241 * SCSI host template entry points
1da177e4
LT		 242 */
243static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 244static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 245static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
246static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 247static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 248static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 249static int qla2xxx_eh_abort(struct scsi_cmnd *);
250static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 251static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 252static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
253static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 254
1a2fbf18 255static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 256static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 257static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 258static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 259
a5326f86 260struct scsi_host_template qla2xxx_driver_template = {
1da177e4 261 .module = THIS_MODULE,
cb63067a 262 .name = QLA2XXX_DRIVER_NAME,
a5326f86 263 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 264
265 .eh_abort_handler = qla2xxx_eh_abort,
266 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 267 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 268 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
269 .eh_host_reset_handler = qla2xxx_eh_host_reset,
270
271 .slave_configure = qla2xxx_slave_configure,
272
273 .slave_alloc = qla2xxx_slave_alloc,
274 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 275 .scan_finished = qla2xxx_scan_finished,
276 .scan_start = qla2xxx_scan_start,
db5ed4df 277 .change_queue_depth = scsi_change_queue_depth,
5601236b 278 .map_queues = qla2xxx_map_queues,
fca29703
AV		 279 .this_id = -1,
280 .cmd_per_lun = 3,
281 .use_clustering = ENABLE_CLUSTERING,
282 .sg_tablesize = SG_ALL,
283
284 .max_sectors = 0xFFFF,
afb046e2 285 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 286
287 .supported_mode = MODE_INITIATOR,
c40ecc12 288 .track_queue_depth = 1,
fca29703
AV		 289};
290
1da177e4 291static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 292struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 293
1da177e4
LT		 294/* TODO Convert to inlines
295 *
296 * Timer routines
297 */
1da177e4 298
2c3dfe3f 299__inline__ void
e315cd28 300qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 301{
e315cd28
AC		 302 init_timer(&vha->timer);
303 vha->timer.expires = jiffies + interval * HZ;
304 vha->timer.data = (unsigned long)vha;
305 vha->timer.function = (void (*)(unsigned long))func;
306 add_timer(&vha->timer);
307 vha->timer_active = 1;
1da177e4
LT		 308}
309
310static inline void
e315cd28 311qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 312{
a9083016 313 /* Currently used for 82XX only. */
7c3df132
SK		 314 if (vha->device_flags & DFLG_DEV_FAILED) {
315 ql_dbg(ql_dbg_timer, vha, 0x600d,
316 "Device in a failed state, returning.\n");
a9083016 317 return;
7c3df132 318 }
a9083016 319
e315cd28 320 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 321}
322
a824ebb3 323static __inline__ void
e315cd28 324qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 325{
e315cd28
AC		 326 del_timer_sync(&vha->timer);
327 vha->timer_active = 0;
1da177e4
LT		 328}
329
1da177e4
LT		 330static int qla2x00_do_dpc(void *data);
331
332static void qla2x00_rst_aen(scsi_qla_host_t *);
333
73208dfd
AC		 334static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
335 struct req_que **, struct rsp_que **);
e30d1756 336static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 337static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 338int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
339 struct qla_qpair *qpair);
1da177e4 340
1da177e4 341/* -------------------------------------------------------------------------- */
9a347ff4
CD		 342static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
343 struct rsp_que *rsp)
73208dfd 344{
7c3df132 345 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 346 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 347 GFP_KERNEL);
348 if (!ha->req_q_map) {
7c3df132
SK		 349 ql_log(ql_log_fatal, vha, 0x003b,
350 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 351 goto fail_req_map;
352 }
353
2afa19a9 354 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 355 GFP_KERNEL);
356 if (!ha->rsp_q_map) {
7c3df132
SK		 357 ql_log(ql_log_fatal, vha, 0x003c,
358 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 359 goto fail_rsp_map;
360 }
d7459527
MH		 361
362 if (ql2xmqsupport && ha->max_qpairs) {
363 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
364 GFP_KERNEL);
365 if (!ha->queue_pair_map) {
366 ql_log(ql_log_fatal, vha, 0x0180,
367 "Unable to allocate memory for queue pair ptrs.\n");
368 goto fail_qpair_map;
369 }
370 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
371 if (ha->base_qpair == NULL) {
372 ql_log(ql_log_warn, vha, 0x0182,
373 "Failed to allocate base queue pair memory.\n");
374 goto fail_base_qpair;
375 }
376 ha->base_qpair->req = req;
377 ha->base_qpair->rsp = rsp;
378 }
379
9a347ff4
CD		 380 /*
381 * Make sure we record at least the request and response queue zero in
382 * case we need to free them if part of the probe fails.
383 */
384 ha->rsp_q_map[0] = rsp;
385 ha->req_q_map[0] = req;
73208dfd
AC		 386 set_bit(0, ha->rsp_qid_map);
387 set_bit(0, ha->req_qid_map);
388 return 1;
389
d7459527
MH		 390fail_base_qpair:
391 kfree(ha->queue_pair_map);
392fail_qpair_map:
393 kfree(ha->rsp_q_map);
394 ha->rsp_q_map = NULL;
73208dfd
AC		 395fail_rsp_map:
396 kfree(ha->req_q_map);
397 ha->req_q_map = NULL;
398fail_req_map:
399 return -ENOMEM;
400}
401
2afa19a9 402static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 403{
8ae6d9c7
GM		 404 if (IS_QLAFX00(ha)) {
405 if (req && req->ring_fx00)
406 dma_free_coherent(&ha->pdev->dev,
407 (req->length_fx00 + 1) * sizeof(request_t),
408 req->ring_fx00, req->dma_fx00);
409 } else if (req && req->ring)
73208dfd
AC		 410 dma_free_coherent(&ha->pdev->dev,
411 (req->length + 1) * sizeof(request_t),
412 req->ring, req->dma);
413
8d93f550
CD		 414 if (req)
415 kfree(req->outstanding_cmds);
416
73208dfd
AC		 417 kfree(req);
418 req = NULL;
419}
420
2afa19a9
AC		 421static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
422{
8ae6d9c7
GM		 423 if (IS_QLAFX00(ha)) {
424 if (rsp && rsp->ring)
425 dma_free_coherent(&ha->pdev->dev,
426 (rsp->length_fx00 + 1) * sizeof(request_t),
427 rsp->ring_fx00, rsp->dma_fx00);
428 } else if (rsp && rsp->ring) {
2afa19a9
AC		 429 dma_free_coherent(&ha->pdev->dev,
430 (rsp->length + 1) * sizeof(response_t),
431 rsp->ring, rsp->dma);
8ae6d9c7 432 }
2afa19a9
AC		 433 kfree(rsp);
434 rsp = NULL;
435}
436
73208dfd
AC		 437static void qla2x00_free_queues(struct qla_hw_data *ha)
438{
439 struct req_que *req;
440 struct rsp_que *rsp;
441 int cnt;
442
2afa19a9 443 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 444 if (!test_bit(cnt, ha->req_qid_map))
445 continue;
446
73208dfd 447 req = ha->req_q_map[cnt];
2afa19a9 448 qla2x00_free_req_que(ha, req);
73208dfd 449 }
73208dfd
AC		 450 kfree(ha->req_q_map);
451 ha->req_q_map = NULL;
2afa19a9
AC		 452
453 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 454 if (!test_bit(cnt, ha->rsp_qid_map))
455 continue;
456
2afa19a9
AC		 457 rsp = ha->rsp_q_map[cnt];
458 qla2x00_free_rsp_que(ha, rsp);
459 }
460 kfree(ha->rsp_q_map);
461 ha->rsp_q_map = NULL;
73208dfd
AC		 462}
463
1da177e4 464static char *
e315cd28 465qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 466{
e315cd28 467 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 468 static char *pci_bus_modes[] = {
469 "33", "66", "100", "133",
470 };
471 uint16_t pci_bus;
472
473 strcpy(str, "PCI");
474 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
475 if (pci_bus) {
476 strcat(str, "-X (");
477 strcat(str, pci_bus_modes[pci_bus]);
478 } else {
479 pci_bus = (ha->pci_attr & BIT_8) >> 8;
480 strcat(str, " (");
481 strcat(str, pci_bus_modes[pci_bus]);
482 }
483 strcat(str, " MHz)");
484
485 return (str);
486}
487
fca29703 488static char *
e315cd28 489qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 490{
491 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 492 struct qla_hw_data *ha = vha->hw;
fca29703 493 uint32_t pci_bus;
fca29703 494
62a276f8 495 if (pci_is_pcie(ha->pdev)) {
fca29703 496 char lwstr[6];
62a276f8 497 uint32_t lstat, lspeed, lwidth;
fca29703 498
62a276f8
BH		 499 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
500 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
501 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 502
503 strcpy(str, "PCIe (");
49300af7
SK		 504 switch (lspeed) {
505 case 1:
c87a0d8c 506 strcat(str, "2.5GT/s ");
49300af7
SK		 507 break;
508 case 2:
c87a0d8c 509 strcat(str, "5.0GT/s ");
49300af7
SK		 510 break;
511 case 3:
512 strcat(str, "8.0GT/s ");
513 break;
514 default:
fca29703 515 strcat(str, "<unknown> ");
49300af7
SK		 516 break;
517 }
fca29703
AV		 518 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
519 strcat(str, lwstr);
520
521 return str;
522 }
523
524 strcpy(str, "PCI");
525 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
526 if (pci_bus == 0 || pci_bus == 8) {
527 strcat(str, " (");
528 strcat(str, pci_bus_modes[pci_bus >> 3]);
529 } else {
530 strcat(str, "-X ");
531 if (pci_bus & BIT_2)
532 strcat(str, "Mode 2");
533 else
534 strcat(str, "Mode 1");
535 strcat(str, " (");
536 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
537 }
538 strcat(str, " MHz)");
539
540 return str;
541}
542
e5f82ab8 543static char *
df57caba 544qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 545{
546 char un_str[10];
e315cd28 547 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 548
df57caba
HM		 549 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
550 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 551
552 if (ha->fw_attributes & BIT_9) {
553 strcat(str, "FLX");
554 return (str);
555 }
556
557 switch (ha->fw_attributes & 0xFF) {
558 case 0x7:
559 strcat(str, "EF");
560 break;
561 case 0x17:
562 strcat(str, "TP");
563 break;
564 case 0x37:
565 strcat(str, "IP");
566 break;
567 case 0x77:
568 strcat(str, "VI");
569 break;
570 default:
571 sprintf(un_str, "(%x)", ha->fw_attributes);
572 strcat(str, un_str);
573 break;
574 }
575 if (ha->fw_attributes & 0x100)
576 strcat(str, "X");
577
578 return (str);
579}
580
e5f82ab8 581static char *
df57caba 582qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 583{
e315cd28 584 struct qla_hw_data *ha = vha->hw;
f0883ac6 585
df57caba 586 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 587 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 588 return str;
fca29703
AV		 589}
590
9ba56b95
GM		 591void
592qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 593{
9ba56b95
GM		 594 srb_t *sp = (srb_t *)ptr;
595 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
596 struct qla_hw_data *ha = sp->fcport->vha->hw;
597 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 598
9ba56b95
GM		 599 if (sp->flags & SRB_DMA_VALID) {
600 scsi_dma_unmap(cmd);
601 sp->flags &= ~SRB_DMA_VALID;
7c3df132 602 }
fca29703 603
9ba56b95
GM		 604 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
605 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
606 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
607 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
608 }
609
610 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
611 /* List assured to be having elements */
f83adb61 612 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 613 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
614 }
615
616 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
617 dma_pool_free(ha->dl_dma_pool, ctx,
618 ((struct crc_context *)ctx)->crc_ctx_dma);
619 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
620 }
621
622 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
623 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 624
9ba56b95
GM		 625 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
626 ctx1->fcp_cmnd_dma);
627 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
628 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
629 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
630 mempool_free(ctx1, ha->ctx_mempool);
631 ctx1 = NULL;
632 }
633
634 CMD_SP(cmd) = NULL;
b00ee7d7 635 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 636}
637
d7459527 638void
9ba56b95
GM		 639qla2x00_sp_compl(void *data, void *ptr, int res)
640{
641 struct qla_hw_data *ha = (struct qla_hw_data *)data;
642 srb_t *sp = (srb_t *)ptr;
643 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
644
645 cmd->result = res;
646
647 if (atomic_read(&sp->ref_count) == 0) {
648 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
649 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
650 sp, GET_CMD_SP(sp));
651 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 652 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 653 return;
654 }
655 if (!atomic_dec_and_test(&sp->ref_count))
656 return;
657
658 qla2x00_sp_free_dma(ha, sp);
659 cmd->scsi_done(cmd);
fca29703
AV		 660}
661
d7459527
MH		 662void
663qla2xxx_qpair_sp_free_dma(void *vha, void *ptr)
664{
665 srb_t *sp = (srb_t *)ptr;
666 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
667 struct qla_hw_data *ha = sp->fcport->vha->hw;
668 void *ctx = GET_CMD_CTX_SP(sp);
669
670 if (sp->flags & SRB_DMA_VALID) {
671 scsi_dma_unmap(cmd);
672 sp->flags &= ~SRB_DMA_VALID;
673 }
674
675 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
676 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
677 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
678 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
679 }
680
681 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
682 /* List assured to be having elements */
683 qla2x00_clean_dsd_pool(ha, sp, NULL);
684 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
685 }
686
687 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
688 dma_pool_free(ha->dl_dma_pool, ctx,
689 ((struct crc_context *)ctx)->crc_ctx_dma);
690 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
691 }
692
693 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
694 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
695
696 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
697 ctx1->fcp_cmnd_dma);
698 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
699 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
700 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
701 mempool_free(ctx1, ha->ctx_mempool);
702 }
703
704 CMD_SP(cmd) = NULL;
705 qla2xxx_rel_qpair_sp(sp->qpair, sp);
706}
707
708void
709qla2xxx_qpair_sp_compl(void *data, void *ptr, int res)
710{
711 srb_t *sp = (srb_t *)ptr;
712 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
713
714 cmd->result = res;
715
716 if (atomic_read(&sp->ref_count) == 0) {
717 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
718 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
719 sp, GET_CMD_SP(sp));
720 if (ql2xextended_error_logging & ql_dbg_io)
721 WARN_ON(atomic_read(&sp->ref_count) == 0);
722 return;
723 }
724 if (!atomic_dec_and_test(&sp->ref_count))
725 return;
726
727 qla2xxx_qpair_sp_free_dma(sp->fcport->vha, sp);
728 cmd->scsi_done(cmd);
729}
730
8ae6d9c7
GM		 731/* If we are SP1 here, we need to still take and release the host_lock as SP1
732 * does not have the changes necessary to avoid taking host->host_lock.
733 */
1da177e4 734static int
f5e3e40b 735qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 736{
134ae078 737 scsi_qla_host_t *vha = shost_priv(host);
fca29703 738 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 739 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 740 struct qla_hw_data *ha = vha->hw;
741 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 742 srb_t *sp;
743 int rval;
5601236b
MH		 744 struct qla_qpair *qpair = NULL;
745 uint32_t tag;
746 uint16_t hwq;
fca29703 747
04dfaa53
MFO		 748 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
749 cmd->result = DID_NO_CONNECT << 16;
750 goto qc24_fail_command;
751 }
752
5601236b
MH		 753 if (ha->mqenable) {
754 if (shost_use_blk_mq(vha->host)) {
755 tag = blk_mq_unique_tag(cmd->request);
756 hwq = blk_mq_unique_tag_to_hwq(tag);
757 qpair = ha->queue_pair_map[hwq];
758 } else if (vha->vp_idx && vha->qpair) {
759 qpair = vha->qpair;
760 }
761
762 if (qpair)
763 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 764 }
765
85880801 766 if (ha->flags.eeh_busy) {
7c3df132 767 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 768 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 769 "PCI Channel IO permanent failure, exiting "
770 "cmd=%p.\n", cmd);
b9b12f73 771 cmd->result = DID_NO_CONNECT << 16;
7c3df132 772 } else {
5f28d2d7 773 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 774 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 775 cmd->result = DID_REQUEUE << 16;
7c3df132 776 }
14e660e6
SJ		 777 goto qc24_fail_command;
778 }
779
19a7b4ae
JSEC		 780 rval = fc_remote_port_chkready(rport);
781 if (rval) {
782 cmd->result = rval;
5f28d2d7 783 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 784 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
785 cmd, rval);
fca29703
AV		 786 goto qc24_fail_command;
787 }
788
bad75002
AE		 789 if (!vha->flags.difdix_supported &&
790 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 791 ql_dbg(ql_dbg_io, vha, 0x3004,
792 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
793 cmd);
bad75002
AE		 794 cmd->result = DID_NO_CONNECT << 16;
795 goto qc24_fail_command;
796 }
aa651be8
CD		 797
798 if (!fcport) {
799 cmd->result = DID_NO_CONNECT << 16;
800 goto qc24_fail_command;
801 }
802
fca29703
AV		 803 if (atomic_read(&fcport->state) != FCS_ONLINE) {
804 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 805 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 806 ql_dbg(ql_dbg_io, vha, 0x3005,
807 "Returning DNC, fcport_state=%d loop_state=%d.\n",
808 atomic_read(&fcport->state),
809 atomic_read(&base_vha->loop_state));
fca29703
AV		 810 cmd->result = DID_NO_CONNECT << 16;
811 goto qc24_fail_command;
812 }
7b594131 813 goto qc24_target_busy;
fca29703
AV		 814 }
815
e05fe292
CD		 816 /*
817 * Return target busy if we've received a non-zero retry_delay_timer
818 * in a FCP_RSP.
819 */
975f7d46
BP		 820 if (fcport->retry_delay_timestamp == 0) {
821 /* retry delay not set */
822 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 823 fcport->retry_delay_timestamp = 0;
824 else
825 goto qc24_target_busy;
826
b00ee7d7 827 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 828 if (!sp)
f5e3e40b 829 goto qc24_host_busy;
fca29703 830
9ba56b95
GM		 831 sp->u.scmd.cmd = cmd;
832 sp->type = SRB_SCSI_CMD;
833 atomic_set(&sp->ref_count, 1);
834 CMD_SP(cmd) = (void *)sp;
835 sp->free = qla2x00_sp_free_dma;
836 sp->done = qla2x00_sp_compl;
837
e315cd28 838 rval = ha->isp_ops->start_scsi(sp);
7c3df132 839 if (rval != QLA_SUCCESS) {
53016ed3 840 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 841 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 842 goto qc24_host_busy_free_sp;
7c3df132 843 }
fca29703 844
fca29703
AV		 845 return 0;
846
847qc24_host_busy_free_sp:
9ba56b95 848 qla2x00_sp_free_dma(ha, sp);
fca29703 849
f5e3e40b 850qc24_host_busy:
fca29703
AV		 851 return SCSI_MLQUEUE_HOST_BUSY;
852
7b594131
MC		 853qc24_target_busy:
854 return SCSI_MLQUEUE_TARGET_BUSY;
855
fca29703 856qc24_fail_command:
f5e3e40b 857 cmd->scsi_done(cmd);
fca29703
AV		 858
859 return 0;
860}
861
d7459527
MH		 862/* For MQ supported I/O */
863int
864qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
865 struct qla_qpair *qpair)
866{
867 scsi_qla_host_t *vha = shost_priv(host);
868 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
869 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
870 struct qla_hw_data *ha = vha->hw;
871 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
872 srb_t *sp;
873 int rval;
874
875 rval = fc_remote_port_chkready(rport);
876 if (rval) {
877 cmd->result = rval;
878 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
879 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
880 cmd, rval);
881 goto qc24_fail_command;
882 }
883
884 if (!fcport) {
885 cmd->result = DID_NO_CONNECT << 16;
886 goto qc24_fail_command;
887 }
888
889 if (atomic_read(&fcport->state) != FCS_ONLINE) {
890 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
891 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
892 ql_dbg(ql_dbg_io, vha, 0x3077,
893 "Returning DNC, fcport_state=%d loop_state=%d.\n",
894 atomic_read(&fcport->state),
895 atomic_read(&base_vha->loop_state));
896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
899 goto qc24_target_busy;
900 }
901
902 /*
903 * Return target busy if we've received a non-zero retry_delay_timer
904 * in a FCP_RSP.
905 */
906 if (fcport->retry_delay_timestamp == 0) {
907 /* retry delay not set */
908 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
909 fcport->retry_delay_timestamp = 0;
910 else
911 goto qc24_target_busy;
912
913 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
914 if (!sp)
915 goto qc24_host_busy;
916
917 sp->u.scmd.cmd = cmd;
918 sp->type = SRB_SCSI_CMD;
919 atomic_set(&sp->ref_count, 1);
920 CMD_SP(cmd) = (void *)sp;
921 sp->free = qla2xxx_qpair_sp_free_dma;
922 sp->done = qla2xxx_qpair_sp_compl;
923 sp->qpair = qpair;
924
925 rval = ha->isp_ops->start_scsi_mq(sp);
926 if (rval != QLA_SUCCESS) {
927 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
928 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
929 if (rval == QLA_INTERFACE_ERROR)
930 goto qc24_fail_command;
931 goto qc24_host_busy_free_sp;
932 }
933
934 return 0;
935
936qc24_host_busy_free_sp:
937 qla2xxx_qpair_sp_free_dma(vha, sp);
938
939qc24_host_busy:
940 return SCSI_MLQUEUE_HOST_BUSY;
941
942qc24_target_busy:
943 return SCSI_MLQUEUE_TARGET_BUSY;
944
945qc24_fail_command:
946 cmd->scsi_done(cmd);
947
948 return 0;
949}
950
1da177e4
LT		 951/*
952 * qla2x00_eh_wait_on_command
953 * Waits for the command to be returned by the Firmware for some
954 * max time.
955 *
956 * Input:
1da177e4 957 * cmd = Scsi Command to wait on.
1da177e4
LT		 958 *
959 * Return:
960 * Not Found : 0
961 * Found : 1
962 */
963static int
e315cd28 964qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 965{
fe74c71f 966#define ABORT_POLLING_PERIOD 1000
478c3b03 967#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 968 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 969 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
970 struct qla_hw_data *ha = vha->hw;
f4f051eb 971 int ret = QLA_SUCCESS;
1da177e4 972
85880801 973 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 974 ql_dbg(ql_dbg_taskm, vha, 0x8005,
975 "Return:eh_wait.\n");
85880801
AV		 976 return ret;
977 }
978
d970432c 979 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 980 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 981 }
982 if (CMD_SP(cmd))
983 ret = QLA_FUNCTION_FAILED;
1da177e4 984
f4f051eb 985 return ret;
1da177e4
LT		 986}
987
988/*
989 * qla2x00_wait_for_hba_online
fa2a1ce5 990 * Wait till the HBA is online after going through
1da177e4
LT		 991 * <= MAX_RETRIES_OF_ISP_ABORT or
992 * finally HBA is disabled ie marked offline
993 *
994 * Input:
995 * ha - pointer to host adapter structure
fa2a1ce5
AV		 996 *
997 * Note:
1da177e4
LT		 998 * Does context switching-Release SPIN_LOCK
999 * (if any) before calling this routine.
1000 *
1001 * Return:
1002 * Success (Adapter is online) : 0
1003 * Failed (Adapter is offline/disabled) : 1
1004 */
854165f4 1005int
e315cd28 1006qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1007{
fca29703
AV		 1008 int return_status;
1009 unsigned long wait_online;
e315cd28
AC		 1010 struct qla_hw_data *ha = vha->hw;
1011 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1012
fa2a1ce5 1013 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1014 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1015 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1016 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1017 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1018
1019 msleep(1000);
1020 }
e315cd28 1021 if (base_vha->flags.online)
fa2a1ce5 1022 return_status = QLA_SUCCESS;
1da177e4
LT		 1023 else
1024 return_status = QLA_FUNCTION_FAILED;
1025
1da177e4
LT		 1026 return (return_status);
1027}
1028
86fbee86 1029/*
638a1a01
SC		 1030 * qla2x00_wait_for_hba_ready
1031 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1032 *
1033 * Input:
1034 * ha - pointer to host adapter structure
1035 *
1036 * Note:
1037 * Does context switching-Release SPIN_LOCK
1038 * (if any) before calling this routine.
1039 *
86fbee86 1040 */
638a1a01
SC		 1041static void
1042qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1043{
86fbee86 1044 struct qla_hw_data *ha = vha->hw;
783e0dc4 1045 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1046
1d483901
DC		 1047 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1048 ha->flags.mbox_busy) ||
1049 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1050 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1051 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1052 break;
86fbee86 1053 msleep(1000);
783e0dc4 1054 }
86fbee86
LC		 1055}
1056
2533cf67
LC		 1057int
1058qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1059{
1060 int return_status;
1061 unsigned long wait_reset;
1062 struct qla_hw_data *ha = vha->hw;
1063 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1064
1065 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1066 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1067 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1068 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1069 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1070
1071 msleep(1000);
1072
1073 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1074 ha->flags.chip_reset_done)
1075 break;
1076 }
1077 if (ha->flags.chip_reset_done)
1078 return_status = QLA_SUCCESS;
1079 else
1080 return_status = QLA_FUNCTION_FAILED;
1081
1082 return return_status;
1083}
1084
083a469d
GM		 1085static void
1086sp_get(struct srb *sp)
1087{
1088 atomic_inc(&sp->ref_count);
1089}
1090
a465537a
SC		 1091#define ISP_REG_DISCONNECT 0xffffffffU
1092/**************************************************************************
1093* qla2x00_isp_reg_stat
1094*
1095* Description:
1096* Read the host status register of ISP before aborting the command.
1097*
1098* Input:
1099* ha = pointer to host adapter structure.
1100*
1101*
1102* Returns:
1103* Either true or false.
1104*
1105* Note: Return true if there is register disconnect.
1106**************************************************************************/
1107static inline
1108uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1109{
1110 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1111
1112 return ((RD_REG_DWORD(&reg->host_status)) == ISP_REG_DISCONNECT);
1113}
1114
1da177e4
LT		 1115/**************************************************************************
1116* qla2xxx_eh_abort
1117*
1118* Description:
1119* The abort function will abort the specified command.
1120*
1121* Input:
1122* cmd = Linux SCSI command packet to be aborted.
1123*
1124* Returns:
1125* Either SUCCESS or FAILED.
1126*
1127* Note:
2ea00202 1128* Only return FAILED if command not returned by firmware.
1da177e4 1129**************************************************************************/
e5f82ab8 1130static int
1da177e4
LT		 1131qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1132{
e315cd28 1133 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1134 srb_t *sp;
4e98d3b8 1135 int ret;
9cb78c16
HR		 1136 unsigned int id;
1137 uint64_t lun;
18e144d3 1138 unsigned long flags;
f934c9d0 1139 int rval, wait = 0;
e315cd28 1140 struct qla_hw_data *ha = vha->hw;
1da177e4 1141
a465537a
SC		 1142 if (qla2x00_isp_reg_stat(ha)) {
1143 ql_log(ql_log_info, vha, 0x8042,
1144 "PCI/Register disconnect, exiting.\n");
1145 return FAILED;
1146 }
f4f051eb 1147 if (!CMD_SP(cmd))
2ea00202 1148 return SUCCESS;
1da177e4 1149
4e98d3b8
AV		 1150 ret = fc_block_scsi_eh(cmd);
1151 if (ret != 0)
1152 return ret;
1153 ret = SUCCESS;
1154
f4f051eb
AV		 1155 id = cmd->device->id;
1156 lun = cmd->device->lun;
1da177e4 1157
e315cd28 1158 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1159 sp = (srb_t *) CMD_SP(cmd);
1160 if (!sp) {
1161 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1162 return SUCCESS;
1163 }
1da177e4 1164
7c3df132 1165 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1166 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1167 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1168
170babc3
MC		 1169 /* Get a reference to the sp and drop the lock.*/
1170 sp_get(sp);
083a469d 1171
e315cd28 1172 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1173 rval = ha->isp_ops->abort_command(sp);
1174 if (rval) {
96219424 1175 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1176 ret = SUCCESS;
96219424 1177 else
f934c9d0
CD		 1178 ret = FAILED;
1179
7c3df132 1180 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1181 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1182 } else {
7c3df132 1183 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1184 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1185 wait = 1;
1186 }
75942064
SK		 1187
1188 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 1189 sp->done(ha, sp, 0);
75942064 1190 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1191
bc91ade9
CD		 1192 /* Did the command return during mailbox execution? */
1193 if (ret == FAILED && !CMD_SP(cmd))
1194 ret = SUCCESS;
1195
f4f051eb 1196 /* Wait for the command to be returned. */
2ea00202 1197 if (wait) {
e315cd28 1198 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1199 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1200 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1201 ret = FAILED;
f4f051eb 1202 }
1da177e4 1203 }
1da177e4 1204
7c3df132 1205 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1206 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1207 vha->host_no, id, lun, wait, ret);
1da177e4 1208
f4f051eb
AV		 1209 return ret;
1210}
1da177e4 1211
4d78c973 1212int
e315cd28 1213qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1214 uint64_t l, enum nexus_wait_type type)
f4f051eb 1215{
17d98630 1216 int cnt, match, status;
18e144d3 1217 unsigned long flags;
e315cd28 1218 struct qla_hw_data *ha = vha->hw;
73208dfd 1219 struct req_que *req;
4d78c973 1220 srb_t *sp;
9ba56b95 1221 struct scsi_cmnd *cmd;
1da177e4 1222
523ec773 1223 status = QLA_SUCCESS;
17d98630 1224
e315cd28 1225 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1226 req = vha->req;
17d98630 1227 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1228 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1229 sp = req->outstanding_cmds[cnt];
1230 if (!sp)
523ec773 1231 continue;
9ba56b95 1232 if (sp->type != SRB_SCSI_CMD)
cf53b069 1233 continue;
17d98630
AC		 1234 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1235 continue;
1236 match = 0;
9ba56b95 1237 cmd = GET_CMD_SP(sp);
17d98630
AC		 1238 switch (type) {
1239 case WAIT_HOST:
1240 match = 1;
1241 break;
1242 case WAIT_TARGET:
9ba56b95 1243 match = cmd->device->id == t;
17d98630
AC		 1244 break;
1245 case WAIT_LUN:
9ba56b95
GM		 1246 match = (cmd->device->id == t &&
1247 cmd->device->lun == l);
17d98630 1248 break;
73208dfd 1249 }
17d98630
AC		 1250 if (!match)
1251 continue;
1252
1253 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1254 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1255 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1256 }
e315cd28 1257 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1258
1259 return status;
1da177e4
LT		 1260}
1261
523ec773
AV		 1262static char *reset_errors[] = {
1263 "HBA not online",
1264 "HBA not ready",
1265 "Task management failed",
1266 "Waiting for command completions",
1267};
1da177e4 1268
e5f82ab8 1269static int
523ec773 1270__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1271 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1272{
e315cd28 1273 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1274 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1275 int err;
1da177e4 1276
7c3df132 1277 if (!fcport) {
523ec773 1278 return FAILED;
7c3df132 1279 }
1da177e4 1280
4e98d3b8
AV		 1281 err = fc_block_scsi_eh(cmd);
1282 if (err != 0)
1283 return err;
1284
7c3df132 1285 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1286 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1287 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1288
523ec773 1289 err = 0;
7c3df132
SK		 1290 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1291 ql_log(ql_log_warn, vha, 0x800a,
1292 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1293 goto eh_reset_failed;
7c3df132 1294 }
523ec773 1295 err = 2;
2afa19a9 1296 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1297 != QLA_SUCCESS) {
1298 ql_log(ql_log_warn, vha, 0x800c,
1299 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1300 goto eh_reset_failed;
7c3df132 1301 }
523ec773 1302 err = 3;
e315cd28 1303 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1304 cmd->device->lun, type) != QLA_SUCCESS) {
1305 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1306 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1307 goto eh_reset_failed;
7c3df132 1308 }
523ec773 1309
7c3df132 1310 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1311 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1312 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1313
1314 return SUCCESS;
1315
4d78c973 1316eh_reset_failed:
7c3df132 1317 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1318 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1319 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1320 cmd);
523ec773
AV		 1321 return FAILED;
1322}
1da177e4 1323
523ec773
AV		 1324static int
1325qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1326{
e315cd28
AC		 1327 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1328 struct qla_hw_data *ha = vha->hw;
1da177e4 1329
a465537a
SC		 1330 if (qla2x00_isp_reg_stat(ha)) {
1331 ql_log(ql_log_info, vha, 0x803e,
1332 "PCI/Register disconnect, exiting.\n");
1333 return FAILED;
1334 }
1335
523ec773
AV		 1336 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1337 ha->isp_ops->lun_reset);
1da177e4
LT		 1338}
1339
1da177e4 1340static int
523ec773 1341qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1342{
e315cd28
AC		 1343 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1344 struct qla_hw_data *ha = vha->hw;
1da177e4 1345
a465537a
SC		 1346 if (qla2x00_isp_reg_stat(ha)) {
1347 ql_log(ql_log_info, vha, 0x803f,
1348 "PCI/Register disconnect, exiting.\n");
1349 return FAILED;
1350 }
1351
523ec773
AV		 1352 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1353 ha->isp_ops->target_reset);
1da177e4
LT		 1354}
1355
1da177e4
LT		 1356/**************************************************************************
1357* qla2xxx_eh_bus_reset
1358*
1359* Description:
1360* The bus reset function will reset the bus and abort any executing
1361* commands.
1362*
1363* Input:
1364* cmd = Linux SCSI command packet of the command that cause the
1365* bus reset.
1366*
1367* Returns:
1368* SUCCESS/FAILURE (defined as macro in scsi.h).
1369*
1370**************************************************************************/
e5f82ab8 1371static int
1da177e4
LT		 1372qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1373{
e315cd28 1374 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1375 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1376 int ret = FAILED;
9cb78c16
HR		 1377 unsigned int id;
1378 uint64_t lun;
a465537a
SC		 1379 struct qla_hw_data *ha = vha->hw;
1380
1381 if (qla2x00_isp_reg_stat(ha)) {
1382 ql_log(ql_log_info, vha, 0x8040,
1383 "PCI/Register disconnect, exiting.\n");
1384 return FAILED;
1385 }
f4f051eb 1386
f4f051eb
AV		 1387 id = cmd->device->id;
1388 lun = cmd->device->lun;
1da177e4 1389
7c3df132 1390 if (!fcport) {
f4f051eb 1391 return ret;
7c3df132 1392 }
1da177e4 1393
4e98d3b8
AV		 1394 ret = fc_block_scsi_eh(cmd);
1395 if (ret != 0)
1396 return ret;
1397 ret = FAILED;
1398
7c3df132 1399 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1400 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1401
e315cd28 1402 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1403 ql_log(ql_log_fatal, vha, 0x8013,
1404 "Wait for hba online failed board disabled.\n");
f4f051eb 1405 goto eh_bus_reset_done;
1da177e4
LT		 1406 }
1407
ad537689
SK		 1408 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1409 ret = SUCCESS;
1410
f4f051eb
AV		 1411 if (ret == FAILED)
1412 goto eh_bus_reset_done;
1da177e4 1413
9a41a62b 1414 /* Flush outstanding commands. */
4d78c973 1415 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1416 QLA_SUCCESS) {
1417 ql_log(ql_log_warn, vha, 0x8014,
1418 "Wait for pending commands failed.\n");
9a41a62b 1419 ret = FAILED;
7c3df132 1420 }
1da177e4 1421
f4f051eb 1422eh_bus_reset_done:
7c3df132 1423 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1424 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1425 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1426
f4f051eb 1427 return ret;
1da177e4
LT		 1428}
1429
1430/**************************************************************************
1431* qla2xxx_eh_host_reset
1432*
1433* Description:
1434* The reset function will reset the Adapter.
1435*
1436* Input:
1437* cmd = Linux SCSI command packet of the command that cause the
1438* adapter reset.
1439*
1440* Returns:
1441* Either SUCCESS or FAILED.
1442*
1443* Note:
1444**************************************************************************/
e5f82ab8 1445static int
1da177e4
LT		 1446qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1447{
e315cd28 1448 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1449 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1450 int ret = FAILED;
9cb78c16
HR		 1451 unsigned int id;
1452 uint64_t lun;
e315cd28 1453 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1454
a465537a
SC		 1455 if (qla2x00_isp_reg_stat(ha)) {
1456 ql_log(ql_log_info, vha, 0x8041,
1457 "PCI/Register disconnect, exiting.\n");
1458 schedule_work(&ha->board_disable);
1459 return SUCCESS;
1460 }
1461
f4f051eb
AV		 1462 id = cmd->device->id;
1463 lun = cmd->device->lun;
f4f051eb 1464
7c3df132 1465 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1466 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1467
63ee7072
CD		 1468 /*
1469 * No point in issuing another reset if one is active. Also do not
1470 * attempt a reset if we are updating flash.
1471 */
1472 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1473 goto eh_host_reset_lock;
1da177e4 1474
e315cd28
AC		 1475 if (vha != base_vha) {
1476 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1477 goto eh_host_reset_lock;
e315cd28 1478 } else {
7ec0effd 1479 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1480 if (!qla82xx_fcoe_ctx_reset(vha)) {
1481 /* Ctx reset success */
1482 ret = SUCCESS;
1483 goto eh_host_reset_lock;
1484 }
1485 /* fall thru if ctx reset failed */
1486 }
68ca949c
AC		 1487 if (ha->wq)
1488 flush_workqueue(ha->wq);
1489
e315cd28 1490 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1491 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1492 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1493 /* failed. schedule dpc to try */
1494 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1495
7c3df132
SK		 1496 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1497 ql_log(ql_log_warn, vha, 0x802a,
1498 "wait for hba online failed.\n");
e315cd28 1499 goto eh_host_reset_lock;
7c3df132 1500 }
e315cd28
AC		 1501 }
1502 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1503 }
1da177e4 1504
e315cd28 1505 /* Waiting for command to be returned to OS.*/
4d78c973 1506 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1507 QLA_SUCCESS)
f4f051eb 1508 ret = SUCCESS;
1da177e4 1509
f4f051eb 1510eh_host_reset_lock:
cfb0919c 1511 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1512 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1513 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1514
f4f051eb
AV		 1515 return ret;
1516}
1da177e4
LT		 1517
1518/*
1519* qla2x00_loop_reset
1520* Issue loop reset.
1521*
1522* Input:
1523* ha = adapter block pointer.
1524*
1525* Returns:
1526* 0 = success
1527*/
a4722cf2 1528int
e315cd28 1529qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1530{
0c8c39af 1531 int ret;
bdf79621 1532 struct fc_port *fcport;
e315cd28 1533 struct qla_hw_data *ha = vha->hw;
1da177e4 1534
5854771e
AB		 1535 if (IS_QLAFX00(ha)) {
1536 return qlafx00_loop_reset(vha);
1537 }
1538
f4c496c1 1539 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1540 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1541 if (fcport->port_type != FCT_TARGET)
1542 continue;
1543
1544 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1545 if (ret != QLA_SUCCESS) {
7c3df132 1546 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1547 "Bus Reset failed: Reset=%d "
7c3df132 1548 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1549 }
1550 }
1551 }
1552
8ae6d9c7 1553
6246b8a1 1554 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1555 atomic_set(&vha->loop_state, LOOP_DOWN);
1556 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1557 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1558 ret = qla2x00_full_login_lip(vha);
0c8c39af 1559 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1560 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1561 "full_login_lip=%d.\n", ret);
749af3d5 1562 }
0c8c39af
AV		 1563 }
1564
0d6e61bc 1565 if (ha->flags.enable_lip_reset) {
e315cd28 1566 ret = qla2x00_lip_reset(vha);
ad537689 1567 if (ret != QLA_SUCCESS)
7c3df132
SK		 1568 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1569 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1570 }
1571
1da177e4 1572 /* Issue marker command only when we are going to start the I/O */
e315cd28 1573 vha->marker_needed = 1;
1da177e4 1574
0c8c39af 1575 return QLA_SUCCESS;
1da177e4
LT		 1576}
1577
df4bf0bb 1578void
e315cd28 1579qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1580{
73208dfd 1581 int que, cnt;
df4bf0bb
AV		 1582 unsigned long flags;
1583 srb_t *sp;
e315cd28 1584 struct qla_hw_data *ha = vha->hw;
73208dfd 1585 struct req_que *req;
df4bf0bb 1586
c0cb4496
AE		 1587 qlt_host_reset_handler(ha);
1588
df4bf0bb 1589 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1590 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1591 req = ha->req_q_map[que];
73208dfd
AC		 1592 if (!req)
1593 continue;
8d93f550
CD		 1594 if (!req->outstanding_cmds)
1595 continue;
1596 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1597 sp = req->outstanding_cmds[cnt];
e612d465 1598 if (sp) {
c733ab35
MFO		 1599 /* Don't abort commands in adapter during EEH
1600 * recovery as it's not accessible/responding.
1535aa75 1601 */
c733ab35
MFO		 1602 if (!ha->flags.eeh_busy) {
1603 /* Get a reference to the sp and drop the lock.
1604 * The reference ensures this sp->done() call
1605 * - and not the call in qla2xxx_eh_abort() -
1606 * ends the SCSI command (with result 'res').
1607 */
1608 sp_get(sp);
1609 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1610 qla2xxx_eh_abort(GET_CMD_SP(sp));
1611 spin_lock_irqsave(&ha->hardware_lock, flags);
1612 }
73208dfd 1613 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1614 sp->done(vha, sp, res);
73208dfd 1615 }
df4bf0bb
AV		 1616 }
1617 }
1618 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1619}
1620
f4f051eb
AV		 1621static int
1622qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1623{
bdf79621 1624 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1625
19a7b4ae 1626 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1627 return -ENXIO;
bdf79621 1628
19a7b4ae 1629 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1630
f4f051eb
AV		 1631 return 0;
1632}
1da177e4 1633
f4f051eb
AV		 1634static int
1635qla2xxx_slave_configure(struct scsi_device *sdev)
1636{
e315cd28 1637 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1638 struct req_que *req = vha->req;
8482e118 1639
9e522cd8
AE		 1640 if (IS_T10_PI_CAPABLE(vha->hw))
1641 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1642
db5ed4df 1643 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1644 return 0;
1645}
1da177e4 1646
f4f051eb
AV		 1647static void
1648qla2xxx_slave_destroy(struct scsi_device *sdev)
1649{
1650 sdev->hostdata = NULL;
1da177e4
LT		 1651}
1652
1653/**
1654 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1655 * @ha: HA context
1656 *
1657 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1658 * supported addressing method.
1659 */
1660static void
53303c42 1661qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1662{
7524f9b9 1663 /* Assume a 32bit DMA mask. */
1da177e4 1664 ha->flags.enable_64bit_addressing = 0;
1da177e4 1665
6a35528a 1666 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1667 /* Any upper-dword bits set? */
1668 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1669 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1670 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1671 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1672 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1673 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1674 return;
1da177e4 1675 }
1da177e4 1676 }
7524f9b9 1677
284901a9
YH		 1678 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1679 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1680}
1681
fd34f556 1682static void
e315cd28 1683qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1684{
1685 unsigned long flags = 0;
1686 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1687
1688 spin_lock_irqsave(&ha->hardware_lock, flags);
1689 ha->interrupts_on = 1;
1690 /* enable risc and host interrupts */
1691 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1692 RD_REG_WORD(&reg->ictrl);
1693 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1694
1695}
1696
1697static void
e315cd28 1698qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1699{
1700 unsigned long flags = 0;
1701 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1702
1703 spin_lock_irqsave(&ha->hardware_lock, flags);
1704 ha->interrupts_on = 0;
1705 /* disable risc and host interrupts */
1706 WRT_REG_WORD(&reg->ictrl, 0);
1707 RD_REG_WORD(&reg->ictrl);
1708 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1709}
1710
1711static void
e315cd28 1712qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1713{
1714 unsigned long flags = 0;
1715 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1716
1717 spin_lock_irqsave(&ha->hardware_lock, flags);
1718 ha->interrupts_on = 1;
1719 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1720 RD_REG_DWORD(&reg->ictrl);
1721 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1722}
1723
1724static void
e315cd28 1725qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1726{
1727 unsigned long flags = 0;
1728 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1729
124f85e6
AV		 1730 if (IS_NOPOLLING_TYPE(ha))
1731 return;
fd34f556
AV		 1732 spin_lock_irqsave(&ha->hardware_lock, flags);
1733 ha->interrupts_on = 0;
1734 WRT_REG_DWORD(&reg->ictrl, 0);
1735 RD_REG_DWORD(&reg->ictrl);
1736 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1737}
1738
706f457d
GM		 1739static int
1740qla2x00_iospace_config(struct qla_hw_data *ha)
1741{
1742 resource_size_t pio;
1743 uint16_t msix;
706f457d 1744
706f457d
GM		 1745 if (pci_request_selected_regions(ha->pdev, ha->bars,
1746 QLA2XXX_DRIVER_NAME)) {
1747 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1748 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1749 pci_name(ha->pdev));
1750 goto iospace_error_exit;
1751 }
1752 if (!(ha->bars & 1))
1753 goto skip_pio;
1754
1755 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1756 pio = pci_resource_start(ha->pdev, 0);
1757 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1758 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1759 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1760 "Invalid pci I/O region size (%s).\n",
1761 pci_name(ha->pdev));
1762 pio = 0;
1763 }
1764 } else {
1765 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1766 "Region #0 no a PIO resource (%s).\n",
1767 pci_name(ha->pdev));
1768 pio = 0;
1769 }
1770 ha->pio_address = pio;
1771 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1772 "PIO address=%llu.\n",
1773 (unsigned long long)ha->pio_address);
1774
1775skip_pio:
1776 /* Use MMIO operations for all accesses. */
1777 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1778 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1779 "Region #1 not an MMIO resource (%s), aborting.\n",
1780 pci_name(ha->pdev));
1781 goto iospace_error_exit;
1782 }
1783 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1784 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1785 "Invalid PCI mem region size (%s), aborting.\n",
1786 pci_name(ha->pdev));
1787 goto iospace_error_exit;
1788 }
1789
1790 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1791 if (!ha->iobase) {
1792 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1793 "Cannot remap MMIO (%s), aborting.\n",
1794 pci_name(ha->pdev));
1795 goto iospace_error_exit;
1796 }
1797
1798 /* Determine queue resources */
1799 ha->max_req_queues = ha->max_rsp_queues = 1;
d7459527 1800 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1801 goto mqiobase_exit;
1802
1803 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1804 pci_resource_len(ha->pdev, 3));
1805 if (ha->mqiobase) {
1806 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1807 "MQIO Base=%p.\n", ha->mqiobase);
1808 /* Read MSIX vector size of the board */
1809 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1810 ha->msix_count = msix + 1;
706f457d 1811 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1812 /* MB interrupt uses 1 vector */
1813 ha->max_req_queues = ha->msix_count - 1;
1814 ha->max_rsp_queues = ha->max_req_queues;
1815 /* Queue pairs is the max value minus the base queue pair */
1816 ha->max_qpairs = ha->max_rsp_queues - 1;
1817 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1818 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1819
706f457d 1820 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1821 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1822 } else
1823 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1824 "BAR 3 not enabled.\n");
1825
1826mqiobase_exit:
1827 ha->msix_count = ha->max_rsp_queues + 1;
1828 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1829 "MSIX Count:%d.\n", ha->msix_count);
1830 return (0);
1831
1832iospace_error_exit:
1833 return (-ENOMEM);
1834}
1835
1836
6246b8a1
GM		 1837static int
1838qla83xx_iospace_config(struct qla_hw_data *ha)
1839{
1840 uint16_t msix;
6246b8a1
GM		 1841
1842 if (pci_request_selected_regions(ha->pdev, ha->bars,
1843 QLA2XXX_DRIVER_NAME)) {
1844 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1845 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1846 pci_name(ha->pdev));
1847
1848 goto iospace_error_exit;
1849 }
1850
1851 /* Use MMIO operations for all accesses. */
1852 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1853 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1854 "Invalid pci I/O region size (%s).\n",
1855 pci_name(ha->pdev));
1856 goto iospace_error_exit;
1857 }
1858 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1859 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1860 "Invalid PCI mem region size (%s), aborting\n",
1861 pci_name(ha->pdev));
1862 goto iospace_error_exit;
1863 }
1864
1865 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1866 if (!ha->iobase) {
1867 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1868 "Cannot remap MMIO (%s), aborting.\n",
1869 pci_name(ha->pdev));
1870 goto iospace_error_exit;
1871 }
1872
1873 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1874 /* 83XX 26XX always use MQ type access for queues
1875 * - mbar 2, a.k.a region 4 */
1876 ha->max_req_queues = ha->max_rsp_queues = 1;
1877 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1878 pci_resource_len(ha->pdev, 4));
1879
1880 if (!ha->mqiobase) {
1881 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1882 "BAR2/region4 not enabled\n");
1883 goto mqiobase_exit;
1884 }
1885
1886 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1887 pci_resource_len(ha->pdev, 2));
1888 if (ha->msixbase) {
1889 /* Read MSIX vector size of the board */
1890 pci_read_config_word(ha->pdev,
1891 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1892 ha->msix_count = msix + 1;
6246b8a1
GM		 1893 /* Max queues are bounded by available msix vectors */
1894 /* queue 0 uses two msix vectors */
d7459527
MH		 1895 if (ql2xmqsupport) {
1896 /* MB interrupt uses 1 vector */
1897 ha->max_req_queues = ha->msix_count - 1;
1898 ha->max_rsp_queues = ha->max_req_queues;
1899 /* Queue pairs is the max value minus
1900 * the base queue pair */
1901 ha->max_qpairs = ha->max_req_queues - 1;
1902 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc010,
1903 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1904 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1905 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1906 }
1907 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1908 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1909 } else
1910 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1911 "BAR 1 not enabled.\n");
1912
1913mqiobase_exit:
1914 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1915
1916 qlt_83xx_iospace_config(ha);
1917
6246b8a1
GM		 1918 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1919 "MSIX Count:%d.\n", ha->msix_count);
1920 return 0;
1921
1922iospace_error_exit:
1923 return -ENOMEM;
1924}
1925
fd34f556
AV		 1926static struct isp_operations qla2100_isp_ops = {
1927 .pci_config = qla2100_pci_config,
1928 .reset_chip = qla2x00_reset_chip,
1929 .chip_diag = qla2x00_chip_diag,
1930 .config_rings = qla2x00_config_rings,
1931 .reset_adapter = qla2x00_reset_adapter,
1932 .nvram_config = qla2x00_nvram_config,
1933 .update_fw_options = qla2x00_update_fw_options,
1934 .load_risc = qla2x00_load_risc,
1935 .pci_info_str = qla2x00_pci_info_str,
1936 .fw_version_str = qla2x00_fw_version_str,
1937 .intr_handler = qla2100_intr_handler,
1938 .enable_intrs = qla2x00_enable_intrs,
1939 .disable_intrs = qla2x00_disable_intrs,
1940 .abort_command = qla2x00_abort_command,
523ec773
AV		 1941 .target_reset = qla2x00_abort_target,
1942 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1943 .fabric_login = qla2x00_login_fabric,
1944 .fabric_logout = qla2x00_fabric_logout,
1945 .calc_req_entries = qla2x00_calc_iocbs_32,
1946 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1947 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1948 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1949 .read_nvram = qla2x00_read_nvram_data,
1950 .write_nvram = qla2x00_write_nvram_data,
1951 .fw_dump = qla2100_fw_dump,
1952 .beacon_on = NULL,
1953 .beacon_off = NULL,
1954 .beacon_blink = NULL,
1955 .read_optrom = qla2x00_read_optrom_data,
1956 .write_optrom = qla2x00_write_optrom_data,
1957 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1958 .start_scsi = qla2x00_start_scsi,
d7459527 1959 .start_scsi_mq = NULL,
a9083016 1960 .abort_isp = qla2x00_abort_isp,
706f457d 1961 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1962 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1963};
1964
1965static struct isp_operations qla2300_isp_ops = {
1966 .pci_config = qla2300_pci_config,
1967 .reset_chip = qla2x00_reset_chip,
1968 .chip_diag = qla2x00_chip_diag,
1969 .config_rings = qla2x00_config_rings,
1970 .reset_adapter = qla2x00_reset_adapter,
1971 .nvram_config = qla2x00_nvram_config,
1972 .update_fw_options = qla2x00_update_fw_options,
1973 .load_risc = qla2x00_load_risc,
1974 .pci_info_str = qla2x00_pci_info_str,
1975 .fw_version_str = qla2x00_fw_version_str,
1976 .intr_handler = qla2300_intr_handler,
1977 .enable_intrs = qla2x00_enable_intrs,
1978 .disable_intrs = qla2x00_disable_intrs,
1979 .abort_command = qla2x00_abort_command,
523ec773
AV		 1980 .target_reset = qla2x00_abort_target,
1981 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1982 .fabric_login = qla2x00_login_fabric,
1983 .fabric_logout = qla2x00_fabric_logout,
1984 .calc_req_entries = qla2x00_calc_iocbs_32,
1985 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1986 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1987 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1988 .read_nvram = qla2x00_read_nvram_data,
1989 .write_nvram = qla2x00_write_nvram_data,
1990 .fw_dump = qla2300_fw_dump,
1991 .beacon_on = qla2x00_beacon_on,
1992 .beacon_off = qla2x00_beacon_off,
1993 .beacon_blink = qla2x00_beacon_blink,
1994 .read_optrom = qla2x00_read_optrom_data,
1995 .write_optrom = qla2x00_write_optrom_data,
1996 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1997 .start_scsi = qla2x00_start_scsi,
d7459527 1998 .start_scsi_mq = NULL,
a9083016 1999 .abort_isp = qla2x00_abort_isp,
7ec0effd 2000 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2001 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2002};
2003
2004static struct isp_operations qla24xx_isp_ops = {
2005 .pci_config = qla24xx_pci_config,
2006 .reset_chip = qla24xx_reset_chip,
2007 .chip_diag = qla24xx_chip_diag,
2008 .config_rings = qla24xx_config_rings,
2009 .reset_adapter = qla24xx_reset_adapter,
2010 .nvram_config = qla24xx_nvram_config,
2011 .update_fw_options = qla24xx_update_fw_options,
2012 .load_risc = qla24xx_load_risc,
2013 .pci_info_str = qla24xx_pci_info_str,
2014 .fw_version_str = qla24xx_fw_version_str,
2015 .intr_handler = qla24xx_intr_handler,
2016 .enable_intrs = qla24xx_enable_intrs,
2017 .disable_intrs = qla24xx_disable_intrs,
2018 .abort_command = qla24xx_abort_command,
523ec773
AV		 2019 .target_reset = qla24xx_abort_target,
2020 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2021 .fabric_login = qla24xx_login_fabric,
2022 .fabric_logout = qla24xx_fabric_logout,
2023 .calc_req_entries = NULL,
2024 .build_iocbs = NULL,
2025 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2026 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2027 .read_nvram = qla24xx_read_nvram_data,
2028 .write_nvram = qla24xx_write_nvram_data,
2029 .fw_dump = qla24xx_fw_dump,
2030 .beacon_on = qla24xx_beacon_on,
2031 .beacon_off = qla24xx_beacon_off,
2032 .beacon_blink = qla24xx_beacon_blink,
2033 .read_optrom = qla24xx_read_optrom_data,
2034 .write_optrom = qla24xx_write_optrom_data,
2035 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2036 .start_scsi = qla24xx_start_scsi,
d7459527 2037 .start_scsi_mq = NULL,
a9083016 2038 .abort_isp = qla2x00_abort_isp,
7ec0effd 2039 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2040 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2041};
2042
c3a2f0df
AV		 2043static struct isp_operations qla25xx_isp_ops = {
2044 .pci_config = qla25xx_pci_config,
2045 .reset_chip = qla24xx_reset_chip,
2046 .chip_diag = qla24xx_chip_diag,
2047 .config_rings = qla24xx_config_rings,
2048 .reset_adapter = qla24xx_reset_adapter,
2049 .nvram_config = qla24xx_nvram_config,
2050 .update_fw_options = qla24xx_update_fw_options,
2051 .load_risc = qla24xx_load_risc,
2052 .pci_info_str = qla24xx_pci_info_str,
2053 .fw_version_str = qla24xx_fw_version_str,
2054 .intr_handler = qla24xx_intr_handler,
2055 .enable_intrs = qla24xx_enable_intrs,
2056 .disable_intrs = qla24xx_disable_intrs,
2057 .abort_command = qla24xx_abort_command,
523ec773
AV		 2058 .target_reset = qla24xx_abort_target,
2059 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2060 .fabric_login = qla24xx_login_fabric,
2061 .fabric_logout = qla24xx_fabric_logout,
2062 .calc_req_entries = NULL,
2063 .build_iocbs = NULL,
2064 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2065 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2066 .read_nvram = qla25xx_read_nvram_data,
2067 .write_nvram = qla25xx_write_nvram_data,
2068 .fw_dump = qla25xx_fw_dump,
2069 .beacon_on = qla24xx_beacon_on,
2070 .beacon_off = qla24xx_beacon_off,
2071 .beacon_blink = qla24xx_beacon_blink,
338c9161 2072 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2073 .write_optrom = qla24xx_write_optrom_data,
2074 .get_flash_version = qla24xx_get_flash_version,
bad75002 2075 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2076 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2077 .abort_isp = qla2x00_abort_isp,
7ec0effd 2078 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2079 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2080};
2081
3a03eb79
AV		 2082static struct isp_operations qla81xx_isp_ops = {
2083 .pci_config = qla25xx_pci_config,
2084 .reset_chip = qla24xx_reset_chip,
2085 .chip_diag = qla24xx_chip_diag,
2086 .config_rings = qla24xx_config_rings,
2087 .reset_adapter = qla24xx_reset_adapter,
2088 .nvram_config = qla81xx_nvram_config,
2089 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2090 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2091 .pci_info_str = qla24xx_pci_info_str,
2092 .fw_version_str = qla24xx_fw_version_str,
2093 .intr_handler = qla24xx_intr_handler,
2094 .enable_intrs = qla24xx_enable_intrs,
2095 .disable_intrs = qla24xx_disable_intrs,
2096 .abort_command = qla24xx_abort_command,
2097 .target_reset = qla24xx_abort_target,
2098 .lun_reset = qla24xx_lun_reset,
2099 .fabric_login = qla24xx_login_fabric,
2100 .fabric_logout = qla24xx_fabric_logout,
2101 .calc_req_entries = NULL,
2102 .build_iocbs = NULL,
2103 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2104 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2105 .read_nvram = NULL,
2106 .write_nvram = NULL,
3a03eb79
AV		 2107 .fw_dump = qla81xx_fw_dump,
2108 .beacon_on = qla24xx_beacon_on,
2109 .beacon_off = qla24xx_beacon_off,
6246b8a1 2110 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2111 .read_optrom = qla25xx_read_optrom_data,
2112 .write_optrom = qla24xx_write_optrom_data,
2113 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2114 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2115 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2116 .abort_isp = qla2x00_abort_isp,
7ec0effd 2117 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2118 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2119};
2120
2121static struct isp_operations qla82xx_isp_ops = {
2122 .pci_config = qla82xx_pci_config,
2123 .reset_chip = qla82xx_reset_chip,
2124 .chip_diag = qla24xx_chip_diag,
2125 .config_rings = qla82xx_config_rings,
2126 .reset_adapter = qla24xx_reset_adapter,
2127 .nvram_config = qla81xx_nvram_config,
2128 .update_fw_options = qla24xx_update_fw_options,
2129 .load_risc = qla82xx_load_risc,
9d55ca66 2130 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2131 .fw_version_str = qla24xx_fw_version_str,
2132 .intr_handler = qla82xx_intr_handler,
2133 .enable_intrs = qla82xx_enable_intrs,
2134 .disable_intrs = qla82xx_disable_intrs,
2135 .abort_command = qla24xx_abort_command,
2136 .target_reset = qla24xx_abort_target,
2137 .lun_reset = qla24xx_lun_reset,
2138 .fabric_login = qla24xx_login_fabric,
2139 .fabric_logout = qla24xx_fabric_logout,
2140 .calc_req_entries = NULL,
2141 .build_iocbs = NULL,
2142 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2143 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2144 .read_nvram = qla24xx_read_nvram_data,
2145 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2146 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2147 .beacon_on = qla82xx_beacon_on,
2148 .beacon_off = qla82xx_beacon_off,
2149 .beacon_blink = NULL,
a9083016
GM		 2150 .read_optrom = qla82xx_read_optrom_data,
2151 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2152 .get_flash_version = qla82xx_get_flash_version,
a9083016 2153 .start_scsi = qla82xx_start_scsi,
d7459527 2154 .start_scsi_mq = NULL,
a9083016 2155 .abort_isp = qla82xx_abort_isp,
706f457d 2156 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2157 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2158};
2159
7ec0effd
AD		 2160static struct isp_operations qla8044_isp_ops = {
2161 .pci_config = qla82xx_pci_config,
2162 .reset_chip = qla82xx_reset_chip,
2163 .chip_diag = qla24xx_chip_diag,
2164 .config_rings = qla82xx_config_rings,
2165 .reset_adapter = qla24xx_reset_adapter,
2166 .nvram_config = qla81xx_nvram_config,
2167 .update_fw_options = qla24xx_update_fw_options,
2168 .load_risc = qla82xx_load_risc,
2169 .pci_info_str = qla24xx_pci_info_str,
2170 .fw_version_str = qla24xx_fw_version_str,
2171 .intr_handler = qla8044_intr_handler,
2172 .enable_intrs = qla82xx_enable_intrs,
2173 .disable_intrs = qla82xx_disable_intrs,
2174 .abort_command = qla24xx_abort_command,
2175 .target_reset = qla24xx_abort_target,
2176 .lun_reset = qla24xx_lun_reset,
2177 .fabric_login = qla24xx_login_fabric,
2178 .fabric_logout = qla24xx_fabric_logout,
2179 .calc_req_entries = NULL,
2180 .build_iocbs = NULL,
2181 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2182 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2183 .read_nvram = NULL,
2184 .write_nvram = NULL,
a1b23c5a 2185 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2186 .beacon_on = qla82xx_beacon_on,
2187 .beacon_off = qla82xx_beacon_off,
2188 .beacon_blink = NULL,
888e639d 2189 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2190 .write_optrom = qla8044_write_optrom_data,
2191 .get_flash_version = qla82xx_get_flash_version,
2192 .start_scsi = qla82xx_start_scsi,
d7459527 2193 .start_scsi_mq = NULL,
7ec0effd
AD		 2194 .abort_isp = qla8044_abort_isp,
2195 .iospace_config = qla82xx_iospace_config,
2196 .initialize_adapter = qla2x00_initialize_adapter,
2197};
2198
6246b8a1
GM		 2199static struct isp_operations qla83xx_isp_ops = {
2200 .pci_config = qla25xx_pci_config,
2201 .reset_chip = qla24xx_reset_chip,
2202 .chip_diag = qla24xx_chip_diag,
2203 .config_rings = qla24xx_config_rings,
2204 .reset_adapter = qla24xx_reset_adapter,
2205 .nvram_config = qla81xx_nvram_config,
2206 .update_fw_options = qla81xx_update_fw_options,
2207 .load_risc = qla81xx_load_risc,
2208 .pci_info_str = qla24xx_pci_info_str,
2209 .fw_version_str = qla24xx_fw_version_str,
2210 .intr_handler = qla24xx_intr_handler,
2211 .enable_intrs = qla24xx_enable_intrs,
2212 .disable_intrs = qla24xx_disable_intrs,
2213 .abort_command = qla24xx_abort_command,
2214 .target_reset = qla24xx_abort_target,
2215 .lun_reset = qla24xx_lun_reset,
2216 .fabric_login = qla24xx_login_fabric,
2217 .fabric_logout = qla24xx_fabric_logout,
2218 .calc_req_entries = NULL,
2219 .build_iocbs = NULL,
2220 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2221 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2222 .read_nvram = NULL,
2223 .write_nvram = NULL,
2224 .fw_dump = qla83xx_fw_dump,
2225 .beacon_on = qla24xx_beacon_on,
2226 .beacon_off = qla24xx_beacon_off,
2227 .beacon_blink = qla83xx_beacon_blink,
2228 .read_optrom = qla25xx_read_optrom_data,
2229 .write_optrom = qla24xx_write_optrom_data,
2230 .get_flash_version = qla24xx_get_flash_version,
2231 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2232 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2233 .abort_isp = qla2x00_abort_isp,
2234 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2235 .initialize_adapter = qla2x00_initialize_adapter,
2236};
2237
2238static struct isp_operations qlafx00_isp_ops = {
2239 .pci_config = qlafx00_pci_config,
2240 .reset_chip = qlafx00_soft_reset,
2241 .chip_diag = qlafx00_chip_diag,
2242 .config_rings = qlafx00_config_rings,
2243 .reset_adapter = qlafx00_soft_reset,
2244 .nvram_config = NULL,
2245 .update_fw_options = NULL,
2246 .load_risc = NULL,
2247 .pci_info_str = qlafx00_pci_info_str,
2248 .fw_version_str = qlafx00_fw_version_str,
2249 .intr_handler = qlafx00_intr_handler,
2250 .enable_intrs = qlafx00_enable_intrs,
2251 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2252 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2253 .target_reset = qlafx00_abort_target,
2254 .lun_reset = qlafx00_lun_reset,
2255 .fabric_login = NULL,
2256 .fabric_logout = NULL,
2257 .calc_req_entries = NULL,
2258 .build_iocbs = NULL,
2259 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2260 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2261 .read_nvram = qla24xx_read_nvram_data,
2262 .write_nvram = qla24xx_write_nvram_data,
2263 .fw_dump = NULL,
2264 .beacon_on = qla24xx_beacon_on,
2265 .beacon_off = qla24xx_beacon_off,
2266 .beacon_blink = NULL,
2267 .read_optrom = qla24xx_read_optrom_data,
2268 .write_optrom = qla24xx_write_optrom_data,
2269 .get_flash_version = qla24xx_get_flash_version,
2270 .start_scsi = qlafx00_start_scsi,
d7459527 2271 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2272 .abort_isp = qlafx00_abort_isp,
2273 .iospace_config = qlafx00_iospace_config,
2274 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2275};
2276
f73cb695
CD		 2277static struct isp_operations qla27xx_isp_ops = {
2278 .pci_config = qla25xx_pci_config,
2279 .reset_chip = qla24xx_reset_chip,
2280 .chip_diag = qla24xx_chip_diag,
2281 .config_rings = qla24xx_config_rings,
2282 .reset_adapter = qla24xx_reset_adapter,
2283 .nvram_config = qla81xx_nvram_config,
2284 .update_fw_options = qla81xx_update_fw_options,
2285 .load_risc = qla81xx_load_risc,
2286 .pci_info_str = qla24xx_pci_info_str,
2287 .fw_version_str = qla24xx_fw_version_str,
2288 .intr_handler = qla24xx_intr_handler,
2289 .enable_intrs = qla24xx_enable_intrs,
2290 .disable_intrs = qla24xx_disable_intrs,
2291 .abort_command = qla24xx_abort_command,
2292 .target_reset = qla24xx_abort_target,
2293 .lun_reset = qla24xx_lun_reset,
2294 .fabric_login = qla24xx_login_fabric,
2295 .fabric_logout = qla24xx_fabric_logout,
2296 .calc_req_entries = NULL,
2297 .build_iocbs = NULL,
2298 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2299 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2300 .read_nvram = NULL,
2301 .write_nvram = NULL,
2302 .fw_dump = qla27xx_fwdump,
2303 .beacon_on = qla24xx_beacon_on,
2304 .beacon_off = qla24xx_beacon_off,
2305 .beacon_blink = qla83xx_beacon_blink,
2306 .read_optrom = qla25xx_read_optrom_data,
2307 .write_optrom = qla24xx_write_optrom_data,
2308 .get_flash_version = qla24xx_get_flash_version,
2309 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2310 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2311 .abort_isp = qla2x00_abort_isp,
2312 .iospace_config = qla83xx_iospace_config,
2313 .initialize_adapter = qla2x00_initialize_adapter,
2314};
2315
ea5b6382 2316static inline void
e315cd28 2317qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2318{
2319 ha->device_type = DT_EXTENDED_IDS;
2320 switch (ha->pdev->device) {
2321 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2322 ha->isp_type |= DT_ISP2100;
ea5b6382 2323 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2324 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2325 break;
2326 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2327 ha->isp_type |= DT_ISP2200;
ea5b6382 2328 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2329 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2330 break;
2331 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2332 ha->isp_type |= DT_ISP2300;
4a59f71d 2333 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2334 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2335 break;
2336 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2337 ha->isp_type |= DT_ISP2312;
4a59f71d 2338 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2339 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2340 break;
2341 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2342 ha->isp_type |= DT_ISP2322;
4a59f71d 2343 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2344 if (ha->pdev->subsystem_vendor == 0x1028 &&
2345 ha->pdev->subsystem_device == 0x0170)
2346 ha->device_type |= DT_OEM_001;
441d1072 2347 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2348 break;
2349 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2350 ha->isp_type |= DT_ISP6312;
441d1072 2351 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2352 break;
2353 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2354 ha->isp_type |= DT_ISP6322;
441d1072 2355 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2356 break;
2357 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2358 ha->isp_type |= DT_ISP2422;
4a59f71d 2359 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2360 ha->device_type |= DT_FWI2;
c76f2c01 2361 ha->device_type |= DT_IIDMA;
441d1072 2362 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2363 break;
2364 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2365 ha->isp_type |= DT_ISP2432;
4a59f71d 2366 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2367 ha->device_type |= DT_FWI2;
c76f2c01 2368 ha->device_type |= DT_IIDMA;
441d1072 2369 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2370 break;
4d4df193 2371 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2372 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2373 ha->device_type |= DT_ZIO_SUPPORTED;
2374 ha->device_type |= DT_FWI2;
2375 ha->device_type |= DT_IIDMA;
2376 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2377 break;
044cc6c8 2378 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2379 ha->isp_type |= DT_ISP5422;
e428924c 2380 ha->device_type |= DT_FWI2;
441d1072 2381 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2382 break;
044cc6c8 2383 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2384 ha->isp_type |= DT_ISP5432;
e428924c 2385 ha->device_type |= DT_FWI2;
441d1072 2386 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2387 break;
c3a2f0df 2388 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2389 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2390 ha->device_type |= DT_ZIO_SUPPORTED;
2391 ha->device_type |= DT_FWI2;
2392 ha->device_type |= DT_IIDMA;
441d1072 2393 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2394 break;
3a03eb79 2395 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2396 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2397 ha->device_type |= DT_ZIO_SUPPORTED;
2398 ha->device_type |= DT_FWI2;
2399 ha->device_type |= DT_IIDMA;
2400 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2401 break;
a9083016 2402 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2403 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2404 ha->device_type |= DT_ZIO_SUPPORTED;
2405 ha->device_type |= DT_FWI2;
2406 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2407 /* Initialize 82XX ISP flags */
2408 qla82xx_init_flags(ha);
2409 break;
7ec0effd 2410 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2411 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2412 ha->device_type |= DT_ZIO_SUPPORTED;
2413 ha->device_type |= DT_FWI2;
2414 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2415 /* Initialize 82XX ISP flags */
2416 qla82xx_init_flags(ha);
2417 break;
6246b8a1 2418 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2419 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2420 ha->device_type |= DT_ZIO_SUPPORTED;
2421 ha->device_type |= DT_FWI2;
2422 ha->device_type |= DT_IIDMA;
2423 ha->device_type |= DT_T10_PI;
2424 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2425 break;
2426 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2427 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2428 ha->device_type |= DT_ZIO_SUPPORTED;
2429 ha->device_type |= DT_FWI2;
2430 ha->device_type |= DT_IIDMA;
2431 ha->device_type |= DT_T10_PI;
2432 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2433 break;
8ae6d9c7 2434 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2435 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2436 break;
f73cb695 2437 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2438 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2439 ha->device_type |= DT_ZIO_SUPPORTED;
2440 ha->device_type |= DT_FWI2;
2441 ha->device_type |= DT_IIDMA;
8ce3f570 2442 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2443 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2444 break;
2c5bbbb2 2445 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2446 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2447 ha->device_type |= DT_ZIO_SUPPORTED;
2448 ha->device_type |= DT_FWI2;
2449 ha->device_type |= DT_IIDMA;
8ce3f570 2450 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2451 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2452 break;
2b48992f 2453 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2454 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2455 ha->device_type |= DT_ZIO_SUPPORTED;
2456 ha->device_type |= DT_FWI2;
2457 ha->device_type |= DT_IIDMA;
8ce3f570 2458 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2459 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2460 break;
ea5b6382 2461 }
e5b68a61 2462
a9083016 2463 if (IS_QLA82XX(ha))
43a9c38b 2464 ha->port_no = ha->portnum & 1;
f73cb695 2465 else {
a9083016
GM		 2466 /* Get adapter physical port no from interrupt pin register. */
2467 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2468 if (IS_QLA27XX(ha))
2469 ha->port_no--;
2470 else
2471 ha->port_no = !(ha->port_no & 1);
2472 }
a9083016 2473
7c3df132 2474 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2475 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2476 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2477}
2478
1e99e33a
AV		 2479static void
2480qla2xxx_scan_start(struct Scsi_Host *shost)
2481{
e315cd28 2482 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2483
cbc8eb67
AV		 2484 if (vha->hw->flags.running_gold_fw)
2485 return;
2486
e315cd28
AC		 2487 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2488 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2489 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2490 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2491}
2492
2493static int
2494qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2495{
e315cd28 2496 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2497
a5dd506e
BK		 2498 if (test_bit(UNLOADING, &vha->dpc_flags))
2499 return 1;
e315cd28 2500 if (!vha->host)
1e99e33a 2501 return 1;
e315cd28 2502 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2503 return 1;
2504
e315cd28 2505 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2506}
2507
1da177e4
LT		 2508/*
2509 * PCI driver interface
2510 */
6f039790 2511static int
7ee61397 2512qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2513{
a1541d5a 2514 int ret = -ENODEV;
1da177e4 2515 struct Scsi_Host *host;
e315cd28
AC		 2516 scsi_qla_host_t *base_vha = NULL;
2517 struct qla_hw_data *ha;
29856e28 2518 char pci_info[30];
7d613ac6 2519 char fw_str[30], wq_name[30];
5433383e 2520 struct scsi_host_template *sht;
642ef983 2521 int bars, mem_only = 0;
e315cd28 2522 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2523 struct req_que *req = NULL;
2524 struct rsp_que *rsp = NULL;
5601236b 2525 int i;
d7459527 2526
285d0321 2527 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2528 sht = &qla2xxx_driver_template;
5433383e 2529 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2530 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2531 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2532 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2533 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2534 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2535 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2536 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2537 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2538 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2539 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2540 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2541 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2542 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2543 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2544 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2545 mem_only = 1;
7c3df132
SK		 2546 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2547 "Mem only adapter.\n");
285d0321 2548 }
7c3df132
SK		 2549 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2550 "Bars=%d.\n", bars);
285d0321 2551
09483916
BH		 2552 if (mem_only) {
2553 if (pci_enable_device_mem(pdev))
2554 goto probe_out;
2555 } else {
2556 if (pci_enable_device(pdev))
2557 goto probe_out;
2558 }
285d0321 2559
0927678f
JB		 2560 /* This may fail but that's ok */
2561 pci_enable_pcie_error_reporting(pdev);
285d0321 2562
e315cd28
AC		 2563 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2564 if (!ha) {
7c3df132
SK		 2565 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2566 "Unable to allocate memory for ha.\n");
e315cd28 2567 goto probe_out;
1da177e4 2568 }
7c3df132
SK		 2569 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2570 "Memory allocated for ha=%p.\n", ha);
e315cd28 2571 ha->pdev = pdev;
2d70c103 2572 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2573 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2574 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2575 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2576 spin_lock_init(&ha->tgt.atio_lock);
2577
1da177e4
LT		 2578
2579 /* Clear our data area */
285d0321 2580 ha->bars = bars;
09483916 2581 ha->mem_only = mem_only;
df4bf0bb 2582 spin_lock_init(&ha->hardware_lock);
339aa70e 2583 spin_lock_init(&ha->vport_slock);
a9b6f722 2584 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2585 mutex_init(&ha->optrom_mutex);
1da177e4 2586
ea5b6382
AV		 2587 /* Set ISP-type information. */
2588 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2589
2590 /* Set EEH reset type to fundamental if required by hba */
95676112 2591 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2592 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2593 pdev->needs_freset = 1;
ca79cf66 2594
cba1e47f
CD		 2595 ha->prev_topology = 0;
2596 ha->init_cb_size = sizeof(init_cb_t);
2597 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2598 ha->optrom_size = OPTROM_SIZE_2300;
2599
abbd8870 2600 /* Assign ISP specific operations. */
1da177e4 2601 if (IS_QLA2100(ha)) {
642ef983 2602 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2603 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2604 req_length = REQUEST_ENTRY_CNT_2100;
2605 rsp_length = RESPONSE_ENTRY_CNT_2100;
2606 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2607 ha->gid_list_info_size = 4;
3a03eb79
AV		 2608 ha->flash_conf_off = ~0;
2609 ha->flash_data_off = ~0;
2610 ha->nvram_conf_off = ~0;
2611 ha->nvram_data_off = ~0;
fd34f556 2612 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2613 } else if (IS_QLA2200(ha)) {
642ef983 2614 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2615 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2616 req_length = REQUEST_ENTRY_CNT_2200;
2617 rsp_length = RESPONSE_ENTRY_CNT_2100;
2618 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2619 ha->gid_list_info_size = 4;
3a03eb79
AV		 2620 ha->flash_conf_off = ~0;
2621 ha->flash_data_off = ~0;
2622 ha->nvram_conf_off = ~0;
2623 ha->nvram_data_off = ~0;
fd34f556 2624 ha->isp_ops = &qla2100_isp_ops;
fca29703 2625 } else if (IS_QLA23XX(ha)) {
642ef983 2626 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2627 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2628 req_length = REQUEST_ENTRY_CNT_2200;
2629 rsp_length = RESPONSE_ENTRY_CNT_2300;
2630 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2631 ha->gid_list_info_size = 6;
854165f4
AV		 2632 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2633 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2634 ha->flash_conf_off = ~0;
2635 ha->flash_data_off = ~0;
2636 ha->nvram_conf_off = ~0;
2637 ha->nvram_data_off = ~0;
fd34f556 2638 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2639 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2640 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2641 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2642 req_length = REQUEST_ENTRY_CNT_24XX;
2643 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2644 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2645 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2646 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2647 ha->gid_list_info_size = 8;
854165f4 2648 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2649 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2650 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2651 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2652 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2653 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2654 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2655 } else if (IS_QLA25XX(ha)) {
642ef983 2656 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2657 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2658 req_length = REQUEST_ENTRY_CNT_24XX;
2659 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2660 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2661 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2662 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2663 ha->gid_list_info_size = 8;
2664 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2665 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2666 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2667 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2668 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2669 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2670 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2671 } else if (IS_QLA81XX(ha)) {
642ef983 2672 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2673 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2674 req_length = REQUEST_ENTRY_CNT_24XX;
2675 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2676 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2677 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2678 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2679 ha->gid_list_info_size = 8;
2680 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2681 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2682 ha->isp_ops = &qla81xx_isp_ops;
2683 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2684 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2685 ha->nvram_conf_off = ~0;
2686 ha->nvram_data_off = ~0;
a9083016 2687 } else if (IS_QLA82XX(ha)) {
642ef983 2688 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2689 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2690 req_length = REQUEST_ENTRY_CNT_82XX;
2691 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2692 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2693 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2694 ha->gid_list_info_size = 8;
2695 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2696 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2697 ha->isp_ops = &qla82xx_isp_ops;
2698 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2699 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2700 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2701 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2702 } else if (IS_QLA8044(ha)) {
2703 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2704 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2705 req_length = REQUEST_ENTRY_CNT_82XX;
2706 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2707 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2708 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2709 ha->gid_list_info_size = 8;
2710 ha->optrom_size = OPTROM_SIZE_83XX;
2711 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2712 ha->isp_ops = &qla8044_isp_ops;
2713 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2714 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2715 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2716 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2717 } else if (IS_QLA83XX(ha)) {
7d613ac6 2718 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2719 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2720 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2721 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2722 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2723 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2724 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2725 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2726 ha->gid_list_info_size = 8;
2727 ha->optrom_size = OPTROM_SIZE_83XX;
2728 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2729 ha->isp_ops = &qla83xx_isp_ops;
2730 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2731 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2732 ha->nvram_conf_off = ~0;
2733 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2734 } else if (IS_QLAFX00(ha)) {
2735 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2736 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2737 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2738 req_length = REQUEST_ENTRY_CNT_FX00;
2739 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2740 ha->isp_ops = &qlafx00_isp_ops;
2741 ha->port_down_retry_count = 30; /* default value */
2742 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2743 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2744 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2745 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2746 ha->mr.host_info_resend = false;
2747 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2748 } else if (IS_QLA27XX(ha)) {
2749 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2750 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2751 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2752 req_length = REQUEST_ENTRY_CNT_83XX;
2753 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2754 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2755 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2756 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2757 ha->gid_list_info_size = 8;
2758 ha->optrom_size = OPTROM_SIZE_83XX;
2759 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2760 ha->isp_ops = &qla27xx_isp_ops;
2761 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2762 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2763 ha->nvram_conf_off = ~0;
2764 ha->nvram_data_off = ~0;
1da177e4 2765 }
6246b8a1 2766
7c3df132
SK		 2767 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2768 "mbx_count=%d, req_length=%d, "
2769 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2770 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2771 "max_fibre_devices=%d.\n",
7c3df132
SK		 2772 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2773 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2774 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2775 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2776 "isp_ops=%p, flash_conf_off=%d, "
2777 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2778 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2779 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2780
2781 /* Configure PCI I/O space */
2782 ret = ha->isp_ops->iospace_config(ha);
2783 if (ret)
0a63ad12 2784 goto iospace_config_failed;
706f457d
GM		 2785
2786 ql_log_pci(ql_log_info, pdev, 0x001d,
2787 "Found an ISP%04X irq %d iobase 0x%p.\n",
2788 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2789 mutex_init(&ha->vport_lock);
d7459527 2790 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2791 init_completion(&ha->mbx_cmd_comp);
2792 complete(&ha->mbx_cmd_comp);
2793 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2794 init_completion(&ha->dcbx_comp);
f356bef1 2795 init_completion(&ha->lb_portup_comp);
1da177e4 2796
2c3dfe3f 2797 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2798
53303c42 2799 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2800 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2801 "64 Bit addressing is %s.\n",
2802 ha->flags.enable_64bit_addressing ? "enable" :
2803 "disable");
73208dfd 2804 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2805 if (ret) {
7c3df132
SK		 2806 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2807 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2808
e315cd28
AC		 2809 goto probe_hw_failed;
2810 }
2811
73208dfd 2812 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2813 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2814 req->max_q_depth = ql2xmaxqdepth;
2815
e315cd28
AC		 2816
2817 base_vha = qla2x00_create_host(sht, ha);
2818 if (!base_vha) {
a1541d5a 2819 ret = -ENOMEM;
6e9f21f3 2820 qla2x00_mem_free(ha);
2afa19a9
AC		 2821 qla2x00_free_req_que(ha, req);
2822 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2823 goto probe_hw_failed;
1da177e4
LT		 2824 }
2825
e315cd28 2826 pci_set_drvdata(pdev, base_vha);
6b383979 2827 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2828
e315cd28 2829 host = base_vha->host;
2afa19a9 2830 base_vha->req = req;
73208dfd 2831 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2832 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2833 else
e315cd28
AC		 2834 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2835 base_vha->vp_idx;
58548cb5 2836
8ae6d9c7
GM		 2837 /* Setup fcport template structure. */
2838 ha->mr.fcport.vha = base_vha;
2839 ha->mr.fcport.port_type = FCT_UNKNOWN;
2840 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2841 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2842 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2843 ha->mr.fcport.scan_state = 1;
2844
58548cb5
GM		 2845 /* Set the SG table size based on ISP type */
2846 if (!IS_FWI2_CAPABLE(ha)) {
2847 if (IS_QLA2100(ha))
2848 host->sg_tablesize = 32;
2849 } else {
2850 if (!IS_QLA82XX(ha))
2851 host->sg_tablesize = QLA_SG_ALL;
2852 }
642ef983 2853 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2854 host->cmd_per_lun = 3;
2855 host->unique_id = host->host_no;
e02587d7 2856 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2857 host->max_cmd_len = 32;
2858 else
2859 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2860 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2861 /* Older HBAs support only 16-bit LUNs */
2862 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2863 ql2xmaxlun > 0xffff)
2864 host->max_lun = 0xffff;
2865 else
2866 host->max_lun = ql2xmaxlun;
e315cd28 2867 host->transportt = qla2xxx_transport_template;
9a069e19 2868 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2869
7c3df132
SK		 2870 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2871 "max_id=%d this_id=%d "
2872 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2873 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2874 host->this_id, host->cmd_per_lun, host->unique_id,
2875 host->max_cmd_len, host->max_channel, host->max_lun,
2876 host->transportt, sht->vendor_id);
2877
d7459527
MH		 2878 /* Set up the irqs */
2879 ret = qla2x00_request_irqs(ha, rsp);
2880 if (ret)
2881 goto probe_init_failed;
2882
9a347ff4
CD		 2883 /* Alloc arrays of request and response ring ptrs */
2884 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2885 ql_log(ql_log_fatal, base_vha, 0x003d,
2886 "Failed to allocate memory for queue pointers..."
2887 "aborting.\n");
2888 goto probe_init_failed;
2889 }
2890
5601236b
MH		 2891 if (ha->mqenable && shost_use_blk_mq(host)) {
2892 /* number of hardware queues supported by blk/scsi-mq*/
2893 host->nr_hw_queues = ha->max_qpairs;
2894
2895 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2896 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2897 } else
2898 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2899 "blk/scsi-mq disabled.\n");
2900
2d70c103 2901 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2902
90a86fc0
JC		 2903 pci_save_state(pdev);
2904
9a347ff4 2905 /* Assign back pointers */
2afa19a9
AC		 2906 rsp->req = req;
2907 req->rsp = rsp;
9a347ff4 2908
8ae6d9c7
GM		 2909 if (IS_QLAFX00(ha)) {
2910 ha->rsp_q_map[0] = rsp;
2911 ha->req_q_map[0] = req;
2912 set_bit(0, ha->req_qid_map);
2913 set_bit(0, ha->rsp_qid_map);
2914 }
2915
08029990
AV		 2916 /* FWI2-capable only. */
2917 req->req_q_in = &ha->iobase->isp24.req_q_in;
2918 req->req_q_out = &ha->iobase->isp24.req_q_out;
2919 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2920 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2921 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2922 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2923 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2924 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2925 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2926 }
2927
8ae6d9c7
GM		 2928 if (IS_QLAFX00(ha)) {
2929 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2930 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2931 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2932 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2933 }
2934
7ec0effd 2935 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2936 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2937 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2938 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2939 }
2940
7c3df132
SK		 2941 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2942 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2943 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2944 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2945 "req->req_q_in=%p req->req_q_out=%p "
2946 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2947 req->req_q_in, req->req_q_out,
2948 rsp->rsp_q_in, rsp->rsp_q_out);
2949 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2950 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2951 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2952 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2953 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2954 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2955
8ae6d9c7 2956 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2957 ql_log(ql_log_fatal, base_vha, 0x00d6,
2958 "Failed to initialize adapter - Adapter flags %x.\n",
2959 base_vha->device_flags);
1da177e4 2960
a9083016
GM		 2961 if (IS_QLA82XX(ha)) {
2962 qla82xx_idc_lock(ha);
2963 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2964 QLA8XXX_DEV_FAILED);
a9083016 2965 qla82xx_idc_unlock(ha);
7c3df132
SK		 2966 ql_log(ql_log_fatal, base_vha, 0x00d7,
2967 "HW State: FAILED.\n");
7ec0effd
AD		 2968 } else if (IS_QLA8044(ha)) {
2969 qla8044_idc_lock(ha);
2970 qla8044_wr_direct(base_vha,
2971 QLA8044_CRB_DEV_STATE_INDEX,
2972 QLA8XXX_DEV_FAILED);
2973 qla8044_idc_unlock(ha);
2974 ql_log(ql_log_fatal, base_vha, 0x0150,
2975 "HW State: FAILED.\n");
a9083016
GM		 2976 }
2977
a1541d5a 2978 ret = -ENODEV;
1da177e4
LT		 2979 goto probe_failed;
2980 }
2981
3b1bef64
CD		 2982 if (IS_QLAFX00(ha))
2983 host->can_queue = QLAFX00_MAX_CANQUEUE;
2984 else
2985 host->can_queue = req->num_outstanding_cmds - 10;
2986
2987 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2988 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2989 host->can_queue, base_vha->req,
2990 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2991
5601236b 2992 if (ha->mqenable) {
d7459527 2993 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 2994 /* Create start of day qpairs for Block MQ */
2995 if (shost_use_blk_mq(host)) {
2996 for (i = 0; i < ha->max_qpairs; i++)
2997 qla2xxx_create_qpair(base_vha, 5, 0);
2998 }
2999 }
68ca949c 3000
cbc8eb67
AV		 3001 if (ha->flags.running_gold_fw)
3002 goto skip_dpc;
3003
1da177e4
LT		 3004 /*
3005 * Startup the kernel thread for this host adapter
3006 */
39a11240 3007 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3008 "%s_dpc", base_vha->host_str);
39a11240 3009 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3010 ql_log(ql_log_fatal, base_vha, 0x00ed,
3011 "Failed to start DPC thread.\n");
39a11240 3012 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3013 goto probe_failed;
3014 }
7c3df132
SK		 3015 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3016 "DPC thread started successfully.\n");
1da177e4 3017
2d70c103
NB		 3018 /*
3019 * If we're not coming up in initiator mode, we might sit for
3020 * a while without waking up the dpc thread, which leads to a
3021 * stuck process warning. So just kick the dpc once here and
3022 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3023 */
3024 qla2xxx_wake_dpc(base_vha);
3025
f3ddac19
CD		 3026 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3027
81178772
SK		 3028 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3029 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3030 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3031 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3032
3033 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3034 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3035 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3036 INIT_WORK(&ha->idc_state_handler,
3037 qla83xx_idc_state_handler_work);
3038 INIT_WORK(&ha->nic_core_unrecoverable,
3039 qla83xx_nic_core_unrecoverable_work);
3040 }
3041
cbc8eb67 3042skip_dpc:
e315cd28
AC		 3043 list_add_tail(&base_vha->list, &ha->vp_list);
3044 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3045
3046 /* Initialized the timer */
e315cd28 3047 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3048 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3049 "Started qla2x00_timer with "
3050 "interval=%d.\n", WATCH_INTERVAL);
3051 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3052 "Detected hba at address=%p.\n",
3053 ha);
d19044c3 3054
e02587d7 3055 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3056 if (ha->fw_attributes & BIT_4) {
9e522cd8 3057 int prot = 0, guard;
bad75002 3058 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3059 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3060 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3061 if (ql2xenabledif == 1)
3062 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3063 scsi_host_set_prot(host,
8cb2049c 3064 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3065 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3066 | SHOST_DIF_TYPE3_PROTECTION
3067 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3068 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3069 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3070
3071 guard = SHOST_DIX_GUARD_CRC;
3072
3073 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3074 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3075 guard |= SHOST_DIX_GUARD_IP;
3076
3077 scsi_host_set_guard(host, guard);
bad75002
AE		 3078 } else
3079 base_vha->flags.difdix_supported = 0;
3080 }
3081
a9083016
GM		 3082 ha->isp_ops->enable_intrs(ha);
3083
1fe19ee4
AB		 3084 if (IS_QLAFX00(ha)) {
3085 ret = qlafx00_fx_disc(base_vha,
3086 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3087 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3088 QLA_SG_ALL : 128;
3089 }
3090
a1541d5a
AV		 3091 ret = scsi_add_host(host, &pdev->dev);
3092 if (ret)
3093 goto probe_failed;
3094
1486400f
MR		 3095 base_vha->flags.init_done = 1;
3096 base_vha->flags.online = 1;
edaa5c74 3097 ha->prev_minidump_failed = 0;
1486400f 3098
7c3df132
SK		 3099 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3100 "Init done and hba is online.\n");
3101
2d70c103
NB		 3102 if (qla_ini_mode_enabled(base_vha))
3103 scsi_scan_host(host);
3104 else
3105 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3106 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3107
e315cd28 3108 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3109
8ae6d9c7 3110 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3111 ret = qlafx00_fx_disc(base_vha,
3112 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3113
3114 /* Register system information */
3115 ret = qlafx00_fx_disc(base_vha,
3116 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3117 }
3118
e315cd28 3119 qla2x00_init_host_attr(base_vha);
a1541d5a 3120
e315cd28 3121 qla2x00_dfs_setup(base_vha);
df613b96 3122
03eb912a
AB		 3123 ql_log(ql_log_info, base_vha, 0x00fb,
3124 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3125 ql_log(ql_log_info, base_vha, 0x00fc,
3126 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3127 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3128 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3129 base_vha->host_no,
df57caba 3130 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3131
2d70c103
NB		 3132 qlt_add_target(ha, base_vha);
3133
6b383979 3134 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3135
3136 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3137 return -ENODEV;
3138
1da177e4
LT		 3139 return 0;
3140
6e9f21f3 3141probe_init_failed:
2afa19a9 3142 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3143 ha->req_q_map[0] = NULL;
3144 clear_bit(0, ha->req_qid_map);
2afa19a9 3145 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3146 ha->rsp_q_map[0] = NULL;
3147 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3148 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3149
1da177e4 3150probe_failed:
b9978769
AV		 3151 if (base_vha->timer_active)
3152 qla2x00_stop_timer(base_vha);
3153 base_vha->flags.online = 0;
3154 if (ha->dpc_thread) {
3155 struct task_struct *t = ha->dpc_thread;
3156
3157 ha->dpc_thread = NULL;
3158 kthread_stop(t);
3159 }
3160
e315cd28 3161 qla2x00_free_device(base_vha);
1da177e4 3162
e315cd28 3163 scsi_host_put(base_vha->host);
1da177e4 3164
e315cd28 3165probe_hw_failed:
1a2fbf18
JL		 3166 qla2x00_clear_drv_active(ha);
3167
0a63ad12 3168iospace_config_failed:
7ec0effd 3169 if (IS_P3P_TYPE(ha)) {
0a63ad12 3170 if (!ha->nx_pcibase)
f73cb695 3171 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3172 if (!ql2xdbwr)
f73cb695 3173 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3174 } else {
3175 if (ha->iobase)
3176 iounmap(ha->iobase);
8ae6d9c7
GM		 3177 if (ha->cregbase)
3178 iounmap(ha->cregbase);
a9083016 3179 }
e315cd28
AC		 3180 pci_release_selected_regions(ha->pdev, ha->bars);
3181 kfree(ha);
3182 ha = NULL;
1da177e4 3183
a1541d5a 3184probe_out:
e315cd28 3185 pci_disable_device(pdev);
a1541d5a 3186 return ret;
1da177e4 3187}
1da177e4 3188
e30d1756
MI		 3189static void
3190qla2x00_shutdown(struct pci_dev *pdev)
3191{
3192 scsi_qla_host_t *vha;
3193 struct qla_hw_data *ha;
3194
552f3f9a
MI		 3195 if (!atomic_read(&pdev->enable_cnt))
3196 return;
3197
e30d1756
MI		 3198 vha = pci_get_drvdata(pdev);
3199 ha = vha->hw;
3200
42479343
AB		 3201 /* Notify ISPFX00 firmware */
3202 if (IS_QLAFX00(ha))
3203 qlafx00_driver_shutdown(vha, 20);
3204
e30d1756
MI		 3205 /* Turn-off FCE trace */
3206 if (ha->flags.fce_enabled) {
3207 qla2x00_disable_fce_trace(vha, NULL, NULL);
3208 ha->flags.fce_enabled = 0;
3209 }
3210
3211 /* Turn-off EFT trace */
3212 if (ha->eft)
3213 qla2x00_disable_eft_trace(vha);
3214
3215 /* Stop currently executing firmware. */
3216 qla2x00_try_to_stop_firmware(vha);
3217
3218 /* Turn adapter off line */
3219 vha->flags.online = 0;
3220
3221 /* turn-off interrupts on the card */
3222 if (ha->interrupts_on) {
3223 vha->flags.init_done = 0;
3224 ha->isp_ops->disable_intrs(ha);
3225 }
3226
3227 qla2x00_free_irqs(vha);
3228
3229 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3230
3231 pci_disable_pcie_error_reporting(pdev);
3232 pci_disable_device(pdev);
e30d1756
MI		 3233}
3234
fe1b806f 3235/* Deletes all the virtual ports for a given ha */
4c993f76 3236static void
fe1b806f 3237qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3238{
fe1b806f 3239 scsi_qla_host_t *vha;
feafb7b1 3240 unsigned long flags;
e315cd28 3241
43ebf16d
AE		 3242 mutex_lock(&ha->vport_lock);
3243 while (ha->cur_vport_count) {
43ebf16d 3244 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3245
43ebf16d
AE		 3246 BUG_ON(base_vha->list.next == &ha->vp_list);
3247 /* This assumes first entry in ha->vp_list is always base vha */
3248 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3249 scsi_host_get(vha->host);
feafb7b1 3250
43ebf16d
AE		 3251 spin_unlock_irqrestore(&ha->vport_slock, flags);
3252 mutex_unlock(&ha->vport_lock);
3253
3254 fc_vport_terminate(vha->fc_vport);
3255 scsi_host_put(vha->host);
feafb7b1 3256
43ebf16d 3257 mutex_lock(&ha->vport_lock);
e315cd28 3258 }
43ebf16d 3259 mutex_unlock(&ha->vport_lock);
fe1b806f 3260}
1da177e4 3261
fe1b806f
CD		 3262/* Stops all deferred work threads */
3263static void
3264qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3265{
68ca949c
AC		 3266 /* Flush the work queue and remove it */
3267 if (ha->wq) {
3268 flush_workqueue(ha->wq);
3269 destroy_workqueue(ha->wq);
3270 ha->wq = NULL;
3271 }
3272
7d613ac6
SV		 3273 /* Cancel all work and destroy DPC workqueues */
3274 if (ha->dpc_lp_wq) {
3275 cancel_work_sync(&ha->idc_aen);
3276 destroy_workqueue(ha->dpc_lp_wq);
3277 ha->dpc_lp_wq = NULL;
3278 }
3279
3280 if (ha->dpc_hp_wq) {
3281 cancel_work_sync(&ha->nic_core_reset);
3282 cancel_work_sync(&ha->idc_state_handler);
3283 cancel_work_sync(&ha->nic_core_unrecoverable);
3284 destroy_workqueue(ha->dpc_hp_wq);
3285 ha->dpc_hp_wq = NULL;
3286 }
3287
b9978769
AV		 3288 /* Kill the kernel thread for this host */
3289 if (ha->dpc_thread) {
3290 struct task_struct *t = ha->dpc_thread;
3291
3292 /*
3293 * qla2xxx_wake_dpc checks for ->dpc_thread
3294 * so we need to zero it out.
3295 */
3296 ha->dpc_thread = NULL;
3297 kthread_stop(t);
3298 }
fe1b806f 3299}
1da177e4 3300
fe1b806f
CD		 3301static void
3302qla2x00_unmap_iobases(struct qla_hw_data *ha)
3303{
a9083016 3304 if (IS_QLA82XX(ha)) {
b963752f 3305
f73cb695 3306 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3307 if (!ql2xdbwr)
f73cb695 3308 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3309 } else {
3310 if (ha->iobase)
3311 iounmap(ha->iobase);
1da177e4 3312
8ae6d9c7
GM		 3313 if (ha->cregbase)
3314 iounmap(ha->cregbase);
3315
a9083016
GM		 3316 if (ha->mqiobase)
3317 iounmap(ha->mqiobase);
6246b8a1 3318
f73cb695 3319 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3320 iounmap(ha->msixbase);
a9083016 3321 }
fe1b806f
CD		 3322}
3323
3324static void
db7157d4 3325qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3326{
fe1b806f
CD		 3327 if (IS_QLA8044(ha)) {
3328 qla8044_idc_lock(ha);
c41afc9a 3329 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3330 qla8044_idc_unlock(ha);
3331 } else if (IS_QLA82XX(ha)) {
3332 qla82xx_idc_lock(ha);
3333 qla82xx_clear_drv_active(ha);
3334 qla82xx_idc_unlock(ha);
3335 }
3336}
3337
3338static void
3339qla2x00_remove_one(struct pci_dev *pdev)
3340{
3341 scsi_qla_host_t *base_vha;
3342 struct qla_hw_data *ha;
3343
beb9e315
JL		 3344 base_vha = pci_get_drvdata(pdev);
3345 ha = base_vha->hw;
3346
3347 /* Indicate device removal to prevent future board_disable and wait
3348 * until any pending board_disable has completed. */
3349 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3350 cancel_work_sync(&ha->board_disable);
3351
fe1b806f 3352 /*
beb9e315
JL		 3353 * If the PCI device is disabled then there was a PCI-disconnect and
3354 * qla2x00_disable_board_on_pci_error has taken care of most of the
3355 * resources.
fe1b806f 3356 */
beb9e315
JL		 3357 if (!atomic_read(&pdev->enable_cnt)) {
3358 scsi_host_put(base_vha->host);
3359 kfree(ha);
3360 pci_set_drvdata(pdev, NULL);
fe1b806f 3361 return;
beb9e315 3362 }
fe1b806f 3363
638a1a01
SC		 3364 qla2x00_wait_for_hba_ready(base_vha);
3365
783e0dc4
SC		 3366 /* if UNLOAD flag is already set, then continue unload,
3367 * where it was set first.
3368 */
3369 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3370 return;
3371
fe1b806f
CD		 3372 set_bit(UNLOADING, &base_vha->dpc_flags);
3373
3374 if (IS_QLAFX00(ha))
3375 qlafx00_driver_shutdown(base_vha, 20);
3376
3377 qla2x00_delete_all_vps(ha, base_vha);
3378
3379 if (IS_QLA8031(ha)) {
3380 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3381 "Clearing fcoe driver presence.\n");
3382 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3383 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3384 "Error while clearing DRV-Presence.\n");
3385 }
3386
3387 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3388
3389 qla2x00_dfs_remove(base_vha);
3390
3391 qla84xx_put_chip(base_vha);
3392
2d5a4c34
HM		 3393 /* Laser should be disabled only for ISP2031 */
3394 if (IS_QLA2031(ha))
3395 qla83xx_disable_laser(base_vha);
3396
fe1b806f
CD		 3397 /* Disable timer */
3398 if (base_vha->timer_active)
3399 qla2x00_stop_timer(base_vha);
3400
3401 base_vha->flags.online = 0;
3402
b0d6cabd
HM		 3403 /* free DMA memory */
3404 if (ha->exlogin_buf)
3405 qla2x00_free_exlogin_buffer(ha);
3406
2f56a7f1
HM		 3407 /* free DMA memory */
3408 if (ha->exchoffld_buf)
3409 qla2x00_free_exchoffld_buffer(ha);
3410
fe1b806f
CD		 3411 qla2x00_destroy_deferred_work(ha);
3412
3413 qlt_remove_target(ha, base_vha);
3414
3415 qla2x00_free_sysfs_attr(base_vha, true);
3416
3417 fc_remove_host(base_vha->host);
3418
3419 scsi_remove_host(base_vha->host);
3420
3421 qla2x00_free_device(base_vha);
3422
db7157d4 3423 qla2x00_clear_drv_active(ha);
fe1b806f 3424
d2749ffa
AE		 3425 scsi_host_put(base_vha->host);
3426
fe1b806f 3427 qla2x00_unmap_iobases(ha);
73208dfd 3428
e315cd28
AC		 3429 pci_release_selected_regions(ha->pdev, ha->bars);
3430 kfree(ha);
3431 ha = NULL;
1da177e4 3432
90a86fc0
JC		 3433 pci_disable_pcie_error_reporting(pdev);
3434
665db93b 3435 pci_disable_device(pdev);
1da177e4 3436}
1da177e4
LT		 3437
3438static void
e315cd28 3439qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3440{
e315cd28 3441 struct qla_hw_data *ha = vha->hw;
1da177e4 3442
85880801
AV		 3443 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3444
3445 /* Disable timer */
3446 if (vha->timer_active)
3447 qla2x00_stop_timer(vha);
3448
2afa19a9 3449 qla25xx_delete_queues(vha);
fe1b806f 3450
df613b96 3451 if (ha->flags.fce_enabled)
e315cd28 3452 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3453
a7a167bf 3454 if (ha->eft)
e315cd28 3455 qla2x00_disable_eft_trace(vha);
a7a167bf 3456
f6ef3b18 3457 /* Stop currently executing firmware. */
e315cd28 3458 qla2x00_try_to_stop_firmware(vha);
1da177e4 3459
85880801
AV		 3460 vha->flags.online = 0;
3461
f6ef3b18 3462 /* turn-off interrupts on the card */
a9083016
GM		 3463 if (ha->interrupts_on) {
3464 vha->flags.init_done = 0;
fd34f556 3465 ha->isp_ops->disable_intrs(ha);
a9083016 3466 }
f6ef3b18 3467
e315cd28 3468 qla2x00_free_irqs(vha);
1da177e4 3469
8867048b
CD		 3470 qla2x00_free_fcports(vha);
3471
e315cd28 3472 qla2x00_mem_free(ha);
73208dfd 3473
08de2844
GM		 3474 qla82xx_md_free(vha);
3475
73208dfd 3476 qla2x00_free_queues(ha);
1da177e4
LT		 3477}
3478
8867048b
CD		 3479void qla2x00_free_fcports(struct scsi_qla_host *vha)
3480{
3481 fc_port_t *fcport, *tfcport;
3482
3483 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3484 list_del(&fcport->list);
5f16b331 3485 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3486 kfree(fcport);
3487 fcport = NULL;
3488 }
3489}
3490
d97994dc 3491static inline void
e315cd28 3492qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3493 int defer)
3494{
d97994dc 3495 struct fc_rport *rport;
67becc00 3496 scsi_qla_host_t *base_vha;
044d78e1 3497 unsigned long flags;
d97994dc
AV		 3498
3499 if (!fcport->rport)
3500 return;
3501
3502 rport = fcport->rport;
3503 if (defer) {
67becc00 3504 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3505 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3506 fcport->drport = rport;
044d78e1 3507 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3508 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3509 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3510 qla2xxx_wake_dpc(base_vha);
2d70c103 3511 } else {
df673274 3512 int now;
d20ed91b
AP		 3513 if (rport)
3514 fc_remote_port_delete(rport);
df673274
AP		 3515 qlt_do_generation_tick(vha, &now);
3516 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3517 }
d97994dc
AV		 3518}
3519
1da177e4
LT		 3520/*
3521 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3522 *
3523 * Input: ha = adapter block pointer. fcport = port structure pointer.
3524 *
3525 * Return: None.
3526 *
3527 * Context:
3528 */
e315cd28 3529void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3530 int do_login, int defer)
1da177e4 3531{
8ae6d9c7
GM		 3532 if (IS_QLAFX00(vha->hw)) {
3533 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3534 qla2x00_schedule_rport_del(vha, fcport, defer);
3535 return;
3536 }
3537
2c3dfe3f 3538 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3539 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3540 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3541 qla2x00_schedule_rport_del(vha, fcport, defer);
3542 }
fa2a1ce5 3543 /*
1da177e4
LT		 3544 * We may need to retry the login, so don't change the state of the
3545 * port but do the retries.
3546 */
3547 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3548 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3549
3550 if (!do_login)
3551 return;
3552
a1d0285e
AE		 3553 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3554
1da177e4 3555 if (fcport->login_retry == 0) {
e315cd28 3556 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3557
7c3df132 3558 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3559 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3560 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3561 }
3562}
3563
3564/*
3565 * qla2x00_mark_all_devices_lost
3566 * Updates fcport state when device goes offline.
3567 *
3568 * Input:
3569 * ha = adapter block pointer.
3570 * fcport = port structure pointer.
3571 *
3572 * Return:
3573 * None.
3574 *
3575 * Context:
3576 */
3577void
e315cd28 3578qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3579{
3580 fc_port_t *fcport;
3581
e315cd28 3582 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3583 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3584 continue;
0d6e61bc 3585
1da177e4
LT		 3586 /*
3587 * No point in marking the device as lost, if the device is
3588 * already DEAD.
3589 */
3590 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3591 continue;
e315cd28 3592 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3593 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3594 if (defer)
3595 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3596 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3597 qla2x00_schedule_rport_del(vha, fcport, defer);
3598 }
1da177e4
LT		 3599 }
3600}
3601
3602/*
3603* qla2x00_mem_alloc
3604* Allocates adapter memory.
3605*
3606* Returns:
3607* 0 = success.
e8711085 3608* !0 = failure.
1da177e4 3609*/
e8711085 3610static int
73208dfd
AC		 3611qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3612 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3613{
3614 char name[16];
1da177e4 3615
e8711085 3616 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3617 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3618 if (!ha->init_cb)
e315cd28 3619 goto fail;
e8711085 3620
2d70c103
NB		 3621 if (qlt_mem_alloc(ha) < 0)
3622 goto fail_free_init_cb;
3623
642ef983
CD		 3624 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3625 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3626 if (!ha->gid_list)
2d70c103 3627 goto fail_free_tgt_mem;
1da177e4 3628
e8711085
AV		 3629 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3630 if (!ha->srb_mempool)
e315cd28 3631 goto fail_free_gid_list;
e8711085 3632
7ec0effd 3633 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3634 /* Allocate cache for CT6 Ctx. */
3635 if (!ctx_cachep) {
3636 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3637 sizeof(struct ct6_dsd), 0,
3638 SLAB_HWCACHE_ALIGN, NULL);
3639 if (!ctx_cachep)
3640 goto fail_free_gid_list;
3641 }
3642 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3643 ctx_cachep);
3644 if (!ha->ctx_mempool)
3645 goto fail_free_srb_mempool;
7c3df132
SK		 3646 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3647 "ctx_cachep=%p ctx_mempool=%p.\n",
3648 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3649 }
3650
e8711085
AV		 3651 /* Get memory for cached NVRAM */
3652 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3653 if (!ha->nvram)
a9083016 3654 goto fail_free_ctx_mempool;
e8711085 3655
e315cd28
AC		 3656 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3657 ha->pdev->device);
3658 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3659 DMA_POOL_SIZE, 8, 0);
3660 if (!ha->s_dma_pool)
3661 goto fail_free_nvram;
3662
7c3df132
SK		 3663 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3664 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3665 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3666
7ec0effd 3667 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3668 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3669 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3670 if (!ha->dl_dma_pool) {
7c3df132
SK		 3671 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3672 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3673 goto fail_s_dma_pool;
3674 }
3675
3676 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3677 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3678 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3679 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3680 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3681 goto fail_dl_dma_pool;
3682 }
7c3df132
SK		 3683 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3684 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3685 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3686 }
3687
e8711085
AV		 3688 /* Allocate memory for SNS commands */
3689 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3690 /* Get consistent memory allocated for SNS commands */
e8711085 3691 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3692 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3693 if (!ha->sns_cmd)
e315cd28 3694 goto fail_dma_pool;
7c3df132 3695 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3696 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3697 } else {
e315cd28 3698 /* Get consistent memory allocated for MS IOCB */
e8711085 3699 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3700 &ha->ms_iocb_dma);
e8711085 3701 if (!ha->ms_iocb)
e315cd28
AC		 3702 goto fail_dma_pool;
3703 /* Get consistent memory allocated for CT SNS commands */
e8711085 3704 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3705 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3706 if (!ha->ct_sns)
3707 goto fail_free_ms_iocb;
7c3df132
SK		 3708 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3709 "ms_iocb=%p ct_sns=%p.\n",
3710 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3711 }
3712
e315cd28 3713 /* Allocate memory for request ring */
73208dfd
AC		 3714 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3715 if (!*req) {
7c3df132
SK		 3716 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3717 "Failed to allocate memory for req.\n");
e315cd28
AC		 3718 goto fail_req;
3719 }
73208dfd
AC		 3720 (*req)->length = req_len;
3721 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3722 ((*req)->length + 1) * sizeof(request_t),
3723 &(*req)->dma, GFP_KERNEL);
3724 if (!(*req)->ring) {
7c3df132
SK		 3725 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3726 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3727 goto fail_req_ring;
3728 }
3729 /* Allocate memory for response ring */
73208dfd
AC		 3730 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3731 if (!*rsp) {
7c3df132
SK		 3732 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3733 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3734 goto fail_rsp;
3735 }
73208dfd
AC		 3736 (*rsp)->hw = ha;
3737 (*rsp)->length = rsp_len;
3738 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3739 ((*rsp)->length + 1) * sizeof(response_t),
3740 &(*rsp)->dma, GFP_KERNEL);
3741 if (!(*rsp)->ring) {
7c3df132
SK		 3742 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3743 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3744 goto fail_rsp_ring;
3745 }
73208dfd
AC		 3746 (*req)->rsp = *rsp;
3747 (*rsp)->req = *req;
7c3df132
SK		 3748 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3749 "req=%p req->length=%d req->ring=%p rsp=%p "
3750 "rsp->length=%d rsp->ring=%p.\n",
3751 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3752 (*rsp)->ring);
73208dfd
AC		 3753 /* Allocate memory for NVRAM data for vports */
3754 if (ha->nvram_npiv_size) {
3755 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3756 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3757 if (!ha->npiv_info) {
7c3df132
SK		 3758 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3759 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3760 goto fail_npiv_info;
3761 }
3762 } else
3763 ha->npiv_info = NULL;
e8711085 3764
b64b0e8f 3765 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3766 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3767 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3768 &ha->ex_init_cb_dma);
3769 if (!ha->ex_init_cb)
3770 goto fail_ex_init_cb;
7c3df132
SK		 3771 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3772 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3773 }
3774
a9083016
GM		 3775 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3776
5ff1d584
AV		 3777 /* Get consistent memory allocated for Async Port-Database. */
3778 if (!IS_FWI2_CAPABLE(ha)) {
3779 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3780 &ha->async_pd_dma);
3781 if (!ha->async_pd)
3782 goto fail_async_pd;
7c3df132
SK		 3783 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3784 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3785 }
3786
e315cd28 3787 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3788
3789 /* Allocate memory for our loop_id bitmap */
3790 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3791 GFP_KERNEL);
3792 if (!ha->loop_id_map)
3793 goto fail_async_pd;
3794 else {
3795 qla2x00_set_reserved_loop_ids(ha);
3796 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3797 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3798 }
3799
b2a72ec3 3800 return 0;
e315cd28 3801
5ff1d584
AV		 3802fail_async_pd:
3803 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3804fail_ex_init_cb:
3805 kfree(ha->npiv_info);
73208dfd
AC		 3806fail_npiv_info:
3807 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3808 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3809 (*rsp)->ring = NULL;
3810 (*rsp)->dma = 0;
e315cd28 3811fail_rsp_ring:
73208dfd 3812 kfree(*rsp);
e315cd28 3813fail_rsp:
73208dfd
AC		 3814 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3815 sizeof(request_t), (*req)->ring, (*req)->dma);
3816 (*req)->ring = NULL;
3817 (*req)->dma = 0;
e315cd28 3818fail_req_ring:
73208dfd 3819 kfree(*req);
e315cd28
AC		 3820fail_req:
3821 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3822 ha->ct_sns, ha->ct_sns_dma);
3823 ha->ct_sns = NULL;
3824 ha->ct_sns_dma = 0;
e8711085
AV		 3825fail_free_ms_iocb:
3826 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3827 ha->ms_iocb = NULL;
3828 ha->ms_iocb_dma = 0;
e315cd28 3829fail_dma_pool:
bad75002 3830 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3831 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3832 ha->fcp_cmnd_dma_pool = NULL;
3833 }
3834fail_dl_dma_pool:
bad75002 3835 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3836 dma_pool_destroy(ha->dl_dma_pool);
3837 ha->dl_dma_pool = NULL;
3838 }
3839fail_s_dma_pool:
e315cd28
AC		 3840 dma_pool_destroy(ha->s_dma_pool);
3841 ha->s_dma_pool = NULL;
e8711085
AV		 3842fail_free_nvram:
3843 kfree(ha->nvram);
3844 ha->nvram = NULL;
a9083016
GM		 3845fail_free_ctx_mempool:
3846 mempool_destroy(ha->ctx_mempool);
3847 ha->ctx_mempool = NULL;
e8711085
AV		 3848fail_free_srb_mempool:
3849 mempool_destroy(ha->srb_mempool);
3850 ha->srb_mempool = NULL;
e8711085 3851fail_free_gid_list:
642ef983
CD		 3852 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3853 ha->gid_list,
e315cd28 3854 ha->gid_list_dma);
e8711085
AV		 3855 ha->gid_list = NULL;
3856 ha->gid_list_dma = 0;
2d70c103
NB		 3857fail_free_tgt_mem:
3858 qlt_mem_free(ha);
e315cd28
AC		 3859fail_free_init_cb:
3860 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3861 ha->init_cb_dma);
3862 ha->init_cb = NULL;
3863 ha->init_cb_dma = 0;
e8711085 3864fail:
7c3df132
SK		 3865 ql_log(ql_log_fatal, NULL, 0x0030,
3866 "Memory allocation failure.\n");
e8711085 3867 return -ENOMEM;
1da177e4
LT		 3868}
3869
b0d6cabd
HM		 3870int
3871qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3872{
3873 int rval;
3874 uint16_t size, max_cnt, temp;
3875 struct qla_hw_data *ha = vha->hw;
3876
3877 /* Return if we don't need to alloacate any extended logins */
3878 if (!ql2xexlogins)
3879 return QLA_SUCCESS;
3880
3881 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3882 max_cnt = 0;
3883 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3884 if (rval != QLA_SUCCESS) {
3885 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3886 "Failed to get exlogin status.\n");
3887 return rval;
3888 }
3889
3890 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3891 ha->exlogin_size = (size * temp);
3892 ql_log(ql_log_info, vha, 0xd024,
3893 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3894 max_cnt, size, temp);
3895
3896 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3897 ha->exlogin_size);
3898
3899 /* Get consistent memory for extended logins */
3900 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3901 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3902 if (!ha->exlogin_buf) {
3903 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3904 "Failed to allocate memory for exlogin_buf_dma.\n");
3905 return -ENOMEM;
3906 }
3907
3908 /* Now configure the dma buffer */
3909 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3910 if (rval) {
3911 ql_log(ql_log_fatal, vha, 0x00cf,
3912 "Setup extended login buffer ****FAILED****.\n");
3913 qla2x00_free_exlogin_buffer(ha);
3914 }
3915
3916 return rval;
3917}
3918
3919/*
3920* qla2x00_free_exlogin_buffer
3921*
3922* Input:
3923* ha = adapter block pointer
3924*/
3925void
3926qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3927{
3928 if (ha->exlogin_buf) {
3929 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3930 ha->exlogin_buf, ha->exlogin_buf_dma);
3931 ha->exlogin_buf = NULL;
3932 ha->exlogin_size = 0;
3933 }
3934}
3935
2f56a7f1
HM		 3936int
3937qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3938{
3939 int rval;
3940 uint16_t size, max_cnt, temp;
3941 struct qla_hw_data *ha = vha->hw;
3942
3943 /* Return if we don't need to alloacate any extended logins */
3944 if (!ql2xexchoffld)
3945 return QLA_SUCCESS;
3946
3947 ql_log(ql_log_info, vha, 0xd014,
3948 "Exchange offload count: %d.\n", ql2xexlogins);
3949
3950 max_cnt = 0;
3951 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3952 if (rval != QLA_SUCCESS) {
3953 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3954 "Failed to get exlogin status.\n");
3955 return rval;
3956 }
3957
3958 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3959 ha->exchoffld_size = (size * temp);
3960 ql_log(ql_log_info, vha, 0xd016,
3961 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3962 max_cnt, size, temp);
3963
3964 ql_log(ql_log_info, vha, 0xd017,
3965 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3966
3967 /* Get consistent memory for extended logins */
3968 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3969 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3970 if (!ha->exchoffld_buf) {
3971 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
3972 "Failed to allocate memory for exchoffld_buf_dma.\n");
3973 return -ENOMEM;
3974 }
3975
3976 /* Now configure the dma buffer */
3977 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
3978 if (rval) {
3979 ql_log(ql_log_fatal, vha, 0xd02e,
3980 "Setup exchange offload buffer ****FAILED****.\n");
3981 qla2x00_free_exchoffld_buffer(ha);
3982 }
3983
3984 return rval;
3985}
3986
3987/*
3988* qla2x00_free_exchoffld_buffer
3989*
3990* Input:
3991* ha = adapter block pointer
3992*/
3993void
3994qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
3995{
3996 if (ha->exchoffld_buf) {
3997 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
3998 ha->exchoffld_buf, ha->exchoffld_buf_dma);
3999 ha->exchoffld_buf = NULL;
4000 ha->exchoffld_size = 0;
4001 }
4002}
4003
1da177e4 4004/*
e30d1756
MI		 4005* qla2x00_free_fw_dump
4006* Frees fw dump stuff.
1da177e4
LT		 4007*
4008* Input:
7ec0effd 4009* ha = adapter block pointer
1da177e4 4010*/
a824ebb3 4011static void
e30d1756 4012qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4013{
df613b96 4014 if (ha->fce)
f73cb695
CD		 4015 dma_free_coherent(&ha->pdev->dev,
4016 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4017
f73cb695
CD		 4018 if (ha->eft)
4019 dma_free_coherent(&ha->pdev->dev,
4020 EFT_SIZE, ha->eft, ha->eft_dma);
4021
4022 if (ha->fw_dump)
a7a167bf 4023 vfree(ha->fw_dump);
f73cb695
CD		 4024 if (ha->fw_dump_template)
4025 vfree(ha->fw_dump_template);
4026
e30d1756
MI		 4027 ha->fce = NULL;
4028 ha->fce_dma = 0;
4029 ha->eft = NULL;
4030 ha->eft_dma = 0;
e30d1756 4031 ha->fw_dumped = 0;
61f098dd 4032 ha->fw_dump_cap_flags = 0;
e30d1756 4033 ha->fw_dump_reading = 0;
f73cb695
CD		 4034 ha->fw_dump = NULL;
4035 ha->fw_dump_len = 0;
4036 ha->fw_dump_template = NULL;
4037 ha->fw_dump_template_len = 0;
e30d1756
MI		 4038}
4039
4040/*
4041* qla2x00_mem_free
4042* Frees all adapter allocated memory.
4043*
4044* Input:
4045* ha = adapter block pointer.
4046*/
4047static void
4048qla2x00_mem_free(struct qla_hw_data *ha)
4049{
4050 qla2x00_free_fw_dump(ha);
4051
81178772
SK		 4052 if (ha->mctp_dump)
4053 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4054 ha->mctp_dump_dma);
4055
e30d1756
MI		 4056 if (ha->srb_mempool)
4057 mempool_destroy(ha->srb_mempool);
a7a167bf 4058
11bbc1d8
AV		 4059 if (ha->dcbx_tlv)
4060 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4061 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4062
ce0423f4
AV		 4063 if (ha->xgmac_data)
4064 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4065 ha->xgmac_data, ha->xgmac_data_dma);
4066
1da177e4
LT		 4067 if (ha->sns_cmd)
4068 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4069 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4070
4071 if (ha->ct_sns)
4072 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4073 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4074
88729e53
AV		 4075 if (ha->sfp_data)
4076 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4077
1da177e4
LT		 4078 if (ha->ms_iocb)
4079 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4080
b64b0e8f 4081 if (ha->ex_init_cb)
a9083016
GM		 4082 dma_pool_free(ha->s_dma_pool,
4083 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4084
5ff1d584
AV		 4085 if (ha->async_pd)
4086 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4087
1da177e4
LT		 4088 if (ha->s_dma_pool)
4089 dma_pool_destroy(ha->s_dma_pool);
4090
1da177e4 4091 if (ha->gid_list)
642ef983
CD		 4092 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4093 ha->gid_list, ha->gid_list_dma);
1da177e4 4094
a9083016
GM		 4095 if (IS_QLA82XX(ha)) {
4096 if (!list_empty(&ha->gbl_dsd_list)) {
4097 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4098
4099 /* clean up allocated prev pool */
4100 list_for_each_entry_safe(dsd_ptr,
4101 tdsd_ptr, &ha->gbl_dsd_list, list) {
4102 dma_pool_free(ha->dl_dma_pool,
4103 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4104 list_del(&dsd_ptr->list);
4105 kfree(dsd_ptr);
4106 }
4107 }
4108 }
4109
4110 if (ha->dl_dma_pool)
4111 dma_pool_destroy(ha->dl_dma_pool);
4112
4113 if (ha->fcp_cmnd_dma_pool)
4114 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4115
4116 if (ha->ctx_mempool)
4117 mempool_destroy(ha->ctx_mempool);
4118
2d70c103
NB		 4119 qlt_mem_free(ha);
4120
e315cd28
AC		 4121 if (ha->init_cb)
4122 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4123 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4124 vfree(ha->optrom_buffer);
4125 kfree(ha->nvram);
73208dfd 4126 kfree(ha->npiv_info);
7a67735b 4127 kfree(ha->swl);
5f16b331 4128 kfree(ha->loop_id_map);
1da177e4 4129
e8711085 4130 ha->srb_mempool = NULL;
a9083016 4131 ha->ctx_mempool = NULL;
1da177e4
LT		 4132 ha->sns_cmd = NULL;
4133 ha->sns_cmd_dma = 0;
4134 ha->ct_sns = NULL;
4135 ha->ct_sns_dma = 0;
4136 ha->ms_iocb = NULL;
4137 ha->ms_iocb_dma = 0;
1da177e4
LT		 4138 ha->init_cb = NULL;
4139 ha->init_cb_dma = 0;
b64b0e8f
AV		 4140 ha->ex_init_cb = NULL;
4141 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4142 ha->async_pd = NULL;
4143 ha->async_pd_dma = 0;
1da177e4
LT		 4144
4145 ha->s_dma_pool = NULL;
a9083016
GM		 4146 ha->dl_dma_pool = NULL;
4147 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4148
1da177e4
LT		 4149 ha->gid_list = NULL;
4150 ha->gid_list_dma = 0;
2d70c103
NB		 4151
4152 ha->tgt.atio_ring = NULL;
4153 ha->tgt.atio_dma = 0;
4154 ha->tgt.tgt_vp_map = NULL;
e315cd28 4155}
1da177e4 4156
e315cd28
AC		 4157struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4158 struct qla_hw_data *ha)
4159{
4160 struct Scsi_Host *host;
4161 struct scsi_qla_host *vha = NULL;
854165f4 4162
e315cd28
AC		 4163 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4164 if (host == NULL) {
7c3df132
SK		 4165 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4166 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 4167 goto fail;
4168 }
4169
4170 /* Clear our data area */
4171 vha = shost_priv(host);
4172 memset(vha, 0, sizeof(scsi_qla_host_t));
4173
4174 vha->host = host;
4175 vha->host_no = host->host_no;
4176 vha->hw = ha;
4177
4178 INIT_LIST_HEAD(&vha->vp_fcports);
4179 INIT_LIST_HEAD(&vha->work_list);
4180 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4181 INIT_LIST_HEAD(&vha->qla_cmd_list);
4182 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4183 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4184 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4185 INIT_LIST_HEAD(&vha->qp_list);
e315cd28 4186
f999f4c1 4187 spin_lock_init(&vha->work_lock);
8b2f5ff3 4188 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 4189
e315cd28 4190 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4191 ql_dbg(ql_dbg_init, vha, 0x0041,
4192 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4193 vha->host, vha->hw, vha,
4194 dev_name(&(ha->pdev->dev)));
4195
e315cd28
AC		 4196 return vha;
4197
4198fail:
4199 return vha;
1da177e4
LT		 4200}
4201
01ef66bb 4202static struct qla_work_evt *
f999f4c1 4203qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4204{
4205 struct qla_work_evt *e;
feafb7b1
AE		 4206 uint8_t bail;
4207
4208 QLA_VHA_MARK_BUSY(vha, bail);
4209 if (bail)
4210 return NULL;
0971de7f 4211
f999f4c1 4212 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4213 if (!e) {
4214 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4215 return NULL;
feafb7b1 4216 }
0971de7f
AV		 4217
4218 INIT_LIST_HEAD(&e->list);
4219 e->type = type;
4220 e->flags = QLA_EVT_FLAG_FREE;
4221 return e;
4222}
4223
01ef66bb 4224static int
f999f4c1 4225qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4226{
f999f4c1 4227 unsigned long flags;
0971de7f 4228
f999f4c1 4229 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4230 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4231 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 4232 qla2xxx_wake_dpc(vha);
f999f4c1 4233
0971de7f
AV		 4234 return QLA_SUCCESS;
4235}
4236
4237int
e315cd28 4238qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4239 u32 data)
4240{
4241 struct qla_work_evt *e;
4242
f999f4c1 4243 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4244 if (!e)
4245 return QLA_FUNCTION_FAILED;
4246
4247 e->u.aen.code = code;
4248 e->u.aen.data = data;
f999f4c1 4249 return qla2x00_post_work(vha, e);
0971de7f
AV		 4250}
4251
8a659571
AV		 4252int
4253qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4254{
4255 struct qla_work_evt *e;
4256
f999f4c1 4257 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4258 if (!e)
4259 return QLA_FUNCTION_FAILED;
4260
4261 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4262 return qla2x00_post_work(vha, e);
8a659571
AV		 4263}
4264
ac280b67
AV		 4265#define qla2x00_post_async_work(name, type) \
4266int qla2x00_post_async_##name##_work( \
4267 struct scsi_qla_host *vha, \
4268 fc_port_t *fcport, uint16_t *data) \
4269{ \
4270 struct qla_work_evt *e; \
4271 \
4272 e = qla2x00_alloc_work(vha, type); \
4273 if (!e) \
4274 return QLA_FUNCTION_FAILED; \
4275 \
4276 e->u.logio.fcport = fcport; \
4277 if (data) { \
4278 e->u.logio.data[0] = data[0]; \
4279 e->u.logio.data[1] = data[1]; \
4280 } \
4281 return qla2x00_post_work(vha, e); \
4282}
4283
4284qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4285qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4286qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4287qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4288qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4289qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4290
3420d36c
AV		 4291int
4292qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4293{
4294 struct qla_work_evt *e;
4295
4296 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4297 if (!e)
4298 return QLA_FUNCTION_FAILED;
4299
4300 e->u.uevent.code = code;
4301 return qla2x00_post_work(vha, e);
4302}
4303
4304static void
4305qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4306{
4307 char event_string[40];
4308 char *envp[] = { event_string, NULL };
4309
4310 switch (code) {
4311 case QLA_UEVENT_CODE_FW_DUMP:
4312 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4313 vha->host_no);
4314 break;
4315 default:
4316 /* do nothing */
4317 break;
4318 }
4319 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4320}
4321
8ae6d9c7
GM		 4322int
4323qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4324 uint32_t *data, int cnt)
4325{
4326 struct qla_work_evt *e;
4327
4328 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4329 if (!e)
4330 return QLA_FUNCTION_FAILED;
4331
4332 e->u.aenfx.evtcode = evtcode;
4333 e->u.aenfx.count = cnt;
4334 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4335 return qla2x00_post_work(vha, e);
4336}
4337
ac280b67 4338void
e315cd28 4339qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4340{
f999f4c1
AV		 4341 struct qla_work_evt *e, *tmp;
4342 unsigned long flags;
4343 LIST_HEAD(work);
0971de7f 4344
f999f4c1
AV		 4345 spin_lock_irqsave(&vha->work_lock, flags);
4346 list_splice_init(&vha->work_list, &work);
4347 spin_unlock_irqrestore(&vha->work_lock, flags);
4348
4349 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4350 list_del_init(&e->list);
0971de7f
AV		 4351
4352 switch (e->type) {
4353 case QLA_EVT_AEN:
e315cd28 4354 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4355 e->u.aen.code, e->u.aen.data);
4356 break;
8a659571
AV		 4357 case QLA_EVT_IDC_ACK:
4358 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4359 break;
ac280b67
AV		 4360 case QLA_EVT_ASYNC_LOGIN:
4361 qla2x00_async_login(vha, e->u.logio.fcport,
4362 e->u.logio.data);
4363 break;
4364 case QLA_EVT_ASYNC_LOGIN_DONE:
4365 qla2x00_async_login_done(vha, e->u.logio.fcport,
4366 e->u.logio.data);
4367 break;
4368 case QLA_EVT_ASYNC_LOGOUT:
4369 qla2x00_async_logout(vha, e->u.logio.fcport);
4370 break;
4371 case QLA_EVT_ASYNC_LOGOUT_DONE:
4372 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4373 e->u.logio.data);
4374 break;
5ff1d584
AV		 4375 case QLA_EVT_ASYNC_ADISC:
4376 qla2x00_async_adisc(vha, e->u.logio.fcport,
4377 e->u.logio.data);
4378 break;
4379 case QLA_EVT_ASYNC_ADISC_DONE:
4380 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4381 e->u.logio.data);
4382 break;
3420d36c
AV		 4383 case QLA_EVT_UEVENT:
4384 qla2x00_uevent_emit(vha, e->u.uevent.code);
4385 break;
8ae6d9c7
GM		 4386 case QLA_EVT_AENFX:
4387 qlafx00_process_aen(vha, e);
4388 break;
0971de7f
AV		 4389 }
4390 if (e->flags & QLA_EVT_FLAG_FREE)
4391 kfree(e);
feafb7b1
AE		 4392
4393 /* For each work completed decrement vha ref count */
4394 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4395 }
e315cd28 4396}
f999f4c1 4397
e315cd28
AC		 4398/* Relogins all the fcports of a vport
4399 * Context: dpc thread
4400 */
4401void qla2x00_relogin(struct scsi_qla_host *vha)
4402{
4403 fc_port_t *fcport;
c6b2fca8 4404 int status;
e315cd28
AC		 4405 uint16_t next_loopid = 0;
4406 struct qla_hw_data *ha = vha->hw;
ac280b67 4407 uint16_t data[2];
e315cd28
AC		 4408
4409 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4410 /*
4411 * If the port is not ONLINE then try to login
4412 * to it if we haven't run out of retries.
4413 */
5ff1d584
AV		 4414 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4415 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4416 fcport->login_retry--;
e315cd28 4417 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4418 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4419 ha->isp_ops->fabric_logout(vha,
4420 fcport->loop_id,
4421 fcport->d_id.b.domain,
4422 fcport->d_id.b.area,
4423 fcport->d_id.b.al_pa);
4424
03bcfb57
JC		 4425 if (fcport->loop_id == FC_NO_LOOP_ID) {
4426 fcport->loop_id = next_loopid =
4427 ha->min_external_loopid;
4428 status = qla2x00_find_new_loop_id(
4429 vha, fcport);
4430 if (status != QLA_SUCCESS) {
4431 /* Ran out of IDs to use */
4432 break;
4433 }
4434 }
4435
ac280b67 4436 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4437 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4438 data[0] = 0;
4439 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4440 status = qla2x00_post_async_login_work(
4441 vha, fcport, data);
4442 if (status == QLA_SUCCESS)
4443 continue;
4444 /* Attempt a retry. */
4445 status = 1;
aaf4d3e2 4446 } else {
ac280b67
AV		 4447 status = qla2x00_fabric_login(vha,
4448 fcport, &next_loopid);
aaf4d3e2
SK		 4449 if (status == QLA_SUCCESS) {
4450 int status2;
4451 uint8_t opts;
4452
4453 opts = 0;
4454 if (fcport->flags &
4455 FCF_FCP2_DEVICE)
4456 opts |= BIT_1;
03003960
SK		 4457 status2 =
4458 qla2x00_get_port_database(
4459 vha, fcport, opts);
aaf4d3e2
SK		 4460 if (status2 != QLA_SUCCESS)
4461 status = 1;
4462 }
4463 }
e315cd28
AC		 4464 } else
4465 status = qla2x00_local_device_login(vha,
4466 fcport);
4467
e315cd28
AC		 4468 if (status == QLA_SUCCESS) {
4469 fcport->old_loop_id = fcport->loop_id;
4470
7c3df132
SK		 4471 ql_dbg(ql_dbg_disc, vha, 0x2003,
4472 "Port login OK: logged in ID 0x%x.\n",
4473 fcport->loop_id);
e315cd28
AC		 4474
4475 qla2x00_update_fcport(vha, fcport);
4476
4477 } else if (status == 1) {
4478 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4479 /* retry the login again */
7c3df132
SK		 4480 ql_dbg(ql_dbg_disc, vha, 0x2007,
4481 "Retrying %d login again loop_id 0x%x.\n",
4482 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4483 } else {
4484 fcport->login_retry = 0;
4485 }
4486
4487 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4488 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4489 }
4490 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4491 break;
0971de7f 4492 }
0971de7f
AV		 4493}
4494
7d613ac6
SV		 4495/* Schedule work on any of the dpc-workqueues */
4496void
4497qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4498{
4499 struct qla_hw_data *ha = base_vha->hw;
4500
4501 switch (work_code) {
4502 case MBA_IDC_AEN: /* 0x8200 */
4503 if (ha->dpc_lp_wq)
4504 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4505 break;
4506
4507 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4508 if (!ha->flags.nic_core_reset_hdlr_active) {
4509 if (ha->dpc_hp_wq)
4510 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4511 } else
4512 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4513 "NIC Core reset is already active. Skip "
4514 "scheduling it again.\n");
4515 break;
4516 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4517 if (ha->dpc_hp_wq)
4518 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4519 break;
4520 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4521 if (ha->dpc_hp_wq)
4522 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4523 break;
4524 default:
4525 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4526 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4527 }
4528
4529 return;
4530}
4531
4532/* Work: Perform NIC Core Unrecoverable state handling */
4533void
4534qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4535{
4536 struct qla_hw_data *ha =
2ad1b67c 4537 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4538 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4539 uint32_t dev_state = 0;
4540
4541 qla83xx_idc_lock(base_vha, 0);
4542 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4543 qla83xx_reset_ownership(base_vha);
4544 if (ha->flags.nic_core_reset_owner) {
4545 ha->flags.nic_core_reset_owner = 0;
4546 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4547 QLA8XXX_DEV_FAILED);
4548 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4549 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4550 }
4551 qla83xx_idc_unlock(base_vha, 0);
4552}
4553
4554/* Work: Execute IDC state handler */
4555void
4556qla83xx_idc_state_handler_work(struct work_struct *work)
4557{
4558 struct qla_hw_data *ha =
2ad1b67c 4559 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4560 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4561 uint32_t dev_state = 0;
4562
4563 qla83xx_idc_lock(base_vha, 0);
4564 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4565 if (dev_state == QLA8XXX_DEV_FAILED ||
4566 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4567 qla83xx_idc_state_handler(base_vha);
4568 qla83xx_idc_unlock(base_vha, 0);
4569}
4570
fa492630 4571static int
7d613ac6
SV		 4572qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4573{
4574 int rval = QLA_SUCCESS;
4575 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4576 uint32_t heart_beat_counter1, heart_beat_counter2;
4577
4578 do {
4579 if (time_after(jiffies, heart_beat_wait)) {
4580 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4581 "Nic Core f/w is not alive.\n");
4582 rval = QLA_FUNCTION_FAILED;
4583 break;
4584 }
4585
4586 qla83xx_idc_lock(base_vha, 0);
4587 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4588 &heart_beat_counter1);
4589 qla83xx_idc_unlock(base_vha, 0);
4590 msleep(100);
4591 qla83xx_idc_lock(base_vha, 0);
4592 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4593 &heart_beat_counter2);
4594 qla83xx_idc_unlock(base_vha, 0);
4595 } while (heart_beat_counter1 == heart_beat_counter2);
4596
4597 return rval;
4598}
4599
4600/* Work: Perform NIC Core Reset handling */
4601void
4602qla83xx_nic_core_reset_work(struct work_struct *work)
4603{
4604 struct qla_hw_data *ha =
4605 container_of(work, struct qla_hw_data, nic_core_reset);
4606 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4607 uint32_t dev_state = 0;
4608
81178772
SK		 4609 if (IS_QLA2031(ha)) {
4610 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4611 ql_log(ql_log_warn, base_vha, 0xb081,
4612 "Failed to dump mctp\n");
4613 return;
4614 }
4615
7d613ac6
SV		 4616 if (!ha->flags.nic_core_reset_hdlr_active) {
4617 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4618 qla83xx_idc_lock(base_vha, 0);
4619 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4620 &dev_state);
4621 qla83xx_idc_unlock(base_vha, 0);
4622 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4623 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4624 "Nic Core f/w is alive.\n");
4625 return;
4626 }
4627 }
4628
4629 ha->flags.nic_core_reset_hdlr_active = 1;
4630 if (qla83xx_nic_core_reset(base_vha)) {
4631 /* NIC Core reset failed. */
4632 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4633 "NIC Core reset failed.\n");
4634 }
4635 ha->flags.nic_core_reset_hdlr_active = 0;
4636 }
4637}
4638
4639/* Work: Handle 8200 IDC aens */
4640void
4641qla83xx_service_idc_aen(struct work_struct *work)
4642{
4643 struct qla_hw_data *ha =
4644 container_of(work, struct qla_hw_data, idc_aen);
4645 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4646 uint32_t dev_state, idc_control;
4647
4648 qla83xx_idc_lock(base_vha, 0);
4649 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4650 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4651 qla83xx_idc_unlock(base_vha, 0);
4652 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4653 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4654 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4655 "Application requested NIC Core Reset.\n");
4656 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4657 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4658 QLA_SUCCESS) {
4659 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4660 "Other protocol driver requested NIC Core Reset.\n");
4661 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4662 }
4663 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4664 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4665 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4666 }
4667}
4668
4669static void
4670qla83xx_wait_logic(void)
4671{
4672 int i;
4673
4674 /* Yield CPU */
4675 if (!in_interrupt()) {
4676 /*
4677 * Wait about 200ms before retrying again.
4678 * This controls the number of retries for single
4679 * lock operation.
4680 */
4681 msleep(100);
4682 schedule();
4683 } else {
4684 for (i = 0; i < 20; i++)
4685 cpu_relax(); /* This a nop instr on i386 */
4686 }
4687}
4688
fa492630 4689static int
7d613ac6
SV		 4690qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4691{
4692 int rval;
4693 uint32_t data;
4694 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4695 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4696 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4697 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4698 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4699
4700 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4701 if (rval)
4702 return rval;
4703
4704 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4705 return QLA_SUCCESS;
4706 } else {
4707 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4708 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4709 data);
4710 if (rval)
4711 return rval;
4712
4713 msleep(200);
4714
4715 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4716 &data);
4717 if (rval)
4718 return rval;
4719
4720 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4721 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4722 ~(idc_lck_rcvry_stage_mask));
4723 rval = qla83xx_wr_reg(base_vha,
4724 QLA83XX_IDC_LOCK_RECOVERY, data);
4725 if (rval)
4726 return rval;
4727
4728 /* Forcefully perform IDC UnLock */
4729 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4730 &data);
4731 if (rval)
4732 return rval;
4733 /* Clear lock-id by setting 0xff */
4734 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4735 0xff);
4736 if (rval)
4737 return rval;
4738 /* Clear lock-recovery by setting 0x0 */
4739 rval = qla83xx_wr_reg(base_vha,
4740 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4741 if (rval)
4742 return rval;
4743 } else
4744 return QLA_SUCCESS;
4745 }
4746
4747 return rval;
4748}
4749
fa492630 4750static int
7d613ac6
SV		 4751qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4752{
4753 int rval = QLA_SUCCESS;
4754 uint32_t o_drv_lockid, n_drv_lockid;
4755 unsigned long lock_recovery_timeout;
4756
4757 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4758retry_lockid:
4759 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4760 if (rval)
4761 goto exit;
4762
4763 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4764 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4765 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4766 return QLA_SUCCESS;
4767 else
4768 return QLA_FUNCTION_FAILED;
4769 }
4770
4771 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4772 if (rval)
4773 goto exit;
4774
4775 if (o_drv_lockid == n_drv_lockid) {
4776 qla83xx_wait_logic();
4777 goto retry_lockid;
4778 } else
4779 return QLA_SUCCESS;
4780
4781exit:
4782 return rval;
4783}
4784
4785void
4786qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4787{
4788 uint16_t options = (requester_id << 15) | BIT_6;
4789 uint32_t data;
6c315553 4790 uint32_t lock_owner;
7d613ac6
SV		 4791 struct qla_hw_data *ha = base_vha->hw;
4792
4793 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4794retry_lock:
4795 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4796 == QLA_SUCCESS) {
4797 if (data) {
4798 /* Setting lock-id to our function-number */
4799 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4800 ha->portnum);
4801 } else {
6c315553
SK		 4802 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4803 &lock_owner);
7d613ac6 4804 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4805 "Failed to acquire IDC lock, acquired by %d, "
4806 "retrying...\n", lock_owner);
7d613ac6
SV		 4807
4808 /* Retry/Perform IDC-Lock recovery */
4809 if (qla83xx_idc_lock_recovery(base_vha)
4810 == QLA_SUCCESS) {
4811 qla83xx_wait_logic();
4812 goto retry_lock;
4813 } else
4814 ql_log(ql_log_warn, base_vha, 0xb075,
4815 "IDC Lock recovery FAILED.\n");
4816 }
4817
4818 }
4819
4820 return;
4821
4822 /* XXX: IDC-lock implementation using access-control mbx */
4823retry_lock2:
4824 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4825 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4826 "Failed to acquire IDC lock. retrying...\n");
4827 /* Retry/Perform IDC-Lock recovery */
4828 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4829 qla83xx_wait_logic();
4830 goto retry_lock2;
4831 } else
4832 ql_log(ql_log_warn, base_vha, 0xb076,
4833 "IDC Lock recovery FAILED.\n");
4834 }
4835
4836 return;
4837}
4838
4839void
4840qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4841{
5897cb2f
BVA		 4842#if 0
4843 uint16_t options = (requester_id << 15) | BIT_7;
4844#endif
4845 uint16_t retry;
7d613ac6
SV		 4846 uint32_t data;
4847 struct qla_hw_data *ha = base_vha->hw;
4848
4849 /* IDC-unlock implementation using driver-unlock/lock-id
4850 * remote registers
4851 */
4852 retry = 0;
4853retry_unlock:
4854 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4855 == QLA_SUCCESS) {
4856 if (data == ha->portnum) {
4857 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4858 /* Clearing lock-id by setting 0xff */
4859 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4860 } else if (retry < 10) {
4861 /* SV: XXX: IDC unlock retrying needed here? */
4862
4863 /* Retry for IDC-unlock */
4864 qla83xx_wait_logic();
4865 retry++;
4866 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 4867 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4868 goto retry_unlock;
4869 }
4870 } else if (retry < 10) {
4871 /* Retry for IDC-unlock */
4872 qla83xx_wait_logic();
4873 retry++;
4874 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 4875 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 4876 goto retry_unlock;
4877 }
4878
4879 return;
4880
5897cb2f 4881#if 0
7d613ac6
SV		 4882 /* XXX: IDC-unlock implementation using access-control mbx */
4883 retry = 0;
4884retry_unlock2:
4885 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4886 if (retry < 10) {
4887 /* Retry for IDC-unlock */
4888 qla83xx_wait_logic();
4889 retry++;
4890 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 4891 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4892 goto retry_unlock2;
4893 }
4894 }
4895
4896 return;
5897cb2f 4897#endif
7d613ac6
SV		 4898}
4899
4900int
4901__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4902{
4903 int rval = QLA_SUCCESS;
4904 struct qla_hw_data *ha = vha->hw;
4905 uint32_t drv_presence;
4906
4907 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4908 if (rval == QLA_SUCCESS) {
4909 drv_presence |= (1 << ha->portnum);
4910 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4911 drv_presence);
4912 }
4913
4914 return rval;
4915}
4916
4917int
4918qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4919{
4920 int rval = QLA_SUCCESS;
4921
4922 qla83xx_idc_lock(vha, 0);
4923 rval = __qla83xx_set_drv_presence(vha);
4924 qla83xx_idc_unlock(vha, 0);
4925
4926 return rval;
4927}
4928
4929int
4930__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4931{
4932 int rval = QLA_SUCCESS;
4933 struct qla_hw_data *ha = vha->hw;
4934 uint32_t drv_presence;
4935
4936 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4937 if (rval == QLA_SUCCESS) {
4938 drv_presence &= ~(1 << ha->portnum);
4939 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4940 drv_presence);
4941 }
4942
4943 return rval;
4944}
4945
4946int
4947qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4948{
4949 int rval = QLA_SUCCESS;
4950
4951 qla83xx_idc_lock(vha, 0);
4952 rval = __qla83xx_clear_drv_presence(vha);
4953 qla83xx_idc_unlock(vha, 0);
4954
4955 return rval;
4956}
4957
fa492630 4958static void
7d613ac6
SV		 4959qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4960{
4961 struct qla_hw_data *ha = vha->hw;
4962 uint32_t drv_ack, drv_presence;
4963 unsigned long ack_timeout;
4964
4965 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4966 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4967 while (1) {
4968 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4969 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4970 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4971 break;
4972
4973 if (time_after_eq(jiffies, ack_timeout)) {
4974 ql_log(ql_log_warn, vha, 0xb067,
4975 "RESET ACK TIMEOUT! drv_presence=0x%x "
4976 "drv_ack=0x%x\n", drv_presence, drv_ack);
4977 /*
4978 * The function(s) which did not ack in time are forced
4979 * to withdraw any further participation in the IDC
4980 * reset.
4981 */
4982 if (drv_ack != drv_presence)
4983 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4984 drv_ack);
4985 break;
4986 }
4987
4988 qla83xx_idc_unlock(vha, 0);
4989 msleep(1000);
4990 qla83xx_idc_lock(vha, 0);
4991 }
4992
4993 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4994 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4995}
4996
fa492630 4997static int
7d613ac6
SV		 4998qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4999{
5000 int rval = QLA_SUCCESS;
5001 uint32_t idc_control;
5002
5003 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5004 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5005
5006 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5007 __qla83xx_get_idc_control(vha, &idc_control);
5008 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5009 __qla83xx_set_idc_control(vha, 0);
5010
5011 qla83xx_idc_unlock(vha, 0);
5012 rval = qla83xx_restart_nic_firmware(vha);
5013 qla83xx_idc_lock(vha, 0);
5014
5015 if (rval != QLA_SUCCESS) {
5016 ql_log(ql_log_fatal, vha, 0xb06a,
5017 "Failed to restart NIC f/w.\n");
5018 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5019 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5020 } else {
5021 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5022 "Success in restarting nic f/w.\n");
5023 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5024 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5025 }
5026
5027 return rval;
5028}
5029
5030/* Assumes idc_lock always held on entry */
5031int
5032qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5033{
5034 struct qla_hw_data *ha = base_vha->hw;
5035 int rval = QLA_SUCCESS;
5036 unsigned long dev_init_timeout;
5037 uint32_t dev_state;
5038
5039 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5040 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5041
5042 while (1) {
5043
5044 if (time_after_eq(jiffies, dev_init_timeout)) {
5045 ql_log(ql_log_warn, base_vha, 0xb06e,
5046 "Initialization TIMEOUT!\n");
5047 /* Init timeout. Disable further NIC Core
5048 * communication.
5049 */
5050 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5051 QLA8XXX_DEV_FAILED);
5052 ql_log(ql_log_info, base_vha, 0xb06f,
5053 "HW State: FAILED.\n");
5054 }
5055
5056 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5057 switch (dev_state) {
5058 case QLA8XXX_DEV_READY:
5059 if (ha->flags.nic_core_reset_owner)
5060 qla83xx_idc_audit(base_vha,
5061 IDC_AUDIT_COMPLETION);
5062 ha->flags.nic_core_reset_owner = 0;
5063 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5064 "Reset_owner reset by 0x%x.\n",
5065 ha->portnum);
5066 goto exit;
5067 case QLA8XXX_DEV_COLD:
5068 if (ha->flags.nic_core_reset_owner)
5069 rval = qla83xx_device_bootstrap(base_vha);
5070 else {
5071 /* Wait for AEN to change device-state */
5072 qla83xx_idc_unlock(base_vha, 0);
5073 msleep(1000);
5074 qla83xx_idc_lock(base_vha, 0);
5075 }
5076 break;
5077 case QLA8XXX_DEV_INITIALIZING:
5078 /* Wait for AEN to change device-state */
5079 qla83xx_idc_unlock(base_vha, 0);
5080 msleep(1000);
5081 qla83xx_idc_lock(base_vha, 0);
5082 break;
5083 case QLA8XXX_DEV_NEED_RESET:
5084 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5085 qla83xx_need_reset_handler(base_vha);
5086 else {
5087 /* Wait for AEN to change device-state */
5088 qla83xx_idc_unlock(base_vha, 0);
5089 msleep(1000);
5090 qla83xx_idc_lock(base_vha, 0);
5091 }
5092 /* reset timeout value after need reset handler */
5093 dev_init_timeout = jiffies +
5094 (ha->fcoe_dev_init_timeout * HZ);
5095 break;
5096 case QLA8XXX_DEV_NEED_QUIESCENT:
5097 /* XXX: DEBUG for now */
5098 qla83xx_idc_unlock(base_vha, 0);
5099 msleep(1000);
5100 qla83xx_idc_lock(base_vha, 0);
5101 break;
5102 case QLA8XXX_DEV_QUIESCENT:
5103 /* XXX: DEBUG for now */
5104 if (ha->flags.quiesce_owner)
5105 goto exit;
5106
5107 qla83xx_idc_unlock(base_vha, 0);
5108 msleep(1000);
5109 qla83xx_idc_lock(base_vha, 0);
5110 dev_init_timeout = jiffies +
5111 (ha->fcoe_dev_init_timeout * HZ);
5112 break;
5113 case QLA8XXX_DEV_FAILED:
5114 if (ha->flags.nic_core_reset_owner)
5115 qla83xx_idc_audit(base_vha,
5116 IDC_AUDIT_COMPLETION);
5117 ha->flags.nic_core_reset_owner = 0;
5118 __qla83xx_clear_drv_presence(base_vha);
5119 qla83xx_idc_unlock(base_vha, 0);
5120 qla8xxx_dev_failed_handler(base_vha);
5121 rval = QLA_FUNCTION_FAILED;
5122 qla83xx_idc_lock(base_vha, 0);
5123 goto exit;
5124 case QLA8XXX_BAD_VALUE:
5125 qla83xx_idc_unlock(base_vha, 0);
5126 msleep(1000);
5127 qla83xx_idc_lock(base_vha, 0);
5128 break;
5129 default:
5130 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5131 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5132 qla83xx_idc_unlock(base_vha, 0);
5133 qla8xxx_dev_failed_handler(base_vha);
5134 rval = QLA_FUNCTION_FAILED;
5135 qla83xx_idc_lock(base_vha, 0);
5136 goto exit;
5137 }
5138 }
5139
5140exit:
5141 return rval;
5142}
5143
f3ddac19
CD		 5144void
5145qla2x00_disable_board_on_pci_error(struct work_struct *work)
5146{
5147 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5148 board_disable);
5149 struct pci_dev *pdev = ha->pdev;
5150 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5151
783e0dc4
SC		 5152 /* if UNLOAD flag is already set, then continue unload,
5153 * where it was set first.
5154 */
5155 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5156 return;
5157
f3ddac19
CD		 5158 ql_log(ql_log_warn, base_vha, 0x015b,
5159 "Disabling adapter.\n");
5160
5161 set_bit(UNLOADING, &base_vha->dpc_flags);
5162
5163 qla2x00_delete_all_vps(ha, base_vha);
5164
5165 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5166
5167 qla2x00_dfs_remove(base_vha);
5168
5169 qla84xx_put_chip(base_vha);
5170
5171 if (base_vha->timer_active)
5172 qla2x00_stop_timer(base_vha);
5173
5174 base_vha->flags.online = 0;
5175
5176 qla2x00_destroy_deferred_work(ha);
5177
5178 /*
5179 * Do not try to stop beacon blink as it will issue a mailbox
5180 * command.
5181 */
5182 qla2x00_free_sysfs_attr(base_vha, false);
5183
5184 fc_remove_host(base_vha->host);
5185
5186 scsi_remove_host(base_vha->host);
5187
5188 base_vha->flags.init_done = 0;
5189 qla25xx_delete_queues(base_vha);
5190 qla2x00_free_irqs(base_vha);
5191 qla2x00_free_fcports(base_vha);
5192 qla2x00_mem_free(ha);
5193 qla82xx_md_free(base_vha);
5194 qla2x00_free_queues(ha);
5195
f3ddac19
CD		 5196 qla2x00_unmap_iobases(ha);
5197
5198 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5199 pci_disable_pcie_error_reporting(pdev);
5200 pci_disable_device(pdev);
f3ddac19 5201
beb9e315
JL		 5202 /*
5203 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5204 */
f3ddac19
CD		 5205}
5206
1da177e4
LT		 5207/**************************************************************************
5208* qla2x00_do_dpc
5209* This kernel thread is a task that is schedule by the interrupt handler
5210* to perform the background processing for interrupts.
5211*
5212* Notes:
5213* This task always run in the context of a kernel thread. It
5214* is kick-off by the driver's detect code and starts up
5215* up one per adapter. It immediately goes to sleep and waits for
5216* some fibre event. When either the interrupt handler or
5217* the timer routine detects a event it will one of the task
5218* bits then wake us up.
5219**************************************************************************/
5220static int
5221qla2x00_do_dpc(void *data)
5222{
e315cd28
AC		 5223 scsi_qla_host_t *base_vha;
5224 struct qla_hw_data *ha;
d7459527
MH		 5225 uint32_t online;
5226 struct qla_qpair *qpair;
1da177e4 5227
e315cd28
AC		 5228 ha = (struct qla_hw_data *)data;
5229 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5230
8698a745 5231 set_user_nice(current, MIN_NICE);
1da177e4 5232
563585ec 5233 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5234 while (!kthread_should_stop()) {
7c3df132
SK		 5235 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5236 "DPC handler sleeping.\n");
1da177e4 5237
39a11240 5238 schedule();
1da177e4 5239
c142caf0
AV		 5240 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5241 goto end_loop;
1da177e4 5242
85880801 5243 if (ha->flags.eeh_busy) {
7c3df132
SK		 5244 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5245 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5246 goto end_loop;
85880801
AV		 5247 }
5248
1da177e4
LT		 5249 ha->dpc_active = 1;
5250
5f28d2d7
SK		 5251 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5252 "DPC handler waking up, dpc_flags=0x%lx.\n",
5253 base_vha->dpc_flags);
1da177e4 5254
a29b3dd7
JC		 5255 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5256 break;
5257
e315cd28 5258 qla2x00_do_work(base_vha);
0971de7f 5259
7ec0effd
AD		 5260 if (IS_P3P_TYPE(ha)) {
5261 if (IS_QLA8044(ha)) {
5262 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5263 &base_vha->dpc_flags)) {
5264 qla8044_idc_lock(ha);
5265 qla8044_wr_direct(base_vha,
5266 QLA8044_CRB_DEV_STATE_INDEX,
5267 QLA8XXX_DEV_FAILED);
5268 qla8044_idc_unlock(ha);
5269 ql_log(ql_log_info, base_vha, 0x4004,
5270 "HW State: FAILED.\n");
5271 qla8044_device_state_handler(base_vha);
5272 continue;
5273 }
5274
5275 } else {
5276 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5277 &base_vha->dpc_flags)) {
5278 qla82xx_idc_lock(ha);
5279 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5280 QLA8XXX_DEV_FAILED);
5281 qla82xx_idc_unlock(ha);
5282 ql_log(ql_log_info, base_vha, 0x0151,
5283 "HW State: FAILED.\n");
5284 qla82xx_device_state_handler(base_vha);
5285 continue;
5286 }
a9083016
GM		 5287 }
5288
5289 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5290 &base_vha->dpc_flags)) {
5291
7c3df132
SK		 5292 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5293 "FCoE context reset scheduled.\n");
a9083016
GM		 5294 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5295 &base_vha->dpc_flags))) {
5296 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5297 /* FCoE-ctx reset failed.
5298 * Escalate to chip-reset
5299 */
5300 set_bit(ISP_ABORT_NEEDED,
5301 &base_vha->dpc_flags);
5302 }
5303 clear_bit(ABORT_ISP_ACTIVE,
5304 &base_vha->dpc_flags);
5305 }
5306
7c3df132
SK		 5307 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5308 "FCoE context reset end.\n");
a9083016 5309 }
8ae6d9c7
GM		 5310 } else if (IS_QLAFX00(ha)) {
5311 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5312 &base_vha->dpc_flags)) {
5313 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5314 "Firmware Reset Recovery\n");
5315 if (qlafx00_reset_initialize(base_vha)) {
5316 /* Failed. Abort isp later. */
5317 if (!test_bit(UNLOADING,
f92f82d6 5318 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5319 set_bit(ISP_UNRECOVERABLE,
5320 &base_vha->dpc_flags);
5321 ql_dbg(ql_dbg_dpc, base_vha,
5322 0x4021,
5323 "Reset Recovery Failed\n");
f92f82d6 5324 }
8ae6d9c7
GM		 5325 }
5326 }
5327
5328 if (test_and_clear_bit(FX00_TARGET_SCAN,
5329 &base_vha->dpc_flags)) {
5330 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5331 "ISPFx00 Target Scan scheduled\n");
5332 if (qlafx00_rescan_isp(base_vha)) {
5333 if (!test_bit(UNLOADING,
5334 &base_vha->dpc_flags))
5335 set_bit(ISP_UNRECOVERABLE,
5336 &base_vha->dpc_flags);
5337 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5338 "ISPFx00 Target Scan Failed\n");
5339 }
5340 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5341 "ISPFx00 Target Scan End\n");
5342 }
e8f5e95d
AB		 5343 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5344 &base_vha->dpc_flags)) {
5345 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5346 "ISPFx00 Host Info resend scheduled\n");
5347 qlafx00_fx_disc(base_vha,
5348 &base_vha->hw->mr.fcport,
5349 FXDISC_REG_HOST_INFO);
5350 }
a9083016
GM		 5351 }
5352
e315cd28
AC		 5353 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5354 &base_vha->dpc_flags)) {
1da177e4 5355
7c3df132
SK		 5356 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5357 "ISP abort scheduled.\n");
1da177e4 5358 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5359 &base_vha->dpc_flags))) {
1da177e4 5360
a9083016 5361 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5362 /* failed. retry later */
5363 set_bit(ISP_ABORT_NEEDED,
e315cd28 5364 &base_vha->dpc_flags);
99363ef8 5365 }
e315cd28
AC		 5366 clear_bit(ABORT_ISP_ACTIVE,
5367 &base_vha->dpc_flags);
99363ef8
SJ		 5368 }
5369
7c3df132
SK		 5370 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5371 "ISP abort end.\n");
1da177e4
LT		 5372 }
5373
a394aac8
DJ		 5374 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5375 &base_vha->dpc_flags)) {
e315cd28 5376 qla2x00_update_fcports(base_vha);
c9c5ced9 5377 }
d97994dc 5378
2d70c103
NB		 5379 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5380 int ret;
5381 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5382 if (ret != QLA_SUCCESS)
5383 ql_log(ql_log_warn, base_vha, 0x121,
5384 "Failed to enable receiving of RSCN "
5385 "requests: 0x%x.\n", ret);
5386 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5387 }
5388
8ae6d9c7
GM		 5389 if (IS_QLAFX00(ha))
5390 goto loop_resync_check;
5391
579d12b5 5392 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5393 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5394 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5395 if (IS_P3P_TYPE(ha)) {
5396 if (IS_QLA82XX(ha))
5397 qla82xx_device_state_handler(base_vha);
5398 if (IS_QLA8044(ha))
5399 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5400 clear_bit(ISP_QUIESCE_NEEDED,
5401 &base_vha->dpc_flags);
5402 if (!ha->flags.quiesce_owner) {
5403 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5404 if (IS_QLA82XX(ha)) {
5405 qla82xx_idc_lock(ha);
5406 qla82xx_clear_qsnt_ready(
5407 base_vha);
5408 qla82xx_idc_unlock(ha);
5409 } else if (IS_QLA8044(ha)) {
5410 qla8044_idc_lock(ha);
5411 qla8044_clear_qsnt_ready(
5412 base_vha);
5413 qla8044_idc_unlock(ha);
5414 }
8fcd6b8b
CD		 5415 }
5416 } else {
5417 clear_bit(ISP_QUIESCE_NEEDED,
5418 &base_vha->dpc_flags);
5419 qla2x00_quiesce_io(base_vha);
579d12b5 5420 }
7c3df132
SK		 5421 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5422 "Quiescence mode end.\n");
579d12b5
SK		 5423 }
5424
e315cd28 5425 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5426 &base_vha->dpc_flags) &&
e315cd28 5427 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5428
7c3df132
SK		 5429 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5430 "Reset marker scheduled.\n");
e315cd28
AC		 5431 qla2x00_rst_aen(base_vha);
5432 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5433 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5434 "Reset marker end.\n");
1da177e4
LT		 5435 }
5436
5437 /* Retry each device up to login retry count */
e315cd28
AC		 5438 if ((test_and_clear_bit(RELOGIN_NEEDED,
5439 &base_vha->dpc_flags)) &&
5440 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5441 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5442
7c3df132
SK		 5443 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5444 "Relogin scheduled.\n");
e315cd28 5445 qla2x00_relogin(base_vha);
7c3df132
SK		 5446 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5447 "Relogin end.\n");
1da177e4 5448 }
8ae6d9c7 5449loop_resync_check:
e315cd28 5450 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5451 &base_vha->dpc_flags)) {
1da177e4 5452
7c3df132
SK		 5453 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5454 "Loop resync scheduled.\n");
1da177e4
LT		 5455
5456 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5457 &base_vha->dpc_flags))) {
1da177e4 5458
52c82823 5459 qla2x00_loop_resync(base_vha);
1da177e4 5460
e315cd28
AC		 5461 clear_bit(LOOP_RESYNC_ACTIVE,
5462 &base_vha->dpc_flags);
1da177e4
LT		 5463 }
5464
7c3df132
SK		 5465 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5466 "Loop resync end.\n");
1da177e4
LT		 5467 }
5468
8ae6d9c7
GM		 5469 if (IS_QLAFX00(ha))
5470 goto intr_on_check;
5471
e315cd28
AC		 5472 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5473 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5474 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5475 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5476 }
5477
8ae6d9c7 5478intr_on_check:
1da177e4 5479 if (!ha->interrupts_on)
fd34f556 5480 ha->isp_ops->enable_intrs(ha);
1da177e4 5481
e315cd28 5482 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5483 &base_vha->dpc_flags)) {
5484 if (ha->beacon_blink_led == 1)
5485 ha->isp_ops->beacon_blink(base_vha);
5486 }
f6df144c 5487
d7459527
MH		 5488 /* qpair online check */
5489 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5490 &base_vha->dpc_flags)) {
5491 if (ha->flags.eeh_busy ||
5492 ha->flags.pci_channel_io_perm_failure)
5493 online = 0;
5494 else
5495 online = 1;
5496
5497 mutex_lock(&ha->mq_lock);
5498 list_for_each_entry(qpair, &base_vha->qp_list,
5499 qp_list_elem)
5500 qpair->online = online;
5501 mutex_unlock(&ha->mq_lock);
5502 }
5503
8ae6d9c7
GM		 5504 if (!IS_QLAFX00(ha))
5505 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5506
1da177e4 5507 ha->dpc_active = 0;
c142caf0 5508end_loop:
563585ec 5509 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5510 } /* End of while(1) */
563585ec 5511 __set_current_state(TASK_RUNNING);
1da177e4 5512
7c3df132
SK		 5513 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5514 "DPC handler exiting.\n");
1da177e4
LT		 5515
5516 /*
5517 * Make sure that nobody tries to wake us up again.
5518 */
1da177e4
LT		 5519 ha->dpc_active = 0;
5520
ac280b67
AV		 5521 /* Cleanup any residual CTX SRBs. */
5522 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5523
39a11240
CH		 5524 return 0;
5525}
5526
5527void
e315cd28 5528qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5529{
e315cd28 5530 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5531 struct task_struct *t = ha->dpc_thread;
5532
e315cd28 5533 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5534 wake_up_process(t);
1da177e4
LT		 5535}
5536
1da177e4
LT		 5537/*
5538* qla2x00_rst_aen
5539* Processes asynchronous reset.
5540*
5541* Input:
5542* ha = adapter block pointer.
5543*/
5544static void
e315cd28 5545qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5546{
e315cd28
AC		 5547 if (vha->flags.online && !vha->flags.reset_active &&
5548 !atomic_read(&vha->loop_down_timer) &&
5549 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5550 do {
e315cd28 5551 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5552
5553 /*
5554 * Issue marker command only when we are going to start
5555 * the I/O.
5556 */
e315cd28
AC		 5557 vha->marker_needed = 1;
5558 } while (!atomic_read(&vha->loop_down_timer) &&
5559 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5560 }
5561}
5562
1da177e4
LT		 5563/**************************************************************************
5564* qla2x00_timer
5565*
5566* Description:
5567* One second timer
5568*
5569* Context: Interrupt
5570***************************************************************************/
2c3dfe3f 5571void
e315cd28 5572qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5573{
1da177e4 5574 unsigned long cpu_flags = 0;
1da177e4
LT		 5575 int start_dpc = 0;
5576 int index;
5577 srb_t *sp;
85880801 5578 uint16_t w;
e315cd28 5579 struct qla_hw_data *ha = vha->hw;
73208dfd 5580 struct req_que *req;
85880801 5581
a5b36321 5582 if (ha->flags.eeh_busy) {
7c3df132
SK		 5583 ql_dbg(ql_dbg_timer, vha, 0x6000,
5584 "EEH = %d, restarting timer.\n",
5585 ha->flags.eeh_busy);
a5b36321
LC		 5586 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5587 return;
5588 }
5589
f3ddac19
CD		 5590 /*
5591 * Hardware read to raise pending EEH errors during mailbox waits. If
5592 * the read returns -1 then disable the board.
5593 */
5594 if (!pci_channel_offline(ha->pdev)) {
85880801 5595 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5596 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5597 }
1da177e4 5598
cefcaba6 5599 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5600 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5601 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5602 start_dpc++;
7ec0effd
AD		 5603 if (IS_QLA82XX(ha))
5604 qla82xx_watchdog(vha);
5605 else if (IS_QLA8044(ha))
5606 qla8044_watchdog(vha);
579d12b5
SK		 5607 }
5608
8ae6d9c7
GM		 5609 if (!vha->vp_idx && IS_QLAFX00(ha))
5610 qlafx00_timer_routine(vha);
5611
1da177e4 5612 /* Loop down handler. */
e315cd28 5613 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5614 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5615 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5616 && vha->flags.online) {
1da177e4 5617
e315cd28
AC		 5618 if (atomic_read(&vha->loop_down_timer) ==
5619 vha->loop_down_abort_time) {
1da177e4 5620
7c3df132
SK		 5621 ql_log(ql_log_info, vha, 0x6008,
5622 "Loop down - aborting the queues before time expires.\n");
1da177e4 5623
e315cd28
AC		 5624 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5625 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5626
f08b7251
AV		 5627 /*
5628 * Schedule an ISP abort to return any FCP2-device
5629 * commands.
5630 */
2c3dfe3f 5631 /* NPIV - scan physical port only */
e315cd28 5632 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5633 spin_lock_irqsave(&ha->hardware_lock,
5634 cpu_flags);
73208dfd 5635 req = ha->req_q_map[0];
2c3dfe3f 5636 for (index = 1;
8d93f550 5637 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5638 index++) {
5639 fc_port_t *sfcp;
5640
e315cd28 5641 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5642 if (!sp)
5643 continue;
9ba56b95 5644 if (sp->type != SRB_SCSI_CMD)
cf53b069 5645 continue;
2c3dfe3f 5646 sfcp = sp->fcport;
f08b7251 5647 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5648 continue;
bdf79621 5649
8f7daead
GM		 5650 if (IS_QLA82XX(ha))
5651 set_bit(FCOE_CTX_RESET_NEEDED,
5652 &vha->dpc_flags);
5653 else
5654 set_bit(ISP_ABORT_NEEDED,
e315cd28 5655 &vha->dpc_flags);
2c3dfe3f
SJ		 5656 break;
5657 }
5658 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5659 cpu_flags);
1da177e4 5660 }
1da177e4
LT		 5661 start_dpc++;
5662 }
5663
5664 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5665 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5666 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5667 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5668 "Loop down - aborting ISP.\n");
5669
8f7daead
GM		 5670 if (IS_QLA82XX(ha))
5671 set_bit(FCOE_CTX_RESET_NEEDED,
5672 &vha->dpc_flags);
5673 else
5674 set_bit(ISP_ABORT_NEEDED,
5675 &vha->dpc_flags);
1da177e4
LT		 5676 }
5677 }
7c3df132
SK		 5678 ql_dbg(ql_dbg_timer, vha, 0x600a,
5679 "Loop down - seconds remaining %d.\n",
5680 atomic_read(&vha->loop_down_timer));
1da177e4 5681 }
cefcaba6
SK		 5682 /* Check if beacon LED needs to be blinked for physical host only */
5683 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5684 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5685 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5686 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5687 start_dpc++;
5688 }
f6df144c
AV		 5689 }
5690
550bf57d 5691 /* Process any deferred work. */
e315cd28 5692 if (!list_empty(&vha->work_list))
550bf57d
AV		 5693 start_dpc++;
5694
1da177e4 5695 /* Schedule the DPC routine if needed */
e315cd28
AC		 5696 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5697 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5698 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5699 start_dpc ||
e315cd28
AC		 5700 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5701 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5702 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5703 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5704 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5705 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5706 ql_dbg(ql_dbg_timer, vha, 0x600b,
5707 "isp_abort_needed=%d loop_resync_needed=%d "
5708 "fcport_update_needed=%d start_dpc=%d "
5709 "reset_marker_needed=%d",
5710 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5711 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5712 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5713 start_dpc,
5714 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5715 ql_dbg(ql_dbg_timer, vha, 0x600c,
5716 "beacon_blink_needed=%d isp_unrecoverable=%d "
5717 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5718 "relogin_needed=%d.\n",
7c3df132
SK		 5719 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5720 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5721 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5722 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5723 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5724 qla2xxx_wake_dpc(vha);
7c3df132 5725 }
1da177e4 5726
e315cd28 5727 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5728}
5729
5433383e
AV		 5730/* Firmware interface routines. */
5731
f73cb695 5732#define FW_BLOBS 11
5433383e
AV		 5733#define FW_ISP21XX 0
5734#define FW_ISP22XX 1
5735#define FW_ISP2300 2
5736#define FW_ISP2322 3
48c02fde 5737#define FW_ISP24XX 4
c3a2f0df 5738#define FW_ISP25XX 5
3a03eb79 5739#define FW_ISP81XX 6
a9083016 5740#define FW_ISP82XX 7
6246b8a1
GM		 5741#define FW_ISP2031 8
5742#define FW_ISP8031 9
2c5bbbb2 5743#define FW_ISP27XX 10
5433383e 5744
bb8ee499
AV		 5745#define FW_FILE_ISP21XX "ql2100_fw.bin"
5746#define FW_FILE_ISP22XX "ql2200_fw.bin"
5747#define FW_FILE_ISP2300 "ql2300_fw.bin"
5748#define FW_FILE_ISP2322 "ql2322_fw.bin"
5749#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5750#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5751#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5752#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5753#define FW_FILE_ISP2031 "ql2600_fw.bin"
5754#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5755#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5756
bb8ee499 5757
e1e82b6f 5758static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5759
5760static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5761 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5762 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5763 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5764 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5765 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5766 { .name = FW_FILE_ISP25XX, },
3a03eb79 5767 { .name = FW_FILE_ISP81XX, },
a9083016 5768 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5769 { .name = FW_FILE_ISP2031, },
5770 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5771 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5772};
5773
5774struct fw_blob *
e315cd28 5775qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5776{
e315cd28 5777 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5778 struct fw_blob *blob;
5779
5433383e
AV		 5780 if (IS_QLA2100(ha)) {
5781 blob = &qla_fw_blobs[FW_ISP21XX];
5782 } else if (IS_QLA2200(ha)) {
5783 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5784 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5785 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5786 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5787 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5788 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5789 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5790 } else if (IS_QLA25XX(ha)) {
5791 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5792 } else if (IS_QLA81XX(ha)) {
5793 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5794 } else if (IS_QLA82XX(ha)) {
5795 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5796 } else if (IS_QLA2031(ha)) {
5797 blob = &qla_fw_blobs[FW_ISP2031];
5798 } else if (IS_QLA8031(ha)) {
5799 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5800 } else if (IS_QLA27XX(ha)) {
5801 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5802 } else {
5803 return NULL;
5433383e
AV		 5804 }
5805
e1e82b6f 5806 mutex_lock(&qla_fw_lock);
5433383e
AV		 5807 if (blob->fw)
5808 goto out;
5809
5810 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5811 ql_log(ql_log_warn, vha, 0x0063,
5812 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5813 blob->fw = NULL;
5814 blob = NULL;
5815 goto out;
5816 }
5817
5818out:
e1e82b6f 5819 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5820 return blob;
5821}
5822
5823static void
5824qla2x00_release_firmware(void)
5825{
5826 int idx;
5827
e1e82b6f 5828 mutex_lock(&qla_fw_lock);
5433383e 5829 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5830 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5831 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5832}
5833
14e660e6
SJ		 5834static pci_ers_result_t
5835qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5836{
85880801
AV		 5837 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5838 struct qla_hw_data *ha = vha->hw;
5839
7c3df132
SK		 5840 ql_dbg(ql_dbg_aer, vha, 0x9000,
5841 "PCI error detected, state %x.\n", state);
b9b12f73 5842
14e660e6
SJ		 5843 switch (state) {
5844 case pci_channel_io_normal:
85880801 5845 ha->flags.eeh_busy = 0;
d7459527
MH		 5846 if (ql2xmqsupport) {
5847 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5848 qla2xxx_wake_dpc(vha);
5849 }
14e660e6
SJ		 5850 return PCI_ERS_RESULT_CAN_RECOVER;
5851 case pci_channel_io_frozen:
85880801 5852 ha->flags.eeh_busy = 1;
a5b36321
LC		 5853 /* For ISP82XX complete any pending mailbox cmd */
5854 if (IS_QLA82XX(ha)) {
7190575f 5855 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5856 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5857 qla82xx_clear_pending_mbx(vha);
a5b36321 5858 }
90a86fc0 5859 qla2x00_free_irqs(vha);
14e660e6 5860 pci_disable_device(pdev);
bddd2d65
LC		 5861 /* Return back all IOs */
5862 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 5863 if (ql2xmqsupport) {
5864 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5865 qla2xxx_wake_dpc(vha);
5866 }
14e660e6
SJ		 5867 return PCI_ERS_RESULT_NEED_RESET;
5868 case pci_channel_io_perm_failure:
85880801
AV		 5869 ha->flags.pci_channel_io_perm_failure = 1;
5870 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 5871 if (ql2xmqsupport) {
5872 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5873 qla2xxx_wake_dpc(vha);
5874 }
14e660e6
SJ		 5875 return PCI_ERS_RESULT_DISCONNECT;
5876 }
5877 return PCI_ERS_RESULT_NEED_RESET;
5878}
5879
5880static pci_ers_result_t
5881qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5882{
5883 int risc_paused = 0;
5884 uint32_t stat;
5885 unsigned long flags;
e315cd28
AC		 5886 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5887 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5888 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5889 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5890
bcc5b6d3
SK		 5891 if (IS_QLA82XX(ha))
5892 return PCI_ERS_RESULT_RECOVERED;
5893
14e660e6
SJ		 5894 spin_lock_irqsave(&ha->hardware_lock, flags);
5895 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5896 stat = RD_REG_DWORD(&reg->hccr);
5897 if (stat & HCCR_RISC_PAUSE)
5898 risc_paused = 1;
5899 } else if (IS_QLA23XX(ha)) {
5900 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5901 if (stat & HSR_RISC_PAUSED)
5902 risc_paused = 1;
5903 } else if (IS_FWI2_CAPABLE(ha)) {
5904 stat = RD_REG_DWORD(&reg24->host_status);
5905 if (stat & HSRX_RISC_PAUSED)
5906 risc_paused = 1;
5907 }
5908 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5909
5910 if (risc_paused) {
7c3df132
SK		 5911 ql_log(ql_log_info, base_vha, 0x9003,
5912 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5913 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5914
5915 return PCI_ERS_RESULT_NEED_RESET;
5916 } else
5917 return PCI_ERS_RESULT_RECOVERED;
5918}
5919
fa492630
SK		 5920static uint32_t
5921qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5922{
5923 uint32_t rval = QLA_FUNCTION_FAILED;
5924 uint32_t drv_active = 0;
5925 struct qla_hw_data *ha = base_vha->hw;
5926 int fn;
5927 struct pci_dev *other_pdev = NULL;
5928
7c3df132
SK		 5929 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5930 "Entered %s.\n", __func__);
a5b36321
LC		 5931
5932 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5933
5934 if (base_vha->flags.online) {
5935 /* Abort all outstanding commands,
5936 * so as to be requeued later */
5937 qla2x00_abort_isp_cleanup(base_vha);
5938 }
5939
5940
5941 fn = PCI_FUNC(ha->pdev->devfn);
5942 while (fn > 0) {
5943 fn--;
7c3df132
SK		 5944 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5945 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5946 other_pdev =
5947 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5948 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5949 fn));
5950
5951 if (!other_pdev)
5952 continue;
5953 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5954 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5955 "Found PCI func available and enable at 0x%x.\n",
5956 fn);
a5b36321
LC		 5957 pci_dev_put(other_pdev);
5958 break;
5959 }
5960 pci_dev_put(other_pdev);
5961 }
5962
5963 if (!fn) {
5964 /* Reset owner */
7c3df132
SK		 5965 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5966 "This devfn is reset owner = 0x%x.\n",
5967 ha->pdev->devfn);
a5b36321
LC		 5968 qla82xx_idc_lock(ha);
5969
5970 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5971 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5972
5973 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5974 QLA82XX_IDC_VERSION);
5975
5976 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5977 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5978 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5979
5980 qla82xx_idc_unlock(ha);
5981 /* Reset if device is not already reset
5982 * drv_active would be 0 if a reset has already been done
5983 */
5984 if (drv_active)
5985 rval = qla82xx_start_firmware(base_vha);
5986 else
5987 rval = QLA_SUCCESS;
5988 qla82xx_idc_lock(ha);
5989
5990 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5991 ql_log(ql_log_info, base_vha, 0x900b,
5992 "HW State: FAILED.\n");
a5b36321
LC		 5993 qla82xx_clear_drv_active(ha);
5994 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5995 QLA8XXX_DEV_FAILED);
a5b36321 5996 } else {
7c3df132
SK		 5997 ql_log(ql_log_info, base_vha, 0x900c,
5998 "HW State: READY.\n");
a5b36321 5999 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6000 QLA8XXX_DEV_READY);
a5b36321 6001 qla82xx_idc_unlock(ha);
7190575f 6002 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6003 rval = qla82xx_restart_isp(base_vha);
6004 qla82xx_idc_lock(ha);
6005 /* Clear driver state register */
6006 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6007 qla82xx_set_drv_active(base_vha);
6008 }
6009 qla82xx_idc_unlock(ha);
6010 } else {
7c3df132
SK		 6011 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6012 "This devfn is not reset owner = 0x%x.\n",
6013 ha->pdev->devfn);
a5b36321 6014 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6015 QLA8XXX_DEV_READY)) {
7190575f 6016 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6017 rval = qla82xx_restart_isp(base_vha);
6018 qla82xx_idc_lock(ha);
6019 qla82xx_set_drv_active(base_vha);
6020 qla82xx_idc_unlock(ha);
6021 }
6022 }
6023 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6024
6025 return rval;
6026}
6027
14e660e6
SJ		 6028static pci_ers_result_t
6029qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6030{
6031 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6032 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6033 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6034 struct rsp_que *rsp;
6035 int rc, retries = 10;
09483916 6036
7c3df132
SK		 6037 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6038 "Slot Reset.\n");
85880801 6039
90a86fc0
JC		 6040 /* Workaround: qla2xxx driver which access hardware earlier
6041 * needs error state to be pci_channel_io_online.
6042 * Otherwise mailbox command timesout.
6043 */
6044 pdev->error_state = pci_channel_io_normal;
6045
6046 pci_restore_state(pdev);
6047
8c1496bd
RL		 6048 /* pci_restore_state() clears the saved_state flag of the device
6049 * save restored state which resets saved_state flag
6050 */
6051 pci_save_state(pdev);
6052
09483916
BH		 6053 if (ha->mem_only)
6054 rc = pci_enable_device_mem(pdev);
6055 else
6056 rc = pci_enable_device(pdev);
14e660e6 6057
09483916 6058 if (rc) {
7c3df132 6059 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6060 "Can't re-enable PCI device after reset.\n");
a5b36321 6061 goto exit_slot_reset;
14e660e6 6062 }
14e660e6 6063
90a86fc0
JC		 6064 rsp = ha->rsp_q_map[0];
6065 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6066 goto exit_slot_reset;
90a86fc0 6067
e315cd28 6068 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6069 goto exit_slot_reset;
6070
6071 if (IS_QLA82XX(ha)) {
6072 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6073 ret = PCI_ERS_RESULT_RECOVERED;
6074 goto exit_slot_reset;
6075 } else
6076 goto exit_slot_reset;
6077 }
14e660e6 6078
90a86fc0
JC		 6079 while (ha->flags.mbox_busy && retries--)
6080 msleep(1000);
85880801 6081
e315cd28 6082 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6083 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6084 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6085 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6086
90a86fc0 6087
a5b36321 6088exit_slot_reset:
7c3df132
SK		 6089 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6090 "slot_reset return %x.\n", ret);
85880801 6091
14e660e6
SJ		 6092 return ret;
6093}
6094
6095static void
6096qla2xxx_pci_resume(struct pci_dev *pdev)
6097{
e315cd28
AC		 6098 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6099 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6100 int ret;
6101
7c3df132
SK		 6102 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6103 "pci_resume.\n");
85880801 6104
e315cd28 6105 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6106 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6107 ql_log(ql_log_fatal, base_vha, 0x9002,
6108 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6109 }
85880801 6110
3e46f031
LC		 6111 pci_cleanup_aer_uncorrect_error_status(pdev);
6112
85880801 6113 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6114}
6115
2d5a4c34
HM		 6116static void
6117qla83xx_disable_laser(scsi_qla_host_t *vha)
6118{
6119 uint32_t reg, data, fn;
6120 struct qla_hw_data *ha = vha->hw;
6121 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6122
6123 /* pci func #/port # */
6124 ql_dbg(ql_dbg_init, vha, 0x004b,
6125 "Disabling Laser for hba: %p\n", vha);
6126
6127 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6128 (BIT_15|BIT_14|BIT_13|BIT_12));
6129
6130 fn = (fn >> 12);
6131
6132 if (fn & 1)
6133 reg = PORT_1_2031;
6134 else
6135 reg = PORT_0_2031;
6136
6137 data = LASER_OFF_2031;
6138
6139 qla83xx_wr_reg(vha, reg, data);
6140}
6141
5601236b
MH		 6142static int qla2xxx_map_queues(struct Scsi_Host *shost)
6143{
6144 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6145
6146 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6147}
6148
a55b2d21 6149static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6150 .error_detected = qla2xxx_pci_error_detected,
6151 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6152 .slot_reset = qla2xxx_pci_slot_reset,
6153 .resume = qla2xxx_pci_resume,
6154};
6155
5433383e 6156static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6157 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6158 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6159 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6160 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6161 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6162 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6163 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6164 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6165 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6166 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6167 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6168 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6169 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6170 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6171 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6172 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6173 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6174 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6175 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6176 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6177 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6178 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6179 { 0 },
6180};
6181MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6182
fca29703 6183static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6184 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6185 .driver = {
6186 .owner = THIS_MODULE,
6187 },
fca29703 6188 .id_table = qla2xxx_pci_tbl,
7ee61397 6189 .probe = qla2x00_probe_one,
4c993f76 6190 .remove = qla2x00_remove_one,
e30d1756 6191 .shutdown = qla2x00_shutdown,
14e660e6 6192 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6193};
6194
75ef9de1 6195static const struct file_operations apidev_fops = {
6a03b4cd 6196 .owner = THIS_MODULE,
6038f373 6197 .llseek = noop_llseek,
6a03b4cd
HZ		 6198};
6199
1da177e4
LT		 6200/**
6201 * qla2x00_module_init - Module initialization.
6202 **/
6203static int __init
6204qla2x00_module_init(void)
6205{
fca29703
AV		 6206 int ret = 0;
6207
1da177e4 6208 /* Allocate cache for SRBs. */
354d6b21 6209 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6210 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6211 if (srb_cachep == NULL) {
7c3df132
SK		 6212 ql_log(ql_log_fatal, NULL, 0x0001,
6213 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6214 return -ENOMEM;
6215 }
6216
2d70c103
NB		 6217 /* Initialize target kmem_cache and mem_pools */
6218 ret = qlt_init();
6219 if (ret < 0) {
6220 kmem_cache_destroy(srb_cachep);
6221 return ret;
6222 } else if (ret > 0) {
6223 /*
6224 * If initiator mode is explictly disabled by qlt_init(),
6225 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6226 * performing scsi_scan_target() during LOOP UP event.
6227 */
6228 qla2xxx_transport_functions.disable_target_scan = 1;
6229 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6230 }
6231
1da177e4
LT		 6232 /* Derive version string. */
6233 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6234 if (ql2xextended_error_logging)
0181944f
AV		 6235 strcat(qla2x00_version_str, "-debug");
6236
1c97a12a
AV		 6237 qla2xxx_transport_template =
6238 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6239 if (!qla2xxx_transport_template) {
6240 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6241 ql_log(ql_log_fatal, NULL, 0x0002,
6242 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6243 qlt_exit();
1da177e4 6244 return -ENODEV;
2c3dfe3f 6245 }
6a03b4cd
HZ		 6246
6247 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6248 if (apidev_major < 0) {
7c3df132
SK		 6249 ql_log(ql_log_fatal, NULL, 0x0003,
6250 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6251 }
6252
2c3dfe3f
SJ		 6253 qla2xxx_transport_vport_template =
6254 fc_attach_transport(&qla2xxx_transport_vport_functions);
6255 if (!qla2xxx_transport_vport_template) {
6256 kmem_cache_destroy(srb_cachep);
2d70c103 6257 qlt_exit();
2c3dfe3f 6258 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6259 ql_log(ql_log_fatal, NULL, 0x0004,
6260 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6261 return -ENODEV;
2c3dfe3f 6262 }
7c3df132
SK		 6263 ql_log(ql_log_info, NULL, 0x0005,
6264 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6265 qla2x00_version_str);
7ee61397 6266 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6267 if (ret) {
6268 kmem_cache_destroy(srb_cachep);
2d70c103 6269 qlt_exit();
fca29703 6270 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6271 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6272 ql_log(ql_log_fatal, NULL, 0x0006,
6273 "pci_register_driver failed...ret=%d Failing load!.\n",
6274 ret);
fca29703
AV		 6275 }
6276 return ret;
1da177e4
LT		 6277}
6278
6279/**
6280 * qla2x00_module_exit - Module cleanup.
6281 **/
6282static void __exit
6283qla2x00_module_exit(void)
6284{
6a03b4cd 6285 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6286 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6287 qla2x00_release_firmware();
354d6b21 6288 kmem_cache_destroy(srb_cachep);
2d70c103 6289 qlt_exit();
a9083016
GM		 6290 if (ctx_cachep)
6291 kmem_cache_destroy(ctx_cachep);
1da177e4 6292 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6293 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6294}
6295
6296module_init(qla2x00_module_init);
6297module_exit(qla2x00_module_exit);
6298
6299MODULE_AUTHOR("QLogic Corporation");
6300MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6301MODULE_LICENSE("GPL");
6302MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6303MODULE_FIRMWARE(FW_FILE_ISP21XX);
6304MODULE_FIRMWARE(FW_FILE_ISP22XX);
6305MODULE_FIRMWARE(FW_FILE_ISP2300);
6306MODULE_FIRMWARE(FW_FILE_ISP2322);
6307MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6308MODULE_FIRMWARE(FW_FILE_ISP25XX);
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