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Commit | Line | Data |
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1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
07e264b7 | 3 | * Copyright (c) 2003-2011 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/moduleparam.h> | |
10 | #include <linux/vmalloc.h> | |
1da177e4 | 11 | #include <linux/delay.h> |
39a11240 | 12 | #include <linux/kthread.h> |
e1e82b6f | 13 | #include <linux/mutex.h> |
3420d36c | 14 | #include <linux/kobject.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | |
17 | #include <scsi/scsi_tcq.h> | |
18 | #include <scsi/scsicam.h> | |
19 | #include <scsi/scsi_transport.h> | |
20 | #include <scsi/scsi_transport_fc.h> | |
21 | ||
22 | /* | |
23 | * Driver version | |
24 | */ | |
25 | char qla2x00_version_str[40]; | |
26 | ||
6a03b4cd HZ |
27 | static int apidev_major; |
28 | ||
1da177e4 LT |
29 | /* |
30 | * SRB allocation cache | |
31 | */ | |
e18b890b | 32 | static struct kmem_cache *srb_cachep; |
1da177e4 | 33 | |
a9083016 GM |
34 | /* |
35 | * CT6 CTX allocation cache | |
36 | */ | |
37 | static struct kmem_cache *ctx_cachep; | |
3ce8866c SK |
38 | /* |
39 | * error level for logging | |
40 | */ | |
41 | int ql_errlev = ql_log_all; | |
a9083016 | 42 | |
1da177e4 | 43 | int ql2xlogintimeout = 20; |
f2019cb1 | 44 | module_param(ql2xlogintimeout, int, S_IRUGO); |
1da177e4 LT |
45 | MODULE_PARM_DESC(ql2xlogintimeout, |
46 | "Login timeout value in seconds."); | |
47 | ||
a7b61842 | 48 | int qlport_down_retry; |
f2019cb1 | 49 | module_param(qlport_down_retry, int, S_IRUGO); |
1da177e4 | 50 | MODULE_PARM_DESC(qlport_down_retry, |
900d9f98 | 51 | "Maximum number of command retries to a port that returns " |
1da177e4 LT |
52 | "a PORT-DOWN status."); |
53 | ||
1da177e4 LT |
54 | int ql2xplogiabsentdevice; |
55 | module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); | |
56 | MODULE_PARM_DESC(ql2xplogiabsentdevice, | |
57 | "Option to enable PLOGI to devices that are not present after " | |
900d9f98 | 58 | "a Fabric scan. This is needed for several broken switches. " |
1da177e4 LT |
59 | "Default is 0 - no PLOGI. 1 - perfom PLOGI."); |
60 | ||
1da177e4 | 61 | int ql2xloginretrycount = 0; |
f2019cb1 | 62 | module_param(ql2xloginretrycount, int, S_IRUGO); |
1da177e4 LT |
63 | MODULE_PARM_DESC(ql2xloginretrycount, |
64 | "Specify an alternate value for the NVRAM login retry count."); | |
65 | ||
a7a167bf | 66 | int ql2xallocfwdump = 1; |
f2019cb1 | 67 | module_param(ql2xallocfwdump, int, S_IRUGO); |
a7a167bf AV |
68 | MODULE_PARM_DESC(ql2xallocfwdump, |
69 | "Option to enable allocation of memory for a firmware dump " | |
70 | "during HBA initialization. Memory allocation requirements " | |
71 | "vary by ISP type. Default is 1 - allocate memory."); | |
72 | ||
11010fec | 73 | int ql2xextended_error_logging; |
27d94035 | 74 | module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); |
11010fec | 75 | MODULE_PARM_DESC(ql2xextended_error_logging, |
3ce8866c SK |
76 | "Option to enable extended error logging,\n" |
77 | "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" | |
78 | "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" | |
79 | "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" | |
80 | "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" | |
81 | "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" | |
82 | "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" | |
83 | "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" | |
84 | "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" | |
85 | "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" | |
cfb0919c CD |
86 | "\t\t0x1e400000 - Preferred value for capturing essential " |
87 | "debug information (equivalent to old " | |
88 | "ql2xextended_error_logging=1).\n" | |
3ce8866c | 89 | "\t\tDo LOGICAL OR of the value to enable more than one level"); |
0181944f | 90 | |
a9083016 | 91 | int ql2xshiftctondsd = 6; |
f2019cb1 | 92 | module_param(ql2xshiftctondsd, int, S_IRUGO); |
a9083016 GM |
93 | MODULE_PARM_DESC(ql2xshiftctondsd, |
94 | "Set to control shifting of command type processing " | |
95 | "based on total number of SG elements."); | |
96 | ||
1da177e4 LT |
97 | static void qla2x00_free_device(scsi_qla_host_t *); |
98 | ||
7e47e5ca | 99 | int ql2xfdmienable=1; |
f2019cb1 | 100 | module_param(ql2xfdmienable, int, S_IRUGO); |
cca5335c | 101 | MODULE_PARM_DESC(ql2xfdmienable, |
7794a5af FW |
102 | "Enables FDMI registrations. " |
103 | "0 - no FDMI. Default is 1 - perform FDMI."); | |
cca5335c | 104 | |
df7baa50 AV |
105 | #define MAX_Q_DEPTH 32 |
106 | static int ql2xmaxqdepth = MAX_Q_DEPTH; | |
107 | module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); | |
108 | MODULE_PARM_DESC(ql2xmaxqdepth, | |
109 | "Maximum queue depth to report for target devices."); | |
110 | ||
bad75002 | 111 | /* Do not change the value of this after module load */ |
8cb2049c | 112 | int ql2xenabledif = 0; |
bad75002 AE |
113 | module_param(ql2xenabledif, int, S_IRUGO|S_IWUSR); |
114 | MODULE_PARM_DESC(ql2xenabledif, | |
115 | " Enable T10-CRC-DIF " | |
8cb2049c AE |
116 | " Default is 0 - No DIF Support. 1 - Enable it" |
117 | ", 2 - Enable DIF for all types, except Type 0."); | |
bad75002 | 118 | |
8cb2049c | 119 | int ql2xenablehba_err_chk = 2; |
bad75002 AE |
120 | module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); |
121 | MODULE_PARM_DESC(ql2xenablehba_err_chk, | |
8cb2049c AE |
122 | " Enable T10-CRC-DIF Error isolation by HBA:\n" |
123 | " Default is 1.\n" | |
124 | " 0 -- Error isolation disabled\n" | |
125 | " 1 -- Error isolation enabled only for DIX Type 0\n" | |
126 | " 2 -- Error isolation enabled for all Types\n"); | |
bad75002 | 127 | |
e5896bd5 | 128 | int ql2xiidmaenable=1; |
f2019cb1 | 129 | module_param(ql2xiidmaenable, int, S_IRUGO); |
e5896bd5 AV |
130 | MODULE_PARM_DESC(ql2xiidmaenable, |
131 | "Enables iIDMA settings " | |
132 | "Default is 1 - perform iIDMA. 0 - no iIDMA."); | |
133 | ||
73208dfd | 134 | int ql2xmaxqueues = 1; |
f2019cb1 | 135 | module_param(ql2xmaxqueues, int, S_IRUGO); |
73208dfd AC |
136 | MODULE_PARM_DESC(ql2xmaxqueues, |
137 | "Enables MQ settings " | |
ae68230c JP |
138 | "Default is 1 for single queue. Set it to number " |
139 | "of queues in MQ mode."); | |
68ca949c AC |
140 | |
141 | int ql2xmultique_tag; | |
f2019cb1 | 142 | module_param(ql2xmultique_tag, int, S_IRUGO); |
68ca949c AC |
143 | MODULE_PARM_DESC(ql2xmultique_tag, |
144 | "Enables CPU affinity settings for the driver " | |
145 | "Default is 0 for no affinity of request and response IO. " | |
146 | "Set it to 1 to turn on the cpu affinity."); | |
e337d907 AV |
147 | |
148 | int ql2xfwloadbin; | |
86e45bf6 | 149 | module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); |
e337d907 | 150 | MODULE_PARM_DESC(ql2xfwloadbin, |
7c3df132 SK |
151 | "Option to specify location from which to load ISP firmware:.\n" |
152 | " 2 -- load firmware via the request_firmware() (hotplug).\n" | |
e337d907 AV |
153 | " interface.\n" |
154 | " 1 -- load firmware from flash.\n" | |
155 | " 0 -- use default semantics.\n"); | |
156 | ||
ae97c91e | 157 | int ql2xetsenable; |
f2019cb1 | 158 | module_param(ql2xetsenable, int, S_IRUGO); |
ae97c91e AV |
159 | MODULE_PARM_DESC(ql2xetsenable, |
160 | "Enables firmware ETS burst." | |
161 | "Default is 0 - skip ETS enablement."); | |
162 | ||
6907869d | 163 | int ql2xdbwr = 1; |
86e45bf6 | 164 | module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); |
a9083016 | 165 | MODULE_PARM_DESC(ql2xdbwr, |
08de2844 GM |
166 | "Option to specify scheme for request queue posting.\n" |
167 | " 0 -- Regular doorbell.\n" | |
168 | " 1 -- CAMRAM doorbell (faster).\n"); | |
a9083016 | 169 | |
f4c496c1 | 170 | int ql2xtargetreset = 1; |
f2019cb1 | 171 | module_param(ql2xtargetreset, int, S_IRUGO); |
f4c496c1 GM |
172 | MODULE_PARM_DESC(ql2xtargetreset, |
173 | "Enable target reset." | |
174 | "Default is 1 - use hw defaults."); | |
175 | ||
4da26e16 | 176 | int ql2xgffidenable; |
f2019cb1 | 177 | module_param(ql2xgffidenable, int, S_IRUGO); |
4da26e16 CD |
178 | MODULE_PARM_DESC(ql2xgffidenable, |
179 | "Enables GFF_ID checks of port type. " | |
180 | "Default is 0 - Do not use GFF_ID information."); | |
a9083016 | 181 | |
3822263e | 182 | int ql2xasynctmfenable; |
f2019cb1 | 183 | module_param(ql2xasynctmfenable, int, S_IRUGO); |
3822263e MI |
184 | MODULE_PARM_DESC(ql2xasynctmfenable, |
185 | "Enables issue of TM IOCBs asynchronously via IOCB mechanism" | |
186 | "Default is 0 - Issue TM IOCBs via mailbox mechanism."); | |
ed0de87c GM |
187 | |
188 | int ql2xdontresethba; | |
86e45bf6 | 189 | module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); |
ed0de87c | 190 | MODULE_PARM_DESC(ql2xdontresethba, |
08de2844 GM |
191 | "Option to specify reset behaviour.\n" |
192 | " 0 (Default) -- Reset on failure.\n" | |
193 | " 1 -- Do not reset on failure.\n"); | |
ed0de87c | 194 | |
82515920 AV |
195 | uint ql2xmaxlun = MAX_LUNS; |
196 | module_param(ql2xmaxlun, uint, S_IRUGO); | |
197 | MODULE_PARM_DESC(ql2xmaxlun, | |
198 | "Defines the maximum LU number to register with the SCSI " | |
199 | "midlayer. Default is 65535."); | |
200 | ||
08de2844 GM |
201 | int ql2xmdcapmask = 0x1F; |
202 | module_param(ql2xmdcapmask, int, S_IRUGO); | |
203 | MODULE_PARM_DESC(ql2xmdcapmask, | |
204 | "Set the Minidump driver capture mask level. " | |
205 | "Default is 0x7F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); | |
206 | ||
3aadff35 | 207 | int ql2xmdenable = 1; |
08de2844 GM |
208 | module_param(ql2xmdenable, int, S_IRUGO); |
209 | MODULE_PARM_DESC(ql2xmdenable, | |
210 | "Enable/disable MiniDump. " | |
3aadff35 GM |
211 | "0 - MiniDump disabled. " |
212 | "1 (Default) - MiniDump enabled."); | |
08de2844 | 213 | |
1da177e4 | 214 | /* |
fa2a1ce5 | 215 | * SCSI host template entry points |
1da177e4 LT |
216 | */ |
217 | static int qla2xxx_slave_configure(struct scsi_device * device); | |
f4f051eb | 218 | static int qla2xxx_slave_alloc(struct scsi_device *); |
1e99e33a AV |
219 | static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); |
220 | static void qla2xxx_scan_start(struct Scsi_Host *); | |
f4f051eb | 221 | static void qla2xxx_slave_destroy(struct scsi_device *); |
f281233d | 222 | static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
1da177e4 LT |
223 | static int qla2xxx_eh_abort(struct scsi_cmnd *); |
224 | static int qla2xxx_eh_device_reset(struct scsi_cmnd *); | |
523ec773 | 225 | static int qla2xxx_eh_target_reset(struct scsi_cmnd *); |
1da177e4 LT |
226 | static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); |
227 | static int qla2xxx_eh_host_reset(struct scsi_cmnd *); | |
1da177e4 | 228 | |
e881a172 | 229 | static int qla2x00_change_queue_depth(struct scsi_device *, int, int); |
ce7e4af7 AV |
230 | static int qla2x00_change_queue_type(struct scsi_device *, int); |
231 | ||
a5326f86 | 232 | struct scsi_host_template qla2xxx_driver_template = { |
1da177e4 | 233 | .module = THIS_MODULE, |
cb63067a | 234 | .name = QLA2XXX_DRIVER_NAME, |
a5326f86 | 235 | .queuecommand = qla2xxx_queuecommand, |
fca29703 AV |
236 | |
237 | .eh_abort_handler = qla2xxx_eh_abort, | |
238 | .eh_device_reset_handler = qla2xxx_eh_device_reset, | |
523ec773 | 239 | .eh_target_reset_handler = qla2xxx_eh_target_reset, |
fca29703 AV |
240 | .eh_bus_reset_handler = qla2xxx_eh_bus_reset, |
241 | .eh_host_reset_handler = qla2xxx_eh_host_reset, | |
242 | ||
243 | .slave_configure = qla2xxx_slave_configure, | |
244 | ||
245 | .slave_alloc = qla2xxx_slave_alloc, | |
246 | .slave_destroy = qla2xxx_slave_destroy, | |
ed677086 AV |
247 | .scan_finished = qla2xxx_scan_finished, |
248 | .scan_start = qla2xxx_scan_start, | |
ce7e4af7 AV |
249 | .change_queue_depth = qla2x00_change_queue_depth, |
250 | .change_queue_type = qla2x00_change_queue_type, | |
fca29703 AV |
251 | .this_id = -1, |
252 | .cmd_per_lun = 3, | |
253 | .use_clustering = ENABLE_CLUSTERING, | |
254 | .sg_tablesize = SG_ALL, | |
255 | ||
256 | .max_sectors = 0xFFFF, | |
afb046e2 | 257 | .shost_attrs = qla2x00_host_attrs, |
fca29703 AV |
258 | }; |
259 | ||
1da177e4 | 260 | static struct scsi_transport_template *qla2xxx_transport_template = NULL; |
2c3dfe3f | 261 | struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; |
1da177e4 | 262 | |
1da177e4 LT |
263 | /* TODO Convert to inlines |
264 | * | |
265 | * Timer routines | |
266 | */ | |
1da177e4 | 267 | |
2c3dfe3f | 268 | __inline__ void |
e315cd28 | 269 | qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) |
1da177e4 | 270 | { |
e315cd28 AC |
271 | init_timer(&vha->timer); |
272 | vha->timer.expires = jiffies + interval * HZ; | |
273 | vha->timer.data = (unsigned long)vha; | |
274 | vha->timer.function = (void (*)(unsigned long))func; | |
275 | add_timer(&vha->timer); | |
276 | vha->timer_active = 1; | |
1da177e4 LT |
277 | } |
278 | ||
279 | static inline void | |
e315cd28 | 280 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) |
1da177e4 | 281 | { |
a9083016 | 282 | /* Currently used for 82XX only. */ |
7c3df132 SK |
283 | if (vha->device_flags & DFLG_DEV_FAILED) { |
284 | ql_dbg(ql_dbg_timer, vha, 0x600d, | |
285 | "Device in a failed state, returning.\n"); | |
a9083016 | 286 | return; |
7c3df132 | 287 | } |
a9083016 | 288 | |
e315cd28 | 289 | mod_timer(&vha->timer, jiffies + interval * HZ); |
1da177e4 LT |
290 | } |
291 | ||
a824ebb3 | 292 | static __inline__ void |
e315cd28 | 293 | qla2x00_stop_timer(scsi_qla_host_t *vha) |
1da177e4 | 294 | { |
e315cd28 AC |
295 | del_timer_sync(&vha->timer); |
296 | vha->timer_active = 0; | |
1da177e4 LT |
297 | } |
298 | ||
1da177e4 LT |
299 | static int qla2x00_do_dpc(void *data); |
300 | ||
301 | static void qla2x00_rst_aen(scsi_qla_host_t *); | |
302 | ||
73208dfd AC |
303 | static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, |
304 | struct req_que **, struct rsp_que **); | |
e30d1756 | 305 | static void qla2x00_free_fw_dump(struct qla_hw_data *); |
e315cd28 AC |
306 | static void qla2x00_mem_free(struct qla_hw_data *); |
307 | static void qla2x00_sp_free_dma(srb_t *); | |
1da177e4 | 308 | |
1da177e4 | 309 | /* -------------------------------------------------------------------------- */ |
73208dfd AC |
310 | static int qla2x00_alloc_queues(struct qla_hw_data *ha) |
311 | { | |
7c3df132 | 312 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
2afa19a9 | 313 | ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, |
73208dfd AC |
314 | GFP_KERNEL); |
315 | if (!ha->req_q_map) { | |
7c3df132 SK |
316 | ql_log(ql_log_fatal, vha, 0x003b, |
317 | "Unable to allocate memory for request queue ptrs.\n"); | |
73208dfd AC |
318 | goto fail_req_map; |
319 | } | |
320 | ||
2afa19a9 | 321 | ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, |
73208dfd AC |
322 | GFP_KERNEL); |
323 | if (!ha->rsp_q_map) { | |
7c3df132 SK |
324 | ql_log(ql_log_fatal, vha, 0x003c, |
325 | "Unable to allocate memory for response queue ptrs.\n"); | |
73208dfd AC |
326 | goto fail_rsp_map; |
327 | } | |
328 | set_bit(0, ha->rsp_qid_map); | |
329 | set_bit(0, ha->req_qid_map); | |
330 | return 1; | |
331 | ||
332 | fail_rsp_map: | |
333 | kfree(ha->req_q_map); | |
334 | ha->req_q_map = NULL; | |
335 | fail_req_map: | |
336 | return -ENOMEM; | |
337 | } | |
338 | ||
2afa19a9 | 339 | static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) |
73208dfd | 340 | { |
73208dfd AC |
341 | if (req && req->ring) |
342 | dma_free_coherent(&ha->pdev->dev, | |
343 | (req->length + 1) * sizeof(request_t), | |
344 | req->ring, req->dma); | |
345 | ||
346 | kfree(req); | |
347 | req = NULL; | |
348 | } | |
349 | ||
2afa19a9 AC |
350 | static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) |
351 | { | |
352 | if (rsp && rsp->ring) | |
353 | dma_free_coherent(&ha->pdev->dev, | |
354 | (rsp->length + 1) * sizeof(response_t), | |
355 | rsp->ring, rsp->dma); | |
356 | ||
357 | kfree(rsp); | |
358 | rsp = NULL; | |
359 | } | |
360 | ||
73208dfd AC |
361 | static void qla2x00_free_queues(struct qla_hw_data *ha) |
362 | { | |
363 | struct req_que *req; | |
364 | struct rsp_que *rsp; | |
365 | int cnt; | |
366 | ||
2afa19a9 | 367 | for (cnt = 0; cnt < ha->max_req_queues; cnt++) { |
73208dfd | 368 | req = ha->req_q_map[cnt]; |
2afa19a9 | 369 | qla2x00_free_req_que(ha, req); |
73208dfd | 370 | } |
73208dfd AC |
371 | kfree(ha->req_q_map); |
372 | ha->req_q_map = NULL; | |
2afa19a9 AC |
373 | |
374 | for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { | |
375 | rsp = ha->rsp_q_map[cnt]; | |
376 | qla2x00_free_rsp_que(ha, rsp); | |
377 | } | |
378 | kfree(ha->rsp_q_map); | |
379 | ha->rsp_q_map = NULL; | |
73208dfd AC |
380 | } |
381 | ||
68ca949c AC |
382 | static int qla25xx_setup_mode(struct scsi_qla_host *vha) |
383 | { | |
384 | uint16_t options = 0; | |
385 | int ques, req, ret; | |
386 | struct qla_hw_data *ha = vha->hw; | |
387 | ||
7163ea81 | 388 | if (!(ha->fw_attributes & BIT_6)) { |
7c3df132 SK |
389 | ql_log(ql_log_warn, vha, 0x00d8, |
390 | "Firmware is not multi-queue capable.\n"); | |
7163ea81 AC |
391 | goto fail; |
392 | } | |
68ca949c | 393 | if (ql2xmultique_tag) { |
68ca949c AC |
394 | /* create a request queue for IO */ |
395 | options |= BIT_7; | |
396 | req = qla25xx_create_req_que(ha, options, 0, 0, -1, | |
397 | QLA_DEFAULT_QUE_QOS); | |
398 | if (!req) { | |
7c3df132 SK |
399 | ql_log(ql_log_warn, vha, 0x00e0, |
400 | "Failed to create request queue.\n"); | |
68ca949c AC |
401 | goto fail; |
402 | } | |
278274d5 | 403 | ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); |
68ca949c AC |
404 | vha->req = ha->req_q_map[req]; |
405 | options |= BIT_1; | |
406 | for (ques = 1; ques < ha->max_rsp_queues; ques++) { | |
407 | ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); | |
408 | if (!ret) { | |
7c3df132 SK |
409 | ql_log(ql_log_warn, vha, 0x00e8, |
410 | "Failed to create response queue.\n"); | |
68ca949c AC |
411 | goto fail2; |
412 | } | |
413 | } | |
7163ea81 | 414 | ha->flags.cpu_affinity_enabled = 1; |
7c3df132 SK |
415 | ql_dbg(ql_dbg_multiq, vha, 0xc007, |
416 | "CPU affinity mode enalbed, " | |
417 | "no. of response queues:%d no. of request queues:%d.\n", | |
418 | ha->max_rsp_queues, ha->max_req_queues); | |
419 | ql_dbg(ql_dbg_init, vha, 0x00e9, | |
420 | "CPU affinity mode enalbed, " | |
421 | "no. of response queues:%d no. of request queues:%d.\n", | |
422 | ha->max_rsp_queues, ha->max_req_queues); | |
68ca949c AC |
423 | } |
424 | return 0; | |
425 | fail2: | |
426 | qla25xx_delete_queues(vha); | |
7163ea81 AC |
427 | destroy_workqueue(ha->wq); |
428 | ha->wq = NULL; | |
0cd33fcf | 429 | vha->req = ha->req_q_map[0]; |
68ca949c AC |
430 | fail: |
431 | ha->mqenable = 0; | |
7163ea81 AC |
432 | kfree(ha->req_q_map); |
433 | kfree(ha->rsp_q_map); | |
434 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
68ca949c AC |
435 | return 1; |
436 | } | |
437 | ||
1da177e4 | 438 | static char * |
e315cd28 | 439 | qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) |
1da177e4 | 440 | { |
e315cd28 | 441 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
442 | static char *pci_bus_modes[] = { |
443 | "33", "66", "100", "133", | |
444 | }; | |
445 | uint16_t pci_bus; | |
446 | ||
447 | strcpy(str, "PCI"); | |
448 | pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; | |
449 | if (pci_bus) { | |
450 | strcat(str, "-X ("); | |
451 | strcat(str, pci_bus_modes[pci_bus]); | |
452 | } else { | |
453 | pci_bus = (ha->pci_attr & BIT_8) >> 8; | |
454 | strcat(str, " ("); | |
455 | strcat(str, pci_bus_modes[pci_bus]); | |
456 | } | |
457 | strcat(str, " MHz)"); | |
458 | ||
459 | return (str); | |
460 | } | |
461 | ||
fca29703 | 462 | static char * |
e315cd28 | 463 | qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) |
fca29703 AV |
464 | { |
465 | static char *pci_bus_modes[] = { "33", "66", "100", "133", }; | |
e315cd28 | 466 | struct qla_hw_data *ha = vha->hw; |
fca29703 AV |
467 | uint32_t pci_bus; |
468 | int pcie_reg; | |
469 | ||
470 | pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); | |
471 | if (pcie_reg) { | |
472 | char lwstr[6]; | |
473 | uint16_t pcie_lstat, lspeed, lwidth; | |
474 | ||
475 | pcie_reg += 0x12; | |
476 | pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat); | |
477 | lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3); | |
478 | lwidth = (pcie_lstat & | |
479 | (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; | |
480 | ||
481 | strcpy(str, "PCIe ("); | |
482 | if (lspeed == 1) | |
c87a0d8c | 483 | strcat(str, "2.5GT/s "); |
c3a2f0df | 484 | else if (lspeed == 2) |
c87a0d8c | 485 | strcat(str, "5.0GT/s "); |
fca29703 AV |
486 | else |
487 | strcat(str, "<unknown> "); | |
488 | snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); | |
489 | strcat(str, lwstr); | |
490 | ||
491 | return str; | |
492 | } | |
493 | ||
494 | strcpy(str, "PCI"); | |
495 | pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; | |
496 | if (pci_bus == 0 || pci_bus == 8) { | |
497 | strcat(str, " ("); | |
498 | strcat(str, pci_bus_modes[pci_bus >> 3]); | |
499 | } else { | |
500 | strcat(str, "-X "); | |
501 | if (pci_bus & BIT_2) | |
502 | strcat(str, "Mode 2"); | |
503 | else | |
504 | strcat(str, "Mode 1"); | |
505 | strcat(str, " ("); | |
506 | strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); | |
507 | } | |
508 | strcat(str, " MHz)"); | |
509 | ||
510 | return str; | |
511 | } | |
512 | ||
e5f82ab8 | 513 | static char * |
e315cd28 | 514 | qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str) |
1da177e4 LT |
515 | { |
516 | char un_str[10]; | |
e315cd28 | 517 | struct qla_hw_data *ha = vha->hw; |
fa2a1ce5 | 518 | |
1da177e4 LT |
519 | sprintf(str, "%d.%02d.%02d ", ha->fw_major_version, |
520 | ha->fw_minor_version, | |
521 | ha->fw_subminor_version); | |
522 | ||
523 | if (ha->fw_attributes & BIT_9) { | |
524 | strcat(str, "FLX"); | |
525 | return (str); | |
526 | } | |
527 | ||
528 | switch (ha->fw_attributes & 0xFF) { | |
529 | case 0x7: | |
530 | strcat(str, "EF"); | |
531 | break; | |
532 | case 0x17: | |
533 | strcat(str, "TP"); | |
534 | break; | |
535 | case 0x37: | |
536 | strcat(str, "IP"); | |
537 | break; | |
538 | case 0x77: | |
539 | strcat(str, "VI"); | |
540 | break; | |
541 | default: | |
542 | sprintf(un_str, "(%x)", ha->fw_attributes); | |
543 | strcat(str, un_str); | |
544 | break; | |
545 | } | |
546 | if (ha->fw_attributes & 0x100) | |
547 | strcat(str, "X"); | |
548 | ||
549 | return (str); | |
550 | } | |
551 | ||
e5f82ab8 | 552 | static char * |
e315cd28 | 553 | qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str) |
fca29703 | 554 | { |
e315cd28 | 555 | struct qla_hw_data *ha = vha->hw; |
f0883ac6 | 556 | |
3a03eb79 AV |
557 | sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version, |
558 | ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); | |
fca29703 | 559 | return str; |
fca29703 AV |
560 | } |
561 | ||
562 | static inline srb_t * | |
e315cd28 | 563 | qla2x00_get_new_sp(scsi_qla_host_t *vha, fc_port_t *fcport, |
f5e3e40b | 564 | struct scsi_cmnd *cmd) |
fca29703 AV |
565 | { |
566 | srb_t *sp; | |
e315cd28 | 567 | struct qla_hw_data *ha = vha->hw; |
fca29703 AV |
568 | |
569 | sp = mempool_alloc(ha->srb_mempool, GFP_ATOMIC); | |
7c3df132 SK |
570 | if (!sp) { |
571 | ql_log(ql_log_warn, vha, 0x3006, | |
572 | "Memory allocation failed for sp.\n"); | |
fca29703 | 573 | return sp; |
7c3df132 | 574 | } |
fca29703 | 575 | |
083a469d | 576 | atomic_set(&sp->ref_count, 1); |
fca29703 AV |
577 | sp->fcport = fcport; |
578 | sp->cmd = cmd; | |
579 | sp->flags = 0; | |
580 | CMD_SP(cmd) = (void *)sp; | |
cf53b069 | 581 | sp->ctx = NULL; |
fca29703 AV |
582 | |
583 | return sp; | |
584 | } | |
585 | ||
1da177e4 | 586 | static int |
f5e3e40b | 587 | qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) |
fca29703 | 588 | { |
134ae078 | 589 | scsi_qla_host_t *vha = shost_priv(host); |
fca29703 | 590 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
19a7b4ae | 591 | struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); |
e315cd28 AC |
592 | struct qla_hw_data *ha = vha->hw; |
593 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
fca29703 AV |
594 | srb_t *sp; |
595 | int rval; | |
596 | ||
85880801 | 597 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
598 | if (ha->flags.pci_channel_io_perm_failure) { |
599 | ql_dbg(ql_dbg_io, vha, 0x3001, | |
600 | "PCI Channel IO permanent failure, exiting " | |
601 | "cmd=%p.\n", cmd); | |
b9b12f73 | 602 | cmd->result = DID_NO_CONNECT << 16; |
7c3df132 SK |
603 | } else { |
604 | ql_dbg(ql_dbg_io, vha, 0x3002, | |
605 | "EEH_Busy, Requeuing the cmd=%p.\n", cmd); | |
85880801 | 606 | cmd->result = DID_REQUEUE << 16; |
7c3df132 | 607 | } |
14e660e6 SJ |
608 | goto qc24_fail_command; |
609 | } | |
610 | ||
19a7b4ae JSEC |
611 | rval = fc_remote_port_chkready(rport); |
612 | if (rval) { | |
613 | cmd->result = rval; | |
7c3df132 SK |
614 | ql_dbg(ql_dbg_io, vha, 0x3003, |
615 | "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", | |
616 | cmd, rval); | |
fca29703 AV |
617 | goto qc24_fail_command; |
618 | } | |
619 | ||
bad75002 AE |
620 | if (!vha->flags.difdix_supported && |
621 | scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { | |
7c3df132 SK |
622 | ql_dbg(ql_dbg_io, vha, 0x3004, |
623 | "DIF Cap not reg, fail DIF capable cmd's:%p.\n", | |
624 | cmd); | |
bad75002 AE |
625 | cmd->result = DID_NO_CONNECT << 16; |
626 | goto qc24_fail_command; | |
627 | } | |
fca29703 AV |
628 | if (atomic_read(&fcport->state) != FCS_ONLINE) { |
629 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || | |
38170fa8 | 630 | atomic_read(&base_vha->loop_state) == LOOP_DEAD) { |
7c3df132 SK |
631 | ql_dbg(ql_dbg_io, vha, 0x3005, |
632 | "Returning DNC, fcport_state=%d loop_state=%d.\n", | |
633 | atomic_read(&fcport->state), | |
634 | atomic_read(&base_vha->loop_state)); | |
fca29703 AV |
635 | cmd->result = DID_NO_CONNECT << 16; |
636 | goto qc24_fail_command; | |
637 | } | |
7b594131 | 638 | goto qc24_target_busy; |
fca29703 AV |
639 | } |
640 | ||
f5e3e40b | 641 | sp = qla2x00_get_new_sp(base_vha, fcport, cmd); |
fca29703 | 642 | if (!sp) |
f5e3e40b | 643 | goto qc24_host_busy; |
fca29703 | 644 | |
e315cd28 | 645 | rval = ha->isp_ops->start_scsi(sp); |
7c3df132 SK |
646 | if (rval != QLA_SUCCESS) { |
647 | ql_dbg(ql_dbg_io, vha, 0x3013, | |
648 | "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); | |
fca29703 | 649 | goto qc24_host_busy_free_sp; |
7c3df132 | 650 | } |
fca29703 | 651 | |
fca29703 AV |
652 | return 0; |
653 | ||
654 | qc24_host_busy_free_sp: | |
e315cd28 AC |
655 | qla2x00_sp_free_dma(sp); |
656 | mempool_free(sp, ha->srb_mempool); | |
fca29703 | 657 | |
f5e3e40b | 658 | qc24_host_busy: |
fca29703 AV |
659 | return SCSI_MLQUEUE_HOST_BUSY; |
660 | ||
7b594131 MC |
661 | qc24_target_busy: |
662 | return SCSI_MLQUEUE_TARGET_BUSY; | |
663 | ||
fca29703 | 664 | qc24_fail_command: |
f5e3e40b | 665 | cmd->scsi_done(cmd); |
fca29703 AV |
666 | |
667 | return 0; | |
668 | } | |
669 | ||
1da177e4 LT |
670 | /* |
671 | * qla2x00_eh_wait_on_command | |
672 | * Waits for the command to be returned by the Firmware for some | |
673 | * max time. | |
674 | * | |
675 | * Input: | |
1da177e4 | 676 | * cmd = Scsi Command to wait on. |
1da177e4 LT |
677 | * |
678 | * Return: | |
679 | * Not Found : 0 | |
680 | * Found : 1 | |
681 | */ | |
682 | static int | |
e315cd28 | 683 | qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) |
1da177e4 | 684 | { |
fe74c71f AV |
685 | #define ABORT_POLLING_PERIOD 1000 |
686 | #define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD)) | |
f4f051eb | 687 | unsigned long wait_iter = ABORT_WAIT_ITER; |
85880801 AV |
688 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
689 | struct qla_hw_data *ha = vha->hw; | |
f4f051eb | 690 | int ret = QLA_SUCCESS; |
1da177e4 | 691 | |
85880801 | 692 | if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { |
7c3df132 SK |
693 | ql_dbg(ql_dbg_taskm, vha, 0x8005, |
694 | "Return:eh_wait.\n"); | |
85880801 AV |
695 | return ret; |
696 | } | |
697 | ||
d970432c | 698 | while (CMD_SP(cmd) && wait_iter--) { |
fe74c71f | 699 | msleep(ABORT_POLLING_PERIOD); |
f4f051eb AV |
700 | } |
701 | if (CMD_SP(cmd)) | |
702 | ret = QLA_FUNCTION_FAILED; | |
1da177e4 | 703 | |
f4f051eb | 704 | return ret; |
1da177e4 LT |
705 | } |
706 | ||
707 | /* | |
708 | * qla2x00_wait_for_hba_online | |
fa2a1ce5 | 709 | * Wait till the HBA is online after going through |
1da177e4 LT |
710 | * <= MAX_RETRIES_OF_ISP_ABORT or |
711 | * finally HBA is disabled ie marked offline | |
712 | * | |
713 | * Input: | |
714 | * ha - pointer to host adapter structure | |
fa2a1ce5 AV |
715 | * |
716 | * Note: | |
1da177e4 LT |
717 | * Does context switching-Release SPIN_LOCK |
718 | * (if any) before calling this routine. | |
719 | * | |
720 | * Return: | |
721 | * Success (Adapter is online) : 0 | |
722 | * Failed (Adapter is offline/disabled) : 1 | |
723 | */ | |
854165f4 | 724 | int |
e315cd28 | 725 | qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) |
1da177e4 | 726 | { |
fca29703 AV |
727 | int return_status; |
728 | unsigned long wait_online; | |
e315cd28 AC |
729 | struct qla_hw_data *ha = vha->hw; |
730 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 731 | |
fa2a1ce5 | 732 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); |
e315cd28 AC |
733 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || |
734 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
735 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
736 | ha->dpc_active) && time_before(jiffies, wait_online)) { | |
1da177e4 LT |
737 | |
738 | msleep(1000); | |
739 | } | |
e315cd28 | 740 | if (base_vha->flags.online) |
fa2a1ce5 | 741 | return_status = QLA_SUCCESS; |
1da177e4 LT |
742 | else |
743 | return_status = QLA_FUNCTION_FAILED; | |
744 | ||
1da177e4 LT |
745 | return (return_status); |
746 | } | |
747 | ||
86fbee86 LC |
748 | /* |
749 | * qla2x00_wait_for_reset_ready | |
750 | * Wait till the HBA is online after going through | |
751 | * <= MAX_RETRIES_OF_ISP_ABORT or | |
752 | * finally HBA is disabled ie marked offline or flash | |
753 | * operations are in progress. | |
754 | * | |
755 | * Input: | |
756 | * ha - pointer to host adapter structure | |
757 | * | |
758 | * Note: | |
759 | * Does context switching-Release SPIN_LOCK | |
760 | * (if any) before calling this routine. | |
761 | * | |
762 | * Return: | |
763 | * Success (Adapter is online/no flash ops) : 0 | |
764 | * Failed (Adapter is offline/disabled/flash ops in progress) : 1 | |
765 | */ | |
3dbe756a | 766 | static int |
86fbee86 LC |
767 | qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha) |
768 | { | |
769 | int return_status; | |
770 | unsigned long wait_online; | |
771 | struct qla_hw_data *ha = vha->hw; | |
772 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
773 | ||
774 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
775 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
776 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
777 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
778 | ha->optrom_state != QLA_SWAITING || | |
779 | ha->dpc_active) && time_before(jiffies, wait_online)) | |
780 | msleep(1000); | |
781 | ||
782 | if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING) | |
783 | return_status = QLA_SUCCESS; | |
784 | else | |
785 | return_status = QLA_FUNCTION_FAILED; | |
786 | ||
7c3df132 SK |
787 | ql_dbg(ql_dbg_taskm, vha, 0x8019, |
788 | "%s return status=%d.\n", __func__, return_status); | |
86fbee86 LC |
789 | |
790 | return return_status; | |
791 | } | |
792 | ||
2533cf67 LC |
793 | int |
794 | qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) | |
795 | { | |
796 | int return_status; | |
797 | unsigned long wait_reset; | |
798 | struct qla_hw_data *ha = vha->hw; | |
799 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
800 | ||
801 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
802 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
803 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
804 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
805 | ha->dpc_active) && time_before(jiffies, wait_reset)) { | |
806 | ||
807 | msleep(1000); | |
808 | ||
809 | if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && | |
810 | ha->flags.chip_reset_done) | |
811 | break; | |
812 | } | |
813 | if (ha->flags.chip_reset_done) | |
814 | return_status = QLA_SUCCESS; | |
815 | else | |
816 | return_status = QLA_FUNCTION_FAILED; | |
817 | ||
818 | return return_status; | |
819 | } | |
820 | ||
083a469d GM |
821 | static void |
822 | sp_get(struct srb *sp) | |
823 | { | |
824 | atomic_inc(&sp->ref_count); | |
825 | } | |
826 | ||
1da177e4 LT |
827 | /************************************************************************** |
828 | * qla2xxx_eh_abort | |
829 | * | |
830 | * Description: | |
831 | * The abort function will abort the specified command. | |
832 | * | |
833 | * Input: | |
834 | * cmd = Linux SCSI command packet to be aborted. | |
835 | * | |
836 | * Returns: | |
837 | * Either SUCCESS or FAILED. | |
838 | * | |
839 | * Note: | |
2ea00202 | 840 | * Only return FAILED if command not returned by firmware. |
1da177e4 | 841 | **************************************************************************/ |
e5f82ab8 | 842 | static int |
1da177e4 LT |
843 | qla2xxx_eh_abort(struct scsi_cmnd *cmd) |
844 | { | |
e315cd28 | 845 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
f4f051eb | 846 | srb_t *sp; |
4e98d3b8 | 847 | int ret; |
f4f051eb | 848 | unsigned int id, lun; |
18e144d3 | 849 | unsigned long flags; |
2ea00202 | 850 | int wait = 0; |
e315cd28 | 851 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 852 | |
f4f051eb | 853 | if (!CMD_SP(cmd)) |
2ea00202 | 854 | return SUCCESS; |
1da177e4 | 855 | |
4e98d3b8 AV |
856 | ret = fc_block_scsi_eh(cmd); |
857 | if (ret != 0) | |
858 | return ret; | |
859 | ret = SUCCESS; | |
860 | ||
f4f051eb AV |
861 | id = cmd->device->id; |
862 | lun = cmd->device->lun; | |
1da177e4 | 863 | |
e315cd28 | 864 | spin_lock_irqsave(&ha->hardware_lock, flags); |
170babc3 MC |
865 | sp = (srb_t *) CMD_SP(cmd); |
866 | if (!sp) { | |
867 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
868 | return SUCCESS; | |
869 | } | |
1da177e4 | 870 | |
7c3df132 | 871 | ql_dbg(ql_dbg_taskm, vha, 0x8002, |
cfb0919c CD |
872 | "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n", |
873 | vha->host_no, id, lun, sp, cmd); | |
17d98630 | 874 | |
170babc3 MC |
875 | /* Get a reference to the sp and drop the lock.*/ |
876 | sp_get(sp); | |
083a469d | 877 | |
e315cd28 | 878 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
170babc3 | 879 | if (ha->isp_ops->abort_command(sp)) { |
7c3df132 | 880 | ql_dbg(ql_dbg_taskm, vha, 0x8003, |
cfb0919c | 881 | "Abort command mbx failed cmd=%p.\n", cmd); |
170babc3 | 882 | } else { |
7c3df132 | 883 | ql_dbg(ql_dbg_taskm, vha, 0x8004, |
cfb0919c | 884 | "Abort command mbx success cmd=%p.\n", cmd); |
170babc3 MC |
885 | wait = 1; |
886 | } | |
75942064 SK |
887 | |
888 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
170babc3 | 889 | qla2x00_sp_compl(ha, sp); |
75942064 | 890 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
1da177e4 | 891 | |
bc91ade9 CD |
892 | /* Did the command return during mailbox execution? */ |
893 | if (ret == FAILED && !CMD_SP(cmd)) | |
894 | ret = SUCCESS; | |
895 | ||
f4f051eb | 896 | /* Wait for the command to be returned. */ |
2ea00202 | 897 | if (wait) { |
e315cd28 | 898 | if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { |
7c3df132 | 899 | ql_log(ql_log_warn, vha, 0x8006, |
cfb0919c | 900 | "Abort handler timed out cmd=%p.\n", cmd); |
2ea00202 | 901 | ret = FAILED; |
f4f051eb | 902 | } |
1da177e4 | 903 | } |
1da177e4 | 904 | |
7c3df132 | 905 | ql_log(ql_log_info, vha, 0x801c, |
cfb0919c CD |
906 | "Abort command issued nexus=%ld:%d:%d -- %d %x.\n", |
907 | vha->host_no, id, lun, wait, ret); | |
1da177e4 | 908 | |
f4f051eb AV |
909 | return ret; |
910 | } | |
1da177e4 | 911 | |
4d78c973 | 912 | int |
e315cd28 | 913 | qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, |
4d78c973 | 914 | unsigned int l, enum nexus_wait_type type) |
f4f051eb | 915 | { |
17d98630 | 916 | int cnt, match, status; |
18e144d3 | 917 | unsigned long flags; |
e315cd28 | 918 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 919 | struct req_que *req; |
4d78c973 | 920 | srb_t *sp; |
1da177e4 | 921 | |
523ec773 | 922 | status = QLA_SUCCESS; |
17d98630 | 923 | |
e315cd28 | 924 | spin_lock_irqsave(&ha->hardware_lock, flags); |
67c2e93a | 925 | req = vha->req; |
17d98630 AC |
926 | for (cnt = 1; status == QLA_SUCCESS && |
927 | cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { | |
928 | sp = req->outstanding_cmds[cnt]; | |
929 | if (!sp) | |
523ec773 | 930 | continue; |
bad75002 | 931 | if ((sp->ctx) && !IS_PROT_IO(sp)) |
cf53b069 | 932 | continue; |
17d98630 AC |
933 | if (vha->vp_idx != sp->fcport->vha->vp_idx) |
934 | continue; | |
935 | match = 0; | |
936 | switch (type) { | |
937 | case WAIT_HOST: | |
938 | match = 1; | |
939 | break; | |
940 | case WAIT_TARGET: | |
941 | match = sp->cmd->device->id == t; | |
942 | break; | |
943 | case WAIT_LUN: | |
944 | match = (sp->cmd->device->id == t && | |
945 | sp->cmd->device->lun == l); | |
946 | break; | |
73208dfd | 947 | } |
17d98630 AC |
948 | if (!match) |
949 | continue; | |
950 | ||
951 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
952 | status = qla2x00_eh_wait_on_command(sp->cmd); | |
953 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1da177e4 | 954 | } |
e315cd28 | 955 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
523ec773 AV |
956 | |
957 | return status; | |
1da177e4 LT |
958 | } |
959 | ||
523ec773 AV |
960 | static char *reset_errors[] = { |
961 | "HBA not online", | |
962 | "HBA not ready", | |
963 | "Task management failed", | |
964 | "Waiting for command completions", | |
965 | }; | |
1da177e4 | 966 | |
e5f82ab8 | 967 | static int |
523ec773 | 968 | __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, |
2afa19a9 | 969 | struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int)) |
1da177e4 | 970 | { |
e315cd28 | 971 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 972 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
523ec773 | 973 | int err; |
1da177e4 | 974 | |
7c3df132 | 975 | if (!fcport) { |
523ec773 | 976 | return FAILED; |
7c3df132 | 977 | } |
1da177e4 | 978 | |
4e98d3b8 AV |
979 | err = fc_block_scsi_eh(cmd); |
980 | if (err != 0) | |
981 | return err; | |
982 | ||
7c3df132 | 983 | ql_log(ql_log_info, vha, 0x8009, |
cfb0919c | 984 | "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no, |
7c3df132 | 985 | cmd->device->id, cmd->device->lun, cmd); |
1da177e4 | 986 | |
523ec773 | 987 | err = 0; |
7c3df132 SK |
988 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
989 | ql_log(ql_log_warn, vha, 0x800a, | |
990 | "Wait for hba online failed for cmd=%p.\n", cmd); | |
523ec773 | 991 | goto eh_reset_failed; |
7c3df132 | 992 | } |
523ec773 | 993 | err = 2; |
2afa19a9 | 994 | if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) |
7c3df132 SK |
995 | != QLA_SUCCESS) { |
996 | ql_log(ql_log_warn, vha, 0x800c, | |
997 | "do_reset failed for cmd=%p.\n", cmd); | |
523ec773 | 998 | goto eh_reset_failed; |
7c3df132 | 999 | } |
523ec773 | 1000 | err = 3; |
e315cd28 | 1001 | if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, |
7c3df132 SK |
1002 | cmd->device->lun, type) != QLA_SUCCESS) { |
1003 | ql_log(ql_log_warn, vha, 0x800d, | |
1004 | "wait for peding cmds failed for cmd=%p.\n", cmd); | |
523ec773 | 1005 | goto eh_reset_failed; |
7c3df132 | 1006 | } |
523ec773 | 1007 | |
7c3df132 | 1008 | ql_log(ql_log_info, vha, 0x800e, |
cfb0919c CD |
1009 | "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name, |
1010 | vha->host_no, cmd->device->id, cmd->device->lun, cmd); | |
523ec773 AV |
1011 | |
1012 | return SUCCESS; | |
1013 | ||
4d78c973 | 1014 | eh_reset_failed: |
7c3df132 | 1015 | ql_log(ql_log_info, vha, 0x800f, |
cfb0919c CD |
1016 | "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name, |
1017 | reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, | |
1018 | cmd); | |
523ec773 AV |
1019 | return FAILED; |
1020 | } | |
1da177e4 | 1021 | |
523ec773 AV |
1022 | static int |
1023 | qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) | |
1024 | { | |
e315cd28 AC |
1025 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1026 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1027 | |
523ec773 AV |
1028 | return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, |
1029 | ha->isp_ops->lun_reset); | |
1da177e4 LT |
1030 | } |
1031 | ||
1da177e4 | 1032 | static int |
523ec773 | 1033 | qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) |
1da177e4 | 1034 | { |
e315cd28 AC |
1035 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1036 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1037 | |
523ec773 AV |
1038 | return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, |
1039 | ha->isp_ops->target_reset); | |
1da177e4 LT |
1040 | } |
1041 | ||
1da177e4 LT |
1042 | /************************************************************************** |
1043 | * qla2xxx_eh_bus_reset | |
1044 | * | |
1045 | * Description: | |
1046 | * The bus reset function will reset the bus and abort any executing | |
1047 | * commands. | |
1048 | * | |
1049 | * Input: | |
1050 | * cmd = Linux SCSI command packet of the command that cause the | |
1051 | * bus reset. | |
1052 | * | |
1053 | * Returns: | |
1054 | * SUCCESS/FAILURE (defined as macro in scsi.h). | |
1055 | * | |
1056 | **************************************************************************/ | |
e5f82ab8 | 1057 | static int |
1da177e4 LT |
1058 | qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) |
1059 | { | |
e315cd28 | 1060 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1061 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
2c3dfe3f | 1062 | int ret = FAILED; |
f4f051eb | 1063 | unsigned int id, lun; |
f4f051eb | 1064 | |
f4f051eb AV |
1065 | id = cmd->device->id; |
1066 | lun = cmd->device->lun; | |
1da177e4 | 1067 | |
7c3df132 | 1068 | if (!fcport) { |
f4f051eb | 1069 | return ret; |
7c3df132 | 1070 | } |
1da177e4 | 1071 | |
4e98d3b8 AV |
1072 | ret = fc_block_scsi_eh(cmd); |
1073 | if (ret != 0) | |
1074 | return ret; | |
1075 | ret = FAILED; | |
1076 | ||
7c3df132 | 1077 | ql_log(ql_log_info, vha, 0x8012, |
cfb0919c | 1078 | "BUS RESET ISSUED nexus=%ld:%d%d.\n", vha->host_no, id, lun); |
1da177e4 | 1079 | |
e315cd28 | 1080 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
7c3df132 SK |
1081 | ql_log(ql_log_fatal, vha, 0x8013, |
1082 | "Wait for hba online failed board disabled.\n"); | |
f4f051eb | 1083 | goto eh_bus_reset_done; |
1da177e4 LT |
1084 | } |
1085 | ||
ad537689 SK |
1086 | if (qla2x00_loop_reset(vha) == QLA_SUCCESS) |
1087 | ret = SUCCESS; | |
1088 | ||
f4f051eb AV |
1089 | if (ret == FAILED) |
1090 | goto eh_bus_reset_done; | |
1da177e4 | 1091 | |
9a41a62b | 1092 | /* Flush outstanding commands. */ |
4d78c973 | 1093 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != |
7c3df132 SK |
1094 | QLA_SUCCESS) { |
1095 | ql_log(ql_log_warn, vha, 0x8014, | |
1096 | "Wait for pending commands failed.\n"); | |
9a41a62b | 1097 | ret = FAILED; |
7c3df132 | 1098 | } |
1da177e4 | 1099 | |
f4f051eb | 1100 | eh_bus_reset_done: |
7c3df132 | 1101 | ql_log(ql_log_warn, vha, 0x802b, |
cfb0919c CD |
1102 | "BUS RESET %s nexus=%ld:%d:%d.\n", |
1103 | (ret == FAILED) ? "FAILED" : "SUCCEDED", vha->host_no, id, lun); | |
1da177e4 | 1104 | |
f4f051eb | 1105 | return ret; |
1da177e4 LT |
1106 | } |
1107 | ||
1108 | /************************************************************************** | |
1109 | * qla2xxx_eh_host_reset | |
1110 | * | |
1111 | * Description: | |
1112 | * The reset function will reset the Adapter. | |
1113 | * | |
1114 | * Input: | |
1115 | * cmd = Linux SCSI command packet of the command that cause the | |
1116 | * adapter reset. | |
1117 | * | |
1118 | * Returns: | |
1119 | * Either SUCCESS or FAILED. | |
1120 | * | |
1121 | * Note: | |
1122 | **************************************************************************/ | |
e5f82ab8 | 1123 | static int |
1da177e4 LT |
1124 | qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) |
1125 | { | |
e315cd28 | 1126 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1127 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
e315cd28 | 1128 | struct qla_hw_data *ha = vha->hw; |
2c3dfe3f | 1129 | int ret = FAILED; |
f4f051eb | 1130 | unsigned int id, lun; |
e315cd28 | 1131 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 1132 | |
f4f051eb AV |
1133 | id = cmd->device->id; |
1134 | lun = cmd->device->lun; | |
f4f051eb | 1135 | |
7c3df132 | 1136 | if (!fcport) { |
f4f051eb | 1137 | return ret; |
7c3df132 | 1138 | } |
1da177e4 | 1139 | |
4e98d3b8 AV |
1140 | ret = fc_block_scsi_eh(cmd); |
1141 | if (ret != 0) | |
1142 | return ret; | |
1143 | ret = FAILED; | |
1144 | ||
7c3df132 | 1145 | ql_log(ql_log_info, vha, 0x8018, |
cfb0919c | 1146 | "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun); |
1da177e4 | 1147 | |
86fbee86 | 1148 | if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS) |
f4f051eb | 1149 | goto eh_host_reset_lock; |
1da177e4 | 1150 | |
e315cd28 AC |
1151 | if (vha != base_vha) { |
1152 | if (qla2x00_vp_abort_isp(vha)) | |
f4f051eb | 1153 | goto eh_host_reset_lock; |
e315cd28 | 1154 | } else { |
a9083016 GM |
1155 | if (IS_QLA82XX(vha->hw)) { |
1156 | if (!qla82xx_fcoe_ctx_reset(vha)) { | |
1157 | /* Ctx reset success */ | |
1158 | ret = SUCCESS; | |
1159 | goto eh_host_reset_lock; | |
1160 | } | |
1161 | /* fall thru if ctx reset failed */ | |
1162 | } | |
68ca949c AC |
1163 | if (ha->wq) |
1164 | flush_workqueue(ha->wq); | |
1165 | ||
e315cd28 | 1166 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 1167 | if (ha->isp_ops->abort_isp(base_vha)) { |
e315cd28 AC |
1168 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
1169 | /* failed. schedule dpc to try */ | |
1170 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | |
1171 | ||
7c3df132 SK |
1172 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
1173 | ql_log(ql_log_warn, vha, 0x802a, | |
1174 | "wait for hba online failed.\n"); | |
e315cd28 | 1175 | goto eh_host_reset_lock; |
7c3df132 | 1176 | } |
e315cd28 AC |
1177 | } |
1178 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
fa2a1ce5 | 1179 | } |
1da177e4 | 1180 | |
e315cd28 | 1181 | /* Waiting for command to be returned to OS.*/ |
4d78c973 | 1182 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == |
e315cd28 | 1183 | QLA_SUCCESS) |
f4f051eb | 1184 | ret = SUCCESS; |
1da177e4 | 1185 | |
f4f051eb | 1186 | eh_host_reset_lock: |
cfb0919c CD |
1187 | ql_log(ql_log_info, vha, 0x8017, |
1188 | "ADAPTER RESET %s nexus=%ld:%d:%d.\n", | |
1189 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); | |
1da177e4 | 1190 | |
f4f051eb AV |
1191 | return ret; |
1192 | } | |
1da177e4 LT |
1193 | |
1194 | /* | |
1195 | * qla2x00_loop_reset | |
1196 | * Issue loop reset. | |
1197 | * | |
1198 | * Input: | |
1199 | * ha = adapter block pointer. | |
1200 | * | |
1201 | * Returns: | |
1202 | * 0 = success | |
1203 | */ | |
a4722cf2 | 1204 | int |
e315cd28 | 1205 | qla2x00_loop_reset(scsi_qla_host_t *vha) |
1da177e4 | 1206 | { |
0c8c39af | 1207 | int ret; |
bdf79621 | 1208 | struct fc_port *fcport; |
e315cd28 | 1209 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 1210 | |
f4c496c1 | 1211 | if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { |
55e5ed27 AV |
1212 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1213 | if (fcport->port_type != FCT_TARGET) | |
1214 | continue; | |
1215 | ||
1216 | ret = ha->isp_ops->target_reset(fcport, 0, 0); | |
1217 | if (ret != QLA_SUCCESS) { | |
7c3df132 SK |
1218 | ql_dbg(ql_dbg_taskm, vha, 0x802c, |
1219 | "Bus Reset failed: Target Reset=%d " | |
1220 | "d_id=%x.\n", ret, fcport->d_id.b24); | |
55e5ed27 AV |
1221 | } |
1222 | } | |
1223 | } | |
1224 | ||
a9083016 | 1225 | if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) { |
e315cd28 | 1226 | ret = qla2x00_full_login_lip(vha); |
0c8c39af | 1227 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
1228 | ql_dbg(ql_dbg_taskm, vha, 0x802d, |
1229 | "full_login_lip=%d.\n", ret); | |
749af3d5 AC |
1230 | } |
1231 | atomic_set(&vha->loop_state, LOOP_DOWN); | |
1232 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
1233 | qla2x00_mark_all_devices_lost(vha, 0); | |
0c8c39af AV |
1234 | } |
1235 | ||
0d6e61bc | 1236 | if (ha->flags.enable_lip_reset) { |
e315cd28 | 1237 | ret = qla2x00_lip_reset(vha); |
ad537689 | 1238 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
1239 | ql_dbg(ql_dbg_taskm, vha, 0x802e, |
1240 | "lip_reset failed (%d).\n", ret); | |
1da177e4 LT |
1241 | } |
1242 | ||
1da177e4 | 1243 | /* Issue marker command only when we are going to start the I/O */ |
e315cd28 | 1244 | vha->marker_needed = 1; |
1da177e4 | 1245 | |
0c8c39af | 1246 | return QLA_SUCCESS; |
1da177e4 LT |
1247 | } |
1248 | ||
df4bf0bb | 1249 | void |
e315cd28 | 1250 | qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) |
df4bf0bb | 1251 | { |
73208dfd | 1252 | int que, cnt; |
df4bf0bb AV |
1253 | unsigned long flags; |
1254 | srb_t *sp; | |
ac280b67 | 1255 | struct srb_ctx *ctx; |
e315cd28 | 1256 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1257 | struct req_que *req; |
df4bf0bb AV |
1258 | |
1259 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
2afa19a9 | 1260 | for (que = 0; que < ha->max_req_queues; que++) { |
29bdccbe | 1261 | req = ha->req_q_map[que]; |
73208dfd AC |
1262 | if (!req) |
1263 | continue; | |
1264 | for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { | |
1265 | sp = req->outstanding_cmds[cnt]; | |
e612d465 | 1266 | if (sp) { |
73208dfd | 1267 | req->outstanding_cmds[cnt] = NULL; |
a9083016 | 1268 | if (!sp->ctx || |
bad75002 AE |
1269 | (sp->flags & SRB_FCP_CMND_DMA_VALID) || |
1270 | IS_PROT_IO(sp)) { | |
ac280b67 AV |
1271 | sp->cmd->result = res; |
1272 | qla2x00_sp_compl(ha, sp); | |
1273 | } else { | |
1274 | ctx = sp->ctx; | |
9bfacd01 RD |
1275 | if (ctx->type == SRB_ELS_CMD_RPT || |
1276 | ctx->type == SRB_ELS_CMD_HST || | |
1277 | ctx->type == SRB_CT_CMD) { | |
6c452a45 | 1278 | struct fc_bsg_job *bsg_job = |
4916392b | 1279 | ctx->u.bsg_job; |
6c452a45 AV |
1280 | if (bsg_job->request->msgcode |
1281 | == FC_BSG_HST_CT) | |
db3ad7f8 | 1282 | kfree(sp->fcport); |
6c452a45 AV |
1283 | bsg_job->req->errors = 0; |
1284 | bsg_job->reply->result = res; | |
4916392b | 1285 | bsg_job->job_done(bsg_job); |
db3ad7f8 | 1286 | kfree(sp->ctx); |
6c452a45 | 1287 | mempool_free(sp, |
4916392b | 1288 | ha->srb_mempool); |
9bfacd01 RD |
1289 | } else { |
1290 | ctx->u.iocb_cmd->free(sp); | |
db3ad7f8 | 1291 | } |
ac280b67 | 1292 | } |
73208dfd | 1293 | } |
df4bf0bb AV |
1294 | } |
1295 | } | |
1296 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1297 | } | |
1298 | ||
f4f051eb AV |
1299 | static int |
1300 | qla2xxx_slave_alloc(struct scsi_device *sdev) | |
1da177e4 | 1301 | { |
bdf79621 | 1302 | struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); |
1da177e4 | 1303 | |
19a7b4ae | 1304 | if (!rport || fc_remote_port_chkready(rport)) |
f4f051eb | 1305 | return -ENXIO; |
bdf79621 | 1306 | |
19a7b4ae | 1307 | sdev->hostdata = *(fc_port_t **)rport->dd_data; |
1da177e4 | 1308 | |
f4f051eb AV |
1309 | return 0; |
1310 | } | |
1da177e4 | 1311 | |
f4f051eb AV |
1312 | static int |
1313 | qla2xxx_slave_configure(struct scsi_device *sdev) | |
1314 | { | |
e315cd28 | 1315 | scsi_qla_host_t *vha = shost_priv(sdev->host); |
2afa19a9 | 1316 | struct req_que *req = vha->req; |
8482e118 | 1317 | |
f4f051eb | 1318 | if (sdev->tagged_supported) |
73208dfd | 1319 | scsi_activate_tcq(sdev, req->max_q_depth); |
f4f051eb | 1320 | else |
73208dfd | 1321 | scsi_deactivate_tcq(sdev, req->max_q_depth); |
f4f051eb AV |
1322 | return 0; |
1323 | } | |
1da177e4 | 1324 | |
f4f051eb AV |
1325 | static void |
1326 | qla2xxx_slave_destroy(struct scsi_device *sdev) | |
1327 | { | |
1328 | sdev->hostdata = NULL; | |
1da177e4 LT |
1329 | } |
1330 | ||
c45dd305 GM |
1331 | static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth) |
1332 | { | |
1333 | fc_port_t *fcport = (struct fc_port *) sdev->hostdata; | |
1334 | ||
1335 | if (!scsi_track_queue_full(sdev, qdepth)) | |
1336 | return; | |
1337 | ||
7c3df132 | 1338 | ql_dbg(ql_dbg_io, fcport->vha, 0x3029, |
cfb0919c CD |
1339 | "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n", |
1340 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); | |
c45dd305 GM |
1341 | } |
1342 | ||
1343 | static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth) | |
1344 | { | |
1345 | fc_port_t *fcport = sdev->hostdata; | |
1346 | struct scsi_qla_host *vha = fcport->vha; | |
c45dd305 GM |
1347 | struct req_que *req = NULL; |
1348 | ||
1349 | req = vha->req; | |
1350 | if (!req) | |
1351 | return; | |
1352 | ||
1353 | if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth) | |
1354 | return; | |
1355 | ||
1356 | if (sdev->ordered_tags) | |
1357 | scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth); | |
1358 | else | |
1359 | scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth); | |
1360 | ||
7c3df132 | 1361 | ql_dbg(ql_dbg_io, vha, 0x302a, |
cfb0919c CD |
1362 | "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n", |
1363 | sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun); | |
c45dd305 GM |
1364 | } |
1365 | ||
ce7e4af7 | 1366 | static int |
e881a172 | 1367 | qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason) |
ce7e4af7 | 1368 | { |
c45dd305 GM |
1369 | switch (reason) { |
1370 | case SCSI_QDEPTH_DEFAULT: | |
1371 | scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); | |
1372 | break; | |
1373 | case SCSI_QDEPTH_QFULL: | |
1374 | qla2x00_handle_queue_full(sdev, qdepth); | |
1375 | break; | |
1376 | case SCSI_QDEPTH_RAMP_UP: | |
1377 | qla2x00_adjust_sdev_qdepth_up(sdev, qdepth); | |
1378 | break; | |
1379 | default: | |
08002af2 | 1380 | return -EOPNOTSUPP; |
c45dd305 | 1381 | } |
e881a172 | 1382 | |
ce7e4af7 AV |
1383 | return sdev->queue_depth; |
1384 | } | |
1385 | ||
1386 | static int | |
1387 | qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type) | |
1388 | { | |
1389 | if (sdev->tagged_supported) { | |
1390 | scsi_set_tag_type(sdev, tag_type); | |
1391 | if (tag_type) | |
1392 | scsi_activate_tcq(sdev, sdev->queue_depth); | |
1393 | else | |
1394 | scsi_deactivate_tcq(sdev, sdev->queue_depth); | |
1395 | } else | |
1396 | tag_type = 0; | |
1397 | ||
1398 | return tag_type; | |
1399 | } | |
1400 | ||
1da177e4 LT |
1401 | /** |
1402 | * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. | |
1403 | * @ha: HA context | |
1404 | * | |
1405 | * At exit, the @ha's flags.enable_64bit_addressing set to indicated | |
1406 | * supported addressing method. | |
1407 | */ | |
1408 | static void | |
53303c42 | 1409 | qla2x00_config_dma_addressing(struct qla_hw_data *ha) |
1da177e4 | 1410 | { |
7524f9b9 | 1411 | /* Assume a 32bit DMA mask. */ |
1da177e4 | 1412 | ha->flags.enable_64bit_addressing = 0; |
1da177e4 | 1413 | |
6a35528a | 1414 | if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { |
7524f9b9 AV |
1415 | /* Any upper-dword bits set? */ |
1416 | if (MSD(dma_get_required_mask(&ha->pdev->dev)) && | |
6a35528a | 1417 | !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { |
7524f9b9 | 1418 | /* Ok, a 64bit DMA mask is applicable. */ |
1da177e4 | 1419 | ha->flags.enable_64bit_addressing = 1; |
fd34f556 AV |
1420 | ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; |
1421 | ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; | |
7524f9b9 | 1422 | return; |
1da177e4 | 1423 | } |
1da177e4 | 1424 | } |
7524f9b9 | 1425 | |
284901a9 YH |
1426 | dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); |
1427 | pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); | |
1da177e4 LT |
1428 | } |
1429 | ||
fd34f556 | 1430 | static void |
e315cd28 | 1431 | qla2x00_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1432 | { |
1433 | unsigned long flags = 0; | |
1434 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1435 | ||
1436 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1437 | ha->interrupts_on = 1; | |
1438 | /* enable risc and host interrupts */ | |
1439 | WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); | |
1440 | RD_REG_WORD(®->ictrl); | |
1441 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1442 | ||
1443 | } | |
1444 | ||
1445 | static void | |
e315cd28 | 1446 | qla2x00_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1447 | { |
1448 | unsigned long flags = 0; | |
1449 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1450 | ||
1451 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1452 | ha->interrupts_on = 0; | |
1453 | /* disable risc and host interrupts */ | |
1454 | WRT_REG_WORD(®->ictrl, 0); | |
1455 | RD_REG_WORD(®->ictrl); | |
1456 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1457 | } | |
1458 | ||
1459 | static void | |
e315cd28 | 1460 | qla24xx_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1461 | { |
1462 | unsigned long flags = 0; | |
1463 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1464 | ||
1465 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1466 | ha->interrupts_on = 1; | |
1467 | WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); | |
1468 | RD_REG_DWORD(®->ictrl); | |
1469 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1470 | } | |
1471 | ||
1472 | static void | |
e315cd28 | 1473 | qla24xx_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1474 | { |
1475 | unsigned long flags = 0; | |
1476 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1477 | ||
124f85e6 AV |
1478 | if (IS_NOPOLLING_TYPE(ha)) |
1479 | return; | |
fd34f556 AV |
1480 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1481 | ha->interrupts_on = 0; | |
1482 | WRT_REG_DWORD(®->ictrl, 0); | |
1483 | RD_REG_DWORD(®->ictrl); | |
1484 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1485 | } | |
1486 | ||
1487 | static struct isp_operations qla2100_isp_ops = { | |
1488 | .pci_config = qla2100_pci_config, | |
1489 | .reset_chip = qla2x00_reset_chip, | |
1490 | .chip_diag = qla2x00_chip_diag, | |
1491 | .config_rings = qla2x00_config_rings, | |
1492 | .reset_adapter = qla2x00_reset_adapter, | |
1493 | .nvram_config = qla2x00_nvram_config, | |
1494 | .update_fw_options = qla2x00_update_fw_options, | |
1495 | .load_risc = qla2x00_load_risc, | |
1496 | .pci_info_str = qla2x00_pci_info_str, | |
1497 | .fw_version_str = qla2x00_fw_version_str, | |
1498 | .intr_handler = qla2100_intr_handler, | |
1499 | .enable_intrs = qla2x00_enable_intrs, | |
1500 | .disable_intrs = qla2x00_disable_intrs, | |
1501 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1502 | .target_reset = qla2x00_abort_target, |
1503 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1504 | .fabric_login = qla2x00_login_fabric, |
1505 | .fabric_logout = qla2x00_fabric_logout, | |
1506 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1507 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1508 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1509 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1510 | .read_nvram = qla2x00_read_nvram_data, | |
1511 | .write_nvram = qla2x00_write_nvram_data, | |
1512 | .fw_dump = qla2100_fw_dump, | |
1513 | .beacon_on = NULL, | |
1514 | .beacon_off = NULL, | |
1515 | .beacon_blink = NULL, | |
1516 | .read_optrom = qla2x00_read_optrom_data, | |
1517 | .write_optrom = qla2x00_write_optrom_data, | |
1518 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1519 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1520 | .abort_isp = qla2x00_abort_isp, |
fd34f556 AV |
1521 | }; |
1522 | ||
1523 | static struct isp_operations qla2300_isp_ops = { | |
1524 | .pci_config = qla2300_pci_config, | |
1525 | .reset_chip = qla2x00_reset_chip, | |
1526 | .chip_diag = qla2x00_chip_diag, | |
1527 | .config_rings = qla2x00_config_rings, | |
1528 | .reset_adapter = qla2x00_reset_adapter, | |
1529 | .nvram_config = qla2x00_nvram_config, | |
1530 | .update_fw_options = qla2x00_update_fw_options, | |
1531 | .load_risc = qla2x00_load_risc, | |
1532 | .pci_info_str = qla2x00_pci_info_str, | |
1533 | .fw_version_str = qla2x00_fw_version_str, | |
1534 | .intr_handler = qla2300_intr_handler, | |
1535 | .enable_intrs = qla2x00_enable_intrs, | |
1536 | .disable_intrs = qla2x00_disable_intrs, | |
1537 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1538 | .target_reset = qla2x00_abort_target, |
1539 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1540 | .fabric_login = qla2x00_login_fabric, |
1541 | .fabric_logout = qla2x00_fabric_logout, | |
1542 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1543 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1544 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1545 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1546 | .read_nvram = qla2x00_read_nvram_data, | |
1547 | .write_nvram = qla2x00_write_nvram_data, | |
1548 | .fw_dump = qla2300_fw_dump, | |
1549 | .beacon_on = qla2x00_beacon_on, | |
1550 | .beacon_off = qla2x00_beacon_off, | |
1551 | .beacon_blink = qla2x00_beacon_blink, | |
1552 | .read_optrom = qla2x00_read_optrom_data, | |
1553 | .write_optrom = qla2x00_write_optrom_data, | |
1554 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1555 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1556 | .abort_isp = qla2x00_abort_isp, |
fd34f556 AV |
1557 | }; |
1558 | ||
1559 | static struct isp_operations qla24xx_isp_ops = { | |
1560 | .pci_config = qla24xx_pci_config, | |
1561 | .reset_chip = qla24xx_reset_chip, | |
1562 | .chip_diag = qla24xx_chip_diag, | |
1563 | .config_rings = qla24xx_config_rings, | |
1564 | .reset_adapter = qla24xx_reset_adapter, | |
1565 | .nvram_config = qla24xx_nvram_config, | |
1566 | .update_fw_options = qla24xx_update_fw_options, | |
1567 | .load_risc = qla24xx_load_risc, | |
1568 | .pci_info_str = qla24xx_pci_info_str, | |
1569 | .fw_version_str = qla24xx_fw_version_str, | |
1570 | .intr_handler = qla24xx_intr_handler, | |
1571 | .enable_intrs = qla24xx_enable_intrs, | |
1572 | .disable_intrs = qla24xx_disable_intrs, | |
1573 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1574 | .target_reset = qla24xx_abort_target, |
1575 | .lun_reset = qla24xx_lun_reset, | |
fd34f556 AV |
1576 | .fabric_login = qla24xx_login_fabric, |
1577 | .fabric_logout = qla24xx_fabric_logout, | |
1578 | .calc_req_entries = NULL, | |
1579 | .build_iocbs = NULL, | |
1580 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1581 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1582 | .read_nvram = qla24xx_read_nvram_data, | |
1583 | .write_nvram = qla24xx_write_nvram_data, | |
1584 | .fw_dump = qla24xx_fw_dump, | |
1585 | .beacon_on = qla24xx_beacon_on, | |
1586 | .beacon_off = qla24xx_beacon_off, | |
1587 | .beacon_blink = qla24xx_beacon_blink, | |
1588 | .read_optrom = qla24xx_read_optrom_data, | |
1589 | .write_optrom = qla24xx_write_optrom_data, | |
1590 | .get_flash_version = qla24xx_get_flash_version, | |
e315cd28 | 1591 | .start_scsi = qla24xx_start_scsi, |
a9083016 | 1592 | .abort_isp = qla2x00_abort_isp, |
fd34f556 AV |
1593 | }; |
1594 | ||
c3a2f0df AV |
1595 | static struct isp_operations qla25xx_isp_ops = { |
1596 | .pci_config = qla25xx_pci_config, | |
1597 | .reset_chip = qla24xx_reset_chip, | |
1598 | .chip_diag = qla24xx_chip_diag, | |
1599 | .config_rings = qla24xx_config_rings, | |
1600 | .reset_adapter = qla24xx_reset_adapter, | |
1601 | .nvram_config = qla24xx_nvram_config, | |
1602 | .update_fw_options = qla24xx_update_fw_options, | |
1603 | .load_risc = qla24xx_load_risc, | |
1604 | .pci_info_str = qla24xx_pci_info_str, | |
1605 | .fw_version_str = qla24xx_fw_version_str, | |
1606 | .intr_handler = qla24xx_intr_handler, | |
1607 | .enable_intrs = qla24xx_enable_intrs, | |
1608 | .disable_intrs = qla24xx_disable_intrs, | |
1609 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1610 | .target_reset = qla24xx_abort_target, |
1611 | .lun_reset = qla24xx_lun_reset, | |
c3a2f0df AV |
1612 | .fabric_login = qla24xx_login_fabric, |
1613 | .fabric_logout = qla24xx_fabric_logout, | |
1614 | .calc_req_entries = NULL, | |
1615 | .build_iocbs = NULL, | |
1616 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1617 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1618 | .read_nvram = qla25xx_read_nvram_data, | |
1619 | .write_nvram = qla25xx_write_nvram_data, | |
1620 | .fw_dump = qla25xx_fw_dump, | |
1621 | .beacon_on = qla24xx_beacon_on, | |
1622 | .beacon_off = qla24xx_beacon_off, | |
1623 | .beacon_blink = qla24xx_beacon_blink, | |
338c9161 | 1624 | .read_optrom = qla25xx_read_optrom_data, |
c3a2f0df AV |
1625 | .write_optrom = qla24xx_write_optrom_data, |
1626 | .get_flash_version = qla24xx_get_flash_version, | |
bad75002 | 1627 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 | 1628 | .abort_isp = qla2x00_abort_isp, |
c3a2f0df AV |
1629 | }; |
1630 | ||
3a03eb79 AV |
1631 | static struct isp_operations qla81xx_isp_ops = { |
1632 | .pci_config = qla25xx_pci_config, | |
1633 | .reset_chip = qla24xx_reset_chip, | |
1634 | .chip_diag = qla24xx_chip_diag, | |
1635 | .config_rings = qla24xx_config_rings, | |
1636 | .reset_adapter = qla24xx_reset_adapter, | |
1637 | .nvram_config = qla81xx_nvram_config, | |
1638 | .update_fw_options = qla81xx_update_fw_options, | |
eaac30be | 1639 | .load_risc = qla81xx_load_risc, |
3a03eb79 AV |
1640 | .pci_info_str = qla24xx_pci_info_str, |
1641 | .fw_version_str = qla24xx_fw_version_str, | |
1642 | .intr_handler = qla24xx_intr_handler, | |
1643 | .enable_intrs = qla24xx_enable_intrs, | |
1644 | .disable_intrs = qla24xx_disable_intrs, | |
1645 | .abort_command = qla24xx_abort_command, | |
1646 | .target_reset = qla24xx_abort_target, | |
1647 | .lun_reset = qla24xx_lun_reset, | |
1648 | .fabric_login = qla24xx_login_fabric, | |
1649 | .fabric_logout = qla24xx_fabric_logout, | |
1650 | .calc_req_entries = NULL, | |
1651 | .build_iocbs = NULL, | |
1652 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1653 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
3d79038f AV |
1654 | .read_nvram = NULL, |
1655 | .write_nvram = NULL, | |
3a03eb79 AV |
1656 | .fw_dump = qla81xx_fw_dump, |
1657 | .beacon_on = qla24xx_beacon_on, | |
1658 | .beacon_off = qla24xx_beacon_off, | |
1659 | .beacon_blink = qla24xx_beacon_blink, | |
1660 | .read_optrom = qla25xx_read_optrom_data, | |
1661 | .write_optrom = qla24xx_write_optrom_data, | |
1662 | .get_flash_version = qla24xx_get_flash_version, | |
ba77ef53 | 1663 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 GM |
1664 | .abort_isp = qla2x00_abort_isp, |
1665 | }; | |
1666 | ||
1667 | static struct isp_operations qla82xx_isp_ops = { | |
1668 | .pci_config = qla82xx_pci_config, | |
1669 | .reset_chip = qla82xx_reset_chip, | |
1670 | .chip_diag = qla24xx_chip_diag, | |
1671 | .config_rings = qla82xx_config_rings, | |
1672 | .reset_adapter = qla24xx_reset_adapter, | |
1673 | .nvram_config = qla81xx_nvram_config, | |
1674 | .update_fw_options = qla24xx_update_fw_options, | |
1675 | .load_risc = qla82xx_load_risc, | |
1676 | .pci_info_str = qla82xx_pci_info_str, | |
1677 | .fw_version_str = qla24xx_fw_version_str, | |
1678 | .intr_handler = qla82xx_intr_handler, | |
1679 | .enable_intrs = qla82xx_enable_intrs, | |
1680 | .disable_intrs = qla82xx_disable_intrs, | |
1681 | .abort_command = qla24xx_abort_command, | |
1682 | .target_reset = qla24xx_abort_target, | |
1683 | .lun_reset = qla24xx_lun_reset, | |
1684 | .fabric_login = qla24xx_login_fabric, | |
1685 | .fabric_logout = qla24xx_fabric_logout, | |
1686 | .calc_req_entries = NULL, | |
1687 | .build_iocbs = NULL, | |
1688 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1689 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1690 | .read_nvram = qla24xx_read_nvram_data, | |
1691 | .write_nvram = qla24xx_write_nvram_data, | |
1692 | .fw_dump = qla24xx_fw_dump, | |
999916dc SK |
1693 | .beacon_on = qla82xx_beacon_on, |
1694 | .beacon_off = qla82xx_beacon_off, | |
1695 | .beacon_blink = NULL, | |
a9083016 GM |
1696 | .read_optrom = qla82xx_read_optrom_data, |
1697 | .write_optrom = qla82xx_write_optrom_data, | |
1698 | .get_flash_version = qla24xx_get_flash_version, | |
1699 | .start_scsi = qla82xx_start_scsi, | |
1700 | .abort_isp = qla82xx_abort_isp, | |
3a03eb79 AV |
1701 | }; |
1702 | ||
ea5b6382 | 1703 | static inline void |
e315cd28 | 1704 | qla2x00_set_isp_flags(struct qla_hw_data *ha) |
ea5b6382 AV |
1705 | { |
1706 | ha->device_type = DT_EXTENDED_IDS; | |
1707 | switch (ha->pdev->device) { | |
1708 | case PCI_DEVICE_ID_QLOGIC_ISP2100: | |
1709 | ha->device_type |= DT_ISP2100; | |
1710 | ha->device_type &= ~DT_EXTENDED_IDS; | |
441d1072 | 1711 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 AV |
1712 | break; |
1713 | case PCI_DEVICE_ID_QLOGIC_ISP2200: | |
1714 | ha->device_type |= DT_ISP2200; | |
1715 | ha->device_type &= ~DT_EXTENDED_IDS; | |
441d1072 | 1716 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 AV |
1717 | break; |
1718 | case PCI_DEVICE_ID_QLOGIC_ISP2300: | |
1719 | ha->device_type |= DT_ISP2300; | |
4a59f71d | 1720 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 1721 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
1722 | break; |
1723 | case PCI_DEVICE_ID_QLOGIC_ISP2312: | |
1724 | ha->device_type |= DT_ISP2312; | |
4a59f71d | 1725 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 1726 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
1727 | break; |
1728 | case PCI_DEVICE_ID_QLOGIC_ISP2322: | |
1729 | ha->device_type |= DT_ISP2322; | |
4a59f71d | 1730 | ha->device_type |= DT_ZIO_SUPPORTED; |
ea5b6382 AV |
1731 | if (ha->pdev->subsystem_vendor == 0x1028 && |
1732 | ha->pdev->subsystem_device == 0x0170) | |
1733 | ha->device_type |= DT_OEM_001; | |
441d1072 | 1734 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
1735 | break; |
1736 | case PCI_DEVICE_ID_QLOGIC_ISP6312: | |
1737 | ha->device_type |= DT_ISP6312; | |
441d1072 | 1738 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
1739 | break; |
1740 | case PCI_DEVICE_ID_QLOGIC_ISP6322: | |
1741 | ha->device_type |= DT_ISP6322; | |
441d1072 | 1742 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
1743 | break; |
1744 | case PCI_DEVICE_ID_QLOGIC_ISP2422: | |
1745 | ha->device_type |= DT_ISP2422; | |
4a59f71d | 1746 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 1747 | ha->device_type |= DT_FWI2; |
c76f2c01 | 1748 | ha->device_type |= DT_IIDMA; |
441d1072 | 1749 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 AV |
1750 | break; |
1751 | case PCI_DEVICE_ID_QLOGIC_ISP2432: | |
1752 | ha->device_type |= DT_ISP2432; | |
4a59f71d | 1753 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 1754 | ha->device_type |= DT_FWI2; |
c76f2c01 | 1755 | ha->device_type |= DT_IIDMA; |
441d1072 | 1756 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 1757 | break; |
4d4df193 HK |
1758 | case PCI_DEVICE_ID_QLOGIC_ISP8432: |
1759 | ha->device_type |= DT_ISP8432; | |
1760 | ha->device_type |= DT_ZIO_SUPPORTED; | |
1761 | ha->device_type |= DT_FWI2; | |
1762 | ha->device_type |= DT_IIDMA; | |
1763 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
1764 | break; | |
044cc6c8 AV |
1765 | case PCI_DEVICE_ID_QLOGIC_ISP5422: |
1766 | ha->device_type |= DT_ISP5422; | |
e428924c | 1767 | ha->device_type |= DT_FWI2; |
441d1072 | 1768 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 1769 | break; |
044cc6c8 AV |
1770 | case PCI_DEVICE_ID_QLOGIC_ISP5432: |
1771 | ha->device_type |= DT_ISP5432; | |
e428924c | 1772 | ha->device_type |= DT_FWI2; |
441d1072 | 1773 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 1774 | break; |
c3a2f0df AV |
1775 | case PCI_DEVICE_ID_QLOGIC_ISP2532: |
1776 | ha->device_type |= DT_ISP2532; | |
1777 | ha->device_type |= DT_ZIO_SUPPORTED; | |
1778 | ha->device_type |= DT_FWI2; | |
1779 | ha->device_type |= DT_IIDMA; | |
441d1072 | 1780 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 1781 | break; |
3a03eb79 AV |
1782 | case PCI_DEVICE_ID_QLOGIC_ISP8001: |
1783 | ha->device_type |= DT_ISP8001; | |
1784 | ha->device_type |= DT_ZIO_SUPPORTED; | |
1785 | ha->device_type |= DT_FWI2; | |
1786 | ha->device_type |= DT_IIDMA; | |
1787 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
1788 | break; | |
a9083016 GM |
1789 | case PCI_DEVICE_ID_QLOGIC_ISP8021: |
1790 | ha->device_type |= DT_ISP8021; | |
1791 | ha->device_type |= DT_ZIO_SUPPORTED; | |
1792 | ha->device_type |= DT_FWI2; | |
1793 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
1794 | /* Initialize 82XX ISP flags */ | |
1795 | qla82xx_init_flags(ha); | |
1796 | break; | |
ea5b6382 | 1797 | } |
e5b68a61 | 1798 | |
a9083016 GM |
1799 | if (IS_QLA82XX(ha)) |
1800 | ha->port_no = !(ha->portnum & 1); | |
1801 | else | |
1802 | /* Get adapter physical port no from interrupt pin register. */ | |
1803 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); | |
1804 | ||
e5b68a61 AC |
1805 | if (ha->port_no & 1) |
1806 | ha->flags.port0 = 1; | |
1807 | else | |
1808 | ha->flags.port0 = 0; | |
7c3df132 | 1809 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, |
d8424f68 | 1810 | "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", |
7c3df132 | 1811 | ha->device_type, ha->flags.port0, ha->fw_srisc_address); |
ea5b6382 AV |
1812 | } |
1813 | ||
1da177e4 | 1814 | static int |
e315cd28 | 1815 | qla2x00_iospace_config(struct qla_hw_data *ha) |
1da177e4 | 1816 | { |
3776541d | 1817 | resource_size_t pio; |
73208dfd | 1818 | uint16_t msix; |
68ca949c | 1819 | int cpus; |
1da177e4 | 1820 | |
a9083016 GM |
1821 | if (IS_QLA82XX(ha)) |
1822 | return qla82xx_iospace_config(ha); | |
1823 | ||
285d0321 AV |
1824 | if (pci_request_selected_regions(ha->pdev, ha->bars, |
1825 | QLA2XXX_DRIVER_NAME)) { | |
7c3df132 SK |
1826 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, |
1827 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
285d0321 | 1828 | pci_name(ha->pdev)); |
285d0321 AV |
1829 | goto iospace_error_exit; |
1830 | } | |
1831 | if (!(ha->bars & 1)) | |
1832 | goto skip_pio; | |
1833 | ||
1da177e4 LT |
1834 | /* We only need PIO for Flash operations on ISP2312 v2 chips. */ |
1835 | pio = pci_resource_start(ha->pdev, 0); | |
3776541d AV |
1836 | if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { |
1837 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
7c3df132 SK |
1838 | ql_log_pci(ql_log_warn, ha->pdev, 0x0012, |
1839 | "Invalid pci I/O region size (%s).\n", | |
1840 | pci_name(ha->pdev)); | |
1da177e4 LT |
1841 | pio = 0; |
1842 | } | |
1843 | } else { | |
7c3df132 SK |
1844 | ql_log_pci(ql_log_warn, ha->pdev, 0x0013, |
1845 | "Region #0 no a PIO resource (%s).\n", | |
1da177e4 LT |
1846 | pci_name(ha->pdev)); |
1847 | pio = 0; | |
1848 | } | |
285d0321 | 1849 | ha->pio_address = pio; |
7c3df132 | 1850 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, |
d8424f68 JP |
1851 | "PIO address=%llu.\n", |
1852 | (unsigned long long)ha->pio_address); | |
1da177e4 | 1853 | |
285d0321 | 1854 | skip_pio: |
1da177e4 | 1855 | /* Use MMIO operations for all accesses. */ |
3776541d | 1856 | if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { |
7c3df132 SK |
1857 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, |
1858 | "Region #1 not an MMIO resource (%s), aborting.\n", | |
1da177e4 LT |
1859 | pci_name(ha->pdev)); |
1860 | goto iospace_error_exit; | |
1861 | } | |
3776541d | 1862 | if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { |
7c3df132 SK |
1863 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, |
1864 | "Invalid PCI mem region size (%s), aborting.\n", | |
1865 | pci_name(ha->pdev)); | |
1da177e4 LT |
1866 | goto iospace_error_exit; |
1867 | } | |
1868 | ||
3776541d | 1869 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); |
1da177e4 | 1870 | if (!ha->iobase) { |
7c3df132 SK |
1871 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, |
1872 | "Cannot remap MMIO (%s), aborting.\n", | |
1873 | pci_name(ha->pdev)); | |
1da177e4 LT |
1874 | goto iospace_error_exit; |
1875 | } | |
1876 | ||
73208dfd | 1877 | /* Determine queue resources */ |
2afa19a9 | 1878 | ha->max_req_queues = ha->max_rsp_queues = 1; |
d84a47c2 MH |
1879 | if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || |
1880 | (ql2xmaxqueues > 1 && ql2xmultique_tag) || | |
2afa19a9 | 1881 | (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) |
17d98630 | 1882 | goto mqiobase_exit; |
d84a47c2 | 1883 | |
17d98630 AC |
1884 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), |
1885 | pci_resource_len(ha->pdev, 3)); | |
1886 | if (ha->mqiobase) { | |
7c3df132 SK |
1887 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, |
1888 | "MQIO Base=%p.\n", ha->mqiobase); | |
17d98630 AC |
1889 | /* Read MSIX vector size of the board */ |
1890 | pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); | |
1891 | ha->msix_count = msix; | |
68ca949c AC |
1892 | /* Max queues are bounded by available msix vectors */ |
1893 | /* queue 0 uses two msix vectors */ | |
1894 | if (ql2xmultique_tag) { | |
1895 | cpus = num_online_cpus(); | |
27dc9c5a | 1896 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? |
68ca949c AC |
1897 | (cpus + 1) : (ha->msix_count - 1); |
1898 | ha->max_req_queues = 2; | |
1899 | } else if (ql2xmaxqueues > 1) { | |
2afa19a9 | 1900 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? |
7c3df132 SK |
1901 | QLA_MQ_SIZE : ql2xmaxqueues; |
1902 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, | |
1903 | "QoS mode set, max no of request queues:%d.\n", | |
1904 | ha->max_req_queues); | |
1905 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, | |
1906 | "QoS mode set, max no of request queues:%d.\n", | |
1907 | ha->max_req_queues); | |
2afa19a9 | 1908 | } |
7c3df132 SK |
1909 | ql_log_pci(ql_log_info, ha->pdev, 0x001a, |
1910 | "MSI-X vector count: %d.\n", msix); | |
2afa19a9 | 1911 | } else |
7c3df132 SK |
1912 | ql_log_pci(ql_log_info, ha->pdev, 0x001b, |
1913 | "BAR 3 not enabled.\n"); | |
17d98630 AC |
1914 | |
1915 | mqiobase_exit: | |
2afa19a9 | 1916 | ha->msix_count = ha->max_rsp_queues + 1; |
7c3df132 SK |
1917 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, |
1918 | "MSIX Count:%d.\n", ha->msix_count); | |
1da177e4 LT |
1919 | return (0); |
1920 | ||
1921 | iospace_error_exit: | |
1922 | return (-ENOMEM); | |
1923 | } | |
1924 | ||
1e99e33a AV |
1925 | static void |
1926 | qla2xxx_scan_start(struct Scsi_Host *shost) | |
1927 | { | |
e315cd28 | 1928 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 1929 | |
cbc8eb67 AV |
1930 | if (vha->hw->flags.running_gold_fw) |
1931 | return; | |
1932 | ||
e315cd28 AC |
1933 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
1934 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
1935 | set_bit(RSCN_UPDATE, &vha->dpc_flags); | |
1936 | set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); | |
1e99e33a AV |
1937 | } |
1938 | ||
1939 | static int | |
1940 | qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) | |
1941 | { | |
e315cd28 | 1942 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 1943 | |
e315cd28 | 1944 | if (!vha->host) |
1e99e33a | 1945 | return 1; |
e315cd28 | 1946 | if (time > vha->hw->loop_reset_delay * HZ) |
1e99e33a AV |
1947 | return 1; |
1948 | ||
e315cd28 | 1949 | return atomic_read(&vha->loop_state) == LOOP_READY; |
1e99e33a AV |
1950 | } |
1951 | ||
1da177e4 LT |
1952 | /* |
1953 | * PCI driver interface | |
1954 | */ | |
7ee61397 AV |
1955 | static int __devinit |
1956 | qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
1da177e4 | 1957 | { |
a1541d5a | 1958 | int ret = -ENODEV; |
1da177e4 | 1959 | struct Scsi_Host *host; |
e315cd28 AC |
1960 | scsi_qla_host_t *base_vha = NULL; |
1961 | struct qla_hw_data *ha; | |
29856e28 | 1962 | char pci_info[30]; |
1da177e4 | 1963 | char fw_str[30]; |
5433383e | 1964 | struct scsi_host_template *sht; |
c51da4ec | 1965 | int bars, max_id, mem_only = 0; |
e315cd28 | 1966 | uint16_t req_length = 0, rsp_length = 0; |
73208dfd AC |
1967 | struct req_que *req = NULL; |
1968 | struct rsp_que *rsp = NULL; | |
1da177e4 | 1969 | |
285d0321 | 1970 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); |
a5326f86 | 1971 | sht = &qla2xxx_driver_template; |
5433383e | 1972 | if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || |
8bc69e7d | 1973 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || |
4d4df193 | 1974 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || |
8bc69e7d | 1975 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || |
c3a2f0df | 1976 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || |
3a03eb79 | 1977 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || |
a9083016 GM |
1978 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || |
1979 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) { | |
285d0321 | 1980 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
09483916 | 1981 | mem_only = 1; |
7c3df132 SK |
1982 | ql_dbg_pci(ql_dbg_init, pdev, 0x0007, |
1983 | "Mem only adapter.\n"); | |
285d0321 | 1984 | } |
7c3df132 SK |
1985 | ql_dbg_pci(ql_dbg_init, pdev, 0x0008, |
1986 | "Bars=%d.\n", bars); | |
285d0321 | 1987 | |
09483916 BH |
1988 | if (mem_only) { |
1989 | if (pci_enable_device_mem(pdev)) | |
1990 | goto probe_out; | |
1991 | } else { | |
1992 | if (pci_enable_device(pdev)) | |
1993 | goto probe_out; | |
1994 | } | |
285d0321 | 1995 | |
0927678f JB |
1996 | /* This may fail but that's ok */ |
1997 | pci_enable_pcie_error_reporting(pdev); | |
285d0321 | 1998 | |
e315cd28 AC |
1999 | ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); |
2000 | if (!ha) { | |
7c3df132 SK |
2001 | ql_log_pci(ql_log_fatal, pdev, 0x0009, |
2002 | "Unable to allocate memory for ha.\n"); | |
e315cd28 | 2003 | goto probe_out; |
1da177e4 | 2004 | } |
7c3df132 SK |
2005 | ql_dbg_pci(ql_dbg_init, pdev, 0x000a, |
2006 | "Memory allocated for ha=%p.\n", ha); | |
e315cd28 | 2007 | ha->pdev = pdev; |
1da177e4 LT |
2008 | |
2009 | /* Clear our data area */ | |
285d0321 | 2010 | ha->bars = bars; |
09483916 | 2011 | ha->mem_only = mem_only; |
df4bf0bb | 2012 | spin_lock_init(&ha->hardware_lock); |
339aa70e | 2013 | spin_lock_init(&ha->vport_slock); |
1da177e4 | 2014 | |
ea5b6382 AV |
2015 | /* Set ISP-type information. */ |
2016 | qla2x00_set_isp_flags(ha); | |
ca79cf66 DG |
2017 | |
2018 | /* Set EEH reset type to fundamental if required by hba */ | |
2019 | if ( IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) { | |
2020 | pdev->needs_freset = 1; | |
ca79cf66 DG |
2021 | } |
2022 | ||
1da177e4 LT |
2023 | /* Configure PCI I/O space */ |
2024 | ret = qla2x00_iospace_config(ha); | |
a1541d5a | 2025 | if (ret) |
e315cd28 | 2026 | goto probe_hw_failed; |
1da177e4 | 2027 | |
7c3df132 SK |
2028 | ql_log_pci(ql_log_info, pdev, 0x001d, |
2029 | "Found an ISP%04X irq %d iobase 0x%p.\n", | |
2030 | pdev->device, pdev->irq, ha->iobase); | |
1da177e4 | 2031 | ha->prev_topology = 0; |
fca29703 | 2032 | ha->init_cb_size = sizeof(init_cb_t); |
d8b45213 | 2033 | ha->link_data_rate = PORT_SPEED_UNKNOWN; |
854165f4 | 2034 | ha->optrom_size = OPTROM_SIZE_2300; |
1da177e4 | 2035 | |
abbd8870 | 2036 | /* Assign ISP specific operations. */ |
e315cd28 | 2037 | max_id = MAX_TARGETS_2200; |
1da177e4 | 2038 | if (IS_QLA2100(ha)) { |
e315cd28 | 2039 | max_id = MAX_TARGETS_2100; |
1da177e4 | 2040 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; |
e315cd28 AC |
2041 | req_length = REQUEST_ENTRY_CNT_2100; |
2042 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2043 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2044 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2045 | ha->flash_conf_off = ~0; |
2046 | ha->flash_data_off = ~0; | |
2047 | ha->nvram_conf_off = ~0; | |
2048 | ha->nvram_data_off = ~0; | |
fd34f556 | 2049 | ha->isp_ops = &qla2100_isp_ops; |
1da177e4 | 2050 | } else if (IS_QLA2200(ha)) { |
1da177e4 | 2051 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2052 | req_length = REQUEST_ENTRY_CNT_2200; |
2053 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2054 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2055 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2056 | ha->flash_conf_off = ~0; |
2057 | ha->flash_data_off = ~0; | |
2058 | ha->nvram_conf_off = ~0; | |
2059 | ha->nvram_data_off = ~0; | |
fd34f556 | 2060 | ha->isp_ops = &qla2100_isp_ops; |
fca29703 | 2061 | } else if (IS_QLA23XX(ha)) { |
1da177e4 | 2062 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2063 | req_length = REQUEST_ENTRY_CNT_2200; |
2064 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2065 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
abbd8870 | 2066 | ha->gid_list_info_size = 6; |
854165f4 AV |
2067 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
2068 | ha->optrom_size = OPTROM_SIZE_2322; | |
3a03eb79 AV |
2069 | ha->flash_conf_off = ~0; |
2070 | ha->flash_data_off = ~0; | |
2071 | ha->nvram_conf_off = ~0; | |
2072 | ha->nvram_data_off = ~0; | |
fd34f556 | 2073 | ha->isp_ops = &qla2300_isp_ops; |
4d4df193 | 2074 | } else if (IS_QLA24XX_TYPE(ha)) { |
fca29703 | 2075 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2076 | req_length = REQUEST_ENTRY_CNT_24XX; |
2077 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2078 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2c3dfe3f | 2079 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
fca29703 | 2080 | ha->gid_list_info_size = 8; |
854165f4 | 2081 | ha->optrom_size = OPTROM_SIZE_24XX; |
73208dfd | 2082 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; |
fd34f556 | 2083 | ha->isp_ops = &qla24xx_isp_ops; |
3a03eb79 AV |
2084 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2085 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2086 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2087 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
c3a2f0df | 2088 | } else if (IS_QLA25XX(ha)) { |
c3a2f0df | 2089 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2090 | req_length = REQUEST_ENTRY_CNT_24XX; |
2091 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2092 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
c3a2f0df | 2093 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
c3a2f0df AV |
2094 | ha->gid_list_info_size = 8; |
2095 | ha->optrom_size = OPTROM_SIZE_25XX; | |
73208dfd | 2096 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
c3a2f0df | 2097 | ha->isp_ops = &qla25xx_isp_ops; |
3a03eb79 AV |
2098 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2099 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2100 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2101 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2102 | } else if (IS_QLA81XX(ha)) { | |
2103 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2104 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2105 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2106 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2107 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2108 | ha->gid_list_info_size = 8; | |
2109 | ha->optrom_size = OPTROM_SIZE_81XX; | |
40859ae5 | 2110 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
3a03eb79 AV |
2111 | ha->isp_ops = &qla81xx_isp_ops; |
2112 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2113 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2114 | ha->nvram_conf_off = ~0; | |
2115 | ha->nvram_data_off = ~0; | |
a9083016 GM |
2116 | } else if (IS_QLA82XX(ha)) { |
2117 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2118 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2119 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2120 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2121 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2122 | ha->gid_list_info_size = 8; | |
2123 | ha->optrom_size = OPTROM_SIZE_82XX; | |
087c621e | 2124 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
a9083016 GM |
2125 | ha->isp_ops = &qla82xx_isp_ops; |
2126 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2127 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2128 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2129 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
1da177e4 | 2130 | } |
7c3df132 SK |
2131 | ql_dbg_pci(ql_dbg_init, pdev, 0x001e, |
2132 | "mbx_count=%d, req_length=%d, " | |
2133 | "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " | |
2134 | "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, .\n", | |
2135 | ha->mbx_count, req_length, rsp_length, ha->max_loop_id, | |
2136 | ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, | |
2137 | ha->nvram_npiv_size); | |
2138 | ql_dbg_pci(ql_dbg_init, pdev, 0x001f, | |
2139 | "isp_ops=%p, flash_conf_off=%d, " | |
2140 | "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", | |
2141 | ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, | |
2142 | ha->nvram_conf_off, ha->nvram_data_off); | |
6c2f527c | 2143 | mutex_init(&ha->vport_lock); |
0b05a1f0 MB |
2144 | init_completion(&ha->mbx_cmd_comp); |
2145 | complete(&ha->mbx_cmd_comp); | |
2146 | init_completion(&ha->mbx_intr_comp); | |
23f2ebd1 | 2147 | init_completion(&ha->dcbx_comp); |
1da177e4 | 2148 | |
2c3dfe3f | 2149 | set_bit(0, (unsigned long *) ha->vp_idx_map); |
1da177e4 | 2150 | |
53303c42 | 2151 | qla2x00_config_dma_addressing(ha); |
7c3df132 SK |
2152 | ql_dbg_pci(ql_dbg_init, pdev, 0x0020, |
2153 | "64 Bit addressing is %s.\n", | |
2154 | ha->flags.enable_64bit_addressing ? "enable" : | |
2155 | "disable"); | |
73208dfd | 2156 | ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); |
e315cd28 | 2157 | if (!ret) { |
7c3df132 SK |
2158 | ql_log_pci(ql_log_fatal, pdev, 0x0031, |
2159 | "Failed to allocate memory for adapter, aborting.\n"); | |
1da177e4 | 2160 | |
e315cd28 AC |
2161 | goto probe_hw_failed; |
2162 | } | |
2163 | ||
73208dfd | 2164 | req->max_q_depth = MAX_Q_DEPTH; |
e315cd28 | 2165 | if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) |
73208dfd AC |
2166 | req->max_q_depth = ql2xmaxqdepth; |
2167 | ||
e315cd28 AC |
2168 | |
2169 | base_vha = qla2x00_create_host(sht, ha); | |
2170 | if (!base_vha) { | |
a1541d5a | 2171 | ret = -ENOMEM; |
6e9f21f3 | 2172 | qla2x00_mem_free(ha); |
2afa19a9 AC |
2173 | qla2x00_free_req_que(ha, req); |
2174 | qla2x00_free_rsp_que(ha, rsp); | |
e315cd28 | 2175 | goto probe_hw_failed; |
1da177e4 LT |
2176 | } |
2177 | ||
e315cd28 AC |
2178 | pci_set_drvdata(pdev, base_vha); |
2179 | ||
e315cd28 | 2180 | host = base_vha->host; |
2afa19a9 | 2181 | base_vha->req = req; |
73208dfd AC |
2182 | host->can_queue = req->length + 128; |
2183 | if (IS_QLA2XXX_MIDTYPE(ha)) | |
e315cd28 | 2184 | base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; |
73208dfd | 2185 | else |
e315cd28 AC |
2186 | base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + |
2187 | base_vha->vp_idx; | |
58548cb5 GM |
2188 | |
2189 | /* Set the SG table size based on ISP type */ | |
2190 | if (!IS_FWI2_CAPABLE(ha)) { | |
2191 | if (IS_QLA2100(ha)) | |
2192 | host->sg_tablesize = 32; | |
2193 | } else { | |
2194 | if (!IS_QLA82XX(ha)) | |
2195 | host->sg_tablesize = QLA_SG_ALL; | |
2196 | } | |
7c3df132 SK |
2197 | ql_dbg(ql_dbg_init, base_vha, 0x0032, |
2198 | "can_queue=%d, req=%p, " | |
2199 | "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", | |
2200 | host->can_queue, base_vha->req, | |
2201 | base_vha->mgmt_svr_loop_id, host->sg_tablesize); | |
e315cd28 AC |
2202 | host->max_id = max_id; |
2203 | host->this_id = 255; | |
2204 | host->cmd_per_lun = 3; | |
2205 | host->unique_id = host->host_no; | |
e02587d7 | 2206 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) |
0c470874 AE |
2207 | host->max_cmd_len = 32; |
2208 | else | |
2209 | host->max_cmd_len = MAX_CMDSZ; | |
e315cd28 | 2210 | host->max_channel = MAX_BUSES - 1; |
82515920 | 2211 | host->max_lun = ql2xmaxlun; |
e315cd28 | 2212 | host->transportt = qla2xxx_transport_template; |
9a069e19 | 2213 | sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); |
e315cd28 | 2214 | |
7c3df132 SK |
2215 | ql_dbg(ql_dbg_init, base_vha, 0x0033, |
2216 | "max_id=%d this_id=%d " | |
2217 | "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " | |
d8424f68 | 2218 | "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id, |
7c3df132 SK |
2219 | host->this_id, host->cmd_per_lun, host->unique_id, |
2220 | host->max_cmd_len, host->max_channel, host->max_lun, | |
2221 | host->transportt, sht->vendor_id); | |
2222 | ||
73208dfd AC |
2223 | /* Set up the irqs */ |
2224 | ret = qla2x00_request_irqs(ha, rsp); | |
2225 | if (ret) | |
6e9f21f3 | 2226 | goto probe_init_failed; |
90a86fc0 JC |
2227 | |
2228 | pci_save_state(pdev); | |
2229 | ||
73208dfd | 2230 | /* Alloc arrays of request and response ring ptrs */ |
7163ea81 | 2231 | que_init: |
73208dfd | 2232 | if (!qla2x00_alloc_queues(ha)) { |
7c3df132 SK |
2233 | ql_log(ql_log_fatal, base_vha, 0x003d, |
2234 | "Failed to allocate memory for queue pointers.. aborting.\n"); | |
6e9f21f3 | 2235 | goto probe_init_failed; |
73208dfd | 2236 | } |
a9083016 | 2237 | |
73208dfd AC |
2238 | ha->rsp_q_map[0] = rsp; |
2239 | ha->req_q_map[0] = req; | |
2afa19a9 AC |
2240 | rsp->req = req; |
2241 | req->rsp = rsp; | |
2242 | set_bit(0, ha->req_qid_map); | |
2243 | set_bit(0, ha->rsp_qid_map); | |
08029990 AV |
2244 | /* FWI2-capable only. */ |
2245 | req->req_q_in = &ha->iobase->isp24.req_q_in; | |
2246 | req->req_q_out = &ha->iobase->isp24.req_q_out; | |
2247 | rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; | |
2248 | rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; | |
17d98630 | 2249 | if (ha->mqenable) { |
08029990 AV |
2250 | req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; |
2251 | req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; | |
2252 | rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; | |
2253 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; | |
17d98630 AC |
2254 | } |
2255 | ||
a9083016 GM |
2256 | if (IS_QLA82XX(ha)) { |
2257 | req->req_q_out = &ha->iobase->isp82.req_q_out[0]; | |
2258 | rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; | |
2259 | rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; | |
2260 | } | |
2261 | ||
7c3df132 SK |
2262 | ql_dbg(ql_dbg_multiq, base_vha, 0xc009, |
2263 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2264 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2265 | ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, | |
2266 | "req->req_q_in=%p req->req_q_out=%p " | |
2267 | "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2268 | req->req_q_in, req->req_q_out, | |
2269 | rsp->rsp_q_in, rsp->rsp_q_out); | |
2270 | ql_dbg(ql_dbg_init, base_vha, 0x003e, | |
2271 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2272 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2273 | ql_dbg(ql_dbg_init, base_vha, 0x003f, | |
2274 | "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2275 | req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); | |
1da177e4 | 2276 | |
7c3df132 SK |
2277 | if (qla2x00_initialize_adapter(base_vha)) { |
2278 | ql_log(ql_log_fatal, base_vha, 0x00d6, | |
2279 | "Failed to initialize adapter - Adapter flags %x.\n", | |
2280 | base_vha->device_flags); | |
1da177e4 | 2281 | |
a9083016 GM |
2282 | if (IS_QLA82XX(ha)) { |
2283 | qla82xx_idc_lock(ha); | |
2284 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
2285 | QLA82XX_DEV_FAILED); | |
2286 | qla82xx_idc_unlock(ha); | |
7c3df132 SK |
2287 | ql_log(ql_log_fatal, base_vha, 0x00d7, |
2288 | "HW State: FAILED.\n"); | |
a9083016 GM |
2289 | } |
2290 | ||
a1541d5a | 2291 | ret = -ENODEV; |
1da177e4 LT |
2292 | goto probe_failed; |
2293 | } | |
2294 | ||
7163ea81 AC |
2295 | if (ha->mqenable) { |
2296 | if (qla25xx_setup_mode(base_vha)) { | |
7c3df132 SK |
2297 | ql_log(ql_log_warn, base_vha, 0x00ec, |
2298 | "Failed to create queues, falling back to single queue mode.\n"); | |
7163ea81 AC |
2299 | goto que_init; |
2300 | } | |
2301 | } | |
68ca949c | 2302 | |
cbc8eb67 AV |
2303 | if (ha->flags.running_gold_fw) |
2304 | goto skip_dpc; | |
2305 | ||
1da177e4 LT |
2306 | /* |
2307 | * Startup the kernel thread for this host adapter | |
2308 | */ | |
39a11240 | 2309 | ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, |
7c3df132 | 2310 | "%s_dpc", base_vha->host_str); |
39a11240 | 2311 | if (IS_ERR(ha->dpc_thread)) { |
7c3df132 SK |
2312 | ql_log(ql_log_fatal, base_vha, 0x00ed, |
2313 | "Failed to start DPC thread.\n"); | |
39a11240 | 2314 | ret = PTR_ERR(ha->dpc_thread); |
1da177e4 LT |
2315 | goto probe_failed; |
2316 | } | |
7c3df132 SK |
2317 | ql_dbg(ql_dbg_init, base_vha, 0x00ee, |
2318 | "DPC thread started successfully.\n"); | |
1da177e4 | 2319 | |
cbc8eb67 | 2320 | skip_dpc: |
e315cd28 AC |
2321 | list_add_tail(&base_vha->list, &ha->vp_list); |
2322 | base_vha->host->irq = ha->pdev->irq; | |
1da177e4 LT |
2323 | |
2324 | /* Initialized the timer */ | |
e315cd28 | 2325 | qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); |
7c3df132 SK |
2326 | ql_dbg(ql_dbg_init, base_vha, 0x00ef, |
2327 | "Started qla2x00_timer with " | |
2328 | "interval=%d.\n", WATCH_INTERVAL); | |
2329 | ql_dbg(ql_dbg_init, base_vha, 0x00f0, | |
2330 | "Detected hba at address=%p.\n", | |
2331 | ha); | |
d19044c3 | 2332 | |
e02587d7 | 2333 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { |
bad75002 | 2334 | if (ha->fw_attributes & BIT_4) { |
8cb2049c | 2335 | int prot = 0; |
bad75002 | 2336 | base_vha->flags.difdix_supported = 1; |
7c3df132 SK |
2337 | ql_dbg(ql_dbg_init, base_vha, 0x00f1, |
2338 | "Registering for DIF/DIX type 1 and 3 protection.\n"); | |
8cb2049c AE |
2339 | if (ql2xenabledif == 1) |
2340 | prot = SHOST_DIX_TYPE0_PROTECTION; | |
bad75002 | 2341 | scsi_host_set_prot(host, |
8cb2049c | 2342 | prot | SHOST_DIF_TYPE1_PROTECTION |
0c470874 | 2343 | | SHOST_DIF_TYPE2_PROTECTION |
bad75002 AE |
2344 | | SHOST_DIF_TYPE3_PROTECTION |
2345 | | SHOST_DIX_TYPE1_PROTECTION | |
0c470874 | 2346 | | SHOST_DIX_TYPE2_PROTECTION |
bad75002 AE |
2347 | | SHOST_DIX_TYPE3_PROTECTION); |
2348 | scsi_host_set_guard(host, SHOST_DIX_GUARD_CRC); | |
2349 | } else | |
2350 | base_vha->flags.difdix_supported = 0; | |
2351 | } | |
2352 | ||
a9083016 GM |
2353 | ha->isp_ops->enable_intrs(ha); |
2354 | ||
a1541d5a AV |
2355 | ret = scsi_add_host(host, &pdev->dev); |
2356 | if (ret) | |
2357 | goto probe_failed; | |
2358 | ||
1486400f MR |
2359 | base_vha->flags.init_done = 1; |
2360 | base_vha->flags.online = 1; | |
2361 | ||
7c3df132 SK |
2362 | ql_dbg(ql_dbg_init, base_vha, 0x00f2, |
2363 | "Init done and hba is online.\n"); | |
2364 | ||
1e99e33a AV |
2365 | scsi_scan_host(host); |
2366 | ||
e315cd28 | 2367 | qla2x00_alloc_sysfs_attr(base_vha); |
a1541d5a | 2368 | |
e315cd28 | 2369 | qla2x00_init_host_attr(base_vha); |
a1541d5a | 2370 | |
e315cd28 | 2371 | qla2x00_dfs_setup(base_vha); |
df613b96 | 2372 | |
7c3df132 SK |
2373 | ql_log(ql_log_info, base_vha, 0x00fb, |
2374 | "QLogic %s - %s.\n", | |
2375 | ha->model_number, ha->model_desc ? ha->model_desc : ""); | |
2376 | ql_log(ql_log_info, base_vha, 0x00fc, | |
2377 | "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", | |
2378 | pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), | |
2379 | pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', | |
2380 | base_vha->host_no, | |
e315cd28 | 2381 | ha->isp_ops->fw_version_str(base_vha, fw_str)); |
1da177e4 | 2382 | |
1da177e4 LT |
2383 | return 0; |
2384 | ||
6e9f21f3 | 2385 | probe_init_failed: |
2afa19a9 AC |
2386 | qla2x00_free_req_que(ha, req); |
2387 | qla2x00_free_rsp_que(ha, rsp); | |
2388 | ha->max_req_queues = ha->max_rsp_queues = 0; | |
6e9f21f3 | 2389 | |
1da177e4 | 2390 | probe_failed: |
b9978769 AV |
2391 | if (base_vha->timer_active) |
2392 | qla2x00_stop_timer(base_vha); | |
2393 | base_vha->flags.online = 0; | |
2394 | if (ha->dpc_thread) { | |
2395 | struct task_struct *t = ha->dpc_thread; | |
2396 | ||
2397 | ha->dpc_thread = NULL; | |
2398 | kthread_stop(t); | |
2399 | } | |
2400 | ||
e315cd28 | 2401 | qla2x00_free_device(base_vha); |
1da177e4 | 2402 | |
e315cd28 | 2403 | scsi_host_put(base_vha->host); |
1da177e4 | 2404 | |
e315cd28 | 2405 | probe_hw_failed: |
a9083016 GM |
2406 | if (IS_QLA82XX(ha)) { |
2407 | qla82xx_idc_lock(ha); | |
2408 | qla82xx_clear_drv_active(ha); | |
2409 | qla82xx_idc_unlock(ha); | |
2410 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); | |
2411 | if (!ql2xdbwr) | |
2412 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); | |
2413 | } else { | |
2414 | if (ha->iobase) | |
2415 | iounmap(ha->iobase); | |
2416 | } | |
e315cd28 AC |
2417 | pci_release_selected_regions(ha->pdev, ha->bars); |
2418 | kfree(ha); | |
2419 | ha = NULL; | |
1da177e4 | 2420 | |
a1541d5a | 2421 | probe_out: |
e315cd28 | 2422 | pci_disable_device(pdev); |
a1541d5a | 2423 | return ret; |
1da177e4 | 2424 | } |
1da177e4 | 2425 | |
e30d1756 MI |
2426 | static void |
2427 | qla2x00_shutdown(struct pci_dev *pdev) | |
2428 | { | |
2429 | scsi_qla_host_t *vha; | |
2430 | struct qla_hw_data *ha; | |
2431 | ||
2432 | vha = pci_get_drvdata(pdev); | |
2433 | ha = vha->hw; | |
2434 | ||
2435 | /* Turn-off FCE trace */ | |
2436 | if (ha->flags.fce_enabled) { | |
2437 | qla2x00_disable_fce_trace(vha, NULL, NULL); | |
2438 | ha->flags.fce_enabled = 0; | |
2439 | } | |
2440 | ||
2441 | /* Turn-off EFT trace */ | |
2442 | if (ha->eft) | |
2443 | qla2x00_disable_eft_trace(vha); | |
2444 | ||
2445 | /* Stop currently executing firmware. */ | |
2446 | qla2x00_try_to_stop_firmware(vha); | |
2447 | ||
2448 | /* Turn adapter off line */ | |
2449 | vha->flags.online = 0; | |
2450 | ||
2451 | /* turn-off interrupts on the card */ | |
2452 | if (ha->interrupts_on) { | |
2453 | vha->flags.init_done = 0; | |
2454 | ha->isp_ops->disable_intrs(ha); | |
2455 | } | |
2456 | ||
2457 | qla2x00_free_irqs(vha); | |
2458 | ||
2459 | qla2x00_free_fw_dump(ha); | |
2460 | } | |
2461 | ||
4c993f76 | 2462 | static void |
7ee61397 | 2463 | qla2x00_remove_one(struct pci_dev *pdev) |
1da177e4 | 2464 | { |
feafb7b1 | 2465 | scsi_qla_host_t *base_vha, *vha; |
e315cd28 | 2466 | struct qla_hw_data *ha; |
feafb7b1 | 2467 | unsigned long flags; |
e315cd28 AC |
2468 | |
2469 | base_vha = pci_get_drvdata(pdev); | |
2470 | ha = base_vha->hw; | |
2471 | ||
43ebf16d AE |
2472 | mutex_lock(&ha->vport_lock); |
2473 | while (ha->cur_vport_count) { | |
2474 | struct Scsi_Host *scsi_host; | |
feafb7b1 | 2475 | |
43ebf16d | 2476 | spin_lock_irqsave(&ha->vport_slock, flags); |
feafb7b1 | 2477 | |
43ebf16d AE |
2478 | BUG_ON(base_vha->list.next == &ha->vp_list); |
2479 | /* This assumes first entry in ha->vp_list is always base vha */ | |
2480 | vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); | |
2481 | scsi_host = scsi_host_get(vha->host); | |
feafb7b1 | 2482 | |
43ebf16d AE |
2483 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
2484 | mutex_unlock(&ha->vport_lock); | |
2485 | ||
2486 | fc_vport_terminate(vha->fc_vport); | |
2487 | scsi_host_put(vha->host); | |
feafb7b1 | 2488 | |
43ebf16d | 2489 | mutex_lock(&ha->vport_lock); |
e315cd28 | 2490 | } |
43ebf16d | 2491 | mutex_unlock(&ha->vport_lock); |
1da177e4 | 2492 | |
e315cd28 | 2493 | set_bit(UNLOADING, &base_vha->dpc_flags); |
1da177e4 | 2494 | |
b9978769 AV |
2495 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); |
2496 | ||
e315cd28 | 2497 | qla2x00_dfs_remove(base_vha); |
c795c1e4 | 2498 | |
e315cd28 | 2499 | qla84xx_put_chip(base_vha); |
c795c1e4 | 2500 | |
b9978769 AV |
2501 | /* Disable timer */ |
2502 | if (base_vha->timer_active) | |
2503 | qla2x00_stop_timer(base_vha); | |
2504 | ||
2505 | base_vha->flags.online = 0; | |
2506 | ||
68ca949c AC |
2507 | /* Flush the work queue and remove it */ |
2508 | if (ha->wq) { | |
2509 | flush_workqueue(ha->wq); | |
2510 | destroy_workqueue(ha->wq); | |
2511 | ha->wq = NULL; | |
2512 | } | |
2513 | ||
b9978769 AV |
2514 | /* Kill the kernel thread for this host */ |
2515 | if (ha->dpc_thread) { | |
2516 | struct task_struct *t = ha->dpc_thread; | |
2517 | ||
2518 | /* | |
2519 | * qla2xxx_wake_dpc checks for ->dpc_thread | |
2520 | * so we need to zero it out. | |
2521 | */ | |
2522 | ha->dpc_thread = NULL; | |
2523 | kthread_stop(t); | |
2524 | } | |
2525 | ||
e315cd28 | 2526 | qla2x00_free_sysfs_attr(base_vha); |
df613b96 | 2527 | |
e315cd28 | 2528 | fc_remove_host(base_vha->host); |
4d4df193 | 2529 | |
e315cd28 | 2530 | scsi_remove_host(base_vha->host); |
1da177e4 | 2531 | |
e315cd28 | 2532 | qla2x00_free_device(base_vha); |
bdf79621 | 2533 | |
e315cd28 | 2534 | scsi_host_put(base_vha->host); |
1da177e4 | 2535 | |
a9083016 | 2536 | if (IS_QLA82XX(ha)) { |
b963752f GM |
2537 | qla82xx_idc_lock(ha); |
2538 | qla82xx_clear_drv_active(ha); | |
2539 | qla82xx_idc_unlock(ha); | |
2540 | ||
a9083016 GM |
2541 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); |
2542 | if (!ql2xdbwr) | |
2543 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); | |
2544 | } else { | |
2545 | if (ha->iobase) | |
2546 | iounmap(ha->iobase); | |
1da177e4 | 2547 | |
a9083016 GM |
2548 | if (ha->mqiobase) |
2549 | iounmap(ha->mqiobase); | |
2550 | } | |
73208dfd | 2551 | |
e315cd28 AC |
2552 | pci_release_selected_regions(ha->pdev, ha->bars); |
2553 | kfree(ha); | |
2554 | ha = NULL; | |
1da177e4 | 2555 | |
90a86fc0 JC |
2556 | pci_disable_pcie_error_reporting(pdev); |
2557 | ||
665db93b | 2558 | pci_disable_device(pdev); |
1da177e4 LT |
2559 | pci_set_drvdata(pdev, NULL); |
2560 | } | |
1da177e4 LT |
2561 | |
2562 | static void | |
e315cd28 | 2563 | qla2x00_free_device(scsi_qla_host_t *vha) |
1da177e4 | 2564 | { |
e315cd28 | 2565 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 2566 | |
85880801 AV |
2567 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); |
2568 | ||
2569 | /* Disable timer */ | |
2570 | if (vha->timer_active) | |
2571 | qla2x00_stop_timer(vha); | |
2572 | ||
2573 | /* Kill the kernel thread for this host */ | |
2574 | if (ha->dpc_thread) { | |
2575 | struct task_struct *t = ha->dpc_thread; | |
2576 | ||
2577 | /* | |
2578 | * qla2xxx_wake_dpc checks for ->dpc_thread | |
2579 | * so we need to zero it out. | |
2580 | */ | |
2581 | ha->dpc_thread = NULL; | |
2582 | kthread_stop(t); | |
2583 | } | |
2584 | ||
2afa19a9 AC |
2585 | qla25xx_delete_queues(vha); |
2586 | ||
df613b96 | 2587 | if (ha->flags.fce_enabled) |
e315cd28 | 2588 | qla2x00_disable_fce_trace(vha, NULL, NULL); |
df613b96 | 2589 | |
a7a167bf | 2590 | if (ha->eft) |
e315cd28 | 2591 | qla2x00_disable_eft_trace(vha); |
a7a167bf | 2592 | |
f6ef3b18 | 2593 | /* Stop currently executing firmware. */ |
e315cd28 | 2594 | qla2x00_try_to_stop_firmware(vha); |
1da177e4 | 2595 | |
85880801 AV |
2596 | vha->flags.online = 0; |
2597 | ||
f6ef3b18 | 2598 | /* turn-off interrupts on the card */ |
a9083016 GM |
2599 | if (ha->interrupts_on) { |
2600 | vha->flags.init_done = 0; | |
fd34f556 | 2601 | ha->isp_ops->disable_intrs(ha); |
a9083016 | 2602 | } |
f6ef3b18 | 2603 | |
e315cd28 | 2604 | qla2x00_free_irqs(vha); |
1da177e4 | 2605 | |
8867048b CD |
2606 | qla2x00_free_fcports(vha); |
2607 | ||
e315cd28 | 2608 | qla2x00_mem_free(ha); |
73208dfd | 2609 | |
08de2844 GM |
2610 | qla82xx_md_free(vha); |
2611 | ||
73208dfd | 2612 | qla2x00_free_queues(ha); |
1da177e4 LT |
2613 | } |
2614 | ||
8867048b CD |
2615 | void qla2x00_free_fcports(struct scsi_qla_host *vha) |
2616 | { | |
2617 | fc_port_t *fcport, *tfcport; | |
2618 | ||
2619 | list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { | |
2620 | list_del(&fcport->list); | |
2621 | kfree(fcport); | |
2622 | fcport = NULL; | |
2623 | } | |
2624 | } | |
2625 | ||
d97994dc | 2626 | static inline void |
e315cd28 | 2627 | qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, |
d97994dc AV |
2628 | int defer) |
2629 | { | |
d97994dc | 2630 | struct fc_rport *rport; |
67becc00 | 2631 | scsi_qla_host_t *base_vha; |
044d78e1 | 2632 | unsigned long flags; |
d97994dc AV |
2633 | |
2634 | if (!fcport->rport) | |
2635 | return; | |
2636 | ||
2637 | rport = fcport->rport; | |
2638 | if (defer) { | |
67becc00 | 2639 | base_vha = pci_get_drvdata(vha->hw->pdev); |
044d78e1 | 2640 | spin_lock_irqsave(vha->host->host_lock, flags); |
d97994dc | 2641 | fcport->drport = rport; |
044d78e1 | 2642 | spin_unlock_irqrestore(vha->host->host_lock, flags); |
67becc00 AV |
2643 | set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); |
2644 | qla2xxx_wake_dpc(base_vha); | |
5f3a9a20 | 2645 | } else |
d97994dc | 2646 | fc_remote_port_delete(rport); |
d97994dc AV |
2647 | } |
2648 | ||
1da177e4 LT |
2649 | /* |
2650 | * qla2x00_mark_device_lost Updates fcport state when device goes offline. | |
2651 | * | |
2652 | * Input: ha = adapter block pointer. fcport = port structure pointer. | |
2653 | * | |
2654 | * Return: None. | |
2655 | * | |
2656 | * Context: | |
2657 | */ | |
e315cd28 | 2658 | void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, |
d97994dc | 2659 | int do_login, int defer) |
1da177e4 | 2660 | { |
2c3dfe3f | 2661 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
e315cd28 | 2662 | vha->vp_idx == fcport->vp_idx) { |
ec426e10 | 2663 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
e315cd28 AC |
2664 | qla2x00_schedule_rport_del(vha, fcport, defer); |
2665 | } | |
fa2a1ce5 | 2666 | /* |
1da177e4 LT |
2667 | * We may need to retry the login, so don't change the state of the |
2668 | * port but do the retries. | |
2669 | */ | |
2670 | if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) | |
ec426e10 | 2671 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
1da177e4 LT |
2672 | |
2673 | if (!do_login) | |
2674 | return; | |
2675 | ||
2676 | if (fcport->login_retry == 0) { | |
e315cd28 AC |
2677 | fcport->login_retry = vha->hw->login_retry_count; |
2678 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
1da177e4 | 2679 | |
7c3df132 SK |
2680 | ql_dbg(ql_dbg_disc, vha, 0x2067, |
2681 | "Port login retry " | |
1da177e4 | 2682 | "%02x%02x%02x%02x%02x%02x%02x%02x, " |
7c3df132 SK |
2683 | "id = 0x%04x retry cnt=%d.\n", |
2684 | fcport->port_name[0], fcport->port_name[1], | |
2685 | fcport->port_name[2], fcport->port_name[3], | |
2686 | fcport->port_name[4], fcport->port_name[5], | |
2687 | fcport->port_name[6], fcport->port_name[7], | |
2688 | fcport->loop_id, fcport->login_retry); | |
1da177e4 LT |
2689 | } |
2690 | } | |
2691 | ||
2692 | /* | |
2693 | * qla2x00_mark_all_devices_lost | |
2694 | * Updates fcport state when device goes offline. | |
2695 | * | |
2696 | * Input: | |
2697 | * ha = adapter block pointer. | |
2698 | * fcport = port structure pointer. | |
2699 | * | |
2700 | * Return: | |
2701 | * None. | |
2702 | * | |
2703 | * Context: | |
2704 | */ | |
2705 | void | |
e315cd28 | 2706 | qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) |
1da177e4 LT |
2707 | { |
2708 | fc_port_t *fcport; | |
2709 | ||
e315cd28 | 2710 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
0d6e61bc | 2711 | if (vha->vp_idx != 0 && vha->vp_idx != fcport->vp_idx) |
1da177e4 | 2712 | continue; |
0d6e61bc | 2713 | |
1da177e4 LT |
2714 | /* |
2715 | * No point in marking the device as lost, if the device is | |
2716 | * already DEAD. | |
2717 | */ | |
2718 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) | |
2719 | continue; | |
e315cd28 | 2720 | if (atomic_read(&fcport->state) == FCS_ONLINE) { |
ec426e10 | 2721 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
0d6e61bc AV |
2722 | if (defer) |
2723 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
2724 | else if (vha->vp_idx == fcport->vp_idx) | |
2725 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
2726 | } | |
1da177e4 LT |
2727 | } |
2728 | } | |
2729 | ||
2730 | /* | |
2731 | * qla2x00_mem_alloc | |
2732 | * Allocates adapter memory. | |
2733 | * | |
2734 | * Returns: | |
2735 | * 0 = success. | |
e8711085 | 2736 | * !0 = failure. |
1da177e4 | 2737 | */ |
e8711085 | 2738 | static int |
73208dfd AC |
2739 | qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, |
2740 | struct req_que **req, struct rsp_que **rsp) | |
1da177e4 LT |
2741 | { |
2742 | char name[16]; | |
1da177e4 | 2743 | |
e8711085 | 2744 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, |
e315cd28 | 2745 | &ha->init_cb_dma, GFP_KERNEL); |
e8711085 | 2746 | if (!ha->init_cb) |
e315cd28 | 2747 | goto fail; |
e8711085 | 2748 | |
e315cd28 AC |
2749 | ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, GID_LIST_SIZE, |
2750 | &ha->gid_list_dma, GFP_KERNEL); | |
2751 | if (!ha->gid_list) | |
e8711085 | 2752 | goto fail_free_init_cb; |
1da177e4 | 2753 | |
e8711085 AV |
2754 | ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); |
2755 | if (!ha->srb_mempool) | |
e315cd28 | 2756 | goto fail_free_gid_list; |
e8711085 | 2757 | |
a9083016 GM |
2758 | if (IS_QLA82XX(ha)) { |
2759 | /* Allocate cache for CT6 Ctx. */ | |
2760 | if (!ctx_cachep) { | |
2761 | ctx_cachep = kmem_cache_create("qla2xxx_ctx", | |
2762 | sizeof(struct ct6_dsd), 0, | |
2763 | SLAB_HWCACHE_ALIGN, NULL); | |
2764 | if (!ctx_cachep) | |
2765 | goto fail_free_gid_list; | |
2766 | } | |
2767 | ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, | |
2768 | ctx_cachep); | |
2769 | if (!ha->ctx_mempool) | |
2770 | goto fail_free_srb_mempool; | |
7c3df132 SK |
2771 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, |
2772 | "ctx_cachep=%p ctx_mempool=%p.\n", | |
2773 | ctx_cachep, ha->ctx_mempool); | |
a9083016 GM |
2774 | } |
2775 | ||
e8711085 AV |
2776 | /* Get memory for cached NVRAM */ |
2777 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); | |
2778 | if (!ha->nvram) | |
a9083016 | 2779 | goto fail_free_ctx_mempool; |
e8711085 | 2780 | |
e315cd28 AC |
2781 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, |
2782 | ha->pdev->device); | |
2783 | ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
2784 | DMA_POOL_SIZE, 8, 0); | |
2785 | if (!ha->s_dma_pool) | |
2786 | goto fail_free_nvram; | |
2787 | ||
7c3df132 SK |
2788 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, |
2789 | "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", | |
2790 | ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); | |
2791 | ||
bad75002 | 2792 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
2793 | ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, |
2794 | DSD_LIST_DMA_POOL_SIZE, 8, 0); | |
2795 | if (!ha->dl_dma_pool) { | |
7c3df132 SK |
2796 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, |
2797 | "Failed to allocate memory for dl_dma_pool.\n"); | |
a9083016 GM |
2798 | goto fail_s_dma_pool; |
2799 | } | |
2800 | ||
2801 | ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
2802 | FCP_CMND_DMA_POOL_SIZE, 8, 0); | |
2803 | if (!ha->fcp_cmnd_dma_pool) { | |
7c3df132 SK |
2804 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, |
2805 | "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); | |
a9083016 GM |
2806 | goto fail_dl_dma_pool; |
2807 | } | |
7c3df132 SK |
2808 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, |
2809 | "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", | |
2810 | ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); | |
a9083016 GM |
2811 | } |
2812 | ||
e8711085 AV |
2813 | /* Allocate memory for SNS commands */ |
2814 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
e315cd28 | 2815 | /* Get consistent memory allocated for SNS commands */ |
e8711085 | 2816 | ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 2817 | sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); |
e8711085 | 2818 | if (!ha->sns_cmd) |
e315cd28 | 2819 | goto fail_dma_pool; |
7c3df132 | 2820 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, |
d8424f68 | 2821 | "sns_cmd: %p.\n", ha->sns_cmd); |
e8711085 | 2822 | } else { |
e315cd28 | 2823 | /* Get consistent memory allocated for MS IOCB */ |
e8711085 | 2824 | ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
e315cd28 | 2825 | &ha->ms_iocb_dma); |
e8711085 | 2826 | if (!ha->ms_iocb) |
e315cd28 AC |
2827 | goto fail_dma_pool; |
2828 | /* Get consistent memory allocated for CT SNS commands */ | |
e8711085 | 2829 | ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 2830 | sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); |
e8711085 AV |
2831 | if (!ha->ct_sns) |
2832 | goto fail_free_ms_iocb; | |
7c3df132 SK |
2833 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, |
2834 | "ms_iocb=%p ct_sns=%p.\n", | |
2835 | ha->ms_iocb, ha->ct_sns); | |
1da177e4 LT |
2836 | } |
2837 | ||
e315cd28 | 2838 | /* Allocate memory for request ring */ |
73208dfd AC |
2839 | *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); |
2840 | if (!*req) { | |
7c3df132 SK |
2841 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, |
2842 | "Failed to allocate memory for req.\n"); | |
e315cd28 AC |
2843 | goto fail_req; |
2844 | } | |
73208dfd AC |
2845 | (*req)->length = req_len; |
2846 | (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
2847 | ((*req)->length + 1) * sizeof(request_t), | |
2848 | &(*req)->dma, GFP_KERNEL); | |
2849 | if (!(*req)->ring) { | |
7c3df132 SK |
2850 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, |
2851 | "Failed to allocate memory for req_ring.\n"); | |
e315cd28 AC |
2852 | goto fail_req_ring; |
2853 | } | |
2854 | /* Allocate memory for response ring */ | |
73208dfd AC |
2855 | *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); |
2856 | if (!*rsp) { | |
7c3df132 SK |
2857 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, |
2858 | "Failed to allocate memory for rsp.\n"); | |
e315cd28 AC |
2859 | goto fail_rsp; |
2860 | } | |
73208dfd AC |
2861 | (*rsp)->hw = ha; |
2862 | (*rsp)->length = rsp_len; | |
2863 | (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
2864 | ((*rsp)->length + 1) * sizeof(response_t), | |
2865 | &(*rsp)->dma, GFP_KERNEL); | |
2866 | if (!(*rsp)->ring) { | |
7c3df132 SK |
2867 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, |
2868 | "Failed to allocate memory for rsp_ring.\n"); | |
e315cd28 AC |
2869 | goto fail_rsp_ring; |
2870 | } | |
73208dfd AC |
2871 | (*req)->rsp = *rsp; |
2872 | (*rsp)->req = *req; | |
7c3df132 SK |
2873 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, |
2874 | "req=%p req->length=%d req->ring=%p rsp=%p " | |
2875 | "rsp->length=%d rsp->ring=%p.\n", | |
2876 | *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, | |
2877 | (*rsp)->ring); | |
73208dfd AC |
2878 | /* Allocate memory for NVRAM data for vports */ |
2879 | if (ha->nvram_npiv_size) { | |
2880 | ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * | |
7c3df132 | 2881 | ha->nvram_npiv_size, GFP_KERNEL); |
73208dfd | 2882 | if (!ha->npiv_info) { |
7c3df132 SK |
2883 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, |
2884 | "Failed to allocate memory for npiv_info.\n"); | |
73208dfd AC |
2885 | goto fail_npiv_info; |
2886 | } | |
2887 | } else | |
2888 | ha->npiv_info = NULL; | |
e8711085 | 2889 | |
b64b0e8f | 2890 | /* Get consistent memory allocated for EX-INIT-CB. */ |
a9083016 | 2891 | if (IS_QLA8XXX_TYPE(ha)) { |
b64b0e8f AV |
2892 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
2893 | &ha->ex_init_cb_dma); | |
2894 | if (!ha->ex_init_cb) | |
2895 | goto fail_ex_init_cb; | |
7c3df132 SK |
2896 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, |
2897 | "ex_init_cb=%p.\n", ha->ex_init_cb); | |
b64b0e8f AV |
2898 | } |
2899 | ||
a9083016 GM |
2900 | INIT_LIST_HEAD(&ha->gbl_dsd_list); |
2901 | ||
5ff1d584 AV |
2902 | /* Get consistent memory allocated for Async Port-Database. */ |
2903 | if (!IS_FWI2_CAPABLE(ha)) { | |
2904 | ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | |
2905 | &ha->async_pd_dma); | |
2906 | if (!ha->async_pd) | |
2907 | goto fail_async_pd; | |
7c3df132 SK |
2908 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, |
2909 | "async_pd=%p.\n", ha->async_pd); | |
5ff1d584 AV |
2910 | } |
2911 | ||
e315cd28 AC |
2912 | INIT_LIST_HEAD(&ha->vp_list); |
2913 | return 1; | |
2914 | ||
5ff1d584 AV |
2915 | fail_async_pd: |
2916 | dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f AV |
2917 | fail_ex_init_cb: |
2918 | kfree(ha->npiv_info); | |
73208dfd AC |
2919 | fail_npiv_info: |
2920 | dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * | |
2921 | sizeof(response_t), (*rsp)->ring, (*rsp)->dma); | |
2922 | (*rsp)->ring = NULL; | |
2923 | (*rsp)->dma = 0; | |
e315cd28 | 2924 | fail_rsp_ring: |
73208dfd | 2925 | kfree(*rsp); |
e315cd28 | 2926 | fail_rsp: |
73208dfd AC |
2927 | dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * |
2928 | sizeof(request_t), (*req)->ring, (*req)->dma); | |
2929 | (*req)->ring = NULL; | |
2930 | (*req)->dma = 0; | |
e315cd28 | 2931 | fail_req_ring: |
73208dfd | 2932 | kfree(*req); |
e315cd28 AC |
2933 | fail_req: |
2934 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
2935 | ha->ct_sns, ha->ct_sns_dma); | |
2936 | ha->ct_sns = NULL; | |
2937 | ha->ct_sns_dma = 0; | |
e8711085 AV |
2938 | fail_free_ms_iocb: |
2939 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
2940 | ha->ms_iocb = NULL; | |
2941 | ha->ms_iocb_dma = 0; | |
e315cd28 | 2942 | fail_dma_pool: |
bad75002 | 2943 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
2944 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); |
2945 | ha->fcp_cmnd_dma_pool = NULL; | |
2946 | } | |
2947 | fail_dl_dma_pool: | |
bad75002 | 2948 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
2949 | dma_pool_destroy(ha->dl_dma_pool); |
2950 | ha->dl_dma_pool = NULL; | |
2951 | } | |
2952 | fail_s_dma_pool: | |
e315cd28 AC |
2953 | dma_pool_destroy(ha->s_dma_pool); |
2954 | ha->s_dma_pool = NULL; | |
e8711085 AV |
2955 | fail_free_nvram: |
2956 | kfree(ha->nvram); | |
2957 | ha->nvram = NULL; | |
a9083016 GM |
2958 | fail_free_ctx_mempool: |
2959 | mempool_destroy(ha->ctx_mempool); | |
2960 | ha->ctx_mempool = NULL; | |
e8711085 AV |
2961 | fail_free_srb_mempool: |
2962 | mempool_destroy(ha->srb_mempool); | |
2963 | ha->srb_mempool = NULL; | |
e8711085 AV |
2964 | fail_free_gid_list: |
2965 | dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, | |
e315cd28 | 2966 | ha->gid_list_dma); |
e8711085 AV |
2967 | ha->gid_list = NULL; |
2968 | ha->gid_list_dma = 0; | |
e315cd28 AC |
2969 | fail_free_init_cb: |
2970 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, | |
2971 | ha->init_cb_dma); | |
2972 | ha->init_cb = NULL; | |
2973 | ha->init_cb_dma = 0; | |
e8711085 | 2974 | fail: |
7c3df132 SK |
2975 | ql_log(ql_log_fatal, NULL, 0x0030, |
2976 | "Memory allocation failure.\n"); | |
e8711085 | 2977 | return -ENOMEM; |
1da177e4 LT |
2978 | } |
2979 | ||
2980 | /* | |
e30d1756 MI |
2981 | * qla2x00_free_fw_dump |
2982 | * Frees fw dump stuff. | |
1da177e4 LT |
2983 | * |
2984 | * Input: | |
e30d1756 | 2985 | * ha = adapter block pointer. |
1da177e4 | 2986 | */ |
a824ebb3 | 2987 | static void |
e30d1756 | 2988 | qla2x00_free_fw_dump(struct qla_hw_data *ha) |
1da177e4 | 2989 | { |
df613b96 AV |
2990 | if (ha->fce) |
2991 | dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, | |
e30d1756 | 2992 | ha->fce_dma); |
df613b96 | 2993 | |
a7a167bf AV |
2994 | if (ha->fw_dump) { |
2995 | if (ha->eft) | |
2996 | dma_free_coherent(&ha->pdev->dev, | |
e30d1756 | 2997 | ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma); |
a7a167bf AV |
2998 | vfree(ha->fw_dump); |
2999 | } | |
e30d1756 MI |
3000 | ha->fce = NULL; |
3001 | ha->fce_dma = 0; | |
3002 | ha->eft = NULL; | |
3003 | ha->eft_dma = 0; | |
3004 | ha->fw_dump = NULL; | |
3005 | ha->fw_dumped = 0; | |
3006 | ha->fw_dump_reading = 0; | |
3007 | } | |
3008 | ||
3009 | /* | |
3010 | * qla2x00_mem_free | |
3011 | * Frees all adapter allocated memory. | |
3012 | * | |
3013 | * Input: | |
3014 | * ha = adapter block pointer. | |
3015 | */ | |
3016 | static void | |
3017 | qla2x00_mem_free(struct qla_hw_data *ha) | |
3018 | { | |
3019 | qla2x00_free_fw_dump(ha); | |
3020 | ||
3021 | if (ha->srb_mempool) | |
3022 | mempool_destroy(ha->srb_mempool); | |
a7a167bf | 3023 | |
11bbc1d8 AV |
3024 | if (ha->dcbx_tlv) |
3025 | dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, | |
3026 | ha->dcbx_tlv, ha->dcbx_tlv_dma); | |
3027 | ||
ce0423f4 AV |
3028 | if (ha->xgmac_data) |
3029 | dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, | |
3030 | ha->xgmac_data, ha->xgmac_data_dma); | |
3031 | ||
1da177e4 LT |
3032 | if (ha->sns_cmd) |
3033 | dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), | |
e315cd28 | 3034 | ha->sns_cmd, ha->sns_cmd_dma); |
1da177e4 LT |
3035 | |
3036 | if (ha->ct_sns) | |
3037 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
e315cd28 | 3038 | ha->ct_sns, ha->ct_sns_dma); |
1da177e4 | 3039 | |
88729e53 AV |
3040 | if (ha->sfp_data) |
3041 | dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); | |
3042 | ||
ad0ecd61 JC |
3043 | if (ha->edc_data) |
3044 | dma_pool_free(ha->s_dma_pool, ha->edc_data, ha->edc_data_dma); | |
3045 | ||
1da177e4 LT |
3046 | if (ha->ms_iocb) |
3047 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3048 | ||
b64b0e8f | 3049 | if (ha->ex_init_cb) |
a9083016 GM |
3050 | dma_pool_free(ha->s_dma_pool, |
3051 | ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f | 3052 | |
5ff1d584 AV |
3053 | if (ha->async_pd) |
3054 | dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); | |
3055 | ||
1da177e4 LT |
3056 | if (ha->s_dma_pool) |
3057 | dma_pool_destroy(ha->s_dma_pool); | |
3058 | ||
1da177e4 LT |
3059 | if (ha->gid_list) |
3060 | dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, | |
e315cd28 | 3061 | ha->gid_list_dma); |
1da177e4 | 3062 | |
a9083016 GM |
3063 | if (IS_QLA82XX(ha)) { |
3064 | if (!list_empty(&ha->gbl_dsd_list)) { | |
3065 | struct dsd_dma *dsd_ptr, *tdsd_ptr; | |
3066 | ||
3067 | /* clean up allocated prev pool */ | |
3068 | list_for_each_entry_safe(dsd_ptr, | |
3069 | tdsd_ptr, &ha->gbl_dsd_list, list) { | |
3070 | dma_pool_free(ha->dl_dma_pool, | |
3071 | dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); | |
3072 | list_del(&dsd_ptr->list); | |
3073 | kfree(dsd_ptr); | |
3074 | } | |
3075 | } | |
3076 | } | |
3077 | ||
3078 | if (ha->dl_dma_pool) | |
3079 | dma_pool_destroy(ha->dl_dma_pool); | |
3080 | ||
3081 | if (ha->fcp_cmnd_dma_pool) | |
3082 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | |
3083 | ||
3084 | if (ha->ctx_mempool) | |
3085 | mempool_destroy(ha->ctx_mempool); | |
3086 | ||
e315cd28 AC |
3087 | if (ha->init_cb) |
3088 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, | |
a9083016 | 3089 | ha->init_cb, ha->init_cb_dma); |
e315cd28 AC |
3090 | vfree(ha->optrom_buffer); |
3091 | kfree(ha->nvram); | |
73208dfd | 3092 | kfree(ha->npiv_info); |
1da177e4 | 3093 | |
e8711085 | 3094 | ha->srb_mempool = NULL; |
a9083016 | 3095 | ha->ctx_mempool = NULL; |
1da177e4 LT |
3096 | ha->sns_cmd = NULL; |
3097 | ha->sns_cmd_dma = 0; | |
3098 | ha->ct_sns = NULL; | |
3099 | ha->ct_sns_dma = 0; | |
3100 | ha->ms_iocb = NULL; | |
3101 | ha->ms_iocb_dma = 0; | |
1da177e4 LT |
3102 | ha->init_cb = NULL; |
3103 | ha->init_cb_dma = 0; | |
b64b0e8f AV |
3104 | ha->ex_init_cb = NULL; |
3105 | ha->ex_init_cb_dma = 0; | |
5ff1d584 AV |
3106 | ha->async_pd = NULL; |
3107 | ha->async_pd_dma = 0; | |
1da177e4 LT |
3108 | |
3109 | ha->s_dma_pool = NULL; | |
a9083016 GM |
3110 | ha->dl_dma_pool = NULL; |
3111 | ha->fcp_cmnd_dma_pool = NULL; | |
1da177e4 | 3112 | |
1da177e4 LT |
3113 | ha->gid_list = NULL; |
3114 | ha->gid_list_dma = 0; | |
e315cd28 | 3115 | } |
1da177e4 | 3116 | |
e315cd28 AC |
3117 | struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, |
3118 | struct qla_hw_data *ha) | |
3119 | { | |
3120 | struct Scsi_Host *host; | |
3121 | struct scsi_qla_host *vha = NULL; | |
854165f4 | 3122 | |
e315cd28 AC |
3123 | host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); |
3124 | if (host == NULL) { | |
7c3df132 SK |
3125 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, |
3126 | "Failed to allocate host from the scsi layer, aborting.\n"); | |
e315cd28 AC |
3127 | goto fail; |
3128 | } | |
3129 | ||
3130 | /* Clear our data area */ | |
3131 | vha = shost_priv(host); | |
3132 | memset(vha, 0, sizeof(scsi_qla_host_t)); | |
3133 | ||
3134 | vha->host = host; | |
3135 | vha->host_no = host->host_no; | |
3136 | vha->hw = ha; | |
3137 | ||
3138 | INIT_LIST_HEAD(&vha->vp_fcports); | |
3139 | INIT_LIST_HEAD(&vha->work_list); | |
3140 | INIT_LIST_HEAD(&vha->list); | |
3141 | ||
f999f4c1 AV |
3142 | spin_lock_init(&vha->work_lock); |
3143 | ||
e315cd28 | 3144 | sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); |
7c3df132 SK |
3145 | ql_dbg(ql_dbg_init, vha, 0x0041, |
3146 | "Allocated the host=%p hw=%p vha=%p dev_name=%s", | |
3147 | vha->host, vha->hw, vha, | |
3148 | dev_name(&(ha->pdev->dev))); | |
3149 | ||
e315cd28 AC |
3150 | return vha; |
3151 | ||
3152 | fail: | |
3153 | return vha; | |
1da177e4 LT |
3154 | } |
3155 | ||
01ef66bb | 3156 | static struct qla_work_evt * |
f999f4c1 | 3157 | qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) |
0971de7f AV |
3158 | { |
3159 | struct qla_work_evt *e; | |
feafb7b1 AE |
3160 | uint8_t bail; |
3161 | ||
3162 | QLA_VHA_MARK_BUSY(vha, bail); | |
3163 | if (bail) | |
3164 | return NULL; | |
0971de7f | 3165 | |
f999f4c1 | 3166 | e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); |
feafb7b1 AE |
3167 | if (!e) { |
3168 | QLA_VHA_MARK_NOT_BUSY(vha); | |
0971de7f | 3169 | return NULL; |
feafb7b1 | 3170 | } |
0971de7f AV |
3171 | |
3172 | INIT_LIST_HEAD(&e->list); | |
3173 | e->type = type; | |
3174 | e->flags = QLA_EVT_FLAG_FREE; | |
3175 | return e; | |
3176 | } | |
3177 | ||
01ef66bb | 3178 | static int |
f999f4c1 | 3179 | qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) |
0971de7f | 3180 | { |
f999f4c1 | 3181 | unsigned long flags; |
0971de7f | 3182 | |
f999f4c1 | 3183 | spin_lock_irqsave(&vha->work_lock, flags); |
e315cd28 | 3184 | list_add_tail(&e->list, &vha->work_list); |
f999f4c1 | 3185 | spin_unlock_irqrestore(&vha->work_lock, flags); |
e315cd28 | 3186 | qla2xxx_wake_dpc(vha); |
f999f4c1 | 3187 | |
0971de7f AV |
3188 | return QLA_SUCCESS; |
3189 | } | |
3190 | ||
3191 | int | |
e315cd28 | 3192 | qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, |
0971de7f AV |
3193 | u32 data) |
3194 | { | |
3195 | struct qla_work_evt *e; | |
3196 | ||
f999f4c1 | 3197 | e = qla2x00_alloc_work(vha, QLA_EVT_AEN); |
0971de7f AV |
3198 | if (!e) |
3199 | return QLA_FUNCTION_FAILED; | |
3200 | ||
3201 | e->u.aen.code = code; | |
3202 | e->u.aen.data = data; | |
f999f4c1 | 3203 | return qla2x00_post_work(vha, e); |
0971de7f AV |
3204 | } |
3205 | ||
8a659571 AV |
3206 | int |
3207 | qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) | |
3208 | { | |
3209 | struct qla_work_evt *e; | |
3210 | ||
f999f4c1 | 3211 | e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); |
8a659571 AV |
3212 | if (!e) |
3213 | return QLA_FUNCTION_FAILED; | |
3214 | ||
3215 | memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); | |
f999f4c1 | 3216 | return qla2x00_post_work(vha, e); |
8a659571 AV |
3217 | } |
3218 | ||
ac280b67 AV |
3219 | #define qla2x00_post_async_work(name, type) \ |
3220 | int qla2x00_post_async_##name##_work( \ | |
3221 | struct scsi_qla_host *vha, \ | |
3222 | fc_port_t *fcport, uint16_t *data) \ | |
3223 | { \ | |
3224 | struct qla_work_evt *e; \ | |
3225 | \ | |
3226 | e = qla2x00_alloc_work(vha, type); \ | |
3227 | if (!e) \ | |
3228 | return QLA_FUNCTION_FAILED; \ | |
3229 | \ | |
3230 | e->u.logio.fcport = fcport; \ | |
3231 | if (data) { \ | |
3232 | e->u.logio.data[0] = data[0]; \ | |
3233 | e->u.logio.data[1] = data[1]; \ | |
3234 | } \ | |
3235 | return qla2x00_post_work(vha, e); \ | |
3236 | } | |
3237 | ||
3238 | qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); | |
3239 | qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); | |
3240 | qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); | |
3241 | qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); | |
5ff1d584 AV |
3242 | qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); |
3243 | qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); | |
ac280b67 | 3244 | |
3420d36c AV |
3245 | int |
3246 | qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) | |
3247 | { | |
3248 | struct qla_work_evt *e; | |
3249 | ||
3250 | e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); | |
3251 | if (!e) | |
3252 | return QLA_FUNCTION_FAILED; | |
3253 | ||
3254 | e->u.uevent.code = code; | |
3255 | return qla2x00_post_work(vha, e); | |
3256 | } | |
3257 | ||
3258 | static void | |
3259 | qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) | |
3260 | { | |
3261 | char event_string[40]; | |
3262 | char *envp[] = { event_string, NULL }; | |
3263 | ||
3264 | switch (code) { | |
3265 | case QLA_UEVENT_CODE_FW_DUMP: | |
3266 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", | |
3267 | vha->host_no); | |
3268 | break; | |
3269 | default: | |
3270 | /* do nothing */ | |
3271 | break; | |
3272 | } | |
3273 | kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); | |
3274 | } | |
3275 | ||
ac280b67 | 3276 | void |
e315cd28 | 3277 | qla2x00_do_work(struct scsi_qla_host *vha) |
0971de7f | 3278 | { |
f999f4c1 AV |
3279 | struct qla_work_evt *e, *tmp; |
3280 | unsigned long flags; | |
3281 | LIST_HEAD(work); | |
0971de7f | 3282 | |
f999f4c1 AV |
3283 | spin_lock_irqsave(&vha->work_lock, flags); |
3284 | list_splice_init(&vha->work_list, &work); | |
3285 | spin_unlock_irqrestore(&vha->work_lock, flags); | |
3286 | ||
3287 | list_for_each_entry_safe(e, tmp, &work, list) { | |
0971de7f | 3288 | list_del_init(&e->list); |
0971de7f AV |
3289 | |
3290 | switch (e->type) { | |
3291 | case QLA_EVT_AEN: | |
e315cd28 | 3292 | fc_host_post_event(vha->host, fc_get_event_number(), |
0971de7f AV |
3293 | e->u.aen.code, e->u.aen.data); |
3294 | break; | |
8a659571 AV |
3295 | case QLA_EVT_IDC_ACK: |
3296 | qla81xx_idc_ack(vha, e->u.idc_ack.mb); | |
3297 | break; | |
ac280b67 AV |
3298 | case QLA_EVT_ASYNC_LOGIN: |
3299 | qla2x00_async_login(vha, e->u.logio.fcport, | |
3300 | e->u.logio.data); | |
3301 | break; | |
3302 | case QLA_EVT_ASYNC_LOGIN_DONE: | |
3303 | qla2x00_async_login_done(vha, e->u.logio.fcport, | |
3304 | e->u.logio.data); | |
3305 | break; | |
3306 | case QLA_EVT_ASYNC_LOGOUT: | |
3307 | qla2x00_async_logout(vha, e->u.logio.fcport); | |
3308 | break; | |
3309 | case QLA_EVT_ASYNC_LOGOUT_DONE: | |
3310 | qla2x00_async_logout_done(vha, e->u.logio.fcport, | |
3311 | e->u.logio.data); | |
3312 | break; | |
5ff1d584 AV |
3313 | case QLA_EVT_ASYNC_ADISC: |
3314 | qla2x00_async_adisc(vha, e->u.logio.fcport, | |
3315 | e->u.logio.data); | |
3316 | break; | |
3317 | case QLA_EVT_ASYNC_ADISC_DONE: | |
3318 | qla2x00_async_adisc_done(vha, e->u.logio.fcport, | |
3319 | e->u.logio.data); | |
3320 | break; | |
3420d36c AV |
3321 | case QLA_EVT_UEVENT: |
3322 | qla2x00_uevent_emit(vha, e->u.uevent.code); | |
3323 | break; | |
0971de7f AV |
3324 | } |
3325 | if (e->flags & QLA_EVT_FLAG_FREE) | |
3326 | kfree(e); | |
feafb7b1 AE |
3327 | |
3328 | /* For each work completed decrement vha ref count */ | |
3329 | QLA_VHA_MARK_NOT_BUSY(vha); | |
e315cd28 | 3330 | } |
e315cd28 | 3331 | } |
f999f4c1 | 3332 | |
e315cd28 AC |
3333 | /* Relogins all the fcports of a vport |
3334 | * Context: dpc thread | |
3335 | */ | |
3336 | void qla2x00_relogin(struct scsi_qla_host *vha) | |
3337 | { | |
3338 | fc_port_t *fcport; | |
c6b2fca8 | 3339 | int status; |
e315cd28 AC |
3340 | uint16_t next_loopid = 0; |
3341 | struct qla_hw_data *ha = vha->hw; | |
ac280b67 | 3342 | uint16_t data[2]; |
e315cd28 AC |
3343 | |
3344 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3345 | /* | |
3346 | * If the port is not ONLINE then try to login | |
3347 | * to it if we haven't run out of retries. | |
3348 | */ | |
5ff1d584 AV |
3349 | if (atomic_read(&fcport->state) != FCS_ONLINE && |
3350 | fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { | |
ac280b67 | 3351 | fcport->login_retry--; |
e315cd28 | 3352 | if (fcport->flags & FCF_FABRIC_DEVICE) { |
f08b7251 | 3353 | if (fcport->flags & FCF_FCP2_DEVICE) |
e315cd28 AC |
3354 | ha->isp_ops->fabric_logout(vha, |
3355 | fcport->loop_id, | |
3356 | fcport->d_id.b.domain, | |
3357 | fcport->d_id.b.area, | |
3358 | fcport->d_id.b.al_pa); | |
3359 | ||
03bcfb57 JC |
3360 | if (fcport->loop_id == FC_NO_LOOP_ID) { |
3361 | fcport->loop_id = next_loopid = | |
3362 | ha->min_external_loopid; | |
3363 | status = qla2x00_find_new_loop_id( | |
3364 | vha, fcport); | |
3365 | if (status != QLA_SUCCESS) { | |
3366 | /* Ran out of IDs to use */ | |
3367 | break; | |
3368 | } | |
3369 | } | |
3370 | ||
ac280b67 | 3371 | if (IS_ALOGIO_CAPABLE(ha)) { |
5ff1d584 | 3372 | fcport->flags |= FCF_ASYNC_SENT; |
ac280b67 AV |
3373 | data[0] = 0; |
3374 | data[1] = QLA_LOGIO_LOGIN_RETRIED; | |
3375 | status = qla2x00_post_async_login_work( | |
3376 | vha, fcport, data); | |
3377 | if (status == QLA_SUCCESS) | |
3378 | continue; | |
3379 | /* Attempt a retry. */ | |
3380 | status = 1; | |
3381 | } else | |
3382 | status = qla2x00_fabric_login(vha, | |
3383 | fcport, &next_loopid); | |
e315cd28 AC |
3384 | } else |
3385 | status = qla2x00_local_device_login(vha, | |
3386 | fcport); | |
3387 | ||
e315cd28 AC |
3388 | if (status == QLA_SUCCESS) { |
3389 | fcport->old_loop_id = fcport->loop_id; | |
3390 | ||
7c3df132 SK |
3391 | ql_dbg(ql_dbg_disc, vha, 0x2003, |
3392 | "Port login OK: logged in ID 0x%x.\n", | |
3393 | fcport->loop_id); | |
e315cd28 AC |
3394 | |
3395 | qla2x00_update_fcport(vha, fcport); | |
3396 | ||
3397 | } else if (status == 1) { | |
3398 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
3399 | /* retry the login again */ | |
7c3df132 SK |
3400 | ql_dbg(ql_dbg_disc, vha, 0x2007, |
3401 | "Retrying %d login again loop_id 0x%x.\n", | |
3402 | fcport->login_retry, fcport->loop_id); | |
e315cd28 AC |
3403 | } else { |
3404 | fcport->login_retry = 0; | |
3405 | } | |
3406 | ||
3407 | if (fcport->login_retry == 0 && status != QLA_SUCCESS) | |
3408 | fcport->loop_id = FC_NO_LOOP_ID; | |
3409 | } | |
3410 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
3411 | break; | |
0971de7f | 3412 | } |
0971de7f AV |
3413 | } |
3414 | ||
1da177e4 LT |
3415 | /************************************************************************** |
3416 | * qla2x00_do_dpc | |
3417 | * This kernel thread is a task that is schedule by the interrupt handler | |
3418 | * to perform the background processing for interrupts. | |
3419 | * | |
3420 | * Notes: | |
3421 | * This task always run in the context of a kernel thread. It | |
3422 | * is kick-off by the driver's detect code and starts up | |
3423 | * up one per adapter. It immediately goes to sleep and waits for | |
3424 | * some fibre event. When either the interrupt handler or | |
3425 | * the timer routine detects a event it will one of the task | |
3426 | * bits then wake us up. | |
3427 | **************************************************************************/ | |
3428 | static int | |
3429 | qla2x00_do_dpc(void *data) | |
3430 | { | |
2c3dfe3f | 3431 | int rval; |
e315cd28 AC |
3432 | scsi_qla_host_t *base_vha; |
3433 | struct qla_hw_data *ha; | |
1da177e4 | 3434 | |
e315cd28 AC |
3435 | ha = (struct qla_hw_data *)data; |
3436 | base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 3437 | |
1da177e4 LT |
3438 | set_user_nice(current, -20); |
3439 | ||
563585ec | 3440 | set_current_state(TASK_INTERRUPTIBLE); |
39a11240 | 3441 | while (!kthread_should_stop()) { |
7c3df132 SK |
3442 | ql_dbg(ql_dbg_dpc, base_vha, 0x4000, |
3443 | "DPC handler sleeping.\n"); | |
1da177e4 | 3444 | |
39a11240 CH |
3445 | schedule(); |
3446 | __set_current_state(TASK_RUNNING); | |
1da177e4 | 3447 | |
c142caf0 AV |
3448 | if (!base_vha->flags.init_done || ha->flags.mbox_busy) |
3449 | goto end_loop; | |
1da177e4 | 3450 | |
85880801 | 3451 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
3452 | ql_dbg(ql_dbg_dpc, base_vha, 0x4003, |
3453 | "eeh_busy=%d.\n", ha->flags.eeh_busy); | |
c142caf0 | 3454 | goto end_loop; |
85880801 AV |
3455 | } |
3456 | ||
1da177e4 LT |
3457 | ha->dpc_active = 1; |
3458 | ||
c142caf0 AV |
3459 | ql_dbg(ql_dbg_dpc, base_vha, 0x4001, |
3460 | "DPC handler waking up.\n"); | |
3461 | ql_dbg(ql_dbg_dpc, base_vha, 0x4002, | |
3462 | "dpc_flags=0x%lx.\n", base_vha->dpc_flags); | |
1da177e4 | 3463 | |
e315cd28 | 3464 | qla2x00_do_work(base_vha); |
0971de7f | 3465 | |
a9083016 GM |
3466 | if (IS_QLA82XX(ha)) { |
3467 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
3468 | &base_vha->dpc_flags)) { | |
3469 | qla82xx_idc_lock(ha); | |
3470 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
3471 | QLA82XX_DEV_FAILED); | |
3472 | qla82xx_idc_unlock(ha); | |
7c3df132 SK |
3473 | ql_log(ql_log_info, base_vha, 0x4004, |
3474 | "HW State: FAILED.\n"); | |
a9083016 GM |
3475 | qla82xx_device_state_handler(base_vha); |
3476 | continue; | |
3477 | } | |
3478 | ||
3479 | if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, | |
3480 | &base_vha->dpc_flags)) { | |
3481 | ||
7c3df132 SK |
3482 | ql_dbg(ql_dbg_dpc, base_vha, 0x4005, |
3483 | "FCoE context reset scheduled.\n"); | |
a9083016 GM |
3484 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
3485 | &base_vha->dpc_flags))) { | |
3486 | if (qla82xx_fcoe_ctx_reset(base_vha)) { | |
3487 | /* FCoE-ctx reset failed. | |
3488 | * Escalate to chip-reset | |
3489 | */ | |
3490 | set_bit(ISP_ABORT_NEEDED, | |
3491 | &base_vha->dpc_flags); | |
3492 | } | |
3493 | clear_bit(ABORT_ISP_ACTIVE, | |
3494 | &base_vha->dpc_flags); | |
3495 | } | |
3496 | ||
7c3df132 SK |
3497 | ql_dbg(ql_dbg_dpc, base_vha, 0x4006, |
3498 | "FCoE context reset end.\n"); | |
a9083016 GM |
3499 | } |
3500 | } | |
3501 | ||
e315cd28 AC |
3502 | if (test_and_clear_bit(ISP_ABORT_NEEDED, |
3503 | &base_vha->dpc_flags)) { | |
1da177e4 | 3504 | |
7c3df132 SK |
3505 | ql_dbg(ql_dbg_dpc, base_vha, 0x4007, |
3506 | "ISP abort scheduled.\n"); | |
1da177e4 | 3507 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
e315cd28 | 3508 | &base_vha->dpc_flags))) { |
1da177e4 | 3509 | |
a9083016 | 3510 | if (ha->isp_ops->abort_isp(base_vha)) { |
1da177e4 LT |
3511 | /* failed. retry later */ |
3512 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 3513 | &base_vha->dpc_flags); |
99363ef8 | 3514 | } |
e315cd28 AC |
3515 | clear_bit(ABORT_ISP_ACTIVE, |
3516 | &base_vha->dpc_flags); | |
99363ef8 SJ |
3517 | } |
3518 | ||
7c3df132 SK |
3519 | ql_dbg(ql_dbg_dpc, base_vha, 0x4008, |
3520 | "ISP abort end.\n"); | |
1da177e4 LT |
3521 | } |
3522 | ||
e315cd28 AC |
3523 | if (test_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags)) { |
3524 | qla2x00_update_fcports(base_vha); | |
3525 | clear_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); | |
c9c5ced9 | 3526 | } |
d97994dc | 3527 | |
579d12b5 | 3528 | if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { |
7c3df132 SK |
3529 | ql_dbg(ql_dbg_dpc, base_vha, 0x4009, |
3530 | "Quiescence mode scheduled.\n"); | |
579d12b5 SK |
3531 | qla82xx_device_state_handler(base_vha); |
3532 | clear_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags); | |
3533 | if (!ha->flags.quiesce_owner) { | |
3534 | qla2x00_perform_loop_resync(base_vha); | |
3535 | ||
3536 | qla82xx_idc_lock(ha); | |
3537 | qla82xx_clear_qsnt_ready(base_vha); | |
3538 | qla82xx_idc_unlock(ha); | |
3539 | } | |
7c3df132 SK |
3540 | ql_dbg(ql_dbg_dpc, base_vha, 0x400a, |
3541 | "Quiescence mode end.\n"); | |
579d12b5 SK |
3542 | } |
3543 | ||
e315cd28 AC |
3544 | if (test_and_clear_bit(RESET_MARKER_NEEDED, |
3545 | &base_vha->dpc_flags) && | |
3546 | (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { | |
1da177e4 | 3547 | |
7c3df132 SK |
3548 | ql_dbg(ql_dbg_dpc, base_vha, 0x400b, |
3549 | "Reset marker scheduled.\n"); | |
e315cd28 AC |
3550 | qla2x00_rst_aen(base_vha); |
3551 | clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); | |
7c3df132 SK |
3552 | ql_dbg(ql_dbg_dpc, base_vha, 0x400c, |
3553 | "Reset marker end.\n"); | |
1da177e4 LT |
3554 | } |
3555 | ||
3556 | /* Retry each device up to login retry count */ | |
e315cd28 AC |
3557 | if ((test_and_clear_bit(RELOGIN_NEEDED, |
3558 | &base_vha->dpc_flags)) && | |
3559 | !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && | |
3560 | atomic_read(&base_vha->loop_state) != LOOP_DOWN) { | |
1da177e4 | 3561 | |
7c3df132 SK |
3562 | ql_dbg(ql_dbg_dpc, base_vha, 0x400d, |
3563 | "Relogin scheduled.\n"); | |
e315cd28 | 3564 | qla2x00_relogin(base_vha); |
7c3df132 SK |
3565 | ql_dbg(ql_dbg_dpc, base_vha, 0x400e, |
3566 | "Relogin end.\n"); | |
1da177e4 LT |
3567 | } |
3568 | ||
e315cd28 AC |
3569 | if (test_and_clear_bit(LOOP_RESYNC_NEEDED, |
3570 | &base_vha->dpc_flags)) { | |
1da177e4 | 3571 | |
7c3df132 SK |
3572 | ql_dbg(ql_dbg_dpc, base_vha, 0x400f, |
3573 | "Loop resync scheduled.\n"); | |
1da177e4 LT |
3574 | |
3575 | if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, | |
e315cd28 | 3576 | &base_vha->dpc_flags))) { |
1da177e4 | 3577 | |
e315cd28 | 3578 | rval = qla2x00_loop_resync(base_vha); |
1da177e4 | 3579 | |
e315cd28 AC |
3580 | clear_bit(LOOP_RESYNC_ACTIVE, |
3581 | &base_vha->dpc_flags); | |
1da177e4 LT |
3582 | } |
3583 | ||
7c3df132 SK |
3584 | ql_dbg(ql_dbg_dpc, base_vha, 0x4010, |
3585 | "Loop resync end.\n"); | |
1da177e4 LT |
3586 | } |
3587 | ||
e315cd28 AC |
3588 | if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && |
3589 | atomic_read(&base_vha->loop_state) == LOOP_READY) { | |
3590 | clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); | |
3591 | qla2xxx_flash_npiv_conf(base_vha); | |
272976ca AV |
3592 | } |
3593 | ||
1da177e4 | 3594 | if (!ha->interrupts_on) |
fd34f556 | 3595 | ha->isp_ops->enable_intrs(ha); |
1da177e4 | 3596 | |
e315cd28 AC |
3597 | if (test_and_clear_bit(BEACON_BLINK_NEEDED, |
3598 | &base_vha->dpc_flags)) | |
3599 | ha->isp_ops->beacon_blink(base_vha); | |
f6df144c | 3600 | |
e315cd28 | 3601 | qla2x00_do_dpc_all_vps(base_vha); |
2c3dfe3f | 3602 | |
1da177e4 | 3603 | ha->dpc_active = 0; |
c142caf0 | 3604 | end_loop: |
563585ec | 3605 | set_current_state(TASK_INTERRUPTIBLE); |
1da177e4 | 3606 | } /* End of while(1) */ |
563585ec | 3607 | __set_current_state(TASK_RUNNING); |
1da177e4 | 3608 | |
7c3df132 SK |
3609 | ql_dbg(ql_dbg_dpc, base_vha, 0x4011, |
3610 | "DPC handler exiting.\n"); | |
1da177e4 LT |
3611 | |
3612 | /* | |
3613 | * Make sure that nobody tries to wake us up again. | |
3614 | */ | |
1da177e4 LT |
3615 | ha->dpc_active = 0; |
3616 | ||
ac280b67 AV |
3617 | /* Cleanup any residual CTX SRBs. */ |
3618 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
3619 | ||
39a11240 CH |
3620 | return 0; |
3621 | } | |
3622 | ||
3623 | void | |
e315cd28 | 3624 | qla2xxx_wake_dpc(struct scsi_qla_host *vha) |
39a11240 | 3625 | { |
e315cd28 | 3626 | struct qla_hw_data *ha = vha->hw; |
c795c1e4 AV |
3627 | struct task_struct *t = ha->dpc_thread; |
3628 | ||
e315cd28 | 3629 | if (!test_bit(UNLOADING, &vha->dpc_flags) && t) |
c795c1e4 | 3630 | wake_up_process(t); |
1da177e4 LT |
3631 | } |
3632 | ||
1da177e4 LT |
3633 | /* |
3634 | * qla2x00_rst_aen | |
3635 | * Processes asynchronous reset. | |
3636 | * | |
3637 | * Input: | |
3638 | * ha = adapter block pointer. | |
3639 | */ | |
3640 | static void | |
e315cd28 | 3641 | qla2x00_rst_aen(scsi_qla_host_t *vha) |
1da177e4 | 3642 | { |
e315cd28 AC |
3643 | if (vha->flags.online && !vha->flags.reset_active && |
3644 | !atomic_read(&vha->loop_down_timer) && | |
3645 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { | |
1da177e4 | 3646 | do { |
e315cd28 | 3647 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
3648 | |
3649 | /* | |
3650 | * Issue marker command only when we are going to start | |
3651 | * the I/O. | |
3652 | */ | |
e315cd28 AC |
3653 | vha->marker_needed = 1; |
3654 | } while (!atomic_read(&vha->loop_down_timer) && | |
3655 | (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); | |
1da177e4 LT |
3656 | } |
3657 | } | |
3658 | ||
f4f051eb | 3659 | static void |
e315cd28 | 3660 | qla2x00_sp_free_dma(srb_t *sp) |
f4f051eb AV |
3661 | { |
3662 | struct scsi_cmnd *cmd = sp->cmd; | |
bad75002 | 3663 | struct qla_hw_data *ha = sp->fcport->vha->hw; |
f4f051eb AV |
3664 | |
3665 | if (sp->flags & SRB_DMA_VALID) { | |
385d70b4 | 3666 | scsi_dma_unmap(cmd); |
f4f051eb AV |
3667 | sp->flags &= ~SRB_DMA_VALID; |
3668 | } | |
bad75002 AE |
3669 | |
3670 | if (sp->flags & SRB_CRC_PROT_DMA_VALID) { | |
3671 | dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), | |
3672 | scsi_prot_sg_count(cmd), cmd->sc_data_direction); | |
3673 | sp->flags &= ~SRB_CRC_PROT_DMA_VALID; | |
3674 | } | |
3675 | ||
3676 | if (sp->flags & SRB_CRC_CTX_DSD_VALID) { | |
3677 | /* List assured to be having elements */ | |
3678 | qla2x00_clean_dsd_pool(ha, sp); | |
3679 | sp->flags &= ~SRB_CRC_CTX_DSD_VALID; | |
3680 | } | |
3681 | ||
3682 | if (sp->flags & SRB_CRC_CTX_DMA_VALID) { | |
3683 | dma_pool_free(ha->dl_dma_pool, sp->ctx, | |
3684 | ((struct crc_context *)sp->ctx)->crc_ctx_dma); | |
3685 | sp->flags &= ~SRB_CRC_CTX_DMA_VALID; | |
3686 | } | |
3687 | ||
a9083016 GM |
3688 | if (sp->flags & SRB_FCP_CMND_DMA_VALID) { |
3689 | struct ct6_dsd *ctx = sp->ctx; | |
3690 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, | |
3691 | ctx->fcp_cmnd_dma); | |
3692 | list_splice(&ctx->dsd_list, &ha->gbl_dsd_list); | |
3693 | ha->gbl_dsd_inuse -= ctx->dsd_use_cnt; | |
3694 | ha->gbl_dsd_avail += ctx->dsd_use_cnt; | |
3695 | mempool_free(sp->ctx, ha->ctx_mempool); | |
3696 | sp->ctx = NULL; | |
3697 | } | |
f4f051eb | 3698 | |
c4631191 GM |
3699 | CMD_SP(cmd) = NULL; |
3700 | } | |
3701 | ||
3702 | static void | |
3703 | qla2x00_sp_final_compl(struct qla_hw_data *ha, srb_t *sp) | |
3704 | { | |
3705 | struct scsi_cmnd *cmd = sp->cmd; | |
3706 | ||
3707 | qla2x00_sp_free_dma(sp); | |
a9083016 | 3708 | mempool_free(sp, ha->srb_mempool); |
f4f051eb AV |
3709 | cmd->scsi_done(cmd); |
3710 | } | |
bdf79621 | 3711 | |
083a469d GM |
3712 | void |
3713 | qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp) | |
3714 | { | |
3715 | if (atomic_read(&sp->ref_count) == 0) { | |
7c3df132 SK |
3716 | ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, |
3717 | "SP reference-count to ZERO -- sp=%p cmd=%p.\n", | |
3718 | sp, sp->cmd); | |
3719 | if (ql2xextended_error_logging & ql_dbg_io) | |
3720 | BUG(); | |
083a469d GM |
3721 | return; |
3722 | } | |
3723 | if (!atomic_dec_and_test(&sp->ref_count)) | |
3724 | return; | |
3725 | qla2x00_sp_final_compl(ha, sp); | |
3726 | } | |
3727 | ||
1da177e4 LT |
3728 | /************************************************************************** |
3729 | * qla2x00_timer | |
3730 | * | |
3731 | * Description: | |
3732 | * One second timer | |
3733 | * | |
3734 | * Context: Interrupt | |
3735 | ***************************************************************************/ | |
2c3dfe3f | 3736 | void |
e315cd28 | 3737 | qla2x00_timer(scsi_qla_host_t *vha) |
1da177e4 | 3738 | { |
1da177e4 | 3739 | unsigned long cpu_flags = 0; |
1da177e4 LT |
3740 | int start_dpc = 0; |
3741 | int index; | |
3742 | srb_t *sp; | |
85880801 | 3743 | uint16_t w; |
e315cd28 | 3744 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 3745 | struct req_que *req; |
85880801 | 3746 | |
a5b36321 | 3747 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
3748 | ql_dbg(ql_dbg_timer, vha, 0x6000, |
3749 | "EEH = %d, restarting timer.\n", | |
3750 | ha->flags.eeh_busy); | |
a5b36321 LC |
3751 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
3752 | return; | |
3753 | } | |
3754 | ||
85880801 AV |
3755 | /* Hardware read to raise pending EEH errors during mailbox waits. */ |
3756 | if (!pci_channel_offline(ha->pdev)) | |
3757 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); | |
1da177e4 | 3758 | |
cefcaba6 SK |
3759 | /* Make sure qla82xx_watchdog is run only for physical port */ |
3760 | if (!vha->vp_idx && IS_QLA82XX(ha)) { | |
579d12b5 SK |
3761 | if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) |
3762 | start_dpc++; | |
3763 | qla82xx_watchdog(vha); | |
3764 | } | |
3765 | ||
1da177e4 | 3766 | /* Loop down handler. */ |
e315cd28 | 3767 | if (atomic_read(&vha->loop_down_timer) > 0 && |
8f7daead GM |
3768 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && |
3769 | !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) | |
e315cd28 | 3770 | && vha->flags.online) { |
1da177e4 | 3771 | |
e315cd28 AC |
3772 | if (atomic_read(&vha->loop_down_timer) == |
3773 | vha->loop_down_abort_time) { | |
1da177e4 | 3774 | |
7c3df132 SK |
3775 | ql_log(ql_log_info, vha, 0x6008, |
3776 | "Loop down - aborting the queues before time expires.\n"); | |
1da177e4 | 3777 | |
e315cd28 AC |
3778 | if (!IS_QLA2100(ha) && vha->link_down_timeout) |
3779 | atomic_set(&vha->loop_state, LOOP_DEAD); | |
1da177e4 | 3780 | |
f08b7251 AV |
3781 | /* |
3782 | * Schedule an ISP abort to return any FCP2-device | |
3783 | * commands. | |
3784 | */ | |
2c3dfe3f | 3785 | /* NPIV - scan physical port only */ |
e315cd28 | 3786 | if (!vha->vp_idx) { |
2c3dfe3f SJ |
3787 | spin_lock_irqsave(&ha->hardware_lock, |
3788 | cpu_flags); | |
73208dfd | 3789 | req = ha->req_q_map[0]; |
2c3dfe3f SJ |
3790 | for (index = 1; |
3791 | index < MAX_OUTSTANDING_COMMANDS; | |
3792 | index++) { | |
3793 | fc_port_t *sfcp; | |
3794 | ||
e315cd28 | 3795 | sp = req->outstanding_cmds[index]; |
2c3dfe3f SJ |
3796 | if (!sp) |
3797 | continue; | |
bad75002 | 3798 | if (sp->ctx && !IS_PROT_IO(sp)) |
cf53b069 | 3799 | continue; |
2c3dfe3f | 3800 | sfcp = sp->fcport; |
f08b7251 | 3801 | if (!(sfcp->flags & FCF_FCP2_DEVICE)) |
2c3dfe3f | 3802 | continue; |
bdf79621 | 3803 | |
8f7daead GM |
3804 | if (IS_QLA82XX(ha)) |
3805 | set_bit(FCOE_CTX_RESET_NEEDED, | |
3806 | &vha->dpc_flags); | |
3807 | else | |
3808 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 3809 | &vha->dpc_flags); |
2c3dfe3f SJ |
3810 | break; |
3811 | } | |
3812 | spin_unlock_irqrestore(&ha->hardware_lock, | |
e315cd28 | 3813 | cpu_flags); |
1da177e4 | 3814 | } |
1da177e4 LT |
3815 | start_dpc++; |
3816 | } | |
3817 | ||
3818 | /* if the loop has been down for 4 minutes, reinit adapter */ | |
e315cd28 | 3819 | if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { |
0d6e61bc | 3820 | if (!(vha->device_flags & DFLG_NO_CABLE)) { |
7c3df132 | 3821 | ql_log(ql_log_warn, vha, 0x6009, |
1da177e4 LT |
3822 | "Loop down - aborting ISP.\n"); |
3823 | ||
8f7daead GM |
3824 | if (IS_QLA82XX(ha)) |
3825 | set_bit(FCOE_CTX_RESET_NEEDED, | |
3826 | &vha->dpc_flags); | |
3827 | else | |
3828 | set_bit(ISP_ABORT_NEEDED, | |
3829 | &vha->dpc_flags); | |
1da177e4 LT |
3830 | } |
3831 | } | |
7c3df132 SK |
3832 | ql_dbg(ql_dbg_timer, vha, 0x600a, |
3833 | "Loop down - seconds remaining %d.\n", | |
3834 | atomic_read(&vha->loop_down_timer)); | |
1da177e4 LT |
3835 | } |
3836 | ||
cefcaba6 SK |
3837 | /* Check if beacon LED needs to be blinked for physical host only */ |
3838 | if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { | |
999916dc SK |
3839 | /* There is no beacon_blink function for ISP82xx */ |
3840 | if (!IS_QLA82XX(ha)) { | |
3841 | set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); | |
3842 | start_dpc++; | |
3843 | } | |
f6df144c AV |
3844 | } |
3845 | ||
550bf57d | 3846 | /* Process any deferred work. */ |
e315cd28 | 3847 | if (!list_empty(&vha->work_list)) |
550bf57d AV |
3848 | start_dpc++; |
3849 | ||
1da177e4 | 3850 | /* Schedule the DPC routine if needed */ |
e315cd28 AC |
3851 | if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || |
3852 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || | |
3853 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || | |
1da177e4 | 3854 | start_dpc || |
e315cd28 AC |
3855 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || |
3856 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || | |
a9083016 GM |
3857 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || |
3858 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | |
e315cd28 | 3859 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || |
7c3df132 SK |
3860 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { |
3861 | ql_dbg(ql_dbg_timer, vha, 0x600b, | |
3862 | "isp_abort_needed=%d loop_resync_needed=%d " | |
3863 | "fcport_update_needed=%d start_dpc=%d " | |
3864 | "reset_marker_needed=%d", | |
3865 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), | |
3866 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), | |
3867 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), | |
3868 | start_dpc, | |
3869 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); | |
3870 | ql_dbg(ql_dbg_timer, vha, 0x600c, | |
3871 | "beacon_blink_needed=%d isp_unrecoverable=%d " | |
3872 | "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " | |
3873 | "relogin_needed=%d.\n", | |
3874 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), | |
3875 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), | |
3876 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), | |
3877 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags), | |
3878 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); | |
e315cd28 | 3879 | qla2xxx_wake_dpc(vha); |
7c3df132 | 3880 | } |
1da177e4 | 3881 | |
e315cd28 | 3882 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
1da177e4 LT |
3883 | } |
3884 | ||
5433383e AV |
3885 | /* Firmware interface routines. */ |
3886 | ||
a9083016 | 3887 | #define FW_BLOBS 8 |
5433383e AV |
3888 | #define FW_ISP21XX 0 |
3889 | #define FW_ISP22XX 1 | |
3890 | #define FW_ISP2300 2 | |
3891 | #define FW_ISP2322 3 | |
48c02fde | 3892 | #define FW_ISP24XX 4 |
c3a2f0df | 3893 | #define FW_ISP25XX 5 |
3a03eb79 | 3894 | #define FW_ISP81XX 6 |
a9083016 | 3895 | #define FW_ISP82XX 7 |
5433383e | 3896 | |
bb8ee499 AV |
3897 | #define FW_FILE_ISP21XX "ql2100_fw.bin" |
3898 | #define FW_FILE_ISP22XX "ql2200_fw.bin" | |
3899 | #define FW_FILE_ISP2300 "ql2300_fw.bin" | |
3900 | #define FW_FILE_ISP2322 "ql2322_fw.bin" | |
3901 | #define FW_FILE_ISP24XX "ql2400_fw.bin" | |
c3a2f0df | 3902 | #define FW_FILE_ISP25XX "ql2500_fw.bin" |
3a03eb79 | 3903 | #define FW_FILE_ISP81XX "ql8100_fw.bin" |
a9083016 | 3904 | #define FW_FILE_ISP82XX "ql8200_fw.bin" |
bb8ee499 | 3905 | |
e1e82b6f | 3906 | static DEFINE_MUTEX(qla_fw_lock); |
5433383e AV |
3907 | |
3908 | static struct fw_blob qla_fw_blobs[FW_BLOBS] = { | |
bb8ee499 AV |
3909 | { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, |
3910 | { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, | |
3911 | { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, | |
3912 | { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, | |
3913 | { .name = FW_FILE_ISP24XX, }, | |
c3a2f0df | 3914 | { .name = FW_FILE_ISP25XX, }, |
3a03eb79 | 3915 | { .name = FW_FILE_ISP81XX, }, |
a9083016 | 3916 | { .name = FW_FILE_ISP82XX, }, |
5433383e AV |
3917 | }; |
3918 | ||
3919 | struct fw_blob * | |
e315cd28 | 3920 | qla2x00_request_firmware(scsi_qla_host_t *vha) |
5433383e | 3921 | { |
e315cd28 | 3922 | struct qla_hw_data *ha = vha->hw; |
5433383e AV |
3923 | struct fw_blob *blob; |
3924 | ||
3925 | blob = NULL; | |
3926 | if (IS_QLA2100(ha)) { | |
3927 | blob = &qla_fw_blobs[FW_ISP21XX]; | |
3928 | } else if (IS_QLA2200(ha)) { | |
3929 | blob = &qla_fw_blobs[FW_ISP22XX]; | |
48c02fde | 3930 | } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { |
5433383e | 3931 | blob = &qla_fw_blobs[FW_ISP2300]; |
48c02fde | 3932 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { |
5433383e | 3933 | blob = &qla_fw_blobs[FW_ISP2322]; |
4d4df193 | 3934 | } else if (IS_QLA24XX_TYPE(ha)) { |
5433383e | 3935 | blob = &qla_fw_blobs[FW_ISP24XX]; |
c3a2f0df AV |
3936 | } else if (IS_QLA25XX(ha)) { |
3937 | blob = &qla_fw_blobs[FW_ISP25XX]; | |
3a03eb79 AV |
3938 | } else if (IS_QLA81XX(ha)) { |
3939 | blob = &qla_fw_blobs[FW_ISP81XX]; | |
a9083016 GM |
3940 | } else if (IS_QLA82XX(ha)) { |
3941 | blob = &qla_fw_blobs[FW_ISP82XX]; | |
5433383e AV |
3942 | } |
3943 | ||
e1e82b6f | 3944 | mutex_lock(&qla_fw_lock); |
5433383e AV |
3945 | if (blob->fw) |
3946 | goto out; | |
3947 | ||
3948 | if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { | |
7c3df132 SK |
3949 | ql_log(ql_log_warn, vha, 0x0063, |
3950 | "Failed to load firmware image (%s).\n", blob->name); | |
5433383e AV |
3951 | blob->fw = NULL; |
3952 | blob = NULL; | |
3953 | goto out; | |
3954 | } | |
3955 | ||
3956 | out: | |
e1e82b6f | 3957 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
3958 | return blob; |
3959 | } | |
3960 | ||
3961 | static void | |
3962 | qla2x00_release_firmware(void) | |
3963 | { | |
3964 | int idx; | |
3965 | ||
e1e82b6f | 3966 | mutex_lock(&qla_fw_lock); |
5433383e AV |
3967 | for (idx = 0; idx < FW_BLOBS; idx++) |
3968 | if (qla_fw_blobs[idx].fw) | |
3969 | release_firmware(qla_fw_blobs[idx].fw); | |
e1e82b6f | 3970 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
3971 | } |
3972 | ||
14e660e6 SJ |
3973 | static pci_ers_result_t |
3974 | qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
3975 | { | |
85880801 AV |
3976 | scsi_qla_host_t *vha = pci_get_drvdata(pdev); |
3977 | struct qla_hw_data *ha = vha->hw; | |
3978 | ||
7c3df132 SK |
3979 | ql_dbg(ql_dbg_aer, vha, 0x9000, |
3980 | "PCI error detected, state %x.\n", state); | |
b9b12f73 | 3981 | |
14e660e6 SJ |
3982 | switch (state) { |
3983 | case pci_channel_io_normal: | |
85880801 | 3984 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
3985 | return PCI_ERS_RESULT_CAN_RECOVER; |
3986 | case pci_channel_io_frozen: | |
85880801 | 3987 | ha->flags.eeh_busy = 1; |
a5b36321 LC |
3988 | /* For ISP82XX complete any pending mailbox cmd */ |
3989 | if (IS_QLA82XX(ha)) { | |
7190575f | 3990 | ha->flags.isp82xx_fw_hung = 1; |
c8f6544e CD |
3991 | ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); |
3992 | qla82xx_clear_pending_mbx(vha); | |
a5b36321 | 3993 | } |
90a86fc0 | 3994 | qla2x00_free_irqs(vha); |
14e660e6 | 3995 | pci_disable_device(pdev); |
bddd2d65 LC |
3996 | /* Return back all IOs */ |
3997 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
14e660e6 SJ |
3998 | return PCI_ERS_RESULT_NEED_RESET; |
3999 | case pci_channel_io_perm_failure: | |
85880801 AV |
4000 | ha->flags.pci_channel_io_perm_failure = 1; |
4001 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
14e660e6 SJ |
4002 | return PCI_ERS_RESULT_DISCONNECT; |
4003 | } | |
4004 | return PCI_ERS_RESULT_NEED_RESET; | |
4005 | } | |
4006 | ||
4007 | static pci_ers_result_t | |
4008 | qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) | |
4009 | { | |
4010 | int risc_paused = 0; | |
4011 | uint32_t stat; | |
4012 | unsigned long flags; | |
e315cd28 AC |
4013 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
4014 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
4015 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
4016 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
4017 | ||
bcc5b6d3 SK |
4018 | if (IS_QLA82XX(ha)) |
4019 | return PCI_ERS_RESULT_RECOVERED; | |
4020 | ||
14e660e6 SJ |
4021 | spin_lock_irqsave(&ha->hardware_lock, flags); |
4022 | if (IS_QLA2100(ha) || IS_QLA2200(ha)){ | |
4023 | stat = RD_REG_DWORD(®->hccr); | |
4024 | if (stat & HCCR_RISC_PAUSE) | |
4025 | risc_paused = 1; | |
4026 | } else if (IS_QLA23XX(ha)) { | |
4027 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
4028 | if (stat & HSR_RISC_PAUSED) | |
4029 | risc_paused = 1; | |
4030 | } else if (IS_FWI2_CAPABLE(ha)) { | |
4031 | stat = RD_REG_DWORD(®24->host_status); | |
4032 | if (stat & HSRX_RISC_PAUSED) | |
4033 | risc_paused = 1; | |
4034 | } | |
4035 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
4036 | ||
4037 | if (risc_paused) { | |
7c3df132 SK |
4038 | ql_log(ql_log_info, base_vha, 0x9003, |
4039 | "RISC paused -- mmio_enabled, Dumping firmware.\n"); | |
e315cd28 | 4040 | ha->isp_ops->fw_dump(base_vha, 0); |
14e660e6 SJ |
4041 | |
4042 | return PCI_ERS_RESULT_NEED_RESET; | |
4043 | } else | |
4044 | return PCI_ERS_RESULT_RECOVERED; | |
4045 | } | |
4046 | ||
a5b36321 LC |
4047 | uint32_t qla82xx_error_recovery(scsi_qla_host_t *base_vha) |
4048 | { | |
4049 | uint32_t rval = QLA_FUNCTION_FAILED; | |
4050 | uint32_t drv_active = 0; | |
4051 | struct qla_hw_data *ha = base_vha->hw; | |
4052 | int fn; | |
4053 | struct pci_dev *other_pdev = NULL; | |
4054 | ||
7c3df132 SK |
4055 | ql_dbg(ql_dbg_aer, base_vha, 0x9006, |
4056 | "Entered %s.\n", __func__); | |
a5b36321 LC |
4057 | |
4058 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
4059 | ||
4060 | if (base_vha->flags.online) { | |
4061 | /* Abort all outstanding commands, | |
4062 | * so as to be requeued later */ | |
4063 | qla2x00_abort_isp_cleanup(base_vha); | |
4064 | } | |
4065 | ||
4066 | ||
4067 | fn = PCI_FUNC(ha->pdev->devfn); | |
4068 | while (fn > 0) { | |
4069 | fn--; | |
7c3df132 SK |
4070 | ql_dbg(ql_dbg_aer, base_vha, 0x9007, |
4071 | "Finding pci device at function = 0x%x.\n", fn); | |
a5b36321 LC |
4072 | other_pdev = |
4073 | pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), | |
4074 | ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), | |
4075 | fn)); | |
4076 | ||
4077 | if (!other_pdev) | |
4078 | continue; | |
4079 | if (atomic_read(&other_pdev->enable_cnt)) { | |
7c3df132 SK |
4080 | ql_dbg(ql_dbg_aer, base_vha, 0x9008, |
4081 | "Found PCI func available and enable at 0x%x.\n", | |
4082 | fn); | |
a5b36321 LC |
4083 | pci_dev_put(other_pdev); |
4084 | break; | |
4085 | } | |
4086 | pci_dev_put(other_pdev); | |
4087 | } | |
4088 | ||
4089 | if (!fn) { | |
4090 | /* Reset owner */ | |
7c3df132 SK |
4091 | ql_dbg(ql_dbg_aer, base_vha, 0x9009, |
4092 | "This devfn is reset owner = 0x%x.\n", | |
4093 | ha->pdev->devfn); | |
a5b36321 LC |
4094 | qla82xx_idc_lock(ha); |
4095 | ||
4096 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
4097 | QLA82XX_DEV_INITIALIZING); | |
4098 | ||
4099 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, | |
4100 | QLA82XX_IDC_VERSION); | |
4101 | ||
4102 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
7c3df132 SK |
4103 | ql_dbg(ql_dbg_aer, base_vha, 0x900a, |
4104 | "drv_active = 0x%x.\n", drv_active); | |
a5b36321 LC |
4105 | |
4106 | qla82xx_idc_unlock(ha); | |
4107 | /* Reset if device is not already reset | |
4108 | * drv_active would be 0 if a reset has already been done | |
4109 | */ | |
4110 | if (drv_active) | |
4111 | rval = qla82xx_start_firmware(base_vha); | |
4112 | else | |
4113 | rval = QLA_SUCCESS; | |
4114 | qla82xx_idc_lock(ha); | |
4115 | ||
4116 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
4117 | ql_log(ql_log_info, base_vha, 0x900b, |
4118 | "HW State: FAILED.\n"); | |
a5b36321 LC |
4119 | qla82xx_clear_drv_active(ha); |
4120 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
4121 | QLA82XX_DEV_FAILED); | |
4122 | } else { | |
7c3df132 SK |
4123 | ql_log(ql_log_info, base_vha, 0x900c, |
4124 | "HW State: READY.\n"); | |
a5b36321 LC |
4125 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
4126 | QLA82XX_DEV_READY); | |
4127 | qla82xx_idc_unlock(ha); | |
7190575f | 4128 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
4129 | rval = qla82xx_restart_isp(base_vha); |
4130 | qla82xx_idc_lock(ha); | |
4131 | /* Clear driver state register */ | |
4132 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | |
4133 | qla82xx_set_drv_active(base_vha); | |
4134 | } | |
4135 | qla82xx_idc_unlock(ha); | |
4136 | } else { | |
7c3df132 SK |
4137 | ql_dbg(ql_dbg_aer, base_vha, 0x900d, |
4138 | "This devfn is not reset owner = 0x%x.\n", | |
4139 | ha->pdev->devfn); | |
a5b36321 LC |
4140 | if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == |
4141 | QLA82XX_DEV_READY)) { | |
7190575f | 4142 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
4143 | rval = qla82xx_restart_isp(base_vha); |
4144 | qla82xx_idc_lock(ha); | |
4145 | qla82xx_set_drv_active(base_vha); | |
4146 | qla82xx_idc_unlock(ha); | |
4147 | } | |
4148 | } | |
4149 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
4150 | ||
4151 | return rval; | |
4152 | } | |
4153 | ||
14e660e6 SJ |
4154 | static pci_ers_result_t |
4155 | qla2xxx_pci_slot_reset(struct pci_dev *pdev) | |
4156 | { | |
4157 | pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; | |
e315cd28 AC |
4158 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
4159 | struct qla_hw_data *ha = base_vha->hw; | |
90a86fc0 JC |
4160 | struct rsp_que *rsp; |
4161 | int rc, retries = 10; | |
09483916 | 4162 | |
7c3df132 SK |
4163 | ql_dbg(ql_dbg_aer, base_vha, 0x9004, |
4164 | "Slot Reset.\n"); | |
85880801 | 4165 | |
90a86fc0 JC |
4166 | /* Workaround: qla2xxx driver which access hardware earlier |
4167 | * needs error state to be pci_channel_io_online. | |
4168 | * Otherwise mailbox command timesout. | |
4169 | */ | |
4170 | pdev->error_state = pci_channel_io_normal; | |
4171 | ||
4172 | pci_restore_state(pdev); | |
4173 | ||
8c1496bd RL |
4174 | /* pci_restore_state() clears the saved_state flag of the device |
4175 | * save restored state which resets saved_state flag | |
4176 | */ | |
4177 | pci_save_state(pdev); | |
4178 | ||
09483916 BH |
4179 | if (ha->mem_only) |
4180 | rc = pci_enable_device_mem(pdev); | |
4181 | else | |
4182 | rc = pci_enable_device(pdev); | |
14e660e6 | 4183 | |
09483916 | 4184 | if (rc) { |
7c3df132 | 4185 | ql_log(ql_log_warn, base_vha, 0x9005, |
14e660e6 | 4186 | "Can't re-enable PCI device after reset.\n"); |
a5b36321 | 4187 | goto exit_slot_reset; |
14e660e6 | 4188 | } |
14e660e6 | 4189 | |
90a86fc0 JC |
4190 | rsp = ha->rsp_q_map[0]; |
4191 | if (qla2x00_request_irqs(ha, rsp)) | |
a5b36321 | 4192 | goto exit_slot_reset; |
90a86fc0 | 4193 | |
e315cd28 | 4194 | if (ha->isp_ops->pci_config(base_vha)) |
a5b36321 LC |
4195 | goto exit_slot_reset; |
4196 | ||
4197 | if (IS_QLA82XX(ha)) { | |
4198 | if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { | |
4199 | ret = PCI_ERS_RESULT_RECOVERED; | |
4200 | goto exit_slot_reset; | |
4201 | } else | |
4202 | goto exit_slot_reset; | |
4203 | } | |
14e660e6 | 4204 | |
90a86fc0 JC |
4205 | while (ha->flags.mbox_busy && retries--) |
4206 | msleep(1000); | |
85880801 | 4207 | |
e315cd28 | 4208 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 4209 | if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) |
14e660e6 | 4210 | ret = PCI_ERS_RESULT_RECOVERED; |
e315cd28 | 4211 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
14e660e6 | 4212 | |
90a86fc0 | 4213 | |
a5b36321 | 4214 | exit_slot_reset: |
7c3df132 SK |
4215 | ql_dbg(ql_dbg_aer, base_vha, 0x900e, |
4216 | "slot_reset return %x.\n", ret); | |
85880801 | 4217 | |
14e660e6 SJ |
4218 | return ret; |
4219 | } | |
4220 | ||
4221 | static void | |
4222 | qla2xxx_pci_resume(struct pci_dev *pdev) | |
4223 | { | |
e315cd28 AC |
4224 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
4225 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
4226 | int ret; |
4227 | ||
7c3df132 SK |
4228 | ql_dbg(ql_dbg_aer, base_vha, 0x900f, |
4229 | "pci_resume.\n"); | |
85880801 | 4230 | |
e315cd28 | 4231 | ret = qla2x00_wait_for_hba_online(base_vha); |
14e660e6 | 4232 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
4233 | ql_log(ql_log_fatal, base_vha, 0x9002, |
4234 | "The device failed to resume I/O from slot/link_reset.\n"); | |
14e660e6 | 4235 | } |
85880801 | 4236 | |
3e46f031 LC |
4237 | pci_cleanup_aer_uncorrect_error_status(pdev); |
4238 | ||
85880801 | 4239 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
4240 | } |
4241 | ||
4242 | static struct pci_error_handlers qla2xxx_err_handler = { | |
4243 | .error_detected = qla2xxx_pci_error_detected, | |
4244 | .mmio_enabled = qla2xxx_pci_mmio_enabled, | |
4245 | .slot_reset = qla2xxx_pci_slot_reset, | |
4246 | .resume = qla2xxx_pci_resume, | |
4247 | }; | |
4248 | ||
5433383e | 4249 | static struct pci_device_id qla2xxx_pci_tbl[] = { |
47f5e069 AV |
4250 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, |
4251 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, | |
4252 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, | |
4253 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, | |
4254 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, | |
4255 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, | |
4256 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, | |
4257 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, | |
4258 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, | |
4d4df193 | 4259 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, |
47f5e069 AV |
4260 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, |
4261 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, | |
c3a2f0df | 4262 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, |
3a03eb79 | 4263 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, |
a9083016 | 4264 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, |
5433383e AV |
4265 | { 0 }, |
4266 | }; | |
4267 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); | |
4268 | ||
fca29703 | 4269 | static struct pci_driver qla2xxx_pci_driver = { |
cb63067a | 4270 | .name = QLA2XXX_DRIVER_NAME, |
0a21ef1e JB |
4271 | .driver = { |
4272 | .owner = THIS_MODULE, | |
4273 | }, | |
fca29703 | 4274 | .id_table = qla2xxx_pci_tbl, |
7ee61397 | 4275 | .probe = qla2x00_probe_one, |
4c993f76 | 4276 | .remove = qla2x00_remove_one, |
e30d1756 | 4277 | .shutdown = qla2x00_shutdown, |
14e660e6 | 4278 | .err_handler = &qla2xxx_err_handler, |
fca29703 AV |
4279 | }; |
4280 | ||
6a03b4cd HZ |
4281 | static struct file_operations apidev_fops = { |
4282 | .owner = THIS_MODULE, | |
6038f373 | 4283 | .llseek = noop_llseek, |
6a03b4cd HZ |
4284 | }; |
4285 | ||
1da177e4 LT |
4286 | /** |
4287 | * qla2x00_module_init - Module initialization. | |
4288 | **/ | |
4289 | static int __init | |
4290 | qla2x00_module_init(void) | |
4291 | { | |
fca29703 AV |
4292 | int ret = 0; |
4293 | ||
1da177e4 | 4294 | /* Allocate cache for SRBs. */ |
354d6b21 | 4295 | srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, |
20c2df83 | 4296 | SLAB_HWCACHE_ALIGN, NULL); |
1da177e4 | 4297 | if (srb_cachep == NULL) { |
7c3df132 SK |
4298 | ql_log(ql_log_fatal, NULL, 0x0001, |
4299 | "Unable to allocate SRB cache...Failing load!.\n"); | |
1da177e4 LT |
4300 | return -ENOMEM; |
4301 | } | |
4302 | ||
4303 | /* Derive version string. */ | |
4304 | strcpy(qla2x00_version_str, QLA2XXX_VERSION); | |
11010fec | 4305 | if (ql2xextended_error_logging) |
0181944f AV |
4306 | strcat(qla2x00_version_str, "-debug"); |
4307 | ||
1c97a12a AV |
4308 | qla2xxx_transport_template = |
4309 | fc_attach_transport(&qla2xxx_transport_functions); | |
2c3dfe3f SJ |
4310 | if (!qla2xxx_transport_template) { |
4311 | kmem_cache_destroy(srb_cachep); | |
7c3df132 SK |
4312 | ql_log(ql_log_fatal, NULL, 0x0002, |
4313 | "fc_attach_transport failed...Failing load!.\n"); | |
1da177e4 | 4314 | return -ENODEV; |
2c3dfe3f | 4315 | } |
6a03b4cd HZ |
4316 | |
4317 | apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); | |
4318 | if (apidev_major < 0) { | |
7c3df132 SK |
4319 | ql_log(ql_log_fatal, NULL, 0x0003, |
4320 | "Unable to register char device %s.\n", QLA2XXX_APIDEV); | |
6a03b4cd HZ |
4321 | } |
4322 | ||
2c3dfe3f SJ |
4323 | qla2xxx_transport_vport_template = |
4324 | fc_attach_transport(&qla2xxx_transport_vport_functions); | |
4325 | if (!qla2xxx_transport_vport_template) { | |
4326 | kmem_cache_destroy(srb_cachep); | |
4327 | fc_release_transport(qla2xxx_transport_template); | |
7c3df132 SK |
4328 | ql_log(ql_log_fatal, NULL, 0x0004, |
4329 | "fc_attach_transport vport failed...Failing load!.\n"); | |
1da177e4 | 4330 | return -ENODEV; |
2c3dfe3f | 4331 | } |
7c3df132 SK |
4332 | ql_log(ql_log_info, NULL, 0x0005, |
4333 | "QLogic Fibre Channel HBA Driver: %s.\n", | |
fd9a29f0 | 4334 | qla2x00_version_str); |
7ee61397 | 4335 | ret = pci_register_driver(&qla2xxx_pci_driver); |
fca29703 AV |
4336 | if (ret) { |
4337 | kmem_cache_destroy(srb_cachep); | |
4338 | fc_release_transport(qla2xxx_transport_template); | |
2c3dfe3f | 4339 | fc_release_transport(qla2xxx_transport_vport_template); |
7c3df132 SK |
4340 | ql_log(ql_log_fatal, NULL, 0x0006, |
4341 | "pci_register_driver failed...ret=%d Failing load!.\n", | |
4342 | ret); | |
fca29703 AV |
4343 | } |
4344 | return ret; | |
1da177e4 LT |
4345 | } |
4346 | ||
4347 | /** | |
4348 | * qla2x00_module_exit - Module cleanup. | |
4349 | **/ | |
4350 | static void __exit | |
4351 | qla2x00_module_exit(void) | |
4352 | { | |
6a03b4cd | 4353 | unregister_chrdev(apidev_major, QLA2XXX_APIDEV); |
7ee61397 | 4354 | pci_unregister_driver(&qla2xxx_pci_driver); |
5433383e | 4355 | qla2x00_release_firmware(); |
354d6b21 | 4356 | kmem_cache_destroy(srb_cachep); |
a9083016 GM |
4357 | if (ctx_cachep) |
4358 | kmem_cache_destroy(ctx_cachep); | |
1da177e4 | 4359 | fc_release_transport(qla2xxx_transport_template); |
2c3dfe3f | 4360 | fc_release_transport(qla2xxx_transport_vport_template); |
1da177e4 LT |
4361 | } |
4362 | ||
4363 | module_init(qla2x00_module_init); | |
4364 | module_exit(qla2x00_module_exit); | |
4365 | ||
4366 | MODULE_AUTHOR("QLogic Corporation"); | |
4367 | MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); | |
4368 | MODULE_LICENSE("GPL"); | |
4369 | MODULE_VERSION(QLA2XXX_VERSION); | |
bb8ee499 AV |
4370 | MODULE_FIRMWARE(FW_FILE_ISP21XX); |
4371 | MODULE_FIRMWARE(FW_FILE_ISP22XX); | |
4372 | MODULE_FIRMWARE(FW_FILE_ISP2300); | |
4373 | MODULE_FIRMWARE(FW_FILE_ISP2322); | |
4374 | MODULE_FIRMWARE(FW_FILE_ISP24XX); | |
61623fc3 | 4375 | MODULE_FIRMWARE(FW_FILE_ISP25XX); |