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[SCSI] qla2xxx: Add logic to abort BSG commands for ISPFX00.
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
50280c01
CD		 113#define MAX_Q_DEPTH 32
114static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 122MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF "
8cb2049c
AE		 124 " Default is 0 - No DIF Support. 1 - Enable it"
125 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 126
8cb2049c 127int ql2xenablehba_err_chk = 2;
bad75002
AE		 128module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
129MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 130 " Enable T10-CRC-DIF Error isolation by HBA:\n"
131 " Default is 1.\n"
132 " 0 -- Error isolation disabled\n"
133 " 1 -- Error isolation enabled only for DIX Type 0\n"
134 " 2 -- Error isolation enabled for all Types\n");
bad75002 135
e5896bd5 136int ql2xiidmaenable=1;
f2019cb1 137module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 138MODULE_PARM_DESC(ql2xiidmaenable,
139 "Enables iIDMA settings "
140 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
141
73208dfd 142int ql2xmaxqueues = 1;
f2019cb1 143module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 144MODULE_PARM_DESC(ql2xmaxqueues,
145 "Enables MQ settings "
ae68230c
JP		 146 "Default is 1 for single queue. Set it to number "
147 "of queues in MQ mode.");
68ca949c
AC		 148
149int ql2xmultique_tag;
f2019cb1 150module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 151MODULE_PARM_DESC(ql2xmultique_tag,
152 "Enables CPU affinity settings for the driver "
153 "Default is 0 for no affinity of request and response IO. "
154 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 155
156int ql2xfwloadbin;
86e45bf6 157module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 158MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 159 "Option to specify location from which to load ISP firmware:.\n"
160 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 161 " interface.\n"
162 " 1 -- load firmware from flash.\n"
163 " 0 -- use default semantics.\n");
164
ae97c91e 165int ql2xetsenable;
f2019cb1 166module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 167MODULE_PARM_DESC(ql2xetsenable,
168 "Enables firmware ETS burst."
169 "Default is 0 - skip ETS enablement.");
170
6907869d 171int ql2xdbwr = 1;
86e45bf6 172module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 173MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 174 "Option to specify scheme for request queue posting.\n"
175 " 0 -- Regular doorbell.\n"
176 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 177
f4c496c1 178int ql2xtargetreset = 1;
f2019cb1 179module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 180MODULE_PARM_DESC(ql2xtargetreset,
181 "Enable target reset."
182 "Default is 1 - use hw defaults.");
183
4da26e16 184int ql2xgffidenable;
f2019cb1 185module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 186MODULE_PARM_DESC(ql2xgffidenable,
187 "Enables GFF_ID checks of port type. "
188 "Default is 0 - Do not use GFF_ID information.");
a9083016 189
3822263e 190int ql2xasynctmfenable;
f2019cb1 191module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 192MODULE_PARM_DESC(ql2xasynctmfenable,
193 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
194 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 195
196int ql2xdontresethba;
86e45bf6 197module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 198MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 199 "Option to specify reset behaviour.\n"
200 " 0 (Default) -- Reset on failure.\n"
201 " 1 -- Do not reset on failure.\n");
ed0de87c 202
82515920
AV		 203uint ql2xmaxlun = MAX_LUNS;
204module_param(ql2xmaxlun, uint, S_IRUGO);
205MODULE_PARM_DESC(ql2xmaxlun,
206 "Defines the maximum LU number to register with the SCSI "
207 "midlayer. Default is 65535.");
208
08de2844
GM		 209int ql2xmdcapmask = 0x1F;
210module_param(ql2xmdcapmask, int, S_IRUGO);
211MODULE_PARM_DESC(ql2xmdcapmask,
212 "Set the Minidump driver capture mask level. "
6e96fa7b 213 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 214
3aadff35 215int ql2xmdenable = 1;
08de2844
GM		 216module_param(ql2xmdenable, int, S_IRUGO);
217MODULE_PARM_DESC(ql2xmdenable,
218 "Enable/disable MiniDump. "
3aadff35
GM		 219 "0 - MiniDump disabled. "
220 "1 (Default) - MiniDump enabled.");
08de2844 221
1da177e4 222/*
fa2a1ce5 223 * SCSI host template entry points
1da177e4
LT		 224 */
225static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 226static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 227static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
228static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 229static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 230static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 231static int qla2xxx_eh_abort(struct scsi_cmnd *);
232static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 233static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 234static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
235static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 236
e881a172 237static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 238static int qla2x00_change_queue_type(struct scsi_device *, int);
3491255e 239static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 240
a5326f86 241struct scsi_host_template qla2xxx_driver_template = {
1da177e4 242 .module = THIS_MODULE,
cb63067a 243 .name = QLA2XXX_DRIVER_NAME,
a5326f86 244 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 245
246 .eh_abort_handler = qla2xxx_eh_abort,
247 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 248 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 249 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
250 .eh_host_reset_handler = qla2xxx_eh_host_reset,
251
252 .slave_configure = qla2xxx_slave_configure,
253
254 .slave_alloc = qla2xxx_slave_alloc,
255 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 256 .scan_finished = qla2xxx_scan_finished,
257 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 258 .change_queue_depth = qla2x00_change_queue_depth,
259 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 260 .this_id = -1,
261 .cmd_per_lun = 3,
262 .use_clustering = ENABLE_CLUSTERING,
263 .sg_tablesize = SG_ALL,
264
265 .max_sectors = 0xFFFF,
afb046e2 266 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 267
268 .supported_mode = MODE_INITIATOR,
fca29703
AV		 269};
270
1da177e4 271static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 272struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 273
1da177e4
LT		 274/* TODO Convert to inlines
275 *
276 * Timer routines
277 */
1da177e4 278
2c3dfe3f 279__inline__ void
e315cd28 280qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 281{
e315cd28
AC		 282 init_timer(&vha->timer);
283 vha->timer.expires = jiffies + interval * HZ;
284 vha->timer.data = (unsigned long)vha;
285 vha->timer.function = (void (*)(unsigned long))func;
286 add_timer(&vha->timer);
287 vha->timer_active = 1;
1da177e4
LT		 288}
289
290static inline void
e315cd28 291qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 292{
a9083016 293 /* Currently used for 82XX only. */
7c3df132
SK		 294 if (vha->device_flags & DFLG_DEV_FAILED) {
295 ql_dbg(ql_dbg_timer, vha, 0x600d,
296 "Device in a failed state, returning.\n");
a9083016 297 return;
7c3df132 298 }
a9083016 299
e315cd28 300 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 301}
302
a824ebb3 303static __inline__ void
e315cd28 304qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 305{
e315cd28
AC		 306 del_timer_sync(&vha->timer);
307 vha->timer_active = 0;
1da177e4
LT		 308}
309
1da177e4
LT		 310static int qla2x00_do_dpc(void *data);
311
312static void qla2x00_rst_aen(scsi_qla_host_t *);
313
73208dfd
AC		 314static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
315 struct req_que **, struct rsp_que **);
e30d1756 316static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 317static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 318
1da177e4 319/* -------------------------------------------------------------------------- */
9a347ff4
CD		 320static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
321 struct rsp_que *rsp)
73208dfd 322{
7c3df132 323 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 324 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 325 GFP_KERNEL);
326 if (!ha->req_q_map) {
7c3df132
SK		 327 ql_log(ql_log_fatal, vha, 0x003b,
328 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 329 goto fail_req_map;
330 }
331
2afa19a9 332 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 333 GFP_KERNEL);
334 if (!ha->rsp_q_map) {
7c3df132
SK		 335 ql_log(ql_log_fatal, vha, 0x003c,
336 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 337 goto fail_rsp_map;
338 }
9a347ff4
CD		 339 /*
340 * Make sure we record at least the request and response queue zero in
341 * case we need to free them if part of the probe fails.
342 */
343 ha->rsp_q_map[0] = rsp;
344 ha->req_q_map[0] = req;
73208dfd
AC		 345 set_bit(0, ha->rsp_qid_map);
346 set_bit(0, ha->req_qid_map);
347 return 1;
348
349fail_rsp_map:
350 kfree(ha->req_q_map);
351 ha->req_q_map = NULL;
352fail_req_map:
353 return -ENOMEM;
354}
355
2afa19a9 356static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 357{
8ae6d9c7
GM		 358 if (IS_QLAFX00(ha)) {
359 if (req && req->ring_fx00)
360 dma_free_coherent(&ha->pdev->dev,
361 (req->length_fx00 + 1) * sizeof(request_t),
362 req->ring_fx00, req->dma_fx00);
363 } else if (req && req->ring)
73208dfd
AC		 364 dma_free_coherent(&ha->pdev->dev,
365 (req->length + 1) * sizeof(request_t),
366 req->ring, req->dma);
367
8d93f550
CD		 368 if (req)
369 kfree(req->outstanding_cmds);
370
73208dfd
AC		 371 kfree(req);
372 req = NULL;
373}
374
2afa19a9
AC		 375static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
376{
8ae6d9c7
GM		 377 if (IS_QLAFX00(ha)) {
378 if (rsp && rsp->ring)
379 dma_free_coherent(&ha->pdev->dev,
380 (rsp->length_fx00 + 1) * sizeof(request_t),
381 rsp->ring_fx00, rsp->dma_fx00);
382 } else if (rsp && rsp->ring) {
2afa19a9
AC		 383 dma_free_coherent(&ha->pdev->dev,
384 (rsp->length + 1) * sizeof(response_t),
385 rsp->ring, rsp->dma);
8ae6d9c7 386 }
2afa19a9
AC		 387 kfree(rsp);
388 rsp = NULL;
389}
390
73208dfd
AC		 391static void qla2x00_free_queues(struct qla_hw_data *ha)
392{
393 struct req_que *req;
394 struct rsp_que *rsp;
395 int cnt;
396
2afa19a9 397 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 398 req = ha->req_q_map[cnt];
2afa19a9 399 qla2x00_free_req_que(ha, req);
73208dfd 400 }
73208dfd
AC		 401 kfree(ha->req_q_map);
402 ha->req_q_map = NULL;
2afa19a9
AC		 403
404 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
405 rsp = ha->rsp_q_map[cnt];
406 qla2x00_free_rsp_que(ha, rsp);
407 }
408 kfree(ha->rsp_q_map);
409 ha->rsp_q_map = NULL;
73208dfd
AC		 410}
411
68ca949c
AC		 412static int qla25xx_setup_mode(struct scsi_qla_host *vha)
413{
414 uint16_t options = 0;
415 int ques, req, ret;
416 struct qla_hw_data *ha = vha->hw;
417
7163ea81 418 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 419 ql_log(ql_log_warn, vha, 0x00d8,
420 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 421 goto fail;
422 }
68ca949c 423 if (ql2xmultique_tag) {
68ca949c
AC		 424 /* create a request queue for IO */
425 options |= BIT_7;
426 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
427 QLA_DEFAULT_QUE_QOS);
428 if (!req) {
7c3df132
SK		 429 ql_log(ql_log_warn, vha, 0x00e0,
430 "Failed to create request queue.\n");
68ca949c
AC		 431 goto fail;
432 }
278274d5 433 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 434 vha->req = ha->req_q_map[req];
435 options |= BIT_1;
436 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
437 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
438 if (!ret) {
7c3df132
SK		 439 ql_log(ql_log_warn, vha, 0x00e8,
440 "Failed to create response queue.\n");
68ca949c
AC		 441 goto fail2;
442 }
443 }
7163ea81 444 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 445 ql_dbg(ql_dbg_multiq, vha, 0xc007,
446 "CPU affinity mode enalbed, "
447 "no. of response queues:%d no. of request queues:%d.\n",
448 ha->max_rsp_queues, ha->max_req_queues);
449 ql_dbg(ql_dbg_init, vha, 0x00e9,
450 "CPU affinity mode enalbed, "
451 "no. of response queues:%d no. of request queues:%d.\n",
452 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 453 }
454 return 0;
455fail2:
456 qla25xx_delete_queues(vha);
7163ea81
AC		 457 destroy_workqueue(ha->wq);
458 ha->wq = NULL;
0cd33fcf 459 vha->req = ha->req_q_map[0];
68ca949c
AC		 460fail:
461 ha->mqenable = 0;
7163ea81
AC		 462 kfree(ha->req_q_map);
463 kfree(ha->rsp_q_map);
464 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 465 return 1;
466}
467
1da177e4 468static char *
e315cd28 469qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 470{
e315cd28 471 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 472 static char *pci_bus_modes[] = {
473 "33", "66", "100", "133",
474 };
475 uint16_t pci_bus;
476
477 strcpy(str, "PCI");
478 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
479 if (pci_bus) {
480 strcat(str, "-X (");
481 strcat(str, pci_bus_modes[pci_bus]);
482 } else {
483 pci_bus = (ha->pci_attr & BIT_8) >> 8;
484 strcat(str, " (");
485 strcat(str, pci_bus_modes[pci_bus]);
486 }
487 strcat(str, " MHz)");
488
489 return (str);
490}
491
fca29703 492static char *
e315cd28 493qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 494{
495 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 496 struct qla_hw_data *ha = vha->hw;
fca29703 497 uint32_t pci_bus;
fca29703 498
62a276f8 499 if (pci_is_pcie(ha->pdev)) {
fca29703 500 char lwstr[6];
62a276f8 501 uint32_t lstat, lspeed, lwidth;
fca29703 502
62a276f8
BH		 503 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
504 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
505 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 506
507 strcpy(str, "PCIe (");
49300af7
SK		 508 switch (lspeed) {
509 case 1:
c87a0d8c 510 strcat(str, "2.5GT/s ");
49300af7
SK		 511 break;
512 case 2:
c87a0d8c 513 strcat(str, "5.0GT/s ");
49300af7
SK		 514 break;
515 case 3:
516 strcat(str, "8.0GT/s ");
517 break;
518 default:
fca29703 519 strcat(str, "<unknown> ");
49300af7
SK		 520 break;
521 }
fca29703
AV		 522 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
523 strcat(str, lwstr);
524
525 return str;
526 }
527
528 strcpy(str, "PCI");
529 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
530 if (pci_bus == 0 || pci_bus == 8) {
531 strcat(str, " (");
532 strcat(str, pci_bus_modes[pci_bus >> 3]);
533 } else {
534 strcat(str, "-X ");
535 if (pci_bus & BIT_2)
536 strcat(str, "Mode 2");
537 else
538 strcat(str, "Mode 1");
539 strcat(str, " (");
540 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
541 }
542 strcat(str, " MHz)");
543
544 return str;
545}
546
e5f82ab8 547static char *
e315cd28 548qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 549{
550 char un_str[10];
e315cd28 551 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 552
1da177e4
LT		 553 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
554 ha->fw_minor_version,
555 ha->fw_subminor_version);
556
557 if (ha->fw_attributes & BIT_9) {
558 strcat(str, "FLX");
559 return (str);
560 }
561
562 switch (ha->fw_attributes & 0xFF) {
563 case 0x7:
564 strcat(str, "EF");
565 break;
566 case 0x17:
567 strcat(str, "TP");
568 break;
569 case 0x37:
570 strcat(str, "IP");
571 break;
572 case 0x77:
573 strcat(str, "VI");
574 break;
575 default:
576 sprintf(un_str, "(%x)", ha->fw_attributes);
577 strcat(str, un_str);
578 break;
579 }
580 if (ha->fw_attributes & 0x100)
581 strcat(str, "X");
582
583 return (str);
584}
585
e5f82ab8 586static char *
e315cd28 587qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 588{
e315cd28 589 struct qla_hw_data *ha = vha->hw;
f0883ac6 590
3a03eb79
AV		 591 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
592 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 593 return str;
fca29703
AV		 594}
595
9ba56b95
GM		 596void
597qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 598{
9ba56b95
GM		 599 srb_t *sp = (srb_t *)ptr;
600 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
601 struct qla_hw_data *ha = sp->fcport->vha->hw;
602 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 603
9ba56b95
GM		 604 if (sp->flags & SRB_DMA_VALID) {
605 scsi_dma_unmap(cmd);
606 sp->flags &= ~SRB_DMA_VALID;
7c3df132 607 }
fca29703 608
9ba56b95
GM		 609 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
610 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
611 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
612 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
613 }
614
615 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
616 /* List assured to be having elements */
617 qla2x00_clean_dsd_pool(ha, sp);
618 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
619 }
620
621 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
622 dma_pool_free(ha->dl_dma_pool, ctx,
623 ((struct crc_context *)ctx)->crc_ctx_dma);
624 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
625 }
626
627 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
628 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 629
9ba56b95
GM		 630 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
631 ctx1->fcp_cmnd_dma);
632 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
633 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
634 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
635 mempool_free(ctx1, ha->ctx_mempool);
636 ctx1 = NULL;
637 }
638
639 CMD_SP(cmd) = NULL;
b00ee7d7 640 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 641}
642
14b06808 643static void
9ba56b95
GM		 644qla2x00_sp_compl(void *data, void *ptr, int res)
645{
646 struct qla_hw_data *ha = (struct qla_hw_data *)data;
647 srb_t *sp = (srb_t *)ptr;
648 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
649
650 cmd->result = res;
651
652 if (atomic_read(&sp->ref_count) == 0) {
653 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
654 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
655 sp, GET_CMD_SP(sp));
656 if (ql2xextended_error_logging & ql_dbg_io)
657 BUG();
658 return;
659 }
660 if (!atomic_dec_and_test(&sp->ref_count))
661 return;
662
663 qla2x00_sp_free_dma(ha, sp);
664 cmd->scsi_done(cmd);
fca29703
AV		 665}
666
8ae6d9c7
GM		 667/* If we are SP1 here, we need to still take and release the host_lock as SP1
668 * does not have the changes necessary to avoid taking host->host_lock.
669 */
1da177e4 670static int
f5e3e40b 671qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 672{
134ae078 673 scsi_qla_host_t *vha = shost_priv(host);
fca29703 674 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 675 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 676 struct qla_hw_data *ha = vha->hw;
677 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 678 srb_t *sp;
679 int rval;
680
85880801 681 if (ha->flags.eeh_busy) {
7c3df132 682 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 683 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 684 "PCI Channel IO permanent failure, exiting "
685 "cmd=%p.\n", cmd);
b9b12f73 686 cmd->result = DID_NO_CONNECT << 16;
7c3df132 687 } else {
5f28d2d7 688 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 689 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 690 cmd->result = DID_REQUEUE << 16;
7c3df132 691 }
14e660e6
SJ		 692 goto qc24_fail_command;
693 }
694
19a7b4ae
JSEC		 695 rval = fc_remote_port_chkready(rport);
696 if (rval) {
697 cmd->result = rval;
5f28d2d7 698 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 699 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
700 cmd, rval);
fca29703
AV		 701 goto qc24_fail_command;
702 }
703
bad75002
AE		 704 if (!vha->flags.difdix_supported &&
705 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 706 ql_dbg(ql_dbg_io, vha, 0x3004,
707 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
708 cmd);
bad75002
AE		 709 cmd->result = DID_NO_CONNECT << 16;
710 goto qc24_fail_command;
711 }
aa651be8
CD		 712
713 if (!fcport) {
714 cmd->result = DID_NO_CONNECT << 16;
715 goto qc24_fail_command;
716 }
717
fca29703
AV		 718 if (atomic_read(&fcport->state) != FCS_ONLINE) {
719 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 720 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 721 ql_dbg(ql_dbg_io, vha, 0x3005,
722 "Returning DNC, fcport_state=%d loop_state=%d.\n",
723 atomic_read(&fcport->state),
724 atomic_read(&base_vha->loop_state));
fca29703
AV		 725 cmd->result = DID_NO_CONNECT << 16;
726 goto qc24_fail_command;
727 }
7b594131 728 goto qc24_target_busy;
fca29703
AV		 729 }
730
b00ee7d7 731 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 732 if (!sp)
f5e3e40b 733 goto qc24_host_busy;
fca29703 734
9ba56b95
GM		 735 sp->u.scmd.cmd = cmd;
736 sp->type = SRB_SCSI_CMD;
737 atomic_set(&sp->ref_count, 1);
738 CMD_SP(cmd) = (void *)sp;
739 sp->free = qla2x00_sp_free_dma;
740 sp->done = qla2x00_sp_compl;
741
e315cd28 742 rval = ha->isp_ops->start_scsi(sp);
7c3df132 743 if (rval != QLA_SUCCESS) {
53016ed3 744 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 745 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 746 goto qc24_host_busy_free_sp;
7c3df132 747 }
fca29703 748
fca29703
AV		 749 return 0;
750
751qc24_host_busy_free_sp:
9ba56b95 752 qla2x00_sp_free_dma(ha, sp);
fca29703 753
f5e3e40b 754qc24_host_busy:
fca29703
AV		 755 return SCSI_MLQUEUE_HOST_BUSY;
756
7b594131
MC		 757qc24_target_busy:
758 return SCSI_MLQUEUE_TARGET_BUSY;
759
fca29703 760qc24_fail_command:
f5e3e40b 761 cmd->scsi_done(cmd);
fca29703
AV		 762
763 return 0;
764}
765
1da177e4
LT		 766/*
767 * qla2x00_eh_wait_on_command
768 * Waits for the command to be returned by the Firmware for some
769 * max time.
770 *
771 * Input:
1da177e4 772 * cmd = Scsi Command to wait on.
1da177e4
LT		 773 *
774 * Return:
775 * Not Found : 0
776 * Found : 1
777 */
778static int
e315cd28 779qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 780{
fe74c71f
AV		 781#define ABORT_POLLING_PERIOD 1000
782#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 783 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 784 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
785 struct qla_hw_data *ha = vha->hw;
f4f051eb 786 int ret = QLA_SUCCESS;
1da177e4 787
85880801 788 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 789 ql_dbg(ql_dbg_taskm, vha, 0x8005,
790 "Return:eh_wait.\n");
85880801
AV		 791 return ret;
792 }
793
d970432c 794 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 795 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 796 }
797 if (CMD_SP(cmd))
798 ret = QLA_FUNCTION_FAILED;
1da177e4 799
f4f051eb 800 return ret;
1da177e4
LT		 801}
802
803/*
804 * qla2x00_wait_for_hba_online
fa2a1ce5 805 * Wait till the HBA is online after going through
1da177e4
LT		 806 * <= MAX_RETRIES_OF_ISP_ABORT or
807 * finally HBA is disabled ie marked offline
808 *
809 * Input:
810 * ha - pointer to host adapter structure
fa2a1ce5
AV		 811 *
812 * Note:
1da177e4
LT		 813 * Does context switching-Release SPIN_LOCK
814 * (if any) before calling this routine.
815 *
816 * Return:
817 * Success (Adapter is online) : 0
818 * Failed (Adapter is offline/disabled) : 1
819 */
854165f4 820int
e315cd28 821qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 822{
fca29703
AV		 823 int return_status;
824 unsigned long wait_online;
e315cd28
AC		 825 struct qla_hw_data *ha = vha->hw;
826 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 827
fa2a1ce5 828 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 829 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
830 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
831 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
832 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 833
834 msleep(1000);
835 }
e315cd28 836 if (base_vha->flags.online)
fa2a1ce5 837 return_status = QLA_SUCCESS;
1da177e4
LT		 838 else
839 return_status = QLA_FUNCTION_FAILED;
840
1da177e4
LT		 841 return (return_status);
842}
843
86fbee86
LC		 844/*
845 * qla2x00_wait_for_reset_ready
846 * Wait till the HBA is online after going through
847 * <= MAX_RETRIES_OF_ISP_ABORT or
848 * finally HBA is disabled ie marked offline or flash
849 * operations are in progress.
850 *
851 * Input:
852 * ha - pointer to host adapter structure
853 *
854 * Note:
855 * Does context switching-Release SPIN_LOCK
856 * (if any) before calling this routine.
857 *
858 * Return:
859 * Success (Adapter is online/no flash ops) : 0
860 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
861 */
3dbe756a 862static int
86fbee86
LC		 863qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
864{
865 int return_status;
866 unsigned long wait_online;
867 struct qla_hw_data *ha = vha->hw;
868 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
869
870 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
871 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
872 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
873 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
874 ha->optrom_state != QLA_SWAITING ||
875 ha->dpc_active) && time_before(jiffies, wait_online))
876 msleep(1000);
877
878 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
879 return_status = QLA_SUCCESS;
880 else
881 return_status = QLA_FUNCTION_FAILED;
882
7c3df132
SK		 883 ql_dbg(ql_dbg_taskm, vha, 0x8019,
884 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 885
886 return return_status;
887}
888
2533cf67
LC		 889int
890qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
891{
892 int return_status;
893 unsigned long wait_reset;
894 struct qla_hw_data *ha = vha->hw;
895 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
896
897 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
898 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
899 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
900 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
901 ha->dpc_active) && time_before(jiffies, wait_reset)) {
902
903 msleep(1000);
904
905 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
906 ha->flags.chip_reset_done)
907 break;
908 }
909 if (ha->flags.chip_reset_done)
910 return_status = QLA_SUCCESS;
911 else
912 return_status = QLA_FUNCTION_FAILED;
913
914 return return_status;
915}
916
083a469d
GM		 917static void
918sp_get(struct srb *sp)
919{
920 atomic_inc(&sp->ref_count);
921}
922
1da177e4
LT		 923/**************************************************************************
924* qla2xxx_eh_abort
925*
926* Description:
927* The abort function will abort the specified command.
928*
929* Input:
930* cmd = Linux SCSI command packet to be aborted.
931*
932* Returns:
933* Either SUCCESS or FAILED.
934*
935* Note:
2ea00202 936* Only return FAILED if command not returned by firmware.
1da177e4 937**************************************************************************/
e5f82ab8 938static int
1da177e4
LT		 939qla2xxx_eh_abort(struct scsi_cmnd *cmd)
940{
e315cd28 941 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 942 srb_t *sp;
4e98d3b8 943 int ret;
f4f051eb 944 unsigned int id, lun;
18e144d3 945 unsigned long flags;
2ea00202 946 int wait = 0;
e315cd28 947 struct qla_hw_data *ha = vha->hw;
1da177e4 948
f4f051eb 949 if (!CMD_SP(cmd))
2ea00202 950 return SUCCESS;
1da177e4 951
4e98d3b8
AV		 952 ret = fc_block_scsi_eh(cmd);
953 if (ret != 0)
954 return ret;
955 ret = SUCCESS;
956
f4f051eb
AV		 957 id = cmd->device->id;
958 lun = cmd->device->lun;
1da177e4 959
e315cd28 960 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 961 sp = (srb_t *) CMD_SP(cmd);
962 if (!sp) {
963 spin_unlock_irqrestore(&ha->hardware_lock, flags);
964 return SUCCESS;
965 }
1da177e4 966
7c3df132 967 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 968 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
969 vha->host_no, id, lun, sp, cmd);
17d98630 970
170babc3
MC		 971 /* Get a reference to the sp and drop the lock.*/
972 sp_get(sp);
083a469d 973
e315cd28 974 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 975 if (ha->isp_ops->abort_command(sp)) {
a55aac79 976 ret = FAILED;
7c3df132 977 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 978 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 979 } else {
7c3df132 980 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 981 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 982 wait = 1;
983 }
75942064
SK		 984
985 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 986 sp->done(ha, sp, 0);
75942064 987 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 988
bc91ade9
CD		 989 /* Did the command return during mailbox execution? */
990 if (ret == FAILED && !CMD_SP(cmd))
991 ret = SUCCESS;
992
f4f051eb 993 /* Wait for the command to be returned. */
2ea00202 994 if (wait) {
e315cd28 995 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 996 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 997 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 998 ret = FAILED;
f4f051eb 999 }
1da177e4 1000 }
1da177e4 1001
7c3df132 1002 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 1003 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1004 vha->host_no, id, lun, wait, ret);
1da177e4 1005
f4f051eb
AV		 1006 return ret;
1007}
1da177e4 1008
4d78c973 1009int
e315cd28 1010qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1011 unsigned int l, enum nexus_wait_type type)
f4f051eb 1012{
17d98630 1013 int cnt, match, status;
18e144d3 1014 unsigned long flags;
e315cd28 1015 struct qla_hw_data *ha = vha->hw;
73208dfd 1016 struct req_que *req;
4d78c973 1017 srb_t *sp;
9ba56b95 1018 struct scsi_cmnd *cmd;
1da177e4 1019
523ec773 1020 status = QLA_SUCCESS;
17d98630 1021
e315cd28 1022 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1023 req = vha->req;
17d98630 1024 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1025 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1026 sp = req->outstanding_cmds[cnt];
1027 if (!sp)
523ec773 1028 continue;
9ba56b95 1029 if (sp->type != SRB_SCSI_CMD)
cf53b069 1030 continue;
17d98630
AC		 1031 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1032 continue;
1033 match = 0;
9ba56b95 1034 cmd = GET_CMD_SP(sp);
17d98630
AC		 1035 switch (type) {
1036 case WAIT_HOST:
1037 match = 1;
1038 break;
1039 case WAIT_TARGET:
9ba56b95 1040 match = cmd->device->id == t;
17d98630
AC		 1041 break;
1042 case WAIT_LUN:
9ba56b95
GM		 1043 match = (cmd->device->id == t &&
1044 cmd->device->lun == l);
17d98630 1045 break;
73208dfd 1046 }
17d98630
AC		 1047 if (!match)
1048 continue;
1049
1050 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1051 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1052 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1053 }
e315cd28 1054 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1055
1056 return status;
1da177e4
LT		 1057}
1058
523ec773
AV		 1059static char *reset_errors[] = {
1060 "HBA not online",
1061 "HBA not ready",
1062 "Task management failed",
1063 "Waiting for command completions",
1064};
1da177e4 1065
e5f82ab8 1066static int
523ec773 1067__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1068 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1069{
e315cd28 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1071 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1072 int err;
1da177e4 1073
7c3df132 1074 if (!fcport) {
523ec773 1075 return FAILED;
7c3df132 1076 }
1da177e4 1077
4e98d3b8
AV		 1078 err = fc_block_scsi_eh(cmd);
1079 if (err != 0)
1080 return err;
1081
7c3df132 1082 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1083 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1084 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1085
523ec773 1086 err = 0;
7c3df132
SK		 1087 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1088 ql_log(ql_log_warn, vha, 0x800a,
1089 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1090 goto eh_reset_failed;
7c3df132 1091 }
523ec773 1092 err = 2;
2afa19a9 1093 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1094 != QLA_SUCCESS) {
1095 ql_log(ql_log_warn, vha, 0x800c,
1096 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1097 goto eh_reset_failed;
7c3df132 1098 }
523ec773 1099 err = 3;
e315cd28 1100 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1101 cmd->device->lun, type) != QLA_SUCCESS) {
1102 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1103 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1104 goto eh_reset_failed;
7c3df132 1105 }
523ec773 1106
7c3df132 1107 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1108 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1109 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1110
1111 return SUCCESS;
1112
4d78c973 1113eh_reset_failed:
7c3df132 1114 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1115 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1116 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1117 cmd);
523ec773
AV		 1118 return FAILED;
1119}
1da177e4 1120
523ec773
AV		 1121static int
1122qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1123{
e315cd28
AC		 1124 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1125 struct qla_hw_data *ha = vha->hw;
1da177e4 1126
523ec773
AV		 1127 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1128 ha->isp_ops->lun_reset);
1da177e4
LT		 1129}
1130
1da177e4 1131static int
523ec773 1132qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1133{
e315cd28
AC		 1134 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1135 struct qla_hw_data *ha = vha->hw;
1da177e4 1136
523ec773
AV		 1137 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1138 ha->isp_ops->target_reset);
1da177e4
LT		 1139}
1140
1da177e4
LT		 1141/**************************************************************************
1142* qla2xxx_eh_bus_reset
1143*
1144* Description:
1145* The bus reset function will reset the bus and abort any executing
1146* commands.
1147*
1148* Input:
1149* cmd = Linux SCSI command packet of the command that cause the
1150* bus reset.
1151*
1152* Returns:
1153* SUCCESS/FAILURE (defined as macro in scsi.h).
1154*
1155**************************************************************************/
e5f82ab8 1156static int
1da177e4
LT		 1157qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1158{
e315cd28 1159 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1160 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1161 int ret = FAILED;
f4f051eb 1162 unsigned int id, lun;
f4f051eb 1163
f4f051eb
AV		 1164 id = cmd->device->id;
1165 lun = cmd->device->lun;
1da177e4 1166
7c3df132 1167 if (!fcport) {
f4f051eb 1168 return ret;
7c3df132 1169 }
1da177e4 1170
4e98d3b8
AV		 1171 ret = fc_block_scsi_eh(cmd);
1172 if (ret != 0)
1173 return ret;
1174 ret = FAILED;
1175
7c3df132 1176 ql_log(ql_log_info, vha, 0x8012,
46270afe 1177 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1178
e315cd28 1179 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1180 ql_log(ql_log_fatal, vha, 0x8013,
1181 "Wait for hba online failed board disabled.\n");
f4f051eb 1182 goto eh_bus_reset_done;
1da177e4
LT		 1183 }
1184
ad537689
SK		 1185 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1186 ret = SUCCESS;
1187
f4f051eb
AV		 1188 if (ret == FAILED)
1189 goto eh_bus_reset_done;
1da177e4 1190
9a41a62b 1191 /* Flush outstanding commands. */
4d78c973 1192 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1193 QLA_SUCCESS) {
1194 ql_log(ql_log_warn, vha, 0x8014,
1195 "Wait for pending commands failed.\n");
9a41a62b 1196 ret = FAILED;
7c3df132 1197 }
1da177e4 1198
f4f051eb 1199eh_bus_reset_done:
7c3df132 1200 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1201 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1202 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1203
f4f051eb 1204 return ret;
1da177e4
LT		 1205}
1206
1207/**************************************************************************
1208* qla2xxx_eh_host_reset
1209*
1210* Description:
1211* The reset function will reset the Adapter.
1212*
1213* Input:
1214* cmd = Linux SCSI command packet of the command that cause the
1215* adapter reset.
1216*
1217* Returns:
1218* Either SUCCESS or FAILED.
1219*
1220* Note:
1221**************************************************************************/
e5f82ab8 1222static int
1da177e4
LT		 1223qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1224{
e315cd28 1225 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1226 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1227 int ret = FAILED;
f4f051eb 1228 unsigned int id, lun;
e315cd28 1229 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1230
f4f051eb
AV		 1231 id = cmd->device->id;
1232 lun = cmd->device->lun;
f4f051eb 1233
7c3df132 1234 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1235 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1236
86fbee86 1237 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1238 goto eh_host_reset_lock;
1da177e4 1239
e315cd28
AC		 1240 if (vha != base_vha) {
1241 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1242 goto eh_host_reset_lock;
e315cd28 1243 } else {
7ec0effd 1244 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1245 if (!qla82xx_fcoe_ctx_reset(vha)) {
1246 /* Ctx reset success */
1247 ret = SUCCESS;
1248 goto eh_host_reset_lock;
1249 }
1250 /* fall thru if ctx reset failed */
1251 }
68ca949c
AC		 1252 if (ha->wq)
1253 flush_workqueue(ha->wq);
1254
e315cd28 1255 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1256 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1257 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1258 /* failed. schedule dpc to try */
1259 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1260
7c3df132
SK		 1261 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1262 ql_log(ql_log_warn, vha, 0x802a,
1263 "wait for hba online failed.\n");
e315cd28 1264 goto eh_host_reset_lock;
7c3df132 1265 }
e315cd28
AC		 1266 }
1267 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1268 }
1da177e4 1269
e315cd28 1270 /* Waiting for command to be returned to OS.*/
4d78c973 1271 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1272 QLA_SUCCESS)
f4f051eb 1273 ret = SUCCESS;
1da177e4 1274
f4f051eb 1275eh_host_reset_lock:
cfb0919c
CD		 1276 ql_log(ql_log_info, vha, 0x8017,
1277 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1278 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1279
f4f051eb
AV		 1280 return ret;
1281}
1da177e4
LT		 1282
1283/*
1284* qla2x00_loop_reset
1285* Issue loop reset.
1286*
1287* Input:
1288* ha = adapter block pointer.
1289*
1290* Returns:
1291* 0 = success
1292*/
a4722cf2 1293int
e315cd28 1294qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1295{
0c8c39af 1296 int ret;
bdf79621 1297 struct fc_port *fcport;
e315cd28 1298 struct qla_hw_data *ha = vha->hw;
1da177e4 1299
5854771e
AB		 1300 if (IS_QLAFX00(ha)) {
1301 return qlafx00_loop_reset(vha);
1302 }
1303
f4c496c1 1304 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1305 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1306 if (fcport->port_type != FCT_TARGET)
1307 continue;
1308
1309 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1310 if (ret != QLA_SUCCESS) {
7c3df132 1311 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1312 "Bus Reset failed: Reset=%d "
7c3df132 1313 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1314 }
1315 }
1316 }
1317
8ae6d9c7 1318
6246b8a1 1319 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1320 atomic_set(&vha->loop_state, LOOP_DOWN);
1321 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1322 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1323 ret = qla2x00_full_login_lip(vha);
0c8c39af 1324 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1325 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1326 "full_login_lip=%d.\n", ret);
749af3d5 1327 }
0c8c39af
AV		 1328 }
1329
0d6e61bc 1330 if (ha->flags.enable_lip_reset) {
e315cd28 1331 ret = qla2x00_lip_reset(vha);
ad537689 1332 if (ret != QLA_SUCCESS)
7c3df132
SK		 1333 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1334 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1335 }
1336
1da177e4 1337 /* Issue marker command only when we are going to start the I/O */
e315cd28 1338 vha->marker_needed = 1;
1da177e4 1339
0c8c39af 1340 return QLA_SUCCESS;
1da177e4
LT		 1341}
1342
df4bf0bb 1343void
e315cd28 1344qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1345{
73208dfd 1346 int que, cnt;
df4bf0bb
AV		 1347 unsigned long flags;
1348 srb_t *sp;
e315cd28 1349 struct qla_hw_data *ha = vha->hw;
73208dfd 1350 struct req_que *req;
df4bf0bb
AV		 1351
1352 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1353 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1354 req = ha->req_q_map[que];
73208dfd
AC		 1355 if (!req)
1356 continue;
8d93f550
CD		 1357 if (!req->outstanding_cmds)
1358 continue;
1359 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1360 sp = req->outstanding_cmds[cnt];
e612d465 1361 if (sp) {
73208dfd 1362 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1363 sp->done(vha, sp, res);
73208dfd 1364 }
df4bf0bb
AV		 1365 }
1366 }
1367 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1368}
1369
f4f051eb
AV		 1370static int
1371qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1372{
bdf79621 1373 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1374
19a7b4ae 1375 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1376 return -ENXIO;
bdf79621 1377
19a7b4ae 1378 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1379
f4f051eb
AV		 1380 return 0;
1381}
1da177e4 1382
f4f051eb
AV		 1383static int
1384qla2xxx_slave_configure(struct scsi_device *sdev)
1385{
e315cd28 1386 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1387 struct req_que *req = vha->req;
8482e118 1388
9e522cd8
AE		 1389 if (IS_T10_PI_CAPABLE(vha->hw))
1390 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1391
f4f051eb 1392 if (sdev->tagged_supported)
73208dfd 1393 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1394 else
73208dfd 1395 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1396 return 0;
1397}
1da177e4 1398
f4f051eb
AV		 1399static void
1400qla2xxx_slave_destroy(struct scsi_device *sdev)
1401{
1402 sdev->hostdata = NULL;
1da177e4
LT		 1403}
1404
c45dd305
GM		 1405static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1406{
1407 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1408
1409 if (!scsi_track_queue_full(sdev, qdepth))
1410 return;
1411
7c3df132 1412 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1413 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1414 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1415}
1416
1417static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1418{
1419 fc_port_t *fcport = sdev->hostdata;
1420 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1421 struct req_que *req = NULL;
1422
1423 req = vha->req;
1424 if (!req)
1425 return;
1426
1427 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1428 return;
1429
1430 if (sdev->ordered_tags)
1431 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1432 else
1433 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1434
7c3df132 1435 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1436 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1437 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1438}
1439
ce7e4af7 1440static int
e881a172 1441qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1442{
c45dd305
GM		 1443 switch (reason) {
1444 case SCSI_QDEPTH_DEFAULT:
1445 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1446 break;
1447 case SCSI_QDEPTH_QFULL:
1448 qla2x00_handle_queue_full(sdev, qdepth);
1449 break;
1450 case SCSI_QDEPTH_RAMP_UP:
1451 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1452 break;
1453 default:
08002af2 1454 return -EOPNOTSUPP;
c45dd305 1455 }
e881a172 1456
ce7e4af7
AV		 1457 return sdev->queue_depth;
1458}
1459
1460static int
1461qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1462{
1463 if (sdev->tagged_supported) {
1464 scsi_set_tag_type(sdev, tag_type);
1465 if (tag_type)
1466 scsi_activate_tcq(sdev, sdev->queue_depth);
1467 else
1468 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1469 } else
1470 tag_type = 0;
1471
1472 return tag_type;
1473}
1474
1da177e4
LT		 1475/**
1476 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1477 * @ha: HA context
1478 *
1479 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1480 * supported addressing method.
1481 */
1482static void
53303c42 1483qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1484{
7524f9b9 1485 /* Assume a 32bit DMA mask. */
1da177e4 1486 ha->flags.enable_64bit_addressing = 0;
1da177e4 1487
6a35528a 1488 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1489 /* Any upper-dword bits set? */
1490 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1491 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1492 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1493 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1494 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1495 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1496 return;
1da177e4 1497 }
1da177e4 1498 }
7524f9b9 1499
284901a9
YH		 1500 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1501 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1502}
1503
fd34f556 1504static void
e315cd28 1505qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1506{
1507 unsigned long flags = 0;
1508 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1509
1510 spin_lock_irqsave(&ha->hardware_lock, flags);
1511 ha->interrupts_on = 1;
1512 /* enable risc and host interrupts */
1513 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1514 RD_REG_WORD(&reg->ictrl);
1515 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1516
1517}
1518
1519static void
e315cd28 1520qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1521{
1522 unsigned long flags = 0;
1523 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1524
1525 spin_lock_irqsave(&ha->hardware_lock, flags);
1526 ha->interrupts_on = 0;
1527 /* disable risc and host interrupts */
1528 WRT_REG_WORD(&reg->ictrl, 0);
1529 RD_REG_WORD(&reg->ictrl);
1530 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1531}
1532
1533static void
e315cd28 1534qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1535{
1536 unsigned long flags = 0;
1537 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1538
1539 spin_lock_irqsave(&ha->hardware_lock, flags);
1540 ha->interrupts_on = 1;
1541 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1542 RD_REG_DWORD(&reg->ictrl);
1543 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1544}
1545
1546static void
e315cd28 1547qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1548{
1549 unsigned long flags = 0;
1550 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1551
124f85e6
AV		 1552 if (IS_NOPOLLING_TYPE(ha))
1553 return;
fd34f556
AV		 1554 spin_lock_irqsave(&ha->hardware_lock, flags);
1555 ha->interrupts_on = 0;
1556 WRT_REG_DWORD(&reg->ictrl, 0);
1557 RD_REG_DWORD(&reg->ictrl);
1558 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1559}
1560
706f457d
GM		 1561static int
1562qla2x00_iospace_config(struct qla_hw_data *ha)
1563{
1564 resource_size_t pio;
1565 uint16_t msix;
1566 int cpus;
1567
706f457d
GM		 1568 if (pci_request_selected_regions(ha->pdev, ha->bars,
1569 QLA2XXX_DRIVER_NAME)) {
1570 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1571 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1572 pci_name(ha->pdev));
1573 goto iospace_error_exit;
1574 }
1575 if (!(ha->bars & 1))
1576 goto skip_pio;
1577
1578 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1579 pio = pci_resource_start(ha->pdev, 0);
1580 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1581 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1582 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1583 "Invalid pci I/O region size (%s).\n",
1584 pci_name(ha->pdev));
1585 pio = 0;
1586 }
1587 } else {
1588 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1589 "Region #0 no a PIO resource (%s).\n",
1590 pci_name(ha->pdev));
1591 pio = 0;
1592 }
1593 ha->pio_address = pio;
1594 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1595 "PIO address=%llu.\n",
1596 (unsigned long long)ha->pio_address);
1597
1598skip_pio:
1599 /* Use MMIO operations for all accesses. */
1600 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1601 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1602 "Region #1 not an MMIO resource (%s), aborting.\n",
1603 pci_name(ha->pdev));
1604 goto iospace_error_exit;
1605 }
1606 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1607 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1608 "Invalid PCI mem region size (%s), aborting.\n",
1609 pci_name(ha->pdev));
1610 goto iospace_error_exit;
1611 }
1612
1613 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1614 if (!ha->iobase) {
1615 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1616 "Cannot remap MMIO (%s), aborting.\n",
1617 pci_name(ha->pdev));
1618 goto iospace_error_exit;
1619 }
1620
1621 /* Determine queue resources */
1622 ha->max_req_queues = ha->max_rsp_queues = 1;
1623 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1624 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1625 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1626 goto mqiobase_exit;
1627
1628 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1629 pci_resource_len(ha->pdev, 3));
1630 if (ha->mqiobase) {
1631 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1632 "MQIO Base=%p.\n", ha->mqiobase);
1633 /* Read MSIX vector size of the board */
1634 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1635 ha->msix_count = msix;
1636 /* Max queues are bounded by available msix vectors */
1637 /* queue 0 uses two msix vectors */
1638 if (ql2xmultique_tag) {
1639 cpus = num_online_cpus();
1640 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1641 (cpus + 1) : (ha->msix_count - 1);
1642 ha->max_req_queues = 2;
1643 } else if (ql2xmaxqueues > 1) {
1644 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1645 QLA_MQ_SIZE : ql2xmaxqueues;
1646 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1647 "QoS mode set, max no of request queues:%d.\n",
1648 ha->max_req_queues);
1649 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1650 "QoS mode set, max no of request queues:%d.\n",
1651 ha->max_req_queues);
1652 }
1653 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1654 "MSI-X vector count: %d.\n", msix);
1655 } else
1656 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1657 "BAR 3 not enabled.\n");
1658
1659mqiobase_exit:
1660 ha->msix_count = ha->max_rsp_queues + 1;
1661 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1662 "MSIX Count:%d.\n", ha->msix_count);
1663 return (0);
1664
1665iospace_error_exit:
1666 return (-ENOMEM);
1667}
1668
1669
6246b8a1
GM		 1670static int
1671qla83xx_iospace_config(struct qla_hw_data *ha)
1672{
1673 uint16_t msix;
1674 int cpus;
1675
1676 if (pci_request_selected_regions(ha->pdev, ha->bars,
1677 QLA2XXX_DRIVER_NAME)) {
1678 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1679 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1680 pci_name(ha->pdev));
1681
1682 goto iospace_error_exit;
1683 }
1684
1685 /* Use MMIO operations for all accesses. */
1686 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1687 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1688 "Invalid pci I/O region size (%s).\n",
1689 pci_name(ha->pdev));
1690 goto iospace_error_exit;
1691 }
1692 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1693 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1694 "Invalid PCI mem region size (%s), aborting\n",
1695 pci_name(ha->pdev));
1696 goto iospace_error_exit;
1697 }
1698
1699 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1700 if (!ha->iobase) {
1701 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1702 "Cannot remap MMIO (%s), aborting.\n",
1703 pci_name(ha->pdev));
1704 goto iospace_error_exit;
1705 }
1706
1707 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1708 /* 83XX 26XX always use MQ type access for queues
1709 * - mbar 2, a.k.a region 4 */
1710 ha->max_req_queues = ha->max_rsp_queues = 1;
1711 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1712 pci_resource_len(ha->pdev, 4));
1713
1714 if (!ha->mqiobase) {
1715 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1716 "BAR2/region4 not enabled\n");
1717 goto mqiobase_exit;
1718 }
1719
1720 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1721 pci_resource_len(ha->pdev, 2));
1722 if (ha->msixbase) {
1723 /* Read MSIX vector size of the board */
1724 pci_read_config_word(ha->pdev,
1725 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1726 ha->msix_count = msix;
1727 /* Max queues are bounded by available msix vectors */
1728 /* queue 0 uses two msix vectors */
1729 if (ql2xmultique_tag) {
1730 cpus = num_online_cpus();
1731 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1732 (cpus + 1) : (ha->msix_count - 1);
1733 ha->max_req_queues = 2;
1734 } else if (ql2xmaxqueues > 1) {
1735 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1736 QLA_MQ_SIZE : ql2xmaxqueues;
1737 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1738 "QoS mode set, max no of request queues:%d.\n",
1739 ha->max_req_queues);
1740 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1741 "QoS mode set, max no of request queues:%d.\n",
1742 ha->max_req_queues);
1743 }
1744 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1745 "MSI-X vector count: %d.\n", msix);
1746 } else
1747 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1748 "BAR 1 not enabled.\n");
1749
1750mqiobase_exit:
1751 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1752
1753 qlt_83xx_iospace_config(ha);
1754
6246b8a1
GM		 1755 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1756 "MSIX Count:%d.\n", ha->msix_count);
1757 return 0;
1758
1759iospace_error_exit:
1760 return -ENOMEM;
1761}
1762
fd34f556
AV		 1763static struct isp_operations qla2100_isp_ops = {
1764 .pci_config = qla2100_pci_config,
1765 .reset_chip = qla2x00_reset_chip,
1766 .chip_diag = qla2x00_chip_diag,
1767 .config_rings = qla2x00_config_rings,
1768 .reset_adapter = qla2x00_reset_adapter,
1769 .nvram_config = qla2x00_nvram_config,
1770 .update_fw_options = qla2x00_update_fw_options,
1771 .load_risc = qla2x00_load_risc,
1772 .pci_info_str = qla2x00_pci_info_str,
1773 .fw_version_str = qla2x00_fw_version_str,
1774 .intr_handler = qla2100_intr_handler,
1775 .enable_intrs = qla2x00_enable_intrs,
1776 .disable_intrs = qla2x00_disable_intrs,
1777 .abort_command = qla2x00_abort_command,
523ec773
AV		 1778 .target_reset = qla2x00_abort_target,
1779 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1780 .fabric_login = qla2x00_login_fabric,
1781 .fabric_logout = qla2x00_fabric_logout,
1782 .calc_req_entries = qla2x00_calc_iocbs_32,
1783 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1784 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1785 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1786 .read_nvram = qla2x00_read_nvram_data,
1787 .write_nvram = qla2x00_write_nvram_data,
1788 .fw_dump = qla2100_fw_dump,
1789 .beacon_on = NULL,
1790 .beacon_off = NULL,
1791 .beacon_blink = NULL,
1792 .read_optrom = qla2x00_read_optrom_data,
1793 .write_optrom = qla2x00_write_optrom_data,
1794 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1795 .start_scsi = qla2x00_start_scsi,
a9083016 1796 .abort_isp = qla2x00_abort_isp,
706f457d 1797 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1798 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1799};
1800
1801static struct isp_operations qla2300_isp_ops = {
1802 .pci_config = qla2300_pci_config,
1803 .reset_chip = qla2x00_reset_chip,
1804 .chip_diag = qla2x00_chip_diag,
1805 .config_rings = qla2x00_config_rings,
1806 .reset_adapter = qla2x00_reset_adapter,
1807 .nvram_config = qla2x00_nvram_config,
1808 .update_fw_options = qla2x00_update_fw_options,
1809 .load_risc = qla2x00_load_risc,
1810 .pci_info_str = qla2x00_pci_info_str,
1811 .fw_version_str = qla2x00_fw_version_str,
1812 .intr_handler = qla2300_intr_handler,
1813 .enable_intrs = qla2x00_enable_intrs,
1814 .disable_intrs = qla2x00_disable_intrs,
1815 .abort_command = qla2x00_abort_command,
523ec773
AV		 1816 .target_reset = qla2x00_abort_target,
1817 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1818 .fabric_login = qla2x00_login_fabric,
1819 .fabric_logout = qla2x00_fabric_logout,
1820 .calc_req_entries = qla2x00_calc_iocbs_32,
1821 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1822 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1823 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1824 .read_nvram = qla2x00_read_nvram_data,
1825 .write_nvram = qla2x00_write_nvram_data,
1826 .fw_dump = qla2300_fw_dump,
1827 .beacon_on = qla2x00_beacon_on,
1828 .beacon_off = qla2x00_beacon_off,
1829 .beacon_blink = qla2x00_beacon_blink,
1830 .read_optrom = qla2x00_read_optrom_data,
1831 .write_optrom = qla2x00_write_optrom_data,
1832 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1833 .start_scsi = qla2x00_start_scsi,
a9083016 1834 .abort_isp = qla2x00_abort_isp,
7ec0effd 1835 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1836 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1837};
1838
1839static struct isp_operations qla24xx_isp_ops = {
1840 .pci_config = qla24xx_pci_config,
1841 .reset_chip = qla24xx_reset_chip,
1842 .chip_diag = qla24xx_chip_diag,
1843 .config_rings = qla24xx_config_rings,
1844 .reset_adapter = qla24xx_reset_adapter,
1845 .nvram_config = qla24xx_nvram_config,
1846 .update_fw_options = qla24xx_update_fw_options,
1847 .load_risc = qla24xx_load_risc,
1848 .pci_info_str = qla24xx_pci_info_str,
1849 .fw_version_str = qla24xx_fw_version_str,
1850 .intr_handler = qla24xx_intr_handler,
1851 .enable_intrs = qla24xx_enable_intrs,
1852 .disable_intrs = qla24xx_disable_intrs,
1853 .abort_command = qla24xx_abort_command,
523ec773
AV		 1854 .target_reset = qla24xx_abort_target,
1855 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1856 .fabric_login = qla24xx_login_fabric,
1857 .fabric_logout = qla24xx_fabric_logout,
1858 .calc_req_entries = NULL,
1859 .build_iocbs = NULL,
1860 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1861 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1862 .read_nvram = qla24xx_read_nvram_data,
1863 .write_nvram = qla24xx_write_nvram_data,
1864 .fw_dump = qla24xx_fw_dump,
1865 .beacon_on = qla24xx_beacon_on,
1866 .beacon_off = qla24xx_beacon_off,
1867 .beacon_blink = qla24xx_beacon_blink,
1868 .read_optrom = qla24xx_read_optrom_data,
1869 .write_optrom = qla24xx_write_optrom_data,
1870 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1871 .start_scsi = qla24xx_start_scsi,
a9083016 1872 .abort_isp = qla2x00_abort_isp,
7ec0effd 1873 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1874 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1875};
1876
c3a2f0df
AV		 1877static struct isp_operations qla25xx_isp_ops = {
1878 .pci_config = qla25xx_pci_config,
1879 .reset_chip = qla24xx_reset_chip,
1880 .chip_diag = qla24xx_chip_diag,
1881 .config_rings = qla24xx_config_rings,
1882 .reset_adapter = qla24xx_reset_adapter,
1883 .nvram_config = qla24xx_nvram_config,
1884 .update_fw_options = qla24xx_update_fw_options,
1885 .load_risc = qla24xx_load_risc,
1886 .pci_info_str = qla24xx_pci_info_str,
1887 .fw_version_str = qla24xx_fw_version_str,
1888 .intr_handler = qla24xx_intr_handler,
1889 .enable_intrs = qla24xx_enable_intrs,
1890 .disable_intrs = qla24xx_disable_intrs,
1891 .abort_command = qla24xx_abort_command,
523ec773
AV		 1892 .target_reset = qla24xx_abort_target,
1893 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1894 .fabric_login = qla24xx_login_fabric,
1895 .fabric_logout = qla24xx_fabric_logout,
1896 .calc_req_entries = NULL,
1897 .build_iocbs = NULL,
1898 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1899 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1900 .read_nvram = qla25xx_read_nvram_data,
1901 .write_nvram = qla25xx_write_nvram_data,
1902 .fw_dump = qla25xx_fw_dump,
1903 .beacon_on = qla24xx_beacon_on,
1904 .beacon_off = qla24xx_beacon_off,
1905 .beacon_blink = qla24xx_beacon_blink,
338c9161 1906 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1907 .write_optrom = qla24xx_write_optrom_data,
1908 .get_flash_version = qla24xx_get_flash_version,
bad75002 1909 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1910 .abort_isp = qla2x00_abort_isp,
7ec0effd 1911 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1912 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1913};
1914
3a03eb79
AV		 1915static struct isp_operations qla81xx_isp_ops = {
1916 .pci_config = qla25xx_pci_config,
1917 .reset_chip = qla24xx_reset_chip,
1918 .chip_diag = qla24xx_chip_diag,
1919 .config_rings = qla24xx_config_rings,
1920 .reset_adapter = qla24xx_reset_adapter,
1921 .nvram_config = qla81xx_nvram_config,
1922 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1923 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1924 .pci_info_str = qla24xx_pci_info_str,
1925 .fw_version_str = qla24xx_fw_version_str,
1926 .intr_handler = qla24xx_intr_handler,
1927 .enable_intrs = qla24xx_enable_intrs,
1928 .disable_intrs = qla24xx_disable_intrs,
1929 .abort_command = qla24xx_abort_command,
1930 .target_reset = qla24xx_abort_target,
1931 .lun_reset = qla24xx_lun_reset,
1932 .fabric_login = qla24xx_login_fabric,
1933 .fabric_logout = qla24xx_fabric_logout,
1934 .calc_req_entries = NULL,
1935 .build_iocbs = NULL,
1936 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1937 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1938 .read_nvram = NULL,
1939 .write_nvram = NULL,
3a03eb79
AV		 1940 .fw_dump = qla81xx_fw_dump,
1941 .beacon_on = qla24xx_beacon_on,
1942 .beacon_off = qla24xx_beacon_off,
6246b8a1 1943 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1944 .read_optrom = qla25xx_read_optrom_data,
1945 .write_optrom = qla24xx_write_optrom_data,
1946 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1947 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1948 .abort_isp = qla2x00_abort_isp,
7ec0effd 1949 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1950 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1951};
1952
1953static struct isp_operations qla82xx_isp_ops = {
1954 .pci_config = qla82xx_pci_config,
1955 .reset_chip = qla82xx_reset_chip,
1956 .chip_diag = qla24xx_chip_diag,
1957 .config_rings = qla82xx_config_rings,
1958 .reset_adapter = qla24xx_reset_adapter,
1959 .nvram_config = qla81xx_nvram_config,
1960 .update_fw_options = qla24xx_update_fw_options,
1961 .load_risc = qla82xx_load_risc,
9d55ca66 1962 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1963 .fw_version_str = qla24xx_fw_version_str,
1964 .intr_handler = qla82xx_intr_handler,
1965 .enable_intrs = qla82xx_enable_intrs,
1966 .disable_intrs = qla82xx_disable_intrs,
1967 .abort_command = qla24xx_abort_command,
1968 .target_reset = qla24xx_abort_target,
1969 .lun_reset = qla24xx_lun_reset,
1970 .fabric_login = qla24xx_login_fabric,
1971 .fabric_logout = qla24xx_fabric_logout,
1972 .calc_req_entries = NULL,
1973 .build_iocbs = NULL,
1974 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1975 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1976 .read_nvram = qla24xx_read_nvram_data,
1977 .write_nvram = qla24xx_write_nvram_data,
1978 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1979 .beacon_on = qla82xx_beacon_on,
1980 .beacon_off = qla82xx_beacon_off,
1981 .beacon_blink = NULL,
a9083016
GM		 1982 .read_optrom = qla82xx_read_optrom_data,
1983 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1984 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1985 .start_scsi = qla82xx_start_scsi,
1986 .abort_isp = qla82xx_abort_isp,
706f457d 1987 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1988 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1989};
1990
7ec0effd
AD		 1991static struct isp_operations qla8044_isp_ops = {
1992 .pci_config = qla82xx_pci_config,
1993 .reset_chip = qla82xx_reset_chip,
1994 .chip_diag = qla24xx_chip_diag,
1995 .config_rings = qla82xx_config_rings,
1996 .reset_adapter = qla24xx_reset_adapter,
1997 .nvram_config = qla81xx_nvram_config,
1998 .update_fw_options = qla24xx_update_fw_options,
1999 .load_risc = qla82xx_load_risc,
2000 .pci_info_str = qla24xx_pci_info_str,
2001 .fw_version_str = qla24xx_fw_version_str,
2002 .intr_handler = qla8044_intr_handler,
2003 .enable_intrs = qla82xx_enable_intrs,
2004 .disable_intrs = qla82xx_disable_intrs,
2005 .abort_command = qla24xx_abort_command,
2006 .target_reset = qla24xx_abort_target,
2007 .lun_reset = qla24xx_lun_reset,
2008 .fabric_login = qla24xx_login_fabric,
2009 .fabric_logout = qla24xx_fabric_logout,
2010 .calc_req_entries = NULL,
2011 .build_iocbs = NULL,
2012 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2013 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2014 .read_nvram = NULL,
2015 .write_nvram = NULL,
2016 .fw_dump = qla24xx_fw_dump,
2017 .beacon_on = qla82xx_beacon_on,
2018 .beacon_off = qla82xx_beacon_off,
2019 .beacon_blink = NULL,
2020 .read_optrom = qla82xx_read_optrom_data,
2021 .write_optrom = qla8044_write_optrom_data,
2022 .get_flash_version = qla82xx_get_flash_version,
2023 .start_scsi = qla82xx_start_scsi,
2024 .abort_isp = qla8044_abort_isp,
2025 .iospace_config = qla82xx_iospace_config,
2026 .initialize_adapter = qla2x00_initialize_adapter,
2027};
2028
6246b8a1
GM		 2029static struct isp_operations qla83xx_isp_ops = {
2030 .pci_config = qla25xx_pci_config,
2031 .reset_chip = qla24xx_reset_chip,
2032 .chip_diag = qla24xx_chip_diag,
2033 .config_rings = qla24xx_config_rings,
2034 .reset_adapter = qla24xx_reset_adapter,
2035 .nvram_config = qla81xx_nvram_config,
2036 .update_fw_options = qla81xx_update_fw_options,
2037 .load_risc = qla81xx_load_risc,
2038 .pci_info_str = qla24xx_pci_info_str,
2039 .fw_version_str = qla24xx_fw_version_str,
2040 .intr_handler = qla24xx_intr_handler,
2041 .enable_intrs = qla24xx_enable_intrs,
2042 .disable_intrs = qla24xx_disable_intrs,
2043 .abort_command = qla24xx_abort_command,
2044 .target_reset = qla24xx_abort_target,
2045 .lun_reset = qla24xx_lun_reset,
2046 .fabric_login = qla24xx_login_fabric,
2047 .fabric_logout = qla24xx_fabric_logout,
2048 .calc_req_entries = NULL,
2049 .build_iocbs = NULL,
2050 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2051 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2052 .read_nvram = NULL,
2053 .write_nvram = NULL,
2054 .fw_dump = qla83xx_fw_dump,
2055 .beacon_on = qla24xx_beacon_on,
2056 .beacon_off = qla24xx_beacon_off,
2057 .beacon_blink = qla83xx_beacon_blink,
2058 .read_optrom = qla25xx_read_optrom_data,
2059 .write_optrom = qla24xx_write_optrom_data,
2060 .get_flash_version = qla24xx_get_flash_version,
2061 .start_scsi = qla24xx_dif_start_scsi,
2062 .abort_isp = qla2x00_abort_isp,
2063 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2064 .initialize_adapter = qla2x00_initialize_adapter,
2065};
2066
2067static struct isp_operations qlafx00_isp_ops = {
2068 .pci_config = qlafx00_pci_config,
2069 .reset_chip = qlafx00_soft_reset,
2070 .chip_diag = qlafx00_chip_diag,
2071 .config_rings = qlafx00_config_rings,
2072 .reset_adapter = qlafx00_soft_reset,
2073 .nvram_config = NULL,
2074 .update_fw_options = NULL,
2075 .load_risc = NULL,
2076 .pci_info_str = qlafx00_pci_info_str,
2077 .fw_version_str = qlafx00_fw_version_str,
2078 .intr_handler = qlafx00_intr_handler,
2079 .enable_intrs = qlafx00_enable_intrs,
2080 .disable_intrs = qlafx00_disable_intrs,
2081 .abort_command = qlafx00_abort_command,
2082 .target_reset = qlafx00_abort_target,
2083 .lun_reset = qlafx00_lun_reset,
2084 .fabric_login = NULL,
2085 .fabric_logout = NULL,
2086 .calc_req_entries = NULL,
2087 .build_iocbs = NULL,
2088 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2089 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2090 .read_nvram = qla24xx_read_nvram_data,
2091 .write_nvram = qla24xx_write_nvram_data,
2092 .fw_dump = NULL,
2093 .beacon_on = qla24xx_beacon_on,
2094 .beacon_off = qla24xx_beacon_off,
2095 .beacon_blink = NULL,
2096 .read_optrom = qla24xx_read_optrom_data,
2097 .write_optrom = qla24xx_write_optrom_data,
2098 .get_flash_version = qla24xx_get_flash_version,
2099 .start_scsi = qlafx00_start_scsi,
2100 .abort_isp = qlafx00_abort_isp,
2101 .iospace_config = qlafx00_iospace_config,
2102 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2103};
2104
ea5b6382 2105static inline void
e315cd28 2106qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2107{
2108 ha->device_type = DT_EXTENDED_IDS;
2109 switch (ha->pdev->device) {
2110 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2111 ha->device_type |= DT_ISP2100;
2112 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2113 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2114 break;
2115 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2116 ha->device_type |= DT_ISP2200;
2117 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2118 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2119 break;
2120 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2121 ha->device_type |= DT_ISP2300;
4a59f71d 2122 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2123 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2124 break;
2125 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2126 ha->device_type |= DT_ISP2312;
4a59f71d 2127 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2128 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2129 break;
2130 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2131 ha->device_type |= DT_ISP2322;
4a59f71d 2132 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2133 if (ha->pdev->subsystem_vendor == 0x1028 &&
2134 ha->pdev->subsystem_device == 0x0170)
2135 ha->device_type |= DT_OEM_001;
441d1072 2136 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2137 break;
2138 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2139 ha->device_type |= DT_ISP6312;
441d1072 2140 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2141 break;
2142 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2143 ha->device_type |= DT_ISP6322;
441d1072 2144 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2145 break;
2146 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2147 ha->device_type |= DT_ISP2422;
4a59f71d 2148 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2149 ha->device_type |= DT_FWI2;
c76f2c01 2150 ha->device_type |= DT_IIDMA;
441d1072 2151 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2152 break;
2153 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2154 ha->device_type |= DT_ISP2432;
4a59f71d 2155 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2156 ha->device_type |= DT_FWI2;
c76f2c01 2157 ha->device_type |= DT_IIDMA;
441d1072 2158 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2159 break;
4d4df193
HK		 2160 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2161 ha->device_type |= DT_ISP8432;
2162 ha->device_type |= DT_ZIO_SUPPORTED;
2163 ha->device_type |= DT_FWI2;
2164 ha->device_type |= DT_IIDMA;
2165 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2166 break;
044cc6c8
AV		 2167 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2168 ha->device_type |= DT_ISP5422;
e428924c 2169 ha->device_type |= DT_FWI2;
441d1072 2170 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2171 break;
044cc6c8
AV		 2172 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2173 ha->device_type |= DT_ISP5432;
e428924c 2174 ha->device_type |= DT_FWI2;
441d1072 2175 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2176 break;
c3a2f0df
AV		 2177 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2178 ha->device_type |= DT_ISP2532;
2179 ha->device_type |= DT_ZIO_SUPPORTED;
2180 ha->device_type |= DT_FWI2;
2181 ha->device_type |= DT_IIDMA;
441d1072 2182 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2183 break;
3a03eb79
AV		 2184 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2185 ha->device_type |= DT_ISP8001;
2186 ha->device_type |= DT_ZIO_SUPPORTED;
2187 ha->device_type |= DT_FWI2;
2188 ha->device_type |= DT_IIDMA;
2189 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2190 break;
a9083016
GM		 2191 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2192 ha->device_type |= DT_ISP8021;
2193 ha->device_type |= DT_ZIO_SUPPORTED;
2194 ha->device_type |= DT_FWI2;
2195 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2196 /* Initialize 82XX ISP flags */
2197 qla82xx_init_flags(ha);
2198 break;
7ec0effd
AD		 2199 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2200 ha->device_type |= DT_ISP8044;
2201 ha->device_type |= DT_ZIO_SUPPORTED;
2202 ha->device_type |= DT_FWI2;
2203 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2204 /* Initialize 82XX ISP flags */
2205 qla82xx_init_flags(ha);
2206 break;
6246b8a1
GM		 2207 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2208 ha->device_type |= DT_ISP2031;
2209 ha->device_type |= DT_ZIO_SUPPORTED;
2210 ha->device_type |= DT_FWI2;
2211 ha->device_type |= DT_IIDMA;
2212 ha->device_type |= DT_T10_PI;
2213 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2214 break;
2215 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2216 ha->device_type |= DT_ISP8031;
2217 ha->device_type |= DT_ZIO_SUPPORTED;
2218 ha->device_type |= DT_FWI2;
2219 ha->device_type |= DT_IIDMA;
2220 ha->device_type |= DT_T10_PI;
2221 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2222 break;
8ae6d9c7
GM		 2223 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2224 ha->device_type |= DT_ISPFX00;
2225 break;
ea5b6382 2226 }
e5b68a61 2227
a9083016
GM		 2228 if (IS_QLA82XX(ha))
2229 ha->port_no = !(ha->portnum & 1);
2230 else
2231 /* Get adapter physical port no from interrupt pin register. */
2232 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2233
e5b68a61
AC		 2234 if (ha->port_no & 1)
2235 ha->flags.port0 = 1;
2236 else
2237 ha->flags.port0 = 0;
7c3df132 2238 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2239 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2240 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 2241}
2242
1e99e33a
AV		 2243static void
2244qla2xxx_scan_start(struct Scsi_Host *shost)
2245{
e315cd28 2246 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2247
cbc8eb67
AV		 2248 if (vha->hw->flags.running_gold_fw)
2249 return;
2250
e315cd28
AC		 2251 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2252 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2253 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2254 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2255}
2256
2257static int
2258qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2259{
e315cd28 2260 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2261
e315cd28 2262 if (!vha->host)
1e99e33a 2263 return 1;
e315cd28 2264 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2265 return 1;
2266
e315cd28 2267 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2268}
2269
1da177e4
LT		 2270/*
2271 * PCI driver interface
2272 */
6f039790 2273static int
7ee61397 2274qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2275{
a1541d5a 2276 int ret = -ENODEV;
1da177e4 2277 struct Scsi_Host *host;
e315cd28
AC		 2278 scsi_qla_host_t *base_vha = NULL;
2279 struct qla_hw_data *ha;
29856e28 2280 char pci_info[30];
7d613ac6 2281 char fw_str[30], wq_name[30];
5433383e 2282 struct scsi_host_template *sht;
642ef983 2283 int bars, mem_only = 0;
e315cd28 2284 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2285 struct req_que *req = NULL;
2286 struct rsp_que *rsp = NULL;
285d0321 2287 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2288 sht = &qla2xxx_driver_template;
5433383e 2289 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2290 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2291 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2292 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2293 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2294 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2295 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2296 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2297 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2298 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd
AD		 2299 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2300 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044) {
285d0321 2301 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2302 mem_only = 1;
7c3df132
SK		 2303 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2304 "Mem only adapter.\n");
285d0321 2305 }
7c3df132
SK		 2306 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2307 "Bars=%d.\n", bars);
285d0321 2308
09483916
BH		 2309 if (mem_only) {
2310 if (pci_enable_device_mem(pdev))
2311 goto probe_out;
2312 } else {
2313 if (pci_enable_device(pdev))
2314 goto probe_out;
2315 }
285d0321 2316
0927678f
JB		 2317 /* This may fail but that's ok */
2318 pci_enable_pcie_error_reporting(pdev);
285d0321 2319
e315cd28
AC		 2320 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2321 if (!ha) {
7c3df132
SK		 2322 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2323 "Unable to allocate memory for ha.\n");
e315cd28 2324 goto probe_out;
1da177e4 2325 }
7c3df132
SK		 2326 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2327 "Memory allocated for ha=%p.\n", ha);
e315cd28 2328 ha->pdev = pdev;
2d70c103 2329 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2330
2331 /* Clear our data area */
285d0321 2332 ha->bars = bars;
09483916 2333 ha->mem_only = mem_only;
df4bf0bb 2334 spin_lock_init(&ha->hardware_lock);
339aa70e 2335 spin_lock_init(&ha->vport_slock);
a9b6f722 2336 mutex_init(&ha->selflogin_lock);
1da177e4 2337
ea5b6382
AV		 2338 /* Set ISP-type information. */
2339 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2340
2341 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2342 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2343 IS_QLA83XX(ha))
ca79cf66 2344 pdev->needs_freset = 1;
ca79cf66 2345
cba1e47f
CD		 2346 ha->prev_topology = 0;
2347 ha->init_cb_size = sizeof(init_cb_t);
2348 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2349 ha->optrom_size = OPTROM_SIZE_2300;
2350
abbd8870 2351 /* Assign ISP specific operations. */
1da177e4 2352 if (IS_QLA2100(ha)) {
642ef983 2353 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2354 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2355 req_length = REQUEST_ENTRY_CNT_2100;
2356 rsp_length = RESPONSE_ENTRY_CNT_2100;
2357 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2358 ha->gid_list_info_size = 4;
3a03eb79
AV		 2359 ha->flash_conf_off = ~0;
2360 ha->flash_data_off = ~0;
2361 ha->nvram_conf_off = ~0;
2362 ha->nvram_data_off = ~0;
fd34f556 2363 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2364 } else if (IS_QLA2200(ha)) {
642ef983 2365 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2366 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2367 req_length = REQUEST_ENTRY_CNT_2200;
2368 rsp_length = RESPONSE_ENTRY_CNT_2100;
2369 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2370 ha->gid_list_info_size = 4;
3a03eb79
AV		 2371 ha->flash_conf_off = ~0;
2372 ha->flash_data_off = ~0;
2373 ha->nvram_conf_off = ~0;
2374 ha->nvram_data_off = ~0;
fd34f556 2375 ha->isp_ops = &qla2100_isp_ops;
fca29703 2376 } else if (IS_QLA23XX(ha)) {
642ef983 2377 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2378 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2379 req_length = REQUEST_ENTRY_CNT_2200;
2380 rsp_length = RESPONSE_ENTRY_CNT_2300;
2381 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2382 ha->gid_list_info_size = 6;
854165f4
AV		 2383 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2384 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2385 ha->flash_conf_off = ~0;
2386 ha->flash_data_off = ~0;
2387 ha->nvram_conf_off = ~0;
2388 ha->nvram_data_off = ~0;
fd34f556 2389 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2390 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2391 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2392 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2393 req_length = REQUEST_ENTRY_CNT_24XX;
2394 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2395 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2396 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2397 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2398 ha->gid_list_info_size = 8;
854165f4 2399 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2400 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2401 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2402 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2403 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2404 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2405 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2406 } else if (IS_QLA25XX(ha)) {
642ef983 2407 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2408 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2409 req_length = REQUEST_ENTRY_CNT_24XX;
2410 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2411 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2412 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2413 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2414 ha->gid_list_info_size = 8;
2415 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2416 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2417 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2418 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2419 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2420 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2421 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2422 } else if (IS_QLA81XX(ha)) {
642ef983 2423 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2424 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2425 req_length = REQUEST_ENTRY_CNT_24XX;
2426 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2427 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2428 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2429 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2430 ha->gid_list_info_size = 8;
2431 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2432 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2433 ha->isp_ops = &qla81xx_isp_ops;
2434 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2435 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2436 ha->nvram_conf_off = ~0;
2437 ha->nvram_data_off = ~0;
a9083016 2438 } else if (IS_QLA82XX(ha)) {
642ef983 2439 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2440 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2441 req_length = REQUEST_ENTRY_CNT_82XX;
2442 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2443 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2444 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2445 ha->gid_list_info_size = 8;
2446 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2447 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2448 ha->isp_ops = &qla82xx_isp_ops;
2449 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2450 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2451 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2452 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2453 } else if (IS_QLA8044(ha)) {
2454 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2455 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2456 req_length = REQUEST_ENTRY_CNT_82XX;
2457 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2458 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2459 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2460 ha->gid_list_info_size = 8;
2461 ha->optrom_size = OPTROM_SIZE_83XX;
2462 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2463 ha->isp_ops = &qla8044_isp_ops;
2464 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2465 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2466 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2467 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2468 } else if (IS_QLA83XX(ha)) {
7d613ac6 2469 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2470 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2471 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2472 req_length = REQUEST_ENTRY_CNT_24XX;
2473 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2474 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2475 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2476 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2477 ha->gid_list_info_size = 8;
2478 ha->optrom_size = OPTROM_SIZE_83XX;
2479 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2480 ha->isp_ops = &qla83xx_isp_ops;
2481 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2482 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2483 ha->nvram_conf_off = ~0;
2484 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2485 } else if (IS_QLAFX00(ha)) {
2486 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2487 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2488 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2489 req_length = REQUEST_ENTRY_CNT_FX00;
2490 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2491 ha->init_cb_size = sizeof(struct init_cb_fx);
2492 ha->isp_ops = &qlafx00_isp_ops;
2493 ha->port_down_retry_count = 30; /* default value */
2494 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2495 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2496 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2497 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2498 ha->mr.host_info_resend = false;
2499 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
1da177e4 2500 }
6246b8a1 2501
7c3df132
SK		 2502 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2503 "mbx_count=%d, req_length=%d, "
2504 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2505 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2506 "max_fibre_devices=%d.\n",
7c3df132
SK		 2507 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2508 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2509 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2510 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2511 "isp_ops=%p, flash_conf_off=%d, "
2512 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2513 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2514 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2515
2516 /* Configure PCI I/O space */
2517 ret = ha->isp_ops->iospace_config(ha);
2518 if (ret)
0a63ad12 2519 goto iospace_config_failed;
706f457d
GM		 2520
2521 ql_log_pci(ql_log_info, pdev, 0x001d,
2522 "Found an ISP%04X irq %d iobase 0x%p.\n",
2523 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2524 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2525 init_completion(&ha->mbx_cmd_comp);
2526 complete(&ha->mbx_cmd_comp);
2527 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2528 init_completion(&ha->dcbx_comp);
f356bef1 2529 init_completion(&ha->lb_portup_comp);
1da177e4 2530
2c3dfe3f 2531 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2532
53303c42 2533 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2534 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2535 "64 Bit addressing is %s.\n",
2536 ha->flags.enable_64bit_addressing ? "enable" :
2537 "disable");
73208dfd 2538 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2539 if (!ret) {
7c3df132
SK		 2540 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2541 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2542
e315cd28
AC		 2543 goto probe_hw_failed;
2544 }
2545
73208dfd 2546 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2547 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2548 req->max_q_depth = ql2xmaxqdepth;
2549
e315cd28
AC		 2550
2551 base_vha = qla2x00_create_host(sht, ha);
2552 if (!base_vha) {
a1541d5a 2553 ret = -ENOMEM;
6e9f21f3 2554 qla2x00_mem_free(ha);
2afa19a9
AC		 2555 qla2x00_free_req_que(ha, req);
2556 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2557 goto probe_hw_failed;
1da177e4
LT		 2558 }
2559
e315cd28
AC		 2560 pci_set_drvdata(pdev, base_vha);
2561
e315cd28 2562 host = base_vha->host;
2afa19a9 2563 base_vha->req = req;
8ae6d9c7
GM		 2564 if (IS_QLAFX00(ha))
2565 host->can_queue = 1024;
2566 else
2567 host->can_queue = req->length + 128;
73208dfd 2568 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2569 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2570 else
e315cd28
AC		 2571 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2572 base_vha->vp_idx;
58548cb5 2573
8ae6d9c7
GM		 2574 /* Setup fcport template structure. */
2575 ha->mr.fcport.vha = base_vha;
2576 ha->mr.fcport.port_type = FCT_UNKNOWN;
2577 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2578 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2579 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2580 ha->mr.fcport.scan_state = 1;
2581
58548cb5
GM		 2582 /* Set the SG table size based on ISP type */
2583 if (!IS_FWI2_CAPABLE(ha)) {
2584 if (IS_QLA2100(ha))
2585 host->sg_tablesize = 32;
2586 } else {
2587 if (!IS_QLA82XX(ha))
2588 host->sg_tablesize = QLA_SG_ALL;
2589 }
7c3df132
SK		 2590 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2591 "can_queue=%d, req=%p, "
2592 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2593 host->can_queue, base_vha->req,
2594 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2595 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2596 host->cmd_per_lun = 3;
2597 host->unique_id = host->host_no;
e02587d7 2598 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2599 host->max_cmd_len = 32;
2600 else
2601 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2602 host->max_channel = MAX_BUSES - 1;
82515920 2603 host->max_lun = ql2xmaxlun;
e315cd28 2604 host->transportt = qla2xxx_transport_template;
9a069e19 2605 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2606
7c3df132
SK		 2607 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2608 "max_id=%d this_id=%d "
2609 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2610 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2611 host->this_id, host->cmd_per_lun, host->unique_id,
2612 host->max_cmd_len, host->max_channel, host->max_lun,
2613 host->transportt, sht->vendor_id);
2614
9a347ff4
CD		 2615que_init:
2616 /* Alloc arrays of request and response ring ptrs */
2617 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2618 ql_log(ql_log_fatal, base_vha, 0x003d,
2619 "Failed to allocate memory for queue pointers..."
2620 "aborting.\n");
2621 goto probe_init_failed;
2622 }
2623
2d70c103 2624 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2625
73208dfd
AC		 2626 /* Set up the irqs */
2627 ret = qla2x00_request_irqs(ha, rsp);
2628 if (ret)
6e9f21f3 2629 goto probe_init_failed;
90a86fc0
JC		 2630
2631 pci_save_state(pdev);
2632
9a347ff4 2633 /* Assign back pointers */
2afa19a9
AC		 2634 rsp->req = req;
2635 req->rsp = rsp;
9a347ff4 2636
8ae6d9c7
GM		 2637 if (IS_QLAFX00(ha)) {
2638 ha->rsp_q_map[0] = rsp;
2639 ha->req_q_map[0] = req;
2640 set_bit(0, ha->req_qid_map);
2641 set_bit(0, ha->rsp_qid_map);
2642 }
2643
08029990
AV		 2644 /* FWI2-capable only. */
2645 req->req_q_in = &ha->iobase->isp24.req_q_in;
2646 req->req_q_out = &ha->iobase->isp24.req_q_out;
2647 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2648 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2649 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2650 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2651 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2652 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2653 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2654 }
2655
8ae6d9c7
GM		 2656 if (IS_QLAFX00(ha)) {
2657 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2658 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2659 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2660 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2661 }
2662
7ec0effd 2663 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2664 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2665 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2666 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2667 }
2668
7c3df132
SK		 2669 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2670 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2671 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2672 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2673 "req->req_q_in=%p req->req_q_out=%p "
2674 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2675 req->req_q_in, req->req_q_out,
2676 rsp->rsp_q_in, rsp->rsp_q_out);
2677 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2678 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2679 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2680 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2681 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2682 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2683
8ae6d9c7 2684 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2685 ql_log(ql_log_fatal, base_vha, 0x00d6,
2686 "Failed to initialize adapter - Adapter flags %x.\n",
2687 base_vha->device_flags);
1da177e4 2688
a9083016
GM		 2689 if (IS_QLA82XX(ha)) {
2690 qla82xx_idc_lock(ha);
2691 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2692 QLA8XXX_DEV_FAILED);
a9083016 2693 qla82xx_idc_unlock(ha);
7c3df132
SK		 2694 ql_log(ql_log_fatal, base_vha, 0x00d7,
2695 "HW State: FAILED.\n");
7ec0effd
AD		 2696 } else if (IS_QLA8044(ha)) {
2697 qla8044_idc_lock(ha);
2698 qla8044_wr_direct(base_vha,
2699 QLA8044_CRB_DEV_STATE_INDEX,
2700 QLA8XXX_DEV_FAILED);
2701 qla8044_idc_unlock(ha);
2702 ql_log(ql_log_fatal, base_vha, 0x0150,
2703 "HW State: FAILED.\n");
a9083016
GM		 2704 }
2705
a1541d5a 2706 ret = -ENODEV;
1da177e4
LT		 2707 goto probe_failed;
2708 }
2709
7163ea81
AC		 2710 if (ha->mqenable) {
2711 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2712 ql_log(ql_log_warn, base_vha, 0x00ec,
2713 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2714 goto que_init;
2715 }
2716 }
68ca949c 2717
cbc8eb67
AV		 2718 if (ha->flags.running_gold_fw)
2719 goto skip_dpc;
2720
1da177e4
LT		 2721 /*
2722 * Startup the kernel thread for this host adapter
2723 */
39a11240 2724 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2725 "%s_dpc", base_vha->host_str);
39a11240 2726 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2727 ql_log(ql_log_fatal, base_vha, 0x00ed,
2728 "Failed to start DPC thread.\n");
39a11240 2729 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2730 goto probe_failed;
2731 }
7c3df132
SK		 2732 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2733 "DPC thread started successfully.\n");
1da177e4 2734
2d70c103
NB		 2735 /*
2736 * If we're not coming up in initiator mode, we might sit for
2737 * a while without waking up the dpc thread, which leads to a
2738 * stuck process warning. So just kick the dpc once here and
2739 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2740 */
2741 qla2xxx_wake_dpc(base_vha);
2742
f3ddac19
CD		 2743 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2744
81178772
SK		 2745 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2746 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2747 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2748 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2749
2750 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2751 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2752 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2753 INIT_WORK(&ha->idc_state_handler,
2754 qla83xx_idc_state_handler_work);
2755 INIT_WORK(&ha->nic_core_unrecoverable,
2756 qla83xx_nic_core_unrecoverable_work);
2757 }
2758
cbc8eb67 2759skip_dpc:
e315cd28
AC		 2760 list_add_tail(&base_vha->list, &ha->vp_list);
2761 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2762
2763 /* Initialized the timer */
e315cd28 2764 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2765 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2766 "Started qla2x00_timer with "
2767 "interval=%d.\n", WATCH_INTERVAL);
2768 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2769 "Detected hba at address=%p.\n",
2770 ha);
d19044c3 2771
e02587d7 2772 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2773 if (ha->fw_attributes & BIT_4) {
9e522cd8 2774 int prot = 0, guard;
bad75002 2775 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2776 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2777 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2778 if (ql2xenabledif == 1)
2779 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2780 scsi_host_set_prot(host,
8cb2049c 2781 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2782 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2783 | SHOST_DIF_TYPE3_PROTECTION
2784 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2785 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2786 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2787
2788 guard = SHOST_DIX_GUARD_CRC;
2789
2790 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2791 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2792 guard |= SHOST_DIX_GUARD_IP;
2793
2794 scsi_host_set_guard(host, guard);
bad75002
AE		 2795 } else
2796 base_vha->flags.difdix_supported = 0;
2797 }
2798
a9083016
GM		 2799 ha->isp_ops->enable_intrs(ha);
2800
1fe19ee4
AB		 2801 if (IS_QLAFX00(ha)) {
2802 ret = qlafx00_fx_disc(base_vha,
2803 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2804 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2805 QLA_SG_ALL : 128;
2806 }
2807
a1541d5a
AV		 2808 ret = scsi_add_host(host, &pdev->dev);
2809 if (ret)
2810 goto probe_failed;
2811
1486400f
MR		 2812 base_vha->flags.init_done = 1;
2813 base_vha->flags.online = 1;
2814
7c3df132
SK		 2815 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2816 "Init done and hba is online.\n");
2817
2d70c103
NB		 2818 if (qla_ini_mode_enabled(base_vha))
2819 scsi_scan_host(host);
2820 else
2821 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2822 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2823
e315cd28 2824 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2825
8ae6d9c7 2826 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2827 ret = qlafx00_fx_disc(base_vha,
2828 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2829
2830 /* Register system information */
2831 ret = qlafx00_fx_disc(base_vha,
2832 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2833 }
2834
e315cd28 2835 qla2x00_init_host_attr(base_vha);
a1541d5a 2836
e315cd28 2837 qla2x00_dfs_setup(base_vha);
df613b96 2838
a324031c
AB		 2839 if (IS_QLAFX00(ha))
2840 ql_log(ql_log_info, base_vha, 0x015a,
2841 "QLogic %s.\n", ha->mr.product_name);
2842 else
2843 ql_log(ql_log_info, base_vha, 0x00fb,
2844 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2845 ql_log(ql_log_info, base_vha, 0x00fc,
2846 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2847 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2848 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2849 base_vha->host_no,
e315cd28 2850 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2851
2d70c103
NB		 2852 qlt_add_target(ha, base_vha);
2853
1da177e4
LT		 2854 return 0;
2855
6e9f21f3 2856probe_init_failed:
2afa19a9 2857 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2858 ha->req_q_map[0] = NULL;
2859 clear_bit(0, ha->req_qid_map);
2afa19a9 2860 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2861 ha->rsp_q_map[0] = NULL;
2862 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2863 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2864
1da177e4 2865probe_failed:
b9978769
AV		 2866 if (base_vha->timer_active)
2867 qla2x00_stop_timer(base_vha);
2868 base_vha->flags.online = 0;
2869 if (ha->dpc_thread) {
2870 struct task_struct *t = ha->dpc_thread;
2871
2872 ha->dpc_thread = NULL;
2873 kthread_stop(t);
2874 }
2875
e315cd28 2876 qla2x00_free_device(base_vha);
1da177e4 2877
e315cd28 2878 scsi_host_put(base_vha->host);
1da177e4 2879
e315cd28 2880probe_hw_failed:
a9083016
GM		 2881 if (IS_QLA82XX(ha)) {
2882 qla82xx_idc_lock(ha);
2883 qla82xx_clear_drv_active(ha);
2884 qla82xx_idc_unlock(ha);
0a63ad12 2885 }
7ec0effd
AD		 2886 if (IS_QLA8044(ha)) {
2887 qla8044_idc_lock(ha);
2888 qla8044_clear_drv_active(base_vha);
2889 qla8044_idc_unlock(ha);
2890 }
0a63ad12 2891iospace_config_failed:
7ec0effd 2892 if (IS_P3P_TYPE(ha)) {
0a63ad12
SK		 2893 if (!ha->nx_pcibase)
2894 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
a9083016
GM		 2895 if (!ql2xdbwr)
2896 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2897 } else {
2898 if (ha->iobase)
2899 iounmap(ha->iobase);
8ae6d9c7
GM		 2900 if (ha->cregbase)
2901 iounmap(ha->cregbase);
a9083016 2902 }
e315cd28
AC		 2903 pci_release_selected_regions(ha->pdev, ha->bars);
2904 kfree(ha);
2905 ha = NULL;
1da177e4 2906
a1541d5a 2907probe_out:
e315cd28 2908 pci_disable_device(pdev);
a1541d5a 2909 return ret;
1da177e4 2910}
1da177e4 2911
e30d1756
MI		 2912static void
2913qla2x00_shutdown(struct pci_dev *pdev)
2914{
2915 scsi_qla_host_t *vha;
2916 struct qla_hw_data *ha;
2917
552f3f9a
MI		 2918 if (!atomic_read(&pdev->enable_cnt))
2919 return;
2920
e30d1756
MI		 2921 vha = pci_get_drvdata(pdev);
2922 ha = vha->hw;
2923
42479343
AB		 2924 /* Notify ISPFX00 firmware */
2925 if (IS_QLAFX00(ha))
2926 qlafx00_driver_shutdown(vha, 20);
2927
e30d1756
MI		 2928 /* Turn-off FCE trace */
2929 if (ha->flags.fce_enabled) {
2930 qla2x00_disable_fce_trace(vha, NULL, NULL);
2931 ha->flags.fce_enabled = 0;
2932 }
2933
2934 /* Turn-off EFT trace */
2935 if (ha->eft)
2936 qla2x00_disable_eft_trace(vha);
2937
2938 /* Stop currently executing firmware. */
2939 qla2x00_try_to_stop_firmware(vha);
2940
2941 /* Turn adapter off line */
2942 vha->flags.online = 0;
2943
2944 /* turn-off interrupts on the card */
2945 if (ha->interrupts_on) {
2946 vha->flags.init_done = 0;
2947 ha->isp_ops->disable_intrs(ha);
2948 }
2949
2950 qla2x00_free_irqs(vha);
2951
2952 qla2x00_free_fw_dump(ha);
2953}
2954
fe1b806f 2955/* Deletes all the virtual ports for a given ha */
4c993f76 2956static void
fe1b806f 2957qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 2958{
fe1b806f
CD		 2959 struct Scsi_Host *scsi_host;
2960 scsi_qla_host_t *vha;
feafb7b1 2961 unsigned long flags;
e315cd28 2962
43ebf16d
AE		 2963 mutex_lock(&ha->vport_lock);
2964 while (ha->cur_vport_count) {
43ebf16d 2965 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2966
43ebf16d
AE		 2967 BUG_ON(base_vha->list.next == &ha->vp_list);
2968 /* This assumes first entry in ha->vp_list is always base vha */
2969 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
fe1b806f 2970 scsi_host = scsi_host_get(vha->host);
feafb7b1 2971
43ebf16d
AE		 2972 spin_unlock_irqrestore(&ha->vport_slock, flags);
2973 mutex_unlock(&ha->vport_lock);
2974
2975 fc_vport_terminate(vha->fc_vport);
2976 scsi_host_put(vha->host);
feafb7b1 2977
43ebf16d 2978 mutex_lock(&ha->vport_lock);
e315cd28 2979 }
43ebf16d 2980 mutex_unlock(&ha->vport_lock);
fe1b806f 2981}
1da177e4 2982
fe1b806f
CD		 2983/* Stops all deferred work threads */
2984static void
2985qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
2986{
68ca949c
AC		 2987 /* Flush the work queue and remove it */
2988 if (ha->wq) {
2989 flush_workqueue(ha->wq);
2990 destroy_workqueue(ha->wq);
2991 ha->wq = NULL;
2992 }
2993
7d613ac6
SV		 2994 /* Cancel all work and destroy DPC workqueues */
2995 if (ha->dpc_lp_wq) {
2996 cancel_work_sync(&ha->idc_aen);
2997 destroy_workqueue(ha->dpc_lp_wq);
2998 ha->dpc_lp_wq = NULL;
2999 }
3000
3001 if (ha->dpc_hp_wq) {
3002 cancel_work_sync(&ha->nic_core_reset);
3003 cancel_work_sync(&ha->idc_state_handler);
3004 cancel_work_sync(&ha->nic_core_unrecoverable);
3005 destroy_workqueue(ha->dpc_hp_wq);
3006 ha->dpc_hp_wq = NULL;
3007 }
3008
b9978769
AV		 3009 /* Kill the kernel thread for this host */
3010 if (ha->dpc_thread) {
3011 struct task_struct *t = ha->dpc_thread;
3012
3013 /*
3014 * qla2xxx_wake_dpc checks for ->dpc_thread
3015 * so we need to zero it out.
3016 */
3017 ha->dpc_thread = NULL;
3018 kthread_stop(t);
3019 }
fe1b806f 3020}
1da177e4 3021
fe1b806f
CD		 3022static void
3023qla2x00_unmap_iobases(struct qla_hw_data *ha)
3024{
a9083016 3025 if (IS_QLA82XX(ha)) {
b963752f 3026
a9083016
GM		 3027 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3028 if (!ql2xdbwr)
3029 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3030 } else {
3031 if (ha->iobase)
3032 iounmap(ha->iobase);
1da177e4 3033
8ae6d9c7
GM		 3034 if (ha->cregbase)
3035 iounmap(ha->cregbase);
3036
a9083016
GM		 3037 if (ha->mqiobase)
3038 iounmap(ha->mqiobase);
6246b8a1
GM		 3039
3040 if (IS_QLA83XX(ha) && ha->msixbase)
3041 iounmap(ha->msixbase);
a9083016 3042 }
fe1b806f
CD		 3043}
3044
3045static void
3046qla2x00_clear_drv_active(scsi_qla_host_t *vha)
3047{
3048 struct qla_hw_data *ha = vha->hw;
3049
3050 if (IS_QLA8044(ha)) {
3051 qla8044_idc_lock(ha);
3052 qla8044_clear_drv_active(vha);
3053 qla8044_idc_unlock(ha);
3054 } else if (IS_QLA82XX(ha)) {
3055 qla82xx_idc_lock(ha);
3056 qla82xx_clear_drv_active(ha);
3057 qla82xx_idc_unlock(ha);
3058 }
3059}
3060
3061static void
3062qla2x00_remove_one(struct pci_dev *pdev)
3063{
3064 scsi_qla_host_t *base_vha;
3065 struct qla_hw_data *ha;
3066
3067 /*
3068 * If the PCI device is disabled that means that probe failed and any
3069 * resources should be have cleaned up on probe exit.
3070 */
3071 if (!atomic_read(&pdev->enable_cnt))
3072 return;
3073
3074 base_vha = pci_get_drvdata(pdev);
3075 ha = base_vha->hw;
3076
3077 set_bit(UNLOADING, &base_vha->dpc_flags);
3078
3079 if (IS_QLAFX00(ha))
3080 qlafx00_driver_shutdown(base_vha, 20);
3081
3082 qla2x00_delete_all_vps(ha, base_vha);
3083
3084 if (IS_QLA8031(ha)) {
3085 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3086 "Clearing fcoe driver presence.\n");
3087 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3088 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3089 "Error while clearing DRV-Presence.\n");
3090 }
3091
3092 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3093
3094 qla2x00_dfs_remove(base_vha);
3095
3096 qla84xx_put_chip(base_vha);
3097
3098 /* Disable timer */
3099 if (base_vha->timer_active)
3100 qla2x00_stop_timer(base_vha);
3101
3102 base_vha->flags.online = 0;
3103
3104 qla2x00_destroy_deferred_work(ha);
3105
3106 qlt_remove_target(ha, base_vha);
3107
3108 qla2x00_free_sysfs_attr(base_vha, true);
3109
3110 fc_remove_host(base_vha->host);
3111
3112 scsi_remove_host(base_vha->host);
3113
3114 qla2x00_free_device(base_vha);
3115
3116 scsi_host_put(base_vha->host);
3117
3118 qla2x00_clear_drv_active(base_vha);
3119
3120 qla2x00_unmap_iobases(ha);
73208dfd 3121
e315cd28
AC		 3122 pci_release_selected_regions(ha->pdev, ha->bars);
3123 kfree(ha);
3124 ha = NULL;
1da177e4 3125
90a86fc0
JC		 3126 pci_disable_pcie_error_reporting(pdev);
3127
665db93b 3128 pci_disable_device(pdev);
1da177e4 3129}
1da177e4
LT		 3130
3131static void
e315cd28 3132qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3133{
e315cd28 3134 struct qla_hw_data *ha = vha->hw;
1da177e4 3135
85880801
AV		 3136 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3137
3138 /* Disable timer */
3139 if (vha->timer_active)
3140 qla2x00_stop_timer(vha);
3141
2afa19a9 3142 qla25xx_delete_queues(vha);
fe1b806f 3143
df613b96 3144 if (ha->flags.fce_enabled)
e315cd28 3145 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3146
a7a167bf 3147 if (ha->eft)
e315cd28 3148 qla2x00_disable_eft_trace(vha);
a7a167bf 3149
f6ef3b18 3150 /* Stop currently executing firmware. */
e315cd28 3151 qla2x00_try_to_stop_firmware(vha);
1da177e4 3152
85880801
AV		 3153 vha->flags.online = 0;
3154
f6ef3b18 3155 /* turn-off interrupts on the card */
a9083016
GM		 3156 if (ha->interrupts_on) {
3157 vha->flags.init_done = 0;
fd34f556 3158 ha->isp_ops->disable_intrs(ha);
a9083016 3159 }
f6ef3b18 3160
e315cd28 3161 qla2x00_free_irqs(vha);
1da177e4 3162
8867048b
CD		 3163 qla2x00_free_fcports(vha);
3164
e315cd28 3165 qla2x00_mem_free(ha);
73208dfd 3166
08de2844
GM		 3167 qla82xx_md_free(vha);
3168
73208dfd 3169 qla2x00_free_queues(ha);
1da177e4
LT		 3170}
3171
8867048b
CD		 3172void qla2x00_free_fcports(struct scsi_qla_host *vha)
3173{
3174 fc_port_t *fcport, *tfcport;
3175
3176 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3177 list_del(&fcport->list);
5f16b331 3178 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3179 kfree(fcport);
3180 fcport = NULL;
3181 }
3182}
3183
d97994dc 3184static inline void
e315cd28 3185qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3186 int defer)
3187{
d97994dc 3188 struct fc_rport *rport;
67becc00 3189 scsi_qla_host_t *base_vha;
044d78e1 3190 unsigned long flags;
d97994dc
AV		 3191
3192 if (!fcport->rport)
3193 return;
3194
3195 rport = fcport->rport;
3196 if (defer) {
67becc00 3197 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3198 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3199 fcport->drport = rport;
044d78e1 3200 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3201 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3202 qla2xxx_wake_dpc(base_vha);
2d70c103 3203 } else {
d97994dc 3204 fc_remote_port_delete(rport);
2d70c103
NB		 3205 qlt_fc_port_deleted(vha, fcport);
3206 }
d97994dc
AV		 3207}
3208
1da177e4
LT		 3209/*
3210 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3211 *
3212 * Input: ha = adapter block pointer. fcport = port structure pointer.
3213 *
3214 * Return: None.
3215 *
3216 * Context:
3217 */
e315cd28 3218void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3219 int do_login, int defer)
1da177e4 3220{
8ae6d9c7
GM		 3221 if (IS_QLAFX00(vha->hw)) {
3222 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3223 qla2x00_schedule_rport_del(vha, fcport, defer);
3224 return;
3225 }
3226
2c3dfe3f 3227 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3228 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3229 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3230 qla2x00_schedule_rport_del(vha, fcport, defer);
3231 }
fa2a1ce5 3232 /*
1da177e4
LT		 3233 * We may need to retry the login, so don't change the state of the
3234 * port but do the retries.
3235 */
3236 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3237 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3238
3239 if (!do_login)
3240 return;
3241
3242 if (fcport->login_retry == 0) {
e315cd28
AC		 3243 fcport->login_retry = vha->hw->login_retry_count;
3244 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3245
7c3df132 3246 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3247 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3248 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3249 }
3250}
3251
3252/*
3253 * qla2x00_mark_all_devices_lost
3254 * Updates fcport state when device goes offline.
3255 *
3256 * Input:
3257 * ha = adapter block pointer.
3258 * fcport = port structure pointer.
3259 *
3260 * Return:
3261 * None.
3262 *
3263 * Context:
3264 */
3265void
e315cd28 3266qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3267{
3268 fc_port_t *fcport;
3269
e315cd28 3270 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3271 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3272 continue;
0d6e61bc 3273
1da177e4
LT		 3274 /*
3275 * No point in marking the device as lost, if the device is
3276 * already DEAD.
3277 */
3278 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3279 continue;
e315cd28 3280 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3281 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3282 if (defer)
3283 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3284 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3285 qla2x00_schedule_rport_del(vha, fcport, defer);
3286 }
1da177e4
LT		 3287 }
3288}
3289
3290/*
3291* qla2x00_mem_alloc
3292* Allocates adapter memory.
3293*
3294* Returns:
3295* 0 = success.
e8711085 3296* !0 = failure.
1da177e4 3297*/
e8711085 3298static int
73208dfd
AC		 3299qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3300 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3301{
3302 char name[16];
1da177e4 3303
e8711085 3304 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3305 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3306 if (!ha->init_cb)
e315cd28 3307 goto fail;
e8711085 3308
2d70c103
NB		 3309 if (qlt_mem_alloc(ha) < 0)
3310 goto fail_free_init_cb;
3311
642ef983
CD		 3312 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3313 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3314 if (!ha->gid_list)
2d70c103 3315 goto fail_free_tgt_mem;
1da177e4 3316
e8711085
AV		 3317 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3318 if (!ha->srb_mempool)
e315cd28 3319 goto fail_free_gid_list;
e8711085 3320
7ec0effd 3321 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3322 /* Allocate cache for CT6 Ctx. */
3323 if (!ctx_cachep) {
3324 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3325 sizeof(struct ct6_dsd), 0,
3326 SLAB_HWCACHE_ALIGN, NULL);
3327 if (!ctx_cachep)
3328 goto fail_free_gid_list;
3329 }
3330 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3331 ctx_cachep);
3332 if (!ha->ctx_mempool)
3333 goto fail_free_srb_mempool;
7c3df132
SK		 3334 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3335 "ctx_cachep=%p ctx_mempool=%p.\n",
3336 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3337 }
3338
e8711085
AV		 3339 /* Get memory for cached NVRAM */
3340 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3341 if (!ha->nvram)
a9083016 3342 goto fail_free_ctx_mempool;
e8711085 3343
e315cd28
AC		 3344 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3345 ha->pdev->device);
3346 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3347 DMA_POOL_SIZE, 8, 0);
3348 if (!ha->s_dma_pool)
3349 goto fail_free_nvram;
3350
7c3df132
SK		 3351 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3352 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3353 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3354
7ec0effd 3355 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3356 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3357 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3358 if (!ha->dl_dma_pool) {
7c3df132
SK		 3359 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3360 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3361 goto fail_s_dma_pool;
3362 }
3363
3364 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3365 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3366 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3367 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3368 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3369 goto fail_dl_dma_pool;
3370 }
7c3df132
SK		 3371 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3372 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3373 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3374 }
3375
e8711085
AV		 3376 /* Allocate memory for SNS commands */
3377 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3378 /* Get consistent memory allocated for SNS commands */
e8711085 3379 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3380 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3381 if (!ha->sns_cmd)
e315cd28 3382 goto fail_dma_pool;
7c3df132 3383 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3384 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3385 } else {
e315cd28 3386 /* Get consistent memory allocated for MS IOCB */
e8711085 3387 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3388 &ha->ms_iocb_dma);
e8711085 3389 if (!ha->ms_iocb)
e315cd28
AC		 3390 goto fail_dma_pool;
3391 /* Get consistent memory allocated for CT SNS commands */
e8711085 3392 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3393 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3394 if (!ha->ct_sns)
3395 goto fail_free_ms_iocb;
7c3df132
SK		 3396 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3397 "ms_iocb=%p ct_sns=%p.\n",
3398 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3399 }
3400
e315cd28 3401 /* Allocate memory for request ring */
73208dfd
AC		 3402 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3403 if (!*req) {
7c3df132
SK		 3404 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3405 "Failed to allocate memory for req.\n");
e315cd28
AC		 3406 goto fail_req;
3407 }
73208dfd
AC		 3408 (*req)->length = req_len;
3409 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3410 ((*req)->length + 1) * sizeof(request_t),
3411 &(*req)->dma, GFP_KERNEL);
3412 if (!(*req)->ring) {
7c3df132
SK		 3413 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3414 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3415 goto fail_req_ring;
3416 }
3417 /* Allocate memory for response ring */
73208dfd
AC		 3418 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3419 if (!*rsp) {
7c3df132
SK		 3420 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3421 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3422 goto fail_rsp;
3423 }
73208dfd
AC		 3424 (*rsp)->hw = ha;
3425 (*rsp)->length = rsp_len;
3426 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3427 ((*rsp)->length + 1) * sizeof(response_t),
3428 &(*rsp)->dma, GFP_KERNEL);
3429 if (!(*rsp)->ring) {
7c3df132
SK		 3430 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3431 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3432 goto fail_rsp_ring;
3433 }
73208dfd
AC		 3434 (*req)->rsp = *rsp;
3435 (*rsp)->req = *req;
7c3df132
SK		 3436 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3437 "req=%p req->length=%d req->ring=%p rsp=%p "
3438 "rsp->length=%d rsp->ring=%p.\n",
3439 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3440 (*rsp)->ring);
73208dfd
AC		 3441 /* Allocate memory for NVRAM data for vports */
3442 if (ha->nvram_npiv_size) {
3443 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3444 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3445 if (!ha->npiv_info) {
7c3df132
SK		 3446 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3447 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3448 goto fail_npiv_info;
3449 }
3450 } else
3451 ha->npiv_info = NULL;
e8711085 3452
b64b0e8f 3453 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3454 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3455 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3456 &ha->ex_init_cb_dma);
3457 if (!ha->ex_init_cb)
3458 goto fail_ex_init_cb;
7c3df132
SK		 3459 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3460 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3461 }
3462
a9083016
GM		 3463 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3464
5ff1d584
AV		 3465 /* Get consistent memory allocated for Async Port-Database. */
3466 if (!IS_FWI2_CAPABLE(ha)) {
3467 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3468 &ha->async_pd_dma);
3469 if (!ha->async_pd)
3470 goto fail_async_pd;
7c3df132
SK		 3471 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3472 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3473 }
3474
e315cd28 3475 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3476
3477 /* Allocate memory for our loop_id bitmap */
3478 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3479 GFP_KERNEL);
3480 if (!ha->loop_id_map)
3481 goto fail_async_pd;
3482 else {
3483 qla2x00_set_reserved_loop_ids(ha);
3484 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3485 "loop_id_map=%p. \n", ha->loop_id_map);
3486 }
3487
e315cd28
AC		 3488 return 1;
3489
5ff1d584
AV		 3490fail_async_pd:
3491 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3492fail_ex_init_cb:
3493 kfree(ha->npiv_info);
73208dfd
AC		 3494fail_npiv_info:
3495 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3496 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3497 (*rsp)->ring = NULL;
3498 (*rsp)->dma = 0;
e315cd28 3499fail_rsp_ring:
73208dfd 3500 kfree(*rsp);
e315cd28 3501fail_rsp:
73208dfd
AC		 3502 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3503 sizeof(request_t), (*req)->ring, (*req)->dma);
3504 (*req)->ring = NULL;
3505 (*req)->dma = 0;
e315cd28 3506fail_req_ring:
73208dfd 3507 kfree(*req);
e315cd28
AC		 3508fail_req:
3509 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3510 ha->ct_sns, ha->ct_sns_dma);
3511 ha->ct_sns = NULL;
3512 ha->ct_sns_dma = 0;
e8711085
AV		 3513fail_free_ms_iocb:
3514 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3515 ha->ms_iocb = NULL;
3516 ha->ms_iocb_dma = 0;
e315cd28 3517fail_dma_pool:
bad75002 3518 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3519 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3520 ha->fcp_cmnd_dma_pool = NULL;
3521 }
3522fail_dl_dma_pool:
bad75002 3523 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3524 dma_pool_destroy(ha->dl_dma_pool);
3525 ha->dl_dma_pool = NULL;
3526 }
3527fail_s_dma_pool:
e315cd28
AC		 3528 dma_pool_destroy(ha->s_dma_pool);
3529 ha->s_dma_pool = NULL;
e8711085
AV		 3530fail_free_nvram:
3531 kfree(ha->nvram);
3532 ha->nvram = NULL;
a9083016
GM		 3533fail_free_ctx_mempool:
3534 mempool_destroy(ha->ctx_mempool);
3535 ha->ctx_mempool = NULL;
e8711085
AV		 3536fail_free_srb_mempool:
3537 mempool_destroy(ha->srb_mempool);
3538 ha->srb_mempool = NULL;
e8711085 3539fail_free_gid_list:
642ef983
CD		 3540 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3541 ha->gid_list,
e315cd28 3542 ha->gid_list_dma);
e8711085
AV		 3543 ha->gid_list = NULL;
3544 ha->gid_list_dma = 0;
2d70c103
NB		 3545fail_free_tgt_mem:
3546 qlt_mem_free(ha);
e315cd28
AC		 3547fail_free_init_cb:
3548 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3549 ha->init_cb_dma);
3550 ha->init_cb = NULL;
3551 ha->init_cb_dma = 0;
e8711085 3552fail:
7c3df132
SK		 3553 ql_log(ql_log_fatal, NULL, 0x0030,
3554 "Memory allocation failure.\n");
e8711085 3555 return -ENOMEM;
1da177e4
LT		 3556}
3557
3558/*
e30d1756
MI		 3559* qla2x00_free_fw_dump
3560* Frees fw dump stuff.
1da177e4
LT		 3561*
3562* Input:
7ec0effd 3563* ha = adapter block pointer
1da177e4 3564*/
a824ebb3 3565static void
e30d1756 3566qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3567{
df613b96
AV		 3568 if (ha->fce)
3569 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3570 ha->fce_dma);
df613b96 3571
a7a167bf
AV		 3572 if (ha->fw_dump) {
3573 if (ha->eft)
3574 dma_free_coherent(&ha->pdev->dev,
e30d1756 3575 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3576 vfree(ha->fw_dump);
3577 }
e30d1756
MI		 3578 ha->fce = NULL;
3579 ha->fce_dma = 0;
3580 ha->eft = NULL;
3581 ha->eft_dma = 0;
3582 ha->fw_dump = NULL;
3583 ha->fw_dumped = 0;
3584 ha->fw_dump_reading = 0;
3585}
3586
3587/*
3588* qla2x00_mem_free
3589* Frees all adapter allocated memory.
3590*
3591* Input:
3592* ha = adapter block pointer.
3593*/
3594static void
3595qla2x00_mem_free(struct qla_hw_data *ha)
3596{
3597 qla2x00_free_fw_dump(ha);
3598
81178772
SK		 3599 if (ha->mctp_dump)
3600 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3601 ha->mctp_dump_dma);
3602
e30d1756
MI		 3603 if (ha->srb_mempool)
3604 mempool_destroy(ha->srb_mempool);
a7a167bf 3605
11bbc1d8
AV		 3606 if (ha->dcbx_tlv)
3607 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3608 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3609
ce0423f4
AV		 3610 if (ha->xgmac_data)
3611 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3612 ha->xgmac_data, ha->xgmac_data_dma);
3613
1da177e4
LT		 3614 if (ha->sns_cmd)
3615 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3616 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3617
3618 if (ha->ct_sns)
3619 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3620 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3621
88729e53
AV		 3622 if (ha->sfp_data)
3623 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3624
1da177e4
LT		 3625 if (ha->ms_iocb)
3626 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3627
b64b0e8f 3628 if (ha->ex_init_cb)
a9083016
GM		 3629 dma_pool_free(ha->s_dma_pool,
3630 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3631
5ff1d584
AV		 3632 if (ha->async_pd)
3633 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3634
1da177e4
LT		 3635 if (ha->s_dma_pool)
3636 dma_pool_destroy(ha->s_dma_pool);
3637
1da177e4 3638 if (ha->gid_list)
642ef983
CD		 3639 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3640 ha->gid_list, ha->gid_list_dma);
1da177e4 3641
a9083016
GM		 3642 if (IS_QLA82XX(ha)) {
3643 if (!list_empty(&ha->gbl_dsd_list)) {
3644 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3645
3646 /* clean up allocated prev pool */
3647 list_for_each_entry_safe(dsd_ptr,
3648 tdsd_ptr, &ha->gbl_dsd_list, list) {
3649 dma_pool_free(ha->dl_dma_pool,
3650 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3651 list_del(&dsd_ptr->list);
3652 kfree(dsd_ptr);
3653 }
3654 }
3655 }
3656
3657 if (ha->dl_dma_pool)
3658 dma_pool_destroy(ha->dl_dma_pool);
3659
3660 if (ha->fcp_cmnd_dma_pool)
3661 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3662
3663 if (ha->ctx_mempool)
3664 mempool_destroy(ha->ctx_mempool);
3665
2d70c103
NB		 3666 qlt_mem_free(ha);
3667
e315cd28
AC		 3668 if (ha->init_cb)
3669 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3670 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3671 vfree(ha->optrom_buffer);
3672 kfree(ha->nvram);
73208dfd 3673 kfree(ha->npiv_info);
7a67735b 3674 kfree(ha->swl);
5f16b331 3675 kfree(ha->loop_id_map);
1da177e4 3676
e8711085 3677 ha->srb_mempool = NULL;
a9083016 3678 ha->ctx_mempool = NULL;
1da177e4
LT		 3679 ha->sns_cmd = NULL;
3680 ha->sns_cmd_dma = 0;
3681 ha->ct_sns = NULL;
3682 ha->ct_sns_dma = 0;
3683 ha->ms_iocb = NULL;
3684 ha->ms_iocb_dma = 0;
1da177e4
LT		 3685 ha->init_cb = NULL;
3686 ha->init_cb_dma = 0;
b64b0e8f
AV		 3687 ha->ex_init_cb = NULL;
3688 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3689 ha->async_pd = NULL;
3690 ha->async_pd_dma = 0;
1da177e4
LT		 3691
3692 ha->s_dma_pool = NULL;
a9083016
GM		 3693 ha->dl_dma_pool = NULL;
3694 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3695
1da177e4
LT		 3696 ha->gid_list = NULL;
3697 ha->gid_list_dma = 0;
2d70c103
NB		 3698
3699 ha->tgt.atio_ring = NULL;
3700 ha->tgt.atio_dma = 0;
3701 ha->tgt.tgt_vp_map = NULL;
e315cd28 3702}
1da177e4 3703
e315cd28
AC		 3704struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3705 struct qla_hw_data *ha)
3706{
3707 struct Scsi_Host *host;
3708 struct scsi_qla_host *vha = NULL;
854165f4 3709
e315cd28
AC		 3710 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3711 if (host == NULL) {
7c3df132
SK		 3712 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3713 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3714 goto fail;
3715 }
3716
3717 /* Clear our data area */
3718 vha = shost_priv(host);
3719 memset(vha, 0, sizeof(scsi_qla_host_t));
3720
3721 vha->host = host;
3722 vha->host_no = host->host_no;
3723 vha->hw = ha;
3724
3725 INIT_LIST_HEAD(&vha->vp_fcports);
3726 INIT_LIST_HEAD(&vha->work_list);
3727 INIT_LIST_HEAD(&vha->list);
3728
f999f4c1
AV		 3729 spin_lock_init(&vha->work_lock);
3730
e315cd28 3731 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3732 ql_dbg(ql_dbg_init, vha, 0x0041,
3733 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3734 vha->host, vha->hw, vha,
3735 dev_name(&(ha->pdev->dev)));
3736
e315cd28
AC		 3737 return vha;
3738
3739fail:
3740 return vha;
1da177e4
LT		 3741}
3742
01ef66bb 3743static struct qla_work_evt *
f999f4c1 3744qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3745{
3746 struct qla_work_evt *e;
feafb7b1
AE		 3747 uint8_t bail;
3748
3749 QLA_VHA_MARK_BUSY(vha, bail);
3750 if (bail)
3751 return NULL;
0971de7f 3752
f999f4c1 3753 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3754 if (!e) {
3755 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3756 return NULL;
feafb7b1 3757 }
0971de7f
AV		 3758
3759 INIT_LIST_HEAD(&e->list);
3760 e->type = type;
3761 e->flags = QLA_EVT_FLAG_FREE;
3762 return e;
3763}
3764
01ef66bb 3765static int
f999f4c1 3766qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3767{
f999f4c1 3768 unsigned long flags;
0971de7f 3769
f999f4c1 3770 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3771 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3772 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3773 qla2xxx_wake_dpc(vha);
f999f4c1 3774
0971de7f
AV		 3775 return QLA_SUCCESS;
3776}
3777
3778int
e315cd28 3779qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3780 u32 data)
3781{
3782 struct qla_work_evt *e;
3783
f999f4c1 3784 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3785 if (!e)
3786 return QLA_FUNCTION_FAILED;
3787
3788 e->u.aen.code = code;
3789 e->u.aen.data = data;
f999f4c1 3790 return qla2x00_post_work(vha, e);
0971de7f
AV		 3791}
3792
8a659571
AV		 3793int
3794qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3795{
3796 struct qla_work_evt *e;
3797
f999f4c1 3798 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3799 if (!e)
3800 return QLA_FUNCTION_FAILED;
3801
3802 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3803 return qla2x00_post_work(vha, e);
8a659571
AV		 3804}
3805
ac280b67
AV		 3806#define qla2x00_post_async_work(name, type) \
3807int qla2x00_post_async_##name##_work( \
3808 struct scsi_qla_host *vha, \
3809 fc_port_t *fcport, uint16_t *data) \
3810{ \
3811 struct qla_work_evt *e; \
3812 \
3813 e = qla2x00_alloc_work(vha, type); \
3814 if (!e) \
3815 return QLA_FUNCTION_FAILED; \
3816 \
3817 e->u.logio.fcport = fcport; \
3818 if (data) { \
3819 e->u.logio.data[0] = data[0]; \
3820 e->u.logio.data[1] = data[1]; \
3821 } \
3822 return qla2x00_post_work(vha, e); \
3823}
3824
3825qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3826qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3827qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3828qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3829qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3830qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3831
3420d36c
AV		 3832int
3833qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3834{
3835 struct qla_work_evt *e;
3836
3837 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3838 if (!e)
3839 return QLA_FUNCTION_FAILED;
3840
3841 e->u.uevent.code = code;
3842 return qla2x00_post_work(vha, e);
3843}
3844
3845static void
3846qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3847{
3848 char event_string[40];
3849 char *envp[] = { event_string, NULL };
3850
3851 switch (code) {
3852 case QLA_UEVENT_CODE_FW_DUMP:
3853 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3854 vha->host_no);
3855 break;
3856 default:
3857 /* do nothing */
3858 break;
3859 }
3860 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3861}
3862
8ae6d9c7
GM		 3863int
3864qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3865 uint32_t *data, int cnt)
3866{
3867 struct qla_work_evt *e;
3868
3869 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3870 if (!e)
3871 return QLA_FUNCTION_FAILED;
3872
3873 e->u.aenfx.evtcode = evtcode;
3874 e->u.aenfx.count = cnt;
3875 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3876 return qla2x00_post_work(vha, e);
3877}
3878
ac280b67 3879void
e315cd28 3880qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3881{
f999f4c1
AV		 3882 struct qla_work_evt *e, *tmp;
3883 unsigned long flags;
3884 LIST_HEAD(work);
0971de7f 3885
f999f4c1
AV		 3886 spin_lock_irqsave(&vha->work_lock, flags);
3887 list_splice_init(&vha->work_list, &work);
3888 spin_unlock_irqrestore(&vha->work_lock, flags);
3889
3890 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3891 list_del_init(&e->list);
0971de7f
AV		 3892
3893 switch (e->type) {
3894 case QLA_EVT_AEN:
e315cd28 3895 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3896 e->u.aen.code, e->u.aen.data);
3897 break;
8a659571
AV		 3898 case QLA_EVT_IDC_ACK:
3899 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3900 break;
ac280b67
AV		 3901 case QLA_EVT_ASYNC_LOGIN:
3902 qla2x00_async_login(vha, e->u.logio.fcport,
3903 e->u.logio.data);
3904 break;
3905 case QLA_EVT_ASYNC_LOGIN_DONE:
3906 qla2x00_async_login_done(vha, e->u.logio.fcport,
3907 e->u.logio.data);
3908 break;
3909 case QLA_EVT_ASYNC_LOGOUT:
3910 qla2x00_async_logout(vha, e->u.logio.fcport);
3911 break;
3912 case QLA_EVT_ASYNC_LOGOUT_DONE:
3913 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3914 e->u.logio.data);
3915 break;
5ff1d584
AV		 3916 case QLA_EVT_ASYNC_ADISC:
3917 qla2x00_async_adisc(vha, e->u.logio.fcport,
3918 e->u.logio.data);
3919 break;
3920 case QLA_EVT_ASYNC_ADISC_DONE:
3921 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3922 e->u.logio.data);
3923 break;
3420d36c
AV		 3924 case QLA_EVT_UEVENT:
3925 qla2x00_uevent_emit(vha, e->u.uevent.code);
3926 break;
8ae6d9c7
GM		 3927 case QLA_EVT_AENFX:
3928 qlafx00_process_aen(vha, e);
3929 break;
0971de7f
AV		 3930 }
3931 if (e->flags & QLA_EVT_FLAG_FREE)
3932 kfree(e);
feafb7b1
AE		 3933
3934 /* For each work completed decrement vha ref count */
3935 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3936 }
e315cd28 3937}
f999f4c1 3938
e315cd28
AC		 3939/* Relogins all the fcports of a vport
3940 * Context: dpc thread
3941 */
3942void qla2x00_relogin(struct scsi_qla_host *vha)
3943{
3944 fc_port_t *fcport;
c6b2fca8 3945 int status;
e315cd28
AC		 3946 uint16_t next_loopid = 0;
3947 struct qla_hw_data *ha = vha->hw;
ac280b67 3948 uint16_t data[2];
e315cd28
AC		 3949
3950 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3951 /*
3952 * If the port is not ONLINE then try to login
3953 * to it if we haven't run out of retries.
3954 */
5ff1d584
AV		 3955 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3956 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3957 fcport->login_retry--;
e315cd28 3958 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3959 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3960 ha->isp_ops->fabric_logout(vha,
3961 fcport->loop_id,
3962 fcport->d_id.b.domain,
3963 fcport->d_id.b.area,
3964 fcport->d_id.b.al_pa);
3965
03bcfb57
JC		 3966 if (fcport->loop_id == FC_NO_LOOP_ID) {
3967 fcport->loop_id = next_loopid =
3968 ha->min_external_loopid;
3969 status = qla2x00_find_new_loop_id(
3970 vha, fcport);
3971 if (status != QLA_SUCCESS) {
3972 /* Ran out of IDs to use */
3973 break;
3974 }
3975 }
3976
ac280b67 3977 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3978 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3979 data[0] = 0;
3980 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3981 status = qla2x00_post_async_login_work(
3982 vha, fcport, data);
3983 if (status == QLA_SUCCESS)
3984 continue;
3985 /* Attempt a retry. */
3986 status = 1;
aaf4d3e2 3987 } else {
ac280b67
AV		 3988 status = qla2x00_fabric_login(vha,
3989 fcport, &next_loopid);
aaf4d3e2
SK		 3990 if (status == QLA_SUCCESS) {
3991 int status2;
3992 uint8_t opts;
3993
3994 opts = 0;
3995 if (fcport->flags &
3996 FCF_FCP2_DEVICE)
3997 opts |= BIT_1;
03003960
SK		 3998 status2 =
3999 qla2x00_get_port_database(
4000 vha, fcport, opts);
aaf4d3e2
SK		 4001 if (status2 != QLA_SUCCESS)
4002 status = 1;
4003 }
4004 }
e315cd28
AC		 4005 } else
4006 status = qla2x00_local_device_login(vha,
4007 fcport);
4008
e315cd28
AC		 4009 if (status == QLA_SUCCESS) {
4010 fcport->old_loop_id = fcport->loop_id;
4011
7c3df132
SK		 4012 ql_dbg(ql_dbg_disc, vha, 0x2003,
4013 "Port login OK: logged in ID 0x%x.\n",
4014 fcport->loop_id);
e315cd28
AC		 4015
4016 qla2x00_update_fcport(vha, fcport);
4017
4018 } else if (status == 1) {
4019 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4020 /* retry the login again */
7c3df132
SK		 4021 ql_dbg(ql_dbg_disc, vha, 0x2007,
4022 "Retrying %d login again loop_id 0x%x.\n",
4023 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4024 } else {
4025 fcport->login_retry = 0;
4026 }
4027
4028 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4029 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4030 }
4031 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4032 break;
0971de7f 4033 }
0971de7f
AV		 4034}
4035
7d613ac6
SV		 4036/* Schedule work on any of the dpc-workqueues */
4037void
4038qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4039{
4040 struct qla_hw_data *ha = base_vha->hw;
4041
4042 switch (work_code) {
4043 case MBA_IDC_AEN: /* 0x8200 */
4044 if (ha->dpc_lp_wq)
4045 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4046 break;
4047
4048 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4049 if (!ha->flags.nic_core_reset_hdlr_active) {
4050 if (ha->dpc_hp_wq)
4051 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4052 } else
4053 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4054 "NIC Core reset is already active. Skip "
4055 "scheduling it again.\n");
4056 break;
4057 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4058 if (ha->dpc_hp_wq)
4059 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4060 break;
4061 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4062 if (ha->dpc_hp_wq)
4063 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4064 break;
4065 default:
4066 ql_log(ql_log_warn, base_vha, 0xb05f,
4067 "Unknow work-code=0x%x.\n", work_code);
4068 }
4069
4070 return;
4071}
4072
4073/* Work: Perform NIC Core Unrecoverable state handling */
4074void
4075qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4076{
4077 struct qla_hw_data *ha =
2ad1b67c 4078 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4079 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4080 uint32_t dev_state = 0;
4081
4082 qla83xx_idc_lock(base_vha, 0);
4083 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4084 qla83xx_reset_ownership(base_vha);
4085 if (ha->flags.nic_core_reset_owner) {
4086 ha->flags.nic_core_reset_owner = 0;
4087 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4088 QLA8XXX_DEV_FAILED);
4089 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4090 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4091 }
4092 qla83xx_idc_unlock(base_vha, 0);
4093}
4094
4095/* Work: Execute IDC state handler */
4096void
4097qla83xx_idc_state_handler_work(struct work_struct *work)
4098{
4099 struct qla_hw_data *ha =
2ad1b67c 4100 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4101 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4102 uint32_t dev_state = 0;
4103
4104 qla83xx_idc_lock(base_vha, 0);
4105 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4106 if (dev_state == QLA8XXX_DEV_FAILED ||
4107 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4108 qla83xx_idc_state_handler(base_vha);
4109 qla83xx_idc_unlock(base_vha, 0);
4110}
4111
fa492630 4112static int
7d613ac6
SV		 4113qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4114{
4115 int rval = QLA_SUCCESS;
4116 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4117 uint32_t heart_beat_counter1, heart_beat_counter2;
4118
4119 do {
4120 if (time_after(jiffies, heart_beat_wait)) {
4121 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4122 "Nic Core f/w is not alive.\n");
4123 rval = QLA_FUNCTION_FAILED;
4124 break;
4125 }
4126
4127 qla83xx_idc_lock(base_vha, 0);
4128 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4129 &heart_beat_counter1);
4130 qla83xx_idc_unlock(base_vha, 0);
4131 msleep(100);
4132 qla83xx_idc_lock(base_vha, 0);
4133 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4134 &heart_beat_counter2);
4135 qla83xx_idc_unlock(base_vha, 0);
4136 } while (heart_beat_counter1 == heart_beat_counter2);
4137
4138 return rval;
4139}
4140
4141/* Work: Perform NIC Core Reset handling */
4142void
4143qla83xx_nic_core_reset_work(struct work_struct *work)
4144{
4145 struct qla_hw_data *ha =
4146 container_of(work, struct qla_hw_data, nic_core_reset);
4147 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4148 uint32_t dev_state = 0;
4149
81178772
SK		 4150 if (IS_QLA2031(ha)) {
4151 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4152 ql_log(ql_log_warn, base_vha, 0xb081,
4153 "Failed to dump mctp\n");
4154 return;
4155 }
4156
7d613ac6
SV		 4157 if (!ha->flags.nic_core_reset_hdlr_active) {
4158 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4159 qla83xx_idc_lock(base_vha, 0);
4160 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4161 &dev_state);
4162 qla83xx_idc_unlock(base_vha, 0);
4163 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4164 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4165 "Nic Core f/w is alive.\n");
4166 return;
4167 }
4168 }
4169
4170 ha->flags.nic_core_reset_hdlr_active = 1;
4171 if (qla83xx_nic_core_reset(base_vha)) {
4172 /* NIC Core reset failed. */
4173 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4174 "NIC Core reset failed.\n");
4175 }
4176 ha->flags.nic_core_reset_hdlr_active = 0;
4177 }
4178}
4179
4180/* Work: Handle 8200 IDC aens */
4181void
4182qla83xx_service_idc_aen(struct work_struct *work)
4183{
4184 struct qla_hw_data *ha =
4185 container_of(work, struct qla_hw_data, idc_aen);
4186 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4187 uint32_t dev_state, idc_control;
4188
4189 qla83xx_idc_lock(base_vha, 0);
4190 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4191 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4192 qla83xx_idc_unlock(base_vha, 0);
4193 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4194 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4195 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4196 "Application requested NIC Core Reset.\n");
4197 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4198 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4199 QLA_SUCCESS) {
4200 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4201 "Other protocol driver requested NIC Core Reset.\n");
4202 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4203 }
4204 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4205 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4206 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4207 }
4208}
4209
4210static void
4211qla83xx_wait_logic(void)
4212{
4213 int i;
4214
4215 /* Yield CPU */
4216 if (!in_interrupt()) {
4217 /*
4218 * Wait about 200ms before retrying again.
4219 * This controls the number of retries for single
4220 * lock operation.
4221 */
4222 msleep(100);
4223 schedule();
4224 } else {
4225 for (i = 0; i < 20; i++)
4226 cpu_relax(); /* This a nop instr on i386 */
4227 }
4228}
4229
fa492630 4230static int
7d613ac6
SV		 4231qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4232{
4233 int rval;
4234 uint32_t data;
4235 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4236 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4237 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4238 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4239 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4240
4241 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4242 if (rval)
4243 return rval;
4244
4245 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4246 return QLA_SUCCESS;
4247 } else {
4248 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4249 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4250 data);
4251 if (rval)
4252 return rval;
4253
4254 msleep(200);
4255
4256 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4257 &data);
4258 if (rval)
4259 return rval;
4260
4261 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4262 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4263 ~(idc_lck_rcvry_stage_mask));
4264 rval = qla83xx_wr_reg(base_vha,
4265 QLA83XX_IDC_LOCK_RECOVERY, data);
4266 if (rval)
4267 return rval;
4268
4269 /* Forcefully perform IDC UnLock */
4270 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4271 &data);
4272 if (rval)
4273 return rval;
4274 /* Clear lock-id by setting 0xff */
4275 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4276 0xff);
4277 if (rval)
4278 return rval;
4279 /* Clear lock-recovery by setting 0x0 */
4280 rval = qla83xx_wr_reg(base_vha,
4281 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4282 if (rval)
4283 return rval;
4284 } else
4285 return QLA_SUCCESS;
4286 }
4287
4288 return rval;
4289}
4290
fa492630 4291static int
7d613ac6
SV		 4292qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4293{
4294 int rval = QLA_SUCCESS;
4295 uint32_t o_drv_lockid, n_drv_lockid;
4296 unsigned long lock_recovery_timeout;
4297
4298 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4299retry_lockid:
4300 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4301 if (rval)
4302 goto exit;
4303
4304 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4305 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4306 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4307 return QLA_SUCCESS;
4308 else
4309 return QLA_FUNCTION_FAILED;
4310 }
4311
4312 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4313 if (rval)
4314 goto exit;
4315
4316 if (o_drv_lockid == n_drv_lockid) {
4317 qla83xx_wait_logic();
4318 goto retry_lockid;
4319 } else
4320 return QLA_SUCCESS;
4321
4322exit:
4323 return rval;
4324}
4325
4326void
4327qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4328{
4329 uint16_t options = (requester_id << 15) | BIT_6;
4330 uint32_t data;
6c315553 4331 uint32_t lock_owner;
7d613ac6
SV		 4332 struct qla_hw_data *ha = base_vha->hw;
4333
4334 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4335retry_lock:
4336 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4337 == QLA_SUCCESS) {
4338 if (data) {
4339 /* Setting lock-id to our function-number */
4340 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4341 ha->portnum);
4342 } else {
6c315553
SK		 4343 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4344 &lock_owner);
7d613ac6 4345 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4346 "Failed to acquire IDC lock, acquired by %d, "
4347 "retrying...\n", lock_owner);
7d613ac6
SV		 4348
4349 /* Retry/Perform IDC-Lock recovery */
4350 if (qla83xx_idc_lock_recovery(base_vha)
4351 == QLA_SUCCESS) {
4352 qla83xx_wait_logic();
4353 goto retry_lock;
4354 } else
4355 ql_log(ql_log_warn, base_vha, 0xb075,
4356 "IDC Lock recovery FAILED.\n");
4357 }
4358
4359 }
4360
4361 return;
4362
4363 /* XXX: IDC-lock implementation using access-control mbx */
4364retry_lock2:
4365 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4366 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4367 "Failed to acquire IDC lock. retrying...\n");
4368 /* Retry/Perform IDC-Lock recovery */
4369 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4370 qla83xx_wait_logic();
4371 goto retry_lock2;
4372 } else
4373 ql_log(ql_log_warn, base_vha, 0xb076,
4374 "IDC Lock recovery FAILED.\n");
4375 }
4376
4377 return;
4378}
4379
4380void
4381qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4382{
4383 uint16_t options = (requester_id << 15) | BIT_7, retry;
4384 uint32_t data;
4385 struct qla_hw_data *ha = base_vha->hw;
4386
4387 /* IDC-unlock implementation using driver-unlock/lock-id
4388 * remote registers
4389 */
4390 retry = 0;
4391retry_unlock:
4392 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4393 == QLA_SUCCESS) {
4394 if (data == ha->portnum) {
4395 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4396 /* Clearing lock-id by setting 0xff */
4397 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4398 } else if (retry < 10) {
4399 /* SV: XXX: IDC unlock retrying needed here? */
4400
4401 /* Retry for IDC-unlock */
4402 qla83xx_wait_logic();
4403 retry++;
4404 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4405 "Failed to release IDC lock, retyring=%d\n", retry);
4406 goto retry_unlock;
4407 }
4408 } else if (retry < 10) {
4409 /* Retry for IDC-unlock */
4410 qla83xx_wait_logic();
4411 retry++;
4412 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4413 "Failed to read drv-lockid, retyring=%d\n", retry);
4414 goto retry_unlock;
4415 }
4416
4417 return;
4418
4419 /* XXX: IDC-unlock implementation using access-control mbx */
4420 retry = 0;
4421retry_unlock2:
4422 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4423 if (retry < 10) {
4424 /* Retry for IDC-unlock */
4425 qla83xx_wait_logic();
4426 retry++;
4427 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4428 "Failed to release IDC lock, retyring=%d\n", retry);
4429 goto retry_unlock2;
4430 }
4431 }
4432
4433 return;
4434}
4435
4436int
4437__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4438{
4439 int rval = QLA_SUCCESS;
4440 struct qla_hw_data *ha = vha->hw;
4441 uint32_t drv_presence;
4442
4443 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4444 if (rval == QLA_SUCCESS) {
4445 drv_presence |= (1 << ha->portnum);
4446 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4447 drv_presence);
4448 }
4449
4450 return rval;
4451}
4452
4453int
4454qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4455{
4456 int rval = QLA_SUCCESS;
4457
4458 qla83xx_idc_lock(vha, 0);
4459 rval = __qla83xx_set_drv_presence(vha);
4460 qla83xx_idc_unlock(vha, 0);
4461
4462 return rval;
4463}
4464
4465int
4466__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4467{
4468 int rval = QLA_SUCCESS;
4469 struct qla_hw_data *ha = vha->hw;
4470 uint32_t drv_presence;
4471
4472 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4473 if (rval == QLA_SUCCESS) {
4474 drv_presence &= ~(1 << ha->portnum);
4475 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4476 drv_presence);
4477 }
4478
4479 return rval;
4480}
4481
4482int
4483qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4484{
4485 int rval = QLA_SUCCESS;
4486
4487 qla83xx_idc_lock(vha, 0);
4488 rval = __qla83xx_clear_drv_presence(vha);
4489 qla83xx_idc_unlock(vha, 0);
4490
4491 return rval;
4492}
4493
fa492630 4494static void
7d613ac6
SV		 4495qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4496{
4497 struct qla_hw_data *ha = vha->hw;
4498 uint32_t drv_ack, drv_presence;
4499 unsigned long ack_timeout;
4500
4501 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4502 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4503 while (1) {
4504 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4505 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4506 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4507 break;
4508
4509 if (time_after_eq(jiffies, ack_timeout)) {
4510 ql_log(ql_log_warn, vha, 0xb067,
4511 "RESET ACK TIMEOUT! drv_presence=0x%x "
4512 "drv_ack=0x%x\n", drv_presence, drv_ack);
4513 /*
4514 * The function(s) which did not ack in time are forced
4515 * to withdraw any further participation in the IDC
4516 * reset.
4517 */
4518 if (drv_ack != drv_presence)
4519 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4520 drv_ack);
4521 break;
4522 }
4523
4524 qla83xx_idc_unlock(vha, 0);
4525 msleep(1000);
4526 qla83xx_idc_lock(vha, 0);
4527 }
4528
4529 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4530 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4531}
4532
fa492630 4533static int
7d613ac6
SV		 4534qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4535{
4536 int rval = QLA_SUCCESS;
4537 uint32_t idc_control;
4538
4539 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4540 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4541
4542 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4543 __qla83xx_get_idc_control(vha, &idc_control);
4544 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4545 __qla83xx_set_idc_control(vha, 0);
4546
4547 qla83xx_idc_unlock(vha, 0);
4548 rval = qla83xx_restart_nic_firmware(vha);
4549 qla83xx_idc_lock(vha, 0);
4550
4551 if (rval != QLA_SUCCESS) {
4552 ql_log(ql_log_fatal, vha, 0xb06a,
4553 "Failed to restart NIC f/w.\n");
4554 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4555 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4556 } else {
4557 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4558 "Success in restarting nic f/w.\n");
4559 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4560 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4561 }
4562
4563 return rval;
4564}
4565
4566/* Assumes idc_lock always held on entry */
4567int
4568qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4569{
4570 struct qla_hw_data *ha = base_vha->hw;
4571 int rval = QLA_SUCCESS;
4572 unsigned long dev_init_timeout;
4573 uint32_t dev_state;
4574
4575 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4576 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4577
4578 while (1) {
4579
4580 if (time_after_eq(jiffies, dev_init_timeout)) {
4581 ql_log(ql_log_warn, base_vha, 0xb06e,
4582 "Initialization TIMEOUT!\n");
4583 /* Init timeout. Disable further NIC Core
4584 * communication.
4585 */
4586 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4587 QLA8XXX_DEV_FAILED);
4588 ql_log(ql_log_info, base_vha, 0xb06f,
4589 "HW State: FAILED.\n");
4590 }
4591
4592 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4593 switch (dev_state) {
4594 case QLA8XXX_DEV_READY:
4595 if (ha->flags.nic_core_reset_owner)
4596 qla83xx_idc_audit(base_vha,
4597 IDC_AUDIT_COMPLETION);
4598 ha->flags.nic_core_reset_owner = 0;
4599 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4600 "Reset_owner reset by 0x%x.\n",
4601 ha->portnum);
4602 goto exit;
4603 case QLA8XXX_DEV_COLD:
4604 if (ha->flags.nic_core_reset_owner)
4605 rval = qla83xx_device_bootstrap(base_vha);
4606 else {
4607 /* Wait for AEN to change device-state */
4608 qla83xx_idc_unlock(base_vha, 0);
4609 msleep(1000);
4610 qla83xx_idc_lock(base_vha, 0);
4611 }
4612 break;
4613 case QLA8XXX_DEV_INITIALIZING:
4614 /* Wait for AEN to change device-state */
4615 qla83xx_idc_unlock(base_vha, 0);
4616 msleep(1000);
4617 qla83xx_idc_lock(base_vha, 0);
4618 break;
4619 case QLA8XXX_DEV_NEED_RESET:
4620 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4621 qla83xx_need_reset_handler(base_vha);
4622 else {
4623 /* Wait for AEN to change device-state */
4624 qla83xx_idc_unlock(base_vha, 0);
4625 msleep(1000);
4626 qla83xx_idc_lock(base_vha, 0);
4627 }
4628 /* reset timeout value after need reset handler */
4629 dev_init_timeout = jiffies +
4630 (ha->fcoe_dev_init_timeout * HZ);
4631 break;
4632 case QLA8XXX_DEV_NEED_QUIESCENT:
4633 /* XXX: DEBUG for now */
4634 qla83xx_idc_unlock(base_vha, 0);
4635 msleep(1000);
4636 qla83xx_idc_lock(base_vha, 0);
4637 break;
4638 case QLA8XXX_DEV_QUIESCENT:
4639 /* XXX: DEBUG for now */
4640 if (ha->flags.quiesce_owner)
4641 goto exit;
4642
4643 qla83xx_idc_unlock(base_vha, 0);
4644 msleep(1000);
4645 qla83xx_idc_lock(base_vha, 0);
4646 dev_init_timeout = jiffies +
4647 (ha->fcoe_dev_init_timeout * HZ);
4648 break;
4649 case QLA8XXX_DEV_FAILED:
4650 if (ha->flags.nic_core_reset_owner)
4651 qla83xx_idc_audit(base_vha,
4652 IDC_AUDIT_COMPLETION);
4653 ha->flags.nic_core_reset_owner = 0;
4654 __qla83xx_clear_drv_presence(base_vha);
4655 qla83xx_idc_unlock(base_vha, 0);
4656 qla8xxx_dev_failed_handler(base_vha);
4657 rval = QLA_FUNCTION_FAILED;
4658 qla83xx_idc_lock(base_vha, 0);
4659 goto exit;
4660 case QLA8XXX_BAD_VALUE:
4661 qla83xx_idc_unlock(base_vha, 0);
4662 msleep(1000);
4663 qla83xx_idc_lock(base_vha, 0);
4664 break;
4665 default:
4666 ql_log(ql_log_warn, base_vha, 0xb071,
4667 "Unknow Device State: %x.\n", dev_state);
4668 qla83xx_idc_unlock(base_vha, 0);
4669 qla8xxx_dev_failed_handler(base_vha);
4670 rval = QLA_FUNCTION_FAILED;
4671 qla83xx_idc_lock(base_vha, 0);
4672 goto exit;
4673 }
4674 }
4675
4676exit:
4677 return rval;
4678}
4679
f3ddac19
CD		 4680void
4681qla2x00_disable_board_on_pci_error(struct work_struct *work)
4682{
4683 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4684 board_disable);
4685 struct pci_dev *pdev = ha->pdev;
4686 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4687
4688 ql_log(ql_log_warn, base_vha, 0x015b,
4689 "Disabling adapter.\n");
4690
4691 set_bit(UNLOADING, &base_vha->dpc_flags);
4692
4693 qla2x00_delete_all_vps(ha, base_vha);
4694
4695 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4696
4697 qla2x00_dfs_remove(base_vha);
4698
4699 qla84xx_put_chip(base_vha);
4700
4701 if (base_vha->timer_active)
4702 qla2x00_stop_timer(base_vha);
4703
4704 base_vha->flags.online = 0;
4705
4706 qla2x00_destroy_deferred_work(ha);
4707
4708 /*
4709 * Do not try to stop beacon blink as it will issue a mailbox
4710 * command.
4711 */
4712 qla2x00_free_sysfs_attr(base_vha, false);
4713
4714 fc_remove_host(base_vha->host);
4715
4716 scsi_remove_host(base_vha->host);
4717
4718 base_vha->flags.init_done = 0;
4719 qla25xx_delete_queues(base_vha);
4720 qla2x00_free_irqs(base_vha);
4721 qla2x00_free_fcports(base_vha);
4722 qla2x00_mem_free(ha);
4723 qla82xx_md_free(base_vha);
4724 qla2x00_free_queues(ha);
4725
4726 scsi_host_put(base_vha->host);
4727
4728 qla2x00_unmap_iobases(ha);
4729
4730 pci_release_selected_regions(ha->pdev, ha->bars);
4731 kfree(ha);
4732 ha = NULL;
4733
4734 pci_disable_pcie_error_reporting(pdev);
4735 pci_disable_device(pdev);
4736 pci_set_drvdata(pdev, NULL);
4737
4738}
4739
1da177e4
LT		 4740/**************************************************************************
4741* qla2x00_do_dpc
4742* This kernel thread is a task that is schedule by the interrupt handler
4743* to perform the background processing for interrupts.
4744*
4745* Notes:
4746* This task always run in the context of a kernel thread. It
4747* is kick-off by the driver's detect code and starts up
4748* up one per adapter. It immediately goes to sleep and waits for
4749* some fibre event. When either the interrupt handler or
4750* the timer routine detects a event it will one of the task
4751* bits then wake us up.
4752**************************************************************************/
4753static int
4754qla2x00_do_dpc(void *data)
4755{
2c3dfe3f 4756 int rval;
e315cd28
AC		 4757 scsi_qla_host_t *base_vha;
4758 struct qla_hw_data *ha;
1da177e4 4759
e315cd28
AC		 4760 ha = (struct qla_hw_data *)data;
4761 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4762
1da177e4
LT		 4763 set_user_nice(current, -20);
4764
563585ec 4765 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4766 while (!kthread_should_stop()) {
7c3df132
SK		 4767 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4768 "DPC handler sleeping.\n");
1da177e4 4769
39a11240
CH		 4770 schedule();
4771 __set_current_state(TASK_RUNNING);
1da177e4 4772
c142caf0
AV		 4773 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4774 goto end_loop;
1da177e4 4775
85880801 4776 if (ha->flags.eeh_busy) {
7c3df132
SK		 4777 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4778 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4779 goto end_loop;
85880801
AV		 4780 }
4781
1da177e4
LT		 4782 ha->dpc_active = 1;
4783
5f28d2d7
SK		 4784 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4785 "DPC handler waking up, dpc_flags=0x%lx.\n",
4786 base_vha->dpc_flags);
1da177e4 4787
e315cd28 4788 qla2x00_do_work(base_vha);
0971de7f 4789
7ec0effd
AD		 4790 if (IS_P3P_TYPE(ha)) {
4791 if (IS_QLA8044(ha)) {
4792 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4793 &base_vha->dpc_flags)) {
4794 qla8044_idc_lock(ha);
4795 qla8044_wr_direct(base_vha,
4796 QLA8044_CRB_DEV_STATE_INDEX,
4797 QLA8XXX_DEV_FAILED);
4798 qla8044_idc_unlock(ha);
4799 ql_log(ql_log_info, base_vha, 0x4004,
4800 "HW State: FAILED.\n");
4801 qla8044_device_state_handler(base_vha);
4802 continue;
4803 }
4804
4805 } else {
4806 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4807 &base_vha->dpc_flags)) {
4808 qla82xx_idc_lock(ha);
4809 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4810 QLA8XXX_DEV_FAILED);
4811 qla82xx_idc_unlock(ha);
4812 ql_log(ql_log_info, base_vha, 0x0151,
4813 "HW State: FAILED.\n");
4814 qla82xx_device_state_handler(base_vha);
4815 continue;
4816 }
a9083016
GM		 4817 }
4818
4819 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4820 &base_vha->dpc_flags)) {
4821
7c3df132
SK		 4822 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4823 "FCoE context reset scheduled.\n");
a9083016
GM		 4824 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4825 &base_vha->dpc_flags))) {
4826 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4827 /* FCoE-ctx reset failed.
4828 * Escalate to chip-reset
4829 */
4830 set_bit(ISP_ABORT_NEEDED,
4831 &base_vha->dpc_flags);
4832 }
4833 clear_bit(ABORT_ISP_ACTIVE,
4834 &base_vha->dpc_flags);
4835 }
4836
7c3df132
SK		 4837 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4838 "FCoE context reset end.\n");
a9083016 4839 }
8ae6d9c7
GM		 4840 } else if (IS_QLAFX00(ha)) {
4841 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4842 &base_vha->dpc_flags)) {
4843 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4844 "Firmware Reset Recovery\n");
4845 if (qlafx00_reset_initialize(base_vha)) {
4846 /* Failed. Abort isp later. */
4847 if (!test_bit(UNLOADING,
4848 &base_vha->dpc_flags))
4849 set_bit(ISP_UNRECOVERABLE,
4850 &base_vha->dpc_flags);
4851 ql_dbg(ql_dbg_dpc, base_vha,
4852 0x4021,
4853 "Reset Recovery Failed\n");
4854 }
4855 }
4856
4857 if (test_and_clear_bit(FX00_TARGET_SCAN,
4858 &base_vha->dpc_flags)) {
4859 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4860 "ISPFx00 Target Scan scheduled\n");
4861 if (qlafx00_rescan_isp(base_vha)) {
4862 if (!test_bit(UNLOADING,
4863 &base_vha->dpc_flags))
4864 set_bit(ISP_UNRECOVERABLE,
4865 &base_vha->dpc_flags);
4866 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4867 "ISPFx00 Target Scan Failed\n");
4868 }
4869 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4870 "ISPFx00 Target Scan End\n");
4871 }
e8f5e95d
AB		 4872 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
4873 &base_vha->dpc_flags)) {
4874 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
4875 "ISPFx00 Host Info resend scheduled\n");
4876 qlafx00_fx_disc(base_vha,
4877 &base_vha->hw->mr.fcport,
4878 FXDISC_REG_HOST_INFO);
4879 }
a9083016
GM		 4880 }
4881
e315cd28
AC		 4882 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4883 &base_vha->dpc_flags)) {
1da177e4 4884
7c3df132
SK		 4885 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4886 "ISP abort scheduled.\n");
1da177e4 4887 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4888 &base_vha->dpc_flags))) {
1da177e4 4889
a9083016 4890 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4891 /* failed. retry later */
4892 set_bit(ISP_ABORT_NEEDED,
e315cd28 4893 &base_vha->dpc_flags);
99363ef8 4894 }
e315cd28
AC		 4895 clear_bit(ABORT_ISP_ACTIVE,
4896 &base_vha->dpc_flags);
99363ef8
SJ		 4897 }
4898
7c3df132
SK		 4899 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4900 "ISP abort end.\n");
1da177e4
LT		 4901 }
4902
a394aac8
DJ		 4903 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4904 &base_vha->dpc_flags)) {
e315cd28 4905 qla2x00_update_fcports(base_vha);
c9c5ced9 4906 }
d97994dc 4907
2d70c103
NB		 4908 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4909 int ret;
4910 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4911 if (ret != QLA_SUCCESS)
4912 ql_log(ql_log_warn, base_vha, 0x121,
4913 "Failed to enable receiving of RSCN "
4914 "requests: 0x%x.\n", ret);
4915 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4916 }
4917
8ae6d9c7
GM		 4918 if (IS_QLAFX00(ha))
4919 goto loop_resync_check;
4920
579d12b5 4921 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4922 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4923 "Quiescence mode scheduled.\n");
7ec0effd
AD		 4924 if (IS_P3P_TYPE(ha)) {
4925 if (IS_QLA82XX(ha))
4926 qla82xx_device_state_handler(base_vha);
4927 if (IS_QLA8044(ha))
4928 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 4929 clear_bit(ISP_QUIESCE_NEEDED,
4930 &base_vha->dpc_flags);
4931 if (!ha->flags.quiesce_owner) {
4932 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 4933 if (IS_QLA82XX(ha)) {
4934 qla82xx_idc_lock(ha);
4935 qla82xx_clear_qsnt_ready(
4936 base_vha);
4937 qla82xx_idc_unlock(ha);
4938 } else if (IS_QLA8044(ha)) {
4939 qla8044_idc_lock(ha);
4940 qla8044_clear_qsnt_ready(
4941 base_vha);
4942 qla8044_idc_unlock(ha);
4943 }
8fcd6b8b
CD		 4944 }
4945 } else {
4946 clear_bit(ISP_QUIESCE_NEEDED,
4947 &base_vha->dpc_flags);
4948 qla2x00_quiesce_io(base_vha);
579d12b5 4949 }
7c3df132
SK		 4950 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4951 "Quiescence mode end.\n");
579d12b5
SK		 4952 }
4953
e315cd28 4954 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 4955 &base_vha->dpc_flags) &&
e315cd28 4956 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4957
7c3df132
SK		 4958 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4959 "Reset marker scheduled.\n");
e315cd28
AC		 4960 qla2x00_rst_aen(base_vha);
4961 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4962 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4963 "Reset marker end.\n");
1da177e4
LT		 4964 }
4965
4966 /* Retry each device up to login retry count */
e315cd28
AC		 4967 if ((test_and_clear_bit(RELOGIN_NEEDED,
4968 &base_vha->dpc_flags)) &&
4969 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4970 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4971
7c3df132
SK		 4972 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4973 "Relogin scheduled.\n");
e315cd28 4974 qla2x00_relogin(base_vha);
7c3df132
SK		 4975 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4976 "Relogin end.\n");
1da177e4 4977 }
8ae6d9c7 4978loop_resync_check:
e315cd28 4979 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 4980 &base_vha->dpc_flags)) {
1da177e4 4981
7c3df132
SK		 4982 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4983 "Loop resync scheduled.\n");
1da177e4
LT		 4984
4985 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4986 &base_vha->dpc_flags))) {
1da177e4 4987
e315cd28 4988 rval = qla2x00_loop_resync(base_vha);
1da177e4 4989
e315cd28
AC		 4990 clear_bit(LOOP_RESYNC_ACTIVE,
4991 &base_vha->dpc_flags);
1da177e4
LT		 4992 }
4993
7c3df132
SK		 4994 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4995 "Loop resync end.\n");
1da177e4
LT		 4996 }
4997
8ae6d9c7
GM		 4998 if (IS_QLAFX00(ha))
4999 goto intr_on_check;
5000
e315cd28
AC		 5001 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5002 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5003 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5004 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5005 }
5006
8ae6d9c7 5007intr_on_check:
1da177e4 5008 if (!ha->interrupts_on)
fd34f556 5009 ha->isp_ops->enable_intrs(ha);
1da177e4 5010
e315cd28
AC		 5011 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5012 &base_vha->dpc_flags))
5013 ha->isp_ops->beacon_blink(base_vha);
f6df144c 5014
8ae6d9c7
GM		 5015 if (!IS_QLAFX00(ha))
5016 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5017
1da177e4 5018 ha->dpc_active = 0;
c142caf0 5019end_loop:
563585ec 5020 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5021 } /* End of while(1) */
563585ec 5022 __set_current_state(TASK_RUNNING);
1da177e4 5023
7c3df132
SK		 5024 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5025 "DPC handler exiting.\n");
1da177e4
LT		 5026
5027 /*
5028 * Make sure that nobody tries to wake us up again.
5029 */
1da177e4
LT		 5030 ha->dpc_active = 0;
5031
ac280b67
AV		 5032 /* Cleanup any residual CTX SRBs. */
5033 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5034
39a11240
CH		 5035 return 0;
5036}
5037
5038void
e315cd28 5039qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5040{
e315cd28 5041 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5042 struct task_struct *t = ha->dpc_thread;
5043
e315cd28 5044 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5045 wake_up_process(t);
1da177e4
LT		 5046}
5047
1da177e4
LT		 5048/*
5049* qla2x00_rst_aen
5050* Processes asynchronous reset.
5051*
5052* Input:
5053* ha = adapter block pointer.
5054*/
5055static void
e315cd28 5056qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5057{
e315cd28
AC		 5058 if (vha->flags.online && !vha->flags.reset_active &&
5059 !atomic_read(&vha->loop_down_timer) &&
5060 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5061 do {
e315cd28 5062 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5063
5064 /*
5065 * Issue marker command only when we are going to start
5066 * the I/O.
5067 */
e315cd28
AC		 5068 vha->marker_needed = 1;
5069 } while (!atomic_read(&vha->loop_down_timer) &&
5070 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5071 }
5072}
5073
1da177e4
LT		 5074/**************************************************************************
5075* qla2x00_timer
5076*
5077* Description:
5078* One second timer
5079*
5080* Context: Interrupt
5081***************************************************************************/
2c3dfe3f 5082void
e315cd28 5083qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5084{
1da177e4 5085 unsigned long cpu_flags = 0;
1da177e4
LT		 5086 int start_dpc = 0;
5087 int index;
5088 srb_t *sp;
85880801 5089 uint16_t w;
e315cd28 5090 struct qla_hw_data *ha = vha->hw;
73208dfd 5091 struct req_que *req;
85880801 5092
a5b36321 5093 if (ha->flags.eeh_busy) {
7c3df132
SK		 5094 ql_dbg(ql_dbg_timer, vha, 0x6000,
5095 "EEH = %d, restarting timer.\n",
5096 ha->flags.eeh_busy);
a5b36321
LC		 5097 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5098 return;
5099 }
5100
f3ddac19
CD		 5101 /*
5102 * Hardware read to raise pending EEH errors during mailbox waits. If
5103 * the read returns -1 then disable the board.
5104 */
5105 if (!pci_channel_offline(ha->pdev)) {
85880801 5106 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
f3ddac19
CD		 5107 if (w == 0xffff)
5108 /*
5109 * Schedule this on the default system workqueue so that
5110 * all the adapter workqueues and the DPC thread can be
5111 * shutdown cleanly.
5112 */
5113 schedule_work(&ha->board_disable);
5114 }
1da177e4 5115
cefcaba6 5116 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5117 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5118 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5119 start_dpc++;
7ec0effd
AD		 5120 if (IS_QLA82XX(ha))
5121 qla82xx_watchdog(vha);
5122 else if (IS_QLA8044(ha))
5123 qla8044_watchdog(vha);
579d12b5
SK		 5124 }
5125
8ae6d9c7
GM		 5126 if (!vha->vp_idx && IS_QLAFX00(ha))
5127 qlafx00_timer_routine(vha);
5128
1da177e4 5129 /* Loop down handler. */
e315cd28 5130 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5131 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5132 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5133 && vha->flags.online) {
1da177e4 5134
e315cd28
AC		 5135 if (atomic_read(&vha->loop_down_timer) ==
5136 vha->loop_down_abort_time) {
1da177e4 5137
7c3df132
SK		 5138 ql_log(ql_log_info, vha, 0x6008,
5139 "Loop down - aborting the queues before time expires.\n");
1da177e4 5140
e315cd28
AC		 5141 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5142 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5143
f08b7251
AV		 5144 /*
5145 * Schedule an ISP abort to return any FCP2-device
5146 * commands.
5147 */
2c3dfe3f 5148 /* NPIV - scan physical port only */
e315cd28 5149 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5150 spin_lock_irqsave(&ha->hardware_lock,
5151 cpu_flags);
73208dfd 5152 req = ha->req_q_map[0];
2c3dfe3f 5153 for (index = 1;
8d93f550 5154 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5155 index++) {
5156 fc_port_t *sfcp;
5157
e315cd28 5158 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5159 if (!sp)
5160 continue;
9ba56b95 5161 if (sp->type != SRB_SCSI_CMD)
cf53b069 5162 continue;
2c3dfe3f 5163 sfcp = sp->fcport;
f08b7251 5164 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5165 continue;
bdf79621 5166
8f7daead
GM		 5167 if (IS_QLA82XX(ha))
5168 set_bit(FCOE_CTX_RESET_NEEDED,
5169 &vha->dpc_flags);
5170 else
5171 set_bit(ISP_ABORT_NEEDED,
e315cd28 5172 &vha->dpc_flags);
2c3dfe3f
SJ		 5173 break;
5174 }
5175 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5176 cpu_flags);
1da177e4 5177 }
1da177e4
LT		 5178 start_dpc++;
5179 }
5180
5181 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5182 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5183 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5184 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5185 "Loop down - aborting ISP.\n");
5186
8f7daead
GM		 5187 if (IS_QLA82XX(ha))
5188 set_bit(FCOE_CTX_RESET_NEEDED,
5189 &vha->dpc_flags);
5190 else
5191 set_bit(ISP_ABORT_NEEDED,
5192 &vha->dpc_flags);
1da177e4
LT		 5193 }
5194 }
7c3df132
SK		 5195 ql_dbg(ql_dbg_timer, vha, 0x600a,
5196 "Loop down - seconds remaining %d.\n",
5197 atomic_read(&vha->loop_down_timer));
1da177e4 5198 }
cefcaba6
SK		 5199 /* Check if beacon LED needs to be blinked for physical host only */
5200 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5201 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5202 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5203 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5204 start_dpc++;
5205 }
f6df144c
AV		 5206 }
5207
550bf57d 5208 /* Process any deferred work. */
e315cd28 5209 if (!list_empty(&vha->work_list))
550bf57d
AV		 5210 start_dpc++;
5211
1da177e4 5212 /* Schedule the DPC routine if needed */
e315cd28
AC		 5213 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5214 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5215 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5216 start_dpc ||
e315cd28
AC		 5217 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5218 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5219 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5220 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5221 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5222 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5223 ql_dbg(ql_dbg_timer, vha, 0x600b,
5224 "isp_abort_needed=%d loop_resync_needed=%d "
5225 "fcport_update_needed=%d start_dpc=%d "
5226 "reset_marker_needed=%d",
5227 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5228 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5229 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5230 start_dpc,
5231 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5232 ql_dbg(ql_dbg_timer, vha, 0x600c,
5233 "beacon_blink_needed=%d isp_unrecoverable=%d "
5234 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5235 "relogin_needed=%d.\n",
7c3df132
SK		 5236 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5237 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5238 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5239 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5240 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5241 qla2xxx_wake_dpc(vha);
7c3df132 5242 }
1da177e4 5243
e315cd28 5244 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5245}
5246
5433383e
AV		 5247/* Firmware interface routines. */
5248
6246b8a1 5249#define FW_BLOBS 10
5433383e
AV		 5250#define FW_ISP21XX 0
5251#define FW_ISP22XX 1
5252#define FW_ISP2300 2
5253#define FW_ISP2322 3
48c02fde 5254#define FW_ISP24XX 4
c3a2f0df 5255#define FW_ISP25XX 5
3a03eb79 5256#define FW_ISP81XX 6
a9083016 5257#define FW_ISP82XX 7
6246b8a1
GM		 5258#define FW_ISP2031 8
5259#define FW_ISP8031 9
5433383e 5260
bb8ee499
AV		 5261#define FW_FILE_ISP21XX "ql2100_fw.bin"
5262#define FW_FILE_ISP22XX "ql2200_fw.bin"
5263#define FW_FILE_ISP2300 "ql2300_fw.bin"
5264#define FW_FILE_ISP2322 "ql2322_fw.bin"
5265#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5266#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5267#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5268#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5269#define FW_FILE_ISP2031 "ql2600_fw.bin"
5270#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 5271
e1e82b6f 5272static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5273
5274static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5275 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5276 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5277 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5278 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5279 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5280 { .name = FW_FILE_ISP25XX, },
3a03eb79 5281 { .name = FW_FILE_ISP81XX, },
a9083016 5282 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5283 { .name = FW_FILE_ISP2031, },
5284 { .name = FW_FILE_ISP8031, },
5433383e
AV		 5285};
5286
5287struct fw_blob *
e315cd28 5288qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5289{
e315cd28 5290 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5291 struct fw_blob *blob;
5292
5433383e
AV		 5293 if (IS_QLA2100(ha)) {
5294 blob = &qla_fw_blobs[FW_ISP21XX];
5295 } else if (IS_QLA2200(ha)) {
5296 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5297 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5298 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5299 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5300 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5301 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5302 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5303 } else if (IS_QLA25XX(ha)) {
5304 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5305 } else if (IS_QLA81XX(ha)) {
5306 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5307 } else if (IS_QLA82XX(ha)) {
5308 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5309 } else if (IS_QLA2031(ha)) {
5310 blob = &qla_fw_blobs[FW_ISP2031];
5311 } else if (IS_QLA8031(ha)) {
5312 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 5313 } else {
5314 return NULL;
5433383e
AV		 5315 }
5316
e1e82b6f 5317 mutex_lock(&qla_fw_lock);
5433383e
AV		 5318 if (blob->fw)
5319 goto out;
5320
5321 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5322 ql_log(ql_log_warn, vha, 0x0063,
5323 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5324 blob->fw = NULL;
5325 blob = NULL;
5326 goto out;
5327 }
5328
5329out:
e1e82b6f 5330 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5331 return blob;
5332}
5333
5334static void
5335qla2x00_release_firmware(void)
5336{
5337 int idx;
5338
e1e82b6f 5339 mutex_lock(&qla_fw_lock);
5433383e 5340 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5341 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5342 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5343}
5344
14e660e6
SJ		 5345static pci_ers_result_t
5346qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5347{
85880801
AV		 5348 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5349 struct qla_hw_data *ha = vha->hw;
5350
7c3df132
SK		 5351 ql_dbg(ql_dbg_aer, vha, 0x9000,
5352 "PCI error detected, state %x.\n", state);
b9b12f73 5353
14e660e6
SJ		 5354 switch (state) {
5355 case pci_channel_io_normal:
85880801 5356 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5357 return PCI_ERS_RESULT_CAN_RECOVER;
5358 case pci_channel_io_frozen:
85880801 5359 ha->flags.eeh_busy = 1;
a5b36321
LC		 5360 /* For ISP82XX complete any pending mailbox cmd */
5361 if (IS_QLA82XX(ha)) {
7190575f 5362 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5363 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5364 qla82xx_clear_pending_mbx(vha);
a5b36321 5365 }
90a86fc0 5366 qla2x00_free_irqs(vha);
14e660e6 5367 pci_disable_device(pdev);
bddd2d65
LC		 5368 /* Return back all IOs */
5369 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5370 return PCI_ERS_RESULT_NEED_RESET;
5371 case pci_channel_io_perm_failure:
85880801
AV		 5372 ha->flags.pci_channel_io_perm_failure = 1;
5373 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5374 return PCI_ERS_RESULT_DISCONNECT;
5375 }
5376 return PCI_ERS_RESULT_NEED_RESET;
5377}
5378
5379static pci_ers_result_t
5380qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5381{
5382 int risc_paused = 0;
5383 uint32_t stat;
5384 unsigned long flags;
e315cd28
AC		 5385 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5386 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5387 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5388 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5389
bcc5b6d3
SK		 5390 if (IS_QLA82XX(ha))
5391 return PCI_ERS_RESULT_RECOVERED;
5392
14e660e6
SJ		 5393 spin_lock_irqsave(&ha->hardware_lock, flags);
5394 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5395 stat = RD_REG_DWORD(&reg->hccr);
5396 if (stat & HCCR_RISC_PAUSE)
5397 risc_paused = 1;
5398 } else if (IS_QLA23XX(ha)) {
5399 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5400 if (stat & HSR_RISC_PAUSED)
5401 risc_paused = 1;
5402 } else if (IS_FWI2_CAPABLE(ha)) {
5403 stat = RD_REG_DWORD(&reg24->host_status);
5404 if (stat & HSRX_RISC_PAUSED)
5405 risc_paused = 1;
5406 }
5407 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5408
5409 if (risc_paused) {
7c3df132
SK		 5410 ql_log(ql_log_info, base_vha, 0x9003,
5411 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5412 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5413
5414 return PCI_ERS_RESULT_NEED_RESET;
5415 } else
5416 return PCI_ERS_RESULT_RECOVERED;
5417}
5418
fa492630
SK		 5419static uint32_t
5420qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5421{
5422 uint32_t rval = QLA_FUNCTION_FAILED;
5423 uint32_t drv_active = 0;
5424 struct qla_hw_data *ha = base_vha->hw;
5425 int fn;
5426 struct pci_dev *other_pdev = NULL;
5427
7c3df132
SK		 5428 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5429 "Entered %s.\n", __func__);
a5b36321
LC		 5430
5431 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5432
5433 if (base_vha->flags.online) {
5434 /* Abort all outstanding commands,
5435 * so as to be requeued later */
5436 qla2x00_abort_isp_cleanup(base_vha);
5437 }
5438
5439
5440 fn = PCI_FUNC(ha->pdev->devfn);
5441 while (fn > 0) {
5442 fn--;
7c3df132
SK		 5443 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5444 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5445 other_pdev =
5446 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5447 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5448 fn));
5449
5450 if (!other_pdev)
5451 continue;
5452 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5453 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5454 "Found PCI func available and enable at 0x%x.\n",
5455 fn);
a5b36321
LC		 5456 pci_dev_put(other_pdev);
5457 break;
5458 }
5459 pci_dev_put(other_pdev);
5460 }
5461
5462 if (!fn) {
5463 /* Reset owner */
7c3df132
SK		 5464 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5465 "This devfn is reset owner = 0x%x.\n",
5466 ha->pdev->devfn);
a5b36321
LC		 5467 qla82xx_idc_lock(ha);
5468
5469 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5470 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5471
5472 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5473 QLA82XX_IDC_VERSION);
5474
5475 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5476 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5477 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5478
5479 qla82xx_idc_unlock(ha);
5480 /* Reset if device is not already reset
5481 * drv_active would be 0 if a reset has already been done
5482 */
5483 if (drv_active)
5484 rval = qla82xx_start_firmware(base_vha);
5485 else
5486 rval = QLA_SUCCESS;
5487 qla82xx_idc_lock(ha);
5488
5489 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5490 ql_log(ql_log_info, base_vha, 0x900b,
5491 "HW State: FAILED.\n");
a5b36321
LC		 5492 qla82xx_clear_drv_active(ha);
5493 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5494 QLA8XXX_DEV_FAILED);
a5b36321 5495 } else {
7c3df132
SK		 5496 ql_log(ql_log_info, base_vha, 0x900c,
5497 "HW State: READY.\n");
a5b36321 5498 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5499 QLA8XXX_DEV_READY);
a5b36321 5500 qla82xx_idc_unlock(ha);
7190575f 5501 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5502 rval = qla82xx_restart_isp(base_vha);
5503 qla82xx_idc_lock(ha);
5504 /* Clear driver state register */
5505 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5506 qla82xx_set_drv_active(base_vha);
5507 }
5508 qla82xx_idc_unlock(ha);
5509 } else {
7c3df132
SK		 5510 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5511 "This devfn is not reset owner = 0x%x.\n",
5512 ha->pdev->devfn);
a5b36321 5513 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5514 QLA8XXX_DEV_READY)) {
7190575f 5515 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5516 rval = qla82xx_restart_isp(base_vha);
5517 qla82xx_idc_lock(ha);
5518 qla82xx_set_drv_active(base_vha);
5519 qla82xx_idc_unlock(ha);
5520 }
5521 }
5522 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5523
5524 return rval;
5525}
5526
14e660e6
SJ		 5527static pci_ers_result_t
5528qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5529{
5530 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5531 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5532 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5533 struct rsp_que *rsp;
5534 int rc, retries = 10;
09483916 5535
7c3df132
SK		 5536 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5537 "Slot Reset.\n");
85880801 5538
90a86fc0
JC		 5539 /* Workaround: qla2xxx driver which access hardware earlier
5540 * needs error state to be pci_channel_io_online.
5541 * Otherwise mailbox command timesout.
5542 */
5543 pdev->error_state = pci_channel_io_normal;
5544
5545 pci_restore_state(pdev);
5546
8c1496bd
RL		 5547 /* pci_restore_state() clears the saved_state flag of the device
5548 * save restored state which resets saved_state flag
5549 */
5550 pci_save_state(pdev);
5551
09483916
BH		 5552 if (ha->mem_only)
5553 rc = pci_enable_device_mem(pdev);
5554 else
5555 rc = pci_enable_device(pdev);
14e660e6 5556
09483916 5557 if (rc) {
7c3df132 5558 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5559 "Can't re-enable PCI device after reset.\n");
a5b36321 5560 goto exit_slot_reset;
14e660e6 5561 }
14e660e6 5562
90a86fc0
JC		 5563 rsp = ha->rsp_q_map[0];
5564 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5565 goto exit_slot_reset;
90a86fc0 5566
e315cd28 5567 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5568 goto exit_slot_reset;
5569
5570 if (IS_QLA82XX(ha)) {
5571 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5572 ret = PCI_ERS_RESULT_RECOVERED;
5573 goto exit_slot_reset;
5574 } else
5575 goto exit_slot_reset;
5576 }
14e660e6 5577
90a86fc0
JC		 5578 while (ha->flags.mbox_busy && retries--)
5579 msleep(1000);
85880801 5580
e315cd28 5581 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5582 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5583 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5584 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5585
90a86fc0 5586
a5b36321 5587exit_slot_reset:
7c3df132
SK		 5588 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5589 "slot_reset return %x.\n", ret);
85880801 5590
14e660e6
SJ		 5591 return ret;
5592}
5593
5594static void
5595qla2xxx_pci_resume(struct pci_dev *pdev)
5596{
e315cd28
AC		 5597 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5598 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5599 int ret;
5600
7c3df132
SK		 5601 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5602 "pci_resume.\n");
85880801 5603
e315cd28 5604 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5605 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5606 ql_log(ql_log_fatal, base_vha, 0x9002,
5607 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5608 }
85880801 5609
3e46f031
LC		 5610 pci_cleanup_aer_uncorrect_error_status(pdev);
5611
85880801 5612 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5613}
5614
a55b2d21 5615static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5616 .error_detected = qla2xxx_pci_error_detected,
5617 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5618 .slot_reset = qla2xxx_pci_slot_reset,
5619 .resume = qla2xxx_pci_resume,
5620};
5621
5433383e 5622static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5626 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5627 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5628 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5629 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5630 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5631 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5632 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5633 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5634 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5635 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5636 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5637 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5638 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5639 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5640 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5641 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5433383e
AV		 5642 { 0 },
5643};
5644MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5645
fca29703 5646static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5647 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5648 .driver = {
5649 .owner = THIS_MODULE,
5650 },
fca29703 5651 .id_table = qla2xxx_pci_tbl,
7ee61397 5652 .probe = qla2x00_probe_one,
4c993f76 5653 .remove = qla2x00_remove_one,
e30d1756 5654 .shutdown = qla2x00_shutdown,
14e660e6 5655 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5656};
5657
75ef9de1 5658static const struct file_operations apidev_fops = {
6a03b4cd 5659 .owner = THIS_MODULE,
6038f373 5660 .llseek = noop_llseek,
6a03b4cd
HZ		 5661};
5662
1da177e4
LT		 5663/**
5664 * qla2x00_module_init - Module initialization.
5665 **/
5666static int __init
5667qla2x00_module_init(void)
5668{
fca29703
AV		 5669 int ret = 0;
5670
1da177e4 5671 /* Allocate cache for SRBs. */
354d6b21 5672 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5673 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5674 if (srb_cachep == NULL) {
7c3df132
SK		 5675 ql_log(ql_log_fatal, NULL, 0x0001,
5676 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5677 return -ENOMEM;
5678 }
5679
2d70c103
NB		 5680 /* Initialize target kmem_cache and mem_pools */
5681 ret = qlt_init();
5682 if (ret < 0) {
5683 kmem_cache_destroy(srb_cachep);
5684 return ret;
5685 } else if (ret > 0) {
5686 /*
5687 * If initiator mode is explictly disabled by qlt_init(),
5688 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5689 * performing scsi_scan_target() during LOOP UP event.
5690 */
5691 qla2xxx_transport_functions.disable_target_scan = 1;
5692 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5693 }
5694
1da177e4
LT		 5695 /* Derive version string. */
5696 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5697 if (ql2xextended_error_logging)
0181944f
AV		 5698 strcat(qla2x00_version_str, "-debug");
5699
1c97a12a
AV		 5700 qla2xxx_transport_template =
5701 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5702 if (!qla2xxx_transport_template) {
5703 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5704 ql_log(ql_log_fatal, NULL, 0x0002,
5705 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5706 qlt_exit();
1da177e4 5707 return -ENODEV;
2c3dfe3f 5708 }
6a03b4cd
HZ		 5709
5710 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5711 if (apidev_major < 0) {
7c3df132
SK		 5712 ql_log(ql_log_fatal, NULL, 0x0003,
5713 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5714 }
5715
2c3dfe3f
SJ		 5716 qla2xxx_transport_vport_template =
5717 fc_attach_transport(&qla2xxx_transport_vport_functions);
5718 if (!qla2xxx_transport_vport_template) {
5719 kmem_cache_destroy(srb_cachep);
2d70c103 5720 qlt_exit();
2c3dfe3f 5721 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5722 ql_log(ql_log_fatal, NULL, 0x0004,
5723 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5724 return -ENODEV;
2c3dfe3f 5725 }
7c3df132
SK		 5726 ql_log(ql_log_info, NULL, 0x0005,
5727 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5728 qla2x00_version_str);
7ee61397 5729 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5730 if (ret) {
5731 kmem_cache_destroy(srb_cachep);
2d70c103 5732 qlt_exit();
fca29703 5733 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5734 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5735 ql_log(ql_log_fatal, NULL, 0x0006,
5736 "pci_register_driver failed...ret=%d Failing load!.\n",
5737 ret);
fca29703
AV		 5738 }
5739 return ret;
1da177e4
LT		 5740}
5741
5742/**
5743 * qla2x00_module_exit - Module cleanup.
5744 **/
5745static void __exit
5746qla2x00_module_exit(void)
5747{
6a03b4cd 5748 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5749 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5750 qla2x00_release_firmware();
354d6b21 5751 kmem_cache_destroy(srb_cachep);
2d70c103 5752 qlt_exit();
a9083016
GM		 5753 if (ctx_cachep)
5754 kmem_cache_destroy(ctx_cachep);
1da177e4 5755 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5756 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5757}
5758
5759module_init(qla2x00_module_init);
5760module_exit(qla2x00_module_exit);
5761
5762MODULE_AUTHOR("QLogic Corporation");
5763MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5764MODULE_LICENSE("GPL");
5765MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5766MODULE_FIRMWARE(FW_FILE_ISP21XX);
5767MODULE_FIRMWARE(FW_FILE_ISP22XX);
5768MODULE_FIRMWARE(FW_FILE_ISP2300);
5769MODULE_FIRMWARE(FW_FILE_ISP2322);
5770MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5771MODULE_FIRMWARE(FW_FILE_ISP25XX);
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