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scsi/qla2xxx: Convert to SPDX license identifiers
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
77adf3f0 1// SPDX-License-Identifier: GPL-2.0-only
1da177e4 2/*
fa90c54f 3 * QLogic Fibre Channel HBA Driver
bd21eaf9 4 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4
LT		 5 */
6#include "qla_def.h"
7
8#include <linux/moduleparam.h>
9#include <linux/vmalloc.h>
1da177e4 10#include <linux/delay.h>
39a11240 11#include <linux/kthread.h>
e1e82b6f 12#include <linux/mutex.h>
3420d36c 13#include <linux/kobject.h>
5a0e3ad6 14#include <linux/slab.h>
5601236b 15#include <linux/blk-mq-pci.h>
585def9b
QT		 16#include <linux/refcount.h>
17
1da177e4
LT		 18#include <scsi/scsi_tcq.h>
19#include <scsi/scsicam.h>
20#include <scsi/scsi_transport.h>
21#include <scsi/scsi_transport_fc.h>
22
2d70c103
NB		 23#include "qla_target.h"
24
1da177e4
LT		 25/*
26 * Driver version
27 */
28char qla2x00_version_str[40];
29
6a03b4cd
HZ		 30static int apidev_major;
31
1da177e4
LT		 32/*
33 * SRB allocation cache
34 */
d7459527 35struct kmem_cache *srb_cachep;
1da177e4 36
cbb01c2f
AE		 37int ql2xfulldump_on_mpifail;
38module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR);
39MODULE_PARM_DESC(ql2xfulldump_on_mpifail,
40 "Set this to take full dump on MPI hang.");
41
a9083016
GM		 42/*
43 * CT6 CTX allocation cache
44 */
45static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 46/*
47 * error level for logging
48 */
3f006ac3 49uint ql_errlev = 0x8001;
a9083016 50
fa492630 51static int ql2xenableclass2;
2d70c103
NB		 52module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
53MODULE_PARM_DESC(ql2xenableclass2,
54 "Specify if Class 2 operations are supported from the very "
55 "beginning. Default is 0 - class 2 not supported.");
56
8ae6d9c7 57
1da177e4 58int ql2xlogintimeout = 20;
f2019cb1 59module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 60MODULE_PARM_DESC(ql2xlogintimeout,
61 "Login timeout value in seconds.");
62
a7b61842 63int qlport_down_retry;
f2019cb1 64module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 65MODULE_PARM_DESC(qlport_down_retry,
900d9f98 66 "Maximum number of command retries to a port that returns "
1da177e4
LT		 67 "a PORT-DOWN status.");
68
1da177e4
LT		 69int ql2xplogiabsentdevice;
70module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
71MODULE_PARM_DESC(ql2xplogiabsentdevice,
72 "Option to enable PLOGI to devices that are not present after "
900d9f98 73 "a Fabric scan. This is needed for several broken switches. "
0d52e642 74 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 75
c1c7178c 76int ql2xloginretrycount;
f2019cb1 77module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 78MODULE_PARM_DESC(ql2xloginretrycount,
79 "Specify an alternate value for the NVRAM login retry count.");
80
a7a167bf 81int ql2xallocfwdump = 1;
f2019cb1 82module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 83MODULE_PARM_DESC(ql2xallocfwdump,
84 "Option to enable allocation of memory for a firmware dump "
85 "during HBA initialization. Memory allocation requirements "
86 "vary by ISP type. Default is 1 - allocate memory.");
87
11010fec 88int ql2xextended_error_logging;
27d94035 89module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 90module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 91MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 92 "Option to enable extended error logging,\n"
93 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
94 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
95 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
96 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
97 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
98 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
99 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
100 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 101 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
102 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 103 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 104 "\t\t0x1e400000 - Preferred value for capturing essential "
105 "debug information (equivalent to old "
106 "ql2xextended_error_logging=1).\n"
3ce8866c 107 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 108
a9083016 109int ql2xshiftctondsd = 6;
f2019cb1 110module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 111MODULE_PARM_DESC(ql2xshiftctondsd,
112 "Set to control shifting of command type processing "
113 "based on total number of SG elements.");
114
58e2753c 115int ql2xfdmienable = 1;
de187df8 116module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 117module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 118MODULE_PARM_DESC(ql2xfdmienable,
7794a5af 119 "Enables FDMI registrations. "
bd7de0b1
JC		 120 "0 - no FDMI registrations. "
121 "1 - provide FDMI registrations (default).");
cca5335c 122
d213a4b7 123#define MAX_Q_DEPTH 64
50280c01 124static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 125module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
126MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 127 "Maximum queue depth to set for each LUN. "
d213a4b7 128 "Default is 64.");
df7baa50 129
9e522cd8
AE		 130int ql2xenabledif = 2;
131module_param(ql2xenabledif, int, S_IRUGO);
bad75002 132MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 133 " Enable T10-CRC-DIF:\n"
134 " Default is 2.\n"
135 " 0 -- No DIF Support\n"
136 " 1 -- Enable DIF for all types\n"
137 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 138
e84067d7
DG		 139#if (IS_ENABLED(CONFIG_NVME_FC))
140int ql2xnvmeenable = 1;
141#else
142int ql2xnvmeenable;
143#endif
144module_param(ql2xnvmeenable, int, 0644);
145MODULE_PARM_DESC(ql2xnvmeenable,
146 "Enables NVME support. "
147 "0 - no NVMe. Default is Y");
148
8cb2049c 149int ql2xenablehba_err_chk = 2;
bad75002
AE		 150module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
151MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 152 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 153 " Default is 2.\n"
8cb2049c
AE		 154 " 0 -- Error isolation disabled\n"
155 " 1 -- Error isolation enabled only for DIX Type 0\n"
156 " 2 -- Error isolation enabled for all Types\n");
bad75002 157
58e2753c 158int ql2xiidmaenable = 1;
f2019cb1 159module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 160MODULE_PARM_DESC(ql2xiidmaenable,
161 "Enables iIDMA settings "
162 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
163
d7459527
MH		 164int ql2xmqsupport = 1;
165module_param(ql2xmqsupport, int, S_IRUGO);
166MODULE_PARM_DESC(ql2xmqsupport,
167 "Enable on demand multiple queue pairs support "
168 "Default is 1 for supported. "
169 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 170
171int ql2xfwloadbin;
86e45bf6 172module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 173module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 174MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 175 "Option to specify location from which to load ISP firmware:.\n"
176 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 177 " interface.\n"
178 " 1 -- load firmware from flash.\n"
179 " 0 -- use default semantics.\n");
180
ae97c91e 181int ql2xetsenable;
f2019cb1 182module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 183MODULE_PARM_DESC(ql2xetsenable,
184 "Enables firmware ETS burst."
185 "Default is 0 - skip ETS enablement.");
186
6907869d 187int ql2xdbwr = 1;
86e45bf6 188module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 189MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 190 "Option to specify scheme for request queue posting.\n"
191 " 0 -- Regular doorbell.\n"
192 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 193
f4c496c1 194int ql2xtargetreset = 1;
f2019cb1 195module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 196MODULE_PARM_DESC(ql2xtargetreset,
197 "Enable target reset."
198 "Default is 1 - use hw defaults.");
199
4da26e16 200int ql2xgffidenable;
f2019cb1 201module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 202MODULE_PARM_DESC(ql2xgffidenable,
203 "Enables GFF_ID checks of port type. "
204 "Default is 0 - Do not use GFF_ID information.");
a9083016 205
043dc1d7 206int ql2xasynctmfenable = 1;
f2019cb1 207module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 208MODULE_PARM_DESC(ql2xasynctmfenable,
209 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 210 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 211
212int ql2xdontresethba;
86e45bf6 213module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 214MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 215 "Option to specify reset behaviour.\n"
216 " 0 (Default) -- Reset on failure.\n"
217 " 1 -- Do not reset on failure.\n");
ed0de87c 218
1abf635d
HR		 219uint64_t ql2xmaxlun = MAX_LUNS;
220module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 221MODULE_PARM_DESC(ql2xmaxlun,
222 "Defines the maximum LU number to register with the SCSI "
223 "midlayer. Default is 65535.");
224
08de2844
GM		 225int ql2xmdcapmask = 0x1F;
226module_param(ql2xmdcapmask, int, S_IRUGO);
227MODULE_PARM_DESC(ql2xmdcapmask,
228 "Set the Minidump driver capture mask level. "
6e96fa7b 229 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 230
3aadff35 231int ql2xmdenable = 1;
08de2844
GM		 232module_param(ql2xmdenable, int, S_IRUGO);
233MODULE_PARM_DESC(ql2xmdenable,
234 "Enable/disable MiniDump. "
3aadff35
GM		 235 "0 - MiniDump disabled. "
236 "1 (Default) - MiniDump enabled.");
08de2844 237
c1c7178c 238int ql2xexlogins;
b0d6cabd
HM		 239module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
240MODULE_PARM_DESC(ql2xexlogins,
241 "Number of extended Logins. "
242 "0 (Default)- Disabled.");
243
99e1b683
QT		 244int ql2xexchoffld = 1024;
245module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 246MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 247 "Number of target exchanges.");
248
249int ql2xiniexchg = 1024;
250module_param(ql2xiniexchg, uint, 0644);
251MODULE_PARM_DESC(ql2xiniexchg,
252 "Number of initiator exchanges.");
2f56a7f1 253
c1c7178c 254int ql2xfwholdabts;
f198cafa
HM		 255module_param(ql2xfwholdabts, int, S_IRUGO);
256MODULE_PARM_DESC(ql2xfwholdabts,
257 "Allow FW to hold status IOCB until ABTS rsp received. "
258 "0 (Default) Do not set fw option. "
259 "1 - Set fw option to hold ABTS.");
260
41dc529a
QT		 261int ql2xmvasynctoatio = 1;
262module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
263MODULE_PARM_DESC(ql2xmvasynctoatio,
264 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
265 "0 (Default). Do not move IOCBs"
266 "1 - Move IOCBs.");
267
e4e3a2ce
QT		 268int ql2xautodetectsfp = 1;
269module_param(ql2xautodetectsfp, int, 0444);
270MODULE_PARM_DESC(ql2xautodetectsfp,
271 "Detect SFP range and set appropriate distance.\n"
272 "1 (Default): Enable\n");
273
e7240af5
HM		 274int ql2xenablemsix = 1;
275module_param(ql2xenablemsix, int, 0444);
276MODULE_PARM_DESC(ql2xenablemsix,
277 "Set to enable MSI or MSI-X interrupt mechanism.\n"
278 " Default is 1, enable MSI-X interrupt mechanism.\n"
279 " 0 -- enable traditional pin-based mechanism.\n"
280 " 1 -- enable MSI-X interrupt mechanism.\n"
281 " 2 -- enable MSI interrupt mechanism.\n");
282
9ecf0b0d
QT		 283int qla2xuseresexchforels;
284module_param(qla2xuseresexchforels, int, 0444);
285MODULE_PARM_DESC(qla2xuseresexchforels,
286 "Reserve 1/2 of emergency exchanges for ELS.\n"
287 " 0 (default): disabled");
288
b3ede8ea 289static int ql2xprotmask;
7855d2ba
MP		 290module_param(ql2xprotmask, int, 0644);
291MODULE_PARM_DESC(ql2xprotmask,
292 "Override DIF/DIX protection capabilities mask\n"
293 "Default is 0 which sets protection mask based on "
294 "capabilities reported by HBA firmware.\n");
295
b3ede8ea 296static int ql2xprotguard;
7855d2ba
MP		 297module_param(ql2xprotguard, int, 0644);
298MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
299 " 0 -- Let HBA firmware decide\n"
300 " 1 -- Force T10 CRC\n"
301 " 2 -- Force IP checksum\n");
302
50b81275
GM		 303int ql2xdifbundlinginternalbuffers;
304module_param(ql2xdifbundlinginternalbuffers, int, 0644);
305MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
306 "Force using internal buffers for DIF information\n"
307 "0 (Default). Based on check.\n"
308 "1 Force using internal buffers\n");
309
d83a80ee
JC		 310int ql2xsmartsan;
311module_param(ql2xsmartsan, int, 0444);
312module_param_named(smartsan, ql2xsmartsan, int, 0444);
313MODULE_PARM_DESC(ql2xsmartsan,
314 "Send SmartSAN Management Attributes for FDMI Registration."
315 " Default is 0 - No SmartSAN registration,"
316 " 1 - Register SmartSAN Management Attributes.");
317
bd7de0b1
JC		 318int ql2xrdpenable;
319module_param(ql2xrdpenable, int, 0444);
320module_param_named(rdpenable, ql2xrdpenable, int, 0444);
321MODULE_PARM_DESC(ql2xrdpenable,
322 "Enables RDP responses. "
323 "0 - no RDP responses (default). "
324 "1 - provide RDP responses.");
d83a80ee 325
1a2fbf18 326static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 327static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 328static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 329static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 330
45235022 331
1da177e4 332static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 333struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 334
1da177e4
LT		 335/* TODO Convert to inlines
336 *
337 * Timer routines
338 */
1da177e4 339
2c3dfe3f 340__inline__ void
8e5f4ba0 341qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 342{
8e5f4ba0 343 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 344 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 345 add_timer(&vha->timer);
346 vha->timer_active = 1;
1da177e4
LT		 347}
348
349static inline void
e315cd28 350qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 351{
a9083016 352 /* Currently used for 82XX only. */
7c3df132
SK		 353 if (vha->device_flags & DFLG_DEV_FAILED) {
354 ql_dbg(ql_dbg_timer, vha, 0x600d,
355 "Device in a failed state, returning.\n");
a9083016 356 return;
7c3df132 357 }
a9083016 358
e315cd28 359 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 360}
361
a824ebb3 362static __inline__ void
e315cd28 363qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 364{
e315cd28
AC		 365 del_timer_sync(&vha->timer);
366 vha->timer_active = 0;
1da177e4
LT		 367}
368
1da177e4
LT		 369static int qla2x00_do_dpc(void *data);
370
371static void qla2x00_rst_aen(scsi_qla_host_t *);
372
73208dfd
AC		 373static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
374 struct req_que **, struct rsp_que **);
e30d1756 375static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 376static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 377int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
378 struct qla_qpair *qpair);
1da177e4 379
1da177e4 380/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 381static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
382 struct rsp_que *rsp)
383{
384 struct qla_hw_data *ha = vha->hw;
bd432bb5 385
8abfa9e2
QT		 386 rsp->qpair = ha->base_qpair;
387 rsp->req = req;
0691094f 388 ha->base_qpair->hw = ha;
8abfa9e2
QT		 389 ha->base_qpair->req = req;
390 ha->base_qpair->rsp = rsp;
391 ha->base_qpair->vha = vha;
392 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
393 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
394 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 395 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 396 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
397 ha->base_qpair->enable_class_2 = ql2xenableclass2;
398 /* init qpair to this cpu. Will adjust at run time. */
86531887 399 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 400 ha->base_qpair->pdev = ha->pdev;
401
ecc89f25 402 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 403 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
404}
405
9a347ff4
CD		 406static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
407 struct rsp_que *rsp)
73208dfd 408{
7c3df132 409 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 410
6396bb22 411 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 412 GFP_KERNEL);
413 if (!ha->req_q_map) {
7c3df132
SK		 414 ql_log(ql_log_fatal, vha, 0x003b,
415 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 416 goto fail_req_map;
417 }
418
6396bb22 419 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 420 GFP_KERNEL);
421 if (!ha->rsp_q_map) {
7c3df132
SK		 422 ql_log(ql_log_fatal, vha, 0x003c,
423 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 424 goto fail_rsp_map;
425 }
d7459527 426
e326d22a
QT		 427 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
428 if (ha->base_qpair == NULL) {
429 ql_log(ql_log_warn, vha, 0x00e0,
430 "Failed to allocate base queue pair memory.\n");
431 goto fail_base_qpair;
432 }
433
8abfa9e2 434 qla_init_base_qpair(vha, req, rsp);
e326d22a 435
c38d1baf 436 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 437 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
438 GFP_KERNEL);
439 if (!ha->queue_pair_map) {
440 ql_log(ql_log_fatal, vha, 0x0180,
441 "Unable to allocate memory for queue pair ptrs.\n");
442 goto fail_qpair_map;
443 }
d7459527
MH		 444 }
445
9a347ff4
CD		 446 /*
447 * Make sure we record at least the request and response queue zero in
448 * case we need to free them if part of the probe fails.
449 */
450 ha->rsp_q_map[0] = rsp;
451 ha->req_q_map[0] = req;
73208dfd
AC		 452 set_bit(0, ha->rsp_qid_map);
453 set_bit(0, ha->req_qid_map);
6a2cf8d3 454 return 0;
73208dfd 455
d7459527 456fail_qpair_map:
82de802a
QT		 457 kfree(ha->base_qpair);
458 ha->base_qpair = NULL;
459fail_base_qpair:
d7459527
MH		 460 kfree(ha->rsp_q_map);
461 ha->rsp_q_map = NULL;
73208dfd
AC		 462fail_rsp_map:
463 kfree(ha->req_q_map);
464 ha->req_q_map = NULL;
465fail_req_map:
466 return -ENOMEM;
467}
468
2afa19a9 469static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 470{
8ae6d9c7
GM		 471 if (IS_QLAFX00(ha)) {
472 if (req && req->ring_fx00)
473 dma_free_coherent(&ha->pdev->dev,
474 (req->length_fx00 + 1) * sizeof(request_t),
475 req->ring_fx00, req->dma_fx00);
476 } else if (req && req->ring)
73208dfd
AC		 477 dma_free_coherent(&ha->pdev->dev,
478 (req->length + 1) * sizeof(request_t),
479 req->ring, req->dma);
480
6d634067 481 if (req)
8d93f550 482 kfree(req->outstanding_cmds);
6d634067
BK		 483
484 kfree(req);
73208dfd
AC		 485}
486
2afa19a9
AC		 487static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
488{
8ae6d9c7 489 if (IS_QLAFX00(ha)) {
3f6c9be2 490 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 491 dma_free_coherent(&ha->pdev->dev,
492 (rsp->length_fx00 + 1) * sizeof(request_t),
493 rsp->ring_fx00, rsp->dma_fx00);
494 } else if (rsp && rsp->ring) {
2afa19a9
AC		 495 dma_free_coherent(&ha->pdev->dev,
496 (rsp->length + 1) * sizeof(response_t),
497 rsp->ring, rsp->dma);
8ae6d9c7 498 }
6d634067 499 kfree(rsp);
2afa19a9
AC		 500}
501
73208dfd
AC		 502static void qla2x00_free_queues(struct qla_hw_data *ha)
503{
504 struct req_que *req;
505 struct rsp_que *rsp;
506 int cnt;
093df737 507 unsigned long flags;
73208dfd 508
82de802a
QT		 509 if (ha->queue_pair_map) {
510 kfree(ha->queue_pair_map);
511 ha->queue_pair_map = NULL;
512 }
513 if (ha->base_qpair) {
514 kfree(ha->base_qpair);
515 ha->base_qpair = NULL;
516 }
517
093df737 518 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 519 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 520 if (!test_bit(cnt, ha->req_qid_map))
521 continue;
522
73208dfd 523 req = ha->req_q_map[cnt];
093df737
QT		 524 clear_bit(cnt, ha->req_qid_map);
525 ha->req_q_map[cnt] = NULL;
526
527 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 528 qla2x00_free_req_que(ha, req);
093df737 529 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 530 }
093df737
QT		 531 spin_unlock_irqrestore(&ha->hardware_lock, flags);
532
73208dfd
AC		 533 kfree(ha->req_q_map);
534 ha->req_q_map = NULL;
2afa19a9 535
093df737
QT		 536
537 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 538 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 539 if (!test_bit(cnt, ha->rsp_qid_map))
540 continue;
541
2afa19a9 542 rsp = ha->rsp_q_map[cnt];
c3c42394 543 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 544 ha->rsp_q_map[cnt] = NULL;
545 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 546 qla2x00_free_rsp_que(ha, rsp);
093df737 547 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 548 }
093df737
QT		 549 spin_unlock_irqrestore(&ha->hardware_lock, flags);
550
2afa19a9
AC		 551 kfree(ha->rsp_q_map);
552 ha->rsp_q_map = NULL;
73208dfd
AC		 553}
554
1da177e4 555static char *
dc6d6d34 556qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
1da177e4 557{
e315cd28 558 struct qla_hw_data *ha = vha->hw;
dc6d6d34 559 static const char *const pci_bus_modes[] = {
1da177e4
LT		 560 "33", "66", "100", "133",
561 };
562 uint16_t pci_bus;
563
1da177e4
LT		 564 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
565 if (pci_bus) {
dc6d6d34
BVA		 566 snprintf(str, str_len, "PCI-X (%s MHz)",
567 pci_bus_modes[pci_bus]);
1da177e4
LT		 568 } else {
569 pci_bus = (ha->pci_attr & BIT_8) >> 8;
dc6d6d34 570 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]);
1da177e4 571 }
1da177e4 572
dc6d6d34 573 return str;
1da177e4
LT		 574}
575
fca29703 576static char *
dc6d6d34 577qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len)
fca29703 578{
dc6d6d34
BVA		 579 static const char *const pci_bus_modes[] = {
580 "33", "66", "100", "133",
581 };
e315cd28 582 struct qla_hw_data *ha = vha->hw;
fca29703 583 uint32_t pci_bus;
fca29703 584
62a276f8 585 if (pci_is_pcie(ha->pdev)) {
62a276f8 586 uint32_t lstat, lspeed, lwidth;
dc6d6d34 587 const char *speed_str;
fca29703 588
62a276f8
BH		 589 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
590 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
591 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703 592
49300af7
SK		 593 switch (lspeed) {
594 case 1:
dc6d6d34 595 speed_str = "2.5GT/s";
49300af7
SK		 596 break;
597 case 2:
dc6d6d34 598 speed_str = "5.0GT/s";
49300af7
SK		 599 break;
600 case 3:
dc6d6d34 601 speed_str = "8.0GT/s";
49300af7 602 break;
efd39a2a
HM		 603 case 4:
604 speed_str = "16.0GT/s";
605 break;
49300af7 606 default:
dc6d6d34 607 speed_str = "<unknown>";
49300af7
SK		 608 break;
609 }
dc6d6d34 610 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth);
fca29703
AV		 611
612 return str;
613 }
614
fca29703 615 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
dc6d6d34
BVA		 616 if (pci_bus == 0 || pci_bus == 8)
617 snprintf(str, str_len, "PCI (%s MHz)",
618 pci_bus_modes[pci_bus >> 3]);
619 else
620 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)",
621 pci_bus & 4 ? 2 : 1,
622 pci_bus_modes[pci_bus & 3]);
fca29703
AV		 623
624 return str;
625}
626
e5f82ab8 627static char *
df57caba 628qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 629{
630 char un_str[10];
e315cd28 631 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 632
df57caba
HM		 633 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
634 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 635
636 if (ha->fw_attributes & BIT_9) {
637 strcat(str, "FLX");
638 return (str);
639 }
640
641 switch (ha->fw_attributes & 0xFF) {
642 case 0x7:
643 strcat(str, "EF");
644 break;
645 case 0x17:
646 strcat(str, "TP");
647 break;
648 case 0x37:
649 strcat(str, "IP");
650 break;
651 case 0x77:
652 strcat(str, "VI");
653 break;
654 default:
655 sprintf(un_str, "(%x)", ha->fw_attributes);
656 strcat(str, un_str);
657 break;
658 }
659 if (ha->fw_attributes & 0x100)
660 strcat(str, "X");
661
662 return (str);
663}
664
e5f82ab8 665static char *
df57caba 666qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 667{
e315cd28 668 struct qla_hw_data *ha = vha->hw;
f0883ac6 669
df57caba 670 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 671 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 672 return str;
fca29703
AV		 673}
674
6c18a43e 675void qla2x00_sp_free_dma(srb_t *sp)
fca29703 676{
25ff6af1 677 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 678 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
fca29703 679
9ba56b95
GM		 680 if (sp->flags & SRB_DMA_VALID) {
681 scsi_dma_unmap(cmd);
682 sp->flags &= ~SRB_DMA_VALID;
7c3df132 683 }
fca29703 684
9ba56b95
GM		 685 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
686 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
687 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
688 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
689 }
690
691 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
692 /* List assured to be having elements */
5ec9f904 693 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
9ba56b95
GM		 694 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
695 }
696
697 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
5ec9f904 698 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
d5ff0eed
JC		 699
700 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 701 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
702 }
703
704 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
5ec9f904 705 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
fca29703 706
9ba56b95 707 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 708 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 709 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
710 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
711 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
712 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 713 }
9ba56b95
GM		 714}
715
6c18a43e 716void qla2x00_sp_compl(srb_t *sp, int res)
9ba56b95 717{
9ba56b95 718 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 719 struct completion *comp = sp->comp;
9ba56b95 720
f3caa990 721 sp->free(sp);
740e2935 722 cmd->result = res;
711a08d7 723 CMD_SP(cmd) = NULL;
9ba56b95 724 cmd->scsi_done(cmd);
219d27d7
BVA		 725 if (comp)
726 complete(comp);
fca29703
AV		 727}
728
6c18a43e 729void qla2xxx_qpair_sp_free_dma(srb_t *sp)
d7459527 730{
d7459527
MH		 731 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
732 struct qla_hw_data *ha = sp->fcport->vha->hw;
d7459527
MH		 733
734 if (sp->flags & SRB_DMA_VALID) {
735 scsi_dma_unmap(cmd);
736 sp->flags &= ~SRB_DMA_VALID;
737 }
738
739 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
740 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
741 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
742 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
743 }
744
745 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
746 /* List assured to be having elements */
5ec9f904 747 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx);
d7459527
MH		 748 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
749 }
750
50b81275 751 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
5ec9f904 752 struct crc_context *difctx = sp->u.scmd.crc_ctx;
50b81275
GM		 753 struct dsd_dma *dif_dsd, *nxt_dsd;
754
755 list_for_each_entry_safe(dif_dsd, nxt_dsd,
756 &difctx->ldif_dma_hndl_list, list) {
757 list_del(&dif_dsd->list);
758 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
759 dif_dsd->dsd_list_dma);
760 kfree(dif_dsd);
761 difctx->no_dif_bundl--;
762 }
763
764 list_for_each_entry_safe(dif_dsd, nxt_dsd,
765 &difctx->ldif_dsd_list, list) {
766 list_del(&dif_dsd->list);
767 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
768 dif_dsd->dsd_list_dma);
769 kfree(dif_dsd);
770 difctx->no_ldif_dsd--;
771 }
772
773 if (difctx->no_ldif_dsd) {
774 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
775 "%s: difctx->no_ldif_dsd=%x\n",
776 __func__, difctx->no_ldif_dsd);
777 }
778
779 if (difctx->no_dif_bundl) {
780 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
781 "%s: difctx->no_dif_bundl=%x\n",
782 __func__, difctx->no_dif_bundl);
783 }
784 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 785 }
d8f945bf
BVA		 786
787 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
5ec9f904 788 struct ct6_dsd *ctx1 = sp->u.scmd.ct6_ctx;
d8f945bf
BVA		 789
790 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
791 ctx1->fcp_cmnd_dma);
792 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
793 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
794 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
795 mempool_free(ctx1, ha->ctx_mempool);
796 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
797 }
798
799 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
5ec9f904 800 struct crc_context *ctx0 = sp->u.scmd.crc_ctx;
d8f945bf 801
5ec9f904 802 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
d8f945bf
BVA		 803 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
804 }
d7459527
MH		 805}
806
6c18a43e 807void qla2xxx_qpair_sp_compl(srb_t *sp, int res)
d7459527 808{
d7459527 809 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 810 struct completion *comp = sp->comp;
d7459527 811
f3caa990 812 sp->free(sp);
711a08d7
GM		 813 cmd->result = res;
814 CMD_SP(cmd) = NULL;
d7459527 815 cmd->scsi_done(cmd);
219d27d7
BVA		 816 if (comp)
817 complete(comp);
d7459527
MH		 818}
819
1da177e4 820static int
f5e3e40b 821qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 822{
134ae078 823 scsi_qla_host_t *vha = shost_priv(host);
fca29703 824 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 825 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 826 struct qla_hw_data *ha = vha->hw;
827 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 828 srb_t *sp;
829 int rval;
830
2dbb02fd
BVA		 831 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
832 WARN_ON_ONCE(!rport)) {
04dfaa53
MFO		 833 cmd->result = DID_NO_CONNECT << 16;
834 goto qc24_fail_command;
835 }
836
5601236b 837 if (ha->mqenable) {
6d58ef05
BVA		 838 uint32_t tag;
839 uint16_t hwq;
840 struct qla_qpair *qpair = NULL;
841
f664a3cc
JA		 842 tag = blk_mq_unique_tag(cmd->request);
843 hwq = blk_mq_unique_tag_to_hwq(tag);
844 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 845
846 if (qpair)
847 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 848 }
849
85880801 850 if (ha->flags.eeh_busy) {
7c3df132 851 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 852 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 853 "PCI Channel IO permanent failure, exiting "
854 "cmd=%p.\n", cmd);
b9b12f73 855 cmd->result = DID_NO_CONNECT << 16;
7c3df132 856 } else {
5f28d2d7 857 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 858 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 859 cmd->result = DID_REQUEUE << 16;
7c3df132 860 }
14e660e6
SJ		 861 goto qc24_fail_command;
862 }
863
19a7b4ae
JSEC		 864 rval = fc_remote_port_chkready(rport);
865 if (rval) {
866 cmd->result = rval;
5f28d2d7 867 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 868 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
869 cmd, rval);
fca29703
AV		 870 goto qc24_fail_command;
871 }
872
bad75002
AE		 873 if (!vha->flags.difdix_supported &&
874 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 875 ql_dbg(ql_dbg_io, vha, 0x3004,
876 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
877 cmd);
bad75002
AE		 878 cmd->result = DID_NO_CONNECT << 16;
879 goto qc24_fail_command;
880 }
aa651be8
CD		 881
882 if (!fcport) {
883 cmd->result = DID_NO_CONNECT << 16;
884 goto qc24_fail_command;
885 }
886
78c3e5e6 887 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
fca29703 888 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 889 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 890 ql_dbg(ql_dbg_io, vha, 0x3005,
891 "Returning DNC, fcport_state=%d loop_state=%d.\n",
892 atomic_read(&fcport->state),
893 atomic_read(&base_vha->loop_state));
fca29703
AV		 894 cmd->result = DID_NO_CONNECT << 16;
895 goto qc24_fail_command;
896 }
7b594131 897 goto qc24_target_busy;
fca29703
AV		 898 }
899
e05fe292
CD		 900 /*
901 * Return target busy if we've received a non-zero retry_delay_timer
902 * in a FCP_RSP.
903 */
975f7d46
BP		 904 if (fcport->retry_delay_timestamp == 0) {
905 /* retry delay not set */
906 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 907 fcport->retry_delay_timestamp = 0;
908 else
909 goto qc24_target_busy;
910
85cffefa
BVA		 911 sp = scsi_cmd_priv(cmd);
912 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport);
fca29703 913
9ba56b95
GM		 914 sp->u.scmd.cmd = cmd;
915 sp->type = SRB_SCSI_CMD;
f45bca8c 916
9ba56b95
GM		 917 CMD_SP(cmd) = (void *)sp;
918 sp->free = qla2x00_sp_free_dma;
919 sp->done = qla2x00_sp_compl;
920
e315cd28 921 rval = ha->isp_ops->start_scsi(sp);
7c3df132 922 if (rval != QLA_SUCCESS) {
53016ed3 923 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 924 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 925 goto qc24_host_busy_free_sp;
7c3df132 926 }
fca29703 927
fca29703
AV		 928 return 0;
929
930qc24_host_busy_free_sp:
f3caa990 931 sp->free(sp);
fca29703 932
7b594131
MC		 933qc24_target_busy:
934 return SCSI_MLQUEUE_TARGET_BUSY;
935
fca29703 936qc24_fail_command:
f5e3e40b 937 cmd->scsi_done(cmd);
fca29703
AV		 938
939 return 0;
940}
941
d7459527
MH		 942/* For MQ supported I/O */
943int
944qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
945 struct qla_qpair *qpair)
946{
947 scsi_qla_host_t *vha = shost_priv(host);
948 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
949 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
950 struct qla_hw_data *ha = vha->hw;
951 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
952 srb_t *sp;
953 int rval;
954
2dbb02fd 955 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
d7459527
MH		 956 if (rval) {
957 cmd->result = rval;
958 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
959 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
960 cmd, rval);
961 goto qc24_fail_command;
962 }
963
964 if (!fcport) {
965 cmd->result = DID_NO_CONNECT << 16;
966 goto qc24_fail_command;
967 }
968
78c3e5e6 969 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) {
d7459527
MH		 970 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
971 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
972 ql_dbg(ql_dbg_io, vha, 0x3077,
973 "Returning DNC, fcport_state=%d loop_state=%d.\n",
974 atomic_read(&fcport->state),
975 atomic_read(&base_vha->loop_state));
976 cmd->result = DID_NO_CONNECT << 16;
977 goto qc24_fail_command;
978 }
979 goto qc24_target_busy;
980 }
981
982 /*
983 * Return target busy if we've received a non-zero retry_delay_timer
984 * in a FCP_RSP.
985 */
986 if (fcport->retry_delay_timestamp == 0) {
987 /* retry delay not set */
988 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
989 fcport->retry_delay_timestamp = 0;
990 else
991 goto qc24_target_busy;
992
85cffefa
BVA		 993 sp = scsi_cmd_priv(cmd);
994 qla2xxx_init_sp(sp, vha, qpair, fcport);
d7459527
MH		 995
996 sp->u.scmd.cmd = cmd;
997 sp->type = SRB_SCSI_CMD;
d7459527
MH		 998 CMD_SP(cmd) = (void *)sp;
999 sp->free = qla2xxx_qpair_sp_free_dma;
1000 sp->done = qla2xxx_qpair_sp_compl;
d7459527
MH		 1001
1002 rval = ha->isp_ops->start_scsi_mq(sp);
1003 if (rval != QLA_SUCCESS) {
1004 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1005 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1006 if (rval == QLA_INTERFACE_ERROR)
af2a0c51 1007 goto qc24_free_sp_fail_command;
d7459527
MH		 1008 goto qc24_host_busy_free_sp;
1009 }
1010
1011 return 0;
1012
1013qc24_host_busy_free_sp:
f3caa990 1014 sp->free(sp);
d7459527 1015
d7459527
MH		 1016qc24_target_busy:
1017 return SCSI_MLQUEUE_TARGET_BUSY;
1018
af2a0c51
QT		 1019qc24_free_sp_fail_command:
1020 sp->free(sp);
1021 CMD_SP(cmd) = NULL;
1022 qla2xxx_rel_qpair_sp(sp->qpair, sp);
1023
d7459527
MH		 1024qc24_fail_command:
1025 cmd->scsi_done(cmd);
1026
1027 return 0;
1028}
1029
1da177e4
LT		 1030/*
1031 * qla2x00_eh_wait_on_command
1032 * Waits for the command to be returned by the Firmware for some
1033 * max time.
1034 *
1035 * Input:
1da177e4 1036 * cmd = Scsi Command to wait on.
1da177e4
LT		 1037 *
1038 * Return:
fcef0893
BVA		 1039 * Completed in time : QLA_SUCCESS
1040 * Did not complete in time : QLA_FUNCTION_FAILED
1da177e4
LT		 1041 */
1042static int
e315cd28 1043qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1044{
fe74c71f 1045#define ABORT_POLLING_PERIOD 1000
478c3b03 1046#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1047 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1048 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1049 struct qla_hw_data *ha = vha->hw;
f4f051eb 1050 int ret = QLA_SUCCESS;
1da177e4 1051
85880801 1052 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1053 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1054 "Return:eh_wait.\n");
85880801
AV		 1055 return ret;
1056 }
1057
d970432c 1058 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1059 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1060 }
1061 if (CMD_SP(cmd))
1062 ret = QLA_FUNCTION_FAILED;
1da177e4 1063
f4f051eb 1064 return ret;
1da177e4
LT		 1065}
1066
1067/*
1068 * qla2x00_wait_for_hba_online
fa2a1ce5 1069 * Wait till the HBA is online after going through
1da177e4
LT		 1070 * <= MAX_RETRIES_OF_ISP_ABORT or
1071 * finally HBA is disabled ie marked offline
1072 *
1073 * Input:
1074 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1075 *
1076 * Note:
1da177e4
LT		 1077 * Does context switching-Release SPIN_LOCK
1078 * (if any) before calling this routine.
1079 *
1080 * Return:
1081 * Success (Adapter is online) : 0
1082 * Failed (Adapter is offline/disabled) : 1
1083 */
854165f4 1084int
e315cd28 1085qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1086{
fca29703
AV		 1087 int return_status;
1088 unsigned long wait_online;
e315cd28
AC		 1089 struct qla_hw_data *ha = vha->hw;
1090 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1091
fa2a1ce5 1092 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1093 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1094 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1095 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1096 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1097
1098 msleep(1000);
1099 }
e315cd28 1100 if (base_vha->flags.online)
fa2a1ce5 1101 return_status = QLA_SUCCESS;
1da177e4
LT		 1102 else
1103 return_status = QLA_FUNCTION_FAILED;
1104
1da177e4
LT		 1105 return (return_status);
1106}
1107
726b8548
QT		 1108static inline int test_fcport_count(scsi_qla_host_t *vha)
1109{
1110 struct qla_hw_data *ha = vha->hw;
1111 unsigned long flags;
1112 int res;
1113
1114 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1115 ql_dbg(ql_dbg_init, vha, 0x00ec,
1116 "tgt %p, fcport_count=%d\n",
1117 vha, vha->fcport_count);
726b8548
QT		 1118 res = (vha->fcport_count == 0);
1119 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1120
1121 return res;
1122}
1123
1124/*
1125 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1126 * it has dependency on UNLOADING flag to stop device discovery
1127 */
efa93f48 1128void
726b8548
QT		 1129qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1130{
f5187b7d
QT		 1131 u8 i;
1132
3c75ad1d 1133 qla2x00_mark_all_devices_lost(vha);
726b8548 1134
8b1062d5
MW		 1135 for (i = 0; i < 10; i++) {
1136 if (wait_event_timeout(vha->fcport_waitQ,
1137 test_fcport_count(vha), HZ) > 0)
1138 break;
1139 }
f5187b7d 1140
fd5564ba 1141 flush_workqueue(vha->hw->wq);
726b8548
QT		 1142}
1143
86fbee86 1144/*
638a1a01
SC		 1145 * qla2x00_wait_for_hba_ready
1146 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1147 *
1148 * Input:
1149 * ha - pointer to host adapter structure
1150 *
1151 * Note:
1152 * Does context switching-Release SPIN_LOCK
1153 * (if any) before calling this routine.
1154 *
86fbee86 1155 */
638a1a01
SC		 1156static void
1157qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1158{
86fbee86 1159 struct qla_hw_data *ha = vha->hw;
783e0dc4 1160 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1161
1d483901
DC		 1162 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1163 ha->flags.mbox_busy) ||
1164 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1165 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1166 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1167 break;
86fbee86 1168 msleep(1000);
783e0dc4 1169 }
86fbee86
LC		 1170}
1171
2533cf67
LC		 1172int
1173qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1174{
1175 int return_status;
1176 unsigned long wait_reset;
1177 struct qla_hw_data *ha = vha->hw;
1178 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1179
1180 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1181 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1182 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1183 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1184 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1185
1186 msleep(1000);
1187
1188 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1189 ha->flags.chip_reset_done)
1190 break;
1191 }
1192 if (ha->flags.chip_reset_done)
1193 return_status = QLA_SUCCESS;
1194 else
1195 return_status = QLA_FUNCTION_FAILED;
1196
1197 return return_status;
1198}
1199
a465537a
SC		 1200#define ISP_REG_DISCONNECT 0xffffffffU
1201/**************************************************************************
1202* qla2x00_isp_reg_stat
1203*
1204* Description:
1205* Read the host status register of ISP before aborting the command.
1206*
1207* Input:
1208* ha = pointer to host adapter structure.
1209*
1210*
1211* Returns:
1212* Either true or false.
1213*
1214* Note: Return true if there is register disconnect.
1215**************************************************************************/
1216static inline
1217uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1218{
1219 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1220 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1221
bf6061b1 1222 if (IS_P3P_TYPE(ha))
04474d3a 1223 return ((rd_reg_dword(&reg82->host_int)) == ISP_REG_DISCONNECT);
bf6061b1 1224 else
04474d3a 1225 return ((rd_reg_dword(&reg->host_status)) ==
bf6061b1 1226 ISP_REG_DISCONNECT);
a465537a
SC		 1227}
1228
1da177e4
LT		 1229/**************************************************************************
1230* qla2xxx_eh_abort
1231*
1232* Description:
1233* The abort function will abort the specified command.
1234*
1235* Input:
1236* cmd = Linux SCSI command packet to be aborted.
1237*
1238* Returns:
1239* Either SUCCESS or FAILED.
1240*
1241* Note:
2ea00202 1242* Only return FAILED if command not returned by firmware.
1da177e4 1243**************************************************************************/
e5f82ab8 1244static int
1da177e4
LT		 1245qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1246{
e315cd28 1247 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
8dd9593c 1248 DECLARE_COMPLETION_ONSTACK(comp);
f4f051eb 1249 srb_t *sp;
4e98d3b8 1250 int ret;
9cb78c16
HR		 1251 unsigned int id;
1252 uint64_t lun;
219d27d7 1253 int rval;
e315cd28 1254 struct qla_hw_data *ha = vha->hw;
f45bca8c
QT		 1255 uint32_t ratov_j;
1256 struct qla_qpair *qpair;
1257 unsigned long flags;
1da177e4 1258
a465537a
SC		 1259 if (qla2x00_isp_reg_stat(ha)) {
1260 ql_log(ql_log_info, vha, 0x8042,
1261 "PCI/Register disconnect, exiting.\n");
1262 return FAILED;
1263 }
1da177e4 1264
4e98d3b8
AV		 1265 ret = fc_block_scsi_eh(cmd);
1266 if (ret != 0)
1267 return ret;
4e98d3b8 1268
85cffefa 1269 sp = scsi_cmd_priv(cmd);
f45bca8c 1270 qpair = sp->qpair;
585def9b 1271
f45bca8c 1272 if ((sp->fcport && sp->fcport->deleted) || !qpair)
170babc3 1273 return SUCCESS;
1da177e4 1274
f45bca8c 1275 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
f45bca8c
QT		 1276 sp->comp = &comp;
1277 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1278
585def9b
QT		 1279
1280 id = cmd->device->id;
1281 lun = cmd->device->lun;
1da177e4 1282
7c3df132 1283 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1284 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1285 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1286
f45bca8c
QT		 1287 /*
1288 * Abort will release the original Command/sp from FW. Let the
1289 * original command call scsi_done. In return, he will wakeup
1290 * this sleeping thread.
1291 */
f934c9d0 1292 rval = ha->isp_ops->abort_command(sp);
f45bca8c 1293
219d27d7
BVA		 1294 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1295 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
f934c9d0 1296
f45bca8c
QT		 1297 /* Wait for the command completion. */
1298 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1299 ratov_j = msecs_to_jiffies(ratov_j);
219d27d7
BVA		 1300 switch (rval) {
1301 case QLA_SUCCESS:
8dd9593c
BVA		 1302 if (!wait_for_completion_timeout(&comp, ratov_j)) {
1303 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1304 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
f45bca8c 1305 __func__, ha->r_a_tov/10);
8dd9593c
BVA		 1306 ret = FAILED;
1307 } else {
1308 ret = SUCCESS;
1309 }
1310 break;
219d27d7 1311 default:
219d27d7
BVA		 1312 ret = FAILED;
1313 break;
1da177e4 1314 }
219d27d7 1315
8dd9593c 1316 sp->comp = NULL;
f45bca8c 1317
7c3df132 1318 ql_log(ql_log_info, vha, 0x801c,
219d27d7
BVA		 1319 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1320 vha->host_no, id, lun, ret);
1da177e4 1321
f4f051eb
AV		 1322 return ret;
1323}
1da177e4 1324
fcef0893
BVA		 1325/*
1326 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED.
1327 */
4d78c973 1328int
e315cd28 1329qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1330 uint64_t l, enum nexus_wait_type type)
f4f051eb 1331{
17d98630 1332 int cnt, match, status;
18e144d3 1333 unsigned long flags;
e315cd28 1334 struct qla_hw_data *ha = vha->hw;
73208dfd 1335 struct req_que *req;
4d78c973 1336 srb_t *sp;
9ba56b95 1337 struct scsi_cmnd *cmd;
1da177e4 1338
523ec773 1339 status = QLA_SUCCESS;
17d98630 1340
e315cd28 1341 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1342 req = vha->req;
17d98630 1343 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1344 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1345 sp = req->outstanding_cmds[cnt];
1346 if (!sp)
523ec773 1347 continue;
9ba56b95 1348 if (sp->type != SRB_SCSI_CMD)
cf53b069 1349 continue;
25ff6af1 1350 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1351 continue;
1352 match = 0;
9ba56b95 1353 cmd = GET_CMD_SP(sp);
17d98630
AC		 1354 switch (type) {
1355 case WAIT_HOST:
1356 match = 1;
1357 break;
1358 case WAIT_TARGET:
9ba56b95 1359 match = cmd->device->id == t;
17d98630
AC		 1360 break;
1361 case WAIT_LUN:
9ba56b95
GM		 1362 match = (cmd->device->id == t &&
1363 cmd->device->lun == l);
17d98630 1364 break;
73208dfd 1365 }
17d98630
AC		 1366 if (!match)
1367 continue;
1368
1369 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1370 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1371 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1372 }
e315cd28 1373 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1374
1375 return status;
1da177e4
LT		 1376}
1377
523ec773
AV		 1378static char *reset_errors[] = {
1379 "HBA not online",
1380 "HBA not ready",
1381 "Task management failed",
1382 "Waiting for command completions",
1383};
1da177e4 1384
e5f82ab8 1385static int
523ec773 1386__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1387 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1388{
e315cd28 1389 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1390 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1391 int err;
1da177e4 1392
7c3df132 1393 if (!fcport) {
523ec773 1394 return FAILED;
7c3df132 1395 }
1da177e4 1396
4e98d3b8
AV		 1397 err = fc_block_scsi_eh(cmd);
1398 if (err != 0)
1399 return err;
1400
7f4374e6
QT		 1401 if (fcport->deleted)
1402 return SUCCESS;
1403
7c3df132 1404 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1405 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1406 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1407
523ec773 1408 err = 0;
7c3df132
SK		 1409 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1410 ql_log(ql_log_warn, vha, 0x800a,
1411 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1412 goto eh_reset_failed;
7c3df132 1413 }
523ec773 1414 err = 2;
ac444b4f 1415 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1416 != QLA_SUCCESS) {
1417 ql_log(ql_log_warn, vha, 0x800c,
1418 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1419 goto eh_reset_failed;
7c3df132 1420 }
523ec773 1421 err = 3;
e315cd28 1422 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1423 cmd->device->lun, type) != QLA_SUCCESS) {
1424 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1425 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1426 goto eh_reset_failed;
7c3df132 1427 }
523ec773 1428
7c3df132 1429 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1430 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1431 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1432
1433 return SUCCESS;
1434
4d78c973 1435eh_reset_failed:
7c3df132 1436 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1437 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1438 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1439 cmd);
523ec773
AV		 1440 return FAILED;
1441}
1da177e4 1442
523ec773
AV		 1443static int
1444qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1445{
e315cd28
AC		 1446 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1447 struct qla_hw_data *ha = vha->hw;
1da177e4 1448
a465537a
SC		 1449 if (qla2x00_isp_reg_stat(ha)) {
1450 ql_log(ql_log_info, vha, 0x803e,
1451 "PCI/Register disconnect, exiting.\n");
1452 return FAILED;
1453 }
1454
523ec773
AV		 1455 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1456 ha->isp_ops->lun_reset);
1da177e4
LT		 1457}
1458
1da177e4 1459static int
523ec773 1460qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1461{
e315cd28
AC		 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1463 struct qla_hw_data *ha = vha->hw;
1da177e4 1464
a465537a
SC		 1465 if (qla2x00_isp_reg_stat(ha)) {
1466 ql_log(ql_log_info, vha, 0x803f,
1467 "PCI/Register disconnect, exiting.\n");
1468 return FAILED;
1469 }
1470
523ec773
AV		 1471 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1472 ha->isp_ops->target_reset);
1da177e4
LT		 1473}
1474
1da177e4
LT		 1475/**************************************************************************
1476* qla2xxx_eh_bus_reset
1477*
1478* Description:
1479* The bus reset function will reset the bus and abort any executing
1480* commands.
1481*
1482* Input:
1483* cmd = Linux SCSI command packet of the command that cause the
1484* bus reset.
1485*
1486* Returns:
1487* SUCCESS/FAILURE (defined as macro in scsi.h).
1488*
1489**************************************************************************/
e5f82ab8 1490static int
1da177e4
LT		 1491qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1492{
e315cd28 1493 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1494 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1495 int ret = FAILED;
9cb78c16
HR		 1496 unsigned int id;
1497 uint64_t lun;
a465537a
SC		 1498 struct qla_hw_data *ha = vha->hw;
1499
1500 if (qla2x00_isp_reg_stat(ha)) {
1501 ql_log(ql_log_info, vha, 0x8040,
1502 "PCI/Register disconnect, exiting.\n");
1503 return FAILED;
1504 }
f4f051eb 1505
f4f051eb
AV		 1506 id = cmd->device->id;
1507 lun = cmd->device->lun;
1da177e4 1508
7c3df132 1509 if (!fcport) {
f4f051eb 1510 return ret;
7c3df132 1511 }
1da177e4 1512
4e98d3b8
AV		 1513 ret = fc_block_scsi_eh(cmd);
1514 if (ret != 0)
1515 return ret;
1516 ret = FAILED;
1517
7f4374e6
QT		 1518 if (qla2x00_chip_is_down(vha))
1519 return ret;
1520
7c3df132 1521 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1522 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1523
e315cd28 1524 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1525 ql_log(ql_log_fatal, vha, 0x8013,
1526 "Wait for hba online failed board disabled.\n");
f4f051eb 1527 goto eh_bus_reset_done;
1da177e4
LT		 1528 }
1529
ad537689
SK		 1530 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1531 ret = SUCCESS;
1532
f4f051eb
AV		 1533 if (ret == FAILED)
1534 goto eh_bus_reset_done;
1da177e4 1535
9a41a62b 1536 /* Flush outstanding commands. */
4d78c973 1537 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1538 QLA_SUCCESS) {
1539 ql_log(ql_log_warn, vha, 0x8014,
1540 "Wait for pending commands failed.\n");
9a41a62b 1541 ret = FAILED;
7c3df132 1542 }
1da177e4 1543
f4f051eb 1544eh_bus_reset_done:
7c3df132 1545 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1546 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1547 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1548
f4f051eb 1549 return ret;
1da177e4
LT		 1550}
1551
1552/**************************************************************************
1553* qla2xxx_eh_host_reset
1554*
1555* Description:
1556* The reset function will reset the Adapter.
1557*
1558* Input:
1559* cmd = Linux SCSI command packet of the command that cause the
1560* adapter reset.
1561*
1562* Returns:
1563* Either SUCCESS or FAILED.
1564*
1565* Note:
1566**************************************************************************/
e5f82ab8 1567static int
1da177e4
LT		 1568qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1569{
e315cd28 1570 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1571 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1572 int ret = FAILED;
9cb78c16
HR		 1573 unsigned int id;
1574 uint64_t lun;
e315cd28 1575 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1576
a465537a
SC		 1577 if (qla2x00_isp_reg_stat(ha)) {
1578 ql_log(ql_log_info, vha, 0x8041,
1579 "PCI/Register disconnect, exiting.\n");
1580 schedule_work(&ha->board_disable);
1581 return SUCCESS;
1582 }
1583
f4f051eb
AV		 1584 id = cmd->device->id;
1585 lun = cmd->device->lun;
f4f051eb 1586
7c3df132 1587 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1588 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1589
63ee7072
CD		 1590 /*
1591 * No point in issuing another reset if one is active. Also do not
1592 * attempt a reset if we are updating flash.
1593 */
1594 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1595 goto eh_host_reset_lock;
1da177e4 1596
e315cd28
AC		 1597 if (vha != base_vha) {
1598 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1599 goto eh_host_reset_lock;
e315cd28 1600 } else {
7ec0effd 1601 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1602 if (!qla82xx_fcoe_ctx_reset(vha)) {
1603 /* Ctx reset success */
1604 ret = SUCCESS;
1605 goto eh_host_reset_lock;
1606 }
1607 /* fall thru if ctx reset failed */
1608 }
68ca949c
AC		 1609 if (ha->wq)
1610 flush_workqueue(ha->wq);
1611
e315cd28 1612 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1613 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1614 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1615 /* failed. schedule dpc to try */
1616 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1617
7c3df132
SK		 1618 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1619 ql_log(ql_log_warn, vha, 0x802a,
1620 "wait for hba online failed.\n");
e315cd28 1621 goto eh_host_reset_lock;
7c3df132 1622 }
e315cd28
AC		 1623 }
1624 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1625 }
1da177e4 1626
e315cd28 1627 /* Waiting for command to be returned to OS.*/
4d78c973 1628 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1629 QLA_SUCCESS)
f4f051eb 1630 ret = SUCCESS;
1da177e4 1631
f4f051eb 1632eh_host_reset_lock:
cfb0919c 1633 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1634 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1635 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1636
f4f051eb
AV		 1637 return ret;
1638}
1da177e4
LT		 1639
1640/*
1641* qla2x00_loop_reset
1642* Issue loop reset.
1643*
1644* Input:
1645* ha = adapter block pointer.
1646*
1647* Returns:
1648* 0 = success
1649*/
a4722cf2 1650int
e315cd28 1651qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1652{
0c8c39af 1653 int ret;
bdf79621 1654 struct fc_port *fcport;
e315cd28 1655 struct qla_hw_data *ha = vha->hw;
1da177e4 1656
5854771e
AB		 1657 if (IS_QLAFX00(ha)) {
1658 return qlafx00_loop_reset(vha);
1659 }
1660
f4c496c1 1661 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1662 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1663 if (fcport->port_type != FCT_TARGET)
1664 continue;
1665
1666 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1667 if (ret != QLA_SUCCESS) {
7c3df132 1668 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1669 "Bus Reset failed: Reset=%d "
7c3df132 1670 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1671 }
1672 }
1673 }
1674
8ae6d9c7 1675
6246b8a1 1676 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1677 atomic_set(&vha->loop_state, LOOP_DOWN);
1678 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
3c75ad1d 1679 qla2x00_mark_all_devices_lost(vha);
e315cd28 1680 ret = qla2x00_full_login_lip(vha);
0c8c39af 1681 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1682 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1683 "full_login_lip=%d.\n", ret);
749af3d5 1684 }
0c8c39af
AV		 1685 }
1686
0d6e61bc 1687 if (ha->flags.enable_lip_reset) {
e315cd28 1688 ret = qla2x00_lip_reset(vha);
ad537689 1689 if (ret != QLA_SUCCESS)
7c3df132
SK		 1690 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1691 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1692 }
1693
1da177e4 1694 /* Issue marker command only when we are going to start the I/O */
e315cd28 1695 vha->marker_needed = 1;
1da177e4 1696
0c8c39af 1697 return QLA_SUCCESS;
1da177e4
LT		 1698}
1699
c81ef0ed
BVA		 1700/*
1701 * The caller must ensure that no completion interrupts will happen
1702 * while this function is in progress.
1703 */
c4e521b6
BVA		 1704static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1705 unsigned long *flags)
1706 __releases(qp->qp_lock_ptr)
1707 __acquires(qp->qp_lock_ptr)
1708{
219d27d7 1709 DECLARE_COMPLETION_ONSTACK(comp);
c4e521b6
BVA		 1710 scsi_qla_host_t *vha = qp->vha;
1711 struct qla_hw_data *ha = vha->hw;
c81ef0ed 1712 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 1713 int rval;
f45bca8c
QT		 1714 bool ret_cmd;
1715 uint32_t ratov_j;
c4e521b6 1716
2494c286
BVA		 1717 lockdep_assert_held(qp->qp_lock_ptr);
1718
f45bca8c
QT		 1719 if (qla2x00_chip_is_down(vha)) {
1720 sp->done(sp, res);
219d27d7 1721 return;
f45bca8c 1722 }
219d27d7
BVA		 1723
1724 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1725 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1726 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1727 !qla2x00_isp_reg_stat(ha))) {
f45bca8c
QT		 1728 if (sp->comp) {
1729 sp->done(sp, res);
1730 return;
1731 }
1732
219d27d7 1733 sp->comp = &comp;
219d27d7
BVA		 1734 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1735
f45bca8c
QT		 1736 rval = ha->isp_ops->abort_command(sp);
1737 /* Wait for command completion. */
1738 ret_cmd = false;
1739 ratov_j = ha->r_a_tov/10 * 4 * 1000;
1740 ratov_j = msecs_to_jiffies(ratov_j);
219d27d7
BVA		 1741 switch (rval) {
1742 case QLA_SUCCESS:
f45bca8c
QT		 1743 if (wait_for_completion_timeout(&comp, ratov_j)) {
1744 ql_dbg(ql_dbg_taskm, vha, 0xffff,
1745 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n",
1746 __func__, ha->r_a_tov/10);
1747 ret_cmd = true;
1748 }
1749 /* else FW return SP to driver */
219d27d7 1750 break;
f45bca8c
QT		 1751 default:
1752 ret_cmd = true;
219d27d7 1753 break;
c4e521b6 1754 }
219d27d7
BVA		 1755
1756 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
c81ef0ed 1757 if (ret_cmd && blk_mq_request_started(cmd->request))
f45bca8c
QT		 1758 sp->done(sp, res);
1759 } else {
1760 sp->done(sp, res);
c4e521b6 1761 }
c4e521b6
BVA		 1762}
1763
c81ef0ed
BVA		 1764/*
1765 * The caller must ensure that no completion interrupts will happen
1766 * while this function is in progress.
1767 */
bbead493
QT		 1768static void
1769__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1770{
eb023220 1771 int cnt;
df4bf0bb
AV		 1772 unsigned long flags;
1773 srb_t *sp;
bbead493 1774 scsi_qla_host_t *vha = qp->vha;
e315cd28 1775 struct qla_hw_data *ha = vha->hw;
73208dfd 1776 struct req_que *req;
c5419e26
QT		 1777 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1778 struct qla_tgt_cmd *cmd;
c0cb4496 1779
6a2cf8d3
BK		 1780 if (!ha->req_q_map)
1781 return;
bbead493
QT		 1782 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1783 req = qp->req;
1784 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1785 sp = req->outstanding_cmds[cnt];
1786 if (sp) {
6b0431d6
QT		 1787 switch (sp->cmd_type) {
1788 case TYPE_SRB:
c4e521b6 1789 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1790 break;
1791 case TYPE_TGT_CMD:
bbead493
QT		 1792 if (!vha->hw->tgt.tgt_ops || !tgt ||
1793 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1794 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1795 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1796 vha->dpc_flags);
bbead493 1797 continue;
c733ab35 1798 }
bbead493 1799 cmd = (struct qla_tgt_cmd *)sp;
aefed3e5 1800 cmd->aborted = 1;
585def9b
QT		 1801 break;
1802 case TYPE_TGT_TMCMD:
aefed3e5 1803 /* Skip task management functions. */
585def9b
QT		 1804 break;
1805 default:
1806 break;
73208dfd 1807 }
f45bca8c 1808 req->outstanding_cmds[cnt] = NULL;
df4bf0bb
AV		 1809 }
1810 }
bbead493
QT		 1811 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1812}
1813
c81ef0ed
BVA		 1814/*
1815 * The caller must ensure that no completion interrupts will happen
1816 * while this function is in progress.
1817 */
bbead493
QT		 1818void
1819qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1820{
1821 int que;
1822 struct qla_hw_data *ha = vha->hw;
1823
26a77799
AV		 1824 /* Continue only if initialization complete. */
1825 if (!ha->base_qpair)
1826 return;
bbead493
QT		 1827 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1828
26a77799
AV		 1829 if (!ha->queue_pair_map)
1830 return;
bbead493
QT		 1831 for (que = 0; que < ha->max_qpairs; que++) {
1832 if (!ha->queue_pair_map[que])
1833 continue;
1834
1835 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1836 }
df4bf0bb
AV		 1837}
1838
f4f051eb
AV		 1839static int
1840qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1841{
bdf79621 1842 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1843
19a7b4ae 1844 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1845 return -ENXIO;
bdf79621 1846
19a7b4ae 1847 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1848
f4f051eb
AV		 1849 return 0;
1850}
1da177e4 1851
f4f051eb
AV		 1852static int
1853qla2xxx_slave_configure(struct scsi_device *sdev)
1854{
e315cd28 1855 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1856 struct req_que *req = vha->req;
8482e118 1857
9e522cd8
AE		 1858 if (IS_T10_PI_CAPABLE(vha->hw))
1859 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1860
db5ed4df 1861 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1862 return 0;
1863}
1da177e4 1864
f4f051eb
AV		 1865static void
1866qla2xxx_slave_destroy(struct scsi_device *sdev)
1867{
1868 sdev->hostdata = NULL;
1da177e4
LT		 1869}
1870
1871/**
1872 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1873 * @ha: HA context
1874 *
1875 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1876 * supported addressing method.
1877 */
1878static void
53303c42 1879qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1880{
7524f9b9 1881 /* Assume a 32bit DMA mask. */
1da177e4 1882 ha->flags.enable_64bit_addressing = 0;
1da177e4 1883
6a35528a 1884 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1885 /* Any upper-dword bits set? */
1886 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1887 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1888 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1889 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1890 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1891 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1892 return;
1da177e4 1893 }
1da177e4 1894 }
7524f9b9 1895
284901a9
YH		 1896 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1897 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1898}
1899
fd34f556 1900static void
e315cd28 1901qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1902{
1903 unsigned long flags = 0;
1904 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1905
1906 spin_lock_irqsave(&ha->hardware_lock, flags);
1907 ha->interrupts_on = 1;
1908 /* enable risc and host interrupts */
04474d3a
BVA		 1909 wrt_reg_word(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1910 rd_reg_word(&reg->ictrl);
fd34f556
AV		 1911 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1912
1913}
1914
1915static void
e315cd28 1916qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1917{
1918 unsigned long flags = 0;
1919 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1920
1921 spin_lock_irqsave(&ha->hardware_lock, flags);
1922 ha->interrupts_on = 0;
1923 /* disable risc and host interrupts */
04474d3a
BVA		 1924 wrt_reg_word(&reg->ictrl, 0);
1925 rd_reg_word(&reg->ictrl);
fd34f556
AV		 1926 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1927}
1928
1929static void
e315cd28 1930qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1931{
1932 unsigned long flags = 0;
1933 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1934
1935 spin_lock_irqsave(&ha->hardware_lock, flags);
1936 ha->interrupts_on = 1;
04474d3a
BVA		 1937 wrt_reg_dword(&reg->ictrl, ICRX_EN_RISC_INT);
1938 rd_reg_dword(&reg->ictrl);
fd34f556
AV		 1939 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1940}
1941
1942static void
e315cd28 1943qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1944{
1945 unsigned long flags = 0;
1946 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1947
124f85e6
AV		 1948 if (IS_NOPOLLING_TYPE(ha))
1949 return;
fd34f556
AV		 1950 spin_lock_irqsave(&ha->hardware_lock, flags);
1951 ha->interrupts_on = 0;
04474d3a
BVA		 1952 wrt_reg_dword(&reg->ictrl, 0);
1953 rd_reg_dword(&reg->ictrl);
fd34f556
AV		 1954 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1955}
1956
706f457d
GM		 1957static int
1958qla2x00_iospace_config(struct qla_hw_data *ha)
1959{
1960 resource_size_t pio;
1961 uint16_t msix;
706f457d 1962
706f457d
GM		 1963 if (pci_request_selected_regions(ha->pdev, ha->bars,
1964 QLA2XXX_DRIVER_NAME)) {
1965 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1966 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1967 pci_name(ha->pdev));
1968 goto iospace_error_exit;
1969 }
1970 if (!(ha->bars & 1))
1971 goto skip_pio;
1972
1973 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1974 pio = pci_resource_start(ha->pdev, 0);
1975 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1976 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1977 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1978 "Invalid pci I/O region size (%s).\n",
1979 pci_name(ha->pdev));
1980 pio = 0;
1981 }
1982 } else {
1983 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1984 "Region #0 no a PIO resource (%s).\n",
1985 pci_name(ha->pdev));
1986 pio = 0;
1987 }
1988 ha->pio_address = pio;
1989 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1990 "PIO address=%llu.\n",
1991 (unsigned long long)ha->pio_address);
1992
1993skip_pio:
1994 /* Use MMIO operations for all accesses. */
1995 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1996 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1997 "Region #1 not an MMIO resource (%s), aborting.\n",
1998 pci_name(ha->pdev));
1999 goto iospace_error_exit;
2000 }
2001 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2002 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2003 "Invalid PCI mem region size (%s), aborting.\n",
2004 pci_name(ha->pdev));
2005 goto iospace_error_exit;
2006 }
2007
2008 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2009 if (!ha->iobase) {
2010 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2011 "Cannot remap MMIO (%s), aborting.\n",
2012 pci_name(ha->pdev));
2013 goto iospace_error_exit;
2014 }
2015
2016 /* Determine queue resources */
2017 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2018 ha->msix_count = QLA_BASE_VECTORS;
dffa1145
SK		 2019
2020 /* Check if FW supports MQ or not */
2021 if (!(ha->fw_attributes & BIT_6))
2022 goto mqiobase_exit;
2023
c38d1baf
HM		 2024 if (!ql2xmqsupport || !ql2xnvmeenable ||
2025 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2026 goto mqiobase_exit;
2027
2028 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2029 pci_resource_len(ha->pdev, 3));
2030 if (ha->mqiobase) {
2031 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2032 "MQIO Base=%p.\n", ha->mqiobase);
2033 /* Read MSIX vector size of the board */
2034 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2035 ha->msix_count = msix + 1;
706f457d 2036 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2037 /* MB interrupt uses 1 vector */
2038 ha->max_req_queues = ha->msix_count - 1;
2039 ha->max_rsp_queues = ha->max_req_queues;
2040 /* Queue pairs is the max value minus the base queue pair */
2041 ha->max_qpairs = ha->max_rsp_queues - 1;
2042 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2043 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2044
706f457d 2045 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2046 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2047 } else
2048 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2049 "BAR 3 not enabled.\n");
2050
2051mqiobase_exit:
706f457d 2052 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2053 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2054 return (0);
2055
2056iospace_error_exit:
2057 return (-ENOMEM);
2058}
2059
2060
6246b8a1
GM		 2061static int
2062qla83xx_iospace_config(struct qla_hw_data *ha)
2063{
2064 uint16_t msix;
6246b8a1
GM		 2065
2066 if (pci_request_selected_regions(ha->pdev, ha->bars,
2067 QLA2XXX_DRIVER_NAME)) {
2068 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2069 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2070 pci_name(ha->pdev));
2071
2072 goto iospace_error_exit;
2073 }
2074
2075 /* Use MMIO operations for all accesses. */
2076 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2077 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2078 "Invalid pci I/O region size (%s).\n",
2079 pci_name(ha->pdev));
2080 goto iospace_error_exit;
2081 }
2082 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2083 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2084 "Invalid PCI mem region size (%s), aborting\n",
2085 pci_name(ha->pdev));
2086 goto iospace_error_exit;
2087 }
2088
2089 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2090 if (!ha->iobase) {
2091 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2092 "Cannot remap MMIO (%s), aborting.\n",
2093 pci_name(ha->pdev));
2094 goto iospace_error_exit;
2095 }
2096
2097 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2098 /* 83XX 26XX always use MQ type access for queues
2099 * - mbar 2, a.k.a region 4 */
2100 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2101 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2102 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2103 pci_resource_len(ha->pdev, 4));
2104
2105 if (!ha->mqiobase) {
2106 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2107 "BAR2/region4 not enabled\n");
2108 goto mqiobase_exit;
2109 }
2110
2111 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2112 pci_resource_len(ha->pdev, 2));
2113 if (ha->msixbase) {
2114 /* Read MSIX vector size of the board */
2115 pci_read_config_word(ha->pdev,
2116 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2117 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2118 /*
2119 * By default, driver uses at least two msix vectors
2120 * (default & rspq)
2121 */
c38d1baf 2122 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2123 /* MB interrupt uses 1 vector */
2124 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2125
2126 /* ATIOQ needs 1 vector. That's 1 less QPair */
2127 if (QLA_TGT_MODE_ENABLED())
2128 ha->max_req_queues--;
2129
d0d2c68b
MH		 2130 ha->max_rsp_queues = ha->max_req_queues;
2131
d7459527
MH		 2132 /* Queue pairs is the max value minus
2133 * the base queue pair */
2134 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2135 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2136 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2137 }
2138 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2139 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2140 } else
2141 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2142 "BAR 1 not enabled.\n");
2143
2144mqiobase_exit:
6246b8a1 2145 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2146 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2147 return 0;
2148
2149iospace_error_exit:
2150 return -ENOMEM;
2151}
2152
fd34f556
AV		 2153static struct isp_operations qla2100_isp_ops = {
2154 .pci_config = qla2100_pci_config,
2155 .reset_chip = qla2x00_reset_chip,
2156 .chip_diag = qla2x00_chip_diag,
2157 .config_rings = qla2x00_config_rings,
2158 .reset_adapter = qla2x00_reset_adapter,
2159 .nvram_config = qla2x00_nvram_config,
2160 .update_fw_options = qla2x00_update_fw_options,
2161 .load_risc = qla2x00_load_risc,
2162 .pci_info_str = qla2x00_pci_info_str,
2163 .fw_version_str = qla2x00_fw_version_str,
2164 .intr_handler = qla2100_intr_handler,
2165 .enable_intrs = qla2x00_enable_intrs,
2166 .disable_intrs = qla2x00_disable_intrs,
2167 .abort_command = qla2x00_abort_command,
523ec773
AV		 2168 .target_reset = qla2x00_abort_target,
2169 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2170 .fabric_login = qla2x00_login_fabric,
2171 .fabric_logout = qla2x00_fabric_logout,
2172 .calc_req_entries = qla2x00_calc_iocbs_32,
2173 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2174 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2175 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2176 .read_nvram = qla2x00_read_nvram_data,
2177 .write_nvram = qla2x00_write_nvram_data,
2178 .fw_dump = qla2100_fw_dump,
2179 .beacon_on = NULL,
2180 .beacon_off = NULL,
2181 .beacon_blink = NULL,
2182 .read_optrom = qla2x00_read_optrom_data,
2183 .write_optrom = qla2x00_write_optrom_data,
2184 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2185 .start_scsi = qla2x00_start_scsi,
d7459527 2186 .start_scsi_mq = NULL,
a9083016 2187 .abort_isp = qla2x00_abort_isp,
706f457d 2188 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2189 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2190};
2191
2192static struct isp_operations qla2300_isp_ops = {
2193 .pci_config = qla2300_pci_config,
2194 .reset_chip = qla2x00_reset_chip,
2195 .chip_diag = qla2x00_chip_diag,
2196 .config_rings = qla2x00_config_rings,
2197 .reset_adapter = qla2x00_reset_adapter,
2198 .nvram_config = qla2x00_nvram_config,
2199 .update_fw_options = qla2x00_update_fw_options,
2200 .load_risc = qla2x00_load_risc,
2201 .pci_info_str = qla2x00_pci_info_str,
2202 .fw_version_str = qla2x00_fw_version_str,
2203 .intr_handler = qla2300_intr_handler,
2204 .enable_intrs = qla2x00_enable_intrs,
2205 .disable_intrs = qla2x00_disable_intrs,
2206 .abort_command = qla2x00_abort_command,
523ec773
AV		 2207 .target_reset = qla2x00_abort_target,
2208 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2209 .fabric_login = qla2x00_login_fabric,
2210 .fabric_logout = qla2x00_fabric_logout,
2211 .calc_req_entries = qla2x00_calc_iocbs_32,
2212 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2213 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2214 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2215 .read_nvram = qla2x00_read_nvram_data,
2216 .write_nvram = qla2x00_write_nvram_data,
2217 .fw_dump = qla2300_fw_dump,
2218 .beacon_on = qla2x00_beacon_on,
2219 .beacon_off = qla2x00_beacon_off,
2220 .beacon_blink = qla2x00_beacon_blink,
2221 .read_optrom = qla2x00_read_optrom_data,
2222 .write_optrom = qla2x00_write_optrom_data,
2223 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2224 .start_scsi = qla2x00_start_scsi,
d7459527 2225 .start_scsi_mq = NULL,
a9083016 2226 .abort_isp = qla2x00_abort_isp,
7ec0effd 2227 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2228 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2229};
2230
2231static struct isp_operations qla24xx_isp_ops = {
2232 .pci_config = qla24xx_pci_config,
2233 .reset_chip = qla24xx_reset_chip,
2234 .chip_diag = qla24xx_chip_diag,
2235 .config_rings = qla24xx_config_rings,
2236 .reset_adapter = qla24xx_reset_adapter,
2237 .nvram_config = qla24xx_nvram_config,
2238 .update_fw_options = qla24xx_update_fw_options,
2239 .load_risc = qla24xx_load_risc,
2240 .pci_info_str = qla24xx_pci_info_str,
2241 .fw_version_str = qla24xx_fw_version_str,
2242 .intr_handler = qla24xx_intr_handler,
2243 .enable_intrs = qla24xx_enable_intrs,
2244 .disable_intrs = qla24xx_disable_intrs,
2245 .abort_command = qla24xx_abort_command,
523ec773
AV		 2246 .target_reset = qla24xx_abort_target,
2247 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2248 .fabric_login = qla24xx_login_fabric,
2249 .fabric_logout = qla24xx_fabric_logout,
2250 .calc_req_entries = NULL,
2251 .build_iocbs = NULL,
2252 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2253 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2254 .read_nvram = qla24xx_read_nvram_data,
2255 .write_nvram = qla24xx_write_nvram_data,
2256 .fw_dump = qla24xx_fw_dump,
2257 .beacon_on = qla24xx_beacon_on,
2258 .beacon_off = qla24xx_beacon_off,
2259 .beacon_blink = qla24xx_beacon_blink,
2260 .read_optrom = qla24xx_read_optrom_data,
2261 .write_optrom = qla24xx_write_optrom_data,
2262 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2263 .start_scsi = qla24xx_start_scsi,
d7459527 2264 .start_scsi_mq = NULL,
a9083016 2265 .abort_isp = qla2x00_abort_isp,
7ec0effd 2266 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2267 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2268};
2269
c3a2f0df
AV		 2270static struct isp_operations qla25xx_isp_ops = {
2271 .pci_config = qla25xx_pci_config,
2272 .reset_chip = qla24xx_reset_chip,
2273 .chip_diag = qla24xx_chip_diag,
2274 .config_rings = qla24xx_config_rings,
2275 .reset_adapter = qla24xx_reset_adapter,
2276 .nvram_config = qla24xx_nvram_config,
2277 .update_fw_options = qla24xx_update_fw_options,
2278 .load_risc = qla24xx_load_risc,
2279 .pci_info_str = qla24xx_pci_info_str,
2280 .fw_version_str = qla24xx_fw_version_str,
2281 .intr_handler = qla24xx_intr_handler,
2282 .enable_intrs = qla24xx_enable_intrs,
2283 .disable_intrs = qla24xx_disable_intrs,
2284 .abort_command = qla24xx_abort_command,
523ec773
AV		 2285 .target_reset = qla24xx_abort_target,
2286 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2287 .fabric_login = qla24xx_login_fabric,
2288 .fabric_logout = qla24xx_fabric_logout,
2289 .calc_req_entries = NULL,
2290 .build_iocbs = NULL,
2291 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2292 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2293 .read_nvram = qla25xx_read_nvram_data,
2294 .write_nvram = qla25xx_write_nvram_data,
2295 .fw_dump = qla25xx_fw_dump,
2296 .beacon_on = qla24xx_beacon_on,
2297 .beacon_off = qla24xx_beacon_off,
2298 .beacon_blink = qla24xx_beacon_blink,
338c9161 2299 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2300 .write_optrom = qla24xx_write_optrom_data,
2301 .get_flash_version = qla24xx_get_flash_version,
bad75002 2302 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2303 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2304 .abort_isp = qla2x00_abort_isp,
7ec0effd 2305 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2306 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2307};
2308
3a03eb79
AV		 2309static struct isp_operations qla81xx_isp_ops = {
2310 .pci_config = qla25xx_pci_config,
2311 .reset_chip = qla24xx_reset_chip,
2312 .chip_diag = qla24xx_chip_diag,
2313 .config_rings = qla24xx_config_rings,
2314 .reset_adapter = qla24xx_reset_adapter,
2315 .nvram_config = qla81xx_nvram_config,
37efd51f 2316 .update_fw_options = qla24xx_update_fw_options,
eaac30be 2317 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2318 .pci_info_str = qla24xx_pci_info_str,
2319 .fw_version_str = qla24xx_fw_version_str,
2320 .intr_handler = qla24xx_intr_handler,
2321 .enable_intrs = qla24xx_enable_intrs,
2322 .disable_intrs = qla24xx_disable_intrs,
2323 .abort_command = qla24xx_abort_command,
2324 .target_reset = qla24xx_abort_target,
2325 .lun_reset = qla24xx_lun_reset,
2326 .fabric_login = qla24xx_login_fabric,
2327 .fabric_logout = qla24xx_fabric_logout,
2328 .calc_req_entries = NULL,
2329 .build_iocbs = NULL,
2330 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2331 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2332 .read_nvram = NULL,
2333 .write_nvram = NULL,
3a03eb79
AV		 2334 .fw_dump = qla81xx_fw_dump,
2335 .beacon_on = qla24xx_beacon_on,
2336 .beacon_off = qla24xx_beacon_off,
6246b8a1 2337 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2338 .read_optrom = qla25xx_read_optrom_data,
2339 .write_optrom = qla24xx_write_optrom_data,
2340 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2341 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2342 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2343 .abort_isp = qla2x00_abort_isp,
7ec0effd 2344 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2345 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2346};
2347
2348static struct isp_operations qla82xx_isp_ops = {
2349 .pci_config = qla82xx_pci_config,
2350 .reset_chip = qla82xx_reset_chip,
2351 .chip_diag = qla24xx_chip_diag,
2352 .config_rings = qla82xx_config_rings,
2353 .reset_adapter = qla24xx_reset_adapter,
2354 .nvram_config = qla81xx_nvram_config,
2355 .update_fw_options = qla24xx_update_fw_options,
2356 .load_risc = qla82xx_load_risc,
9d55ca66 2357 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2358 .fw_version_str = qla24xx_fw_version_str,
2359 .intr_handler = qla82xx_intr_handler,
2360 .enable_intrs = qla82xx_enable_intrs,
2361 .disable_intrs = qla82xx_disable_intrs,
2362 .abort_command = qla24xx_abort_command,
2363 .target_reset = qla24xx_abort_target,
2364 .lun_reset = qla24xx_lun_reset,
2365 .fabric_login = qla24xx_login_fabric,
2366 .fabric_logout = qla24xx_fabric_logout,
2367 .calc_req_entries = NULL,
2368 .build_iocbs = NULL,
2369 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2370 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2371 .read_nvram = qla24xx_read_nvram_data,
2372 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2373 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2374 .beacon_on = qla82xx_beacon_on,
2375 .beacon_off = qla82xx_beacon_off,
2376 .beacon_blink = NULL,
a9083016
GM		 2377 .read_optrom = qla82xx_read_optrom_data,
2378 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2379 .get_flash_version = qla82xx_get_flash_version,
a9083016 2380 .start_scsi = qla82xx_start_scsi,
d7459527 2381 .start_scsi_mq = NULL,
a9083016 2382 .abort_isp = qla82xx_abort_isp,
706f457d 2383 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2384 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2385};
2386
7ec0effd
AD		 2387static struct isp_operations qla8044_isp_ops = {
2388 .pci_config = qla82xx_pci_config,
2389 .reset_chip = qla82xx_reset_chip,
2390 .chip_diag = qla24xx_chip_diag,
2391 .config_rings = qla82xx_config_rings,
2392 .reset_adapter = qla24xx_reset_adapter,
2393 .nvram_config = qla81xx_nvram_config,
2394 .update_fw_options = qla24xx_update_fw_options,
2395 .load_risc = qla82xx_load_risc,
2396 .pci_info_str = qla24xx_pci_info_str,
2397 .fw_version_str = qla24xx_fw_version_str,
2398 .intr_handler = qla8044_intr_handler,
2399 .enable_intrs = qla82xx_enable_intrs,
2400 .disable_intrs = qla82xx_disable_intrs,
2401 .abort_command = qla24xx_abort_command,
2402 .target_reset = qla24xx_abort_target,
2403 .lun_reset = qla24xx_lun_reset,
2404 .fabric_login = qla24xx_login_fabric,
2405 .fabric_logout = qla24xx_fabric_logout,
2406 .calc_req_entries = NULL,
2407 .build_iocbs = NULL,
2408 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2409 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2410 .read_nvram = NULL,
2411 .write_nvram = NULL,
a1b23c5a 2412 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2413 .beacon_on = qla82xx_beacon_on,
2414 .beacon_off = qla82xx_beacon_off,
2415 .beacon_blink = NULL,
888e639d 2416 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2417 .write_optrom = qla8044_write_optrom_data,
2418 .get_flash_version = qla82xx_get_flash_version,
2419 .start_scsi = qla82xx_start_scsi,
d7459527 2420 .start_scsi_mq = NULL,
7ec0effd
AD		 2421 .abort_isp = qla8044_abort_isp,
2422 .iospace_config = qla82xx_iospace_config,
2423 .initialize_adapter = qla2x00_initialize_adapter,
2424};
2425
6246b8a1
GM		 2426static struct isp_operations qla83xx_isp_ops = {
2427 .pci_config = qla25xx_pci_config,
2428 .reset_chip = qla24xx_reset_chip,
2429 .chip_diag = qla24xx_chip_diag,
2430 .config_rings = qla24xx_config_rings,
2431 .reset_adapter = qla24xx_reset_adapter,
2432 .nvram_config = qla81xx_nvram_config,
37efd51f 2433 .update_fw_options = qla24xx_update_fw_options,
6246b8a1
GM		 2434 .load_risc = qla81xx_load_risc,
2435 .pci_info_str = qla24xx_pci_info_str,
2436 .fw_version_str = qla24xx_fw_version_str,
2437 .intr_handler = qla24xx_intr_handler,
2438 .enable_intrs = qla24xx_enable_intrs,
2439 .disable_intrs = qla24xx_disable_intrs,
2440 .abort_command = qla24xx_abort_command,
2441 .target_reset = qla24xx_abort_target,
2442 .lun_reset = qla24xx_lun_reset,
2443 .fabric_login = qla24xx_login_fabric,
2444 .fabric_logout = qla24xx_fabric_logout,
2445 .calc_req_entries = NULL,
2446 .build_iocbs = NULL,
2447 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2448 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2449 .read_nvram = NULL,
2450 .write_nvram = NULL,
2451 .fw_dump = qla83xx_fw_dump,
2452 .beacon_on = qla24xx_beacon_on,
2453 .beacon_off = qla24xx_beacon_off,
2454 .beacon_blink = qla83xx_beacon_blink,
2455 .read_optrom = qla25xx_read_optrom_data,
2456 .write_optrom = qla24xx_write_optrom_data,
2457 .get_flash_version = qla24xx_get_flash_version,
2458 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2459 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2460 .abort_isp = qla2x00_abort_isp,
2461 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2462 .initialize_adapter = qla2x00_initialize_adapter,
2463};
2464
2465static struct isp_operations qlafx00_isp_ops = {
2466 .pci_config = qlafx00_pci_config,
2467 .reset_chip = qlafx00_soft_reset,
2468 .chip_diag = qlafx00_chip_diag,
2469 .config_rings = qlafx00_config_rings,
2470 .reset_adapter = qlafx00_soft_reset,
2471 .nvram_config = NULL,
2472 .update_fw_options = NULL,
2473 .load_risc = NULL,
2474 .pci_info_str = qlafx00_pci_info_str,
2475 .fw_version_str = qlafx00_fw_version_str,
2476 .intr_handler = qlafx00_intr_handler,
2477 .enable_intrs = qlafx00_enable_intrs,
2478 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2479 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2480 .target_reset = qlafx00_abort_target,
2481 .lun_reset = qlafx00_lun_reset,
2482 .fabric_login = NULL,
2483 .fabric_logout = NULL,
2484 .calc_req_entries = NULL,
2485 .build_iocbs = NULL,
2486 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2487 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2488 .read_nvram = qla24xx_read_nvram_data,
2489 .write_nvram = qla24xx_write_nvram_data,
2490 .fw_dump = NULL,
2491 .beacon_on = qla24xx_beacon_on,
2492 .beacon_off = qla24xx_beacon_off,
2493 .beacon_blink = NULL,
2494 .read_optrom = qla24xx_read_optrom_data,
2495 .write_optrom = qla24xx_write_optrom_data,
2496 .get_flash_version = qla24xx_get_flash_version,
2497 .start_scsi = qlafx00_start_scsi,
d7459527 2498 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2499 .abort_isp = qlafx00_abort_isp,
2500 .iospace_config = qlafx00_iospace_config,
2501 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2502};
2503
f73cb695
CD		 2504static struct isp_operations qla27xx_isp_ops = {
2505 .pci_config = qla25xx_pci_config,
2506 .reset_chip = qla24xx_reset_chip,
2507 .chip_diag = qla24xx_chip_diag,
2508 .config_rings = qla24xx_config_rings,
2509 .reset_adapter = qla24xx_reset_adapter,
2510 .nvram_config = qla81xx_nvram_config,
a36f1443 2511 .update_fw_options = qla24xx_update_fw_options,
f73cb695
CD		 2512 .load_risc = qla81xx_load_risc,
2513 .pci_info_str = qla24xx_pci_info_str,
2514 .fw_version_str = qla24xx_fw_version_str,
2515 .intr_handler = qla24xx_intr_handler,
2516 .enable_intrs = qla24xx_enable_intrs,
2517 .disable_intrs = qla24xx_disable_intrs,
2518 .abort_command = qla24xx_abort_command,
2519 .target_reset = qla24xx_abort_target,
2520 .lun_reset = qla24xx_lun_reset,
2521 .fabric_login = qla24xx_login_fabric,
2522 .fabric_logout = qla24xx_fabric_logout,
2523 .calc_req_entries = NULL,
2524 .build_iocbs = NULL,
2525 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2526 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2527 .read_nvram = NULL,
2528 .write_nvram = NULL,
2529 .fw_dump = qla27xx_fwdump,
cbb01c2f 2530 .mpi_fw_dump = qla27xx_mpi_fwdump,
f73cb695
CD		 2531 .beacon_on = qla24xx_beacon_on,
2532 .beacon_off = qla24xx_beacon_off,
2533 .beacon_blink = qla83xx_beacon_blink,
2534 .read_optrom = qla25xx_read_optrom_data,
2535 .write_optrom = qla24xx_write_optrom_data,
2536 .get_flash_version = qla24xx_get_flash_version,
2537 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2538 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2539 .abort_isp = qla2x00_abort_isp,
2540 .iospace_config = qla83xx_iospace_config,
2541 .initialize_adapter = qla2x00_initialize_adapter,
2542};
2543
ea5b6382 2544static inline void
e315cd28 2545qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2546{
2547 ha->device_type = DT_EXTENDED_IDS;
2548 switch (ha->pdev->device) {
2549 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2550 ha->isp_type |= DT_ISP2100;
ea5b6382 2551 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2552 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2553 break;
2554 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2555 ha->isp_type |= DT_ISP2200;
ea5b6382 2556 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2557 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2558 break;
2559 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2560 ha->isp_type |= DT_ISP2300;
4a59f71d 2561 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2562 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2563 break;
2564 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2565 ha->isp_type |= DT_ISP2312;
4a59f71d 2566 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2567 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2568 break;
2569 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2570 ha->isp_type |= DT_ISP2322;
4a59f71d 2571 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2572 if (ha->pdev->subsystem_vendor == 0x1028 &&
2573 ha->pdev->subsystem_device == 0x0170)
2574 ha->device_type |= DT_OEM_001;
441d1072 2575 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2576 break;
2577 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2578 ha->isp_type |= DT_ISP6312;
441d1072 2579 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2580 break;
2581 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2582 ha->isp_type |= DT_ISP6322;
441d1072 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2584 break;
2585 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2586 ha->isp_type |= DT_ISP2422;
4a59f71d 2587 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2588 ha->device_type |= DT_FWI2;
c76f2c01 2589 ha->device_type |= DT_IIDMA;
441d1072 2590 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2591 break;
2592 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2593 ha->isp_type |= DT_ISP2432;
4a59f71d 2594 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2595 ha->device_type |= DT_FWI2;
c76f2c01 2596 ha->device_type |= DT_IIDMA;
441d1072 2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2598 break;
4d4df193 2599 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2600 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2601 ha->device_type |= DT_ZIO_SUPPORTED;
2602 ha->device_type |= DT_FWI2;
2603 ha->device_type |= DT_IIDMA;
2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2605 break;
044cc6c8 2606 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2607 ha->isp_type |= DT_ISP5422;
e428924c 2608 ha->device_type |= DT_FWI2;
441d1072 2609 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2610 break;
044cc6c8 2611 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2612 ha->isp_type |= DT_ISP5432;
e428924c 2613 ha->device_type |= DT_FWI2;
441d1072 2614 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2615 break;
c3a2f0df 2616 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2617 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2618 ha->device_type |= DT_ZIO_SUPPORTED;
2619 ha->device_type |= DT_FWI2;
2620 ha->device_type |= DT_IIDMA;
441d1072 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2622 break;
3a03eb79 2623 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2624 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2625 ha->device_type |= DT_ZIO_SUPPORTED;
2626 ha->device_type |= DT_FWI2;
2627 ha->device_type |= DT_IIDMA;
2628 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2629 break;
a9083016 2630 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2631 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2632 ha->device_type |= DT_ZIO_SUPPORTED;
2633 ha->device_type |= DT_FWI2;
2634 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2635 /* Initialize 82XX ISP flags */
2636 qla82xx_init_flags(ha);
2637 break;
7ec0effd 2638 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2639 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2640 ha->device_type |= DT_ZIO_SUPPORTED;
2641 ha->device_type |= DT_FWI2;
2642 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2643 /* Initialize 82XX ISP flags */
2644 qla82xx_init_flags(ha);
2645 break;
6246b8a1 2646 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2647 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2648 ha->device_type |= DT_ZIO_SUPPORTED;
2649 ha->device_type |= DT_FWI2;
2650 ha->device_type |= DT_IIDMA;
2651 ha->device_type |= DT_T10_PI;
2652 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2653 break;
2654 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2655 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2656 ha->device_type |= DT_ZIO_SUPPORTED;
2657 ha->device_type |= DT_FWI2;
2658 ha->device_type |= DT_IIDMA;
2659 ha->device_type |= DT_T10_PI;
2660 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2661 break;
8ae6d9c7 2662 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2663 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2664 break;
f73cb695 2665 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2666 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2667 ha->device_type |= DT_ZIO_SUPPORTED;
2668 ha->device_type |= DT_FWI2;
2669 ha->device_type |= DT_IIDMA;
8ce3f570 2670 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2671 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2672 break;
2c5bbbb2 2673 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2674 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2675 ha->device_type |= DT_ZIO_SUPPORTED;
2676 ha->device_type |= DT_FWI2;
2677 ha->device_type |= DT_IIDMA;
8ce3f570 2678 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2679 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2680 break;
2b48992f 2681 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2682 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2683 ha->device_type |= DT_ZIO_SUPPORTED;
2684 ha->device_type |= DT_FWI2;
2685 ha->device_type |= DT_IIDMA;
8ce3f570 2686 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2687 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2688 break;
ecc89f25
JC		 2689 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2690 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2691 ha->isp_type |= DT_ISP2081;
2692 ha->device_type |= DT_ZIO_SUPPORTED;
2693 ha->device_type |= DT_FWI2;
2694 ha->device_type |= DT_IIDMA;
2695 ha->device_type |= DT_T10_PI;
2696 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2697 break;
2698 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2699 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2700 ha->isp_type |= DT_ISP2281;
2701 ha->device_type |= DT_ZIO_SUPPORTED;
2702 ha->device_type |= DT_FWI2;
2703 ha->device_type |= DT_IIDMA;
2704 ha->device_type |= DT_T10_PI;
2705 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2706 break;
ea5b6382 2707 }
e5b68a61 2708
a9083016 2709 if (IS_QLA82XX(ha))
43a9c38b 2710 ha->port_no = ha->portnum & 1;
f73cb695 2711 else {
a9083016
GM		 2712 /* Get adapter physical port no from interrupt pin register. */
2713 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2714 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2715 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2716 ha->port_no--;
2717 else
2718 ha->port_no = !(ha->port_no & 1);
2719 }
a9083016 2720
7c3df132 2721 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2722 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2723 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2724}
2725
1e99e33a
AV		 2726static void
2727qla2xxx_scan_start(struct Scsi_Host *shost)
2728{
e315cd28 2729 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2730
cbc8eb67
AV		 2731 if (vha->hw->flags.running_gold_fw)
2732 return;
2733
e315cd28
AC		 2734 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2735 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2736 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2737 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2738}
2739
2740static int
2741qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2742{
e315cd28 2743 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2744
a5dd506e
BK		 2745 if (test_bit(UNLOADING, &vha->dpc_flags))
2746 return 1;
e315cd28 2747 if (!vha->host)
1e99e33a 2748 return 1;
e315cd28 2749 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2750 return 1;
2751
e315cd28 2752 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2753}
2754
ec7193e2
QT		 2755static void qla2x00_iocb_work_fn(struct work_struct *work)
2756{
2757 struct scsi_qla_host *vha = container_of(work,
2758 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2759 struct qla_hw_data *ha = vha->hw;
2760 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2761 int i = 2;
9b3e0f4d
QT		 2762 unsigned long flags;
2763
2764 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2765 return;
ec7193e2 2766
9b3e0f4d 2767 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2768 qla2x00_do_work(vha);
9b3e0f4d 2769 i--;
ec7193e2 2770 }
9b3e0f4d
QT		 2771
2772 spin_lock_irqsave(&vha->work_lock, flags);
2773 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2774 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2775}
2776
1da177e4
LT		 2777/*
2778 * PCI driver interface
2779 */
6f039790 2780static int
7ee61397 2781qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2782{
a1541d5a 2783 int ret = -ENODEV;
1da177e4 2784 struct Scsi_Host *host;
e315cd28
AC		 2785 scsi_qla_host_t *base_vha = NULL;
2786 struct qla_hw_data *ha;
29856e28 2787 char pci_info[30];
7d613ac6 2788 char fw_str[30], wq_name[30];
5433383e 2789 struct scsi_host_template *sht;
642ef983 2790 int bars, mem_only = 0;
e315cd28 2791 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2792 struct req_que *req = NULL;
2793 struct rsp_que *rsp = NULL;
5601236b 2794 int i;
d7459527 2795
285d0321 2796 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2797 sht = &qla2xxx_driver_template;
5433383e 2798 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2800 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2801 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2802 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2803 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2804 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2805 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2806 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2807 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2808 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2809 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2810 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2811 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2812 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2813 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2814 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2815 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2816 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2817 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2818 mem_only = 1;
7c3df132
SK		 2819 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2820 "Mem only adapter.\n");
285d0321 2821 }
7c3df132
SK		 2822 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2823 "Bars=%d.\n", bars);
285d0321 2824
09483916
BH		 2825 if (mem_only) {
2826 if (pci_enable_device_mem(pdev))
ddff7ed4 2827 return ret;
09483916
BH		 2828 } else {
2829 if (pci_enable_device(pdev))
ddff7ed4 2830 return ret;
09483916 2831 }
285d0321 2832
0927678f
JB		 2833 /* This may fail but that's ok */
2834 pci_enable_pcie_error_reporting(pdev);
285d0321 2835
e315cd28
AC		 2836 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2837 if (!ha) {
7c3df132
SK		 2838 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2839 "Unable to allocate memory for ha.\n");
ddff7ed4 2840 goto disable_device;
1da177e4 2841 }
7c3df132
SK		 2842 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2843 "Memory allocated for ha=%p.\n", ha);
e315cd28 2844 ha->pdev = pdev;
33e79977
QT		 2845 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2846 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2847 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2848 spin_lock_init(&ha->tgt.atio_lock);
2849
deeae7a6 2850 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2851
2852 /* Clear our data area */
285d0321 2853 ha->bars = bars;
09483916 2854 ha->mem_only = mem_only;
df4bf0bb 2855 spin_lock_init(&ha->hardware_lock);
339aa70e 2856 spin_lock_init(&ha->vport_slock);
a9b6f722 2857 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2858 mutex_init(&ha->optrom_mutex);
1da177e4 2859
ea5b6382
AV		 2860 /* Set ISP-type information. */
2861 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2862
2863 /* Set EEH reset type to fundamental if required by hba */
95676112 2864 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2865 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2866 pdev->needs_freset = 1;
ca79cf66 2867
cba1e47f
CD		 2868 ha->prev_topology = 0;
2869 ha->init_cb_size = sizeof(init_cb_t);
2870 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2871 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2872 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2873 atomic_set(&ha->num_pend_mbx_stage1, 0);
2874 atomic_set(&ha->num_pend_mbx_stage2, 0);
2875 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2876 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2877 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2878
abbd8870 2879 /* Assign ISP specific operations. */
1da177e4 2880 if (IS_QLA2100(ha)) {
642ef983 2881 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2882 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2883 req_length = REQUEST_ENTRY_CNT_2100;
2884 rsp_length = RESPONSE_ENTRY_CNT_2100;
2885 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2886 ha->gid_list_info_size = 4;
3a03eb79
AV		 2887 ha->flash_conf_off = ~0;
2888 ha->flash_data_off = ~0;
2889 ha->nvram_conf_off = ~0;
2890 ha->nvram_data_off = ~0;
fd34f556 2891 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2892 } else if (IS_QLA2200(ha)) {
642ef983 2893 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2894 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2895 req_length = REQUEST_ENTRY_CNT_2200;
2896 rsp_length = RESPONSE_ENTRY_CNT_2100;
2897 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2898 ha->gid_list_info_size = 4;
3a03eb79
AV		 2899 ha->flash_conf_off = ~0;
2900 ha->flash_data_off = ~0;
2901 ha->nvram_conf_off = ~0;
2902 ha->nvram_data_off = ~0;
fd34f556 2903 ha->isp_ops = &qla2100_isp_ops;
fca29703 2904 } else if (IS_QLA23XX(ha)) {
642ef983 2905 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2906 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2907 req_length = REQUEST_ENTRY_CNT_2200;
2908 rsp_length = RESPONSE_ENTRY_CNT_2300;
2909 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2910 ha->gid_list_info_size = 6;
854165f4
AV		 2911 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2912 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2913 ha->flash_conf_off = ~0;
2914 ha->flash_data_off = ~0;
2915 ha->nvram_conf_off = ~0;
2916 ha->nvram_data_off = ~0;
fd34f556 2917 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2918 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2919 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2920 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2921 req_length = REQUEST_ENTRY_CNT_24XX;
2922 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2923 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2924 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2925 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2926 ha->gid_list_info_size = 8;
854165f4 2927 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2928 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2929 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2930 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2931 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2932 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2933 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2934 } else if (IS_QLA25XX(ha)) {
642ef983 2935 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2936 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2937 req_length = REQUEST_ENTRY_CNT_24XX;
2938 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2939 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2940 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2941 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2942 ha->gid_list_info_size = 8;
2943 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2944 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2945 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2946 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2947 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2948 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2949 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2950 } else if (IS_QLA81XX(ha)) {
642ef983 2951 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2952 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2953 req_length = REQUEST_ENTRY_CNT_24XX;
2954 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2955 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2956 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2957 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2958 ha->gid_list_info_size = 8;
2959 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2960 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2961 ha->isp_ops = &qla81xx_isp_ops;
2962 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2963 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2964 ha->nvram_conf_off = ~0;
2965 ha->nvram_data_off = ~0;
a9083016 2966 } else if (IS_QLA82XX(ha)) {
642ef983 2967 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2968 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2969 req_length = REQUEST_ENTRY_CNT_82XX;
2970 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2971 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2972 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2973 ha->gid_list_info_size = 8;
2974 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2975 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2976 ha->isp_ops = &qla82xx_isp_ops;
2977 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2978 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2979 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2980 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2981 } else if (IS_QLA8044(ha)) {
2982 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2983 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2984 req_length = REQUEST_ENTRY_CNT_82XX;
2985 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2986 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2987 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2988 ha->gid_list_info_size = 8;
2989 ha->optrom_size = OPTROM_SIZE_83XX;
2990 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2991 ha->isp_ops = &qla8044_isp_ops;
2992 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2993 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2994 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2995 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2996 } else if (IS_QLA83XX(ha)) {
7d613ac6 2997 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2998 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2999 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 3000 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 3001 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 3002 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 3003 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3004 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3005 ha->gid_list_info_size = 8;
3006 ha->optrom_size = OPTROM_SIZE_83XX;
3007 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3008 ha->isp_ops = &qla83xx_isp_ops;
3009 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3010 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3011 ha->nvram_conf_off = ~0;
3012 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 3013 } else if (IS_QLAFX00(ha)) {
3014 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
3015 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
3016 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3017 req_length = REQUEST_ENTRY_CNT_FX00;
3018 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 3019 ha->isp_ops = &qlafx00_isp_ops;
3020 ha->port_down_retry_count = 30; /* default value */
3021 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3022 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 3023 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 3024 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 3025 ha->mr.host_info_resend = false;
3026 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3027 } else if (IS_QLA27XX(ha)) {
3028 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3029 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3030 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3031 req_length = REQUEST_ENTRY_CNT_83XX;
3032 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3033 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3034 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3035 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3036 ha->gid_list_info_size = 8;
3037 ha->optrom_size = OPTROM_SIZE_83XX;
3038 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3039 ha->isp_ops = &qla27xx_isp_ops;
3040 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3041 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3042 ha->nvram_conf_off = ~0;
3043 ha->nvram_data_off = ~0;
ecc89f25
JC		 3044 } else if (IS_QLA28XX(ha)) {
3045 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3046 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3047 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3048 req_length = REQUEST_ENTRY_CNT_24XX;
3049 rsp_length = RESPONSE_ENTRY_CNT_2300;
3050 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3051 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3052 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3053 ha->gid_list_info_size = 8;
3054 ha->optrom_size = OPTROM_SIZE_28XX;
3055 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3056 ha->isp_ops = &qla27xx_isp_ops;
3057 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3058 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3059 ha->nvram_conf_off = ~0;
3060 ha->nvram_data_off = ~0;
1da177e4 3061 }
6246b8a1 3062
7c3df132
SK		 3063 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3064 "mbx_count=%d, req_length=%d, "
3065 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3066 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3067 "max_fibre_devices=%d.\n",
7c3df132
SK		 3068 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3069 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3070 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3071 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3072 "isp_ops=%p, flash_conf_off=%d, "
3073 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3074 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3075 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3076
3077 /* Configure PCI I/O space */
3078 ret = ha->isp_ops->iospace_config(ha);
3079 if (ret)
0a63ad12 3080 goto iospace_config_failed;
706f457d
GM		 3081
3082 ql_log_pci(ql_log_info, pdev, 0x001d,
3083 "Found an ISP%04X irq %d iobase 0x%p.\n",
3084 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3085 mutex_init(&ha->vport_lock);
d7459527 3086 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3087 init_completion(&ha->mbx_cmd_comp);
3088 complete(&ha->mbx_cmd_comp);
3089 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3090 init_completion(&ha->dcbx_comp);
f356bef1 3091 init_completion(&ha->lb_portup_comp);
1da177e4 3092
2c3dfe3f 3093 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3094
53303c42 3095 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3096 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3097 "64 Bit addressing is %s.\n",
3098 ha->flags.enable_64bit_addressing ? "enable" :
3099 "disable");
73208dfd 3100 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3101 if (ret) {
7c3df132
SK		 3102 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3103 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3104
e315cd28
AC		 3105 goto probe_hw_failed;
3106 }
3107
73208dfd 3108 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3109 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3110 req->max_q_depth = ql2xmaxqdepth;
3111
e315cd28
AC		 3112
3113 base_vha = qla2x00_create_host(sht, ha);
3114 if (!base_vha) {
a1541d5a 3115 ret = -ENOMEM;
e315cd28 3116 goto probe_hw_failed;
1da177e4
LT		 3117 }
3118
e315cd28 3119 pci_set_drvdata(pdev, base_vha);
6b383979 3120 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3121
e315cd28 3122 host = base_vha->host;
2afa19a9 3123 base_vha->req = req;
73208dfd 3124 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3125 base_vha->mgmt_svr_loop_id =
3126 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3127 else
e315cd28
AC		 3128 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3129 base_vha->vp_idx;
58548cb5 3130
8ae6d9c7
GM		 3131 /* Setup fcport template structure. */
3132 ha->mr.fcport.vha = base_vha;
3133 ha->mr.fcport.port_type = FCT_UNKNOWN;
3134 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3135 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3136 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3137 ha->mr.fcport.scan_state = 1;
3138
58548cb5
GM		 3139 /* Set the SG table size based on ISP type */
3140 if (!IS_FWI2_CAPABLE(ha)) {
3141 if (IS_QLA2100(ha))
3142 host->sg_tablesize = 32;
3143 } else {
3144 if (!IS_QLA82XX(ha))
3145 host->sg_tablesize = QLA_SG_ALL;
3146 }
642ef983 3147 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3148 host->cmd_per_lun = 3;
3149 host->unique_id = host->host_no;
e02587d7 3150 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3151 host->max_cmd_len = 32;
3152 else
3153 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3154 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3155 /* Older HBAs support only 16-bit LUNs */
3156 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3157 ql2xmaxlun > 0xffff)
3158 host->max_lun = 0xffff;
3159 else
3160 host->max_lun = ql2xmaxlun;
e315cd28 3161 host->transportt = qla2xxx_transport_template;
9a069e19 3162 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3163
7c3df132
SK		 3164 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3165 "max_id=%d this_id=%d "
3166 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3167 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3168 host->this_id, host->cmd_per_lun, host->unique_id,
3169 host->max_cmd_len, host->max_channel, host->max_lun,
3170 host->transportt, sht->vendor_id);
3171
1010f21e
HM		 3172 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3173
d7459527
MH		 3174 /* Set up the irqs */
3175 ret = qla2x00_request_irqs(ha, rsp);
3176 if (ret)
6a2cf8d3 3177 goto probe_failed;
d7459527 3178
9a347ff4 3179 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3180 ret = qla2x00_alloc_queues(ha, req, rsp);
3181 if (ret) {
9a347ff4
CD		 3182 ql_log(ql_log_fatal, base_vha, 0x003d,
3183 "Failed to allocate memory for queue pointers..."
3184 "aborting.\n");
26a77799 3185 ret = -ENODEV;
6a2cf8d3 3186 goto probe_failed;
9a347ff4
CD		 3187 }
3188
f664a3cc 3189 if (ha->mqenable) {
5601236b
MH		 3190 /* number of hardware queues supported by blk/scsi-mq*/
3191 host->nr_hw_queues = ha->max_qpairs;
3192
3193 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3194 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3195 } else {
3196 if (ql2xnvmeenable) {
3197 host->nr_hw_queues = ha->max_qpairs;
3198 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3199 "FC-NVMe support is enabled, HW queues=%d\n",
3200 host->nr_hw_queues);
3201 } else {
3202 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3203 "blk/scsi-mq disabled.\n");
3204 }
3205 }
5601236b 3206
2d70c103 3207 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3208
90a86fc0
JC		 3209 pci_save_state(pdev);
3210
9a347ff4 3211 /* Assign back pointers */
2afa19a9
AC		 3212 rsp->req = req;
3213 req->rsp = rsp;
9a347ff4 3214
8ae6d9c7
GM		 3215 if (IS_QLAFX00(ha)) {
3216 ha->rsp_q_map[0] = rsp;
3217 ha->req_q_map[0] = req;
3218 set_bit(0, ha->req_qid_map);
3219 set_bit(0, ha->rsp_qid_map);
3220 }
3221
08029990
AV		 3222 /* FWI2-capable only. */
3223 req->req_q_in = &ha->iobase->isp24.req_q_in;
3224 req->req_q_out = &ha->iobase->isp24.req_q_out;
3225 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3226 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3227 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3228 IS_QLA28XX(ha)) {
08029990
AV		 3229 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3230 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3231 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3232 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3233 }
3234
8ae6d9c7
GM		 3235 if (IS_QLAFX00(ha)) {
3236 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3237 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3238 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3239 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3240 }
3241
7ec0effd 3242 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3243 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3244 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3245 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3246 }
3247
7c3df132
SK		 3248 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3249 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3250 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3251 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3252 "req->req_q_in=%p req->req_q_out=%p "
3253 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3254 req->req_q_in, req->req_q_out,
3255 rsp->rsp_q_in, rsp->rsp_q_out);
3256 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3257 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3258 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3259 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3260 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3261 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3262
d48cc67c 3263 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
35a79a63
AP		 3264 if (unlikely(!ha->wq)) {
3265 ret = -ENOMEM;
3266 goto probe_failed;
3267 }
d48cc67c 3268
8ae6d9c7 3269 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3270 ql_log(ql_log_fatal, base_vha, 0x00d6,
3271 "Failed to initialize adapter - Adapter flags %x.\n",
3272 base_vha->device_flags);
1da177e4 3273
a9083016
GM		 3274 if (IS_QLA82XX(ha)) {
3275 qla82xx_idc_lock(ha);
3276 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3277 QLA8XXX_DEV_FAILED);
a9083016 3278 qla82xx_idc_unlock(ha);
7c3df132
SK		 3279 ql_log(ql_log_fatal, base_vha, 0x00d7,
3280 "HW State: FAILED.\n");
7ec0effd
AD		 3281 } else if (IS_QLA8044(ha)) {
3282 qla8044_idc_lock(ha);
3283 qla8044_wr_direct(base_vha,
3284 QLA8044_CRB_DEV_STATE_INDEX,
3285 QLA8XXX_DEV_FAILED);
3286 qla8044_idc_unlock(ha);
3287 ql_log(ql_log_fatal, base_vha, 0x0150,
3288 "HW State: FAILED.\n");
a9083016
GM		 3289 }
3290
a1541d5a 3291 ret = -ENODEV;
1da177e4
LT		 3292 goto probe_failed;
3293 }
3294
3b1bef64
CD		 3295 if (IS_QLAFX00(ha))
3296 host->can_queue = QLAFX00_MAX_CANQUEUE;
3297 else
3298 host->can_queue = req->num_outstanding_cmds - 10;
3299
3300 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3301 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3302 host->can_queue, base_vha->req,
3303 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3304
e326d22a 3305 if (ha->mqenable) {
e326d22a 3306 bool startit = false;
e326d22a 3307
f664a3cc 3308 if (QLA_TGT_MODE_ENABLED())
e326d22a 3309 startit = false;
e326d22a 3310
f664a3cc 3311 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3312 startit = true;
e326d22a 3313
f664a3cc
JA		 3314 /* Create start of day qpairs for Block MQ */
3315 for (i = 0; i < ha->max_qpairs; i++)
3316 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3317 }
68ca949c 3318
cbc8eb67
AV		 3319 if (ha->flags.running_gold_fw)
3320 goto skip_dpc;
3321
1da177e4
LT		 3322 /*
3323 * Startup the kernel thread for this host adapter
3324 */
39a11240 3325 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3326 "%s_dpc", base_vha->host_str);
39a11240 3327 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3328 ql_log(ql_log_fatal, base_vha, 0x00ed,
3329 "Failed to start DPC thread.\n");
39a11240 3330 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3331 ha->dpc_thread = NULL;
1da177e4
LT		 3332 goto probe_failed;
3333 }
7c3df132
SK		 3334 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3335 "DPC thread started successfully.\n");
1da177e4 3336
2d70c103
NB		 3337 /*
3338 * If we're not coming up in initiator mode, we might sit for
3339 * a while without waking up the dpc thread, which leads to a
3340 * stuck process warning. So just kick the dpc once here and
3341 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3342 */
3343 qla2xxx_wake_dpc(base_vha);
3344
f3ddac19
CD		 3345 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3346
81178772
SK		 3347 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3348 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3349 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3350 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3351
3352 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3353 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3354 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3355 INIT_WORK(&ha->idc_state_handler,
3356 qla83xx_idc_state_handler_work);
3357 INIT_WORK(&ha->nic_core_unrecoverable,
3358 qla83xx_nic_core_unrecoverable_work);
3359 }
3360
cbc8eb67 3361skip_dpc:
e315cd28
AC		 3362 list_add_tail(&base_vha->list, &ha->vp_list);
3363 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3364
3365 /* Initialized the timer */
8e5f4ba0 3366 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3367 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3368 "Started qla2x00_timer with "
3369 "interval=%d.\n", WATCH_INTERVAL);
3370 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3371 "Detected hba at address=%p.\n",
3372 ha);
d19044c3 3373
e02587d7 3374 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3375 if (ha->fw_attributes & BIT_4) {
9e522cd8 3376 int prot = 0, guard;
bd432bb5 3377
bad75002 3378 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3379 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3380 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3381 if (ql2xenabledif == 1)
3382 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3383 if (ql2xprotmask)
3384 scsi_host_set_prot(host, ql2xprotmask);
3385 else
3386 scsi_host_set_prot(host,
3387 prot | SHOST_DIF_TYPE1_PROTECTION
3388 | SHOST_DIF_TYPE2_PROTECTION
3389 | SHOST_DIF_TYPE3_PROTECTION
3390 | SHOST_DIX_TYPE1_PROTECTION
3391 | SHOST_DIX_TYPE2_PROTECTION
3392 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3393
3394 guard = SHOST_DIX_GUARD_CRC;
3395
3396 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3397 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3398 guard |= SHOST_DIX_GUARD_IP;
3399
7855d2ba
MP		 3400 if (ql2xprotguard)
3401 scsi_host_set_guard(host, ql2xprotguard);
3402 else
3403 scsi_host_set_guard(host, guard);
bad75002
AE		 3404 } else
3405 base_vha->flags.difdix_supported = 0;
3406 }
3407
a9083016
GM		 3408 ha->isp_ops->enable_intrs(ha);
3409
1fe19ee4
AB		 3410 if (IS_QLAFX00(ha)) {
3411 ret = qlafx00_fx_disc(base_vha,
3412 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3413 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3414 QLA_SG_ALL : 128;
3415 }
3416
a1541d5a
AV		 3417 ret = scsi_add_host(host, &pdev->dev);
3418 if (ret)
3419 goto probe_failed;
3420
1486400f
MR		 3421 base_vha->flags.init_done = 1;
3422 base_vha->flags.online = 1;
edaa5c74 3423 ha->prev_minidump_failed = 0;
1486400f 3424
7c3df132
SK		 3425 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3426 "Init done and hba is online.\n");
3427
726b8548
QT		 3428 if (qla_ini_mode_enabled(base_vha) ||
3429 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3430 scsi_scan_host(host);
3431 else
3432 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3433 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3434
e315cd28 3435 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3436
8ae6d9c7 3437 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3438 ret = qlafx00_fx_disc(base_vha,
3439 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3440
3441 /* Register system information */
3442 ret = qlafx00_fx_disc(base_vha,
3443 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3444 }
3445
e315cd28 3446 qla2x00_init_host_attr(base_vha);
a1541d5a 3447
e315cd28 3448 qla2x00_dfs_setup(base_vha);
df613b96 3449
03eb912a
AB		 3450 ql_log(ql_log_info, base_vha, 0x00fb,
3451 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3452 ql_log(ql_log_info, base_vha, 0x00fc,
3453 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
dc6d6d34
BVA		 3454 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info,
3455 sizeof(pci_info)),
7c3df132
SK		 3456 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3457 base_vha->host_no,
df57caba 3458 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3459
2d70c103
NB		 3460 qlt_add_target(ha, base_vha);
3461
6b383979 3462 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3463
3464 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3465 return -ENODEV;
3466
1da177e4
LT		 3467 return 0;
3468
3469probe_failed:
26fa656e
BK		 3470 if (base_vha->gnl.l) {
3471 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3472 base_vha->gnl.l, base_vha->gnl.ldma);
3473 base_vha->gnl.l = NULL;
3474 }
3475
b9978769
AV		 3476 if (base_vha->timer_active)
3477 qla2x00_stop_timer(base_vha);
3478 base_vha->flags.online = 0;
3479 if (ha->dpc_thread) {
3480 struct task_struct *t = ha->dpc_thread;
3481
3482 ha->dpc_thread = NULL;
3483 kthread_stop(t);
3484 }
3485
e315cd28 3486 qla2x00_free_device(base_vha);
e315cd28 3487 scsi_host_put(base_vha->host);
6d634067
BK		 3488 /*
3489 * Need to NULL out local req/rsp after
3490 * qla2x00_free_device => qla2x00_free_queues frees
3491 * what these are pointing to. Or else we'll
3492 * fall over below in qla2x00_free_req/rsp_que.
3493 */
3494 req = NULL;
3495 rsp = NULL;
1da177e4 3496
e315cd28 3497probe_hw_failed:
d64d6c56 3498 qla2x00_mem_free(ha);
3499 qla2x00_free_req_que(ha, req);
3500 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3501 qla2x00_clear_drv_active(ha);
3502
0a63ad12 3503iospace_config_failed:
7ec0effd 3504 if (IS_P3P_TYPE(ha)) {
0a63ad12 3505 if (!ha->nx_pcibase)
f73cb695 3506 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3507 if (!ql2xdbwr)
f73cb695 3508 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3509 } else {
3510 if (ha->iobase)
3511 iounmap(ha->iobase);
8ae6d9c7
GM		 3512 if (ha->cregbase)
3513 iounmap(ha->cregbase);
a9083016 3514 }
e315cd28
AC		 3515 pci_release_selected_regions(ha->pdev, ha->bars);
3516 kfree(ha);
1da177e4 3517
ddff7ed4 3518disable_device:
e315cd28 3519 pci_disable_device(pdev);
a1541d5a 3520 return ret;
1da177e4 3521}
1da177e4 3522
6997db98
QT		 3523static void __qla_set_remove_flag(scsi_qla_host_t *base_vha)
3524{
3525 scsi_qla_host_t *vp;
3526 unsigned long flags;
3527 struct qla_hw_data *ha;
3528
3529 if (!base_vha)
3530 return;
3531
3532 ha = base_vha->hw;
3533
3534 spin_lock_irqsave(&ha->vport_slock, flags);
3535 list_for_each_entry(vp, &ha->vp_list, list)
3536 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags);
3537
3538 /*
3539 * Indicate device removal to prevent future board_disable
3540 * and wait until any pending board_disable has completed.
3541 */
3542 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3543 spin_unlock_irqrestore(&ha->vport_slock, flags);
3544}
3545
e30d1756
MI		 3546static void
3547qla2x00_shutdown(struct pci_dev *pdev)
3548{
3549 scsi_qla_host_t *vha;
3550 struct qla_hw_data *ha;
3551
3552 vha = pci_get_drvdata(pdev);
3553 ha = vha->hw;
3554
efdb5760
SC		 3555 ql_log(ql_log_info, vha, 0xfffa,
3556 "Adapter shutdown\n");
3557
3558 /*
3559 * Prevent future board_disable and wait
3560 * until any pending board_disable has completed.
3561 */
6997db98 3562 __qla_set_remove_flag(vha);
efdb5760
SC		 3563 cancel_work_sync(&ha->board_disable);
3564
3565 if (!atomic_read(&pdev->enable_cnt))
3566 return;
3567
42479343
AB		 3568 /* Notify ISPFX00 firmware */
3569 if (IS_QLAFX00(ha))
3570 qlafx00_driver_shutdown(vha, 20);
3571
e30d1756
MI		 3572 /* Turn-off FCE trace */
3573 if (ha->flags.fce_enabled) {
3574 qla2x00_disable_fce_trace(vha, NULL, NULL);
3575 ha->flags.fce_enabled = 0;
3576 }
3577
3578 /* Turn-off EFT trace */
3579 if (ha->eft)
3580 qla2x00_disable_eft_trace(vha);
3581
ecc89f25
JC		 3582 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3583 IS_QLA28XX(ha)) {
3407fc37
QT		 3584 if (ha->flags.fw_started)
3585 qla2x00_abort_isp_cleanup(vha);
3586 } else {
3587 /* Stop currently executing firmware. */
3588 qla2x00_try_to_stop_firmware(vha);
3589 }
e30d1756 3590
d3566abb
NP		 3591 /* Disable timer */
3592 if (vha->timer_active)
3593 qla2x00_stop_timer(vha);
3594
e30d1756
MI		 3595 /* Turn adapter off line */
3596 vha->flags.online = 0;
3597
3598 /* turn-off interrupts on the card */
3599 if (ha->interrupts_on) {
3600 vha->flags.init_done = 0;
3601 ha->isp_ops->disable_intrs(ha);
3602 }
3603
3604 qla2x00_free_irqs(vha);
3605
3606 qla2x00_free_fw_dump(ha);
61d41f61 3607
61d41f61 3608 pci_disable_device(pdev);
efdb5760
SC		 3609 ql_log(ql_log_info, vha, 0xfffe,
3610 "Adapter shutdown successfully.\n");
e30d1756
MI		 3611}
3612
fe1b806f 3613/* Deletes all the virtual ports for a given ha */
4c993f76 3614static void
fe1b806f 3615qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3616{
fe1b806f 3617 scsi_qla_host_t *vha;
feafb7b1 3618 unsigned long flags;
e315cd28 3619
43ebf16d
AE		 3620 mutex_lock(&ha->vport_lock);
3621 while (ha->cur_vport_count) {
43ebf16d 3622 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3623
43ebf16d
AE		 3624 BUG_ON(base_vha->list.next == &ha->vp_list);
3625 /* This assumes first entry in ha->vp_list is always base vha */
3626 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3627 scsi_host_get(vha->host);
feafb7b1 3628
43ebf16d
AE		 3629 spin_unlock_irqrestore(&ha->vport_slock, flags);
3630 mutex_unlock(&ha->vport_lock);
3631
5e6803b4
HM		 3632 qla_nvme_delete(vha);
3633
43ebf16d
AE		 3634 fc_vport_terminate(vha->fc_vport);
3635 scsi_host_put(vha->host);
feafb7b1 3636
43ebf16d 3637 mutex_lock(&ha->vport_lock);
e315cd28 3638 }
43ebf16d 3639 mutex_unlock(&ha->vport_lock);
fe1b806f 3640}
1da177e4 3641
fe1b806f
CD		 3642/* Stops all deferred work threads */
3643static void
3644qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3645{
7d613ac6
SV		 3646 /* Cancel all work and destroy DPC workqueues */
3647 if (ha->dpc_lp_wq) {
3648 cancel_work_sync(&ha->idc_aen);
3649 destroy_workqueue(ha->dpc_lp_wq);
3650 ha->dpc_lp_wq = NULL;
3651 }
3652
3653 if (ha->dpc_hp_wq) {
3654 cancel_work_sync(&ha->nic_core_reset);
3655 cancel_work_sync(&ha->idc_state_handler);
3656 cancel_work_sync(&ha->nic_core_unrecoverable);
3657 destroy_workqueue(ha->dpc_hp_wq);
3658 ha->dpc_hp_wq = NULL;
3659 }
3660
b9978769
AV		 3661 /* Kill the kernel thread for this host */
3662 if (ha->dpc_thread) {
3663 struct task_struct *t = ha->dpc_thread;
3664
3665 /*
3666 * qla2xxx_wake_dpc checks for ->dpc_thread
3667 * so we need to zero it out.
3668 */
3669 ha->dpc_thread = NULL;
3670 kthread_stop(t);
3671 }
fe1b806f 3672}
1da177e4 3673
fe1b806f
CD		 3674static void
3675qla2x00_unmap_iobases(struct qla_hw_data *ha)
3676{
a9083016 3677 if (IS_QLA82XX(ha)) {
b963752f 3678
f73cb695 3679 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3680 if (!ql2xdbwr)
f73cb695 3681 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3682 } else {
3683 if (ha->iobase)
3684 iounmap(ha->iobase);
1da177e4 3685
8ae6d9c7
GM		 3686 if (ha->cregbase)
3687 iounmap(ha->cregbase);
3688
a9083016
GM		 3689 if (ha->mqiobase)
3690 iounmap(ha->mqiobase);
6246b8a1 3691
ecc89f25
JC		 3692 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3693 ha->msixbase)
6246b8a1 3694 iounmap(ha->msixbase);
a9083016 3695 }
fe1b806f
CD		 3696}
3697
3698static void
db7157d4 3699qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3700{
fe1b806f
CD		 3701 if (IS_QLA8044(ha)) {
3702 qla8044_idc_lock(ha);
c41afc9a 3703 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3704 qla8044_idc_unlock(ha);
3705 } else if (IS_QLA82XX(ha)) {
3706 qla82xx_idc_lock(ha);
3707 qla82xx_clear_drv_active(ha);
3708 qla82xx_idc_unlock(ha);
3709 }
3710}
3711
3712static void
3713qla2x00_remove_one(struct pci_dev *pdev)
3714{
3715 scsi_qla_host_t *base_vha;
3716 struct qla_hw_data *ha;
3717
beb9e315
JL		 3718 base_vha = pci_get_drvdata(pdev);
3719 ha = base_vha->hw;
45235022
QT		 3720 ql_log(ql_log_info, base_vha, 0xb079,
3721 "Removing driver\n");
6997db98 3722 __qla_set_remove_flag(base_vha);
beb9e315
JL		 3723 cancel_work_sync(&ha->board_disable);
3724
fe1b806f 3725 /*
beb9e315
JL		 3726 * If the PCI device is disabled then there was a PCI-disconnect and
3727 * qla2x00_disable_board_on_pci_error has taken care of most of the
3728 * resources.
fe1b806f 3729 */
beb9e315 3730 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3731 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3732 base_vha->gnl.l, base_vha->gnl.ldma);
26fa656e 3733 base_vha->gnl.l = NULL;
beb9e315
JL		 3734 scsi_host_put(base_vha->host);
3735 kfree(ha);
3736 pci_set_drvdata(pdev, NULL);
fe1b806f 3737 return;
beb9e315 3738 }
638a1a01
SC		 3739 qla2x00_wait_for_hba_ready(base_vha);
3740
856e152a
MW		 3741 /*
3742 * if UNLOADING flag is already set, then continue unload,
3743 * where it was set first.
3744 */
3745 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
3746 return;
3747
ecc89f25
JC		 3748 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3749 IS_QLA28XX(ha)) {
45235022
QT		 3750 if (ha->flags.fw_started)
3751 qla2x00_abort_isp_cleanup(base_vha);
3752 } else if (!IS_QLAFX00(ha)) {
3753 if (IS_QLA8031(ha)) {
3754 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3755 "Clearing fcoe driver presence.\n");
3756 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3757 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3758 "Error while clearing DRV-Presence.\n");
3759 }
3760
3761 qla2x00_try_to_stop_firmware(base_vha);
3762 }
3763
2ce87cc5
QT		 3764 qla2x00_wait_for_sess_deletion(base_vha);
3765
e84067d7
DG		 3766 qla_nvme_delete(base_vha);
3767
726b8548
QT		 3768 dma_free_coherent(&ha->pdev->dev,
3769 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3770
26fa656e
BK		 3771 base_vha->gnl.l = NULL;
3772
a4239945
QT		 3773 vfree(base_vha->scan.l);
3774
fe1b806f
CD		 3775 if (IS_QLAFX00(ha))
3776 qlafx00_driver_shutdown(base_vha, 20);
3777
3778 qla2x00_delete_all_vps(ha, base_vha);
3779
fe1b806f
CD		 3780 qla2x00_dfs_remove(base_vha);
3781
3782 qla84xx_put_chip(base_vha);
3783
3784 /* Disable timer */
3785 if (base_vha->timer_active)
3786 qla2x00_stop_timer(base_vha);
3787
3788 base_vha->flags.online = 0;
3789
b0d6cabd
HM		 3790 /* free DMA memory */
3791 if (ha->exlogin_buf)
3792 qla2x00_free_exlogin_buffer(ha);
3793
2f56a7f1
HM		 3794 /* free DMA memory */
3795 if (ha->exchoffld_buf)
3796 qla2x00_free_exchoffld_buffer(ha);
3797
fe1b806f
CD		 3798 qla2x00_destroy_deferred_work(ha);
3799
3800 qlt_remove_target(ha, base_vha);
3801
3802 qla2x00_free_sysfs_attr(base_vha, true);
3803
3804 fc_remove_host(base_vha->host);
482c9dc7 3805 qlt_remove_target_resources(ha);
fe1b806f
CD		 3806
3807 scsi_remove_host(base_vha->host);
3808
3809 qla2x00_free_device(base_vha);
3810
db7157d4 3811 qla2x00_clear_drv_active(ha);
fe1b806f 3812
d2749ffa
AE		 3813 scsi_host_put(base_vha->host);
3814
fe1b806f 3815 qla2x00_unmap_iobases(ha);
73208dfd 3816
e315cd28
AC		 3817 pci_release_selected_regions(ha->pdev, ha->bars);
3818 kfree(ha);
1da177e4 3819
90a86fc0
JC		 3820 pci_disable_pcie_error_reporting(pdev);
3821
665db93b 3822 pci_disable_device(pdev);
1da177e4 3823}
1da177e4 3824
576bfde8
JC		 3825static inline void
3826qla24xx_free_purex_list(struct purex_list *list)
3827{
3828 struct list_head *item, *next;
3829 ulong flags;
3830
3831 spin_lock_irqsave(&list->lock, flags);
3832 list_for_each_safe(item, next, &list->head) {
3833 list_del(item);
3834 kfree(list_entry(item, struct purex_item, list));
3835 }
3836 spin_unlock_irqrestore(&list->lock, flags);
3837}
3838
1da177e4 3839static void
e315cd28 3840qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3841{
e315cd28 3842 struct qla_hw_data *ha = vha->hw;
1da177e4 3843
85880801
AV		 3844 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3845
3846 /* Disable timer */
3847 if (vha->timer_active)
3848 qla2x00_stop_timer(vha);
3849
2afa19a9 3850 qla25xx_delete_queues(vha);
85880801
AV		 3851 vha->flags.online = 0;
3852
f6ef3b18 3853 /* turn-off interrupts on the card */
a9083016
GM		 3854 if (ha->interrupts_on) {
3855 vha->flags.init_done = 0;
fd34f556 3856 ha->isp_ops->disable_intrs(ha);
a9083016 3857 }
f6ef3b18 3858
093df737
QT		 3859 qla2x00_free_fcports(vha);
3860
e315cd28 3861 qla2x00_free_irqs(vha);
1da177e4 3862
093df737
QT		 3863 /* Flush the work queue and remove it */
3864 if (ha->wq) {
3865 flush_workqueue(ha->wq);
3866 destroy_workqueue(ha->wq);
3867 ha->wq = NULL;
3868 }
3869
8867048b 3870
576bfde8
JC		 3871 qla24xx_free_purex_list(&vha->purex_list);
3872
e315cd28 3873 qla2x00_mem_free(ha);
73208dfd 3874
08de2844
GM		 3875 qla82xx_md_free(vha);
3876
73208dfd 3877 qla2x00_free_queues(ha);
1da177e4
LT		 3878}
3879
8867048b
CD		 3880void qla2x00_free_fcports(struct scsi_qla_host *vha)
3881{
3882 fc_port_t *fcport, *tfcport;
3883
ffbc6476
QT		 3884 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3885 qla2x00_free_fcport(fcport);
8867048b
CD		 3886}
3887
d97994dc 3888static inline void
3c75ad1d 3889qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport)
d97994dc 3890{
3c75ad1d 3891 int now;
d97994dc
AV		 3892
3893 if (!fcport->rport)
3894 return;
3895
3c75ad1d
HM		 3896 if (fcport->rport) {
3897 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3898 "%s %8phN. rport %p roles %x\n",
3899 __func__, fcport->port_name, fcport->rport,
3900 fcport->rport->roles);
3901 fc_remote_port_delete(fcport->rport);
2d70c103 3902 }
3c75ad1d 3903 qlt_do_generation_tick(vha, &now);
d97994dc
AV		 3904}
3905
1da177e4
LT		 3906/*
3907 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3908 *
3909 * Input: ha = adapter block pointer. fcport = port structure pointer.
3910 *
3911 * Return: None.
3912 *
3913 * Context:
3914 */
e315cd28 3915void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3c75ad1d 3916 int do_login)
1da177e4 3917{
8ae6d9c7
GM		 3918 if (IS_QLAFX00(vha->hw)) {
3919 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3c75ad1d 3920 qla2x00_schedule_rport_del(vha, fcport);
8ae6d9c7
GM		 3921 return;
3922 }
3923
2c3dfe3f 3924 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3925 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3926 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3c75ad1d 3927 qla2x00_schedule_rport_del(vha, fcport);
e315cd28 3928 }
fa2a1ce5 3929 /*
1da177e4
LT		 3930 * We may need to retry the login, so don't change the state of the
3931 * port but do the retries.
3932 */
3933 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3934 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3935
3936 if (!do_login)
3937 return;
3938
a1d0285e 3939 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3940}
3941
1da177e4 3942void
3c75ad1d 3943qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha)
1da177e4
LT		 3944{
3945 fc_port_t *fcport;
3946
83548fe2
QT		 3947 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3948 "Mark all dev lost\n");
726b8548 3949
e315cd28 3950 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3951 fcport->scan_state = 0;
d8630bb9 3952 qlt_schedule_sess_for_deletion(fcport);
1da177e4
LT		 3953 }
3954}
3955
0e145a59
BVA		 3956static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3957{
3958 int i;
3959
3960 if (IS_FWI2_CAPABLE(ha))
3961 return;
3962
3963 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3964 set_bit(i, ha->loop_id_map);
3965 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3966 set_bit(BROADCAST, ha->loop_id_map);
3967}
3968
1da177e4
LT		 3969/*
3970* qla2x00_mem_alloc
3971* Allocates adapter memory.
3972*
3973* Returns:
3974* 0 = success.
e8711085 3975* !0 = failure.
1da177e4 3976*/
e8711085 3977static int
73208dfd
AC		 3978qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3979 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3980{
3981 char name[16];
1da177e4 3982
e8711085 3983 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3984 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3985 if (!ha->init_cb)
e315cd28 3986 goto fail;
e8711085 3987
2d70c103
NB		 3988 if (qlt_mem_alloc(ha) < 0)
3989 goto fail_free_init_cb;
3990
642ef983
CD		 3991 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3992 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3993 if (!ha->gid_list)
2d70c103 3994 goto fail_free_tgt_mem;
1da177e4 3995
e8711085
AV		 3996 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3997 if (!ha->srb_mempool)
e315cd28 3998 goto fail_free_gid_list;
e8711085 3999
7ec0effd 4000 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 4001 /* Allocate cache for CT6 Ctx. */
4002 if (!ctx_cachep) {
4003 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
4004 sizeof(struct ct6_dsd), 0,
4005 SLAB_HWCACHE_ALIGN, NULL);
4006 if (!ctx_cachep)
fc1ffd6c 4007 goto fail_free_srb_mempool;
a9083016
GM		 4008 }
4009 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4010 ctx_cachep);
4011 if (!ha->ctx_mempool)
4012 goto fail_free_srb_mempool;
7c3df132
SK		 4013 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4014 "ctx_cachep=%p ctx_mempool=%p.\n",
4015 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4016 }
4017
e8711085
AV		 4018 /* Get memory for cached NVRAM */
4019 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4020 if (!ha->nvram)
a9083016 4021 goto fail_free_ctx_mempool;
e8711085 4022
e315cd28
AC		 4023 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4024 ha->pdev->device);
4025 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4026 DMA_POOL_SIZE, 8, 0);
4027 if (!ha->s_dma_pool)
4028 goto fail_free_nvram;
4029
7c3df132
SK		 4030 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4031 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4032 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4033
7ec0effd 4034 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4035 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4036 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4037 if (!ha->dl_dma_pool) {
7c3df132
SK		 4038 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4039 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4040 goto fail_s_dma_pool;
4041 }
4042
4043 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4044 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4045 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4046 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4047 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4048 goto fail_dl_dma_pool;
4049 }
50b81275
GM		 4050
4051 if (ql2xenabledif) {
4052 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4053 struct dsd_dma *dsd, *nxt;
4054 uint i;
4055 /* Creata a DMA pool of buffers for DIF bundling */
4056 ha->dif_bundl_pool = dma_pool_create(name,
4057 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4058 if (!ha->dif_bundl_pool) {
4059 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4060 "%s: failed create dif_bundl_pool\n",
4061 __func__);
4062 goto fail_dif_bundl_dma_pool;
4063 }
4064
4065 INIT_LIST_HEAD(&ha->pool.good.head);
4066 INIT_LIST_HEAD(&ha->pool.unusable.head);
4067 ha->pool.good.count = 0;
4068 ha->pool.unusable.count = 0;
4069 for (i = 0; i < 128; i++) {
4070 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4071 if (!dsd) {
4072 ql_dbg_pci(ql_dbg_init, ha->pdev,
4073 0xe0ee, "%s: failed alloc dsd\n",
4074 __func__);
4075 return 1;
4076 }
4077 ha->dif_bundle_kallocs++;
4078
4079 dsd->dsd_addr = dma_pool_alloc(
4080 ha->dif_bundl_pool, GFP_ATOMIC,
4081 &dsd->dsd_list_dma);
4082 if (!dsd->dsd_addr) {
4083 ql_dbg_pci(ql_dbg_init, ha->pdev,
4084 0xe0ee,
4085 "%s: failed alloc ->dsd_addr\n",
4086 __func__);
4087 kfree(dsd);
4088 ha->dif_bundle_kallocs--;
4089 continue;
4090 }
4091 ha->dif_bundle_dma_allocs++;
4092
4093 /*
4094 * if DMA buffer crosses 4G boundary,
4095 * put it on bad list
4096 */
4097 if (MSD(dsd->dsd_list_dma) ^
4098 MSD(dsd->dsd_list_dma + bufsize)) {
4099 list_add_tail(&dsd->list,
4100 &ha->pool.unusable.head);
4101 ha->pool.unusable.count++;
4102 } else {
4103 list_add_tail(&dsd->list,
4104 &ha->pool.good.head);
4105 ha->pool.good.count++;
4106 }
4107 }
4108
4109 /* return the good ones back to the pool */
4110 list_for_each_entry_safe(dsd, nxt,
4111 &ha->pool.good.head, list) {
4112 list_del(&dsd->list);
4113 dma_pool_free(ha->dif_bundl_pool,
4114 dsd->dsd_addr, dsd->dsd_list_dma);
4115 ha->dif_bundle_dma_allocs--;
4116 kfree(dsd);
4117 ha->dif_bundle_kallocs--;
4118 }
4119
4120 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4121 "%s: dif dma pool (good=%u unusable=%u)\n",
4122 __func__, ha->pool.good.count,
4123 ha->pool.unusable.count);
4124 }
4125
7c3df132 4126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4127 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4128 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4129 ha->dif_bundl_pool);
a9083016
GM		 4130 }
4131
e8711085
AV		 4132 /* Allocate memory for SNS commands */
4133 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4134 /* Get consistent memory allocated for SNS commands */
e8711085 4135 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4136 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4137 if (!ha->sns_cmd)
e315cd28 4138 goto fail_dma_pool;
7c3df132 4139 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4140 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4141 } else {
e315cd28 4142 /* Get consistent memory allocated for MS IOCB */
e8711085 4143 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4144 &ha->ms_iocb_dma);
e8711085 4145 if (!ha->ms_iocb)
e315cd28
AC		 4146 goto fail_dma_pool;
4147 /* Get consistent memory allocated for CT SNS commands */
e8711085 4148 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4149 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4150 if (!ha->ct_sns)
4151 goto fail_free_ms_iocb;
7c3df132
SK		 4152 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4153 "ms_iocb=%p ct_sns=%p.\n",
4154 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4155 }
4156
e315cd28 4157 /* Allocate memory for request ring */
73208dfd
AC		 4158 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4159 if (!*req) {
7c3df132
SK		 4160 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4161 "Failed to allocate memory for req.\n");
e315cd28
AC		 4162 goto fail_req;
4163 }
73208dfd
AC		 4164 (*req)->length = req_len;
4165 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4166 ((*req)->length + 1) * sizeof(request_t),
4167 &(*req)->dma, GFP_KERNEL);
4168 if (!(*req)->ring) {
7c3df132
SK		 4169 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4170 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4171 goto fail_req_ring;
4172 }
4173 /* Allocate memory for response ring */
73208dfd
AC		 4174 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4175 if (!*rsp) {
7c3df132
SK		 4176 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4177 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4178 goto fail_rsp;
4179 }
73208dfd
AC		 4180 (*rsp)->hw = ha;
4181 (*rsp)->length = rsp_len;
4182 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4183 ((*rsp)->length + 1) * sizeof(response_t),
4184 &(*rsp)->dma, GFP_KERNEL);
4185 if (!(*rsp)->ring) {
7c3df132
SK		 4186 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4187 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4188 goto fail_rsp_ring;
4189 }
73208dfd
AC		 4190 (*req)->rsp = *rsp;
4191 (*rsp)->req = *req;
7c3df132
SK		 4192 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4193 "req=%p req->length=%d req->ring=%p rsp=%p "
4194 "rsp->length=%d rsp->ring=%p.\n",
4195 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4196 (*rsp)->ring);
73208dfd
AC		 4197 /* Allocate memory for NVRAM data for vports */
4198 if (ha->nvram_npiv_size) {
6396bb22
KC		 4199 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4200 sizeof(struct qla_npiv_entry),
4201 GFP_KERNEL);
73208dfd 4202 if (!ha->npiv_info) {
7c3df132
SK		 4203 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4204 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4205 goto fail_npiv_info;
4206 }
4207 } else
4208 ha->npiv_info = NULL;
e8711085 4209
b64b0e8f 4210 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4211 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4212 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4213 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4214 &ha->ex_init_cb_dma);
4215 if (!ha->ex_init_cb)
4216 goto fail_ex_init_cb;
7c3df132
SK		 4217 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4218 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4219 }
4220
9f2475fe
SS		 4221 /* Get consistent memory allocated for Special Features-CB. */
4222 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
4223 ha->sf_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4224 &ha->sf_init_cb_dma);
4225 if (!ha->sf_init_cb)
4226 goto fail_sf_init_cb;
4227 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199,
4228 "sf_init_cb=%p.\n", ha->sf_init_cb);
4229 }
4230
a9083016
GM		 4231 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4232
5ff1d584
AV		 4233 /* Get consistent memory allocated for Async Port-Database. */
4234 if (!IS_FWI2_CAPABLE(ha)) {
4235 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4236 &ha->async_pd_dma);
4237 if (!ha->async_pd)
4238 goto fail_async_pd;
7c3df132
SK		 4239 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4240 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4241 }
4242
e315cd28 4243 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4244
4245 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4246 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4247 sizeof(long),
4248 GFP_KERNEL);
5f16b331 4249 if (!ha->loop_id_map)
fc1ffd6c 4250 goto fail_loop_id_map;
5f16b331
CD		 4251 else {
4252 qla2x00_set_reserved_loop_ids(ha);
4253 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4254 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4255 }
4256
e4e3a2ce
QT		 4257 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4258 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4259 if (!ha->sfp_data) {
4260 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4261 "Unable to allocate memory for SFP read-data.\n");
4262 goto fail_sfp_data;
4263 }
4264
3f006ac3
MH		 4265 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4266 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4267 GFP_KERNEL);
4268 if (!ha->flt) {
4269 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4270 "Unable to allocate memory for FLT.\n");
4271 goto fail_flt_buffer;
4272 }
4273
b2a72ec3 4274 return 0;
e315cd28 4275
3f006ac3
MH		 4276fail_flt_buffer:
4277 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4278 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4279fail_sfp_data:
4280 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4281fail_loop_id_map:
4282 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584 4283fail_async_pd:
9f2475fe
SS		 4284 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma);
4285fail_sf_init_cb:
5ff1d584 4286 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4287fail_ex_init_cb:
4288 kfree(ha->npiv_info);
73208dfd
AC		 4289fail_npiv_info:
4290 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4291 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4292 (*rsp)->ring = NULL;
4293 (*rsp)->dma = 0;
e315cd28 4294fail_rsp_ring:
73208dfd 4295 kfree(*rsp);
6d634067 4296 *rsp = NULL;
e315cd28 4297fail_rsp:
73208dfd
AC		 4298 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4299 sizeof(request_t), (*req)->ring, (*req)->dma);
4300 (*req)->ring = NULL;
4301 (*req)->dma = 0;
e315cd28 4302fail_req_ring:
73208dfd 4303 kfree(*req);
6d634067 4304 *req = NULL;
e315cd28
AC		 4305fail_req:
4306 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4307 ha->ct_sns, ha->ct_sns_dma);
4308 ha->ct_sns = NULL;
4309 ha->ct_sns_dma = 0;
e8711085
AV		 4310fail_free_ms_iocb:
4311 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4312 ha->ms_iocb = NULL;
4313 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4314
4315 if (ha->sns_cmd)
4316 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4317 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4318fail_dma_pool:
50b81275
GM		 4319 if (ql2xenabledif) {
4320 struct dsd_dma *dsd, *nxt;
4321
4322 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4323 list) {
4324 list_del(&dsd->list);
4325 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4326 dsd->dsd_list_dma);
4327 ha->dif_bundle_dma_allocs--;
4328 kfree(dsd);
4329 ha->dif_bundle_kallocs--;
4330 ha->pool.unusable.count--;
4331 }
4332 dma_pool_destroy(ha->dif_bundl_pool);
4333 ha->dif_bundl_pool = NULL;
4334 }
4335
4336fail_dif_bundl_dma_pool:
bad75002 4337 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4338 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4339 ha->fcp_cmnd_dma_pool = NULL;
4340 }
4341fail_dl_dma_pool:
bad75002 4342 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4343 dma_pool_destroy(ha->dl_dma_pool);
4344 ha->dl_dma_pool = NULL;
4345 }
4346fail_s_dma_pool:
e315cd28
AC		 4347 dma_pool_destroy(ha->s_dma_pool);
4348 ha->s_dma_pool = NULL;
e8711085
AV		 4349fail_free_nvram:
4350 kfree(ha->nvram);
4351 ha->nvram = NULL;
a9083016 4352fail_free_ctx_mempool:
75c1d48a 4353 mempool_destroy(ha->ctx_mempool);
a9083016 4354 ha->ctx_mempool = NULL;
e8711085 4355fail_free_srb_mempool:
75c1d48a 4356 mempool_destroy(ha->srb_mempool);
e8711085 4357 ha->srb_mempool = NULL;
e8711085 4358fail_free_gid_list:
642ef983
CD		 4359 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4360 ha->gid_list,
e315cd28 4361 ha->gid_list_dma);
e8711085
AV		 4362 ha->gid_list = NULL;
4363 ha->gid_list_dma = 0;
2d70c103
NB		 4364fail_free_tgt_mem:
4365 qlt_mem_free(ha);
e315cd28
AC		 4366fail_free_init_cb:
4367 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4368 ha->init_cb_dma);
4369 ha->init_cb = NULL;
4370 ha->init_cb_dma = 0;
e8711085 4371fail:
7c3df132
SK		 4372 ql_log(ql_log_fatal, NULL, 0x0030,
4373 "Memory allocation failure.\n");
e8711085 4374 return -ENOMEM;
1da177e4
LT		 4375}
4376
b0d6cabd
HM		 4377int
4378qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4379{
4380 int rval;
4381 uint16_t size, max_cnt, temp;
4382 struct qla_hw_data *ha = vha->hw;
4383
4384 /* Return if we don't need to alloacate any extended logins */
4385 if (!ql2xexlogins)
4386 return QLA_SUCCESS;
4387
99e1b683
QT		 4388 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4389 return QLA_SUCCESS;
4390
b0d6cabd
HM		 4391 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4392 max_cnt = 0;
4393 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4394 if (rval != QLA_SUCCESS) {
4395 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4396 "Failed to get exlogin status.\n");
4397 return rval;
4398 }
4399
4400 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4401 temp *= size;
4402
4403 if (temp != ha->exlogin_size) {
4404 qla2x00_free_exlogin_buffer(ha);
4405 ha->exlogin_size = temp;
4406
4407 ql_log(ql_log_info, vha, 0xd024,
4408 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4409 max_cnt, size, temp);
4410
4411 ql_log(ql_log_info, vha, 0xd025,
4412 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4413
4414 /* Get consistent memory for extended logins */
4415 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4416 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4417 if (!ha->exlogin_buf) {
4418 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4419 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4420 return -ENOMEM;
4421 }
b0d6cabd
HM		 4422 }
4423
4424 /* Now configure the dma buffer */
4425 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4426 if (rval) {
83548fe2 4427 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4428 "Setup extended login buffer ****FAILED****.\n");
4429 qla2x00_free_exlogin_buffer(ha);
4430 }
4431
4432 return rval;
4433}
4434
4435/*
4436* qla2x00_free_exlogin_buffer
4437*
4438* Input:
4439* ha = adapter block pointer
4440*/
4441void
4442qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4443{
4444 if (ha->exlogin_buf) {
4445 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4446 ha->exlogin_buf, ha->exlogin_buf_dma);
4447 ha->exlogin_buf = NULL;
4448 ha->exlogin_size = 0;
4449 }
4450}
4451
99e1b683
QT		 4452static void
4453qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4454{
4455 u32 temp;
0645cb83 4456 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4457 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4458
d1e3635a
QT		 4459 if (max_cnt > vha->hw->max_exchg)
4460 max_cnt = vha->hw->max_exchg;
4461
99e1b683 4462 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4463 if (vha->ql2xiniexchg > max_cnt)
4464 vha->ql2xiniexchg = max_cnt;
4465
4466 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4467 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4468
99e1b683 4469 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4470 if (vha->ql2xexchoffld > max_cnt) {
4471 vha->ql2xexchoffld = max_cnt;
4472 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4473 }
99e1b683 4474
0645cb83
QT		 4475 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4476 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4477 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4478 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4479 if (temp > max_cnt) {
0645cb83
QT		 4480 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4481 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4482 temp = max_cnt;
0645cb83 4483 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4484 }
4485
4486 if (temp > FW_DEF_EXCHANGES_CNT)
4487 *ret_cnt = temp;
4488 }
4489}
4490
2f56a7f1
HM		 4491int
4492qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4493{
4494 int rval;
d1e3635a
QT		 4495 u16 size, max_cnt;
4496 u32 actual_cnt, totsz;
2f56a7f1
HM		 4497 struct qla_hw_data *ha = vha->hw;
4498
99e1b683
QT		 4499 if (!ha->flags.exchoffld_enabled)
4500 return QLA_SUCCESS;
4501
4502 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4503 return QLA_SUCCESS;
4504
2f56a7f1
HM		 4505 max_cnt = 0;
4506 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4507 if (rval != QLA_SUCCESS) {
4508 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4509 "Failed to get exlogin status.\n");
4510 return rval;
4511 }
4512
d1e3635a
QT		 4513 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4514 ql_log(ql_log_info, vha, 0xd014,
4515 "Actual exchange offload count: %d.\n", actual_cnt);
4516
4517 totsz = actual_cnt * size;
2f56a7f1 4518
d1e3635a 4519 if (totsz != ha->exchoffld_size) {
99e1b683 4520 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4521 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4522 ha->exchoffld_size = 0;
4523 ha->flags.exchoffld_enabled = 0;
4524 return QLA_SUCCESS;
4525 }
4526
d1e3635a 4527 ha->exchoffld_size = totsz;
99e1b683
QT		 4528
4529 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4530 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4531 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4532
4533 ql_log(ql_log_info, vha, 0xd017,
4534 "Exchange Buffers requested size = 0x%x\n",
4535 ha->exchoffld_size);
4536
4537 /* Get consistent memory for extended logins */
4538 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4539 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4540 if (!ha->exchoffld_buf) {
4541 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4542 "Failed to allocate memory for Exchange Offload.\n");
4543
4544 if (ha->max_exchg >
4545 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4546 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4547 } else if (ha->max_exchg >
4548 (FW_DEF_EXCHANGES_CNT + 512)) {
4549 ha->max_exchg -= 512;
4550 } else {
4551 ha->flags.exchoffld_enabled = 0;
4552 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4553 "Disabling Exchange offload due to lack of memory\n");
4554 }
4555 ha->exchoffld_size = 0;
4556
99e1b683
QT		 4557 return -ENOMEM;
4558 }
0645cb83
QT		 4559 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4560 /* pathological case */
4561 qla2x00_free_exchoffld_buffer(ha);
4562 ha->exchoffld_size = 0;
4563 ha->flags.exchoffld_enabled = 0;
4564 ql_log(ql_log_info, vha, 0xd016,
4565 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4566 ha->exchoffld_size, actual_cnt, size, totsz);
4567 return 0;
2f56a7f1
HM		 4568 }
4569
4570 /* Now configure the dma buffer */
99e1b683 4571 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4572 if (rval) {
4573 ql_log(ql_log_fatal, vha, 0xd02e,
4574 "Setup exchange offload buffer ****FAILED****.\n");
4575 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4576 } else {
4577 /* re-adjust number of target exchange */
4578 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4579
4580 if (qla_ini_mode_enabled(vha))
4581 icb->exchange_count = 0;
4582 else
0645cb83 4583 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4584 }
4585
4586 return rval;
4587}
4588
4589/*
4590* qla2x00_free_exchoffld_buffer
4591*
4592* Input:
4593* ha = adapter block pointer
4594*/
4595void
4596qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4597{
4598 if (ha->exchoffld_buf) {
4599 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4600 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4601 ha->exchoffld_buf = NULL;
4602 ha->exchoffld_size = 0;
4603 }
4604}
4605
1da177e4 4606/*
e30d1756
MI		 4607* qla2x00_free_fw_dump
4608* Frees fw dump stuff.
1da177e4
LT		 4609*
4610* Input:
7ec0effd 4611* ha = adapter block pointer
1da177e4 4612*/
a824ebb3 4613static void
e30d1756 4614qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4615{
a28d9e4e
JC		 4616 struct fwdt *fwdt = ha->fwdt;
4617 uint j;
4618
df613b96 4619 if (ha->fce)
f73cb695
CD		 4620 dma_free_coherent(&ha->pdev->dev,
4621 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4622
f73cb695
CD		 4623 if (ha->eft)
4624 dma_free_coherent(&ha->pdev->dev,
4625 EFT_SIZE, ha->eft, ha->eft_dma);
4626
4627 if (ha->fw_dump)
a7a167bf 4628 vfree(ha->fw_dump);
f73cb695 4629
e30d1756
MI		 4630 ha->fce = NULL;
4631 ha->fce_dma = 0;
3cf92f4b 4632 ha->flags.fce_enabled = 0;
e30d1756
MI		 4633 ha->eft = NULL;
4634 ha->eft_dma = 0;
dbe6f492 4635 ha->fw_dumped = false;
61f098dd 4636 ha->fw_dump_cap_flags = 0;
e30d1756 4637 ha->fw_dump_reading = 0;
f73cb695
CD		 4638 ha->fw_dump = NULL;
4639 ha->fw_dump_len = 0;
a28d9e4e
JC		 4640
4641 for (j = 0; j < 2; j++, fwdt++) {
4642 if (fwdt->template)
4643 vfree(fwdt->template);
4644 fwdt->template = NULL;
4645 fwdt->length = 0;
4646 }
e30d1756
MI		 4647}
4648
4649/*
4650* qla2x00_mem_free
4651* Frees all adapter allocated memory.
4652*
4653* Input:
4654* ha = adapter block pointer.
4655*/
4656static void
4657qla2x00_mem_free(struct qla_hw_data *ha)
4658{
4659 qla2x00_free_fw_dump(ha);
4660
81178772
SK		 4661 if (ha->mctp_dump)
4662 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4663 ha->mctp_dump_dma);
5365bf99 4664 ha->mctp_dump = NULL;
81178772 4665
75c1d48a 4666 mempool_destroy(ha->srb_mempool);
5365bf99 4667 ha->srb_mempool = NULL;
a7a167bf 4668
11bbc1d8
AV		 4669 if (ha->dcbx_tlv)
4670 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4671 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5365bf99 4672 ha->dcbx_tlv = NULL;
11bbc1d8 4673
ce0423f4
AV		 4674 if (ha->xgmac_data)
4675 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4676 ha->xgmac_data, ha->xgmac_data_dma);
5365bf99 4677 ha->xgmac_data = NULL;
ce0423f4 4678
1da177e4
LT		 4679 if (ha->sns_cmd)
4680 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4681 ha->sns_cmd, ha->sns_cmd_dma);
5365bf99
BVA		 4682 ha->sns_cmd = NULL;
4683 ha->sns_cmd_dma = 0;
1da177e4
LT		 4684
4685 if (ha->ct_sns)
4686 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4687 ha->ct_sns, ha->ct_sns_dma);
5365bf99
BVA		 4688 ha->ct_sns = NULL;
4689 ha->ct_sns_dma = 0;
1da177e4 4690
88729e53 4691 if (ha->sfp_data)
e4e3a2ce
QT		 4692 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4693 ha->sfp_data_dma);
5365bf99 4694 ha->sfp_data = NULL;
88729e53 4695
3f006ac3 4696 if (ha->flt)
162b805e
BVA		 4697 dma_free_coherent(&ha->pdev->dev,
4698 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE,
3f006ac3 4699 ha->flt, ha->flt_dma);
dc035d4e
BVA		 4700 ha->flt = NULL;
4701 ha->flt_dma = 0;
3f006ac3 4702
1da177e4
LT		 4703 if (ha->ms_iocb)
4704 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5365bf99
BVA		 4705 ha->ms_iocb = NULL;
4706 ha->ms_iocb_dma = 0;
1da177e4 4707
9f2475fe
SS		 4708 if (ha->sf_init_cb)
4709 dma_pool_free(ha->s_dma_pool,
4710 ha->sf_init_cb, ha->sf_init_cb_dma);
4711
b64b0e8f 4712 if (ha->ex_init_cb)
a9083016
GM		 4713 dma_pool_free(ha->s_dma_pool,
4714 ha->ex_init_cb, ha->ex_init_cb_dma);
5365bf99
BVA		 4715 ha->ex_init_cb = NULL;
4716 ha->ex_init_cb_dma = 0;
b64b0e8f 4717
5ff1d584
AV		 4718 if (ha->async_pd)
4719 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5365bf99
BVA		 4720 ha->async_pd = NULL;
4721 ha->async_pd_dma = 0;
5ff1d584 4722
75c1d48a 4723 dma_pool_destroy(ha->s_dma_pool);
5365bf99 4724 ha->s_dma_pool = NULL;
1da177e4 4725
1da177e4 4726 if (ha->gid_list)
642ef983
CD		 4727 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4728 ha->gid_list, ha->gid_list_dma);
5365bf99
BVA		 4729 ha->gid_list = NULL;
4730 ha->gid_list_dma = 0;
1da177e4 4731
a9083016
GM		 4732 if (IS_QLA82XX(ha)) {
4733 if (!list_empty(&ha->gbl_dsd_list)) {
4734 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4735
4736 /* clean up allocated prev pool */
4737 list_for_each_entry_safe(dsd_ptr,
4738 tdsd_ptr, &ha->gbl_dsd_list, list) {
4739 dma_pool_free(ha->dl_dma_pool,
4740 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4741 list_del(&dsd_ptr->list);
4742 kfree(dsd_ptr);
4743 }
4744 }
4745 }
4746
75c1d48a 4747 dma_pool_destroy(ha->dl_dma_pool);
5365bf99 4748 ha->dl_dma_pool = NULL;
a9083016 4749
75c1d48a 4750 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5365bf99 4751 ha->fcp_cmnd_dma_pool = NULL;
a9083016 4752
75c1d48a 4753 mempool_destroy(ha->ctx_mempool);
5365bf99 4754 ha->ctx_mempool = NULL;
a9083016 4755
26a77799 4756 if (ql2xenabledif && ha->dif_bundl_pool) {
50b81275
GM		 4757 struct dsd_dma *dsd, *nxt;
4758
4759 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4760 list) {
4761 list_del(&dsd->list);
4762 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4763 dsd->dsd_list_dma);
4764 ha->dif_bundle_dma_allocs--;
4765 kfree(dsd);
4766 ha->dif_bundle_kallocs--;
4767 ha->pool.unusable.count--;
4768 }
4769 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4770 list_del(&dsd->list);
4771 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4772 dsd->dsd_list_dma);
4773 ha->dif_bundle_dma_allocs--;
4774 kfree(dsd);
4775 ha->dif_bundle_kallocs--;
4776 }
4777 }
4778
0b3b6fe2 4779 dma_pool_destroy(ha->dif_bundl_pool);
dc035d4e 4780 ha->dif_bundl_pool = NULL;
50b81275 4781
2d70c103
NB		 4782 qlt_mem_free(ha);
4783
e315cd28
AC		 4784 if (ha->init_cb)
4785 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4786 ha->init_cb, ha->init_cb_dma);
5365bf99
BVA		 4787 ha->init_cb = NULL;
4788 ha->init_cb_dma = 0;
6a2cf8d3 4789
6d634067 4790 vfree(ha->optrom_buffer);
5365bf99 4791 ha->optrom_buffer = NULL;
6d634067 4792 kfree(ha->nvram);
5365bf99 4793 ha->nvram = NULL;
6d634067 4794 kfree(ha->npiv_info);
5365bf99 4795 ha->npiv_info = NULL;
6d634067 4796 kfree(ha->swl);
5365bf99 4797 ha->swl = NULL;
6d634067 4798 kfree(ha->loop_id_map);
9f2475fe
SS		 4799 ha->sf_init_cb = NULL;
4800 ha->sf_init_cb_dma = 0;
6a2cf8d3 4801 ha->loop_id_map = NULL;
e315cd28 4802}
1da177e4 4803
e315cd28
AC		 4804struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4805 struct qla_hw_data *ha)
4806{
4807 struct Scsi_Host *host;
4808 struct scsi_qla_host *vha = NULL;
854165f4 4809
e315cd28 4810 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4811 if (!host) {
7c3df132
SK		 4812 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4813 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4814 return NULL;
e315cd28
AC		 4815 }
4816
4817 /* Clear our data area */
4818 vha = shost_priv(host);
4819 memset(vha, 0, sizeof(scsi_qla_host_t));
4820
4821 vha->host = host;
4822 vha->host_no = host->host_no;
4823 vha->hw = ha;
4824
0645cb83
QT		 4825 vha->qlini_mode = ql2x_ini_mode;
4826 vha->ql2xexchoffld = ql2xexchoffld;
4827 vha->ql2xiniexchg = ql2xiniexchg;
4828
e315cd28
AC		 4829 INIT_LIST_HEAD(&vha->vp_fcports);
4830 INIT_LIST_HEAD(&vha->work_list);
4831 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4832 INIT_LIST_HEAD(&vha->qla_cmd_list);
4833 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4834 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4835 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4836 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4837 INIT_LIST_HEAD(&vha->gnl.fcports);
2d73ac61 4838 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4839 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4840
576bfde8
JC		 4841 INIT_LIST_HEAD(&vha->purex_list.head);
4842 spin_lock_init(&vha->purex_list.lock);
4843
f999f4c1 4844 spin_lock_init(&vha->work_lock);
8b2f5ff3 4845 spin_lock_init(&vha->cmd_list_lock);
726b8548 4846 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4847 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4848
2fdbc65e
BVA		 4849 vha->gnl.size = sizeof(struct get_name_list_extended) *
4850 (ha->max_loop_id + 1);
41dc529a
QT		 4851 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4852 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4853 if (!vha->gnl.l) {
83548fe2 4854 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a 4855 "Alloc failed for name list.\n");
26a77799 4856 scsi_host_put(vha->host);
41dc529a
QT		 4857 return NULL;
4858 }
f999f4c1 4859
a4239945
QT		 4860 /* todo: what about ext login? */
4861 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4862 vha->scan.l = vmalloc(vha->scan.size);
4863 if (!vha->scan.l) {
4864 ql_log(ql_log_fatal, vha, 0xd04a,
4865 "Alloc failed for scan database.\n");
4866 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4867 vha->gnl.l, vha->gnl.ldma);
26fa656e 4868 vha->gnl.l = NULL;
26a77799 4869 scsi_host_put(vha->host);
a4239945
QT		 4870 return NULL;
4871 }
f352eeb7 4872 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4873
e315cd28 4874 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4875 ql_dbg(ql_dbg_init, vha, 0x0041,
4876 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4877 vha->host, vha->hw, vha,
4878 dev_name(&(ha->pdev->dev)));
4879
e315cd28 4880 return vha;
1da177e4
LT		 4881}
4882
726b8548 4883struct qla_work_evt *
f999f4c1 4884qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4885{
4886 struct qla_work_evt *e;
feafb7b1
AE		 4887 uint8_t bail;
4888
5a263892
MW		 4889 if (test_bit(UNLOADING, &vha->dpc_flags))
4890 return NULL;
4891
feafb7b1
AE		 4892 QLA_VHA_MARK_BUSY(vha, bail);
4893 if (bail)
4894 return NULL;
0971de7f 4895
f999f4c1 4896 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4897 if (!e) {
4898 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4899 return NULL;
feafb7b1 4900 }
0971de7f
AV		 4901
4902 INIT_LIST_HEAD(&e->list);
4903 e->type = type;
4904 e->flags = QLA_EVT_FLAG_FREE;
4905 return e;
4906}
4907
726b8548 4908int
f999f4c1 4909qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4910{
f999f4c1 4911 unsigned long flags;
9b3e0f4d 4912 bool q = false;
0971de7f 4913
f999f4c1 4914 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4915 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4916
4917 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4918 q = true;
4919
f999f4c1 4920 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4921
9b3e0f4d
QT		 4922 if (q)
4923 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4924
0971de7f
AV		 4925 return QLA_SUCCESS;
4926}
4927
4928int
e315cd28 4929qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4930 u32 data)
4931{
4932 struct qla_work_evt *e;
4933
f999f4c1 4934 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4935 if (!e)
4936 return QLA_FUNCTION_FAILED;
4937
4938 e->u.aen.code = code;
4939 e->u.aen.data = data;
f999f4c1 4940 return qla2x00_post_work(vha, e);
0971de7f
AV		 4941}
4942
8a659571
AV		 4943int
4944qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4945{
4946 struct qla_work_evt *e;
4947
f999f4c1 4948 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4949 if (!e)
4950 return QLA_FUNCTION_FAILED;
4951
4952 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4953 return qla2x00_post_work(vha, e);
8a659571
AV		 4954}
4955
ac280b67
AV		 4956#define qla2x00_post_async_work(name, type) \
4957int qla2x00_post_async_##name##_work( \
4958 struct scsi_qla_host *vha, \
4959 fc_port_t *fcport, uint16_t *data) \
4960{ \
4961 struct qla_work_evt *e; \
4962 \
4963 e = qla2x00_alloc_work(vha, type); \
4964 if (!e) \
4965 return QLA_FUNCTION_FAILED; \
4966 \
4967 e->u.logio.fcport = fcport; \
4968 if (data) { \
4969 e->u.logio.data[0] = data[0]; \
4970 e->u.logio.data[1] = data[1]; \
4971 } \
6d674927 4972 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4973 return qla2x00_post_work(vha, e); \
4974}
4975
4976qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67 4977qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
5ff1d584 4978qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4979qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4980qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4981
3420d36c
AV		 4982int
4983qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4984{
4985 struct qla_work_evt *e;
4986
4987 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4988 if (!e)
4989 return QLA_FUNCTION_FAILED;
4990
4991 e->u.uevent.code = code;
4992 return qla2x00_post_work(vha, e);
4993}
4994
4995static void
4996qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4997{
4998 char event_string[40];
4999 char *envp[] = { event_string, NULL };
5000
5001 switch (code) {
5002 case QLA_UEVENT_CODE_FW_DUMP:
5003 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
5004 vha->host_no);
5005 break;
5006 default:
5007 /* do nothing */
5008 break;
5009 }
5010 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
5011}
5012
8ae6d9c7
GM		 5013int
5014qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
5015 uint32_t *data, int cnt)
5016{
5017 struct qla_work_evt *e;
5018
5019 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
5020 if (!e)
5021 return QLA_FUNCTION_FAILED;
5022
5023 e->u.aenfx.evtcode = evtcode;
5024 e->u.aenfx.count = cnt;
5025 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
5026 return qla2x00_post_work(vha, e);
5027}
5028
cd4ed6b4 5029void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 5030{
cd4ed6b4 5031 unsigned long flags;
726b8548 5032
cd4ed6b4
QT		 5033 if (IS_SW_RESV_ADDR(fcport->d_id))
5034 return;
726b8548 5035
cd4ed6b4
QT		 5036 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5037 if (fcport->disc_state == DSC_UPD_FCPORT) {
5038 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5039 return;
5040 }
5041 fcport->jiffies_at_registration = jiffies;
5042 fcport->sec_since_registration = 0;
5043 fcport->next_disc_state = DSC_DELETED;
27258a57 5044 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
cd4ed6b4
QT		 5045 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5046
5047 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5048}
5049
5050static
5051void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5052{
5053 unsigned long flags;
b5d15312 5054 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5055 struct qlt_plogi_ack_t *pla =
5056 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5057 uint8_t free_fcport = 0;
726b8548 5058
9cd883f0
QT		 5059 ql_dbg(ql_dbg_disc, vha, 0xffff,
5060 "%s %d %8phC enter\n",
5061 __func__, __LINE__, e->u.new_sess.port_name);
5062
726b8548
QT		 5063 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5064 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5065 if (fcport) {
5066 fcport->d_id = e->u.new_sess.id;
5067 if (pla) {
5068 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5069 memcpy(fcport->node_name,
5070 pla->iocb.u.isp24.u.plogi.node_name,
5071 WWN_SIZE);
726b8548
QT		 5072 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5073 /* we took an extra ref_count to prevent PLOGI ACK when
5074 * fcport/sess has not been created.
5075 */
5076 pla->ref_count--;
5077 }
5078 } else {
b5d15312 5079 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5080 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5081 if (fcport) {
5082 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5083 fcport->flags |= FCF_FABRIC_DEVICE;
5084 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
33b28357 5085
726b8548
QT		 5086 memcpy(fcport->port_name, e->u.new_sess.port_name,
5087 WWN_SIZE);
7f2a398d 5088
84ed362a
MH		 5089 fcport->fc4_type = e->u.new_sess.fc4_type;
5090 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) {
5091 fcport->fc4_type = FS_FC4TYPE_FCP;
7f2a398d 5092 fcport->n2n_flag = 1;
84ed362a
MH		 5093 if (vha->flags.nvme_enabled)
5094 fcport->fc4_type |= FS_FC4TYPE_NVME;
5095 }
7f2a398d 5096
b5d15312
QT		 5097 } else {
5098 ql_dbg(ql_dbg_disc, vha, 0xffff,
5099 "%s %8phC mem alloc fail.\n",
5100 __func__, e->u.new_sess.port_name);
5101
1df627b4
BVA		 5102 if (pla) {
5103 list_del(&pla->list);
b5d15312 5104 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5105 }
b5d15312
QT		 5106 return;
5107 }
5108
5109 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5110 /* search again to make sure no one else got ahead */
b5d15312
QT		 5111 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5112 e->u.new_sess.port_name, 1);
5113 if (tfcp) {
5114 /* should rarily happen */
5115 ql_dbg(ql_dbg_disc, vha, 0xffff,
5116 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5117 __func__, tfcp->port_name, tfcp->disc_state,
5118 tfcp->fw_login_state);
5119
5120 free_fcport = 1;
5121 } else {
726b8548
QT		 5122 list_add_tail(&fcport->list, &vha->vp_fcports);
5123
19759033
QT		 5124 }
5125 if (pla) {
5126 qlt_plogi_ack_link(vha, pla, fcport,
5127 QLT_PLOGI_LINK_SAME_WWN);
5128 pla->ref_count--;
726b8548
QT		 5129 }
5130 }
5131 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5132
5133 if (fcport) {
a4239945
QT		 5134 fcport->id_changed = 1;
5135 fcport->scan_state = QLA_FCPORT_FOUND;
8b5292bc 5136 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
a4239945
QT		 5137 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5138
5ef696aa 5139 if (pla) {
9cd883f0
QT		 5140 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5141 u16 wd3_lo;
5142
5143 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5144 fcport->local = 0;
5145 fcport->loop_id =
5146 le16_to_cpu(
5147 pla->iocb.u.isp24.nport_handle);
5148 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5149 wd3_lo =
5150 le16_to_cpu(
5151 pla->iocb.u.isp24.u.prli.wd3_lo);
5152
5153 if (wd3_lo & BIT_7)
5154 fcport->conf_compl_supported = 1;
5155
5156 if ((wd3_lo & BIT_4) == 0)
5157 fcport->port_type = FCT_INITIATOR;
5158 else
5159 fcport->port_type = FCT_TARGET;
5160 }
726b8548 5161 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5162 } else {
1c6cacf4
HR		 5163 fc_port_t *dfcp = NULL;
5164
5ef696aa
QT		 5165 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5166 tfcp = qla2x00_find_fcport_by_nportid(vha,
5167 &e->u.new_sess.id, 1);
5168 if (tfcp && (tfcp != fcport)) {
5169 /*
5170 * We have a conflict fcport with same NportID.
5171 */
5172 ql_dbg(ql_dbg_disc, vha, 0xffff,
5173 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5174 __func__, tfcp->port_name, tfcp->disc_state,
5175 tfcp->fw_login_state);
5176
5177 switch (tfcp->disc_state) {
5178 case DSC_DELETED:
5179 break;
5180 case DSC_DELETE_PEND:
5181 fcport->login_pause = 1;
5182 tfcp->conflict = fcport;
5183 break;
5184 default:
5185 fcport->login_pause = 1;
5186 tfcp->conflict = fcport;
1c6cacf4 5187 dfcp = tfcp;
5ef696aa
QT		 5188 break;
5189 }
5190 }
5191 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5192 if (dfcp)
5193 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5194
8777e431 5195 if (N2N_TOPO(vha->hw)) {
f3f1938b
QT		 5196 fcport->flags &= ~FCF_FABRIC_DEVICE;
5197 fcport->keep_nport_handle = 1;
8777e431 5198 if (vha->flags.nvme_enabled) {
84ed362a
MH		 5199 fcport->fc4_type =
5200 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP);
8777e431
QT		 5201 fcport->n2n_flag = 1;
5202 }
5203 fcport->fw_login_state = 0;
11efe875
QT		 5204
5205 schedule_delayed_work(&vha->scan.scan_work, 5);
8777e431
QT		 5206 } else {
5207 qla24xx_fcport_handle_login(vha, fcport);
5208 }
5ef696aa 5209 }
726b8548 5210 }
b5d15312
QT		 5211
5212 if (free_fcport) {
5213 qla2x00_free_fcport(fcport);
1df627b4
BVA		 5214 if (pla) {
5215 list_del(&pla->list);
b5d15312 5216 kmem_cache_free(qla_tgt_plogi_cachep, pla);
1df627b4 5217 }
b5d15312 5218 }
726b8548
QT		 5219}
5220
e374f9f5
QT		 5221static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5222{
5223 struct srb *sp = e->u.iosb.sp;
5224 int rval;
5225
5226 rval = qla2x00_start_sp(sp);
5227 if (rval != QLA_SUCCESS) {
5228 ql_dbg(ql_dbg_disc, vha, 0x2043,
5229 "%s: %s: Re-issue IOCB failed (%d).\n",
5230 __func__, sp->name, rval);
5231 qla24xx_sp_unmap(vha, sp);
5232 }
5233}
5234
ac280b67 5235void
e315cd28 5236qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5237{
f999f4c1
AV		 5238 struct qla_work_evt *e, *tmp;
5239 unsigned long flags;
5240 LIST_HEAD(work);
80676d05 5241 int rc;
0971de7f 5242
f999f4c1
AV		 5243 spin_lock_irqsave(&vha->work_lock, flags);
5244 list_splice_init(&vha->work_list, &work);
5245 spin_unlock_irqrestore(&vha->work_lock, flags);
5246
5247 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5248 rc = QLA_SUCCESS;
0971de7f
AV		 5249 switch (e->type) {
5250 case QLA_EVT_AEN:
e315cd28 5251 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5252 e->u.aen.code, e->u.aen.data);
5253 break;
8a659571
AV		 5254 case QLA_EVT_IDC_ACK:
5255 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5256 break;
ac280b67
AV		 5257 case QLA_EVT_ASYNC_LOGIN:
5258 qla2x00_async_login(vha, e->u.logio.fcport,
5259 e->u.logio.data);
5260 break;
ac280b67 5261 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5262 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67 5263 break;
5ff1d584
AV		 5264 case QLA_EVT_ASYNC_ADISC:
5265 qla2x00_async_adisc(vha, e->u.logio.fcport,
5266 e->u.logio.data);
5267 break;
3420d36c
AV		 5268 case QLA_EVT_UEVENT:
5269 qla2x00_uevent_emit(vha, e->u.uevent.code);
5270 break;
8ae6d9c7
GM		 5271 case QLA_EVT_AENFX:
5272 qlafx00_process_aen(vha, e);
5273 break;
726b8548
QT		 5274 case QLA_EVT_GPNID:
5275 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5276 break;
e374f9f5
QT		 5277 case QLA_EVT_UNMAP:
5278 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5279 break;
9b3e0f4d
QT		 5280 case QLA_EVT_RELOGIN:
5281 qla2x00_relogin(vha);
5282 break;
726b8548
QT		 5283 case QLA_EVT_NEW_SESS:
5284 qla24xx_create_new_sess(vha, e);
5285 break;
5286 case QLA_EVT_GPDB:
5287 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5288 e->u.fcport.opt);
5289 break;
a5d42f4c
DG		 5290 case QLA_EVT_PRLI:
5291 qla24xx_async_prli(vha, e->u.fcport.fcport);
5292 break;
726b8548
QT		 5293 case QLA_EVT_GPSC:
5294 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5295 break;
726b8548
QT		 5296 case QLA_EVT_GNL:
5297 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5298 break;
5299 case QLA_EVT_NACK:
5300 qla24xx_do_nack_work(vha, e);
5301 break;
11aea16a 5302 case QLA_EVT_ASYNC_PRLO:
80676d05 5303 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5304 break;
5305 case QLA_EVT_ASYNC_PRLO_DONE:
5306 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5307 e->u.logio.data);
5308 break;
a4239945 5309 case QLA_EVT_GPNFT:
33b28357
QT		 5310 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5311 e->u.gpnft.sp);
a4239945
QT		 5312 break;
5313 case QLA_EVT_GPNFT_DONE:
5314 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5315 break;
5316 case QLA_EVT_GNNFT_DONE:
5317 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5318 break;
5319 case QLA_EVT_GNNID:
5320 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5321 break;
5322 case QLA_EVT_GFPNID:
5323 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5324 break;
e374f9f5
QT		 5325 case QLA_EVT_SP_RETRY:
5326 qla_sp_retry(vha, e);
cc28e0ac
QT		 5327 break;
5328 case QLA_EVT_IIDMA:
5329 qla_do_iidma_work(vha, e->u.fcport.fcport);
5330 break;
8777e431
QT		 5331 case QLA_EVT_ELS_PLOGI:
5332 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5333 e->u.fcport.fcport, false);
5334 break;
0971de7f 5335 }
80676d05
QT		 5336
5337 if (rc == EAGAIN) {
5338 /* put 'work' at head of 'vha->work_list' */
5339 spin_lock_irqsave(&vha->work_lock, flags);
5340 list_splice(&work, &vha->work_list);
5341 spin_unlock_irqrestore(&vha->work_lock, flags);
5342 break;
5343 }
5344 list_del_init(&e->list);
0971de7f
AV		 5345 if (e->flags & QLA_EVT_FLAG_FREE)
5346 kfree(e);
feafb7b1
AE		 5347
5348 /* For each work completed decrement vha ref count */
5349 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5350 }
e315cd28 5351}
f999f4c1 5352
9b3e0f4d
QT		 5353int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5354{
5355 struct qla_work_evt *e;
5356
5357 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5358
5359 if (!e) {
5360 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5361 return QLA_FUNCTION_FAILED;
5362 }
5363
5364 return qla2x00_post_work(vha, e);
5365}
5366
e315cd28
AC		 5367/* Relogins all the fcports of a vport
5368 * Context: dpc thread
5369 */
5370void qla2x00_relogin(struct scsi_qla_host *vha)
5371{
5372 fc_port_t *fcport;
23dd98a6 5373 int status, relogin_needed = 0;
726b8548 5374 struct event_arg ea;
e315cd28
AC		 5375
5376 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5377 /*
5378 * If the port is not ONLINE then try to login
5379 * to it if we haven't run out of retries.
5380 */
5ff1d584 5381 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5382 fcport->login_retry) {
5383 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5384 fcport->disc_state == DSC_LOGIN_COMPLETE)
5385 continue;
e315cd28 5386
23dd98a6
QT		 5387 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5388 fcport->disc_state == DSC_DELETE_PEND) {
5389 relogin_needed = 1;
5390 } else {
5391 if (vha->hw->current_topology != ISP_CFG_NL) {
5392 memset(&ea, 0, sizeof(ea));
23dd98a6 5393 ea.fcport = fcport;
897def20 5394 qla24xx_handle_relogin_event(vha, &ea);
23dd98a6
QT		 5395 } else if (vha->hw->current_topology ==
5396 ISP_CFG_NL) {
5397 fcport->login_retry--;
5398 status =
5399 qla2x00_local_device_login(vha,
5400 fcport);
5401 if (status == QLA_SUCCESS) {
5402 fcport->old_loop_id =
5403 fcport->loop_id;
5404 ql_dbg(ql_dbg_disc, vha, 0x2003,
5405 "Port login OK: logged in ID 0x%x.\n",
5406 fcport->loop_id);
5407 qla2x00_update_fcport
5408 (vha, fcport);
5409 } else if (status == 1) {
5410 set_bit(RELOGIN_NEEDED,
5411 &vha->dpc_flags);
5412 /* retry the login again */
5413 ql_dbg(ql_dbg_disc, vha, 0x2007,
5414 "Retrying %d login again loop_id 0x%x.\n",
5415 fcport->login_retry,
5416 fcport->loop_id);
5417 } else {
5418 fcport->login_retry = 0;
5419 }
e315cd28 5420
23dd98a6
QT		 5421 if (fcport->login_retry == 0 &&
5422 status != QLA_SUCCESS)
5423 qla2x00_clear_loop_id(fcport);
5424 }
e315cd28 5425 }
e315cd28
AC		 5426 }
5427 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5428 break;
0971de7f 5429 }
9b3e0f4d 5430
23dd98a6
QT		 5431 if (relogin_needed)
5432 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5433
9b3e0f4d
QT		 5434 ql_dbg(ql_dbg_disc, vha, 0x400e,
5435 "Relogin end.\n");
0971de7f
AV		 5436}
5437
7d613ac6
SV		 5438/* Schedule work on any of the dpc-workqueues */
5439void
5440qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5441{
5442 struct qla_hw_data *ha = base_vha->hw;
5443
5444 switch (work_code) {
5445 case MBA_IDC_AEN: /* 0x8200 */
5446 if (ha->dpc_lp_wq)
5447 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5448 break;
5449
5450 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5451 if (!ha->flags.nic_core_reset_hdlr_active) {
5452 if (ha->dpc_hp_wq)
5453 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5454 } else
5455 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5456 "NIC Core reset is already active. Skip "
5457 "scheduling it again.\n");
5458 break;
5459 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5460 if (ha->dpc_hp_wq)
5461 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5462 break;
5463 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5464 if (ha->dpc_hp_wq)
5465 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5466 break;
5467 default:
5468 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5469 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5470 }
5471
5472 return;
5473}
5474
5475/* Work: Perform NIC Core Unrecoverable state handling */
5476void
5477qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5478{
5479 struct qla_hw_data *ha =
2ad1b67c 5480 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5481 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5482 uint32_t dev_state = 0;
5483
5484 qla83xx_idc_lock(base_vha, 0);
5485 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5486 qla83xx_reset_ownership(base_vha);
5487 if (ha->flags.nic_core_reset_owner) {
5488 ha->flags.nic_core_reset_owner = 0;
5489 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5490 QLA8XXX_DEV_FAILED);
5491 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5492 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5493 }
5494 qla83xx_idc_unlock(base_vha, 0);
5495}
5496
5497/* Work: Execute IDC state handler */
5498void
5499qla83xx_idc_state_handler_work(struct work_struct *work)
5500{
5501 struct qla_hw_data *ha =
2ad1b67c 5502 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5503 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5504 uint32_t dev_state = 0;
5505
5506 qla83xx_idc_lock(base_vha, 0);
5507 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5508 if (dev_state == QLA8XXX_DEV_FAILED ||
5509 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5510 qla83xx_idc_state_handler(base_vha);
5511 qla83xx_idc_unlock(base_vha, 0);
5512}
5513
fa492630 5514static int
7d613ac6
SV		 5515qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5516{
5517 int rval = QLA_SUCCESS;
5518 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5519 uint32_t heart_beat_counter1, heart_beat_counter2;
5520
5521 do {
5522 if (time_after(jiffies, heart_beat_wait)) {
5523 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5524 "Nic Core f/w is not alive.\n");
5525 rval = QLA_FUNCTION_FAILED;
5526 break;
5527 }
5528
5529 qla83xx_idc_lock(base_vha, 0);
5530 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5531 &heart_beat_counter1);
5532 qla83xx_idc_unlock(base_vha, 0);
5533 msleep(100);
5534 qla83xx_idc_lock(base_vha, 0);
5535 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5536 &heart_beat_counter2);
5537 qla83xx_idc_unlock(base_vha, 0);
5538 } while (heart_beat_counter1 == heart_beat_counter2);
5539
5540 return rval;
5541}
5542
5543/* Work: Perform NIC Core Reset handling */
5544void
5545qla83xx_nic_core_reset_work(struct work_struct *work)
5546{
5547 struct qla_hw_data *ha =
5548 container_of(work, struct qla_hw_data, nic_core_reset);
5549 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5550 uint32_t dev_state = 0;
5551
81178772
SK		 5552 if (IS_QLA2031(ha)) {
5553 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5554 ql_log(ql_log_warn, base_vha, 0xb081,
5555 "Failed to dump mctp\n");
5556 return;
5557 }
5558
7d613ac6
SV		 5559 if (!ha->flags.nic_core_reset_hdlr_active) {
5560 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5561 qla83xx_idc_lock(base_vha, 0);
5562 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5563 &dev_state);
5564 qla83xx_idc_unlock(base_vha, 0);
5565 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5566 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5567 "Nic Core f/w is alive.\n");
5568 return;
5569 }
5570 }
5571
5572 ha->flags.nic_core_reset_hdlr_active = 1;
5573 if (qla83xx_nic_core_reset(base_vha)) {
5574 /* NIC Core reset failed. */
5575 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5576 "NIC Core reset failed.\n");
5577 }
5578 ha->flags.nic_core_reset_hdlr_active = 0;
5579 }
5580}
5581
5582/* Work: Handle 8200 IDC aens */
5583void
5584qla83xx_service_idc_aen(struct work_struct *work)
5585{
5586 struct qla_hw_data *ha =
5587 container_of(work, struct qla_hw_data, idc_aen);
5588 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5589 uint32_t dev_state, idc_control;
5590
5591 qla83xx_idc_lock(base_vha, 0);
5592 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5593 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5594 qla83xx_idc_unlock(base_vha, 0);
5595 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5596 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5597 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5598 "Application requested NIC Core Reset.\n");
5599 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5600 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5601 QLA_SUCCESS) {
5602 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5603 "Other protocol driver requested NIC Core Reset.\n");
5604 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5605 }
5606 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5607 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5608 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5609 }
5610}
5611
5612static void
5613qla83xx_wait_logic(void)
5614{
5615 int i;
5616
5617 /* Yield CPU */
5618 if (!in_interrupt()) {
5619 /*
5620 * Wait about 200ms before retrying again.
5621 * This controls the number of retries for single
5622 * lock operation.
5623 */
5624 msleep(100);
5625 schedule();
5626 } else {
5627 for (i = 0; i < 20; i++)
5628 cpu_relax(); /* This a nop instr on i386 */
5629 }
5630}
5631
fa492630 5632static int
7d613ac6
SV		 5633qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5634{
5635 int rval;
5636 uint32_t data;
5637 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5638 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5639 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5640
6c315553
SK		 5641 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5642 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5643
5644 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5645 if (rval)
5646 return rval;
5647
5648 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5649 return QLA_SUCCESS;
5650 } else {
5651 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5652 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5653 data);
5654 if (rval)
5655 return rval;
5656
5657 msleep(200);
5658
5659 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5660 &data);
5661 if (rval)
5662 return rval;
5663
5664 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5665 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5666 ~(idc_lck_rcvry_stage_mask));
5667 rval = qla83xx_wr_reg(base_vha,
5668 QLA83XX_IDC_LOCK_RECOVERY, data);
5669 if (rval)
5670 return rval;
5671
5672 /* Forcefully perform IDC UnLock */
5673 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5674 &data);
5675 if (rval)
5676 return rval;
5677 /* Clear lock-id by setting 0xff */
5678 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5679 0xff);
5680 if (rval)
5681 return rval;
5682 /* Clear lock-recovery by setting 0x0 */
5683 rval = qla83xx_wr_reg(base_vha,
5684 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5685 if (rval)
5686 return rval;
5687 } else
5688 return QLA_SUCCESS;
5689 }
5690
5691 return rval;
5692}
5693
fa492630 5694static int
7d613ac6
SV		 5695qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5696{
5697 int rval = QLA_SUCCESS;
5698 uint32_t o_drv_lockid, n_drv_lockid;
5699 unsigned long lock_recovery_timeout;
5700
5701 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5702retry_lockid:
5703 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5704 if (rval)
5705 goto exit;
5706
5707 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5708 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5709 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5710 return QLA_SUCCESS;
5711 else
5712 return QLA_FUNCTION_FAILED;
5713 }
5714
5715 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5716 if (rval)
5717 goto exit;
5718
5719 if (o_drv_lockid == n_drv_lockid) {
5720 qla83xx_wait_logic();
5721 goto retry_lockid;
5722 } else
5723 return QLA_SUCCESS;
5724
5725exit:
5726 return rval;
5727}
5728
5729void
5730qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5731{
7d613ac6 5732 uint32_t data;
6c315553 5733 uint32_t lock_owner;
7d613ac6
SV		 5734 struct qla_hw_data *ha = base_vha->hw;
5735
5736 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5737retry_lock:
5738 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5739 == QLA_SUCCESS) {
5740 if (data) {
5741 /* Setting lock-id to our function-number */
5742 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5743 ha->portnum);
5744 } else {
6c315553
SK		 5745 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5746 &lock_owner);
7d613ac6 5747 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5748 "Failed to acquire IDC lock, acquired by %d, "
5749 "retrying...\n", lock_owner);
7d613ac6
SV		 5750
5751 /* Retry/Perform IDC-Lock recovery */
5752 if (qla83xx_idc_lock_recovery(base_vha)
5753 == QLA_SUCCESS) {
5754 qla83xx_wait_logic();
5755 goto retry_lock;
5756 } else
5757 ql_log(ql_log_warn, base_vha, 0xb075,
5758 "IDC Lock recovery FAILED.\n");
5759 }
5760
5761 }
5762
5763 return;
7d613ac6
SV		 5764}
5765
4879237c
JC		 5766static bool
5767qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha,
5768 struct purex_entry_24xx *purex)
5769{
5770 char fwstr[16];
5771 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0];
84f7d2e7 5772 struct port_database_24xx *pdb;
4879237c
JC		 5773
5774 /* Domain Controller is always logged-out. */
5775 /* if RDP request is not from Domain Controller: */
5776 if (sid != 0xfffc01)
5777 return false;
5778
5779 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid);
5780
84f7d2e7
HM		 5781 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL);
5782 if (!pdb) {
5783 ql_dbg(ql_dbg_init, vha, 0x0181,
5784 "%s: Failed allocate pdb\n", __func__);
7ffa5b93
BVA		 5785 } else if (qla24xx_get_port_database(vha,
5786 le16_to_cpu(purex->nport_handle), pdb)) {
84f7d2e7
HM		 5787 ql_dbg(ql_dbg_init, vha, 0x0181,
5788 "%s: Failed get pdb sid=%x\n", __func__, sid);
5789 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE &&
5790 pdb->current_login_state != PDS_PRLI_COMPLETE) {
5791 ql_dbg(ql_dbg_init, vha, 0x0181,
5792 "%s: Port not logged in sid=%#x\n", __func__, sid);
5793 } else {
5794 /* RDP request is from logged in port */
5795 kfree(pdb);
5796 return false;
5797 }
5798 kfree(pdb);
5799
4879237c
JC		 5800 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr));
5801 fwstr[strcspn(fwstr, " ")] = 0;
5802 /* if FW version allows RDP response length upto 2048 bytes: */
5803 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0)
5804 return false;
5805
5806 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr);
5807
5808 /* RDP response length is to be reduced to maximum 256 bytes */
5809 return true;
5810}
5811
d83a80ee
JC		 5812static uint
5813qla25xx_rdp_port_speed_capability(struct qla_hw_data *ha)
5814{
5815 if (IS_CNA_CAPABLE(ha))
5816 return RDP_PORT_SPEED_10GB;
5817
8b01e4db
HM		 5818 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
5819 unsigned int speeds = 0;
d83a80ee 5820
8b01e4db
HM		 5821 if (ha->max_supported_speed == 2) {
5822 if (ha->min_supported_speed <= 6)
5823 speeds |= RDP_PORT_SPEED_64GB;
5824 }
5825
5826 if (ha->max_supported_speed == 2 ||
5827 ha->max_supported_speed == 1) {
5828 if (ha->min_supported_speed <= 5)
5829 speeds |= RDP_PORT_SPEED_32GB;
5830 }
5831
5832 if (ha->max_supported_speed == 2 ||
5833 ha->max_supported_speed == 1 ||
5834 ha->max_supported_speed == 0) {
5835 if (ha->min_supported_speed <= 4)
5836 speeds |= RDP_PORT_SPEED_16GB;
5837 }
5838
5839 if (ha->max_supported_speed == 1 ||
5840 ha->max_supported_speed == 0) {
5841 if (ha->min_supported_speed <= 3)
5842 speeds |= RDP_PORT_SPEED_8GB;
5843 }
5844
5845 if (ha->max_supported_speed == 0) {
5846 if (ha->min_supported_speed <= 2)
5847 speeds |= RDP_PORT_SPEED_4GB;
5848 }
5849
5850 return speeds;
d83a80ee
JC		 5851 }
5852
5853 if (IS_QLA2031(ha))
5854 return RDP_PORT_SPEED_16GB|RDP_PORT_SPEED_8GB|
5855 RDP_PORT_SPEED_4GB;
5856
5857 if (IS_QLA25XX(ha))
5858 return RDP_PORT_SPEED_8GB|RDP_PORT_SPEED_4GB|
5859 RDP_PORT_SPEED_2GB|RDP_PORT_SPEED_1GB;
5860
5861 if (IS_QLA24XX_TYPE(ha))
5862 return RDP_PORT_SPEED_4GB|RDP_PORT_SPEED_2GB|
5863 RDP_PORT_SPEED_1GB;
5864
5865 if (IS_QLA23XX(ha))
5866 return RDP_PORT_SPEED_2GB|RDP_PORT_SPEED_1GB;
5867
5868 return RDP_PORT_SPEED_1GB;
5869}
5870
5871static uint
5872qla25xx_rdp_port_speed_currently(struct qla_hw_data *ha)
5873{
5874 switch (ha->link_data_rate) {
5875 case PORT_SPEED_1GB:
5876 return RDP_PORT_SPEED_1GB;
5877
5878 case PORT_SPEED_2GB:
5879 return RDP_PORT_SPEED_2GB;
5880
5881 case PORT_SPEED_4GB:
5882 return RDP_PORT_SPEED_4GB;
5883
5884 case PORT_SPEED_8GB:
5885 return RDP_PORT_SPEED_8GB;
5886
5887 case PORT_SPEED_10GB:
5888 return RDP_PORT_SPEED_10GB;
5889
5890 case PORT_SPEED_16GB:
5891 return RDP_PORT_SPEED_16GB;
5892
5893 case PORT_SPEED_32GB:
5894 return RDP_PORT_SPEED_32GB;
5895
8b01e4db
HM		 5896 case PORT_SPEED_64GB:
5897 return RDP_PORT_SPEED_64GB;
5898
d83a80ee
JC		 5899 default:
5900 return RDP_PORT_SPEED_UNKNOWN;
5901 }
5902}
5903
5904/*
5905 * Function Name: qla24xx_process_purex_iocb
5906 *
5907 * Description:
5908 * Prepare a RDP response and send to Fabric switch
5909 *
5910 * PARAMETERS:
5911 * vha: SCSI qla host
5912 * purex: RDP request received by HBA
5913 */
62e9dd17
SS		 5914void qla24xx_process_purex_rdp(struct scsi_qla_host *vha,
5915 struct purex_item *item)
d83a80ee
JC		 5916{
5917 struct qla_hw_data *ha = vha->hw;
62e9dd17
SS		 5918 struct purex_entry_24xx *purex =
5919 (struct purex_entry_24xx *)&item->iocb;
d83a80ee
JC		 5920 dma_addr_t rsp_els_dma;
5921 dma_addr_t rsp_payload_dma;
5922 dma_addr_t stat_dma;
5923 dma_addr_t bbc_dma;
5924 dma_addr_t sfp_dma;
5925 struct els_entry_24xx *rsp_els = NULL;
5926 struct rdp_rsp_payload *rsp_payload = NULL;
5927 struct link_statistics *stat = NULL;
5928 struct buffer_credit_24xx *bbc = NULL;
5929 uint8_t *sfp = NULL;
5930 uint16_t sfp_flags = 0;
4879237c 5931 uint rsp_payload_length = sizeof(*rsp_payload);
576bfde8 5932 int rval;
d83a80ee
JC		 5933
5934 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180,
5935 "%s: Enter\n", __func__);
5936
5937 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181,
5938 "-------- ELS REQ -------\n");
5939 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182,
ab053c09 5940 purex, sizeof(*purex));
d83a80ee 5941
4879237c
JC		 5942 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) {
5943 rsp_payload_length =
5944 offsetof(typeof(*rsp_payload), optical_elmt_desc);
5945 ql_dbg(ql_dbg_init, vha, 0x0181,
5946 "Reducing RSP payload length to %u bytes...\n",
5947 rsp_payload_length);
5948 }
5949
d83a80ee
JC		 5950 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els),
5951 &rsp_els_dma, GFP_KERNEL);
09e382bc
JC		 5952 if (!rsp_els) {
5953 ql_log(ql_log_warn, vha, 0x0183,
5954 "Failed allocate dma buffer ELS RSP.\n");
d83a80ee 5955 goto dealloc;
09e382bc 5956 }
d83a80ee
JC		 5957
5958 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
5959 &rsp_payload_dma, GFP_KERNEL);
09e382bc
JC		 5960 if (!rsp_payload) {
5961 ql_log(ql_log_warn, vha, 0x0184,
5962 "Failed allocate dma buffer ELS RSP payload.\n");
d83a80ee 5963 goto dealloc;
09e382bc 5964 }
d83a80ee
JC		 5965
5966 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
5967 &sfp_dma, GFP_KERNEL);
5968
5969 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat),
5970 &stat_dma, GFP_KERNEL);
5971
5972 bbc = dma_alloc_coherent(&ha->pdev->dev, sizeof(*bbc),
5973 &bbc_dma, GFP_KERNEL);
5974
5975 /* Prepare Response IOCB */
d83a80ee
JC		 5976 rsp_els->entry_type = ELS_IOCB_TYPE;
5977 rsp_els->entry_count = 1;
5978 rsp_els->sys_define = 0;
5979 rsp_els->entry_status = 0;
5980 rsp_els->handle = 0;
5981 rsp_els->nport_handle = purex->nport_handle;
7ffa5b93 5982 rsp_els->tx_dsd_count = cpu_to_le16(1);
d83a80ee
JC		 5983 rsp_els->vp_index = purex->vp_idx;
5984 rsp_els->sof_type = EST_SOFI3;
5985 rsp_els->rx_xchg_address = purex->rx_xchg_addr;
5986 rsp_els->rx_dsd_count = 0;
5987 rsp_els->opcode = purex->els_frame_payload[0];
5988
09e382bc
JC		 5989 rsp_els->d_id[0] = purex->s_id[0];
5990 rsp_els->d_id[1] = purex->s_id[1];
5991 rsp_els->d_id[2] = purex->s_id[2];
d83a80ee 5992
7ffa5b93 5993 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC);
d83a80ee 5994 rsp_els->rx_byte_count = 0;
4879237c 5995 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length);
d83a80ee
JC		 5996
5997 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address);
5998 rsp_els->tx_len = rsp_els->tx_byte_count;
5999
6000 rsp_els->rx_address = 0;
6001 rsp_els->rx_len = 0;
6002
d83a80ee
JC		 6003 /* Prepare Response Payload */
6004 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */
7ffa5b93
BVA		 6005 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) -
6006 sizeof(rsp_payload->hdr));
d83a80ee
JC		 6007
6008 /* Link service Request Info Descriptor */
6009 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1);
6010 rsp_payload->ls_req_info_desc.desc_len =
6011 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc));
6012 rsp_payload->ls_req_info_desc.req_payload_word_0 =
6013 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6014
6015 /* Link service Request Info Descriptor 2 */
6016 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1);
6017 rsp_payload->ls_req_info_desc2.desc_len =
6018 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2));
6019 rsp_payload->ls_req_info_desc2.req_payload_word_0 =
6020 cpu_to_be32p((uint32_t *)purex->els_frame_payload);
6021
770538c3
QT		 6022
6023 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000);
6024 rsp_payload->sfp_diag_desc.desc_len =
6025 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc));
6026
d83a80ee
JC		 6027 if (sfp) {
6028 /* SFP Flags */
6029 memset(sfp, 0, SFP_RTDI_LEN);
6030 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0);
6031 if (!rval) {
6032 /* SFP Flags bits 3-0: Port Tx Laser Type */
6033 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5))
6034 sfp_flags |= BIT_0; /* short wave */
6035 else if (sfp[0] & BIT_1)
6036 sfp_flags |= BIT_1; /* long wave 1310nm */
6037 else if (sfp[1] & BIT_4)
6038 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */
6039 }
6040
6041 /* SFP Type */
6042 memset(sfp, 0, SFP_RTDI_LEN);
6043 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0);
6044 if (!rval) {
6045 sfp_flags |= BIT_4; /* optical */
6046 if (sfp[0] == 0x3)
6047 sfp_flags |= BIT_6; /* sfp+ */
6048 }
6049
770538c3
QT		 6050 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags);
6051
d83a80ee
JC		 6052 /* SFP Diagnostics */
6053 memset(sfp, 0, SFP_RTDI_LEN);
6054 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0);
770538c3 6055 if (!rval) {
7ffa5b93 6056 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
d83a80ee
JC		 6057 rsp_payload->sfp_diag_desc.temperature = trx[0];
6058 rsp_payload->sfp_diag_desc.vcc = trx[1];
6059 rsp_payload->sfp_diag_desc.tx_bias = trx[2];
6060 rsp_payload->sfp_diag_desc.tx_power = trx[3];
6061 rsp_payload->sfp_diag_desc.rx_power = trx[4];
d83a80ee
JC		 6062 }
6063 }
6064
6065 /* Port Speed Descriptor */
6066 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001);
6067 rsp_payload->port_speed_desc.desc_len =
6068 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc));
6069 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16(
6070 qla25xx_rdp_port_speed_capability(ha));
6071 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16(
6072 qla25xx_rdp_port_speed_currently(ha));
6073
770538c3
QT		 6074 /* Link Error Status Descriptor */
6075 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002);
6076 rsp_payload->ls_err_desc.desc_len =
6077 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc));
6078
d83a80ee
JC		 6079 if (stat) {
6080 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0);
6081 if (!rval) {
d83a80ee 6082 rsp_payload->ls_err_desc.link_fail_cnt =
7ffa5b93 6083 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt));
d83a80ee 6084 rsp_payload->ls_err_desc.loss_sync_cnt =
7ffa5b93 6085 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt));
d83a80ee 6086 rsp_payload->ls_err_desc.loss_sig_cnt =
7ffa5b93 6087 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt));
d83a80ee 6088 rsp_payload->ls_err_desc.prim_seq_err_cnt =
7ffa5b93 6089 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt));
d83a80ee 6090 rsp_payload->ls_err_desc.inval_xmit_word_cnt =
7ffa5b93 6091 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt));
d83a80ee 6092 rsp_payload->ls_err_desc.inval_crc_cnt =
7ffa5b93 6093 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt));
d83a80ee
JC		 6094 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6;
6095 }
6096 }
6097
6098 /* Portname Descriptor */
6099 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003);
6100 rsp_payload->port_name_diag_desc.desc_len =
6101 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc));
6102 memcpy(rsp_payload->port_name_diag_desc.WWNN,
6103 vha->node_name,
6104 sizeof(rsp_payload->port_name_diag_desc.WWNN));
6105 memcpy(rsp_payload->port_name_diag_desc.WWPN,
6106 vha->port_name,
6107 sizeof(rsp_payload->port_name_diag_desc.WWPN));
6108
6109 /* F-Port Portname Descriptor */
6110 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003);
6111 rsp_payload->port_name_direct_desc.desc_len =
6112 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc));
6113 memcpy(rsp_payload->port_name_direct_desc.WWNN,
6114 vha->fabric_node_name,
6115 sizeof(rsp_payload->port_name_direct_desc.WWNN));
6116 memcpy(rsp_payload->port_name_direct_desc.WWPN,
6117 vha->fabric_port_name,
6118 sizeof(rsp_payload->port_name_direct_desc.WWPN));
6119
770538c3
QT		 6120 /* Bufer Credit Descriptor */
6121 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006);
6122 rsp_payload->buffer_credit_desc.desc_len =
6123 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc));
6124 rsp_payload->buffer_credit_desc.fcport_b2b = 0;
6125 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0);
6126 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0);
6127
d83a80ee
JC		 6128 if (bbc) {
6129 memset(bbc, 0, sizeof(*bbc));
6130 rval = qla24xx_get_buffer_credits(vha, bbc, bbc_dma);
6131 if (!rval) {
d83a80ee
JC		 6132 rsp_payload->buffer_credit_desc.fcport_b2b =
6133 cpu_to_be32(LSW(bbc->parameter[0]));
d83a80ee
JC		 6134 }
6135 }
6136
4879237c
JC		 6137 if (rsp_payload_length < sizeof(*rsp_payload))
6138 goto send;
6139
770538c3
QT		 6140 /* Optical Element Descriptor, Temperature */
6141 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007);
6142 rsp_payload->optical_elmt_desc[0].desc_len =
6143 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6144 /* Optical Element Descriptor, Voltage */
6145 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007);
6146 rsp_payload->optical_elmt_desc[1].desc_len =
6147 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6148 /* Optical Element Descriptor, Tx Bias Current */
6149 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007);
6150 rsp_payload->optical_elmt_desc[2].desc_len =
6151 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6152 /* Optical Element Descriptor, Tx Power */
6153 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007);
6154 rsp_payload->optical_elmt_desc[3].desc_len =
6155 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6156 /* Optical Element Descriptor, Rx Power */
6157 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007);
6158 rsp_payload->optical_elmt_desc[4].desc_len =
6159 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc));
6160
d83a80ee
JC		 6161 if (sfp) {
6162 memset(sfp, 0, SFP_RTDI_LEN);
6163 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0);
6164 if (!rval) {
7ffa5b93 6165 __be16 *trx = (__force __be16 *)sfp; /* already be16 */
d83a80ee
JC		 6166
6167 /* Optical Element Descriptor, Temperature */
d83a80ee
JC		 6168 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0];
6169 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1];
6170 rsp_payload->optical_elmt_desc[0].high_warn = trx[2];
6171 rsp_payload->optical_elmt_desc[0].low_warn = trx[3];
6172 rsp_payload->optical_elmt_desc[0].element_flags =
6173 cpu_to_be32(1 << 28);
6174
6175 /* Optical Element Descriptor, Voltage */
d83a80ee
JC		 6176 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4];
6177 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5];
6178 rsp_payload->optical_elmt_desc[1].high_warn = trx[6];
6179 rsp_payload->optical_elmt_desc[1].low_warn = trx[7];
6180 rsp_payload->optical_elmt_desc[1].element_flags =
6181 cpu_to_be32(2 << 28);
6182
6183 /* Optical Element Descriptor, Tx Bias Current */
d83a80ee
JC		 6184 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8];
6185 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9];
6186 rsp_payload->optical_elmt_desc[2].high_warn = trx[10];
6187 rsp_payload->optical_elmt_desc[2].low_warn = trx[11];
6188 rsp_payload->optical_elmt_desc[2].element_flags =
6189 cpu_to_be32(3 << 28);
6190
6191 /* Optical Element Descriptor, Tx Power */
d83a80ee
JC		 6192 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12];
6193 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13];
6194 rsp_payload->optical_elmt_desc[3].high_warn = trx[14];
6195 rsp_payload->optical_elmt_desc[3].low_warn = trx[15];
6196 rsp_payload->optical_elmt_desc[3].element_flags =
6197 cpu_to_be32(4 << 28);
6198
6199 /* Optical Element Descriptor, Rx Power */
d83a80ee
JC		 6200 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16];
6201 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17];
6202 rsp_payload->optical_elmt_desc[4].high_warn = trx[18];
6203 rsp_payload->optical_elmt_desc[4].low_warn = trx[19];
6204 rsp_payload->optical_elmt_desc[4].element_flags =
6205 cpu_to_be32(5 << 28);
6206 }
6207
6208 memset(sfp, 0, SFP_RTDI_LEN);
6209 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0);
6210 if (!rval) {
6211 /* Temperature high/low alarm/warning */
6212 rsp_payload->optical_elmt_desc[0].element_flags |=
6213 cpu_to_be32(
6214 (sfp[0] >> 7 & 1) << 3 |
6215 (sfp[0] >> 6 & 1) << 2 |
6216 (sfp[4] >> 7 & 1) << 1 |
6217 (sfp[4] >> 6 & 1) << 0);
6218
6219 /* Voltage high/low alarm/warning */
6220 rsp_payload->optical_elmt_desc[1].element_flags |=
6221 cpu_to_be32(
6222 (sfp[0] >> 5 & 1) << 3 |
6223 (sfp[0] >> 4 & 1) << 2 |
6224 (sfp[4] >> 5 & 1) << 1 |
6225 (sfp[4] >> 4 & 1) << 0);
6226
6227 /* Tx Bias Current high/low alarm/warning */
6228 rsp_payload->optical_elmt_desc[2].element_flags |=
6229 cpu_to_be32(
6230 (sfp[0] >> 3 & 1) << 3 |
6231 (sfp[0] >> 2 & 1) << 2 |
6232 (sfp[4] >> 3 & 1) << 1 |
6233 (sfp[4] >> 2 & 1) << 0);
6234
6235 /* Tx Power high/low alarm/warning */
6236 rsp_payload->optical_elmt_desc[3].element_flags |=
6237 cpu_to_be32(
6238 (sfp[0] >> 1 & 1) << 3 |
6239 (sfp[0] >> 0 & 1) << 2 |
6240 (sfp[4] >> 1 & 1) << 1 |
6241 (sfp[4] >> 0 & 1) << 0);
6242
6243 /* Rx Power high/low alarm/warning */
6244 rsp_payload->optical_elmt_desc[4].element_flags |=
6245 cpu_to_be32(
6246 (sfp[1] >> 7 & 1) << 3 |
6247 (sfp[1] >> 6 & 1) << 2 |
6248 (sfp[5] >> 7 & 1) << 1 |
6249 (sfp[5] >> 6 & 1) << 0);
6250 }
6251 }
6252
770538c3
QT		 6253 /* Optical Product Data Descriptor */
6254 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008);
6255 rsp_payload->optical_prod_desc.desc_len =
6256 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc));
6257
d83a80ee
JC		 6258 if (sfp) {
6259 memset(sfp, 0, SFP_RTDI_LEN);
6260 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0);
6261 if (!rval) {
d83a80ee
JC		 6262 memcpy(rsp_payload->optical_prod_desc.vendor_name,
6263 sfp + 0,
6264 sizeof(rsp_payload->optical_prod_desc.vendor_name));
6265 memcpy(rsp_payload->optical_prod_desc.part_number,
6266 sfp + 20,
6267 sizeof(rsp_payload->optical_prod_desc.part_number));
6268 memcpy(rsp_payload->optical_prod_desc.revision,
6269 sfp + 36,
6270 sizeof(rsp_payload->optical_prod_desc.revision));
6271 memcpy(rsp_payload->optical_prod_desc.serial_number,
6272 sfp + 48,
6273 sizeof(rsp_payload->optical_prod_desc.serial_number));
6274 }
6275
6276 memset(sfp, 0, SFP_RTDI_LEN);
6277 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0);
6278 if (!rval) {
6279 memcpy(rsp_payload->optical_prod_desc.date,
6280 sfp + 0,
6281 sizeof(rsp_payload->optical_prod_desc.date));
6282 }
6283 }
6284
6285send:
6286 ql_dbg(ql_dbg_init, vha, 0x0183,
6287 "Sending ELS Response to RDP Request...\n");
6288 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184,
6289 "-------- ELS RSP -------\n");
6290 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185,
ab053c09 6291 rsp_els, sizeof(*rsp_els));
d83a80ee
JC		 6292 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186,
6293 "-------- ELS RSP PAYLOAD -------\n");
6294 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187,
ab053c09 6295 rsp_payload, rsp_payload_length);
d83a80ee
JC		 6296
6297 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0);
6298
09e382bc 6299 if (rval) {
d83a80ee 6300 ql_log(ql_log_warn, vha, 0x0188,
09e382bc
JC		 6301 "%s: iocb failed to execute -> %x\n", __func__, rval);
6302 } else if (rsp_els->comp_status) {
d83a80ee 6303 ql_log(ql_log_warn, vha, 0x0189,
09e382bc
JC		 6304 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n",
6305 __func__, rsp_els->comp_status,
6306 rsp_els->error_subcode_1, rsp_els->error_subcode_2);
d83a80ee
JC		 6307 } else {
6308 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__);
6309 }
6310
6311dealloc:
d83a80ee
JC		 6312 if (bbc)
6313 dma_free_coherent(&ha->pdev->dev, sizeof(*bbc),
6314 bbc, bbc_dma);
6315 if (stat)
6316 dma_free_coherent(&ha->pdev->dev, sizeof(*stat),
6317 stat, stat_dma);
6318 if (sfp)
6319 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN,
6320 sfp, sfp_dma);
6321 if (rsp_payload)
6322 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload),
6323 rsp_payload, rsp_payload_dma);
6324 if (rsp_els)
6325 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els),
6326 rsp_els, rsp_els_dma);
576bfde8 6327}
d83a80ee 6328
62e9dd17
SS		 6329void
6330qla24xx_free_purex_item(struct purex_item *item)
6331{
6332 if (item == &item->vha->default_item)
6333 memset(&item->vha->default_item, 0, sizeof(struct purex_item));
6334 else
6335 kfree(item);
6336}
6337
576bfde8
JC		 6338void qla24xx_process_purex_list(struct purex_list *list)
6339{
6340 struct list_head head = LIST_HEAD_INIT(head);
6341 struct purex_item *item, *next;
6342 ulong flags;
6343
6344 spin_lock_irqsave(&list->lock, flags);
6345 list_splice_init(&list->head, &head);
6346 spin_unlock_irqrestore(&list->lock, flags);
6347
6348 list_for_each_entry_safe(item, next, &head, list) {
6349 list_del(&item->list);
62e9dd17
SS		 6350 item->process_item(item->vha, item);
6351 qla24xx_free_purex_item(item);
576bfde8 6352 }
d83a80ee
JC		 6353}
6354
7d613ac6
SV		 6355void
6356qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
6357{
5897cb2f
BVA		 6358#if 0
6359 uint16_t options = (requester_id << 15) | BIT_7;
6360#endif
6361 uint16_t retry;
7d613ac6
SV		 6362 uint32_t data;
6363 struct qla_hw_data *ha = base_vha->hw;
6364
6365 /* IDC-unlock implementation using driver-unlock/lock-id
6366 * remote registers
6367 */
6368 retry = 0;
6369retry_unlock:
6370 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
6371 == QLA_SUCCESS) {
6372 if (data == ha->portnum) {
6373 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
6374 /* Clearing lock-id by setting 0xff */
6375 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
6376 } else if (retry < 10) {
6377 /* SV: XXX: IDC unlock retrying needed here? */
6378
6379 /* Retry for IDC-unlock */
6380 qla83xx_wait_logic();
6381 retry++;
6382 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 6383 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 6384 goto retry_unlock;
6385 }
6386 } else if (retry < 10) {
6387 /* Retry for IDC-unlock */
6388 qla83xx_wait_logic();
6389 retry++;
6390 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 6391 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 6392 goto retry_unlock;
6393 }
6394
6395 return;
6396
5897cb2f 6397#if 0
7d613ac6
SV		 6398 /* XXX: IDC-unlock implementation using access-control mbx */
6399 retry = 0;
6400retry_unlock2:
6401 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
6402 if (retry < 10) {
6403 /* Retry for IDC-unlock */
6404 qla83xx_wait_logic();
6405 retry++;
6406 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 6407 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 6408 goto retry_unlock2;
6409 }
6410 }
6411
6412 return;
5897cb2f 6413#endif
7d613ac6
SV		 6414}
6415
6416int
6417__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6418{
6419 int rval = QLA_SUCCESS;
6420 struct qla_hw_data *ha = vha->hw;
6421 uint32_t drv_presence;
6422
6423 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6424 if (rval == QLA_SUCCESS) {
6425 drv_presence |= (1 << ha->portnum);
6426 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6427 drv_presence);
6428 }
6429
6430 return rval;
6431}
6432
6433int
6434qla83xx_set_drv_presence(scsi_qla_host_t *vha)
6435{
6436 int rval = QLA_SUCCESS;
6437
6438 qla83xx_idc_lock(vha, 0);
6439 rval = __qla83xx_set_drv_presence(vha);
6440 qla83xx_idc_unlock(vha, 0);
6441
6442 return rval;
6443}
6444
6445int
6446__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6447{
6448 int rval = QLA_SUCCESS;
6449 struct qla_hw_data *ha = vha->hw;
6450 uint32_t drv_presence;
6451
6452 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6453 if (rval == QLA_SUCCESS) {
6454 drv_presence &= ~(1 << ha->portnum);
6455 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6456 drv_presence);
6457 }
6458
6459 return rval;
6460}
6461
6462int
6463qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
6464{
6465 int rval = QLA_SUCCESS;
6466
6467 qla83xx_idc_lock(vha, 0);
6468 rval = __qla83xx_clear_drv_presence(vha);
6469 qla83xx_idc_unlock(vha, 0);
6470
6471 return rval;
6472}
6473
fa492630 6474static void
7d613ac6
SV		 6475qla83xx_need_reset_handler(scsi_qla_host_t *vha)
6476{
6477 struct qla_hw_data *ha = vha->hw;
6478 uint32_t drv_ack, drv_presence;
6479 unsigned long ack_timeout;
6480
6481 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
6482 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
6483 while (1) {
6484 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6485 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 6486 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 6487 break;
6488
6489 if (time_after_eq(jiffies, ack_timeout)) {
6490 ql_log(ql_log_warn, vha, 0xb067,
6491 "RESET ACK TIMEOUT! drv_presence=0x%x "
6492 "drv_ack=0x%x\n", drv_presence, drv_ack);
6493 /*
6494 * The function(s) which did not ack in time are forced
6495 * to withdraw any further participation in the IDC
6496 * reset.
6497 */
6498 if (drv_ack != drv_presence)
6499 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
6500 drv_ack);
6501 break;
6502 }
6503
6504 qla83xx_idc_unlock(vha, 0);
6505 msleep(1000);
6506 qla83xx_idc_lock(vha, 0);
6507 }
6508
6509 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
6510 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
6511}
6512
fa492630 6513static int
7d613ac6
SV		 6514qla83xx_device_bootstrap(scsi_qla_host_t *vha)
6515{
6516 int rval = QLA_SUCCESS;
6517 uint32_t idc_control;
6518
6519 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
6520 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
6521
6522 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
6523 __qla83xx_get_idc_control(vha, &idc_control);
6524 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
6525 __qla83xx_set_idc_control(vha, 0);
6526
6527 qla83xx_idc_unlock(vha, 0);
6528 rval = qla83xx_restart_nic_firmware(vha);
6529 qla83xx_idc_lock(vha, 0);
6530
6531 if (rval != QLA_SUCCESS) {
6532 ql_log(ql_log_fatal, vha, 0xb06a,
6533 "Failed to restart NIC f/w.\n");
6534 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
6535 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
6536 } else {
6537 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
6538 "Success in restarting nic f/w.\n");
6539 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
6540 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
6541 }
6542
6543 return rval;
6544}
6545
6546/* Assumes idc_lock always held on entry */
6547int
6548qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
6549{
6550 struct qla_hw_data *ha = base_vha->hw;
6551 int rval = QLA_SUCCESS;
6552 unsigned long dev_init_timeout;
6553 uint32_t dev_state;
6554
6555 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
6556 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
6557
6558 while (1) {
6559
6560 if (time_after_eq(jiffies, dev_init_timeout)) {
6561 ql_log(ql_log_warn, base_vha, 0xb06e,
6562 "Initialization TIMEOUT!\n");
6563 /* Init timeout. Disable further NIC Core
6564 * communication.
6565 */
6566 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
6567 QLA8XXX_DEV_FAILED);
6568 ql_log(ql_log_info, base_vha, 0xb06f,
6569 "HW State: FAILED.\n");
6570 }
6571
6572 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6573 switch (dev_state) {
6574 case QLA8XXX_DEV_READY:
6575 if (ha->flags.nic_core_reset_owner)
6576 qla83xx_idc_audit(base_vha,
6577 IDC_AUDIT_COMPLETION);
6578 ha->flags.nic_core_reset_owner = 0;
6579 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
6580 "Reset_owner reset by 0x%x.\n",
6581 ha->portnum);
6582 goto exit;
6583 case QLA8XXX_DEV_COLD:
6584 if (ha->flags.nic_core_reset_owner)
6585 rval = qla83xx_device_bootstrap(base_vha);
6586 else {
6587 /* Wait for AEN to change device-state */
6588 qla83xx_idc_unlock(base_vha, 0);
6589 msleep(1000);
6590 qla83xx_idc_lock(base_vha, 0);
6591 }
6592 break;
6593 case QLA8XXX_DEV_INITIALIZING:
6594 /* Wait for AEN to change device-state */
6595 qla83xx_idc_unlock(base_vha, 0);
6596 msleep(1000);
6597 qla83xx_idc_lock(base_vha, 0);
6598 break;
6599 case QLA8XXX_DEV_NEED_RESET:
6600 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
6601 qla83xx_need_reset_handler(base_vha);
6602 else {
6603 /* Wait for AEN to change device-state */
6604 qla83xx_idc_unlock(base_vha, 0);
6605 msleep(1000);
6606 qla83xx_idc_lock(base_vha, 0);
6607 }
6608 /* reset timeout value after need reset handler */
6609 dev_init_timeout = jiffies +
6610 (ha->fcoe_dev_init_timeout * HZ);
6611 break;
6612 case QLA8XXX_DEV_NEED_QUIESCENT:
6613 /* XXX: DEBUG for now */
6614 qla83xx_idc_unlock(base_vha, 0);
6615 msleep(1000);
6616 qla83xx_idc_lock(base_vha, 0);
6617 break;
6618 case QLA8XXX_DEV_QUIESCENT:
6619 /* XXX: DEBUG for now */
6620 if (ha->flags.quiesce_owner)
6621 goto exit;
6622
6623 qla83xx_idc_unlock(base_vha, 0);
6624 msleep(1000);
6625 qla83xx_idc_lock(base_vha, 0);
6626 dev_init_timeout = jiffies +
6627 (ha->fcoe_dev_init_timeout * HZ);
6628 break;
6629 case QLA8XXX_DEV_FAILED:
6630 if (ha->flags.nic_core_reset_owner)
6631 qla83xx_idc_audit(base_vha,
6632 IDC_AUDIT_COMPLETION);
6633 ha->flags.nic_core_reset_owner = 0;
6634 __qla83xx_clear_drv_presence(base_vha);
6635 qla83xx_idc_unlock(base_vha, 0);
6636 qla8xxx_dev_failed_handler(base_vha);
6637 rval = QLA_FUNCTION_FAILED;
6638 qla83xx_idc_lock(base_vha, 0);
6639 goto exit;
6640 case QLA8XXX_BAD_VALUE:
6641 qla83xx_idc_unlock(base_vha, 0);
6642 msleep(1000);
6643 qla83xx_idc_lock(base_vha, 0);
6644 break;
6645 default:
6646 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6647 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6648 qla83xx_idc_unlock(base_vha, 0);
6649 qla8xxx_dev_failed_handler(base_vha);
6650 rval = QLA_FUNCTION_FAILED;
6651 qla83xx_idc_lock(base_vha, 0);
6652 goto exit;
6653 }
6654 }
6655
6656exit:
6657 return rval;
6658}
6659
f3ddac19
CD		 6660void
6661qla2x00_disable_board_on_pci_error(struct work_struct *work)
6662{
6663 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6664 board_disable);
6665 struct pci_dev *pdev = ha->pdev;
6666 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6667
6668 ql_log(ql_log_warn, base_vha, 0x015b,
6669 "Disabling adapter.\n");
6670
efdb5760
SC		 6671 if (!atomic_read(&pdev->enable_cnt)) {
6672 ql_log(ql_log_info, base_vha, 0xfffc,
6673 "PCI device disabled, no action req for PCI error=%lx\n",
6674 base_vha->pci_flags);
6675 return;
6676 }
6677
856e152a
MW		 6678 /*
6679 * if UNLOADING flag is already set, then continue unload,
6680 * where it was set first.
6681 */
6682 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags))
6683 return;
726b8548 6684
856e152a 6685 qla2x00_wait_for_sess_deletion(base_vha);
f3ddac19
CD		 6686
6687 qla2x00_delete_all_vps(ha, base_vha);
6688
6689 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6690
6691 qla2x00_dfs_remove(base_vha);
6692
6693 qla84xx_put_chip(base_vha);
6694
6695 if (base_vha->timer_active)
6696 qla2x00_stop_timer(base_vha);
6697
6698 base_vha->flags.online = 0;
6699
6700 qla2x00_destroy_deferred_work(ha);
6701
6702 /*
6703 * Do not try to stop beacon blink as it will issue a mailbox
6704 * command.
6705 */
6706 qla2x00_free_sysfs_attr(base_vha, false);
6707
6708 fc_remove_host(base_vha->host);
6709
6710 scsi_remove_host(base_vha->host);
6711
6712 base_vha->flags.init_done = 0;
6713 qla25xx_delete_queues(base_vha);
f3ddac19 6714 qla2x00_free_fcports(base_vha);
093df737 6715 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6716 qla2x00_mem_free(ha);
6717 qla82xx_md_free(base_vha);
6718 qla2x00_free_queues(ha);
6719
f3ddac19
CD		 6720 qla2x00_unmap_iobases(ha);
6721
6722 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6723 pci_disable_pcie_error_reporting(pdev);
6724 pci_disable_device(pdev);
f3ddac19 6725
beb9e315
JL		 6726 /*
6727 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6728 */
f3ddac19
CD		 6729}
6730
1da177e4
LT		 6731/**************************************************************************
6732* qla2x00_do_dpc
6733* This kernel thread is a task that is schedule by the interrupt handler
6734* to perform the background processing for interrupts.
6735*
6736* Notes:
6737* This task always run in the context of a kernel thread. It
6738* is kick-off by the driver's detect code and starts up
6739* up one per adapter. It immediately goes to sleep and waits for
6740* some fibre event. When either the interrupt handler or
6741* the timer routine detects a event it will one of the task
6742* bits then wake us up.
6743**************************************************************************/
6744static int
6745qla2x00_do_dpc(void *data)
6746{
e315cd28
AC		 6747 scsi_qla_host_t *base_vha;
6748 struct qla_hw_data *ha;
d7459527
MH		 6749 uint32_t online;
6750 struct qla_qpair *qpair;
1da177e4 6751
e315cd28
AC		 6752 ha = (struct qla_hw_data *)data;
6753 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6754
8698a745 6755 set_user_nice(current, MIN_NICE);
1da177e4 6756
563585ec 6757 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6758 while (!kthread_should_stop()) {
7c3df132
SK		 6759 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6760 "DPC handler sleeping.\n");
1da177e4 6761
39a11240 6762 schedule();
1da177e4 6763
c142caf0
AV		 6764 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6765 goto end_loop;
1da177e4 6766
85880801 6767 if (ha->flags.eeh_busy) {
7c3df132
SK		 6768 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6769 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6770 goto end_loop;
85880801
AV		 6771 }
6772
1da177e4
LT		 6773 ha->dpc_active = 1;
6774
5f28d2d7
SK		 6775 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6776 "DPC handler waking up, dpc_flags=0x%lx.\n",
6777 base_vha->dpc_flags);
1da177e4 6778
a29b3dd7
JC		 6779 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6780 break;
6781
7ec0effd
AD		 6782 if (IS_P3P_TYPE(ha)) {
6783 if (IS_QLA8044(ha)) {
6784 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6785 &base_vha->dpc_flags)) {
6786 qla8044_idc_lock(ha);
6787 qla8044_wr_direct(base_vha,
6788 QLA8044_CRB_DEV_STATE_INDEX,
6789 QLA8XXX_DEV_FAILED);
6790 qla8044_idc_unlock(ha);
6791 ql_log(ql_log_info, base_vha, 0x4004,
6792 "HW State: FAILED.\n");
6793 qla8044_device_state_handler(base_vha);
6794 continue;
6795 }
6796
6797 } else {
6798 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6799 &base_vha->dpc_flags)) {
6800 qla82xx_idc_lock(ha);
6801 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6802 QLA8XXX_DEV_FAILED);
6803 qla82xx_idc_unlock(ha);
6804 ql_log(ql_log_info, base_vha, 0x0151,
6805 "HW State: FAILED.\n");
6806 qla82xx_device_state_handler(base_vha);
6807 continue;
6808 }
a9083016
GM		 6809 }
6810
6811 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6812 &base_vha->dpc_flags)) {
6813
7c3df132
SK		 6814 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6815 "FCoE context reset scheduled.\n");
a9083016
GM		 6816 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6817 &base_vha->dpc_flags))) {
6818 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6819 /* FCoE-ctx reset failed.
6820 * Escalate to chip-reset
6821 */
6822 set_bit(ISP_ABORT_NEEDED,
6823 &base_vha->dpc_flags);
6824 }
6825 clear_bit(ABORT_ISP_ACTIVE,
6826 &base_vha->dpc_flags);
6827 }
6828
7c3df132
SK		 6829 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6830 "FCoE context reset end.\n");
a9083016 6831 }
8ae6d9c7
GM		 6832 } else if (IS_QLAFX00(ha)) {
6833 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6834 &base_vha->dpc_flags)) {
6835 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6836 "Firmware Reset Recovery\n");
6837 if (qlafx00_reset_initialize(base_vha)) {
6838 /* Failed. Abort isp later. */
6839 if (!test_bit(UNLOADING,
f92f82d6 6840 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6841 set_bit(ISP_UNRECOVERABLE,
6842 &base_vha->dpc_flags);
6843 ql_dbg(ql_dbg_dpc, base_vha,
6844 0x4021,
6845 "Reset Recovery Failed\n");
f92f82d6 6846 }
8ae6d9c7
GM		 6847 }
6848 }
6849
6850 if (test_and_clear_bit(FX00_TARGET_SCAN,
6851 &base_vha->dpc_flags)) {
6852 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6853 "ISPFx00 Target Scan scheduled\n");
6854 if (qlafx00_rescan_isp(base_vha)) {
6855 if (!test_bit(UNLOADING,
6856 &base_vha->dpc_flags))
6857 set_bit(ISP_UNRECOVERABLE,
6858 &base_vha->dpc_flags);
6859 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6860 "ISPFx00 Target Scan Failed\n");
6861 }
6862 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6863 "ISPFx00 Target Scan End\n");
6864 }
e8f5e95d
AB		 6865 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6866 &base_vha->dpc_flags)) {
6867 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6868 "ISPFx00 Host Info resend scheduled\n");
6869 qlafx00_fx_disc(base_vha,
6870 &base_vha->hw->mr.fcport,
6871 FXDISC_REG_HOST_INFO);
6872 }
a9083016
GM		 6873 }
6874
e4e3a2ce 6875 if (test_and_clear_bit(DETECT_SFP_CHANGE,
b0f18eee
AV		 6876 &base_vha->dpc_flags)) {
6877 /* Semantic:
6878 * - NO-OP -- await next ISP-ABORT. Preferred method
6879 * to minimize disruptions that will occur
6880 * when a forced chip-reset occurs.
6881 * - Force -- ISP-ABORT scheduled.
6882 */
6883 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */
e4e3a2ce
QT		 6884 }
6885
b08abbd9
QT		 6886 if (test_and_clear_bit
6887 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6888 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6889 bool do_reset = true;
6890
0645cb83 6891 switch (base_vha->qlini_mode) {
93eca613
QT		 6892 case QLA2XXX_INI_MODE_ENABLED:
6893 break;
6894 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6895 if (!qla_tgt_mode_enabled(base_vha) &&
6896 !ha->flags.fw_started)
93eca613
QT		 6897 do_reset = false;
6898 break;
6899 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6900 if (!qla_dual_mode_enabled(base_vha) &&
6901 !ha->flags.fw_started)
93eca613
QT		 6902 do_reset = false;
6903 break;
6904 default:
6905 break;
6906 }
1da177e4 6907
93eca613 6908 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6909 &base_vha->dpc_flags))) {
f839544c 6910 base_vha->flags.online = 1;
93eca613
QT		 6911 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6912 "ISP abort scheduled.\n");
a9083016 6913 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6914 /* failed. retry later */
6915 set_bit(ISP_ABORT_NEEDED,
e315cd28 6916 &base_vha->dpc_flags);
99363ef8 6917 }
e315cd28
AC		 6918 clear_bit(ABORT_ISP_ACTIVE,
6919 &base_vha->dpc_flags);
93eca613
QT		 6920 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6921 "ISP abort end.\n");
99363ef8 6922 }
1da177e4
LT		 6923 }
6924
576bfde8
JC		 6925 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) {
6926 if (atomic_read(&base_vha->loop_state) == LOOP_READY) {
6927 qla24xx_process_purex_list
6928 (&base_vha->purex_list);
6929 clear_bit(PROCESS_PUREX_IOCB,
6930 &base_vha->dpc_flags);
6931 }
d83a80ee
JC		 6932 }
6933
a394aac8
DJ		 6934 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6935 &base_vha->dpc_flags)) {
e315cd28 6936 qla2x00_update_fcports(base_vha);
c9c5ced9 6937 }
d97994dc 6938
8ae6d9c7
GM		 6939 if (IS_QLAFX00(ha))
6940 goto loop_resync_check;
6941
579d12b5 6942 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6943 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6944 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6945 if (IS_P3P_TYPE(ha)) {
6946 if (IS_QLA82XX(ha))
6947 qla82xx_device_state_handler(base_vha);
6948 if (IS_QLA8044(ha))
6949 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6950 clear_bit(ISP_QUIESCE_NEEDED,
6951 &base_vha->dpc_flags);
6952 if (!ha->flags.quiesce_owner) {
6953 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6954 if (IS_QLA82XX(ha)) {
6955 qla82xx_idc_lock(ha);
6956 qla82xx_clear_qsnt_ready(
6957 base_vha);
6958 qla82xx_idc_unlock(ha);
6959 } else if (IS_QLA8044(ha)) {
6960 qla8044_idc_lock(ha);
6961 qla8044_clear_qsnt_ready(
6962 base_vha);
6963 qla8044_idc_unlock(ha);
6964 }
8fcd6b8b
CD		 6965 }
6966 } else {
6967 clear_bit(ISP_QUIESCE_NEEDED,
6968 &base_vha->dpc_flags);
6969 qla2x00_quiesce_io(base_vha);
579d12b5 6970 }
7c3df132
SK		 6971 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6972 "Quiescence mode end.\n");
579d12b5
SK		 6973 }
6974
e315cd28 6975 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6976 &base_vha->dpc_flags) &&
e315cd28 6977 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6978
7c3df132
SK		 6979 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6980 "Reset marker scheduled.\n");
e315cd28
AC		 6981 qla2x00_rst_aen(base_vha);
6982 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6983 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6984 "Reset marker end.\n");
1da177e4
LT		 6985 }
6986
6987 /* Retry each device up to login retry count */
4005a995 6988 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6989 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6990 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6991
4005a995
QT		 6992 if (!base_vha->relogin_jif ||
6993 time_after_eq(jiffies, base_vha->relogin_jif)) {
6994 base_vha->relogin_jif = jiffies + HZ;
6995 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6996
9b3e0f4d 6997 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6998 "Relogin scheduled.\n");
9b3e0f4d 6999 qla24xx_post_relogin_work(base_vha);
4005a995 7000 }
1da177e4 7001 }
8ae6d9c7 7002loop_resync_check:
e315cd28 7003 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 7004 &base_vha->dpc_flags)) {
1da177e4 7005
7c3df132
SK		 7006 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
7007 "Loop resync scheduled.\n");
1da177e4
LT		 7008
7009 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 7010 &base_vha->dpc_flags))) {
1da177e4 7011
52c82823 7012 qla2x00_loop_resync(base_vha);
1da177e4 7013
e315cd28
AC		 7014 clear_bit(LOOP_RESYNC_ACTIVE,
7015 &base_vha->dpc_flags);
1da177e4
LT		 7016 }
7017
7c3df132
SK		 7018 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
7019 "Loop resync end.\n");
1da177e4
LT		 7020 }
7021
8ae6d9c7
GM		 7022 if (IS_QLAFX00(ha))
7023 goto intr_on_check;
7024
e315cd28
AC		 7025 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
7026 atomic_read(&base_vha->loop_state) == LOOP_READY) {
7027 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
7028 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 7029 }
7030
8ae6d9c7 7031intr_on_check:
1da177e4 7032 if (!ha->interrupts_on)
fd34f556 7033 ha->isp_ops->enable_intrs(ha);
1da177e4 7034
e315cd28 7035 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 7036 &base_vha->dpc_flags)) {
7037 if (ha->beacon_blink_led == 1)
7038 ha->isp_ops->beacon_blink(base_vha);
7039 }
f6df144c 7040
d7459527
MH		 7041 /* qpair online check */
7042 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
7043 &base_vha->dpc_flags)) {
7044 if (ha->flags.eeh_busy ||
7045 ha->flags.pci_channel_io_perm_failure)
7046 online = 0;
7047 else
7048 online = 1;
7049
7050 mutex_lock(&ha->mq_lock);
7051 list_for_each_entry(qpair, &base_vha->qp_list,
7052 qp_list_elem)
7053 qpair->online = online;
7054 mutex_unlock(&ha->mq_lock);
7055 }
7056
8b4673ba
QT		 7057 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
7058 &base_vha->dpc_flags)) {
deeae7a6
DG		 7059 ql_log(ql_log_info, base_vha, 0xffffff,
7060 "nvme: SET ZIO Activity exchange threshold to %d.\n",
7061 ha->nvme_last_rptd_aen);
8b4673ba
QT		 7062 if (qla27xx_set_zio_threshold(base_vha,
7063 ha->nvme_last_rptd_aen)) {
deeae7a6 7064 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 7065 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
7066 ha->nvme_last_rptd_aen);
deeae7a6
DG		 7067 }
7068 }
7069
8b4673ba
QT		 7070 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
7071 &base_vha->dpc_flags)) {
7072 ql_log(ql_log_info, base_vha, 0xffffff,
7073 "SET ZIO Activity exchange threshold to %d.\n",
7074 ha->last_zio_threshold);
7075 qla27xx_set_zio_threshold(base_vha,
7076 ha->last_zio_threshold);
7077 }
7078
8ae6d9c7
GM		 7079 if (!IS_QLAFX00(ha))
7080 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 7081
48acad09
QT		 7082 if (test_and_clear_bit(N2N_LINK_RESET,
7083 &base_vha->dpc_flags)) {
7084 qla2x00_lip_reset(base_vha);
7085 }
7086
1da177e4 7087 ha->dpc_active = 0;
c142caf0 7088end_loop:
563585ec 7089 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 7090 } /* End of while(1) */
563585ec 7091 __set_current_state(TASK_RUNNING);
1da177e4 7092
7c3df132
SK		 7093 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
7094 "DPC handler exiting.\n");
1da177e4
LT		 7095
7096 /*
7097 * Make sure that nobody tries to wake us up again.
7098 */
1da177e4
LT		 7099 ha->dpc_active = 0;
7100
ac280b67
AV		 7101 /* Cleanup any residual CTX SRBs. */
7102 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
7103
39a11240
CH		 7104 return 0;
7105}
7106
7107void
e315cd28 7108qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 7109{
e315cd28 7110 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 7111 struct task_struct *t = ha->dpc_thread;
7112
e315cd28 7113 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 7114 wake_up_process(t);
1da177e4
LT		 7115}
7116
1da177e4
LT		 7117/*
7118* qla2x00_rst_aen
7119* Processes asynchronous reset.
7120*
7121* Input:
7122* ha = adapter block pointer.
7123*/
7124static void
e315cd28 7125qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 7126{
e315cd28
AC		 7127 if (vha->flags.online && !vha->flags.reset_active &&
7128 !atomic_read(&vha->loop_down_timer) &&
7129 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 7130 do {
e315cd28 7131 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 7132
7133 /*
7134 * Issue marker command only when we are going to start
7135 * the I/O.
7136 */
e315cd28
AC		 7137 vha->marker_needed = 1;
7138 } while (!atomic_read(&vha->loop_down_timer) &&
7139 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 7140 }
7141}
7142
1da177e4
LT		 7143/**************************************************************************
7144* qla2x00_timer
7145*
7146* Description:
7147* One second timer
7148*
7149* Context: Interrupt
7150***************************************************************************/
2c3dfe3f 7151void
8e5f4ba0 7152qla2x00_timer(struct timer_list *t)
1da177e4 7153{
8e5f4ba0 7154 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 7155 unsigned long cpu_flags = 0;
1da177e4
LT		 7156 int start_dpc = 0;
7157 int index;
7158 srb_t *sp;
85880801 7159 uint16_t w;
e315cd28 7160 struct qla_hw_data *ha = vha->hw;
73208dfd 7161 struct req_que *req;
85880801 7162
a5b36321 7163 if (ha->flags.eeh_busy) {
7c3df132
SK		 7164 ql_dbg(ql_dbg_timer, vha, 0x6000,
7165 "EEH = %d, restarting timer.\n",
7166 ha->flags.eeh_busy);
a5b36321
LC		 7167 qla2x00_restart_timer(vha, WATCH_INTERVAL);
7168 return;
7169 }
7170
f3ddac19
CD		 7171 /*
7172 * Hardware read to raise pending EEH errors during mailbox waits. If
7173 * the read returns -1 then disable the board.
7174 */
7175 if (!pci_channel_offline(ha->pdev)) {
85880801 7176 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 7177 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 7178 }
1da177e4 7179
cefcaba6 7180 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 7181 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 7182 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
7183 start_dpc++;
7ec0effd
AD		 7184 if (IS_QLA82XX(ha))
7185 qla82xx_watchdog(vha);
7186 else if (IS_QLA8044(ha))
7187 qla8044_watchdog(vha);
579d12b5
SK		 7188 }
7189
8ae6d9c7
GM		 7190 if (!vha->vp_idx && IS_QLAFX00(ha))
7191 qlafx00_timer_routine(vha);
7192
1da177e4 7193 /* Loop down handler. */
e315cd28 7194 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 7195 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
7196 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 7197 && vha->flags.online) {
1da177e4 7198
e315cd28
AC		 7199 if (atomic_read(&vha->loop_down_timer) ==
7200 vha->loop_down_abort_time) {
1da177e4 7201
7c3df132
SK		 7202 ql_log(ql_log_info, vha, 0x6008,
7203 "Loop down - aborting the queues before time expires.\n");
1da177e4 7204
e315cd28
AC		 7205 if (!IS_QLA2100(ha) && vha->link_down_timeout)
7206 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 7207
f08b7251
AV		 7208 /*
7209 * Schedule an ISP abort to return any FCP2-device
7210 * commands.
7211 */
2c3dfe3f 7212 /* NPIV - scan physical port only */
e315cd28 7213 if (!vha->vp_idx) {
2c3dfe3f
SJ		 7214 spin_lock_irqsave(&ha->hardware_lock,
7215 cpu_flags);
73208dfd 7216 req = ha->req_q_map[0];
2c3dfe3f 7217 for (index = 1;
8d93f550 7218 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 7219 index++) {
7220 fc_port_t *sfcp;
7221
e315cd28 7222 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 7223 if (!sp)
7224 continue;
c5419e26
QT		 7225 if (sp->cmd_type != TYPE_SRB)
7226 continue;
9ba56b95 7227 if (sp->type != SRB_SCSI_CMD)
cf53b069 7228 continue;
2c3dfe3f 7229 sfcp = sp->fcport;
f08b7251 7230 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 7231 continue;
bdf79621 7232
8f7daead
GM		 7233 if (IS_QLA82XX(ha))
7234 set_bit(FCOE_CTX_RESET_NEEDED,
7235 &vha->dpc_flags);
7236 else
7237 set_bit(ISP_ABORT_NEEDED,
e315cd28 7238 &vha->dpc_flags);
2c3dfe3f
SJ		 7239 break;
7240 }
7241 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 7242 cpu_flags);
1da177e4 7243 }
1da177e4
LT		 7244 start_dpc++;
7245 }
7246
7247 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 7248 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 7249 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 7250 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 7251 "Loop down - aborting ISP.\n");
7252
8f7daead
GM		 7253 if (IS_QLA82XX(ha))
7254 set_bit(FCOE_CTX_RESET_NEEDED,
7255 &vha->dpc_flags);
7256 else
7257 set_bit(ISP_ABORT_NEEDED,
7258 &vha->dpc_flags);
1da177e4
LT		 7259 }
7260 }
7c3df132
SK		 7261 ql_dbg(ql_dbg_timer, vha, 0x600a,
7262 "Loop down - seconds remaining %d.\n",
7263 atomic_read(&vha->loop_down_timer));
1da177e4 7264 }
cefcaba6
SK		 7265 /* Check if beacon LED needs to be blinked for physical host only */
7266 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 7267 /* There is no beacon_blink function for ISP82xx */
7ec0effd 7268 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 7269 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
7270 start_dpc++;
7271 }
f6df144c
AV		 7272 }
7273
550bf57d 7274 /* Process any deferred work. */
9b3e0f4d
QT		 7275 if (!list_empty(&vha->work_list)) {
7276 unsigned long flags;
7277 bool q = false;
7278
7279 spin_lock_irqsave(&vha->work_lock, flags);
7280 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
7281 q = true;
7282 spin_unlock_irqrestore(&vha->work_lock, flags);
7283 if (q)
7284 queue_work(vha->hw->wq, &vha->iocb_work);
7285 }
550bf57d 7286
7401bc18
DG		 7287 /*
7288 * FC-NVME
7289 * see if the active AEN count has changed from what was last reported.
7290 */
b2d1453a
GM		 7291 if (!vha->vp_idx &&
7292 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
7293 ha->zio_mode == QLA_ZIO_MODE_6 &&
7294 !ha->flags.host_shutting_down) {
7401bc18 7295 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 7296 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
7297 ha->nvme_last_rptd_aen);
deeae7a6 7298 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 7299 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7300 start_dpc++;
7301 }
7302
7303 if (!vha->vp_idx &&
7304 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
7305 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 7306 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 7307 ql_log(ql_log_info, vha, 0x3002,
7308 "Sched: Set ZIO exchange threshold to %d.\n",
7309 ha->last_zio_threshold);
7310 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 7311 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
7312 start_dpc++;
7401bc18
DG		 7313 }
7314
1da177e4 7315 /* Schedule the DPC routine if needed */
e315cd28
AC		 7316 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
7317 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
7318 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 7319 start_dpc ||
e315cd28
AC		 7320 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
7321 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 7322 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
7323 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 7324 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
d83a80ee
JC		 7325 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
7326 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) {
7c3df132
SK		 7327 ql_dbg(ql_dbg_timer, vha, 0x600b,
7328 "isp_abort_needed=%d loop_resync_needed=%d "
7329 "fcport_update_needed=%d start_dpc=%d "
7330 "reset_marker_needed=%d",
7331 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
7332 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
7333 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
7334 start_dpc,
7335 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
7336 ql_dbg(ql_dbg_timer, vha, 0x600c,
7337 "beacon_blink_needed=%d isp_unrecoverable=%d "
7338 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
d83a80ee 7339 "relogin_needed=%d, Process_purex_iocb=%d.\n",
7c3df132
SK		 7340 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
7341 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
7342 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
7343 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
d83a80ee
JC		 7344 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
7345 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags));
e315cd28 7346 qla2xxx_wake_dpc(vha);
7c3df132 7347 }
1da177e4 7348
e315cd28 7349 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 7350}
7351
5433383e
AV		 7352/* Firmware interface routines. */
7353
5433383e
AV		 7354#define FW_ISP21XX 0
7355#define FW_ISP22XX 1
7356#define FW_ISP2300 2
7357#define FW_ISP2322 3
48c02fde 7358#define FW_ISP24XX 4
c3a2f0df 7359#define FW_ISP25XX 5
3a03eb79 7360#define FW_ISP81XX 6
a9083016 7361#define FW_ISP82XX 7
6246b8a1
GM		 7362#define FW_ISP2031 8
7363#define FW_ISP8031 9
2c5bbbb2 7364#define FW_ISP27XX 10
ecc89f25 7365#define FW_ISP28XX 11
5433383e 7366
bb8ee499
AV		 7367#define FW_FILE_ISP21XX "ql2100_fw.bin"
7368#define FW_FILE_ISP22XX "ql2200_fw.bin"
7369#define FW_FILE_ISP2300 "ql2300_fw.bin"
7370#define FW_FILE_ISP2322 "ql2322_fw.bin"
7371#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 7372#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 7373#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 7374#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 7375#define FW_FILE_ISP2031 "ql2600_fw.bin"
7376#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 7377#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 7378#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 7379
bb8ee499 7380
e1e82b6f 7381static DEFINE_MUTEX(qla_fw_lock);
5433383e 7382
ecc89f25 7383static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 7384 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
7385 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
7386 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
7387 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
7388 { .name = FW_FILE_ISP24XX, },
c3a2f0df 7389 { .name = FW_FILE_ISP25XX, },
3a03eb79 7390 { .name = FW_FILE_ISP81XX, },
a9083016 7391 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 7392 { .name = FW_FILE_ISP2031, },
7393 { .name = FW_FILE_ISP8031, },
2c5bbbb2 7394 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 7395 { .name = FW_FILE_ISP28XX, },
7396 { .name = NULL, },
5433383e
AV		 7397};
7398
7399struct fw_blob *
e315cd28 7400qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 7401{
e315cd28 7402 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 7403 struct fw_blob *blob;
7404
5433383e
AV		 7405 if (IS_QLA2100(ha)) {
7406 blob = &qla_fw_blobs[FW_ISP21XX];
7407 } else if (IS_QLA2200(ha)) {
7408 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 7409 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 7410 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 7411 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 7412 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 7413 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 7414 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 7415 } else if (IS_QLA25XX(ha)) {
7416 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 7417 } else if (IS_QLA81XX(ha)) {
7418 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 7419 } else if (IS_QLA82XX(ha)) {
7420 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 7421 } else if (IS_QLA2031(ha)) {
7422 blob = &qla_fw_blobs[FW_ISP2031];
7423 } else if (IS_QLA8031(ha)) {
7424 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 7425 } else if (IS_QLA27XX(ha)) {
7426 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 7427 } else if (IS_QLA28XX(ha)) {
7428 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 7429 } else {
7430 return NULL;
5433383e
AV		 7431 }
7432
ecc89f25
JC		 7433 if (!blob->name)
7434 return NULL;
7435
e1e82b6f 7436 mutex_lock(&qla_fw_lock);
5433383e
AV		 7437 if (blob->fw)
7438 goto out;
7439
7440 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 7441 ql_log(ql_log_warn, vha, 0x0063,
7442 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 7443 blob->fw = NULL;
7444 blob = NULL;
5433383e
AV		 7445 }
7446
7447out:
e1e82b6f 7448 mutex_unlock(&qla_fw_lock);
5433383e
AV		 7449 return blob;
7450}
7451
7452static void
7453qla2x00_release_firmware(void)
7454{
ecc89f25 7455 struct fw_blob *blob;
5433383e 7456
e1e82b6f 7457 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 7458 for (blob = qla_fw_blobs; blob->name; blob++)
7459 release_firmware(blob->fw);
e1e82b6f 7460 mutex_unlock(&qla_fw_lock);
5433383e
AV		 7461}
7462
5386a4e6
QT		 7463static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
7464{
7465 struct qla_hw_data *ha = vha->hw;
7466 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
7467 struct qla_qpair *qpair = NULL;
7468 struct scsi_qla_host *vp;
7469 fc_port_t *fcport;
7470 int i;
7471 unsigned long flags;
7472
7473 ha->chip_reset++;
7474
7475 ha->base_qpair->chip_reset = ha->chip_reset;
7476 for (i = 0; i < ha->max_qpairs; i++) {
7477 if (ha->queue_pair_map[i])
7478 ha->queue_pair_map[i]->chip_reset =
7479 ha->base_qpair->chip_reset;
7480 }
7481
7482 /* purge MBox commands */
7483 if (atomic_read(&ha->num_pend_mbx_stage3)) {
7484 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
7485 complete(&ha->mbx_intr_comp);
7486 }
7487
7488 i = 0;
7489
7490 while (atomic_read(&ha->num_pend_mbx_stage3) ||
7491 atomic_read(&ha->num_pend_mbx_stage2) ||
7492 atomic_read(&ha->num_pend_mbx_stage1)) {
7493 msleep(20);
7494 i++;
7495 if (i > 50)
7496 break;
7497 }
7498
7499 ha->flags.purge_mbox = 0;
7500
7501 mutex_lock(&ha->mq_lock);
7502 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7503 qpair->online = 0;
7504 mutex_unlock(&ha->mq_lock);
7505
3c75ad1d 7506 qla2x00_mark_all_devices_lost(vha);
5386a4e6
QT		 7507
7508 spin_lock_irqsave(&ha->vport_slock, flags);
7509 list_for_each_entry(vp, &ha->vp_list, list) {
7510 atomic_inc(&vp->vref_count);
7511 spin_unlock_irqrestore(&ha->vport_slock, flags);
3c75ad1d 7512 qla2x00_mark_all_devices_lost(vp);
5386a4e6
QT		 7513 spin_lock_irqsave(&ha->vport_slock, flags);
7514 atomic_dec(&vp->vref_count);
7515 }
7516 spin_unlock_irqrestore(&ha->vport_slock, flags);
7517
7518 /* Clear all async request states across all VPs. */
7519 list_for_each_entry(fcport, &vha->vp_fcports, list)
7520 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7521
7522 spin_lock_irqsave(&ha->vport_slock, flags);
7523 list_for_each_entry(vp, &ha->vp_list, list) {
7524 atomic_inc(&vp->vref_count);
7525 spin_unlock_irqrestore(&ha->vport_slock, flags);
7526 list_for_each_entry(fcport, &vp->vp_fcports, list)
7527 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
7528 spin_lock_irqsave(&ha->vport_slock, flags);
7529 atomic_dec(&vp->vref_count);
7530 }
7531 spin_unlock_irqrestore(&ha->vport_slock, flags);
7532}
7533
7534
14e660e6
SJ		 7535static pci_ers_result_t
7536qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
7537{
85880801
AV		 7538 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
7539 struct qla_hw_data *ha = vha->hw;
7540
7c3df132
SK		 7541 ql_dbg(ql_dbg_aer, vha, 0x9000,
7542 "PCI error detected, state %x.\n", state);
b9b12f73 7543
efdb5760
SC		 7544 if (!atomic_read(&pdev->enable_cnt)) {
7545 ql_log(ql_log_info, vha, 0xffff,
7546 "PCI device is disabled,state %x\n", state);
7547 return PCI_ERS_RESULT_NEED_RESET;
7548 }
7549
14e660e6
SJ		 7550 switch (state) {
7551 case pci_channel_io_normal:
85880801 7552 ha->flags.eeh_busy = 0;
c38d1baf 7553 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 7554 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7555 qla2xxx_wake_dpc(vha);
7556 }
14e660e6
SJ		 7557 return PCI_ERS_RESULT_CAN_RECOVER;
7558 case pci_channel_io_frozen:
85880801 7559 ha->flags.eeh_busy = 1;
5386a4e6 7560 qla_pci_error_cleanup(vha);
14e660e6
SJ		 7561 return PCI_ERS_RESULT_NEED_RESET;
7562 case pci_channel_io_perm_failure:
85880801
AV		 7563 ha->flags.pci_channel_io_perm_failure = 1;
7564 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 7565 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 7566 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
7567 qla2xxx_wake_dpc(vha);
7568 }
14e660e6
SJ		 7569 return PCI_ERS_RESULT_DISCONNECT;
7570 }
7571 return PCI_ERS_RESULT_NEED_RESET;
7572}
7573
7574static pci_ers_result_t
7575qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
7576{
7577 int risc_paused = 0;
7578 uint32_t stat;
7579 unsigned long flags;
e315cd28
AC		 7580 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7581 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7582 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7583 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
7584
bcc5b6d3
SK		 7585 if (IS_QLA82XX(ha))
7586 return PCI_ERS_RESULT_RECOVERED;
7587
14e660e6
SJ		 7588 spin_lock_irqsave(&ha->hardware_lock, flags);
7589 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
04474d3a 7590 stat = rd_reg_word(&reg->hccr);
14e660e6
SJ		 7591 if (stat & HCCR_RISC_PAUSE)
7592 risc_paused = 1;
7593 } else if (IS_QLA23XX(ha)) {
04474d3a 7594 stat = rd_reg_dword(&reg->u.isp2300.host_status);
14e660e6
SJ		 7595 if (stat & HSR_RISC_PAUSED)
7596 risc_paused = 1;
7597 } else if (IS_FWI2_CAPABLE(ha)) {
04474d3a 7598 stat = rd_reg_dword(&reg24->host_status);
14e660e6
SJ		 7599 if (stat & HSRX_RISC_PAUSED)
7600 risc_paused = 1;
7601 }
7602 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7603
7604 if (risc_paused) {
7c3df132
SK		 7605 ql_log(ql_log_info, base_vha, 0x9003,
7606 "RISC paused -- mmio_enabled, Dumping firmware.\n");
8ae17876 7607 qla2xxx_dump_fw(base_vha);
14e660e6
SJ		 7608
7609 return PCI_ERS_RESULT_NEED_RESET;
7610 } else
7611 return PCI_ERS_RESULT_RECOVERED;
7612}
7613
7614static pci_ers_result_t
7615qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7616{
7617 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7618 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7619 struct qla_hw_data *ha = base_vha->hw;
5386a4e6
QT		 7620 int rc;
7621 struct qla_qpair *qpair = NULL;
09483916 7622
7c3df132
SK		 7623 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7624 "Slot Reset.\n");
85880801 7625
90a86fc0
JC		 7626 /* Workaround: qla2xxx driver which access hardware earlier
7627 * needs error state to be pci_channel_io_online.
7628 * Otherwise mailbox command timesout.
7629 */
7630 pdev->error_state = pci_channel_io_normal;
7631
7632 pci_restore_state(pdev);
7633
8c1496bd
RL		 7634 /* pci_restore_state() clears the saved_state flag of the device
7635 * save restored state which resets saved_state flag
7636 */
7637 pci_save_state(pdev);
7638
09483916
BH		 7639 if (ha->mem_only)
7640 rc = pci_enable_device_mem(pdev);
7641 else
7642 rc = pci_enable_device(pdev);
14e660e6 7643
09483916 7644 if (rc) {
7c3df132 7645 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7646 "Can't re-enable PCI device after reset.\n");
a5b36321 7647 goto exit_slot_reset;
14e660e6 7648 }
14e660e6 7649
90a86fc0 7650
e315cd28 7651 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7652 goto exit_slot_reset;
7653
5386a4e6
QT		 7654 mutex_lock(&ha->mq_lock);
7655 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7656 qpair->online = 1;
7657 mutex_unlock(&ha->mq_lock);
85880801 7658
5386a4e6 7659 base_vha->flags.online = 1;
e315cd28 7660 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7661 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7662 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7663 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7664
90a86fc0 7665
a5b36321 7666exit_slot_reset:
7c3df132
SK		 7667 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7668 "slot_reset return %x.\n", ret);
85880801 7669
14e660e6
SJ		 7670 return ret;
7671}
7672
7673static void
7674qla2xxx_pci_resume(struct pci_dev *pdev)
7675{
e315cd28
AC		 7676 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7677 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7678 int ret;
7679
7c3df132
SK		 7680 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7681 "pci_resume.\n");
85880801 7682
5386a4e6
QT		 7683 ha->flags.eeh_busy = 0;
7684
e315cd28 7685 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7686 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7687 ql_log(ql_log_fatal, base_vha, 0x9002,
7688 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7689 }
14e660e6
SJ		 7690}
7691
590f806d
QT		 7692static void
7693qla_pci_reset_prepare(struct pci_dev *pdev)
7694{
7695 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7696 struct qla_hw_data *ha = base_vha->hw;
7697 struct qla_qpair *qpair;
7698
7699 ql_log(ql_log_warn, base_vha, 0xffff,
7700 "%s.\n", __func__);
7701
7702 /*
7703 * PCI FLR/function reset is about to reset the
7704 * slot. Stop the chip to stop all DMA access.
7705 * It is assumed that pci_reset_done will be called
7706 * after FLR to resume Chip operation.
7707 */
7708 ha->flags.eeh_busy = 1;
7709 mutex_lock(&ha->mq_lock);
7710 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7711 qpair->online = 0;
7712 mutex_unlock(&ha->mq_lock);
7713
7714 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7715 qla2x00_abort_isp_cleanup(base_vha);
7716 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7717}
7718
7719static void
7720qla_pci_reset_done(struct pci_dev *pdev)
7721{
7722 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7723 struct qla_hw_data *ha = base_vha->hw;
7724 struct qla_qpair *qpair;
7725
7726 ql_log(ql_log_warn, base_vha, 0xffff,
7727 "%s.\n", __func__);
7728
7729 /*
7730 * FLR just completed by PCI layer. Resume adapter
7731 */
7732 ha->flags.eeh_busy = 0;
7733 mutex_lock(&ha->mq_lock);
7734 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7735 qpair->online = 1;
7736 mutex_unlock(&ha->mq_lock);
7737
7738 base_vha->flags.online = 1;
7739 ha->isp_ops->abort_isp(base_vha);
7740 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7741}
7742
5601236b
MH		 7743static int qla2xxx_map_queues(struct Scsi_Host *shost)
7744{
d68b850e 7745 int rc;
5601236b 7746 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7747 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7748
f3e02695 7749 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7750 rc = blk_mq_map_queues(qmap);
d68b850e 7751 else
f0783d43 7752 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7753 return rc;
5601236b
MH		 7754}
7755
6515ad71
BVA		 7756struct scsi_host_template qla2xxx_driver_template = {
7757 .module = THIS_MODULE,
7758 .name = QLA2XXX_DRIVER_NAME,
7759 .queuecommand = qla2xxx_queuecommand,
7760
7761 .eh_timed_out = fc_eh_timed_out,
7762 .eh_abort_handler = qla2xxx_eh_abort,
7763 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7764 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7765 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7766 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7767
7768 .slave_configure = qla2xxx_slave_configure,
7769
7770 .slave_alloc = qla2xxx_slave_alloc,
7771 .slave_destroy = qla2xxx_slave_destroy,
7772 .scan_finished = qla2xxx_scan_finished,
7773 .scan_start = qla2xxx_scan_start,
7774 .change_queue_depth = scsi_change_queue_depth,
7775 .map_queues = qla2xxx_map_queues,
7776 .this_id = -1,
7777 .cmd_per_lun = 3,
7778 .sg_tablesize = SG_ALL,
7779
7780 .max_sectors = 0xFFFF,
7781 .shost_attrs = qla2x00_host_attrs,
7782
7783 .supported_mode = MODE_INITIATOR,
7784 .track_queue_depth = 1,
85cffefa 7785 .cmd_size = sizeof(srb_t),
6515ad71
BVA		 7786};
7787
a55b2d21 7788static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7789 .error_detected = qla2xxx_pci_error_detected,
7790 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7791 .slot_reset = qla2xxx_pci_slot_reset,
7792 .resume = qla2xxx_pci_resume,
590f806d
QT		 7793 .reset_prepare = qla_pci_reset_prepare,
7794 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7795};
7796
5433383e 7797static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7798 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7799 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7800 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7801 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7802 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7803 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7804 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7805 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7806 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7807 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7808 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7809 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7810 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7811 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7812 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7813 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7814 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7815 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7816 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7817 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7818 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7819 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7820 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7821 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7822 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7823 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7824 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7825 { 0 },
7826};
7827MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7828
fca29703 7829static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7830 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7831 .driver = {
7832 .owner = THIS_MODULE,
7833 },
fca29703 7834 .id_table = qla2xxx_pci_tbl,
7ee61397 7835 .probe = qla2x00_probe_one,
4c993f76 7836 .remove = qla2x00_remove_one,
e30d1756 7837 .shutdown = qla2x00_shutdown,
14e660e6 7838 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7839};
7840
75ef9de1 7841static const struct file_operations apidev_fops = {
6a03b4cd 7842 .owner = THIS_MODULE,
6038f373 7843 .llseek = noop_llseek,
6a03b4cd
HZ		 7844};
7845
1da177e4
LT		 7846/**
7847 * qla2x00_module_init - Module initialization.
7848 **/
7849static int __init
7850qla2x00_module_init(void)
7851{
fca29703
AV		 7852 int ret = 0;
7853
8a73a0e0 7854 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64);
bc04459c
BVA		 7855 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7856 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7857 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7858 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
8a73a0e0 7859 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64);
bc04459c
BVA		 7860 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7861 BUILD_BUG_ON(sizeof(request_t) != 64);
8a73a0e0
BVA		 7862 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64);
7863 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64);
7864 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64);
bc04459c 7865 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
8a73a0e0 7866 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64);
bc04459c
BVA		 7867 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7868 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7869 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7870 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7871 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7872 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7873 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
8a73a0e0
BVA		 7874 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2344);
7875 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424);
7876 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164);
7877 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260);
7878 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260);
7879 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16);
bc04459c 7880 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
8a73a0e0
BVA		 7881 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256);
7882 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24);
7883 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256);
7884 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288);
7885 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216);
bc04459c 7886 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
8a73a0e0 7887 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64);
bc04459c 7888 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
8a73a0e0 7889 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64);
bc04459c
BVA		 7890 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7891 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
8a73a0e0
BVA		 7892 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64);
7893 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64);
7894 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252);
7895 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64);
7896 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512);
7897 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512);
bc04459c 7898 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
8a73a0e0
BVA		 7899 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64);
7900 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64);
7901 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634);
7902 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100);
7903 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976);
7904 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228);
7905 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52);
7906 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172);
7907 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524);
7908 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8);
7909 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12);
7910 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24);
7911 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420);
7912 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28);
7913 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32);
7914 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196);
d9ab5f1f 7915 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE);
8a73a0e0 7916 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128);
59d23cf3
BVA		 7917 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8);
7918 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16);
8a73a0e0
BVA		 7919 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24);
7920 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16);
7921 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336);
bc04459c 7922 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
8a73a0e0
BVA		 7923 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64);
7924 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64);
7925 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64);
bc04459c 7926 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
8a73a0e0 7927 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52);
bc04459c 7928 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
8a73a0e0
BVA		 7929 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64);
7930 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64);
7931 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64);
7932 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64);
7933 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64);
7934 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64);
7935 BUILD_BUG_ON(sizeof(sts_entry_t) != 64);
7936 BUILD_BUG_ON(sizeof(sw_info_t) != 32);
7937 BUILD_BUG_ON(sizeof(target_id_t) != 2);
bc04459c 7938
1da177e4 7939 /* Allocate cache for SRBs. */
354d6b21 7940 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7941 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7942 if (srb_cachep == NULL) {
7c3df132
SK		 7943 ql_log(ql_log_fatal, NULL, 0x0001,
7944 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7945 return -ENOMEM;
7946 }
7947
2d70c103
NB		 7948 /* Initialize target kmem_cache and mem_pools */
7949 ret = qlt_init();
7950 if (ret < 0) {
c794d24e 7951 goto destroy_cache;
2d70c103
NB		 7952 } else if (ret > 0) {
7953 /*
7954 * If initiator mode is explictly disabled by qlt_init(),
7955 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7956 * performing scsi_scan_target() during LOOP UP event.
7957 */
7958 qla2xxx_transport_functions.disable_target_scan = 1;
7959 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7960 }
7961
1da177e4
LT		 7962 /* Derive version string. */
7963 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7964 if (ql2xextended_error_logging)
0181944f 7965 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7966 if (ql2xextended_error_logging == 1)
7967 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7968
0645cb83
QT		 7969 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7970 qla_insert_tgt_attrs();
7971
1c97a12a
AV		 7972 qla2xxx_transport_template =
7973 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7974 if (!qla2xxx_transport_template) {
7c3df132
SK		 7975 ql_log(ql_log_fatal, NULL, 0x0002,
7976 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7977 ret = -ENODEV;
7978 goto qlt_exit;
2c3dfe3f 7979 }
6a03b4cd
HZ		 7980
7981 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7982 if (apidev_major < 0) {
7c3df132
SK		 7983 ql_log(ql_log_fatal, NULL, 0x0003,
7984 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7985 }
7986
2c3dfe3f
SJ		 7987 qla2xxx_transport_vport_template =
7988 fc_attach_transport(&qla2xxx_transport_vport_functions);
7989 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7990 ql_log(ql_log_fatal, NULL, 0x0004,
7991 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7992 ret = -ENODEV;
7993 goto unreg_chrdev;
2c3dfe3f 7994 }
7c3df132
SK		 7995 ql_log(ql_log_info, NULL, 0x0005,
7996 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7997 qla2x00_version_str);
7ee61397 7998 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7999 if (ret) {
7c3df132
SK		 8000 ql_log(ql_log_fatal, NULL, 0x0006,
8001 "pci_register_driver failed...ret=%d Failing load!.\n",
8002 ret);
c794d24e 8003 goto release_vport_transport;
fca29703
AV		 8004 }
8005 return ret;
c794d24e
BVA		 8006
8007release_vport_transport:
8008 fc_release_transport(qla2xxx_transport_vport_template);
8009
8010unreg_chrdev:
8011 if (apidev_major >= 0)
8012 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8013 fc_release_transport(qla2xxx_transport_template);
8014
8015qlt_exit:
8016 qlt_exit();
8017
8018destroy_cache:
8019 kmem_cache_destroy(srb_cachep);
8020 return ret;
1da177e4
LT		 8021}
8022
8023/**
8024 * qla2x00_module_exit - Module cleanup.
8025 **/
8026static void __exit
8027qla2x00_module_exit(void)
8028{
7ee61397 8029 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 8030 qla2x00_release_firmware();
75c1d48a 8031 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 8032 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 8033 if (apidev_major >= 0)
8034 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
8035 fc_release_transport(qla2xxx_transport_template);
8036 qlt_exit();
8037 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 8038}
8039
8040module_init(qla2x00_module_init);
8041module_exit(qla2x00_module_exit);
8042
8043MODULE_AUTHOR("QLogic Corporation");
8044MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
8045MODULE_LICENSE("GPL");
8046MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 8047MODULE_FIRMWARE(FW_FILE_ISP21XX);
8048MODULE_FIRMWARE(FW_FILE_ISP22XX);
8049MODULE_FIRMWARE(FW_FILE_ISP2300);
8050MODULE_FIRMWARE(FW_FILE_ISP2322);
8051MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 8052MODULE_FIRMWARE(FW_FILE_ISP25XX);
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