]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/scsi/qla2xxx/qla_os.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'regulator/fix/max77802' into regulator-linus
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
41dc529a
QT		 240int ql2xmvasynctoatio = 1;
241module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
242MODULE_PARM_DESC(ql2xmvasynctoatio,
243 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
244 "0 (Default). Do not move IOCBs"
245 "1 - Move IOCBs.");
246
1da177e4 247/*
fa2a1ce5 248 * SCSI host template entry points
1da177e4
LT		 249 */
250static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 251static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 252static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
253static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 254static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 255static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 256static int qla2xxx_eh_abort(struct scsi_cmnd *);
257static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 258static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 259static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
260static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 261
1a2fbf18 262static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 263static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 264static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 265static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 266
a5326f86 267struct scsi_host_template qla2xxx_driver_template = {
1da177e4 268 .module = THIS_MODULE,
cb63067a 269 .name = QLA2XXX_DRIVER_NAME,
a5326f86 270 .queuecommand = qla2xxx_queuecommand,
fca29703 271
b6a05c82 272 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 273 .eh_abort_handler = qla2xxx_eh_abort,
274 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 275 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 276 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
277 .eh_host_reset_handler = qla2xxx_eh_host_reset,
278
279 .slave_configure = qla2xxx_slave_configure,
280
281 .slave_alloc = qla2xxx_slave_alloc,
282 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 283 .scan_finished = qla2xxx_scan_finished,
284 .scan_start = qla2xxx_scan_start,
db5ed4df 285 .change_queue_depth = scsi_change_queue_depth,
5601236b 286 .map_queues = qla2xxx_map_queues,
fca29703
AV		 287 .this_id = -1,
288 .cmd_per_lun = 3,
289 .use_clustering = ENABLE_CLUSTERING,
290 .sg_tablesize = SG_ALL,
291
292 .max_sectors = 0xFFFF,
afb046e2 293 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 294
295 .supported_mode = MODE_INITIATOR,
c40ecc12 296 .track_queue_depth = 1,
fca29703
AV		 297};
298
1da177e4 299static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 300struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 301
1da177e4
LT		 302/* TODO Convert to inlines
303 *
304 * Timer routines
305 */
1da177e4 306
2c3dfe3f 307__inline__ void
e315cd28 308qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 309{
e315cd28
AC		 310 init_timer(&vha->timer);
311 vha->timer.expires = jiffies + interval * HZ;
312 vha->timer.data = (unsigned long)vha;
313 vha->timer.function = (void (*)(unsigned long))func;
314 add_timer(&vha->timer);
315 vha->timer_active = 1;
1da177e4
LT		 316}
317
318static inline void
e315cd28 319qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 320{
a9083016 321 /* Currently used for 82XX only. */
7c3df132
SK		 322 if (vha->device_flags & DFLG_DEV_FAILED) {
323 ql_dbg(ql_dbg_timer, vha, 0x600d,
324 "Device in a failed state, returning.\n");
a9083016 325 return;
7c3df132 326 }
a9083016 327
e315cd28 328 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 329}
330
a824ebb3 331static __inline__ void
e315cd28 332qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 333{
e315cd28
AC		 334 del_timer_sync(&vha->timer);
335 vha->timer_active = 0;
1da177e4
LT		 336}
337
1da177e4
LT		 338static int qla2x00_do_dpc(void *data);
339
340static void qla2x00_rst_aen(scsi_qla_host_t *);
341
73208dfd
AC		 342static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
343 struct req_que **, struct rsp_que **);
e30d1756 344static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 345static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 346int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
347 struct qla_qpair *qpair);
1da177e4 348
1da177e4 349/* -------------------------------------------------------------------------- */
9a347ff4
CD		 350static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
351 struct rsp_que *rsp)
73208dfd 352{
7c3df132 353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 354 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 355 GFP_KERNEL);
356 if (!ha->req_q_map) {
7c3df132
SK		 357 ql_log(ql_log_fatal, vha, 0x003b,
358 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 359 goto fail_req_map;
360 }
361
2afa19a9 362 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 363 GFP_KERNEL);
364 if (!ha->rsp_q_map) {
7c3df132
SK		 365 ql_log(ql_log_fatal, vha, 0x003c,
366 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 367 goto fail_rsp_map;
368 }
d7459527
MH		 369
370 if (ql2xmqsupport && ha->max_qpairs) {
371 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
372 GFP_KERNEL);
373 if (!ha->queue_pair_map) {
374 ql_log(ql_log_fatal, vha, 0x0180,
375 "Unable to allocate memory for queue pair ptrs.\n");
376 goto fail_qpair_map;
377 }
378 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
379 if (ha->base_qpair == NULL) {
380 ql_log(ql_log_warn, vha, 0x0182,
381 "Failed to allocate base queue pair memory.\n");
382 goto fail_base_qpair;
383 }
384 ha->base_qpair->req = req;
385 ha->base_qpair->rsp = rsp;
386 }
387
9a347ff4
CD		 388 /*
389 * Make sure we record at least the request and response queue zero in
390 * case we need to free them if part of the probe fails.
391 */
392 ha->rsp_q_map[0] = rsp;
393 ha->req_q_map[0] = req;
73208dfd
AC		 394 set_bit(0, ha->rsp_qid_map);
395 set_bit(0, ha->req_qid_map);
396 return 1;
397
d7459527
MH		 398fail_base_qpair:
399 kfree(ha->queue_pair_map);
400fail_qpair_map:
401 kfree(ha->rsp_q_map);
402 ha->rsp_q_map = NULL;
73208dfd
AC		 403fail_rsp_map:
404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
406fail_req_map:
407 return -ENOMEM;
408}
409
2afa19a9 410static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 411{
8ae6d9c7
GM		 412 if (IS_QLAFX00(ha)) {
413 if (req && req->ring_fx00)
414 dma_free_coherent(&ha->pdev->dev,
415 (req->length_fx00 + 1) * sizeof(request_t),
416 req->ring_fx00, req->dma_fx00);
417 } else if (req && req->ring)
73208dfd
AC		 418 dma_free_coherent(&ha->pdev->dev,
419 (req->length + 1) * sizeof(request_t),
420 req->ring, req->dma);
421
8d93f550
CD		 422 if (req)
423 kfree(req->outstanding_cmds);
424
73208dfd 425 kfree(req);
73208dfd
AC		 426}
427
2afa19a9
AC		 428static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
429{
8ae6d9c7
GM		 430 if (IS_QLAFX00(ha)) {
431 if (rsp && rsp->ring)
432 dma_free_coherent(&ha->pdev->dev,
433 (rsp->length_fx00 + 1) * sizeof(request_t),
434 rsp->ring_fx00, rsp->dma_fx00);
435 } else if (rsp && rsp->ring) {
2afa19a9
AC		 436 dma_free_coherent(&ha->pdev->dev,
437 (rsp->length + 1) * sizeof(response_t),
438 rsp->ring, rsp->dma);
8ae6d9c7 439 }
2afa19a9 440 kfree(rsp);
2afa19a9
AC		 441}
442
73208dfd
AC		 443static void qla2x00_free_queues(struct qla_hw_data *ha)
444{
445 struct req_que *req;
446 struct rsp_que *rsp;
447 int cnt;
093df737 448 unsigned long flags;
73208dfd 449
093df737 450 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 451 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 452 if (!test_bit(cnt, ha->req_qid_map))
453 continue;
454
73208dfd 455 req = ha->req_q_map[cnt];
093df737
QT		 456 clear_bit(cnt, ha->req_qid_map);
457 ha->req_q_map[cnt] = NULL;
458
459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 460 qla2x00_free_req_que(ha, req);
093df737 461 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 462 }
093df737
QT		 463 spin_unlock_irqrestore(&ha->hardware_lock, flags);
464
73208dfd
AC		 465 kfree(ha->req_q_map);
466 ha->req_q_map = NULL;
2afa19a9 467
093df737
QT		 468
469 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 470 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 471 if (!test_bit(cnt, ha->rsp_qid_map))
472 continue;
473
2afa19a9 474 rsp = ha->rsp_q_map[cnt];
c3c42394 475 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 476 ha->rsp_q_map[cnt] = NULL;
477 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 478 qla2x00_free_rsp_que(ha, rsp);
093df737 479 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 480 }
093df737
QT		 481 spin_unlock_irqrestore(&ha->hardware_lock, flags);
482
2afa19a9
AC		 483 kfree(ha->rsp_q_map);
484 ha->rsp_q_map = NULL;
73208dfd
AC		 485}
486
1da177e4 487static char *
e315cd28 488qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 489{
e315cd28 490 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 491 static char *pci_bus_modes[] = {
492 "33", "66", "100", "133",
493 };
494 uint16_t pci_bus;
495
496 strcpy(str, "PCI");
497 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
498 if (pci_bus) {
499 strcat(str, "-X (");
500 strcat(str, pci_bus_modes[pci_bus]);
501 } else {
502 pci_bus = (ha->pci_attr & BIT_8) >> 8;
503 strcat(str, " (");
504 strcat(str, pci_bus_modes[pci_bus]);
505 }
506 strcat(str, " MHz)");
507
508 return (str);
509}
510
fca29703 511static char *
e315cd28 512qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 513{
514 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 515 struct qla_hw_data *ha = vha->hw;
fca29703 516 uint32_t pci_bus;
fca29703 517
62a276f8 518 if (pci_is_pcie(ha->pdev)) {
fca29703 519 char lwstr[6];
62a276f8 520 uint32_t lstat, lspeed, lwidth;
fca29703 521
62a276f8
BH		 522 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
523 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
524 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 525
526 strcpy(str, "PCIe (");
49300af7
SK		 527 switch (lspeed) {
528 case 1:
c87a0d8c 529 strcat(str, "2.5GT/s ");
49300af7
SK		 530 break;
531 case 2:
c87a0d8c 532 strcat(str, "5.0GT/s ");
49300af7
SK		 533 break;
534 case 3:
535 strcat(str, "8.0GT/s ");
536 break;
537 default:
fca29703 538 strcat(str, "<unknown> ");
49300af7
SK		 539 break;
540 }
fca29703
AV		 541 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
542 strcat(str, lwstr);
543
544 return str;
545 }
546
547 strcpy(str, "PCI");
548 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
549 if (pci_bus == 0 || pci_bus == 8) {
550 strcat(str, " (");
551 strcat(str, pci_bus_modes[pci_bus >> 3]);
552 } else {
553 strcat(str, "-X ");
554 if (pci_bus & BIT_2)
555 strcat(str, "Mode 2");
556 else
557 strcat(str, "Mode 1");
558 strcat(str, " (");
559 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
560 }
561 strcat(str, " MHz)");
562
563 return str;
564}
565
e5f82ab8 566static char *
df57caba 567qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 568{
569 char un_str[10];
e315cd28 570 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 571
df57caba
HM		 572 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
573 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 574
575 if (ha->fw_attributes & BIT_9) {
576 strcat(str, "FLX");
577 return (str);
578 }
579
580 switch (ha->fw_attributes & 0xFF) {
581 case 0x7:
582 strcat(str, "EF");
583 break;
584 case 0x17:
585 strcat(str, "TP");
586 break;
587 case 0x37:
588 strcat(str, "IP");
589 break;
590 case 0x77:
591 strcat(str, "VI");
592 break;
593 default:
594 sprintf(un_str, "(%x)", ha->fw_attributes);
595 strcat(str, un_str);
596 break;
597 }
598 if (ha->fw_attributes & 0x100)
599 strcat(str, "X");
600
601 return (str);
602}
603
e5f82ab8 604static char *
df57caba 605qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 606{
e315cd28 607 struct qla_hw_data *ha = vha->hw;
f0883ac6 608
df57caba 609 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 610 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 611 return str;
fca29703
AV		 612}
613
9ba56b95 614void
25ff6af1 615qla2x00_sp_free_dma(void *ptr)
fca29703 616{
25ff6af1
JC		 617 srb_t *sp = ptr;
618 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 619 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 620 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 621
9ba56b95
GM		 622 if (sp->flags & SRB_DMA_VALID) {
623 scsi_dma_unmap(cmd);
624 sp->flags &= ~SRB_DMA_VALID;
7c3df132 625 }
fca29703 626
9ba56b95
GM		 627 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
628 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
629 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
630 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
631 }
632
d5ff0eed
JC		 633 if (!ctx)
634 goto end;
635
9ba56b95
GM		 636 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
637 /* List assured to be having elements */
d5ff0eed 638 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 639 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
640 }
641
642 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 643 struct crc_context *ctx0 = ctx;
644
645 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 646 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
647 }
648
649 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 650 struct ct6_dsd *ctx1 = ctx;
fca29703 651
9ba56b95 652 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 653 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 654 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
655 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
656 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
657 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 658 }
659
d5ff0eed 660end:
9ba56b95 661 CMD_SP(cmd) = NULL;
25ff6af1 662 qla2x00_rel_sp(sp);
9ba56b95
GM		 663}
664
d7459527 665void
25ff6af1 666qla2x00_sp_compl(void *ptr, int res)
9ba56b95 667{
25ff6af1 668 srb_t *sp = ptr;
9ba56b95
GM		 669 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
670
671 cmd->result = res;
672
673 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 674 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 675 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
676 sp, GET_CMD_SP(sp));
677 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 678 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 679 return;
680 }
681 if (!atomic_dec_and_test(&sp->ref_count))
682 return;
683
25ff6af1 684 qla2x00_sp_free_dma(sp);
9ba56b95 685 cmd->scsi_done(cmd);
fca29703
AV		 686}
687
d7459527 688void
25ff6af1 689qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 690{
691 srb_t *sp = (srb_t *)ptr;
692 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
693 struct qla_hw_data *ha = sp->fcport->vha->hw;
694 void *ctx = GET_CMD_CTX_SP(sp);
695
696 if (sp->flags & SRB_DMA_VALID) {
697 scsi_dma_unmap(cmd);
698 sp->flags &= ~SRB_DMA_VALID;
699 }
700
701 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
702 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
703 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
704 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
705 }
706
d5ff0eed
JC		 707 if (!ctx)
708 goto end;
709
d7459527
MH		 710 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
711 /* List assured to be having elements */
d5ff0eed 712 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 713 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
714 }
715
716 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 717 struct crc_context *ctx0 = ctx;
718
719 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 720 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
721 }
722
723 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 724 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 725 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
726 ctx1->fcp_cmnd_dma);
727 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
728 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
729 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
730 mempool_free(ctx1, ha->ctx_mempool);
731 }
d5ff0eed 732end:
d7459527
MH		 733 CMD_SP(cmd) = NULL;
734 qla2xxx_rel_qpair_sp(sp->qpair, sp);
735}
736
737void
25ff6af1 738qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 739{
25ff6af1 740 srb_t *sp = ptr;
d7459527
MH		 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
742
743 cmd->result = res;
744
745 if (atomic_read(&sp->ref_count) == 0) {
746 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
747 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
748 sp, GET_CMD_SP(sp));
749 if (ql2xextended_error_logging & ql_dbg_io)
750 WARN_ON(atomic_read(&sp->ref_count) == 0);
751 return;
752 }
753 if (!atomic_dec_and_test(&sp->ref_count))
754 return;
755
25ff6af1 756 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 757 cmd->scsi_done(cmd);
758}
759
8ae6d9c7
GM		 760/* If we are SP1 here, we need to still take and release the host_lock as SP1
761 * does not have the changes necessary to avoid taking host->host_lock.
762 */
1da177e4 763static int
f5e3e40b 764qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 765{
134ae078 766 scsi_qla_host_t *vha = shost_priv(host);
fca29703 767 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 768 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 769 struct qla_hw_data *ha = vha->hw;
770 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 771 srb_t *sp;
772 int rval;
5601236b
MH		 773 struct qla_qpair *qpair = NULL;
774 uint32_t tag;
775 uint16_t hwq;
fca29703 776
04dfaa53
MFO		 777 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
778 cmd->result = DID_NO_CONNECT << 16;
779 goto qc24_fail_command;
780 }
781
5601236b
MH		 782 if (ha->mqenable) {
783 if (shost_use_blk_mq(vha->host)) {
784 tag = blk_mq_unique_tag(cmd->request);
785 hwq = blk_mq_unique_tag_to_hwq(tag);
786 qpair = ha->queue_pair_map[hwq];
787 } else if (vha->vp_idx && vha->qpair) {
788 qpair = vha->qpair;
789 }
790
791 if (qpair)
792 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 793 }
794
85880801 795 if (ha->flags.eeh_busy) {
7c3df132 796 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 797 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 798 "PCI Channel IO permanent failure, exiting "
799 "cmd=%p.\n", cmd);
b9b12f73 800 cmd->result = DID_NO_CONNECT << 16;
7c3df132 801 } else {
5f28d2d7 802 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 803 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 804 cmd->result = DID_REQUEUE << 16;
7c3df132 805 }
14e660e6
SJ		 806 goto qc24_fail_command;
807 }
808
19a7b4ae
JSEC		 809 rval = fc_remote_port_chkready(rport);
810 if (rval) {
811 cmd->result = rval;
5f28d2d7 812 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 813 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
814 cmd, rval);
fca29703
AV		 815 goto qc24_fail_command;
816 }
817
bad75002
AE		 818 if (!vha->flags.difdix_supported &&
819 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 820 ql_dbg(ql_dbg_io, vha, 0x3004,
821 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
822 cmd);
bad75002
AE		 823 cmd->result = DID_NO_CONNECT << 16;
824 goto qc24_fail_command;
825 }
aa651be8
CD		 826
827 if (!fcport) {
828 cmd->result = DID_NO_CONNECT << 16;
829 goto qc24_fail_command;
830 }
831
fca29703
AV		 832 if (atomic_read(&fcport->state) != FCS_ONLINE) {
833 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 834 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 835 ql_dbg(ql_dbg_io, vha, 0x3005,
836 "Returning DNC, fcport_state=%d loop_state=%d.\n",
837 atomic_read(&fcport->state),
838 atomic_read(&base_vha->loop_state));
fca29703
AV		 839 cmd->result = DID_NO_CONNECT << 16;
840 goto qc24_fail_command;
841 }
7b594131 842 goto qc24_target_busy;
fca29703
AV		 843 }
844
e05fe292
CD		 845 /*
846 * Return target busy if we've received a non-zero retry_delay_timer
847 * in a FCP_RSP.
848 */
975f7d46
BP		 849 if (fcport->retry_delay_timestamp == 0) {
850 /* retry delay not set */
851 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 852 fcport->retry_delay_timestamp = 0;
853 else
854 goto qc24_target_busy;
855
b00ee7d7 856 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 857 if (!sp)
f5e3e40b 858 goto qc24_host_busy;
fca29703 859
9ba56b95
GM		 860 sp->u.scmd.cmd = cmd;
861 sp->type = SRB_SCSI_CMD;
862 atomic_set(&sp->ref_count, 1);
863 CMD_SP(cmd) = (void *)sp;
864 sp->free = qla2x00_sp_free_dma;
865 sp->done = qla2x00_sp_compl;
866
e315cd28 867 rval = ha->isp_ops->start_scsi(sp);
7c3df132 868 if (rval != QLA_SUCCESS) {
53016ed3 869 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 870 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 871 goto qc24_host_busy_free_sp;
7c3df132 872 }
fca29703 873
fca29703
AV		 874 return 0;
875
876qc24_host_busy_free_sp:
25ff6af1 877 qla2x00_sp_free_dma(sp);
fca29703 878
f5e3e40b 879qc24_host_busy:
fca29703
AV		 880 return SCSI_MLQUEUE_HOST_BUSY;
881
7b594131
MC		 882qc24_target_busy:
883 return SCSI_MLQUEUE_TARGET_BUSY;
884
fca29703 885qc24_fail_command:
f5e3e40b 886 cmd->scsi_done(cmd);
fca29703
AV		 887
888 return 0;
889}
890
d7459527
MH		 891/* For MQ supported I/O */
892int
893qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
894 struct qla_qpair *qpair)
895{
896 scsi_qla_host_t *vha = shost_priv(host);
897 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
898 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
899 struct qla_hw_data *ha = vha->hw;
900 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
901 srb_t *sp;
902 int rval;
903
904 rval = fc_remote_port_chkready(rport);
905 if (rval) {
906 cmd->result = rval;
907 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
908 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
909 cmd, rval);
910 goto qc24_fail_command;
911 }
912
913 if (!fcport) {
914 cmd->result = DID_NO_CONNECT << 16;
915 goto qc24_fail_command;
916 }
917
918 if (atomic_read(&fcport->state) != FCS_ONLINE) {
919 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
920 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
921 ql_dbg(ql_dbg_io, vha, 0x3077,
922 "Returning DNC, fcport_state=%d loop_state=%d.\n",
923 atomic_read(&fcport->state),
924 atomic_read(&base_vha->loop_state));
925 cmd->result = DID_NO_CONNECT << 16;
926 goto qc24_fail_command;
927 }
928 goto qc24_target_busy;
929 }
930
931 /*
932 * Return target busy if we've received a non-zero retry_delay_timer
933 * in a FCP_RSP.
934 */
935 if (fcport->retry_delay_timestamp == 0) {
936 /* retry delay not set */
937 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
938 fcport->retry_delay_timestamp = 0;
939 else
940 goto qc24_target_busy;
941
942 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
943 if (!sp)
944 goto qc24_host_busy;
945
946 sp->u.scmd.cmd = cmd;
947 sp->type = SRB_SCSI_CMD;
948 atomic_set(&sp->ref_count, 1);
949 CMD_SP(cmd) = (void *)sp;
950 sp->free = qla2xxx_qpair_sp_free_dma;
951 sp->done = qla2xxx_qpair_sp_compl;
952 sp->qpair = qpair;
953
954 rval = ha->isp_ops->start_scsi_mq(sp);
955 if (rval != QLA_SUCCESS) {
956 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
957 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
958 if (rval == QLA_INTERFACE_ERROR)
959 goto qc24_fail_command;
960 goto qc24_host_busy_free_sp;
961 }
962
963 return 0;
964
965qc24_host_busy_free_sp:
25ff6af1 966 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 967
968qc24_host_busy:
969 return SCSI_MLQUEUE_HOST_BUSY;
970
971qc24_target_busy:
972 return SCSI_MLQUEUE_TARGET_BUSY;
973
974qc24_fail_command:
975 cmd->scsi_done(cmd);
976
977 return 0;
978}
979
1da177e4
LT		 980/*
981 * qla2x00_eh_wait_on_command
982 * Waits for the command to be returned by the Firmware for some
983 * max time.
984 *
985 * Input:
1da177e4 986 * cmd = Scsi Command to wait on.
1da177e4
LT		 987 *
988 * Return:
989 * Not Found : 0
990 * Found : 1
991 */
992static int
e315cd28 993qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 994{
fe74c71f 995#define ABORT_POLLING_PERIOD 1000
478c3b03 996#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 997 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 998 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
999 struct qla_hw_data *ha = vha->hw;
f4f051eb 1000 int ret = QLA_SUCCESS;
1da177e4 1001
85880801 1002 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1003 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1004 "Return:eh_wait.\n");
85880801
AV		 1005 return ret;
1006 }
1007
d970432c 1008 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1009 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1010 }
1011 if (CMD_SP(cmd))
1012 ret = QLA_FUNCTION_FAILED;
1da177e4 1013
f4f051eb 1014 return ret;
1da177e4
LT		 1015}
1016
1017/*
1018 * qla2x00_wait_for_hba_online
fa2a1ce5 1019 * Wait till the HBA is online after going through
1da177e4
LT		 1020 * <= MAX_RETRIES_OF_ISP_ABORT or
1021 * finally HBA is disabled ie marked offline
1022 *
1023 * Input:
1024 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1025 *
1026 * Note:
1da177e4
LT		 1027 * Does context switching-Release SPIN_LOCK
1028 * (if any) before calling this routine.
1029 *
1030 * Return:
1031 * Success (Adapter is online) : 0
1032 * Failed (Adapter is offline/disabled) : 1
1033 */
854165f4 1034int
e315cd28 1035qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1036{
fca29703
AV		 1037 int return_status;
1038 unsigned long wait_online;
e315cd28
AC		 1039 struct qla_hw_data *ha = vha->hw;
1040 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1041
fa2a1ce5 1042 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1043 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1044 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1045 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1046 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1047
1048 msleep(1000);
1049 }
e315cd28 1050 if (base_vha->flags.online)
fa2a1ce5 1051 return_status = QLA_SUCCESS;
1da177e4
LT		 1052 else
1053 return_status = QLA_FUNCTION_FAILED;
1054
1da177e4
LT		 1055 return (return_status);
1056}
1057
726b8548
QT		 1058static inline int test_fcport_count(scsi_qla_host_t *vha)
1059{
1060 struct qla_hw_data *ha = vha->hw;
1061 unsigned long flags;
1062 int res;
1063
1064 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1065 ql_dbg(ql_dbg_init, vha, 0xffff,
1066 "tgt %p, fcport_count=%d\n",
1067 vha, vha->fcport_count);
1068 res = (vha->fcport_count == 0);
1069 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1070
1071 return res;
1072}
1073
1074/*
1075 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1076 * it has dependency on UNLOADING flag to stop device discovery
1077 */
1078static void
1079qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1080{
1081 qla2x00_mark_all_devices_lost(vha, 0);
1082
1083 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1084}
1085
86fbee86 1086/*
638a1a01
SC		 1087 * qla2x00_wait_for_hba_ready
1088 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1089 *
1090 * Input:
1091 * ha - pointer to host adapter structure
1092 *
1093 * Note:
1094 * Does context switching-Release SPIN_LOCK
1095 * (if any) before calling this routine.
1096 *
86fbee86 1097 */
638a1a01
SC		 1098static void
1099qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1100{
86fbee86 1101 struct qla_hw_data *ha = vha->hw;
783e0dc4 1102 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1103
1d483901
DC		 1104 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1105 ha->flags.mbox_busy) ||
1106 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1107 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1108 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1109 break;
86fbee86 1110 msleep(1000);
783e0dc4 1111 }
86fbee86
LC		 1112}
1113
2533cf67
LC		 1114int
1115qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1116{
1117 int return_status;
1118 unsigned long wait_reset;
1119 struct qla_hw_data *ha = vha->hw;
1120 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1121
1122 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1123 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1124 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1125 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1126 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1127
1128 msleep(1000);
1129
1130 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1131 ha->flags.chip_reset_done)
1132 break;
1133 }
1134 if (ha->flags.chip_reset_done)
1135 return_status = QLA_SUCCESS;
1136 else
1137 return_status = QLA_FUNCTION_FAILED;
1138
1139 return return_status;
1140}
1141
083a469d
GM		 1142static void
1143sp_get(struct srb *sp)
1144{
1145 atomic_inc(&sp->ref_count);
1146}
1147
a465537a
SC		 1148#define ISP_REG_DISCONNECT 0xffffffffU
1149/**************************************************************************
1150* qla2x00_isp_reg_stat
1151*
1152* Description:
1153* Read the host status register of ISP before aborting the command.
1154*
1155* Input:
1156* ha = pointer to host adapter structure.
1157*
1158*
1159* Returns:
1160* Either true or false.
1161*
1162* Note: Return true if there is register disconnect.
1163**************************************************************************/
1164static inline
1165uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1166{
1167 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1168 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1169
bf6061b1
SC		 1170 if (IS_P3P_TYPE(ha))
1171 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1172 else
1173 return ((RD_REG_DWORD(&reg->host_status)) ==
1174 ISP_REG_DISCONNECT);
a465537a
SC		 1175}
1176
1da177e4
LT		 1177/**************************************************************************
1178* qla2xxx_eh_abort
1179*
1180* Description:
1181* The abort function will abort the specified command.
1182*
1183* Input:
1184* cmd = Linux SCSI command packet to be aborted.
1185*
1186* Returns:
1187* Either SUCCESS or FAILED.
1188*
1189* Note:
2ea00202 1190* Only return FAILED if command not returned by firmware.
1da177e4 1191**************************************************************************/
e5f82ab8 1192static int
1da177e4
LT		 1193qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1194{
e315cd28 1195 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1196 srb_t *sp;
4e98d3b8 1197 int ret;
9cb78c16
HR		 1198 unsigned int id;
1199 uint64_t lun;
18e144d3 1200 unsigned long flags;
f934c9d0 1201 int rval, wait = 0;
e315cd28 1202 struct qla_hw_data *ha = vha->hw;
1da177e4 1203
a465537a
SC		 1204 if (qla2x00_isp_reg_stat(ha)) {
1205 ql_log(ql_log_info, vha, 0x8042,
1206 "PCI/Register disconnect, exiting.\n");
1207 return FAILED;
1208 }
f4f051eb 1209 if (!CMD_SP(cmd))
2ea00202 1210 return SUCCESS;
1da177e4 1211
4e98d3b8
AV		 1212 ret = fc_block_scsi_eh(cmd);
1213 if (ret != 0)
1214 return ret;
1215 ret = SUCCESS;
1216
f4f051eb
AV		 1217 id = cmd->device->id;
1218 lun = cmd->device->lun;
1da177e4 1219
e315cd28 1220 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1221 sp = (srb_t *) CMD_SP(cmd);
1222 if (!sp) {
1223 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1224 return SUCCESS;
1225 }
1da177e4 1226
7c3df132 1227 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1228 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1229 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1230
170babc3
MC		 1231 /* Get a reference to the sp and drop the lock.*/
1232 sp_get(sp);
083a469d 1233
e315cd28 1234 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1235 rval = ha->isp_ops->abort_command(sp);
1236 if (rval) {
96219424 1237 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1238 ret = SUCCESS;
96219424 1239 else
f934c9d0
CD		 1240 ret = FAILED;
1241
7c3df132 1242 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1243 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1244 } else {
7c3df132 1245 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1246 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1247 wait = 1;
1248 }
75942064
SK		 1249
1250 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1251 sp->done(sp, 0);
75942064 1252 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1253
bc91ade9
CD		 1254 /* Did the command return during mailbox execution? */
1255 if (ret == FAILED && !CMD_SP(cmd))
1256 ret = SUCCESS;
1257
f4f051eb 1258 /* Wait for the command to be returned. */
2ea00202 1259 if (wait) {
e315cd28 1260 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1261 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1262 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1263 ret = FAILED;
f4f051eb 1264 }
1da177e4 1265 }
1da177e4 1266
7c3df132 1267 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1268 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1269 vha->host_no, id, lun, wait, ret);
1da177e4 1270
f4f051eb
AV		 1271 return ret;
1272}
1da177e4 1273
4d78c973 1274int
e315cd28 1275qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1276 uint64_t l, enum nexus_wait_type type)
f4f051eb 1277{
17d98630 1278 int cnt, match, status;
18e144d3 1279 unsigned long flags;
e315cd28 1280 struct qla_hw_data *ha = vha->hw;
73208dfd 1281 struct req_que *req;
4d78c973 1282 srb_t *sp;
9ba56b95 1283 struct scsi_cmnd *cmd;
1da177e4 1284
523ec773 1285 status = QLA_SUCCESS;
17d98630 1286
e315cd28 1287 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1288 req = vha->req;
17d98630 1289 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1290 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1291 sp = req->outstanding_cmds[cnt];
1292 if (!sp)
523ec773 1293 continue;
9ba56b95 1294 if (sp->type != SRB_SCSI_CMD)
cf53b069 1295 continue;
25ff6af1 1296 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1297 continue;
1298 match = 0;
9ba56b95 1299 cmd = GET_CMD_SP(sp);
17d98630
AC		 1300 switch (type) {
1301 case WAIT_HOST:
1302 match = 1;
1303 break;
1304 case WAIT_TARGET:
9ba56b95 1305 match = cmd->device->id == t;
17d98630
AC		 1306 break;
1307 case WAIT_LUN:
9ba56b95
GM		 1308 match = (cmd->device->id == t &&
1309 cmd->device->lun == l);
17d98630 1310 break;
73208dfd 1311 }
17d98630
AC		 1312 if (!match)
1313 continue;
1314
1315 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1316 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1317 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1318 }
e315cd28 1319 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1320
1321 return status;
1da177e4
LT		 1322}
1323
523ec773
AV		 1324static char *reset_errors[] = {
1325 "HBA not online",
1326 "HBA not ready",
1327 "Task management failed",
1328 "Waiting for command completions",
1329};
1da177e4 1330
e5f82ab8 1331static int
523ec773 1332__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1333 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1334{
e315cd28 1335 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1336 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1337 int err;
1da177e4 1338
7c3df132 1339 if (!fcport) {
523ec773 1340 return FAILED;
7c3df132 1341 }
1da177e4 1342
4e98d3b8
AV		 1343 err = fc_block_scsi_eh(cmd);
1344 if (err != 0)
1345 return err;
1346
7c3df132 1347 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1348 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1349 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1350
523ec773 1351 err = 0;
7c3df132
SK		 1352 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1353 ql_log(ql_log_warn, vha, 0x800a,
1354 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1355 goto eh_reset_failed;
7c3df132 1356 }
523ec773 1357 err = 2;
2afa19a9 1358 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1359 != QLA_SUCCESS) {
1360 ql_log(ql_log_warn, vha, 0x800c,
1361 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1362 goto eh_reset_failed;
7c3df132 1363 }
523ec773 1364 err = 3;
e315cd28 1365 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1366 cmd->device->lun, type) != QLA_SUCCESS) {
1367 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1368 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1369 goto eh_reset_failed;
7c3df132 1370 }
523ec773 1371
7c3df132 1372 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1373 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1374 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1375
1376 return SUCCESS;
1377
4d78c973 1378eh_reset_failed:
7c3df132 1379 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1380 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1381 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1382 cmd);
523ec773
AV		 1383 return FAILED;
1384}
1da177e4 1385
523ec773
AV		 1386static int
1387qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1388{
e315cd28
AC		 1389 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1390 struct qla_hw_data *ha = vha->hw;
1da177e4 1391
a465537a
SC		 1392 if (qla2x00_isp_reg_stat(ha)) {
1393 ql_log(ql_log_info, vha, 0x803e,
1394 "PCI/Register disconnect, exiting.\n");
1395 return FAILED;
1396 }
1397
523ec773
AV		 1398 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1399 ha->isp_ops->lun_reset);
1da177e4
LT		 1400}
1401
1da177e4 1402static int
523ec773 1403qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1404{
e315cd28
AC		 1405 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1406 struct qla_hw_data *ha = vha->hw;
1da177e4 1407
a465537a
SC		 1408 if (qla2x00_isp_reg_stat(ha)) {
1409 ql_log(ql_log_info, vha, 0x803f,
1410 "PCI/Register disconnect, exiting.\n");
1411 return FAILED;
1412 }
1413
523ec773
AV		 1414 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1415 ha->isp_ops->target_reset);
1da177e4
LT		 1416}
1417
1da177e4
LT		 1418/**************************************************************************
1419* qla2xxx_eh_bus_reset
1420*
1421* Description:
1422* The bus reset function will reset the bus and abort any executing
1423* commands.
1424*
1425* Input:
1426* cmd = Linux SCSI command packet of the command that cause the
1427* bus reset.
1428*
1429* Returns:
1430* SUCCESS/FAILURE (defined as macro in scsi.h).
1431*
1432**************************************************************************/
e5f82ab8 1433static int
1da177e4
LT		 1434qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1435{
e315cd28 1436 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1437 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1438 int ret = FAILED;
9cb78c16
HR		 1439 unsigned int id;
1440 uint64_t lun;
a465537a
SC		 1441 struct qla_hw_data *ha = vha->hw;
1442
1443 if (qla2x00_isp_reg_stat(ha)) {
1444 ql_log(ql_log_info, vha, 0x8040,
1445 "PCI/Register disconnect, exiting.\n");
1446 return FAILED;
1447 }
f4f051eb 1448
f4f051eb
AV		 1449 id = cmd->device->id;
1450 lun = cmd->device->lun;
1da177e4 1451
7c3df132 1452 if (!fcport) {
f4f051eb 1453 return ret;
7c3df132 1454 }
1da177e4 1455
4e98d3b8
AV		 1456 ret = fc_block_scsi_eh(cmd);
1457 if (ret != 0)
1458 return ret;
1459 ret = FAILED;
1460
7c3df132 1461 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1462 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1463
e315cd28 1464 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1465 ql_log(ql_log_fatal, vha, 0x8013,
1466 "Wait for hba online failed board disabled.\n");
f4f051eb 1467 goto eh_bus_reset_done;
1da177e4
LT		 1468 }
1469
ad537689
SK		 1470 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1471 ret = SUCCESS;
1472
f4f051eb
AV		 1473 if (ret == FAILED)
1474 goto eh_bus_reset_done;
1da177e4 1475
9a41a62b 1476 /* Flush outstanding commands. */
4d78c973 1477 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1478 QLA_SUCCESS) {
1479 ql_log(ql_log_warn, vha, 0x8014,
1480 "Wait for pending commands failed.\n");
9a41a62b 1481 ret = FAILED;
7c3df132 1482 }
1da177e4 1483
f4f051eb 1484eh_bus_reset_done:
7c3df132 1485 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1486 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1487 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1488
f4f051eb 1489 return ret;
1da177e4
LT		 1490}
1491
1492/**************************************************************************
1493* qla2xxx_eh_host_reset
1494*
1495* Description:
1496* The reset function will reset the Adapter.
1497*
1498* Input:
1499* cmd = Linux SCSI command packet of the command that cause the
1500* adapter reset.
1501*
1502* Returns:
1503* Either SUCCESS or FAILED.
1504*
1505* Note:
1506**************************************************************************/
e5f82ab8 1507static int
1da177e4
LT		 1508qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1509{
e315cd28 1510 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1511 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1512 int ret = FAILED;
9cb78c16
HR		 1513 unsigned int id;
1514 uint64_t lun;
e315cd28 1515 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1516
a465537a
SC		 1517 if (qla2x00_isp_reg_stat(ha)) {
1518 ql_log(ql_log_info, vha, 0x8041,
1519 "PCI/Register disconnect, exiting.\n");
1520 schedule_work(&ha->board_disable);
1521 return SUCCESS;
1522 }
1523
f4f051eb
AV		 1524 id = cmd->device->id;
1525 lun = cmd->device->lun;
f4f051eb 1526
7c3df132 1527 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1528 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1529
63ee7072
CD		 1530 /*
1531 * No point in issuing another reset if one is active. Also do not
1532 * attempt a reset if we are updating flash.
1533 */
1534 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1535 goto eh_host_reset_lock;
1da177e4 1536
e315cd28
AC		 1537 if (vha != base_vha) {
1538 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1539 goto eh_host_reset_lock;
e315cd28 1540 } else {
7ec0effd 1541 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1542 if (!qla82xx_fcoe_ctx_reset(vha)) {
1543 /* Ctx reset success */
1544 ret = SUCCESS;
1545 goto eh_host_reset_lock;
1546 }
1547 /* fall thru if ctx reset failed */
1548 }
68ca949c
AC		 1549 if (ha->wq)
1550 flush_workqueue(ha->wq);
1551
e315cd28 1552 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1553 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1554 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1555 /* failed. schedule dpc to try */
1556 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1557
7c3df132
SK		 1558 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1559 ql_log(ql_log_warn, vha, 0x802a,
1560 "wait for hba online failed.\n");
e315cd28 1561 goto eh_host_reset_lock;
7c3df132 1562 }
e315cd28
AC		 1563 }
1564 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1565 }
1da177e4 1566
e315cd28 1567 /* Waiting for command to be returned to OS.*/
4d78c973 1568 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1569 QLA_SUCCESS)
f4f051eb 1570 ret = SUCCESS;
1da177e4 1571
f4f051eb 1572eh_host_reset_lock:
cfb0919c 1573 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1574 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1575 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1576
f4f051eb
AV		 1577 return ret;
1578}
1da177e4
LT		 1579
1580/*
1581* qla2x00_loop_reset
1582* Issue loop reset.
1583*
1584* Input:
1585* ha = adapter block pointer.
1586*
1587* Returns:
1588* 0 = success
1589*/
a4722cf2 1590int
e315cd28 1591qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1592{
0c8c39af 1593 int ret;
bdf79621 1594 struct fc_port *fcport;
e315cd28 1595 struct qla_hw_data *ha = vha->hw;
1da177e4 1596
5854771e
AB		 1597 if (IS_QLAFX00(ha)) {
1598 return qlafx00_loop_reset(vha);
1599 }
1600
f4c496c1 1601 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1602 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1603 if (fcport->port_type != FCT_TARGET)
1604 continue;
1605
1606 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1607 if (ret != QLA_SUCCESS) {
7c3df132 1608 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1609 "Bus Reset failed: Reset=%d "
7c3df132 1610 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1611 }
1612 }
1613 }
1614
8ae6d9c7 1615
6246b8a1 1616 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1617 atomic_set(&vha->loop_state, LOOP_DOWN);
1618 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1619 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1620 ret = qla2x00_full_login_lip(vha);
0c8c39af 1621 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1622 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1623 "full_login_lip=%d.\n", ret);
749af3d5 1624 }
0c8c39af
AV		 1625 }
1626
0d6e61bc 1627 if (ha->flags.enable_lip_reset) {
e315cd28 1628 ret = qla2x00_lip_reset(vha);
ad537689 1629 if (ret != QLA_SUCCESS)
7c3df132
SK		 1630 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1631 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1632 }
1633
1da177e4 1634 /* Issue marker command only when we are going to start the I/O */
e315cd28 1635 vha->marker_needed = 1;
1da177e4 1636
0c8c39af 1637 return QLA_SUCCESS;
1da177e4
LT		 1638}
1639
df4bf0bb 1640void
e315cd28 1641qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1642{
4cd3b6eb 1643 int que, cnt, status;
df4bf0bb
AV		 1644 unsigned long flags;
1645 srb_t *sp;
e315cd28 1646 struct qla_hw_data *ha = vha->hw;
73208dfd 1647 struct req_que *req;
df4bf0bb 1648
c0cb4496
AE		 1649 qlt_host_reset_handler(ha);
1650
df4bf0bb 1651 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1652 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1653 req = ha->req_q_map[que];
73208dfd
AC		 1654 if (!req)
1655 continue;
8d93f550
CD		 1656 if (!req->outstanding_cmds)
1657 continue;
1658 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1659 sp = req->outstanding_cmds[cnt];
e612d465 1660 if (sp) {
c733ab35
MFO		 1661 /* Don't abort commands in adapter during EEH
1662 * recovery as it's not accessible/responding.
1535aa75 1663 */
5f7c2bee
BK		 1664 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1665 (sp->type == SRB_SCSI_CMD)) {
c733ab35
MFO		 1666 /* Get a reference to the sp and drop the lock.
1667 * The reference ensures this sp->done() call
1668 * - and not the call in qla2xxx_eh_abort() -
1669 * ends the SCSI command (with result 'res').
1670 */
1671 sp_get(sp);
1672 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4cd3b6eb 1673 status = qla2xxx_eh_abort(GET_CMD_SP(sp));
c733ab35 1674 spin_lock_irqsave(&ha->hardware_lock, flags);
4cd3b6eb
BK		 1675 /* Get rid of extra reference if immediate exit
1676 * from ql2xxx_eh_abort */
1677 if (status == FAILED && (qla2x00_isp_reg_stat(ha)))
1678 atomic_dec(&sp->ref_count);
c733ab35 1679 }
73208dfd 1680 req->outstanding_cmds[cnt] = NULL;
25ff6af1 1681 sp->done(sp, res);
73208dfd 1682 }
df4bf0bb
AV		 1683 }
1684 }
1685 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1686}
1687
f4f051eb
AV		 1688static int
1689qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1690{
bdf79621 1691 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1692
19a7b4ae 1693 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1694 return -ENXIO;
bdf79621 1695
19a7b4ae 1696 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1697
f4f051eb
AV		 1698 return 0;
1699}
1da177e4 1700
f4f051eb
AV		 1701static int
1702qla2xxx_slave_configure(struct scsi_device *sdev)
1703{
e315cd28 1704 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1705 struct req_que *req = vha->req;
8482e118 1706
9e522cd8
AE		 1707 if (IS_T10_PI_CAPABLE(vha->hw))
1708 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1709
db5ed4df 1710 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1711 return 0;
1712}
1da177e4 1713
f4f051eb
AV		 1714static void
1715qla2xxx_slave_destroy(struct scsi_device *sdev)
1716{
1717 sdev->hostdata = NULL;
1da177e4
LT		 1718}
1719
1720/**
1721 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1722 * @ha: HA context
1723 *
1724 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1725 * supported addressing method.
1726 */
1727static void
53303c42 1728qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1729{
7524f9b9 1730 /* Assume a 32bit DMA mask. */
1da177e4 1731 ha->flags.enable_64bit_addressing = 0;
1da177e4 1732
6a35528a 1733 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1734 /* Any upper-dword bits set? */
1735 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1736 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1737 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1738 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1739 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1740 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1741 return;
1da177e4 1742 }
1da177e4 1743 }
7524f9b9 1744
284901a9
YH		 1745 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1746 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1747}
1748
fd34f556 1749static void
e315cd28 1750qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1751{
1752 unsigned long flags = 0;
1753 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1754
1755 spin_lock_irqsave(&ha->hardware_lock, flags);
1756 ha->interrupts_on = 1;
1757 /* enable risc and host interrupts */
1758 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1759 RD_REG_WORD(&reg->ictrl);
1760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1761
1762}
1763
1764static void
e315cd28 1765qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1766{
1767 unsigned long flags = 0;
1768 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1769
1770 spin_lock_irqsave(&ha->hardware_lock, flags);
1771 ha->interrupts_on = 0;
1772 /* disable risc and host interrupts */
1773 WRT_REG_WORD(&reg->ictrl, 0);
1774 RD_REG_WORD(&reg->ictrl);
1775 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1776}
1777
1778static void
e315cd28 1779qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1780{
1781 unsigned long flags = 0;
1782 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1783
1784 spin_lock_irqsave(&ha->hardware_lock, flags);
1785 ha->interrupts_on = 1;
1786 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1787 RD_REG_DWORD(&reg->ictrl);
1788 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1789}
1790
1791static void
e315cd28 1792qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1793{
1794 unsigned long flags = 0;
1795 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1796
124f85e6
AV		 1797 if (IS_NOPOLLING_TYPE(ha))
1798 return;
fd34f556
AV		 1799 spin_lock_irqsave(&ha->hardware_lock, flags);
1800 ha->interrupts_on = 0;
1801 WRT_REG_DWORD(&reg->ictrl, 0);
1802 RD_REG_DWORD(&reg->ictrl);
1803 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1804}
1805
706f457d
GM		 1806static int
1807qla2x00_iospace_config(struct qla_hw_data *ha)
1808{
1809 resource_size_t pio;
1810 uint16_t msix;
706f457d 1811
706f457d
GM		 1812 if (pci_request_selected_regions(ha->pdev, ha->bars,
1813 QLA2XXX_DRIVER_NAME)) {
1814 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1815 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1816 pci_name(ha->pdev));
1817 goto iospace_error_exit;
1818 }
1819 if (!(ha->bars & 1))
1820 goto skip_pio;
1821
1822 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1823 pio = pci_resource_start(ha->pdev, 0);
1824 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1825 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1826 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1827 "Invalid pci I/O region size (%s).\n",
1828 pci_name(ha->pdev));
1829 pio = 0;
1830 }
1831 } else {
1832 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1833 "Region #0 no a PIO resource (%s).\n",
1834 pci_name(ha->pdev));
1835 pio = 0;
1836 }
1837 ha->pio_address = pio;
1838 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1839 "PIO address=%llu.\n",
1840 (unsigned long long)ha->pio_address);
1841
1842skip_pio:
1843 /* Use MMIO operations for all accesses. */
1844 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1845 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1846 "Region #1 not an MMIO resource (%s), aborting.\n",
1847 pci_name(ha->pdev));
1848 goto iospace_error_exit;
1849 }
1850 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1851 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1852 "Invalid PCI mem region size (%s), aborting.\n",
1853 pci_name(ha->pdev));
1854 goto iospace_error_exit;
1855 }
1856
1857 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1858 if (!ha->iobase) {
1859 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1860 "Cannot remap MMIO (%s), aborting.\n",
1861 pci_name(ha->pdev));
1862 goto iospace_error_exit;
1863 }
1864
1865 /* Determine queue resources */
1866 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1867 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1868 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1869 goto mqiobase_exit;
1870
1871 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1872 pci_resource_len(ha->pdev, 3));
1873 if (ha->mqiobase) {
1874 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1875 "MQIO Base=%p.\n", ha->mqiobase);
1876 /* Read MSIX vector size of the board */
1877 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1878 ha->msix_count = msix + 1;
706f457d 1879 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1880 /* MB interrupt uses 1 vector */
1881 ha->max_req_queues = ha->msix_count - 1;
1882 ha->max_rsp_queues = ha->max_req_queues;
1883 /* Queue pairs is the max value minus the base queue pair */
1884 ha->max_qpairs = ha->max_rsp_queues - 1;
1885 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1886 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1887
706f457d 1888 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1889 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1890 } else
1891 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1892 "BAR 3 not enabled.\n");
1893
1894mqiobase_exit:
706f457d 1895 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1896 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1897 return (0);
1898
1899iospace_error_exit:
1900 return (-ENOMEM);
1901}
1902
1903
6246b8a1
GM		 1904static int
1905qla83xx_iospace_config(struct qla_hw_data *ha)
1906{
1907 uint16_t msix;
6246b8a1
GM		 1908
1909 if (pci_request_selected_regions(ha->pdev, ha->bars,
1910 QLA2XXX_DRIVER_NAME)) {
1911 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1912 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1913 pci_name(ha->pdev));
1914
1915 goto iospace_error_exit;
1916 }
1917
1918 /* Use MMIO operations for all accesses. */
1919 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1920 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1921 "Invalid pci I/O region size (%s).\n",
1922 pci_name(ha->pdev));
1923 goto iospace_error_exit;
1924 }
1925 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1926 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1927 "Invalid PCI mem region size (%s), aborting\n",
1928 pci_name(ha->pdev));
1929 goto iospace_error_exit;
1930 }
1931
1932 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1933 if (!ha->iobase) {
1934 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1935 "Cannot remap MMIO (%s), aborting.\n",
1936 pci_name(ha->pdev));
1937 goto iospace_error_exit;
1938 }
1939
1940 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1941 /* 83XX 26XX always use MQ type access for queues
1942 * - mbar 2, a.k.a region 4 */
1943 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1944 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 1945 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1946 pci_resource_len(ha->pdev, 4));
1947
1948 if (!ha->mqiobase) {
1949 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1950 "BAR2/region4 not enabled\n");
1951 goto mqiobase_exit;
1952 }
1953
1954 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1955 pci_resource_len(ha->pdev, 2));
1956 if (ha->msixbase) {
1957 /* Read MSIX vector size of the board */
1958 pci_read_config_word(ha->pdev,
1959 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1960 ha->msix_count = msix + 1;
093df737
QT		 1961 /*
1962 * By default, driver uses at least two msix vectors
1963 * (default & rspq)
1964 */
d7459527
MH		 1965 if (ql2xmqsupport) {
1966 /* MB interrupt uses 1 vector */
1967 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 1968
1969 /* ATIOQ needs 1 vector. That's 1 less QPair */
1970 if (QLA_TGT_MODE_ENABLED())
1971 ha->max_req_queues--;
1972
d0d2c68b
MH		 1973 ha->max_rsp_queues = ha->max_req_queues;
1974
d7459527
MH		 1975 /* Queue pairs is the max value minus
1976 * the base queue pair */
1977 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1978 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1979 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1980 }
1981 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1982 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1983 } else
1984 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1985 "BAR 1 not enabled.\n");
1986
1987mqiobase_exit:
6246b8a1 1988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 1989 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 1990 return 0;
1991
1992iospace_error_exit:
1993 return -ENOMEM;
1994}
1995
fd34f556
AV		 1996static struct isp_operations qla2100_isp_ops = {
1997 .pci_config = qla2100_pci_config,
1998 .reset_chip = qla2x00_reset_chip,
1999 .chip_diag = qla2x00_chip_diag,
2000 .config_rings = qla2x00_config_rings,
2001 .reset_adapter = qla2x00_reset_adapter,
2002 .nvram_config = qla2x00_nvram_config,
2003 .update_fw_options = qla2x00_update_fw_options,
2004 .load_risc = qla2x00_load_risc,
2005 .pci_info_str = qla2x00_pci_info_str,
2006 .fw_version_str = qla2x00_fw_version_str,
2007 .intr_handler = qla2100_intr_handler,
2008 .enable_intrs = qla2x00_enable_intrs,
2009 .disable_intrs = qla2x00_disable_intrs,
2010 .abort_command = qla2x00_abort_command,
523ec773
AV		 2011 .target_reset = qla2x00_abort_target,
2012 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2013 .fabric_login = qla2x00_login_fabric,
2014 .fabric_logout = qla2x00_fabric_logout,
2015 .calc_req_entries = qla2x00_calc_iocbs_32,
2016 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2017 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2018 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2019 .read_nvram = qla2x00_read_nvram_data,
2020 .write_nvram = qla2x00_write_nvram_data,
2021 .fw_dump = qla2100_fw_dump,
2022 .beacon_on = NULL,
2023 .beacon_off = NULL,
2024 .beacon_blink = NULL,
2025 .read_optrom = qla2x00_read_optrom_data,
2026 .write_optrom = qla2x00_write_optrom_data,
2027 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2028 .start_scsi = qla2x00_start_scsi,
d7459527 2029 .start_scsi_mq = NULL,
a9083016 2030 .abort_isp = qla2x00_abort_isp,
706f457d 2031 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2032 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2033};
2034
2035static struct isp_operations qla2300_isp_ops = {
2036 .pci_config = qla2300_pci_config,
2037 .reset_chip = qla2x00_reset_chip,
2038 .chip_diag = qla2x00_chip_diag,
2039 .config_rings = qla2x00_config_rings,
2040 .reset_adapter = qla2x00_reset_adapter,
2041 .nvram_config = qla2x00_nvram_config,
2042 .update_fw_options = qla2x00_update_fw_options,
2043 .load_risc = qla2x00_load_risc,
2044 .pci_info_str = qla2x00_pci_info_str,
2045 .fw_version_str = qla2x00_fw_version_str,
2046 .intr_handler = qla2300_intr_handler,
2047 .enable_intrs = qla2x00_enable_intrs,
2048 .disable_intrs = qla2x00_disable_intrs,
2049 .abort_command = qla2x00_abort_command,
523ec773
AV		 2050 .target_reset = qla2x00_abort_target,
2051 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2052 .fabric_login = qla2x00_login_fabric,
2053 .fabric_logout = qla2x00_fabric_logout,
2054 .calc_req_entries = qla2x00_calc_iocbs_32,
2055 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2056 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2057 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2058 .read_nvram = qla2x00_read_nvram_data,
2059 .write_nvram = qla2x00_write_nvram_data,
2060 .fw_dump = qla2300_fw_dump,
2061 .beacon_on = qla2x00_beacon_on,
2062 .beacon_off = qla2x00_beacon_off,
2063 .beacon_blink = qla2x00_beacon_blink,
2064 .read_optrom = qla2x00_read_optrom_data,
2065 .write_optrom = qla2x00_write_optrom_data,
2066 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2067 .start_scsi = qla2x00_start_scsi,
d7459527 2068 .start_scsi_mq = NULL,
a9083016 2069 .abort_isp = qla2x00_abort_isp,
7ec0effd 2070 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2071 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2072};
2073
2074static struct isp_operations qla24xx_isp_ops = {
2075 .pci_config = qla24xx_pci_config,
2076 .reset_chip = qla24xx_reset_chip,
2077 .chip_diag = qla24xx_chip_diag,
2078 .config_rings = qla24xx_config_rings,
2079 .reset_adapter = qla24xx_reset_adapter,
2080 .nvram_config = qla24xx_nvram_config,
2081 .update_fw_options = qla24xx_update_fw_options,
2082 .load_risc = qla24xx_load_risc,
2083 .pci_info_str = qla24xx_pci_info_str,
2084 .fw_version_str = qla24xx_fw_version_str,
2085 .intr_handler = qla24xx_intr_handler,
2086 .enable_intrs = qla24xx_enable_intrs,
2087 .disable_intrs = qla24xx_disable_intrs,
2088 .abort_command = qla24xx_abort_command,
523ec773
AV		 2089 .target_reset = qla24xx_abort_target,
2090 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2091 .fabric_login = qla24xx_login_fabric,
2092 .fabric_logout = qla24xx_fabric_logout,
2093 .calc_req_entries = NULL,
2094 .build_iocbs = NULL,
2095 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2096 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2097 .read_nvram = qla24xx_read_nvram_data,
2098 .write_nvram = qla24xx_write_nvram_data,
2099 .fw_dump = qla24xx_fw_dump,
2100 .beacon_on = qla24xx_beacon_on,
2101 .beacon_off = qla24xx_beacon_off,
2102 .beacon_blink = qla24xx_beacon_blink,
2103 .read_optrom = qla24xx_read_optrom_data,
2104 .write_optrom = qla24xx_write_optrom_data,
2105 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2106 .start_scsi = qla24xx_start_scsi,
d7459527 2107 .start_scsi_mq = NULL,
a9083016 2108 .abort_isp = qla2x00_abort_isp,
7ec0effd 2109 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2110 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2111};
2112
c3a2f0df
AV		 2113static struct isp_operations qla25xx_isp_ops = {
2114 .pci_config = qla25xx_pci_config,
2115 .reset_chip = qla24xx_reset_chip,
2116 .chip_diag = qla24xx_chip_diag,
2117 .config_rings = qla24xx_config_rings,
2118 .reset_adapter = qla24xx_reset_adapter,
2119 .nvram_config = qla24xx_nvram_config,
2120 .update_fw_options = qla24xx_update_fw_options,
2121 .load_risc = qla24xx_load_risc,
2122 .pci_info_str = qla24xx_pci_info_str,
2123 .fw_version_str = qla24xx_fw_version_str,
2124 .intr_handler = qla24xx_intr_handler,
2125 .enable_intrs = qla24xx_enable_intrs,
2126 .disable_intrs = qla24xx_disable_intrs,
2127 .abort_command = qla24xx_abort_command,
523ec773
AV		 2128 .target_reset = qla24xx_abort_target,
2129 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2130 .fabric_login = qla24xx_login_fabric,
2131 .fabric_logout = qla24xx_fabric_logout,
2132 .calc_req_entries = NULL,
2133 .build_iocbs = NULL,
2134 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2135 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2136 .read_nvram = qla25xx_read_nvram_data,
2137 .write_nvram = qla25xx_write_nvram_data,
2138 .fw_dump = qla25xx_fw_dump,
2139 .beacon_on = qla24xx_beacon_on,
2140 .beacon_off = qla24xx_beacon_off,
2141 .beacon_blink = qla24xx_beacon_blink,
338c9161 2142 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2143 .write_optrom = qla24xx_write_optrom_data,
2144 .get_flash_version = qla24xx_get_flash_version,
bad75002 2145 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2146 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2147 .abort_isp = qla2x00_abort_isp,
7ec0effd 2148 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2149 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2150};
2151
3a03eb79
AV		 2152static struct isp_operations qla81xx_isp_ops = {
2153 .pci_config = qla25xx_pci_config,
2154 .reset_chip = qla24xx_reset_chip,
2155 .chip_diag = qla24xx_chip_diag,
2156 .config_rings = qla24xx_config_rings,
2157 .reset_adapter = qla24xx_reset_adapter,
2158 .nvram_config = qla81xx_nvram_config,
2159 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2160 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2161 .pci_info_str = qla24xx_pci_info_str,
2162 .fw_version_str = qla24xx_fw_version_str,
2163 .intr_handler = qla24xx_intr_handler,
2164 .enable_intrs = qla24xx_enable_intrs,
2165 .disable_intrs = qla24xx_disable_intrs,
2166 .abort_command = qla24xx_abort_command,
2167 .target_reset = qla24xx_abort_target,
2168 .lun_reset = qla24xx_lun_reset,
2169 .fabric_login = qla24xx_login_fabric,
2170 .fabric_logout = qla24xx_fabric_logout,
2171 .calc_req_entries = NULL,
2172 .build_iocbs = NULL,
2173 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2174 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2175 .read_nvram = NULL,
2176 .write_nvram = NULL,
3a03eb79
AV		 2177 .fw_dump = qla81xx_fw_dump,
2178 .beacon_on = qla24xx_beacon_on,
2179 .beacon_off = qla24xx_beacon_off,
6246b8a1 2180 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2181 .read_optrom = qla25xx_read_optrom_data,
2182 .write_optrom = qla24xx_write_optrom_data,
2183 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2184 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2185 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2186 .abort_isp = qla2x00_abort_isp,
7ec0effd 2187 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2188 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2189};
2190
2191static struct isp_operations qla82xx_isp_ops = {
2192 .pci_config = qla82xx_pci_config,
2193 .reset_chip = qla82xx_reset_chip,
2194 .chip_diag = qla24xx_chip_diag,
2195 .config_rings = qla82xx_config_rings,
2196 .reset_adapter = qla24xx_reset_adapter,
2197 .nvram_config = qla81xx_nvram_config,
2198 .update_fw_options = qla24xx_update_fw_options,
2199 .load_risc = qla82xx_load_risc,
9d55ca66 2200 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2201 .fw_version_str = qla24xx_fw_version_str,
2202 .intr_handler = qla82xx_intr_handler,
2203 .enable_intrs = qla82xx_enable_intrs,
2204 .disable_intrs = qla82xx_disable_intrs,
2205 .abort_command = qla24xx_abort_command,
2206 .target_reset = qla24xx_abort_target,
2207 .lun_reset = qla24xx_lun_reset,
2208 .fabric_login = qla24xx_login_fabric,
2209 .fabric_logout = qla24xx_fabric_logout,
2210 .calc_req_entries = NULL,
2211 .build_iocbs = NULL,
2212 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2213 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2214 .read_nvram = qla24xx_read_nvram_data,
2215 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2216 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2217 .beacon_on = qla82xx_beacon_on,
2218 .beacon_off = qla82xx_beacon_off,
2219 .beacon_blink = NULL,
a9083016
GM		 2220 .read_optrom = qla82xx_read_optrom_data,
2221 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2222 .get_flash_version = qla82xx_get_flash_version,
a9083016 2223 .start_scsi = qla82xx_start_scsi,
d7459527 2224 .start_scsi_mq = NULL,
a9083016 2225 .abort_isp = qla82xx_abort_isp,
706f457d 2226 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2227 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2228};
2229
7ec0effd
AD		 2230static struct isp_operations qla8044_isp_ops = {
2231 .pci_config = qla82xx_pci_config,
2232 .reset_chip = qla82xx_reset_chip,
2233 .chip_diag = qla24xx_chip_diag,
2234 .config_rings = qla82xx_config_rings,
2235 .reset_adapter = qla24xx_reset_adapter,
2236 .nvram_config = qla81xx_nvram_config,
2237 .update_fw_options = qla24xx_update_fw_options,
2238 .load_risc = qla82xx_load_risc,
2239 .pci_info_str = qla24xx_pci_info_str,
2240 .fw_version_str = qla24xx_fw_version_str,
2241 .intr_handler = qla8044_intr_handler,
2242 .enable_intrs = qla82xx_enable_intrs,
2243 .disable_intrs = qla82xx_disable_intrs,
2244 .abort_command = qla24xx_abort_command,
2245 .target_reset = qla24xx_abort_target,
2246 .lun_reset = qla24xx_lun_reset,
2247 .fabric_login = qla24xx_login_fabric,
2248 .fabric_logout = qla24xx_fabric_logout,
2249 .calc_req_entries = NULL,
2250 .build_iocbs = NULL,
2251 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2252 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2253 .read_nvram = NULL,
2254 .write_nvram = NULL,
a1b23c5a 2255 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2256 .beacon_on = qla82xx_beacon_on,
2257 .beacon_off = qla82xx_beacon_off,
2258 .beacon_blink = NULL,
888e639d 2259 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2260 .write_optrom = qla8044_write_optrom_data,
2261 .get_flash_version = qla82xx_get_flash_version,
2262 .start_scsi = qla82xx_start_scsi,
d7459527 2263 .start_scsi_mq = NULL,
7ec0effd
AD		 2264 .abort_isp = qla8044_abort_isp,
2265 .iospace_config = qla82xx_iospace_config,
2266 .initialize_adapter = qla2x00_initialize_adapter,
2267};
2268
6246b8a1
GM		 2269static struct isp_operations qla83xx_isp_ops = {
2270 .pci_config = qla25xx_pci_config,
2271 .reset_chip = qla24xx_reset_chip,
2272 .chip_diag = qla24xx_chip_diag,
2273 .config_rings = qla24xx_config_rings,
2274 .reset_adapter = qla24xx_reset_adapter,
2275 .nvram_config = qla81xx_nvram_config,
2276 .update_fw_options = qla81xx_update_fw_options,
2277 .load_risc = qla81xx_load_risc,
2278 .pci_info_str = qla24xx_pci_info_str,
2279 .fw_version_str = qla24xx_fw_version_str,
2280 .intr_handler = qla24xx_intr_handler,
2281 .enable_intrs = qla24xx_enable_intrs,
2282 .disable_intrs = qla24xx_disable_intrs,
2283 .abort_command = qla24xx_abort_command,
2284 .target_reset = qla24xx_abort_target,
2285 .lun_reset = qla24xx_lun_reset,
2286 .fabric_login = qla24xx_login_fabric,
2287 .fabric_logout = qla24xx_fabric_logout,
2288 .calc_req_entries = NULL,
2289 .build_iocbs = NULL,
2290 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2291 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2292 .read_nvram = NULL,
2293 .write_nvram = NULL,
2294 .fw_dump = qla83xx_fw_dump,
2295 .beacon_on = qla24xx_beacon_on,
2296 .beacon_off = qla24xx_beacon_off,
2297 .beacon_blink = qla83xx_beacon_blink,
2298 .read_optrom = qla25xx_read_optrom_data,
2299 .write_optrom = qla24xx_write_optrom_data,
2300 .get_flash_version = qla24xx_get_flash_version,
2301 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2302 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2303 .abort_isp = qla2x00_abort_isp,
2304 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2305 .initialize_adapter = qla2x00_initialize_adapter,
2306};
2307
2308static struct isp_operations qlafx00_isp_ops = {
2309 .pci_config = qlafx00_pci_config,
2310 .reset_chip = qlafx00_soft_reset,
2311 .chip_diag = qlafx00_chip_diag,
2312 .config_rings = qlafx00_config_rings,
2313 .reset_adapter = qlafx00_soft_reset,
2314 .nvram_config = NULL,
2315 .update_fw_options = NULL,
2316 .load_risc = NULL,
2317 .pci_info_str = qlafx00_pci_info_str,
2318 .fw_version_str = qlafx00_fw_version_str,
2319 .intr_handler = qlafx00_intr_handler,
2320 .enable_intrs = qlafx00_enable_intrs,
2321 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2322 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2323 .target_reset = qlafx00_abort_target,
2324 .lun_reset = qlafx00_lun_reset,
2325 .fabric_login = NULL,
2326 .fabric_logout = NULL,
2327 .calc_req_entries = NULL,
2328 .build_iocbs = NULL,
2329 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2330 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2331 .read_nvram = qla24xx_read_nvram_data,
2332 .write_nvram = qla24xx_write_nvram_data,
2333 .fw_dump = NULL,
2334 .beacon_on = qla24xx_beacon_on,
2335 .beacon_off = qla24xx_beacon_off,
2336 .beacon_blink = NULL,
2337 .read_optrom = qla24xx_read_optrom_data,
2338 .write_optrom = qla24xx_write_optrom_data,
2339 .get_flash_version = qla24xx_get_flash_version,
2340 .start_scsi = qlafx00_start_scsi,
d7459527 2341 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2342 .abort_isp = qlafx00_abort_isp,
2343 .iospace_config = qlafx00_iospace_config,
2344 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2345};
2346
f73cb695
CD		 2347static struct isp_operations qla27xx_isp_ops = {
2348 .pci_config = qla25xx_pci_config,
2349 .reset_chip = qla24xx_reset_chip,
2350 .chip_diag = qla24xx_chip_diag,
2351 .config_rings = qla24xx_config_rings,
2352 .reset_adapter = qla24xx_reset_adapter,
2353 .nvram_config = qla81xx_nvram_config,
2354 .update_fw_options = qla81xx_update_fw_options,
2355 .load_risc = qla81xx_load_risc,
2356 .pci_info_str = qla24xx_pci_info_str,
2357 .fw_version_str = qla24xx_fw_version_str,
2358 .intr_handler = qla24xx_intr_handler,
2359 .enable_intrs = qla24xx_enable_intrs,
2360 .disable_intrs = qla24xx_disable_intrs,
2361 .abort_command = qla24xx_abort_command,
2362 .target_reset = qla24xx_abort_target,
2363 .lun_reset = qla24xx_lun_reset,
2364 .fabric_login = qla24xx_login_fabric,
2365 .fabric_logout = qla24xx_fabric_logout,
2366 .calc_req_entries = NULL,
2367 .build_iocbs = NULL,
2368 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2369 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2370 .read_nvram = NULL,
2371 .write_nvram = NULL,
2372 .fw_dump = qla27xx_fwdump,
2373 .beacon_on = qla24xx_beacon_on,
2374 .beacon_off = qla24xx_beacon_off,
2375 .beacon_blink = qla83xx_beacon_blink,
2376 .read_optrom = qla25xx_read_optrom_data,
2377 .write_optrom = qla24xx_write_optrom_data,
2378 .get_flash_version = qla24xx_get_flash_version,
2379 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2380 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2381 .abort_isp = qla2x00_abort_isp,
2382 .iospace_config = qla83xx_iospace_config,
2383 .initialize_adapter = qla2x00_initialize_adapter,
2384};
2385
ea5b6382 2386static inline void
e315cd28 2387qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2388{
2389 ha->device_type = DT_EXTENDED_IDS;
2390 switch (ha->pdev->device) {
2391 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2392 ha->isp_type |= DT_ISP2100;
ea5b6382 2393 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2394 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2395 break;
2396 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2397 ha->isp_type |= DT_ISP2200;
ea5b6382 2398 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2399 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2400 break;
2401 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2402 ha->isp_type |= DT_ISP2300;
4a59f71d 2403 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2404 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2405 break;
2406 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2407 ha->isp_type |= DT_ISP2312;
4a59f71d 2408 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2409 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2410 break;
2411 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2412 ha->isp_type |= DT_ISP2322;
4a59f71d 2413 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2414 if (ha->pdev->subsystem_vendor == 0x1028 &&
2415 ha->pdev->subsystem_device == 0x0170)
2416 ha->device_type |= DT_OEM_001;
441d1072 2417 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2418 break;
2419 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2420 ha->isp_type |= DT_ISP6312;
441d1072 2421 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2422 break;
2423 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2424 ha->isp_type |= DT_ISP6322;
441d1072 2425 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2426 break;
2427 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2428 ha->isp_type |= DT_ISP2422;
4a59f71d 2429 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2430 ha->device_type |= DT_FWI2;
c76f2c01 2431 ha->device_type |= DT_IIDMA;
441d1072 2432 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2433 break;
2434 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2435 ha->isp_type |= DT_ISP2432;
4a59f71d 2436 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2437 ha->device_type |= DT_FWI2;
c76f2c01 2438 ha->device_type |= DT_IIDMA;
441d1072 2439 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2440 break;
4d4df193 2441 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2442 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2443 ha->device_type |= DT_ZIO_SUPPORTED;
2444 ha->device_type |= DT_FWI2;
2445 ha->device_type |= DT_IIDMA;
2446 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2447 break;
044cc6c8 2448 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2449 ha->isp_type |= DT_ISP5422;
e428924c 2450 ha->device_type |= DT_FWI2;
441d1072 2451 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2452 break;
044cc6c8 2453 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2454 ha->isp_type |= DT_ISP5432;
e428924c 2455 ha->device_type |= DT_FWI2;
441d1072 2456 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2457 break;
c3a2f0df 2458 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2459 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2460 ha->device_type |= DT_ZIO_SUPPORTED;
2461 ha->device_type |= DT_FWI2;
2462 ha->device_type |= DT_IIDMA;
441d1072 2463 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2464 break;
3a03eb79 2465 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2466 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2467 ha->device_type |= DT_ZIO_SUPPORTED;
2468 ha->device_type |= DT_FWI2;
2469 ha->device_type |= DT_IIDMA;
2470 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2471 break;
a9083016 2472 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2473 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2474 ha->device_type |= DT_ZIO_SUPPORTED;
2475 ha->device_type |= DT_FWI2;
2476 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2477 /* Initialize 82XX ISP flags */
2478 qla82xx_init_flags(ha);
2479 break;
7ec0effd 2480 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2481 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2482 ha->device_type |= DT_ZIO_SUPPORTED;
2483 ha->device_type |= DT_FWI2;
2484 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2485 /* Initialize 82XX ISP flags */
2486 qla82xx_init_flags(ha);
2487 break;
6246b8a1 2488 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2489 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2490 ha->device_type |= DT_ZIO_SUPPORTED;
2491 ha->device_type |= DT_FWI2;
2492 ha->device_type |= DT_IIDMA;
2493 ha->device_type |= DT_T10_PI;
2494 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2495 break;
2496 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2497 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2498 ha->device_type |= DT_ZIO_SUPPORTED;
2499 ha->device_type |= DT_FWI2;
2500 ha->device_type |= DT_IIDMA;
2501 ha->device_type |= DT_T10_PI;
2502 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2503 break;
8ae6d9c7 2504 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2505 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2506 break;
f73cb695 2507 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2508 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2509 ha->device_type |= DT_ZIO_SUPPORTED;
2510 ha->device_type |= DT_FWI2;
2511 ha->device_type |= DT_IIDMA;
8ce3f570 2512 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2513 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2514 break;
2c5bbbb2 2515 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2516 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2517 ha->device_type |= DT_ZIO_SUPPORTED;
2518 ha->device_type |= DT_FWI2;
2519 ha->device_type |= DT_IIDMA;
8ce3f570 2520 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2522 break;
2b48992f 2523 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2524 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2525 ha->device_type |= DT_ZIO_SUPPORTED;
2526 ha->device_type |= DT_FWI2;
2527 ha->device_type |= DT_IIDMA;
8ce3f570 2528 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2529 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2530 break;
ea5b6382 2531 }
e5b68a61 2532
a9083016 2533 if (IS_QLA82XX(ha))
43a9c38b 2534 ha->port_no = ha->portnum & 1;
f73cb695 2535 else {
a9083016
GM		 2536 /* Get adapter physical port no from interrupt pin register. */
2537 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2538 if (IS_QLA27XX(ha))
2539 ha->port_no--;
2540 else
2541 ha->port_no = !(ha->port_no & 1);
2542 }
a9083016 2543
7c3df132 2544 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2545 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2546 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2547}
2548
1e99e33a
AV		 2549static void
2550qla2xxx_scan_start(struct Scsi_Host *shost)
2551{
e315cd28 2552 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2553
cbc8eb67
AV		 2554 if (vha->hw->flags.running_gold_fw)
2555 return;
2556
e315cd28
AC		 2557 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2558 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2559 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2560 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2561}
2562
2563static int
2564qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2565{
e315cd28 2566 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2567
a5dd506e
BK		 2568 if (test_bit(UNLOADING, &vha->dpc_flags))
2569 return 1;
e315cd28 2570 if (!vha->host)
1e99e33a 2571 return 1;
e315cd28 2572 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2573 return 1;
2574
e315cd28 2575 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2576}
2577
ec7193e2
QT		 2578static void qla2x00_iocb_work_fn(struct work_struct *work)
2579{
2580 struct scsi_qla_host *vha = container_of(work,
2581 struct scsi_qla_host, iocb_work);
2582 int cnt = 0;
2583
2584 while (!list_empty(&vha->work_list)) {
2585 qla2x00_do_work(vha);
2586 cnt++;
2587 if (cnt > 10)
2588 break;
2589 }
2590}
2591
1da177e4
LT		 2592/*
2593 * PCI driver interface
2594 */
6f039790 2595static int
7ee61397 2596qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2597{
a1541d5a 2598 int ret = -ENODEV;
1da177e4 2599 struct Scsi_Host *host;
e315cd28
AC		 2600 scsi_qla_host_t *base_vha = NULL;
2601 struct qla_hw_data *ha;
29856e28 2602 char pci_info[30];
7d613ac6 2603 char fw_str[30], wq_name[30];
5433383e 2604 struct scsi_host_template *sht;
642ef983 2605 int bars, mem_only = 0;
e315cd28 2606 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2607 struct req_que *req = NULL;
2608 struct rsp_que *rsp = NULL;
5601236b 2609 int i;
d7459527 2610
285d0321 2611 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2612 sht = &qla2xxx_driver_template;
5433383e 2613 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2614 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2615 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2616 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2617 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2618 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2619 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2620 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2621 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2622 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2623 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2624 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2625 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2626 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2627 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2628 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2629 mem_only = 1;
7c3df132
SK		 2630 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2631 "Mem only adapter.\n");
285d0321 2632 }
7c3df132
SK		 2633 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2634 "Bars=%d.\n", bars);
285d0321 2635
09483916
BH		 2636 if (mem_only) {
2637 if (pci_enable_device_mem(pdev))
ddff7ed4 2638 return ret;
09483916
BH		 2639 } else {
2640 if (pci_enable_device(pdev))
ddff7ed4 2641 return ret;
09483916 2642 }
285d0321 2643
0927678f
JB		 2644 /* This may fail but that's ok */
2645 pci_enable_pcie_error_reporting(pdev);
285d0321 2646
e315cd28
AC		 2647 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2648 if (!ha) {
7c3df132
SK		 2649 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2650 "Unable to allocate memory for ha.\n");
ddff7ed4 2651 goto disable_device;
1da177e4 2652 }
7c3df132
SK		 2653 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2654 "Memory allocated for ha=%p.\n", ha);
e315cd28 2655 ha->pdev = pdev;
2d70c103 2656 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2657 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2658 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2659 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2660 spin_lock_init(&ha->tgt.atio_lock);
2661
1da177e4
LT		 2662
2663 /* Clear our data area */
285d0321 2664 ha->bars = bars;
09483916 2665 ha->mem_only = mem_only;
df4bf0bb 2666 spin_lock_init(&ha->hardware_lock);
339aa70e 2667 spin_lock_init(&ha->vport_slock);
a9b6f722 2668 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2669 mutex_init(&ha->optrom_mutex);
1da177e4 2670
ea5b6382
AV		 2671 /* Set ISP-type information. */
2672 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2673
2674 /* Set EEH reset type to fundamental if required by hba */
95676112 2675 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2676 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2677 pdev->needs_freset = 1;
ca79cf66 2678
cba1e47f
CD		 2679 ha->prev_topology = 0;
2680 ha->init_cb_size = sizeof(init_cb_t);
2681 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2682 ha->optrom_size = OPTROM_SIZE_2300;
2683
abbd8870 2684 /* Assign ISP specific operations. */
1da177e4 2685 if (IS_QLA2100(ha)) {
642ef983 2686 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2687 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2688 req_length = REQUEST_ENTRY_CNT_2100;
2689 rsp_length = RESPONSE_ENTRY_CNT_2100;
2690 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2691 ha->gid_list_info_size = 4;
3a03eb79
AV		 2692 ha->flash_conf_off = ~0;
2693 ha->flash_data_off = ~0;
2694 ha->nvram_conf_off = ~0;
2695 ha->nvram_data_off = ~0;
fd34f556 2696 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2697 } else if (IS_QLA2200(ha)) {
642ef983 2698 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2699 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2700 req_length = REQUEST_ENTRY_CNT_2200;
2701 rsp_length = RESPONSE_ENTRY_CNT_2100;
2702 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2703 ha->gid_list_info_size = 4;
3a03eb79
AV		 2704 ha->flash_conf_off = ~0;
2705 ha->flash_data_off = ~0;
2706 ha->nvram_conf_off = ~0;
2707 ha->nvram_data_off = ~0;
fd34f556 2708 ha->isp_ops = &qla2100_isp_ops;
fca29703 2709 } else if (IS_QLA23XX(ha)) {
642ef983 2710 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2711 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2712 req_length = REQUEST_ENTRY_CNT_2200;
2713 rsp_length = RESPONSE_ENTRY_CNT_2300;
2714 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2715 ha->gid_list_info_size = 6;
854165f4
AV		 2716 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2717 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2718 ha->flash_conf_off = ~0;
2719 ha->flash_data_off = ~0;
2720 ha->nvram_conf_off = ~0;
2721 ha->nvram_data_off = ~0;
fd34f556 2722 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2723 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2724 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2725 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2726 req_length = REQUEST_ENTRY_CNT_24XX;
2727 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2728 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2729 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2730 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2731 ha->gid_list_info_size = 8;
854165f4 2732 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2733 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2734 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2735 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2736 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2737 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2738 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2739 } else if (IS_QLA25XX(ha)) {
642ef983 2740 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2741 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2742 req_length = REQUEST_ENTRY_CNT_24XX;
2743 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2744 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2745 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2746 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2747 ha->gid_list_info_size = 8;
2748 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2749 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2750 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2751 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2752 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2753 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2754 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2755 } else if (IS_QLA81XX(ha)) {
642ef983 2756 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2757 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2758 req_length = REQUEST_ENTRY_CNT_24XX;
2759 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2760 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2761 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2762 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2763 ha->gid_list_info_size = 8;
2764 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2765 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2766 ha->isp_ops = &qla81xx_isp_ops;
2767 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2768 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2769 ha->nvram_conf_off = ~0;
2770 ha->nvram_data_off = ~0;
a9083016 2771 } else if (IS_QLA82XX(ha)) {
642ef983 2772 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2773 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2774 req_length = REQUEST_ENTRY_CNT_82XX;
2775 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2776 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2777 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2778 ha->gid_list_info_size = 8;
2779 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2780 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2781 ha->isp_ops = &qla82xx_isp_ops;
2782 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2783 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2784 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2785 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2786 } else if (IS_QLA8044(ha)) {
2787 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2788 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2789 req_length = REQUEST_ENTRY_CNT_82XX;
2790 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2791 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2792 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2793 ha->gid_list_info_size = 8;
2794 ha->optrom_size = OPTROM_SIZE_83XX;
2795 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2796 ha->isp_ops = &qla8044_isp_ops;
2797 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2798 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2799 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2800 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2801 } else if (IS_QLA83XX(ha)) {
7d613ac6 2802 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2803 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2804 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2805 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2806 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2807 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2808 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2809 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2810 ha->gid_list_info_size = 8;
2811 ha->optrom_size = OPTROM_SIZE_83XX;
2812 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2813 ha->isp_ops = &qla83xx_isp_ops;
2814 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2815 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2816 ha->nvram_conf_off = ~0;
2817 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2818 } else if (IS_QLAFX00(ha)) {
2819 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2820 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2821 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2822 req_length = REQUEST_ENTRY_CNT_FX00;
2823 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2824 ha->isp_ops = &qlafx00_isp_ops;
2825 ha->port_down_retry_count = 30; /* default value */
2826 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2827 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2828 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2829 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2830 ha->mr.host_info_resend = false;
2831 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2832 } else if (IS_QLA27XX(ha)) {
2833 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2834 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2835 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2836 req_length = REQUEST_ENTRY_CNT_83XX;
2837 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2838 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2839 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2840 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2841 ha->gid_list_info_size = 8;
2842 ha->optrom_size = OPTROM_SIZE_83XX;
2843 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2844 ha->isp_ops = &qla27xx_isp_ops;
2845 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2846 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2847 ha->nvram_conf_off = ~0;
2848 ha->nvram_data_off = ~0;
1da177e4 2849 }
6246b8a1 2850
7c3df132
SK		 2851 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2852 "mbx_count=%d, req_length=%d, "
2853 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2854 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2855 "max_fibre_devices=%d.\n",
7c3df132
SK		 2856 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2857 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2858 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2859 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2860 "isp_ops=%p, flash_conf_off=%d, "
2861 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2862 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2863 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2864
2865 /* Configure PCI I/O space */
2866 ret = ha->isp_ops->iospace_config(ha);
2867 if (ret)
0a63ad12 2868 goto iospace_config_failed;
706f457d
GM		 2869
2870 ql_log_pci(ql_log_info, pdev, 0x001d,
2871 "Found an ISP%04X irq %d iobase 0x%p.\n",
2872 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2873 mutex_init(&ha->vport_lock);
d7459527 2874 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2875 init_completion(&ha->mbx_cmd_comp);
2876 complete(&ha->mbx_cmd_comp);
2877 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2878 init_completion(&ha->dcbx_comp);
f356bef1 2879 init_completion(&ha->lb_portup_comp);
1da177e4 2880
2c3dfe3f 2881 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2882
53303c42 2883 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2884 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2885 "64 Bit addressing is %s.\n",
2886 ha->flags.enable_64bit_addressing ? "enable" :
2887 "disable");
73208dfd 2888 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2889 if (ret) {
7c3df132
SK		 2890 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2891 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2892
e315cd28
AC		 2893 goto probe_hw_failed;
2894 }
2895
73208dfd 2896 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2897 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2898 req->max_q_depth = ql2xmaxqdepth;
2899
e315cd28
AC		 2900
2901 base_vha = qla2x00_create_host(sht, ha);
2902 if (!base_vha) {
a1541d5a 2903 ret = -ENOMEM;
6e9f21f3 2904 qla2x00_mem_free(ha);
2afa19a9
AC		 2905 qla2x00_free_req_que(ha, req);
2906 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2907 goto probe_hw_failed;
1da177e4
LT		 2908 }
2909
e315cd28 2910 pci_set_drvdata(pdev, base_vha);
6b383979 2911 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2912
e315cd28 2913 host = base_vha->host;
2afa19a9 2914 base_vha->req = req;
73208dfd 2915 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2916 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2917 else
e315cd28
AC		 2918 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2919 base_vha->vp_idx;
58548cb5 2920
8ae6d9c7
GM		 2921 /* Setup fcport template structure. */
2922 ha->mr.fcport.vha = base_vha;
2923 ha->mr.fcport.port_type = FCT_UNKNOWN;
2924 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2925 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2926 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2927 ha->mr.fcport.scan_state = 1;
2928
58548cb5
GM		 2929 /* Set the SG table size based on ISP type */
2930 if (!IS_FWI2_CAPABLE(ha)) {
2931 if (IS_QLA2100(ha))
2932 host->sg_tablesize = 32;
2933 } else {
2934 if (!IS_QLA82XX(ha))
2935 host->sg_tablesize = QLA_SG_ALL;
2936 }
642ef983 2937 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2938 host->cmd_per_lun = 3;
2939 host->unique_id = host->host_no;
e02587d7 2940 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2941 host->max_cmd_len = 32;
2942 else
2943 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2944 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2945 /* Older HBAs support only 16-bit LUNs */
2946 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2947 ql2xmaxlun > 0xffff)
2948 host->max_lun = 0xffff;
2949 else
2950 host->max_lun = ql2xmaxlun;
e315cd28 2951 host->transportt = qla2xxx_transport_template;
9a069e19 2952 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2953
7c3df132
SK		 2954 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2955 "max_id=%d this_id=%d "
2956 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2957 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2958 host->this_id, host->cmd_per_lun, host->unique_id,
2959 host->max_cmd_len, host->max_channel, host->max_lun,
2960 host->transportt, sht->vendor_id);
2961
d7459527
MH		 2962 /* Set up the irqs */
2963 ret = qla2x00_request_irqs(ha, rsp);
2964 if (ret)
2965 goto probe_init_failed;
2966
9a347ff4
CD		 2967 /* Alloc arrays of request and response ring ptrs */
2968 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2969 ql_log(ql_log_fatal, base_vha, 0x003d,
2970 "Failed to allocate memory for queue pointers..."
2971 "aborting.\n");
2972 goto probe_init_failed;
2973 }
2974
5601236b
MH		 2975 if (ha->mqenable && shost_use_blk_mq(host)) {
2976 /* number of hardware queues supported by blk/scsi-mq*/
2977 host->nr_hw_queues = ha->max_qpairs;
2978
2979 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2980 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2981 } else
2982 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2983 "blk/scsi-mq disabled.\n");
2984
2d70c103 2985 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2986
90a86fc0
JC		 2987 pci_save_state(pdev);
2988
9a347ff4 2989 /* Assign back pointers */
2afa19a9
AC		 2990 rsp->req = req;
2991 req->rsp = rsp;
9a347ff4 2992
8ae6d9c7
GM		 2993 if (IS_QLAFX00(ha)) {
2994 ha->rsp_q_map[0] = rsp;
2995 ha->req_q_map[0] = req;
2996 set_bit(0, ha->req_qid_map);
2997 set_bit(0, ha->rsp_qid_map);
2998 }
2999
08029990
AV		 3000 /* FWI2-capable only. */
3001 req->req_q_in = &ha->iobase->isp24.req_q_in;
3002 req->req_q_out = &ha->iobase->isp24.req_q_out;
3003 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3004 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3005 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3006 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3007 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3008 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3009 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3010 }
3011
8ae6d9c7
GM		 3012 if (IS_QLAFX00(ha)) {
3013 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3014 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3015 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3016 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3017 }
3018
7ec0effd 3019 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3020 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3021 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3022 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3023 }
3024
7c3df132
SK		 3025 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3026 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3027 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3028 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3029 "req->req_q_in=%p req->req_q_out=%p "
3030 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3031 req->req_q_in, req->req_q_out,
3032 rsp->rsp_q_in, rsp->rsp_q_out);
3033 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3034 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3035 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3036 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3037 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3038 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3039
8ae6d9c7 3040 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3041 ql_log(ql_log_fatal, base_vha, 0x00d6,
3042 "Failed to initialize adapter - Adapter flags %x.\n",
3043 base_vha->device_flags);
1da177e4 3044
a9083016
GM		 3045 if (IS_QLA82XX(ha)) {
3046 qla82xx_idc_lock(ha);
3047 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3048 QLA8XXX_DEV_FAILED);
a9083016 3049 qla82xx_idc_unlock(ha);
7c3df132
SK		 3050 ql_log(ql_log_fatal, base_vha, 0x00d7,
3051 "HW State: FAILED.\n");
7ec0effd
AD		 3052 } else if (IS_QLA8044(ha)) {
3053 qla8044_idc_lock(ha);
3054 qla8044_wr_direct(base_vha,
3055 QLA8044_CRB_DEV_STATE_INDEX,
3056 QLA8XXX_DEV_FAILED);
3057 qla8044_idc_unlock(ha);
3058 ql_log(ql_log_fatal, base_vha, 0x0150,
3059 "HW State: FAILED.\n");
a9083016
GM		 3060 }
3061
a1541d5a 3062 ret = -ENODEV;
1da177e4
LT		 3063 goto probe_failed;
3064 }
3065
3b1bef64
CD		 3066 if (IS_QLAFX00(ha))
3067 host->can_queue = QLAFX00_MAX_CANQUEUE;
3068 else
3069 host->can_queue = req->num_outstanding_cmds - 10;
3070
3071 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3072 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3073 host->can_queue, base_vha->req,
3074 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3075
093df737 3076 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3077 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3078 /* Create start of day qpairs for Block MQ */
3079 if (shost_use_blk_mq(host)) {
3080 for (i = 0; i < ha->max_qpairs; i++)
3081 qla2xxx_create_qpair(base_vha, 5, 0);
3082 }
3083 }
68ca949c 3084
cbc8eb67
AV		 3085 if (ha->flags.running_gold_fw)
3086 goto skip_dpc;
3087
1da177e4
LT		 3088 /*
3089 * Startup the kernel thread for this host adapter
3090 */
39a11240 3091 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3092 "%s_dpc", base_vha->host_str);
39a11240 3093 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3094 ql_log(ql_log_fatal, base_vha, 0x00ed,
3095 "Failed to start DPC thread.\n");
39a11240 3096 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3097 goto probe_failed;
3098 }
7c3df132
SK		 3099 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3100 "DPC thread started successfully.\n");
1da177e4 3101
2d70c103
NB		 3102 /*
3103 * If we're not coming up in initiator mode, we might sit for
3104 * a while without waking up the dpc thread, which leads to a
3105 * stuck process warning. So just kick the dpc once here and
3106 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3107 */
3108 qla2xxx_wake_dpc(base_vha);
3109
ec7193e2 3110 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3111 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3112
81178772
SK		 3113 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3114 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3115 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3116 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3117
3118 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3119 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3120 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3121 INIT_WORK(&ha->idc_state_handler,
3122 qla83xx_idc_state_handler_work);
3123 INIT_WORK(&ha->nic_core_unrecoverable,
3124 qla83xx_nic_core_unrecoverable_work);
3125 }
3126
cbc8eb67 3127skip_dpc:
e315cd28
AC		 3128 list_add_tail(&base_vha->list, &ha->vp_list);
3129 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3130
3131 /* Initialized the timer */
e315cd28 3132 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3133 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3134 "Started qla2x00_timer with "
3135 "interval=%d.\n", WATCH_INTERVAL);
3136 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3137 "Detected hba at address=%p.\n",
3138 ha);
d19044c3 3139
e02587d7 3140 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3141 if (ha->fw_attributes & BIT_4) {
9e522cd8 3142 int prot = 0, guard;
bad75002 3143 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3144 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3145 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3146 if (ql2xenabledif == 1)
3147 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3148 scsi_host_set_prot(host,
8cb2049c 3149 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3150 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3151 | SHOST_DIF_TYPE3_PROTECTION
3152 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3153 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3154 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3155
3156 guard = SHOST_DIX_GUARD_CRC;
3157
3158 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3159 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3160 guard |= SHOST_DIX_GUARD_IP;
3161
3162 scsi_host_set_guard(host, guard);
bad75002
AE		 3163 } else
3164 base_vha->flags.difdix_supported = 0;
3165 }
3166
a9083016
GM		 3167 ha->isp_ops->enable_intrs(ha);
3168
1fe19ee4
AB		 3169 if (IS_QLAFX00(ha)) {
3170 ret = qlafx00_fx_disc(base_vha,
3171 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3172 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3173 QLA_SG_ALL : 128;
3174 }
3175
a1541d5a
AV		 3176 ret = scsi_add_host(host, &pdev->dev);
3177 if (ret)
3178 goto probe_failed;
3179
1486400f
MR		 3180 base_vha->flags.init_done = 1;
3181 base_vha->flags.online = 1;
edaa5c74 3182 ha->prev_minidump_failed = 0;
1486400f 3183
7c3df132
SK		 3184 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3185 "Init done and hba is online.\n");
3186
726b8548
QT		 3187 if (qla_ini_mode_enabled(base_vha) ||
3188 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3189 scsi_scan_host(host);
3190 else
3191 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3192 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3193
e315cd28 3194 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3195
8ae6d9c7 3196 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3197 ret = qlafx00_fx_disc(base_vha,
3198 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3199
3200 /* Register system information */
3201 ret = qlafx00_fx_disc(base_vha,
3202 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3203 }
3204
e315cd28 3205 qla2x00_init_host_attr(base_vha);
a1541d5a 3206
e315cd28 3207 qla2x00_dfs_setup(base_vha);
df613b96 3208
03eb912a
AB		 3209 ql_log(ql_log_info, base_vha, 0x00fb,
3210 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3211 ql_log(ql_log_info, base_vha, 0x00fc,
3212 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3213 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3214 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3215 base_vha->host_no,
df57caba 3216 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3217
2d70c103
NB		 3218 qlt_add_target(ha, base_vha);
3219
6b383979 3220 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3221
3222 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3223 return -ENODEV;
3224
1da177e4
LT		 3225 return 0;
3226
6e9f21f3 3227probe_init_failed:
2afa19a9 3228 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3229 ha->req_q_map[0] = NULL;
3230 clear_bit(0, ha->req_qid_map);
2afa19a9 3231 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3232 ha->rsp_q_map[0] = NULL;
3233 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3234 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3235
1da177e4 3236probe_failed:
b9978769
AV		 3237 if (base_vha->timer_active)
3238 qla2x00_stop_timer(base_vha);
3239 base_vha->flags.online = 0;
3240 if (ha->dpc_thread) {
3241 struct task_struct *t = ha->dpc_thread;
3242
3243 ha->dpc_thread = NULL;
3244 kthread_stop(t);
3245 }
3246
e315cd28 3247 qla2x00_free_device(base_vha);
1da177e4 3248
e315cd28 3249 scsi_host_put(base_vha->host);
1da177e4 3250
e315cd28 3251probe_hw_failed:
1a2fbf18
JL		 3252 qla2x00_clear_drv_active(ha);
3253
0a63ad12 3254iospace_config_failed:
7ec0effd 3255 if (IS_P3P_TYPE(ha)) {
0a63ad12 3256 if (!ha->nx_pcibase)
f73cb695 3257 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3258 if (!ql2xdbwr)
f73cb695 3259 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3260 } else {
3261 if (ha->iobase)
3262 iounmap(ha->iobase);
8ae6d9c7
GM		 3263 if (ha->cregbase)
3264 iounmap(ha->cregbase);
a9083016 3265 }
e315cd28
AC		 3266 pci_release_selected_regions(ha->pdev, ha->bars);
3267 kfree(ha);
1da177e4 3268
ddff7ed4 3269disable_device:
e315cd28 3270 pci_disable_device(pdev);
a1541d5a 3271 return ret;
1da177e4 3272}
1da177e4 3273
e30d1756
MI		 3274static void
3275qla2x00_shutdown(struct pci_dev *pdev)
3276{
3277 scsi_qla_host_t *vha;
3278 struct qla_hw_data *ha;
3279
552f3f9a
MI		 3280 if (!atomic_read(&pdev->enable_cnt))
3281 return;
3282
e30d1756
MI		 3283 vha = pci_get_drvdata(pdev);
3284 ha = vha->hw;
3285
42479343
AB		 3286 /* Notify ISPFX00 firmware */
3287 if (IS_QLAFX00(ha))
3288 qlafx00_driver_shutdown(vha, 20);
3289
e30d1756
MI		 3290 /* Turn-off FCE trace */
3291 if (ha->flags.fce_enabled) {
3292 qla2x00_disable_fce_trace(vha, NULL, NULL);
3293 ha->flags.fce_enabled = 0;
3294 }
3295
3296 /* Turn-off EFT trace */
3297 if (ha->eft)
3298 qla2x00_disable_eft_trace(vha);
3299
3300 /* Stop currently executing firmware. */
3301 qla2x00_try_to_stop_firmware(vha);
3302
3303 /* Turn adapter off line */
3304 vha->flags.online = 0;
3305
3306 /* turn-off interrupts on the card */
3307 if (ha->interrupts_on) {
3308 vha->flags.init_done = 0;
3309 ha->isp_ops->disable_intrs(ha);
3310 }
3311
3312 qla2x00_free_irqs(vha);
3313
3314 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3315
3316 pci_disable_pcie_error_reporting(pdev);
3317 pci_disable_device(pdev);
e30d1756
MI		 3318}
3319
fe1b806f 3320/* Deletes all the virtual ports for a given ha */
4c993f76 3321static void
fe1b806f 3322qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3323{
fe1b806f 3324 scsi_qla_host_t *vha;
feafb7b1 3325 unsigned long flags;
e315cd28 3326
43ebf16d
AE		 3327 mutex_lock(&ha->vport_lock);
3328 while (ha->cur_vport_count) {
43ebf16d 3329 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3330
43ebf16d
AE		 3331 BUG_ON(base_vha->list.next == &ha->vp_list);
3332 /* This assumes first entry in ha->vp_list is always base vha */
3333 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3334 scsi_host_get(vha->host);
feafb7b1 3335
43ebf16d
AE		 3336 spin_unlock_irqrestore(&ha->vport_slock, flags);
3337 mutex_unlock(&ha->vport_lock);
3338
3339 fc_vport_terminate(vha->fc_vport);
3340 scsi_host_put(vha->host);
feafb7b1 3341
43ebf16d 3342 mutex_lock(&ha->vport_lock);
e315cd28 3343 }
43ebf16d 3344 mutex_unlock(&ha->vport_lock);
fe1b806f 3345}
1da177e4 3346
fe1b806f
CD		 3347/* Stops all deferred work threads */
3348static void
3349qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3350{
7d613ac6
SV		 3351 /* Cancel all work and destroy DPC workqueues */
3352 if (ha->dpc_lp_wq) {
3353 cancel_work_sync(&ha->idc_aen);
3354 destroy_workqueue(ha->dpc_lp_wq);
3355 ha->dpc_lp_wq = NULL;
3356 }
3357
3358 if (ha->dpc_hp_wq) {
3359 cancel_work_sync(&ha->nic_core_reset);
3360 cancel_work_sync(&ha->idc_state_handler);
3361 cancel_work_sync(&ha->nic_core_unrecoverable);
3362 destroy_workqueue(ha->dpc_hp_wq);
3363 ha->dpc_hp_wq = NULL;
3364 }
3365
b9978769
AV		 3366 /* Kill the kernel thread for this host */
3367 if (ha->dpc_thread) {
3368 struct task_struct *t = ha->dpc_thread;
3369
3370 /*
3371 * qla2xxx_wake_dpc checks for ->dpc_thread
3372 * so we need to zero it out.
3373 */
3374 ha->dpc_thread = NULL;
3375 kthread_stop(t);
3376 }
fe1b806f 3377}
1da177e4 3378
fe1b806f
CD		 3379static void
3380qla2x00_unmap_iobases(struct qla_hw_data *ha)
3381{
a9083016 3382 if (IS_QLA82XX(ha)) {
b963752f 3383
f73cb695 3384 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3385 if (!ql2xdbwr)
f73cb695 3386 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3387 } else {
3388 if (ha->iobase)
3389 iounmap(ha->iobase);
1da177e4 3390
8ae6d9c7
GM		 3391 if (ha->cregbase)
3392 iounmap(ha->cregbase);
3393
a9083016
GM		 3394 if (ha->mqiobase)
3395 iounmap(ha->mqiobase);
6246b8a1 3396
f73cb695 3397 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3398 iounmap(ha->msixbase);
a9083016 3399 }
fe1b806f
CD		 3400}
3401
3402static void
db7157d4 3403qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3404{
fe1b806f
CD		 3405 if (IS_QLA8044(ha)) {
3406 qla8044_idc_lock(ha);
c41afc9a 3407 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3408 qla8044_idc_unlock(ha);
3409 } else if (IS_QLA82XX(ha)) {
3410 qla82xx_idc_lock(ha);
3411 qla82xx_clear_drv_active(ha);
3412 qla82xx_idc_unlock(ha);
3413 }
3414}
3415
3416static void
3417qla2x00_remove_one(struct pci_dev *pdev)
3418{
3419 scsi_qla_host_t *base_vha;
3420 struct qla_hw_data *ha;
3421
beb9e315
JL		 3422 base_vha = pci_get_drvdata(pdev);
3423 ha = base_vha->hw;
3424
3425 /* Indicate device removal to prevent future board_disable and wait
3426 * until any pending board_disable has completed. */
3427 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3428 cancel_work_sync(&ha->board_disable);
3429
fe1b806f 3430 /*
beb9e315
JL		 3431 * If the PCI device is disabled then there was a PCI-disconnect and
3432 * qla2x00_disable_board_on_pci_error has taken care of most of the
3433 * resources.
fe1b806f 3434 */
beb9e315 3435 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3436 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3437 base_vha->gnl.l, base_vha->gnl.ldma);
3438
beb9e315
JL		 3439 scsi_host_put(base_vha->host);
3440 kfree(ha);
3441 pci_set_drvdata(pdev, NULL);
fe1b806f 3442 return;
beb9e315 3443 }
638a1a01
SC		 3444 qla2x00_wait_for_hba_ready(base_vha);
3445
726b8548
QT		 3446 /*
3447 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3448 * where it was set first.
3449 */
3450 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3451 return;
3452
fe1b806f 3453 set_bit(UNLOADING, &base_vha->dpc_flags);
726b8548
QT		 3454 dma_free_coherent(&ha->pdev->dev,
3455 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3456
3457 if (IS_QLAFX00(ha))
3458 qlafx00_driver_shutdown(base_vha, 20);
3459
3460 qla2x00_delete_all_vps(ha, base_vha);
3461
3462 if (IS_QLA8031(ha)) {
3463 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3464 "Clearing fcoe driver presence.\n");
3465 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3466 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3467 "Error while clearing DRV-Presence.\n");
3468 }
3469
3470 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3471
3472 qla2x00_dfs_remove(base_vha);
3473
3474 qla84xx_put_chip(base_vha);
3475
2d5a4c34
HM		 3476 /* Laser should be disabled only for ISP2031 */
3477 if (IS_QLA2031(ha))
3478 qla83xx_disable_laser(base_vha);
3479
fe1b806f
CD		 3480 /* Disable timer */
3481 if (base_vha->timer_active)
3482 qla2x00_stop_timer(base_vha);
3483
3484 base_vha->flags.online = 0;
3485
b0d6cabd
HM		 3486 /* free DMA memory */
3487 if (ha->exlogin_buf)
3488 qla2x00_free_exlogin_buffer(ha);
3489
2f56a7f1
HM		 3490 /* free DMA memory */
3491 if (ha->exchoffld_buf)
3492 qla2x00_free_exchoffld_buffer(ha);
3493
fe1b806f
CD		 3494 qla2x00_destroy_deferred_work(ha);
3495
3496 qlt_remove_target(ha, base_vha);
3497
3498 qla2x00_free_sysfs_attr(base_vha, true);
3499
3500 fc_remove_host(base_vha->host);
482c9dc7 3501 qlt_remove_target_resources(ha);
fe1b806f
CD		 3502
3503 scsi_remove_host(base_vha->host);
3504
3505 qla2x00_free_device(base_vha);
3506
db7157d4 3507 qla2x00_clear_drv_active(ha);
fe1b806f 3508
d2749ffa
AE		 3509 scsi_host_put(base_vha->host);
3510
fe1b806f 3511 qla2x00_unmap_iobases(ha);
73208dfd 3512
e315cd28
AC		 3513 pci_release_selected_regions(ha->pdev, ha->bars);
3514 kfree(ha);
1da177e4 3515
90a86fc0
JC		 3516 pci_disable_pcie_error_reporting(pdev);
3517
665db93b 3518 pci_disable_device(pdev);
1da177e4 3519}
1da177e4
LT		 3520
3521static void
e315cd28 3522qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3523{
e315cd28 3524 struct qla_hw_data *ha = vha->hw;
1da177e4 3525
85880801
AV		 3526 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3527
3528 /* Disable timer */
3529 if (vha->timer_active)
3530 qla2x00_stop_timer(vha);
3531
2afa19a9 3532 qla25xx_delete_queues(vha);
fe1b806f 3533
df613b96 3534 if (ha->flags.fce_enabled)
e315cd28 3535 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3536
a7a167bf 3537 if (ha->eft)
e315cd28 3538 qla2x00_disable_eft_trace(vha);
a7a167bf 3539
f6ef3b18 3540 /* Stop currently executing firmware. */
e315cd28 3541 qla2x00_try_to_stop_firmware(vha);
1da177e4 3542
85880801
AV		 3543 vha->flags.online = 0;
3544
f6ef3b18 3545 /* turn-off interrupts on the card */
a9083016
GM		 3546 if (ha->interrupts_on) {
3547 vha->flags.init_done = 0;
fd34f556 3548 ha->isp_ops->disable_intrs(ha);
a9083016 3549 }
f6ef3b18 3550
093df737
QT		 3551 qla2x00_free_fcports(vha);
3552
e315cd28 3553 qla2x00_free_irqs(vha);
1da177e4 3554
093df737
QT		 3555 /* Flush the work queue and remove it */
3556 if (ha->wq) {
3557 flush_workqueue(ha->wq);
3558 destroy_workqueue(ha->wq);
3559 ha->wq = NULL;
3560 }
3561
8867048b 3562
e315cd28 3563 qla2x00_mem_free(ha);
73208dfd 3564
08de2844
GM		 3565 qla82xx_md_free(vha);
3566
73208dfd 3567 qla2x00_free_queues(ha);
1da177e4
LT		 3568}
3569
8867048b
CD		 3570void qla2x00_free_fcports(struct scsi_qla_host *vha)
3571{
3572 fc_port_t *fcport, *tfcport;
3573
3574 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3575 list_del(&fcport->list);
5f16b331 3576 qla2x00_clear_loop_id(fcport);
8867048b 3577 kfree(fcport);
8867048b
CD		 3578 }
3579}
3580
d97994dc 3581static inline void
e315cd28 3582qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3583 int defer)
3584{
d97994dc 3585 struct fc_rport *rport;
67becc00 3586 scsi_qla_host_t *base_vha;
044d78e1 3587 unsigned long flags;
d97994dc
AV		 3588
3589 if (!fcport->rport)
3590 return;
3591
3592 rport = fcport->rport;
3593 if (defer) {
67becc00 3594 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3595 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3596 fcport->drport = rport;
044d78e1 3597 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3598 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3599 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3600 qla2xxx_wake_dpc(base_vha);
2d70c103 3601 } else {
df673274 3602 int now;
726b8548
QT		 3603 if (rport) {
3604 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3605 "%s %8phN. rport %p roles %x \n",
3606 __func__, fcport->port_name, rport,
3607 rport->roles);
d20ed91b 3608 fc_remote_port_delete(rport);
726b8548 3609 }
df673274 3610 qlt_do_generation_tick(vha, &now);
2d70c103 3611 }
d97994dc
AV		 3612}
3613
1da177e4
LT		 3614/*
3615 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3616 *
3617 * Input: ha = adapter block pointer. fcport = port structure pointer.
3618 *
3619 * Return: None.
3620 *
3621 * Context:
3622 */
e315cd28 3623void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3624 int do_login, int defer)
1da177e4 3625{
8ae6d9c7
GM		 3626 if (IS_QLAFX00(vha->hw)) {
3627 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3628 qla2x00_schedule_rport_del(vha, fcport, defer);
3629 return;
3630 }
3631
2c3dfe3f 3632 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3633 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3634 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3635 qla2x00_schedule_rport_del(vha, fcport, defer);
3636 }
fa2a1ce5 3637 /*
1da177e4
LT		 3638 * We may need to retry the login, so don't change the state of the
3639 * port but do the retries.
3640 */
3641 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3642 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3643
3644 if (!do_login)
3645 return;
3646
a1d0285e
AE		 3647 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3648
1da177e4 3649 if (fcport->login_retry == 0) {
e315cd28 3650 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3651
7c3df132 3652 ql_dbg(ql_dbg_disc, vha, 0x2067,
726b8548 3653 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3654 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3655 }
3656}
3657
3658/*
3659 * qla2x00_mark_all_devices_lost
3660 * Updates fcport state when device goes offline.
3661 *
3662 * Input:
3663 * ha = adapter block pointer.
3664 * fcport = port structure pointer.
3665 *
3666 * Return:
3667 * None.
3668 *
3669 * Context:
3670 */
3671void
e315cd28 3672qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3673{
3674 fc_port_t *fcport;
3675
726b8548
QT		 3676 ql_dbg(ql_dbg_disc, vha, 0xffff,
3677 "Mark all dev lost\n");
3678
e315cd28 3679 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3680 fcport->scan_state = 0;
3681 qlt_schedule_sess_for_deletion_lock(fcport);
3682
c6d39e23 3683 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3684 continue;
0d6e61bc 3685
1da177e4
LT		 3686 /*
3687 * No point in marking the device as lost, if the device is
3688 * already DEAD.
3689 */
3690 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3691 continue;
e315cd28 3692 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3693 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3694 if (defer)
3695 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3696 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3697 qla2x00_schedule_rport_del(vha, fcport, defer);
3698 }
1da177e4
LT		 3699 }
3700}
3701
3702/*
3703* qla2x00_mem_alloc
3704* Allocates adapter memory.
3705*
3706* Returns:
3707* 0 = success.
e8711085 3708* !0 = failure.
1da177e4 3709*/
e8711085 3710static int
73208dfd
AC		 3711qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3712 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3713{
3714 char name[16];
1da177e4 3715
e8711085 3716 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3717 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3718 if (!ha->init_cb)
e315cd28 3719 goto fail;
e8711085 3720
2d70c103
NB		 3721 if (qlt_mem_alloc(ha) < 0)
3722 goto fail_free_init_cb;
3723
642ef983
CD		 3724 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3725 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3726 if (!ha->gid_list)
2d70c103 3727 goto fail_free_tgt_mem;
1da177e4 3728
e8711085
AV		 3729 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3730 if (!ha->srb_mempool)
e315cd28 3731 goto fail_free_gid_list;
e8711085 3732
7ec0effd 3733 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3734 /* Allocate cache for CT6 Ctx. */
3735 if (!ctx_cachep) {
3736 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3737 sizeof(struct ct6_dsd), 0,
3738 SLAB_HWCACHE_ALIGN, NULL);
3739 if (!ctx_cachep)
fc1ffd6c 3740 goto fail_free_srb_mempool;
a9083016
GM		 3741 }
3742 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3743 ctx_cachep);
3744 if (!ha->ctx_mempool)
3745 goto fail_free_srb_mempool;
7c3df132
SK		 3746 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3747 "ctx_cachep=%p ctx_mempool=%p.\n",
3748 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3749 }
3750
e8711085
AV		 3751 /* Get memory for cached NVRAM */
3752 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3753 if (!ha->nvram)
a9083016 3754 goto fail_free_ctx_mempool;
e8711085 3755
e315cd28
AC		 3756 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3757 ha->pdev->device);
3758 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3759 DMA_POOL_SIZE, 8, 0);
3760 if (!ha->s_dma_pool)
3761 goto fail_free_nvram;
3762
7c3df132
SK		 3763 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3764 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3765 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3766
7ec0effd 3767 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3768 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3769 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3770 if (!ha->dl_dma_pool) {
7c3df132
SK		 3771 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3772 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3773 goto fail_s_dma_pool;
3774 }
3775
3776 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3777 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3778 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3779 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3780 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3781 goto fail_dl_dma_pool;
3782 }
7c3df132
SK		 3783 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3784 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3785 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3786 }
3787
e8711085
AV		 3788 /* Allocate memory for SNS commands */
3789 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3790 /* Get consistent memory allocated for SNS commands */
e8711085 3791 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3792 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3793 if (!ha->sns_cmd)
e315cd28 3794 goto fail_dma_pool;
7c3df132 3795 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3796 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3797 } else {
e315cd28 3798 /* Get consistent memory allocated for MS IOCB */
e8711085 3799 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3800 &ha->ms_iocb_dma);
e8711085 3801 if (!ha->ms_iocb)
e315cd28
AC		 3802 goto fail_dma_pool;
3803 /* Get consistent memory allocated for CT SNS commands */
e8711085 3804 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3805 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3806 if (!ha->ct_sns)
3807 goto fail_free_ms_iocb;
7c3df132
SK		 3808 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3809 "ms_iocb=%p ct_sns=%p.\n",
3810 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3811 }
3812
e315cd28 3813 /* Allocate memory for request ring */
73208dfd
AC		 3814 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3815 if (!*req) {
7c3df132
SK		 3816 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3817 "Failed to allocate memory for req.\n");
e315cd28
AC		 3818 goto fail_req;
3819 }
73208dfd
AC		 3820 (*req)->length = req_len;
3821 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3822 ((*req)->length + 1) * sizeof(request_t),
3823 &(*req)->dma, GFP_KERNEL);
3824 if (!(*req)->ring) {
7c3df132
SK		 3825 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3826 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3827 goto fail_req_ring;
3828 }
3829 /* Allocate memory for response ring */
73208dfd
AC		 3830 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3831 if (!*rsp) {
7c3df132
SK		 3832 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3833 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3834 goto fail_rsp;
3835 }
73208dfd
AC		 3836 (*rsp)->hw = ha;
3837 (*rsp)->length = rsp_len;
3838 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3839 ((*rsp)->length + 1) * sizeof(response_t),
3840 &(*rsp)->dma, GFP_KERNEL);
3841 if (!(*rsp)->ring) {
7c3df132
SK		 3842 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3843 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3844 goto fail_rsp_ring;
3845 }
73208dfd
AC		 3846 (*req)->rsp = *rsp;
3847 (*rsp)->req = *req;
7c3df132
SK		 3848 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3849 "req=%p req->length=%d req->ring=%p rsp=%p "
3850 "rsp->length=%d rsp->ring=%p.\n",
3851 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3852 (*rsp)->ring);
73208dfd
AC		 3853 /* Allocate memory for NVRAM data for vports */
3854 if (ha->nvram_npiv_size) {
3855 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3856 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3857 if (!ha->npiv_info) {
7c3df132
SK		 3858 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3859 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3860 goto fail_npiv_info;
3861 }
3862 } else
3863 ha->npiv_info = NULL;
e8711085 3864
b64b0e8f 3865 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3866 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3867 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3868 &ha->ex_init_cb_dma);
3869 if (!ha->ex_init_cb)
3870 goto fail_ex_init_cb;
7c3df132
SK		 3871 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3872 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3873 }
3874
a9083016
GM		 3875 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3876
5ff1d584
AV		 3877 /* Get consistent memory allocated for Async Port-Database. */
3878 if (!IS_FWI2_CAPABLE(ha)) {
3879 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3880 &ha->async_pd_dma);
3881 if (!ha->async_pd)
3882 goto fail_async_pd;
7c3df132
SK		 3883 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3884 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3885 }
3886
e315cd28 3887 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3888
3889 /* Allocate memory for our loop_id bitmap */
3890 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3891 GFP_KERNEL);
3892 if (!ha->loop_id_map)
fc1ffd6c 3893 goto fail_loop_id_map;
5f16b331
CD		 3894 else {
3895 qla2x00_set_reserved_loop_ids(ha);
3896 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3897 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3898 }
3899
b2a72ec3 3900 return 0;
e315cd28 3901
fc1ffd6c
QT		 3902fail_loop_id_map:
3903 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3904fail_async_pd:
3905 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3906fail_ex_init_cb:
3907 kfree(ha->npiv_info);
73208dfd
AC		 3908fail_npiv_info:
3909 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3910 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3911 (*rsp)->ring = NULL;
3912 (*rsp)->dma = 0;
e315cd28 3913fail_rsp_ring:
73208dfd 3914 kfree(*rsp);
e315cd28 3915fail_rsp:
73208dfd
AC		 3916 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3917 sizeof(request_t), (*req)->ring, (*req)->dma);
3918 (*req)->ring = NULL;
3919 (*req)->dma = 0;
e315cd28 3920fail_req_ring:
73208dfd 3921 kfree(*req);
e315cd28
AC		 3922fail_req:
3923 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3924 ha->ct_sns, ha->ct_sns_dma);
3925 ha->ct_sns = NULL;
3926 ha->ct_sns_dma = 0;
e8711085
AV		 3927fail_free_ms_iocb:
3928 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3929 ha->ms_iocb = NULL;
3930 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3931
3932 if (ha->sns_cmd)
3933 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3934 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3935fail_dma_pool:
bad75002 3936 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3937 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3938 ha->fcp_cmnd_dma_pool = NULL;
3939 }
3940fail_dl_dma_pool:
bad75002 3941 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3942 dma_pool_destroy(ha->dl_dma_pool);
3943 ha->dl_dma_pool = NULL;
3944 }
3945fail_s_dma_pool:
e315cd28
AC		 3946 dma_pool_destroy(ha->s_dma_pool);
3947 ha->s_dma_pool = NULL;
e8711085
AV		 3948fail_free_nvram:
3949 kfree(ha->nvram);
3950 ha->nvram = NULL;
a9083016 3951fail_free_ctx_mempool:
fc1ffd6c
QT		 3952 if (ha->ctx_mempool)
3953 mempool_destroy(ha->ctx_mempool);
a9083016 3954 ha->ctx_mempool = NULL;
e8711085 3955fail_free_srb_mempool:
fc1ffd6c
QT		 3956 if (ha->srb_mempool)
3957 mempool_destroy(ha->srb_mempool);
e8711085 3958 ha->srb_mempool = NULL;
e8711085 3959fail_free_gid_list:
642ef983
CD		 3960 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3961 ha->gid_list,
e315cd28 3962 ha->gid_list_dma);
e8711085
AV		 3963 ha->gid_list = NULL;
3964 ha->gid_list_dma = 0;
2d70c103
NB		 3965fail_free_tgt_mem:
3966 qlt_mem_free(ha);
e315cd28
AC		 3967fail_free_init_cb:
3968 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3969 ha->init_cb_dma);
3970 ha->init_cb = NULL;
3971 ha->init_cb_dma = 0;
e8711085 3972fail:
7c3df132
SK		 3973 ql_log(ql_log_fatal, NULL, 0x0030,
3974 "Memory allocation failure.\n");
e8711085 3975 return -ENOMEM;
1da177e4
LT		 3976}
3977
b0d6cabd
HM		 3978int
3979qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3980{
3981 int rval;
3982 uint16_t size, max_cnt, temp;
3983 struct qla_hw_data *ha = vha->hw;
3984
3985 /* Return if we don't need to alloacate any extended logins */
3986 if (!ql2xexlogins)
3987 return QLA_SUCCESS;
3988
3989 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3990 max_cnt = 0;
3991 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3992 if (rval != QLA_SUCCESS) {
3993 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3994 "Failed to get exlogin status.\n");
3995 return rval;
3996 }
3997
3998 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3999 ha->exlogin_size = (size * temp);
4000 ql_log(ql_log_info, vha, 0xd024,
4001 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4002 max_cnt, size, temp);
4003
4004 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
4005 ha->exlogin_size);
4006
4007 /* Get consistent memory for extended logins */
4008 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4009 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4010 if (!ha->exlogin_buf) {
4011 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4012 "Failed to allocate memory for exlogin_buf_dma.\n");
4013 return -ENOMEM;
4014 }
4015
4016 /* Now configure the dma buffer */
4017 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4018 if (rval) {
4019 ql_log(ql_log_fatal, vha, 0x00cf,
4020 "Setup extended login buffer ****FAILED****.\n");
4021 qla2x00_free_exlogin_buffer(ha);
4022 }
4023
4024 return rval;
4025}
4026
4027/*
4028* qla2x00_free_exlogin_buffer
4029*
4030* Input:
4031* ha = adapter block pointer
4032*/
4033void
4034qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4035{
4036 if (ha->exlogin_buf) {
4037 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4038 ha->exlogin_buf, ha->exlogin_buf_dma);
4039 ha->exlogin_buf = NULL;
4040 ha->exlogin_size = 0;
4041 }
4042}
4043
2f56a7f1
HM		 4044int
4045qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4046{
4047 int rval;
4048 uint16_t size, max_cnt, temp;
4049 struct qla_hw_data *ha = vha->hw;
4050
4051 /* Return if we don't need to alloacate any extended logins */
4052 if (!ql2xexchoffld)
4053 return QLA_SUCCESS;
4054
4055 ql_log(ql_log_info, vha, 0xd014,
4056 "Exchange offload count: %d.\n", ql2xexlogins);
4057
4058 max_cnt = 0;
4059 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4060 if (rval != QLA_SUCCESS) {
4061 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4062 "Failed to get exlogin status.\n");
4063 return rval;
4064 }
4065
4066 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
4067 ha->exchoffld_size = (size * temp);
4068 ql_log(ql_log_info, vha, 0xd016,
4069 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4070 max_cnt, size, temp);
4071
4072 ql_log(ql_log_info, vha, 0xd017,
4073 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
4074
4075 /* Get consistent memory for extended logins */
4076 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4077 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4078 if (!ha->exchoffld_buf) {
4079 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4080 "Failed to allocate memory for exchoffld_buf_dma.\n");
4081 return -ENOMEM;
4082 }
4083
4084 /* Now configure the dma buffer */
4085 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4086 if (rval) {
4087 ql_log(ql_log_fatal, vha, 0xd02e,
4088 "Setup exchange offload buffer ****FAILED****.\n");
4089 qla2x00_free_exchoffld_buffer(ha);
4090 }
4091
4092 return rval;
4093}
4094
4095/*
4096* qla2x00_free_exchoffld_buffer
4097*
4098* Input:
4099* ha = adapter block pointer
4100*/
4101void
4102qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4103{
4104 if (ha->exchoffld_buf) {
4105 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4106 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4107 ha->exchoffld_buf = NULL;
4108 ha->exchoffld_size = 0;
4109 }
4110}
4111
1da177e4 4112/*
e30d1756
MI		 4113* qla2x00_free_fw_dump
4114* Frees fw dump stuff.
1da177e4
LT		 4115*
4116* Input:
7ec0effd 4117* ha = adapter block pointer
1da177e4 4118*/
a824ebb3 4119static void
e30d1756 4120qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4121{
df613b96 4122 if (ha->fce)
f73cb695
CD		 4123 dma_free_coherent(&ha->pdev->dev,
4124 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4125
f73cb695
CD		 4126 if (ha->eft)
4127 dma_free_coherent(&ha->pdev->dev,
4128 EFT_SIZE, ha->eft, ha->eft_dma);
4129
4130 if (ha->fw_dump)
a7a167bf 4131 vfree(ha->fw_dump);
f73cb695
CD		 4132 if (ha->fw_dump_template)
4133 vfree(ha->fw_dump_template);
4134
e30d1756
MI		 4135 ha->fce = NULL;
4136 ha->fce_dma = 0;
4137 ha->eft = NULL;
4138 ha->eft_dma = 0;
e30d1756 4139 ha->fw_dumped = 0;
61f098dd 4140 ha->fw_dump_cap_flags = 0;
e30d1756 4141 ha->fw_dump_reading = 0;
f73cb695
CD		 4142 ha->fw_dump = NULL;
4143 ha->fw_dump_len = 0;
4144 ha->fw_dump_template = NULL;
4145 ha->fw_dump_template_len = 0;
e30d1756
MI		 4146}
4147
4148/*
4149* qla2x00_mem_free
4150* Frees all adapter allocated memory.
4151*
4152* Input:
4153* ha = adapter block pointer.
4154*/
4155static void
4156qla2x00_mem_free(struct qla_hw_data *ha)
4157{
4158 qla2x00_free_fw_dump(ha);
4159
81178772
SK		 4160 if (ha->mctp_dump)
4161 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4162 ha->mctp_dump_dma);
4163
e30d1756
MI		 4164 if (ha->srb_mempool)
4165 mempool_destroy(ha->srb_mempool);
a7a167bf 4166
11bbc1d8
AV		 4167 if (ha->dcbx_tlv)
4168 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4169 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4170
ce0423f4
AV		 4171 if (ha->xgmac_data)
4172 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4173 ha->xgmac_data, ha->xgmac_data_dma);
4174
1da177e4
LT		 4175 if (ha->sns_cmd)
4176 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4177 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4178
4179 if (ha->ct_sns)
4180 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4181 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4182
88729e53
AV		 4183 if (ha->sfp_data)
4184 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4185
1da177e4
LT		 4186 if (ha->ms_iocb)
4187 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4188
b64b0e8f 4189 if (ha->ex_init_cb)
a9083016
GM		 4190 dma_pool_free(ha->s_dma_pool,
4191 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4192
5ff1d584
AV		 4193 if (ha->async_pd)
4194 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4195
1da177e4
LT		 4196 if (ha->s_dma_pool)
4197 dma_pool_destroy(ha->s_dma_pool);
4198
1da177e4 4199 if (ha->gid_list)
642ef983
CD		 4200 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4201 ha->gid_list, ha->gid_list_dma);
1da177e4 4202
a9083016
GM		 4203 if (IS_QLA82XX(ha)) {
4204 if (!list_empty(&ha->gbl_dsd_list)) {
4205 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4206
4207 /* clean up allocated prev pool */
4208 list_for_each_entry_safe(dsd_ptr,
4209 tdsd_ptr, &ha->gbl_dsd_list, list) {
4210 dma_pool_free(ha->dl_dma_pool,
4211 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4212 list_del(&dsd_ptr->list);
4213 kfree(dsd_ptr);
4214 }
4215 }
4216 }
4217
4218 if (ha->dl_dma_pool)
4219 dma_pool_destroy(ha->dl_dma_pool);
4220
4221 if (ha->fcp_cmnd_dma_pool)
4222 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4223
4224 if (ha->ctx_mempool)
4225 mempool_destroy(ha->ctx_mempool);
4226
2d70c103
NB		 4227 qlt_mem_free(ha);
4228
e315cd28
AC		 4229 if (ha->init_cb)
4230 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4231 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4232 vfree(ha->optrom_buffer);
4233 kfree(ha->nvram);
73208dfd 4234 kfree(ha->npiv_info);
7a67735b 4235 kfree(ha->swl);
5f16b331 4236 kfree(ha->loop_id_map);
1da177e4 4237
e8711085 4238 ha->srb_mempool = NULL;
a9083016 4239 ha->ctx_mempool = NULL;
1da177e4
LT		 4240 ha->sns_cmd = NULL;
4241 ha->sns_cmd_dma = 0;
4242 ha->ct_sns = NULL;
4243 ha->ct_sns_dma = 0;
4244 ha->ms_iocb = NULL;
4245 ha->ms_iocb_dma = 0;
1da177e4
LT		 4246 ha->init_cb = NULL;
4247 ha->init_cb_dma = 0;
b64b0e8f
AV		 4248 ha->ex_init_cb = NULL;
4249 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4250 ha->async_pd = NULL;
4251 ha->async_pd_dma = 0;
1da177e4
LT		 4252
4253 ha->s_dma_pool = NULL;
a9083016
GM		 4254 ha->dl_dma_pool = NULL;
4255 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4256
1da177e4
LT		 4257 ha->gid_list = NULL;
4258 ha->gid_list_dma = 0;
2d70c103
NB		 4259
4260 ha->tgt.atio_ring = NULL;
4261 ha->tgt.atio_dma = 0;
4262 ha->tgt.tgt_vp_map = NULL;
e315cd28 4263}
1da177e4 4264
e315cd28
AC		 4265struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4266 struct qla_hw_data *ha)
4267{
4268 struct Scsi_Host *host;
4269 struct scsi_qla_host *vha = NULL;
854165f4 4270
e315cd28 4271 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4272 if (!host) {
7c3df132
SK		 4273 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4274 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4275 return NULL;
e315cd28
AC		 4276 }
4277
4278 /* Clear our data area */
4279 vha = shost_priv(host);
4280 memset(vha, 0, sizeof(scsi_qla_host_t));
4281
4282 vha->host = host;
4283 vha->host_no = host->host_no;
4284 vha->hw = ha;
4285
4286 INIT_LIST_HEAD(&vha->vp_fcports);
4287 INIT_LIST_HEAD(&vha->work_list);
4288 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4289 INIT_LIST_HEAD(&vha->qla_cmd_list);
4290 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4291 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4292 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4293 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4294 INIT_LIST_HEAD(&vha->gnl.fcports);
e315cd28 4295
f999f4c1 4296 spin_lock_init(&vha->work_lock);
8b2f5ff3 4297 spin_lock_init(&vha->cmd_list_lock);
726b8548 4298 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4299 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4300
2fdbc65e
BVA		 4301 vha->gnl.size = sizeof(struct get_name_list_extended) *
4302 (ha->max_loop_id + 1);
41dc529a
QT		 4303 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4304 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4305 if (!vha->gnl.l) {
4306 ql_log(ql_log_fatal, vha, 0xffff,
4307 "Alloc failed for name list.\n");
4308 scsi_remove_host(vha->host);
4309 return NULL;
4310 }
f999f4c1 4311
e315cd28 4312 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4313 ql_dbg(ql_dbg_init, vha, 0x0041,
4314 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4315 vha->host, vha->hw, vha,
4316 dev_name(&(ha->pdev->dev)));
4317
e315cd28 4318 return vha;
1da177e4
LT		 4319}
4320
726b8548 4321struct qla_work_evt *
f999f4c1 4322qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4323{
4324 struct qla_work_evt *e;
feafb7b1
AE		 4325 uint8_t bail;
4326
4327 QLA_VHA_MARK_BUSY(vha, bail);
4328 if (bail)
4329 return NULL;
0971de7f 4330
f999f4c1 4331 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4332 if (!e) {
4333 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4334 return NULL;
feafb7b1 4335 }
0971de7f
AV		 4336
4337 INIT_LIST_HEAD(&e->list);
4338 e->type = type;
4339 e->flags = QLA_EVT_FLAG_FREE;
4340 return e;
4341}
4342
726b8548 4343int
f999f4c1 4344qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4345{
f999f4c1 4346 unsigned long flags;
0971de7f 4347
f999f4c1 4348 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4349 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4350 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4351
4352 if (QLA_EARLY_LINKUP(vha->hw))
4353 schedule_work(&vha->iocb_work);
4354 else
4355 qla2xxx_wake_dpc(vha);
f999f4c1 4356
0971de7f
AV		 4357 return QLA_SUCCESS;
4358}
4359
4360int
e315cd28 4361qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4362 u32 data)
4363{
4364 struct qla_work_evt *e;
4365
f999f4c1 4366 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4367 if (!e)
4368 return QLA_FUNCTION_FAILED;
4369
4370 e->u.aen.code = code;
4371 e->u.aen.data = data;
f999f4c1 4372 return qla2x00_post_work(vha, e);
0971de7f
AV		 4373}
4374
8a659571
AV		 4375int
4376qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4377{
4378 struct qla_work_evt *e;
4379
f999f4c1 4380 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4381 if (!e)
4382 return QLA_FUNCTION_FAILED;
4383
4384 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4385 return qla2x00_post_work(vha, e);
8a659571
AV		 4386}
4387
ac280b67
AV		 4388#define qla2x00_post_async_work(name, type) \
4389int qla2x00_post_async_##name##_work( \
4390 struct scsi_qla_host *vha, \
4391 fc_port_t *fcport, uint16_t *data) \
4392{ \
4393 struct qla_work_evt *e; \
4394 \
4395 e = qla2x00_alloc_work(vha, type); \
4396 if (!e) \
4397 return QLA_FUNCTION_FAILED; \
4398 \
4399 e->u.logio.fcport = fcport; \
4400 if (data) { \
4401 e->u.logio.data[0] = data[0]; \
4402 e->u.logio.data[1] = data[1]; \
4403 } \
4404 return qla2x00_post_work(vha, e); \
4405}
4406
4407qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4408qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4409qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4410qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4411qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4412
3420d36c
AV		 4413int
4414qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4415{
4416 struct qla_work_evt *e;
4417
4418 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4419 if (!e)
4420 return QLA_FUNCTION_FAILED;
4421
4422 e->u.uevent.code = code;
4423 return qla2x00_post_work(vha, e);
4424}
4425
4426static void
4427qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4428{
4429 char event_string[40];
4430 char *envp[] = { event_string, NULL };
4431
4432 switch (code) {
4433 case QLA_UEVENT_CODE_FW_DUMP:
4434 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4435 vha->host_no);
4436 break;
4437 default:
4438 /* do nothing */
4439 break;
4440 }
4441 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4442}
4443
8ae6d9c7
GM		 4444int
4445qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4446 uint32_t *data, int cnt)
4447{
4448 struct qla_work_evt *e;
4449
4450 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4451 if (!e)
4452 return QLA_FUNCTION_FAILED;
4453
4454 e->u.aenfx.evtcode = evtcode;
4455 e->u.aenfx.count = cnt;
4456 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4457 return qla2x00_post_work(vha, e);
4458}
4459
726b8548
QT		 4460int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4461{
4462 struct qla_work_evt *e;
4463
4464 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4465 if (!e)
4466 return QLA_FUNCTION_FAILED;
4467
4468 e->u.fcport.fcport = fcport;
4469 return qla2x00_post_work(vha, e);
4470}
4471
4472static
4473void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4474{
4475 unsigned long flags;
4476 fc_port_t *fcport = NULL;
4477 struct qlt_plogi_ack_t *pla =
4478 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4479
4480 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4481 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4482 if (fcport) {
4483 fcport->d_id = e->u.new_sess.id;
4484 if (pla) {
4485 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4486 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4487 /* we took an extra ref_count to prevent PLOGI ACK when
4488 * fcport/sess has not been created.
4489 */
4490 pla->ref_count--;
4491 }
4492 } else {
4493 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4494 if (fcport) {
4495 fcport->d_id = e->u.new_sess.id;
4496 fcport->scan_state = QLA_FCPORT_FOUND;
4497 fcport->flags |= FCF_FABRIC_DEVICE;
4498 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4499
4500 memcpy(fcport->port_name, e->u.new_sess.port_name,
4501 WWN_SIZE);
4502 list_add_tail(&fcport->list, &vha->vp_fcports);
4503
4504 if (pla) {
4505 qlt_plogi_ack_link(vha, pla, fcport,
4506 QLT_PLOGI_LINK_SAME_WWN);
4507 pla->ref_count--;
4508 }
4509 }
4510 }
4511 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4512
4513 if (fcport) {
4514 if (pla)
4515 qlt_plogi_ack_unref(vha, pla);
4516 else
4517 qla24xx_async_gnl(vha, fcport);
4518 }
4519}
4520
ac280b67 4521void
e315cd28 4522qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4523{
f999f4c1
AV		 4524 struct qla_work_evt *e, *tmp;
4525 unsigned long flags;
4526 LIST_HEAD(work);
0971de7f 4527
f999f4c1
AV		 4528 spin_lock_irqsave(&vha->work_lock, flags);
4529 list_splice_init(&vha->work_list, &work);
4530 spin_unlock_irqrestore(&vha->work_lock, flags);
4531
4532 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4533 list_del_init(&e->list);
0971de7f
AV		 4534
4535 switch (e->type) {
4536 case QLA_EVT_AEN:
e315cd28 4537 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4538 e->u.aen.code, e->u.aen.data);
4539 break;
8a659571
AV		 4540 case QLA_EVT_IDC_ACK:
4541 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4542 break;
ac280b67
AV		 4543 case QLA_EVT_ASYNC_LOGIN:
4544 qla2x00_async_login(vha, e->u.logio.fcport,
4545 e->u.logio.data);
4546 break;
ac280b67
AV		 4547 case QLA_EVT_ASYNC_LOGOUT:
4548 qla2x00_async_logout(vha, e->u.logio.fcport);
4549 break;
4550 case QLA_EVT_ASYNC_LOGOUT_DONE:
4551 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4552 e->u.logio.data);
4553 break;
5ff1d584
AV		 4554 case QLA_EVT_ASYNC_ADISC:
4555 qla2x00_async_adisc(vha, e->u.logio.fcport,
4556 e->u.logio.data);
4557 break;
4558 case QLA_EVT_ASYNC_ADISC_DONE:
4559 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4560 e->u.logio.data);
4561 break;
3420d36c
AV		 4562 case QLA_EVT_UEVENT:
4563 qla2x00_uevent_emit(vha, e->u.uevent.code);
4564 break;
8ae6d9c7
GM		 4565 case QLA_EVT_AENFX:
4566 qlafx00_process_aen(vha, e);
4567 break;
726b8548
QT		 4568 case QLA_EVT_GIDPN:
4569 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4570 break;
4571 case QLA_EVT_GPNID:
4572 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4573 break;
4574 case QLA_EVT_GPNID_DONE:
4575 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4576 break;
4577 case QLA_EVT_NEW_SESS:
4578 qla24xx_create_new_sess(vha, e);
4579 break;
4580 case QLA_EVT_GPDB:
4581 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4582 e->u.fcport.opt);
4583 break;
4584 case QLA_EVT_GPSC:
4585 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4586 break;
4587 case QLA_EVT_UPD_FCPORT:
4588 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4589 break;
4590 case QLA_EVT_GNL:
4591 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4592 break;
4593 case QLA_EVT_NACK:
4594 qla24xx_do_nack_work(vha, e);
4595 break;
0971de7f
AV		 4596 }
4597 if (e->flags & QLA_EVT_FLAG_FREE)
4598 kfree(e);
feafb7b1
AE		 4599
4600 /* For each work completed decrement vha ref count */
4601 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4602 }
e315cd28 4603}
f999f4c1 4604
e315cd28
AC		 4605/* Relogins all the fcports of a vport
4606 * Context: dpc thread
4607 */
4608void qla2x00_relogin(struct scsi_qla_host *vha)
4609{
4610 fc_port_t *fcport;
c6b2fca8 4611 int status;
726b8548 4612 struct event_arg ea;
e315cd28
AC		 4613
4614 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4615 /*
4616 * If the port is not ONLINE then try to login
4617 * to it if we haven't run out of retries.
4618 */
5ff1d584
AV		 4619 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4620 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4621 fcport->login_retry--;
e315cd28 4622 if (fcport->flags & FCF_FABRIC_DEVICE) {
726b8548
QT		 4623 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
4624 "%s %8phC DS %d LS %d\n", __func__,
4625 fcport->port_name, fcport->disc_state,
4626 fcport->fw_login_state);
4627 memset(&ea, 0, sizeof(ea));
4628 ea.event = FCME_RELOGIN;
4629 ea.fcport = fcport;
4630 qla2x00_fcport_event_handler(vha, &ea);
4631 } else {
e315cd28
AC		 4632 status = qla2x00_local_device_login(vha,
4633 fcport);
726b8548
QT		 4634 if (status == QLA_SUCCESS) {
4635 fcport->old_loop_id = fcport->loop_id;
4636 ql_dbg(ql_dbg_disc, vha, 0x2003,
4637 "Port login OK: logged in ID 0x%x.\n",
4638 fcport->loop_id);
4639 qla2x00_update_fcport(vha, fcport);
4640 } else if (status == 1) {
4641 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4642 /* retry the login again */
4643 ql_dbg(ql_dbg_disc, vha, 0x2007,
4644 "Retrying %d login again loop_id 0x%x.\n",
4645 fcport->login_retry,
4646 fcport->loop_id);
4647 } else {
4648 fcport->login_retry = 0;
4649 }
e315cd28 4650
726b8548
QT		 4651 if (fcport->login_retry == 0 &&
4652 status != QLA_SUCCESS)
4653 qla2x00_clear_loop_id(fcport);
e315cd28 4654 }
e315cd28
AC		 4655 }
4656 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4657 break;
0971de7f 4658 }
0971de7f
AV		 4659}
4660
7d613ac6
SV		 4661/* Schedule work on any of the dpc-workqueues */
4662void
4663qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4664{
4665 struct qla_hw_data *ha = base_vha->hw;
4666
4667 switch (work_code) {
4668 case MBA_IDC_AEN: /* 0x8200 */
4669 if (ha->dpc_lp_wq)
4670 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4671 break;
4672
4673 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4674 if (!ha->flags.nic_core_reset_hdlr_active) {
4675 if (ha->dpc_hp_wq)
4676 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4677 } else
4678 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4679 "NIC Core reset is already active. Skip "
4680 "scheduling it again.\n");
4681 break;
4682 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4683 if (ha->dpc_hp_wq)
4684 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4685 break;
4686 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4687 if (ha->dpc_hp_wq)
4688 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4689 break;
4690 default:
4691 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4692 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4693 }
4694
4695 return;
4696}
4697
4698/* Work: Perform NIC Core Unrecoverable state handling */
4699void
4700qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4701{
4702 struct qla_hw_data *ha =
2ad1b67c 4703 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4704 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4705 uint32_t dev_state = 0;
4706
4707 qla83xx_idc_lock(base_vha, 0);
4708 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4709 qla83xx_reset_ownership(base_vha);
4710 if (ha->flags.nic_core_reset_owner) {
4711 ha->flags.nic_core_reset_owner = 0;
4712 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4713 QLA8XXX_DEV_FAILED);
4714 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4715 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4716 }
4717 qla83xx_idc_unlock(base_vha, 0);
4718}
4719
4720/* Work: Execute IDC state handler */
4721void
4722qla83xx_idc_state_handler_work(struct work_struct *work)
4723{
4724 struct qla_hw_data *ha =
2ad1b67c 4725 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4726 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4727 uint32_t dev_state = 0;
4728
4729 qla83xx_idc_lock(base_vha, 0);
4730 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4731 if (dev_state == QLA8XXX_DEV_FAILED ||
4732 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4733 qla83xx_idc_state_handler(base_vha);
4734 qla83xx_idc_unlock(base_vha, 0);
4735}
4736
fa492630 4737static int
7d613ac6
SV		 4738qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4739{
4740 int rval = QLA_SUCCESS;
4741 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4742 uint32_t heart_beat_counter1, heart_beat_counter2;
4743
4744 do {
4745 if (time_after(jiffies, heart_beat_wait)) {
4746 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4747 "Nic Core f/w is not alive.\n");
4748 rval = QLA_FUNCTION_FAILED;
4749 break;
4750 }
4751
4752 qla83xx_idc_lock(base_vha, 0);
4753 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4754 &heart_beat_counter1);
4755 qla83xx_idc_unlock(base_vha, 0);
4756 msleep(100);
4757 qla83xx_idc_lock(base_vha, 0);
4758 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4759 &heart_beat_counter2);
4760 qla83xx_idc_unlock(base_vha, 0);
4761 } while (heart_beat_counter1 == heart_beat_counter2);
4762
4763 return rval;
4764}
4765
4766/* Work: Perform NIC Core Reset handling */
4767void
4768qla83xx_nic_core_reset_work(struct work_struct *work)
4769{
4770 struct qla_hw_data *ha =
4771 container_of(work, struct qla_hw_data, nic_core_reset);
4772 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4773 uint32_t dev_state = 0;
4774
81178772
SK		 4775 if (IS_QLA2031(ha)) {
4776 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4777 ql_log(ql_log_warn, base_vha, 0xb081,
4778 "Failed to dump mctp\n");
4779 return;
4780 }
4781
7d613ac6
SV		 4782 if (!ha->flags.nic_core_reset_hdlr_active) {
4783 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4784 qla83xx_idc_lock(base_vha, 0);
4785 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4786 &dev_state);
4787 qla83xx_idc_unlock(base_vha, 0);
4788 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4789 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4790 "Nic Core f/w is alive.\n");
4791 return;
4792 }
4793 }
4794
4795 ha->flags.nic_core_reset_hdlr_active = 1;
4796 if (qla83xx_nic_core_reset(base_vha)) {
4797 /* NIC Core reset failed. */
4798 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4799 "NIC Core reset failed.\n");
4800 }
4801 ha->flags.nic_core_reset_hdlr_active = 0;
4802 }
4803}
4804
4805/* Work: Handle 8200 IDC aens */
4806void
4807qla83xx_service_idc_aen(struct work_struct *work)
4808{
4809 struct qla_hw_data *ha =
4810 container_of(work, struct qla_hw_data, idc_aen);
4811 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4812 uint32_t dev_state, idc_control;
4813
4814 qla83xx_idc_lock(base_vha, 0);
4815 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4816 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4817 qla83xx_idc_unlock(base_vha, 0);
4818 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4819 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4820 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4821 "Application requested NIC Core Reset.\n");
4822 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4823 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4824 QLA_SUCCESS) {
4825 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4826 "Other protocol driver requested NIC Core Reset.\n");
4827 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4828 }
4829 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4830 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4831 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4832 }
4833}
4834
4835static void
4836qla83xx_wait_logic(void)
4837{
4838 int i;
4839
4840 /* Yield CPU */
4841 if (!in_interrupt()) {
4842 /*
4843 * Wait about 200ms before retrying again.
4844 * This controls the number of retries for single
4845 * lock operation.
4846 */
4847 msleep(100);
4848 schedule();
4849 } else {
4850 for (i = 0; i < 20; i++)
4851 cpu_relax(); /* This a nop instr on i386 */
4852 }
4853}
4854
fa492630 4855static int
7d613ac6
SV		 4856qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4857{
4858 int rval;
4859 uint32_t data;
4860 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4861 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4862 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4863 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4864 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4865
4866 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4867 if (rval)
4868 return rval;
4869
4870 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4871 return QLA_SUCCESS;
4872 } else {
4873 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4874 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4875 data);
4876 if (rval)
4877 return rval;
4878
4879 msleep(200);
4880
4881 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4882 &data);
4883 if (rval)
4884 return rval;
4885
4886 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4887 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4888 ~(idc_lck_rcvry_stage_mask));
4889 rval = qla83xx_wr_reg(base_vha,
4890 QLA83XX_IDC_LOCK_RECOVERY, data);
4891 if (rval)
4892 return rval;
4893
4894 /* Forcefully perform IDC UnLock */
4895 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4896 &data);
4897 if (rval)
4898 return rval;
4899 /* Clear lock-id by setting 0xff */
4900 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4901 0xff);
4902 if (rval)
4903 return rval;
4904 /* Clear lock-recovery by setting 0x0 */
4905 rval = qla83xx_wr_reg(base_vha,
4906 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4907 if (rval)
4908 return rval;
4909 } else
4910 return QLA_SUCCESS;
4911 }
4912
4913 return rval;
4914}
4915
fa492630 4916static int
7d613ac6
SV		 4917qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4918{
4919 int rval = QLA_SUCCESS;
4920 uint32_t o_drv_lockid, n_drv_lockid;
4921 unsigned long lock_recovery_timeout;
4922
4923 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4924retry_lockid:
4925 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4926 if (rval)
4927 goto exit;
4928
4929 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4930 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4931 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4932 return QLA_SUCCESS;
4933 else
4934 return QLA_FUNCTION_FAILED;
4935 }
4936
4937 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4938 if (rval)
4939 goto exit;
4940
4941 if (o_drv_lockid == n_drv_lockid) {
4942 qla83xx_wait_logic();
4943 goto retry_lockid;
4944 } else
4945 return QLA_SUCCESS;
4946
4947exit:
4948 return rval;
4949}
4950
4951void
4952qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4953{
4954 uint16_t options = (requester_id << 15) | BIT_6;
4955 uint32_t data;
6c315553 4956 uint32_t lock_owner;
7d613ac6
SV		 4957 struct qla_hw_data *ha = base_vha->hw;
4958
4959 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4960retry_lock:
4961 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4962 == QLA_SUCCESS) {
4963 if (data) {
4964 /* Setting lock-id to our function-number */
4965 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4966 ha->portnum);
4967 } else {
6c315553
SK		 4968 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4969 &lock_owner);
7d613ac6 4970 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4971 "Failed to acquire IDC lock, acquired by %d, "
4972 "retrying...\n", lock_owner);
7d613ac6
SV		 4973
4974 /* Retry/Perform IDC-Lock recovery */
4975 if (qla83xx_idc_lock_recovery(base_vha)
4976 == QLA_SUCCESS) {
4977 qla83xx_wait_logic();
4978 goto retry_lock;
4979 } else
4980 ql_log(ql_log_warn, base_vha, 0xb075,
4981 "IDC Lock recovery FAILED.\n");
4982 }
4983
4984 }
4985
4986 return;
4987
4988 /* XXX: IDC-lock implementation using access-control mbx */
4989retry_lock2:
4990 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4991 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4992 "Failed to acquire IDC lock. retrying...\n");
4993 /* Retry/Perform IDC-Lock recovery */
4994 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4995 qla83xx_wait_logic();
4996 goto retry_lock2;
4997 } else
4998 ql_log(ql_log_warn, base_vha, 0xb076,
4999 "IDC Lock recovery FAILED.\n");
5000 }
5001
5002 return;
5003}
5004
5005void
5006qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5007{
5897cb2f
BVA		 5008#if 0
5009 uint16_t options = (requester_id << 15) | BIT_7;
5010#endif
5011 uint16_t retry;
7d613ac6
SV		 5012 uint32_t data;
5013 struct qla_hw_data *ha = base_vha->hw;
5014
5015 /* IDC-unlock implementation using driver-unlock/lock-id
5016 * remote registers
5017 */
5018 retry = 0;
5019retry_unlock:
5020 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5021 == QLA_SUCCESS) {
5022 if (data == ha->portnum) {
5023 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5024 /* Clearing lock-id by setting 0xff */
5025 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5026 } else if (retry < 10) {
5027 /* SV: XXX: IDC unlock retrying needed here? */
5028
5029 /* Retry for IDC-unlock */
5030 qla83xx_wait_logic();
5031 retry++;
5032 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5033 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5034 goto retry_unlock;
5035 }
5036 } else if (retry < 10) {
5037 /* Retry for IDC-unlock */
5038 qla83xx_wait_logic();
5039 retry++;
5040 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5041 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5042 goto retry_unlock;
5043 }
5044
5045 return;
5046
5897cb2f 5047#if 0
7d613ac6
SV		 5048 /* XXX: IDC-unlock implementation using access-control mbx */
5049 retry = 0;
5050retry_unlock2:
5051 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5052 if (retry < 10) {
5053 /* Retry for IDC-unlock */
5054 qla83xx_wait_logic();
5055 retry++;
5056 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5057 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5058 goto retry_unlock2;
5059 }
5060 }
5061
5062 return;
5897cb2f 5063#endif
7d613ac6
SV		 5064}
5065
5066int
5067__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5068{
5069 int rval = QLA_SUCCESS;
5070 struct qla_hw_data *ha = vha->hw;
5071 uint32_t drv_presence;
5072
5073 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5074 if (rval == QLA_SUCCESS) {
5075 drv_presence |= (1 << ha->portnum);
5076 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5077 drv_presence);
5078 }
5079
5080 return rval;
5081}
5082
5083int
5084qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5085{
5086 int rval = QLA_SUCCESS;
5087
5088 qla83xx_idc_lock(vha, 0);
5089 rval = __qla83xx_set_drv_presence(vha);
5090 qla83xx_idc_unlock(vha, 0);
5091
5092 return rval;
5093}
5094
5095int
5096__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5097{
5098 int rval = QLA_SUCCESS;
5099 struct qla_hw_data *ha = vha->hw;
5100 uint32_t drv_presence;
5101
5102 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5103 if (rval == QLA_SUCCESS) {
5104 drv_presence &= ~(1 << ha->portnum);
5105 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5106 drv_presence);
5107 }
5108
5109 return rval;
5110}
5111
5112int
5113qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5114{
5115 int rval = QLA_SUCCESS;
5116
5117 qla83xx_idc_lock(vha, 0);
5118 rval = __qla83xx_clear_drv_presence(vha);
5119 qla83xx_idc_unlock(vha, 0);
5120
5121 return rval;
5122}
5123
fa492630 5124static void
7d613ac6
SV		 5125qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5126{
5127 struct qla_hw_data *ha = vha->hw;
5128 uint32_t drv_ack, drv_presence;
5129 unsigned long ack_timeout;
5130
5131 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5132 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5133 while (1) {
5134 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5135 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5136 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5137 break;
5138
5139 if (time_after_eq(jiffies, ack_timeout)) {
5140 ql_log(ql_log_warn, vha, 0xb067,
5141 "RESET ACK TIMEOUT! drv_presence=0x%x "
5142 "drv_ack=0x%x\n", drv_presence, drv_ack);
5143 /*
5144 * The function(s) which did not ack in time are forced
5145 * to withdraw any further participation in the IDC
5146 * reset.
5147 */
5148 if (drv_ack != drv_presence)
5149 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5150 drv_ack);
5151 break;
5152 }
5153
5154 qla83xx_idc_unlock(vha, 0);
5155 msleep(1000);
5156 qla83xx_idc_lock(vha, 0);
5157 }
5158
5159 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5160 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5161}
5162
fa492630 5163static int
7d613ac6
SV		 5164qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5165{
5166 int rval = QLA_SUCCESS;
5167 uint32_t idc_control;
5168
5169 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5170 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5171
5172 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5173 __qla83xx_get_idc_control(vha, &idc_control);
5174 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5175 __qla83xx_set_idc_control(vha, 0);
5176
5177 qla83xx_idc_unlock(vha, 0);
5178 rval = qla83xx_restart_nic_firmware(vha);
5179 qla83xx_idc_lock(vha, 0);
5180
5181 if (rval != QLA_SUCCESS) {
5182 ql_log(ql_log_fatal, vha, 0xb06a,
5183 "Failed to restart NIC f/w.\n");
5184 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5185 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5186 } else {
5187 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5188 "Success in restarting nic f/w.\n");
5189 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5190 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5191 }
5192
5193 return rval;
5194}
5195
5196/* Assumes idc_lock always held on entry */
5197int
5198qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5199{
5200 struct qla_hw_data *ha = base_vha->hw;
5201 int rval = QLA_SUCCESS;
5202 unsigned long dev_init_timeout;
5203 uint32_t dev_state;
5204
5205 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5206 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5207
5208 while (1) {
5209
5210 if (time_after_eq(jiffies, dev_init_timeout)) {
5211 ql_log(ql_log_warn, base_vha, 0xb06e,
5212 "Initialization TIMEOUT!\n");
5213 /* Init timeout. Disable further NIC Core
5214 * communication.
5215 */
5216 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5217 QLA8XXX_DEV_FAILED);
5218 ql_log(ql_log_info, base_vha, 0xb06f,
5219 "HW State: FAILED.\n");
5220 }
5221
5222 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5223 switch (dev_state) {
5224 case QLA8XXX_DEV_READY:
5225 if (ha->flags.nic_core_reset_owner)
5226 qla83xx_idc_audit(base_vha,
5227 IDC_AUDIT_COMPLETION);
5228 ha->flags.nic_core_reset_owner = 0;
5229 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5230 "Reset_owner reset by 0x%x.\n",
5231 ha->portnum);
5232 goto exit;
5233 case QLA8XXX_DEV_COLD:
5234 if (ha->flags.nic_core_reset_owner)
5235 rval = qla83xx_device_bootstrap(base_vha);
5236 else {
5237 /* Wait for AEN to change device-state */
5238 qla83xx_idc_unlock(base_vha, 0);
5239 msleep(1000);
5240 qla83xx_idc_lock(base_vha, 0);
5241 }
5242 break;
5243 case QLA8XXX_DEV_INITIALIZING:
5244 /* Wait for AEN to change device-state */
5245 qla83xx_idc_unlock(base_vha, 0);
5246 msleep(1000);
5247 qla83xx_idc_lock(base_vha, 0);
5248 break;
5249 case QLA8XXX_DEV_NEED_RESET:
5250 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5251 qla83xx_need_reset_handler(base_vha);
5252 else {
5253 /* Wait for AEN to change device-state */
5254 qla83xx_idc_unlock(base_vha, 0);
5255 msleep(1000);
5256 qla83xx_idc_lock(base_vha, 0);
5257 }
5258 /* reset timeout value after need reset handler */
5259 dev_init_timeout = jiffies +
5260 (ha->fcoe_dev_init_timeout * HZ);
5261 break;
5262 case QLA8XXX_DEV_NEED_QUIESCENT:
5263 /* XXX: DEBUG for now */
5264 qla83xx_idc_unlock(base_vha, 0);
5265 msleep(1000);
5266 qla83xx_idc_lock(base_vha, 0);
5267 break;
5268 case QLA8XXX_DEV_QUIESCENT:
5269 /* XXX: DEBUG for now */
5270 if (ha->flags.quiesce_owner)
5271 goto exit;
5272
5273 qla83xx_idc_unlock(base_vha, 0);
5274 msleep(1000);
5275 qla83xx_idc_lock(base_vha, 0);
5276 dev_init_timeout = jiffies +
5277 (ha->fcoe_dev_init_timeout * HZ);
5278 break;
5279 case QLA8XXX_DEV_FAILED:
5280 if (ha->flags.nic_core_reset_owner)
5281 qla83xx_idc_audit(base_vha,
5282 IDC_AUDIT_COMPLETION);
5283 ha->flags.nic_core_reset_owner = 0;
5284 __qla83xx_clear_drv_presence(base_vha);
5285 qla83xx_idc_unlock(base_vha, 0);
5286 qla8xxx_dev_failed_handler(base_vha);
5287 rval = QLA_FUNCTION_FAILED;
5288 qla83xx_idc_lock(base_vha, 0);
5289 goto exit;
5290 case QLA8XXX_BAD_VALUE:
5291 qla83xx_idc_unlock(base_vha, 0);
5292 msleep(1000);
5293 qla83xx_idc_lock(base_vha, 0);
5294 break;
5295 default:
5296 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5297 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5298 qla83xx_idc_unlock(base_vha, 0);
5299 qla8xxx_dev_failed_handler(base_vha);
5300 rval = QLA_FUNCTION_FAILED;
5301 qla83xx_idc_lock(base_vha, 0);
5302 goto exit;
5303 }
5304 }
5305
5306exit:
5307 return rval;
5308}
5309
f3ddac19
CD		 5310void
5311qla2x00_disable_board_on_pci_error(struct work_struct *work)
5312{
5313 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5314 board_disable);
5315 struct pci_dev *pdev = ha->pdev;
5316 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5317
726b8548
QT		 5318 /*
5319 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5320 * where it was set first.
5321 */
5322 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5323 return;
5324
f3ddac19
CD		 5325 ql_log(ql_log_warn, base_vha, 0x015b,
5326 "Disabling adapter.\n");
5327
726b8548
QT		 5328 qla2x00_wait_for_sess_deletion(base_vha);
5329
f3ddac19
CD		 5330 set_bit(UNLOADING, &base_vha->dpc_flags);
5331
5332 qla2x00_delete_all_vps(ha, base_vha);
5333
5334 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5335
5336 qla2x00_dfs_remove(base_vha);
5337
5338 qla84xx_put_chip(base_vha);
5339
5340 if (base_vha->timer_active)
5341 qla2x00_stop_timer(base_vha);
5342
5343 base_vha->flags.online = 0;
5344
5345 qla2x00_destroy_deferred_work(ha);
5346
5347 /*
5348 * Do not try to stop beacon blink as it will issue a mailbox
5349 * command.
5350 */
5351 qla2x00_free_sysfs_attr(base_vha, false);
5352
5353 fc_remove_host(base_vha->host);
5354
5355 scsi_remove_host(base_vha->host);
5356
5357 base_vha->flags.init_done = 0;
5358 qla25xx_delete_queues(base_vha);
f3ddac19 5359 qla2x00_free_fcports(base_vha);
093df737 5360 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5361 qla2x00_mem_free(ha);
5362 qla82xx_md_free(base_vha);
5363 qla2x00_free_queues(ha);
5364
f3ddac19
CD		 5365 qla2x00_unmap_iobases(ha);
5366
5367 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5368 pci_disable_pcie_error_reporting(pdev);
5369 pci_disable_device(pdev);
f3ddac19 5370
beb9e315
JL		 5371 /*
5372 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5373 */
f3ddac19
CD		 5374}
5375
1da177e4
LT		 5376/**************************************************************************
5377* qla2x00_do_dpc
5378* This kernel thread is a task that is schedule by the interrupt handler
5379* to perform the background processing for interrupts.
5380*
5381* Notes:
5382* This task always run in the context of a kernel thread. It
5383* is kick-off by the driver's detect code and starts up
5384* up one per adapter. It immediately goes to sleep and waits for
5385* some fibre event. When either the interrupt handler or
5386* the timer routine detects a event it will one of the task
5387* bits then wake us up.
5388**************************************************************************/
5389static int
5390qla2x00_do_dpc(void *data)
5391{
e315cd28
AC		 5392 scsi_qla_host_t *base_vha;
5393 struct qla_hw_data *ha;
d7459527
MH		 5394 uint32_t online;
5395 struct qla_qpair *qpair;
1da177e4 5396
e315cd28
AC		 5397 ha = (struct qla_hw_data *)data;
5398 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5399
8698a745 5400 set_user_nice(current, MIN_NICE);
1da177e4 5401
563585ec 5402 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5403 while (!kthread_should_stop()) {
7c3df132
SK		 5404 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5405 "DPC handler sleeping.\n");
1da177e4 5406
39a11240 5407 schedule();
1da177e4 5408
c142caf0
AV		 5409 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5410 goto end_loop;
1da177e4 5411
85880801 5412 if (ha->flags.eeh_busy) {
7c3df132
SK		 5413 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5414 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5415 goto end_loop;
85880801
AV		 5416 }
5417
1da177e4
LT		 5418 ha->dpc_active = 1;
5419
5f28d2d7
SK		 5420 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5421 "DPC handler waking up, dpc_flags=0x%lx.\n",
5422 base_vha->dpc_flags);
1da177e4 5423
a29b3dd7
JC		 5424 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5425 break;
5426
e315cd28 5427 qla2x00_do_work(base_vha);
0971de7f 5428
7ec0effd
AD		 5429 if (IS_P3P_TYPE(ha)) {
5430 if (IS_QLA8044(ha)) {
5431 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5432 &base_vha->dpc_flags)) {
5433 qla8044_idc_lock(ha);
5434 qla8044_wr_direct(base_vha,
5435 QLA8044_CRB_DEV_STATE_INDEX,
5436 QLA8XXX_DEV_FAILED);
5437 qla8044_idc_unlock(ha);
5438 ql_log(ql_log_info, base_vha, 0x4004,
5439 "HW State: FAILED.\n");
5440 qla8044_device_state_handler(base_vha);
5441 continue;
5442 }
5443
5444 } else {
5445 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5446 &base_vha->dpc_flags)) {
5447 qla82xx_idc_lock(ha);
5448 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5449 QLA8XXX_DEV_FAILED);
5450 qla82xx_idc_unlock(ha);
5451 ql_log(ql_log_info, base_vha, 0x0151,
5452 "HW State: FAILED.\n");
5453 qla82xx_device_state_handler(base_vha);
5454 continue;
5455 }
a9083016
GM		 5456 }
5457
5458 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5459 &base_vha->dpc_flags)) {
5460
7c3df132
SK		 5461 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5462 "FCoE context reset scheduled.\n");
a9083016
GM		 5463 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5464 &base_vha->dpc_flags))) {
5465 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5466 /* FCoE-ctx reset failed.
5467 * Escalate to chip-reset
5468 */
5469 set_bit(ISP_ABORT_NEEDED,
5470 &base_vha->dpc_flags);
5471 }
5472 clear_bit(ABORT_ISP_ACTIVE,
5473 &base_vha->dpc_flags);
5474 }
5475
7c3df132
SK		 5476 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5477 "FCoE context reset end.\n");
a9083016 5478 }
8ae6d9c7
GM		 5479 } else if (IS_QLAFX00(ha)) {
5480 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5481 &base_vha->dpc_flags)) {
5482 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5483 "Firmware Reset Recovery\n");
5484 if (qlafx00_reset_initialize(base_vha)) {
5485 /* Failed. Abort isp later. */
5486 if (!test_bit(UNLOADING,
f92f82d6 5487 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5488 set_bit(ISP_UNRECOVERABLE,
5489 &base_vha->dpc_flags);
5490 ql_dbg(ql_dbg_dpc, base_vha,
5491 0x4021,
5492 "Reset Recovery Failed\n");
f92f82d6 5493 }
8ae6d9c7
GM		 5494 }
5495 }
5496
5497 if (test_and_clear_bit(FX00_TARGET_SCAN,
5498 &base_vha->dpc_flags)) {
5499 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5500 "ISPFx00 Target Scan scheduled\n");
5501 if (qlafx00_rescan_isp(base_vha)) {
5502 if (!test_bit(UNLOADING,
5503 &base_vha->dpc_flags))
5504 set_bit(ISP_UNRECOVERABLE,
5505 &base_vha->dpc_flags);
5506 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5507 "ISPFx00 Target Scan Failed\n");
5508 }
5509 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5510 "ISPFx00 Target Scan End\n");
5511 }
e8f5e95d
AB		 5512 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5513 &base_vha->dpc_flags)) {
5514 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5515 "ISPFx00 Host Info resend scheduled\n");
5516 qlafx00_fx_disc(base_vha,
5517 &base_vha->hw->mr.fcport,
5518 FXDISC_REG_HOST_INFO);
5519 }
a9083016
GM		 5520 }
5521
e315cd28
AC		 5522 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5523 &base_vha->dpc_flags)) {
1da177e4 5524
7c3df132
SK		 5525 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5526 "ISP abort scheduled.\n");
1da177e4 5527 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5528 &base_vha->dpc_flags))) {
1da177e4 5529
a9083016 5530 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5531 /* failed. retry later */
5532 set_bit(ISP_ABORT_NEEDED,
e315cd28 5533 &base_vha->dpc_flags);
99363ef8 5534 }
e315cd28
AC		 5535 clear_bit(ABORT_ISP_ACTIVE,
5536 &base_vha->dpc_flags);
99363ef8
SJ		 5537 }
5538
7c3df132
SK		 5539 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5540 "ISP abort end.\n");
1da177e4
LT		 5541 }
5542
a394aac8
DJ		 5543 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5544 &base_vha->dpc_flags)) {
e315cd28 5545 qla2x00_update_fcports(base_vha);
c9c5ced9 5546 }
d97994dc 5547
8ae6d9c7
GM		 5548 if (IS_QLAFX00(ha))
5549 goto loop_resync_check;
5550
579d12b5 5551 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5552 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5553 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5554 if (IS_P3P_TYPE(ha)) {
5555 if (IS_QLA82XX(ha))
5556 qla82xx_device_state_handler(base_vha);
5557 if (IS_QLA8044(ha))
5558 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5559 clear_bit(ISP_QUIESCE_NEEDED,
5560 &base_vha->dpc_flags);
5561 if (!ha->flags.quiesce_owner) {
5562 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5563 if (IS_QLA82XX(ha)) {
5564 qla82xx_idc_lock(ha);
5565 qla82xx_clear_qsnt_ready(
5566 base_vha);
5567 qla82xx_idc_unlock(ha);
5568 } else if (IS_QLA8044(ha)) {
5569 qla8044_idc_lock(ha);
5570 qla8044_clear_qsnt_ready(
5571 base_vha);
5572 qla8044_idc_unlock(ha);
5573 }
8fcd6b8b
CD		 5574 }
5575 } else {
5576 clear_bit(ISP_QUIESCE_NEEDED,
5577 &base_vha->dpc_flags);
5578 qla2x00_quiesce_io(base_vha);
579d12b5 5579 }
7c3df132
SK		 5580 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5581 "Quiescence mode end.\n");
579d12b5
SK		 5582 }
5583
e315cd28 5584 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5585 &base_vha->dpc_flags) &&
e315cd28 5586 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5587
7c3df132
SK		 5588 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5589 "Reset marker scheduled.\n");
e315cd28
AC		 5590 qla2x00_rst_aen(base_vha);
5591 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5592 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5593 "Reset marker end.\n");
1da177e4
LT		 5594 }
5595
5596 /* Retry each device up to login retry count */
e315cd28
AC		 5597 if ((test_and_clear_bit(RELOGIN_NEEDED,
5598 &base_vha->dpc_flags)) &&
5599 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5600 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5601
7c3df132
SK		 5602 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5603 "Relogin scheduled.\n");
e315cd28 5604 qla2x00_relogin(base_vha);
7c3df132
SK		 5605 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5606 "Relogin end.\n");
1da177e4 5607 }
8ae6d9c7 5608loop_resync_check:
e315cd28 5609 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5610 &base_vha->dpc_flags)) {
1da177e4 5611
7c3df132
SK		 5612 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5613 "Loop resync scheduled.\n");
1da177e4
LT		 5614
5615 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5616 &base_vha->dpc_flags))) {
1da177e4 5617
52c82823 5618 qla2x00_loop_resync(base_vha);
1da177e4 5619
e315cd28
AC		 5620 clear_bit(LOOP_RESYNC_ACTIVE,
5621 &base_vha->dpc_flags);
1da177e4
LT		 5622 }
5623
7c3df132
SK		 5624 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5625 "Loop resync end.\n");
1da177e4
LT		 5626 }
5627
8ae6d9c7
GM		 5628 if (IS_QLAFX00(ha))
5629 goto intr_on_check;
5630
e315cd28
AC		 5631 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5632 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5633 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5634 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5635 }
5636
8ae6d9c7 5637intr_on_check:
1da177e4 5638 if (!ha->interrupts_on)
fd34f556 5639 ha->isp_ops->enable_intrs(ha);
1da177e4 5640
e315cd28 5641 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5642 &base_vha->dpc_flags)) {
5643 if (ha->beacon_blink_led == 1)
5644 ha->isp_ops->beacon_blink(base_vha);
5645 }
f6df144c 5646
d7459527
MH		 5647 /* qpair online check */
5648 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5649 &base_vha->dpc_flags)) {
5650 if (ha->flags.eeh_busy ||
5651 ha->flags.pci_channel_io_perm_failure)
5652 online = 0;
5653 else
5654 online = 1;
5655
5656 mutex_lock(&ha->mq_lock);
5657 list_for_each_entry(qpair, &base_vha->qp_list,
5658 qp_list_elem)
5659 qpair->online = online;
5660 mutex_unlock(&ha->mq_lock);
5661 }
5662
8ae6d9c7
GM		 5663 if (!IS_QLAFX00(ha))
5664 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5665
1da177e4 5666 ha->dpc_active = 0;
c142caf0 5667end_loop:
563585ec 5668 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5669 } /* End of while(1) */
563585ec 5670 __set_current_state(TASK_RUNNING);
1da177e4 5671
7c3df132
SK		 5672 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5673 "DPC handler exiting.\n");
1da177e4
LT		 5674
5675 /*
5676 * Make sure that nobody tries to wake us up again.
5677 */
1da177e4
LT		 5678 ha->dpc_active = 0;
5679
ac280b67
AV		 5680 /* Cleanup any residual CTX SRBs. */
5681 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5682
39a11240
CH		 5683 return 0;
5684}
5685
5686void
e315cd28 5687qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5688{
e315cd28 5689 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5690 struct task_struct *t = ha->dpc_thread;
5691
e315cd28 5692 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5693 wake_up_process(t);
1da177e4
LT		 5694}
5695
1da177e4
LT		 5696/*
5697* qla2x00_rst_aen
5698* Processes asynchronous reset.
5699*
5700* Input:
5701* ha = adapter block pointer.
5702*/
5703static void
e315cd28 5704qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5705{
e315cd28
AC		 5706 if (vha->flags.online && !vha->flags.reset_active &&
5707 !atomic_read(&vha->loop_down_timer) &&
5708 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5709 do {
e315cd28 5710 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5711
5712 /*
5713 * Issue marker command only when we are going to start
5714 * the I/O.
5715 */
e315cd28
AC		 5716 vha->marker_needed = 1;
5717 } while (!atomic_read(&vha->loop_down_timer) &&
5718 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5719 }
5720}
5721
1da177e4
LT		 5722/**************************************************************************
5723* qla2x00_timer
5724*
5725* Description:
5726* One second timer
5727*
5728* Context: Interrupt
5729***************************************************************************/
2c3dfe3f 5730void
e315cd28 5731qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5732{
1da177e4 5733 unsigned long cpu_flags = 0;
1da177e4
LT		 5734 int start_dpc = 0;
5735 int index;
5736 srb_t *sp;
85880801 5737 uint16_t w;
e315cd28 5738 struct qla_hw_data *ha = vha->hw;
73208dfd 5739 struct req_que *req;
85880801 5740
a5b36321 5741 if (ha->flags.eeh_busy) {
7c3df132
SK		 5742 ql_dbg(ql_dbg_timer, vha, 0x6000,
5743 "EEH = %d, restarting timer.\n",
5744 ha->flags.eeh_busy);
a5b36321
LC		 5745 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5746 return;
5747 }
5748
f3ddac19
CD		 5749 /*
5750 * Hardware read to raise pending EEH errors during mailbox waits. If
5751 * the read returns -1 then disable the board.
5752 */
5753 if (!pci_channel_offline(ha->pdev)) {
85880801 5754 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5755 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5756 }
1da177e4 5757
cefcaba6 5758 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5759 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5760 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5761 start_dpc++;
7ec0effd
AD		 5762 if (IS_QLA82XX(ha))
5763 qla82xx_watchdog(vha);
5764 else if (IS_QLA8044(ha))
5765 qla8044_watchdog(vha);
579d12b5
SK		 5766 }
5767
8ae6d9c7
GM		 5768 if (!vha->vp_idx && IS_QLAFX00(ha))
5769 qlafx00_timer_routine(vha);
5770
1da177e4 5771 /* Loop down handler. */
e315cd28 5772 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5773 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5774 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5775 && vha->flags.online) {
1da177e4 5776
e315cd28
AC		 5777 if (atomic_read(&vha->loop_down_timer) ==
5778 vha->loop_down_abort_time) {
1da177e4 5779
7c3df132
SK		 5780 ql_log(ql_log_info, vha, 0x6008,
5781 "Loop down - aborting the queues before time expires.\n");
1da177e4 5782
e315cd28
AC		 5783 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5784 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5785
f08b7251
AV		 5786 /*
5787 * Schedule an ISP abort to return any FCP2-device
5788 * commands.
5789 */
2c3dfe3f 5790 /* NPIV - scan physical port only */
e315cd28 5791 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5792 spin_lock_irqsave(&ha->hardware_lock,
5793 cpu_flags);
73208dfd 5794 req = ha->req_q_map[0];
2c3dfe3f 5795 for (index = 1;
8d93f550 5796 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5797 index++) {
5798 fc_port_t *sfcp;
5799
e315cd28 5800 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5801 if (!sp)
5802 continue;
9ba56b95 5803 if (sp->type != SRB_SCSI_CMD)
cf53b069 5804 continue;
2c3dfe3f 5805 sfcp = sp->fcport;
f08b7251 5806 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5807 continue;
bdf79621 5808
8f7daead
GM		 5809 if (IS_QLA82XX(ha))
5810 set_bit(FCOE_CTX_RESET_NEEDED,
5811 &vha->dpc_flags);
5812 else
5813 set_bit(ISP_ABORT_NEEDED,
e315cd28 5814 &vha->dpc_flags);
2c3dfe3f
SJ		 5815 break;
5816 }
5817 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5818 cpu_flags);
1da177e4 5819 }
1da177e4
LT		 5820 start_dpc++;
5821 }
5822
5823 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5824 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5825 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5826 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5827 "Loop down - aborting ISP.\n");
5828
8f7daead
GM		 5829 if (IS_QLA82XX(ha))
5830 set_bit(FCOE_CTX_RESET_NEEDED,
5831 &vha->dpc_flags);
5832 else
5833 set_bit(ISP_ABORT_NEEDED,
5834 &vha->dpc_flags);
1da177e4
LT		 5835 }
5836 }
7c3df132
SK		 5837 ql_dbg(ql_dbg_timer, vha, 0x600a,
5838 "Loop down - seconds remaining %d.\n",
5839 atomic_read(&vha->loop_down_timer));
1da177e4 5840 }
cefcaba6
SK		 5841 /* Check if beacon LED needs to be blinked for physical host only */
5842 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5843 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5844 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5845 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5846 start_dpc++;
5847 }
f6df144c
AV		 5848 }
5849
550bf57d 5850 /* Process any deferred work. */
e315cd28 5851 if (!list_empty(&vha->work_list))
550bf57d
AV		 5852 start_dpc++;
5853
1da177e4 5854 /* Schedule the DPC routine if needed */
e315cd28
AC		 5855 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5856 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5857 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5858 start_dpc ||
e315cd28
AC		 5859 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5860 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5861 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5862 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5863 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5864 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5865 ql_dbg(ql_dbg_timer, vha, 0x600b,
5866 "isp_abort_needed=%d loop_resync_needed=%d "
5867 "fcport_update_needed=%d start_dpc=%d "
5868 "reset_marker_needed=%d",
5869 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5870 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5871 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5872 start_dpc,
5873 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5874 ql_dbg(ql_dbg_timer, vha, 0x600c,
5875 "beacon_blink_needed=%d isp_unrecoverable=%d "
5876 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5877 "relogin_needed=%d.\n",
7c3df132
SK		 5878 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5879 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5880 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5881 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5882 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5883 qla2xxx_wake_dpc(vha);
7c3df132 5884 }
1da177e4 5885
e315cd28 5886 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5887}
5888
5433383e
AV		 5889/* Firmware interface routines. */
5890
f73cb695 5891#define FW_BLOBS 11
5433383e
AV		 5892#define FW_ISP21XX 0
5893#define FW_ISP22XX 1
5894#define FW_ISP2300 2
5895#define FW_ISP2322 3
48c02fde 5896#define FW_ISP24XX 4
c3a2f0df 5897#define FW_ISP25XX 5
3a03eb79 5898#define FW_ISP81XX 6
a9083016 5899#define FW_ISP82XX 7
6246b8a1
GM		 5900#define FW_ISP2031 8
5901#define FW_ISP8031 9
2c5bbbb2 5902#define FW_ISP27XX 10
5433383e 5903
bb8ee499
AV		 5904#define FW_FILE_ISP21XX "ql2100_fw.bin"
5905#define FW_FILE_ISP22XX "ql2200_fw.bin"
5906#define FW_FILE_ISP2300 "ql2300_fw.bin"
5907#define FW_FILE_ISP2322 "ql2322_fw.bin"
5908#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5909#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5910#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5911#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5912#define FW_FILE_ISP2031 "ql2600_fw.bin"
5913#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5914#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5915
bb8ee499 5916
e1e82b6f 5917static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5918
5919static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5920 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5921 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5922 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5923 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5924 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5925 { .name = FW_FILE_ISP25XX, },
3a03eb79 5926 { .name = FW_FILE_ISP81XX, },
a9083016 5927 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5928 { .name = FW_FILE_ISP2031, },
5929 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5930 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5931};
5932
5933struct fw_blob *
e315cd28 5934qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5935{
e315cd28 5936 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5937 struct fw_blob *blob;
5938
5433383e
AV		 5939 if (IS_QLA2100(ha)) {
5940 blob = &qla_fw_blobs[FW_ISP21XX];
5941 } else if (IS_QLA2200(ha)) {
5942 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5943 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5944 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5945 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5946 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5947 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5948 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5949 } else if (IS_QLA25XX(ha)) {
5950 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5951 } else if (IS_QLA81XX(ha)) {
5952 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5953 } else if (IS_QLA82XX(ha)) {
5954 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5955 } else if (IS_QLA2031(ha)) {
5956 blob = &qla_fw_blobs[FW_ISP2031];
5957 } else if (IS_QLA8031(ha)) {
5958 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5959 } else if (IS_QLA27XX(ha)) {
5960 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5961 } else {
5962 return NULL;
5433383e
AV		 5963 }
5964
e1e82b6f 5965 mutex_lock(&qla_fw_lock);
5433383e
AV		 5966 if (blob->fw)
5967 goto out;
5968
5969 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5970 ql_log(ql_log_warn, vha, 0x0063,
5971 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5972 blob->fw = NULL;
5973 blob = NULL;
5974 goto out;
5975 }
5976
5977out:
e1e82b6f 5978 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5979 return blob;
5980}
5981
5982static void
5983qla2x00_release_firmware(void)
5984{
5985 int idx;
5986
e1e82b6f 5987 mutex_lock(&qla_fw_lock);
5433383e 5988 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5989 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5990 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5991}
5992
14e660e6
SJ		 5993static pci_ers_result_t
5994qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5995{
85880801
AV		 5996 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5997 struct qla_hw_data *ha = vha->hw;
5998
7c3df132
SK		 5999 ql_dbg(ql_dbg_aer, vha, 0x9000,
6000 "PCI error detected, state %x.\n", state);
b9b12f73 6001
14e660e6
SJ		 6002 switch (state) {
6003 case pci_channel_io_normal:
85880801 6004 ha->flags.eeh_busy = 0;
d7459527
MH		 6005 if (ql2xmqsupport) {
6006 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6007 qla2xxx_wake_dpc(vha);
6008 }
14e660e6
SJ		 6009 return PCI_ERS_RESULT_CAN_RECOVER;
6010 case pci_channel_io_frozen:
85880801 6011 ha->flags.eeh_busy = 1;
a5b36321
LC		 6012 /* For ISP82XX complete any pending mailbox cmd */
6013 if (IS_QLA82XX(ha)) {
7190575f 6014 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6015 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6016 qla82xx_clear_pending_mbx(vha);
a5b36321 6017 }
90a86fc0 6018 qla2x00_free_irqs(vha);
14e660e6 6019 pci_disable_device(pdev);
bddd2d65
LC		 6020 /* Return back all IOs */
6021 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6022 if (ql2xmqsupport) {
6023 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6024 qla2xxx_wake_dpc(vha);
6025 }
14e660e6
SJ		 6026 return PCI_ERS_RESULT_NEED_RESET;
6027 case pci_channel_io_perm_failure:
85880801
AV		 6028 ha->flags.pci_channel_io_perm_failure = 1;
6029 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6030 if (ql2xmqsupport) {
6031 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6032 qla2xxx_wake_dpc(vha);
6033 }
14e660e6
SJ		 6034 return PCI_ERS_RESULT_DISCONNECT;
6035 }
6036 return PCI_ERS_RESULT_NEED_RESET;
6037}
6038
6039static pci_ers_result_t
6040qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6041{
6042 int risc_paused = 0;
6043 uint32_t stat;
6044 unsigned long flags;
e315cd28
AC		 6045 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6046 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6047 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6048 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6049
bcc5b6d3
SK		 6050 if (IS_QLA82XX(ha))
6051 return PCI_ERS_RESULT_RECOVERED;
6052
14e660e6
SJ		 6053 spin_lock_irqsave(&ha->hardware_lock, flags);
6054 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6055 stat = RD_REG_DWORD(&reg->hccr);
6056 if (stat & HCCR_RISC_PAUSE)
6057 risc_paused = 1;
6058 } else if (IS_QLA23XX(ha)) {
6059 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6060 if (stat & HSR_RISC_PAUSED)
6061 risc_paused = 1;
6062 } else if (IS_FWI2_CAPABLE(ha)) {
6063 stat = RD_REG_DWORD(&reg24->host_status);
6064 if (stat & HSRX_RISC_PAUSED)
6065 risc_paused = 1;
6066 }
6067 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6068
6069 if (risc_paused) {
7c3df132
SK		 6070 ql_log(ql_log_info, base_vha, 0x9003,
6071 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6072 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6073
6074 return PCI_ERS_RESULT_NEED_RESET;
6075 } else
6076 return PCI_ERS_RESULT_RECOVERED;
6077}
6078
fa492630
SK		 6079static uint32_t
6080qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6081{
6082 uint32_t rval = QLA_FUNCTION_FAILED;
6083 uint32_t drv_active = 0;
6084 struct qla_hw_data *ha = base_vha->hw;
6085 int fn;
6086 struct pci_dev *other_pdev = NULL;
6087
7c3df132
SK		 6088 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6089 "Entered %s.\n", __func__);
a5b36321
LC		 6090
6091 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6092
6093 if (base_vha->flags.online) {
6094 /* Abort all outstanding commands,
6095 * so as to be requeued later */
6096 qla2x00_abort_isp_cleanup(base_vha);
6097 }
6098
6099
6100 fn = PCI_FUNC(ha->pdev->devfn);
6101 while (fn > 0) {
6102 fn--;
7c3df132
SK		 6103 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6104 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6105 other_pdev =
6106 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6107 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6108 fn));
6109
6110 if (!other_pdev)
6111 continue;
6112 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6113 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6114 "Found PCI func available and enable at 0x%x.\n",
6115 fn);
a5b36321
LC		 6116 pci_dev_put(other_pdev);
6117 break;
6118 }
6119 pci_dev_put(other_pdev);
6120 }
6121
6122 if (!fn) {
6123 /* Reset owner */
7c3df132
SK		 6124 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6125 "This devfn is reset owner = 0x%x.\n",
6126 ha->pdev->devfn);
a5b36321
LC		 6127 qla82xx_idc_lock(ha);
6128
6129 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6130 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6131
6132 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6133 QLA82XX_IDC_VERSION);
6134
6135 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6136 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6137 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6138
6139 qla82xx_idc_unlock(ha);
6140 /* Reset if device is not already reset
6141 * drv_active would be 0 if a reset has already been done
6142 */
6143 if (drv_active)
6144 rval = qla82xx_start_firmware(base_vha);
6145 else
6146 rval = QLA_SUCCESS;
6147 qla82xx_idc_lock(ha);
6148
6149 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6150 ql_log(ql_log_info, base_vha, 0x900b,
6151 "HW State: FAILED.\n");
a5b36321
LC		 6152 qla82xx_clear_drv_active(ha);
6153 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6154 QLA8XXX_DEV_FAILED);
a5b36321 6155 } else {
7c3df132
SK		 6156 ql_log(ql_log_info, base_vha, 0x900c,
6157 "HW State: READY.\n");
a5b36321 6158 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6159 QLA8XXX_DEV_READY);
a5b36321 6160 qla82xx_idc_unlock(ha);
7190575f 6161 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6162 rval = qla82xx_restart_isp(base_vha);
6163 qla82xx_idc_lock(ha);
6164 /* Clear driver state register */
6165 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6166 qla82xx_set_drv_active(base_vha);
6167 }
6168 qla82xx_idc_unlock(ha);
6169 } else {
7c3df132
SK		 6170 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6171 "This devfn is not reset owner = 0x%x.\n",
6172 ha->pdev->devfn);
a5b36321 6173 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6174 QLA8XXX_DEV_READY)) {
7190575f 6175 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6176 rval = qla82xx_restart_isp(base_vha);
6177 qla82xx_idc_lock(ha);
6178 qla82xx_set_drv_active(base_vha);
6179 qla82xx_idc_unlock(ha);
6180 }
6181 }
6182 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6183
6184 return rval;
6185}
6186
14e660e6
SJ		 6187static pci_ers_result_t
6188qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6189{
6190 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6191 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6192 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6193 struct rsp_que *rsp;
6194 int rc, retries = 10;
09483916 6195
7c3df132
SK		 6196 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6197 "Slot Reset.\n");
85880801 6198
90a86fc0
JC		 6199 /* Workaround: qla2xxx driver which access hardware earlier
6200 * needs error state to be pci_channel_io_online.
6201 * Otherwise mailbox command timesout.
6202 */
6203 pdev->error_state = pci_channel_io_normal;
6204
6205 pci_restore_state(pdev);
6206
8c1496bd
RL		 6207 /* pci_restore_state() clears the saved_state flag of the device
6208 * save restored state which resets saved_state flag
6209 */
6210 pci_save_state(pdev);
6211
09483916
BH		 6212 if (ha->mem_only)
6213 rc = pci_enable_device_mem(pdev);
6214 else
6215 rc = pci_enable_device(pdev);
14e660e6 6216
09483916 6217 if (rc) {
7c3df132 6218 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6219 "Can't re-enable PCI device after reset.\n");
a5b36321 6220 goto exit_slot_reset;
14e660e6 6221 }
14e660e6 6222
90a86fc0
JC		 6223 rsp = ha->rsp_q_map[0];
6224 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6225 goto exit_slot_reset;
90a86fc0 6226
e315cd28 6227 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6228 goto exit_slot_reset;
6229
6230 if (IS_QLA82XX(ha)) {
6231 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6232 ret = PCI_ERS_RESULT_RECOVERED;
6233 goto exit_slot_reset;
6234 } else
6235 goto exit_slot_reset;
6236 }
14e660e6 6237
90a86fc0
JC		 6238 while (ha->flags.mbox_busy && retries--)
6239 msleep(1000);
85880801 6240
e315cd28 6241 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6242 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6243 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6244 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6245
90a86fc0 6246
a5b36321 6247exit_slot_reset:
7c3df132
SK		 6248 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6249 "slot_reset return %x.\n", ret);
85880801 6250
14e660e6
SJ		 6251 return ret;
6252}
6253
6254static void
6255qla2xxx_pci_resume(struct pci_dev *pdev)
6256{
e315cd28
AC		 6257 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6258 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6259 int ret;
6260
7c3df132
SK		 6261 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6262 "pci_resume.\n");
85880801 6263
e315cd28 6264 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6265 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6266 ql_log(ql_log_fatal, base_vha, 0x9002,
6267 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6268 }
85880801 6269
3e46f031
LC		 6270 pci_cleanup_aer_uncorrect_error_status(pdev);
6271
85880801 6272 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6273}
6274
2d5a4c34
HM		 6275static void
6276qla83xx_disable_laser(scsi_qla_host_t *vha)
6277{
6278 uint32_t reg, data, fn;
6279 struct qla_hw_data *ha = vha->hw;
6280 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6281
6282 /* pci func #/port # */
6283 ql_dbg(ql_dbg_init, vha, 0x004b,
6284 "Disabling Laser for hba: %p\n", vha);
6285
6286 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6287 (BIT_15|BIT_14|BIT_13|BIT_12));
6288
6289 fn = (fn >> 12);
6290
6291 if (fn & 1)
6292 reg = PORT_1_2031;
6293 else
6294 reg = PORT_0_2031;
6295
6296 data = LASER_OFF_2031;
6297
6298 qla83xx_wr_reg(vha, reg, data);
6299}
6300
5601236b
MH		 6301static int qla2xxx_map_queues(struct Scsi_Host *shost)
6302{
6303 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6304
6305 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6306}
6307
a55b2d21 6308static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6309 .error_detected = qla2xxx_pci_error_detected,
6310 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6311 .slot_reset = qla2xxx_pci_slot_reset,
6312 .resume = qla2xxx_pci_resume,
6313};
6314
5433383e 6315static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6332 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6333 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6334 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6335 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6336 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6337 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6338 { 0 },
6339};
6340MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6341
fca29703 6342static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6343 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6344 .driver = {
6345 .owner = THIS_MODULE,
6346 },
fca29703 6347 .id_table = qla2xxx_pci_tbl,
7ee61397 6348 .probe = qla2x00_probe_one,
4c993f76 6349 .remove = qla2x00_remove_one,
e30d1756 6350 .shutdown = qla2x00_shutdown,
14e660e6 6351 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6352};
6353
75ef9de1 6354static const struct file_operations apidev_fops = {
6a03b4cd 6355 .owner = THIS_MODULE,
6038f373 6356 .llseek = noop_llseek,
6a03b4cd
HZ		 6357};
6358
1da177e4
LT		 6359/**
6360 * qla2x00_module_init - Module initialization.
6361 **/
6362static int __init
6363qla2x00_module_init(void)
6364{
fca29703
AV		 6365 int ret = 0;
6366
1da177e4 6367 /* Allocate cache for SRBs. */
354d6b21 6368 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6369 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6370 if (srb_cachep == NULL) {
7c3df132
SK		 6371 ql_log(ql_log_fatal, NULL, 0x0001,
6372 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6373 return -ENOMEM;
6374 }
6375
2d70c103
NB		 6376 /* Initialize target kmem_cache and mem_pools */
6377 ret = qlt_init();
6378 if (ret < 0) {
6379 kmem_cache_destroy(srb_cachep);
6380 return ret;
6381 } else if (ret > 0) {
6382 /*
6383 * If initiator mode is explictly disabled by qlt_init(),
6384 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6385 * performing scsi_scan_target() during LOOP UP event.
6386 */
6387 qla2xxx_transport_functions.disable_target_scan = 1;
6388 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6389 }
6390
1da177e4
LT		 6391 /* Derive version string. */
6392 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6393 if (ql2xextended_error_logging)
0181944f
AV		 6394 strcat(qla2x00_version_str, "-debug");
6395
1c97a12a
AV		 6396 qla2xxx_transport_template =
6397 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6398 if (!qla2xxx_transport_template) {
6399 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6400 ql_log(ql_log_fatal, NULL, 0x0002,
6401 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6402 qlt_exit();
1da177e4 6403 return -ENODEV;
2c3dfe3f 6404 }
6a03b4cd
HZ		 6405
6406 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6407 if (apidev_major < 0) {
7c3df132
SK		 6408 ql_log(ql_log_fatal, NULL, 0x0003,
6409 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6410 }
6411
2c3dfe3f
SJ		 6412 qla2xxx_transport_vport_template =
6413 fc_attach_transport(&qla2xxx_transport_vport_functions);
6414 if (!qla2xxx_transport_vport_template) {
6415 kmem_cache_destroy(srb_cachep);
2d70c103 6416 qlt_exit();
2c3dfe3f 6417 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6418 ql_log(ql_log_fatal, NULL, 0x0004,
6419 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6420 return -ENODEV;
2c3dfe3f 6421 }
7c3df132
SK		 6422 ql_log(ql_log_info, NULL, 0x0005,
6423 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6424 qla2x00_version_str);
7ee61397 6425 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6426 if (ret) {
6427 kmem_cache_destroy(srb_cachep);
2d70c103 6428 qlt_exit();
fca29703 6429 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6430 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6431 ql_log(ql_log_fatal, NULL, 0x0006,
6432 "pci_register_driver failed...ret=%d Failing load!.\n",
6433 ret);
fca29703
AV		 6434 }
6435 return ret;
1da177e4
LT		 6436}
6437
6438/**
6439 * qla2x00_module_exit - Module cleanup.
6440 **/
6441static void __exit
6442qla2x00_module_exit(void)
6443{
6a03b4cd 6444 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6445 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6446 qla2x00_release_firmware();
354d6b21 6447 kmem_cache_destroy(srb_cachep);
2d70c103 6448 qlt_exit();
a9083016
GM		 6449 if (ctx_cachep)
6450 kmem_cache_destroy(ctx_cachep);
1da177e4 6451 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6452 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6453}
6454
6455module_init(qla2x00_module_init);
6456module_exit(qla2x00_module_exit);
6457
6458MODULE_AUTHOR("QLogic Corporation");
6459MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6460MODULE_LICENSE("GPL");
6461MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6462MODULE_FIRMWARE(FW_FILE_ISP21XX);
6463MODULE_FIRMWARE(FW_FILE_ISP22XX);
6464MODULE_FIRMWARE(FW_FILE_ISP2300);
6465MODULE_FIRMWARE(FW_FILE_ISP2322);
6466MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6467MODULE_FIRMWARE(FW_FILE_ISP25XX);
Ubuntu Artful kernel mirror