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scsi: qla2xxx: Add support for ZIO6 interrupt threshold
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
e7240af5
HM		 271int ql2xenablemsix = 1;
272module_param(ql2xenablemsix, int, 0444);
273MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
9ecf0b0d
QT		 280int qla2xuseresexchforels;
281module_param(qla2xuseresexchforels, int, 0444);
282MODULE_PARM_DESC(qla2xuseresexchforels,
283 "Reserve 1/2 of emergency exchanges for ELS.\n"
284 " 0 (default): disabled");
285
1da177e4 286/*
fa2a1ce5 287 * SCSI host template entry points
1da177e4
LT		 288 */
289static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 290static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 291static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
292static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 293static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 294static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 295static int qla2xxx_eh_abort(struct scsi_cmnd *);
296static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 297static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 298static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
299static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 300
1a2fbf18 301static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 302static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 303static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 304static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 305
45235022 306
a5326f86 307struct scsi_host_template qla2xxx_driver_template = {
1da177e4 308 .module = THIS_MODULE,
cb63067a 309 .name = QLA2XXX_DRIVER_NAME,
a5326f86 310 .queuecommand = qla2xxx_queuecommand,
fca29703 311
b6a05c82 312 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 313 .eh_abort_handler = qla2xxx_eh_abort,
314 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 315 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 316 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
317 .eh_host_reset_handler = qla2xxx_eh_host_reset,
318
319 .slave_configure = qla2xxx_slave_configure,
320
321 .slave_alloc = qla2xxx_slave_alloc,
322 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 323 .scan_finished = qla2xxx_scan_finished,
324 .scan_start = qla2xxx_scan_start,
db5ed4df 325 .change_queue_depth = scsi_change_queue_depth,
5601236b 326 .map_queues = qla2xxx_map_queues,
fca29703
AV		 327 .this_id = -1,
328 .cmd_per_lun = 3,
329 .use_clustering = ENABLE_CLUSTERING,
330 .sg_tablesize = SG_ALL,
331
332 .max_sectors = 0xFFFF,
afb046e2 333 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 334
335 .supported_mode = MODE_INITIATOR,
c40ecc12 336 .track_queue_depth = 1,
fca29703
AV		 337};
338
1da177e4 339static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 340struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 341
1da177e4
LT		 342/* TODO Convert to inlines
343 *
344 * Timer routines
345 */
1da177e4 346
2c3dfe3f 347__inline__ void
8e5f4ba0 348qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 349{
8e5f4ba0 350 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 351 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 352 add_timer(&vha->timer);
353 vha->timer_active = 1;
1da177e4
LT		 354}
355
356static inline void
e315cd28 357qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 358{
a9083016 359 /* Currently used for 82XX only. */
7c3df132
SK		 360 if (vha->device_flags & DFLG_DEV_FAILED) {
361 ql_dbg(ql_dbg_timer, vha, 0x600d,
362 "Device in a failed state, returning.\n");
a9083016 363 return;
7c3df132 364 }
a9083016 365
e315cd28 366 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 367}
368
a824ebb3 369static __inline__ void
e315cd28 370qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 371{
e315cd28
AC		 372 del_timer_sync(&vha->timer);
373 vha->timer_active = 0;
1da177e4
LT		 374}
375
1da177e4
LT		 376static int qla2x00_do_dpc(void *data);
377
378static void qla2x00_rst_aen(scsi_qla_host_t *);
379
73208dfd
AC		 380static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
381 struct req_que **, struct rsp_que **);
e30d1756 382static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 383static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 384int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
385 struct qla_qpair *qpair);
1da177e4 386
1da177e4 387/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 388static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
389 struct rsp_que *rsp)
390{
391 struct qla_hw_data *ha = vha->hw;
392 rsp->qpair = ha->base_qpair;
393 rsp->req = req;
0691094f 394 ha->base_qpair->hw = ha;
8abfa9e2
QT		 395 ha->base_qpair->req = req;
396 ha->base_qpair->rsp = rsp;
397 ha->base_qpair->vha = vha;
398 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
399 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
400 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
401 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
402 ha->base_qpair->enable_class_2 = ql2xenableclass2;
403 /* init qpair to this cpu. Will adjust at run time. */
86531887 404 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 405 ha->base_qpair->pdev = ha->pdev;
406
407 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
408 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
409}
410
9a347ff4
CD		 411static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
412 struct rsp_que *rsp)
73208dfd 413{
7c3df132 414 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
6396bb22 415 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 416 GFP_KERNEL);
417 if (!ha->req_q_map) {
7c3df132
SK		 418 ql_log(ql_log_fatal, vha, 0x003b,
419 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 420 goto fail_req_map;
421 }
422
6396bb22 423 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 424 GFP_KERNEL);
425 if (!ha->rsp_q_map) {
7c3df132
SK		 426 ql_log(ql_log_fatal, vha, 0x003c,
427 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 428 goto fail_rsp_map;
429 }
d7459527 430
e326d22a
QT		 431 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
432 if (ha->base_qpair == NULL) {
433 ql_log(ql_log_warn, vha, 0x00e0,
434 "Failed to allocate base queue pair memory.\n");
435 goto fail_base_qpair;
436 }
437
8abfa9e2 438 qla_init_base_qpair(vha, req, rsp);
e326d22a 439
c38d1baf 440 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 441 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
442 GFP_KERNEL);
443 if (!ha->queue_pair_map) {
444 ql_log(ql_log_fatal, vha, 0x0180,
445 "Unable to allocate memory for queue pair ptrs.\n");
446 goto fail_qpair_map;
447 }
d7459527
MH		 448 }
449
9a347ff4
CD		 450 /*
451 * Make sure we record at least the request and response queue zero in
452 * case we need to free them if part of the probe fails.
453 */
454 ha->rsp_q_map[0] = rsp;
455 ha->req_q_map[0] = req;
73208dfd
AC		 456 set_bit(0, ha->rsp_qid_map);
457 set_bit(0, ha->req_qid_map);
6a2cf8d3 458 return 0;
73208dfd 459
d7459527 460fail_qpair_map:
82de802a
QT		 461 kfree(ha->base_qpair);
462 ha->base_qpair = NULL;
463fail_base_qpair:
d7459527
MH		 464 kfree(ha->rsp_q_map);
465 ha->rsp_q_map = NULL;
73208dfd
AC		 466fail_rsp_map:
467 kfree(ha->req_q_map);
468 ha->req_q_map = NULL;
469fail_req_map:
470 return -ENOMEM;
471}
472
2afa19a9 473static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 474{
8ae6d9c7
GM		 475 if (IS_QLAFX00(ha)) {
476 if (req && req->ring_fx00)
477 dma_free_coherent(&ha->pdev->dev,
478 (req->length_fx00 + 1) * sizeof(request_t),
479 req->ring_fx00, req->dma_fx00);
480 } else if (req && req->ring)
73208dfd
AC		 481 dma_free_coherent(&ha->pdev->dev,
482 (req->length + 1) * sizeof(request_t),
483 req->ring, req->dma);
484
6d634067 485 if (req)
8d93f550 486 kfree(req->outstanding_cmds);
6d634067
BK		 487
488 kfree(req);
73208dfd
AC		 489}
490
2afa19a9
AC		 491static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
492{
8ae6d9c7 493 if (IS_QLAFX00(ha)) {
3f6c9be2 494 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 495 dma_free_coherent(&ha->pdev->dev,
496 (rsp->length_fx00 + 1) * sizeof(request_t),
497 rsp->ring_fx00, rsp->dma_fx00);
498 } else if (rsp && rsp->ring) {
2afa19a9
AC		 499 dma_free_coherent(&ha->pdev->dev,
500 (rsp->length + 1) * sizeof(response_t),
501 rsp->ring, rsp->dma);
8ae6d9c7 502 }
6d634067 503 kfree(rsp);
2afa19a9
AC		 504}
505
73208dfd
AC		 506static void qla2x00_free_queues(struct qla_hw_data *ha)
507{
508 struct req_que *req;
509 struct rsp_que *rsp;
510 int cnt;
093df737 511 unsigned long flags;
73208dfd 512
82de802a
QT		 513 if (ha->queue_pair_map) {
514 kfree(ha->queue_pair_map);
515 ha->queue_pair_map = NULL;
516 }
517 if (ha->base_qpair) {
518 kfree(ha->base_qpair);
519 ha->base_qpair = NULL;
520 }
521
093df737 522 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 523 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 524 if (!test_bit(cnt, ha->req_qid_map))
525 continue;
526
73208dfd 527 req = ha->req_q_map[cnt];
093df737
QT		 528 clear_bit(cnt, ha->req_qid_map);
529 ha->req_q_map[cnt] = NULL;
530
531 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 532 qla2x00_free_req_que(ha, req);
093df737 533 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 534 }
093df737
QT		 535 spin_unlock_irqrestore(&ha->hardware_lock, flags);
536
73208dfd
AC		 537 kfree(ha->req_q_map);
538 ha->req_q_map = NULL;
2afa19a9 539
093df737
QT		 540
541 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 542 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 543 if (!test_bit(cnt, ha->rsp_qid_map))
544 continue;
545
2afa19a9 546 rsp = ha->rsp_q_map[cnt];
c3c42394 547 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 548 ha->rsp_q_map[cnt] = NULL;
549 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 550 qla2x00_free_rsp_que(ha, rsp);
093df737 551 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 552 }
093df737
QT		 553 spin_unlock_irqrestore(&ha->hardware_lock, flags);
554
2afa19a9
AC		 555 kfree(ha->rsp_q_map);
556 ha->rsp_q_map = NULL;
73208dfd
AC		 557}
558
1da177e4 559static char *
e315cd28 560qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 561{
e315cd28 562 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 563 static char *pci_bus_modes[] = {
564 "33", "66", "100", "133",
565 };
566 uint16_t pci_bus;
567
568 strcpy(str, "PCI");
569 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
570 if (pci_bus) {
571 strcat(str, "-X (");
572 strcat(str, pci_bus_modes[pci_bus]);
573 } else {
574 pci_bus = (ha->pci_attr & BIT_8) >> 8;
575 strcat(str, " (");
576 strcat(str, pci_bus_modes[pci_bus]);
577 }
578 strcat(str, " MHz)");
579
580 return (str);
581}
582
fca29703 583static char *
e315cd28 584qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 585{
586 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 587 struct qla_hw_data *ha = vha->hw;
fca29703 588 uint32_t pci_bus;
fca29703 589
62a276f8 590 if (pci_is_pcie(ha->pdev)) {
fca29703 591 char lwstr[6];
62a276f8 592 uint32_t lstat, lspeed, lwidth;
fca29703 593
62a276f8
BH		 594 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
595 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
596 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 597
598 strcpy(str, "PCIe (");
49300af7
SK		 599 switch (lspeed) {
600 case 1:
c87a0d8c 601 strcat(str, "2.5GT/s ");
49300af7
SK		 602 break;
603 case 2:
c87a0d8c 604 strcat(str, "5.0GT/s ");
49300af7
SK		 605 break;
606 case 3:
607 strcat(str, "8.0GT/s ");
608 break;
609 default:
fca29703 610 strcat(str, "<unknown> ");
49300af7
SK		 611 break;
612 }
fca29703
AV		 613 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
614 strcat(str, lwstr);
615
616 return str;
617 }
618
619 strcpy(str, "PCI");
620 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
621 if (pci_bus == 0 || pci_bus == 8) {
622 strcat(str, " (");
623 strcat(str, pci_bus_modes[pci_bus >> 3]);
624 } else {
625 strcat(str, "-X ");
626 if (pci_bus & BIT_2)
627 strcat(str, "Mode 2");
628 else
629 strcat(str, "Mode 1");
630 strcat(str, " (");
631 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
632 }
633 strcat(str, " MHz)");
634
635 return str;
636}
637
e5f82ab8 638static char *
df57caba 639qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 640{
641 char un_str[10];
e315cd28 642 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 643
df57caba
HM		 644 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
645 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 646
647 if (ha->fw_attributes & BIT_9) {
648 strcat(str, "FLX");
649 return (str);
650 }
651
652 switch (ha->fw_attributes & 0xFF) {
653 case 0x7:
654 strcat(str, "EF");
655 break;
656 case 0x17:
657 strcat(str, "TP");
658 break;
659 case 0x37:
660 strcat(str, "IP");
661 break;
662 case 0x77:
663 strcat(str, "VI");
664 break;
665 default:
666 sprintf(un_str, "(%x)", ha->fw_attributes);
667 strcat(str, un_str);
668 break;
669 }
670 if (ha->fw_attributes & 0x100)
671 strcat(str, "X");
672
673 return (str);
674}
675
e5f82ab8 676static char *
df57caba 677qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 678{
e315cd28 679 struct qla_hw_data *ha = vha->hw;
f0883ac6 680
df57caba 681 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 682 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 683 return str;
fca29703
AV		 684}
685
9ba56b95 686void
25ff6af1 687qla2x00_sp_free_dma(void *ptr)
fca29703 688{
25ff6af1
JC		 689 srb_t *sp = ptr;
690 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 691 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 692 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 693
9ba56b95
GM		 694 if (sp->flags & SRB_DMA_VALID) {
695 scsi_dma_unmap(cmd);
696 sp->flags &= ~SRB_DMA_VALID;
7c3df132 697 }
fca29703 698
9ba56b95
GM		 699 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
700 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
701 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
702 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
703 }
704
d5ff0eed
JC		 705 if (!ctx)
706 goto end;
707
9ba56b95
GM		 708 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
709 /* List assured to be having elements */
d5ff0eed 710 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 711 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
712 }
713
714 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 715 struct crc_context *ctx0 = ctx;
716
717 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 718 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
719 }
720
721 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 722 struct ct6_dsd *ctx1 = ctx;
fca29703 723
9ba56b95 724 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 725 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 726 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
727 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
728 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
729 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 730 }
731
d5ff0eed 732end:
6fcd98fd 733 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 734 CMD_SP(cmd) = NULL;
735 qla2x00_rel_sp(sp);
736 }
9ba56b95
GM		 737}
738
d7459527 739void
25ff6af1 740qla2x00_sp_compl(void *ptr, int res)
9ba56b95 741{
25ff6af1 742 srb_t *sp = ptr;
9ba56b95
GM		 743 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
744
745 cmd->result = res;
746
747 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 748 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 749 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
750 sp, GET_CMD_SP(sp));
751 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 752 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 753 return;
754 }
755 if (!atomic_dec_and_test(&sp->ref_count))
756 return;
757
f3caa990 758 sp->free(sp);
9ba56b95 759 cmd->scsi_done(cmd);
fca29703
AV		 760}
761
d7459527 762void
25ff6af1 763qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 764{
765 srb_t *sp = (srb_t *)ptr;
766 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
767 struct qla_hw_data *ha = sp->fcport->vha->hw;
768 void *ctx = GET_CMD_CTX_SP(sp);
769
770 if (sp->flags & SRB_DMA_VALID) {
771 scsi_dma_unmap(cmd);
772 sp->flags &= ~SRB_DMA_VALID;
773 }
774
775 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
776 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
777 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
778 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
779 }
780
d5ff0eed
JC		 781 if (!ctx)
782 goto end;
783
d7459527
MH		 784 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
785 /* List assured to be having elements */
d5ff0eed 786 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 787 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
788 }
789
790 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 791 struct crc_context *ctx0 = ctx;
792
793 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 794 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
795 }
796
797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 798 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 799 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
800 ctx1->fcp_cmnd_dma);
801 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
802 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
803 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
804 mempool_free(ctx1, ha->ctx_mempool);
805 }
d5ff0eed 806end:
d7459527
MH		 807 CMD_SP(cmd) = NULL;
808 qla2xxx_rel_qpair_sp(sp->qpair, sp);
809}
810
811void
25ff6af1 812qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 813{
25ff6af1 814 srb_t *sp = ptr;
d7459527
MH		 815 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
816
817 cmd->result = res;
818
819 if (atomic_read(&sp->ref_count) == 0) {
820 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
821 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
822 sp, GET_CMD_SP(sp));
823 if (ql2xextended_error_logging & ql_dbg_io)
824 WARN_ON(atomic_read(&sp->ref_count) == 0);
825 return;
826 }
827 if (!atomic_dec_and_test(&sp->ref_count))
828 return;
829
f3caa990 830 sp->free(sp);
d7459527
MH		 831 cmd->scsi_done(cmd);
832}
833
8ae6d9c7
GM		 834/* If we are SP1 here, we need to still take and release the host_lock as SP1
835 * does not have the changes necessary to avoid taking host->host_lock.
836 */
1da177e4 837static int
f5e3e40b 838qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 839{
134ae078 840 scsi_qla_host_t *vha = shost_priv(host);
fca29703 841 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 842 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 843 struct qla_hw_data *ha = vha->hw;
844 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 845 srb_t *sp;
846 int rval;
5601236b
MH		 847 struct qla_qpair *qpair = NULL;
848 uint32_t tag;
849 uint16_t hwq;
fca29703 850
04dfaa53
MFO		 851 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
852 cmd->result = DID_NO_CONNECT << 16;
853 goto qc24_fail_command;
854 }
855
5601236b
MH		 856 if (ha->mqenable) {
857 if (shost_use_blk_mq(vha->host)) {
858 tag = blk_mq_unique_tag(cmd->request);
859 hwq = blk_mq_unique_tag_to_hwq(tag);
860 qpair = ha->queue_pair_map[hwq];
861 } else if (vha->vp_idx && vha->qpair) {
862 qpair = vha->qpair;
863 }
864
865 if (qpair)
866 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 867 }
868
85880801 869 if (ha->flags.eeh_busy) {
7c3df132 870 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 871 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 872 "PCI Channel IO permanent failure, exiting "
873 "cmd=%p.\n", cmd);
b9b12f73 874 cmd->result = DID_NO_CONNECT << 16;
7c3df132 875 } else {
5f28d2d7 876 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 877 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 878 cmd->result = DID_REQUEUE << 16;
7c3df132 879 }
14e660e6
SJ		 880 goto qc24_fail_command;
881 }
882
19a7b4ae
JSEC		 883 rval = fc_remote_port_chkready(rport);
884 if (rval) {
885 cmd->result = rval;
5f28d2d7 886 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 887 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
888 cmd, rval);
fca29703
AV		 889 goto qc24_fail_command;
890 }
891
bad75002
AE		 892 if (!vha->flags.difdix_supported &&
893 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 894 ql_dbg(ql_dbg_io, vha, 0x3004,
895 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
896 cmd);
bad75002
AE		 897 cmd->result = DID_NO_CONNECT << 16;
898 goto qc24_fail_command;
899 }
aa651be8
CD		 900
901 if (!fcport) {
902 cmd->result = DID_NO_CONNECT << 16;
903 goto qc24_fail_command;
904 }
905
fca29703
AV		 906 if (atomic_read(&fcport->state) != FCS_ONLINE) {
907 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 908 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 909 ql_dbg(ql_dbg_io, vha, 0x3005,
910 "Returning DNC, fcport_state=%d loop_state=%d.\n",
911 atomic_read(&fcport->state),
912 atomic_read(&base_vha->loop_state));
fca29703
AV		 913 cmd->result = DID_NO_CONNECT << 16;
914 goto qc24_fail_command;
915 }
7b594131 916 goto qc24_target_busy;
fca29703
AV		 917 }
918
e05fe292
CD		 919 /*
920 * Return target busy if we've received a non-zero retry_delay_timer
921 * in a FCP_RSP.
922 */
975f7d46
BP		 923 if (fcport->retry_delay_timestamp == 0) {
924 /* retry delay not set */
925 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 926 fcport->retry_delay_timestamp = 0;
927 else
928 goto qc24_target_busy;
929
b00ee7d7 930 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 931 if (!sp)
f5e3e40b 932 goto qc24_host_busy;
fca29703 933
9ba56b95
GM		 934 sp->u.scmd.cmd = cmd;
935 sp->type = SRB_SCSI_CMD;
936 atomic_set(&sp->ref_count, 1);
937 CMD_SP(cmd) = (void *)sp;
938 sp->free = qla2x00_sp_free_dma;
939 sp->done = qla2x00_sp_compl;
940
e315cd28 941 rval = ha->isp_ops->start_scsi(sp);
7c3df132 942 if (rval != QLA_SUCCESS) {
53016ed3 943 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 944 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 945 goto qc24_host_busy_free_sp;
7c3df132 946 }
fca29703 947
fca29703
AV		 948 return 0;
949
950qc24_host_busy_free_sp:
f3caa990 951 sp->free(sp);
fca29703 952
f5e3e40b 953qc24_host_busy:
fca29703
AV		 954 return SCSI_MLQUEUE_HOST_BUSY;
955
7b594131
MC		 956qc24_target_busy:
957 return SCSI_MLQUEUE_TARGET_BUSY;
958
fca29703 959qc24_fail_command:
f5e3e40b 960 cmd->scsi_done(cmd);
fca29703
AV		 961
962 return 0;
963}
964
d7459527
MH		 965/* For MQ supported I/O */
966int
967qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
968 struct qla_qpair *qpair)
969{
970 scsi_qla_host_t *vha = shost_priv(host);
971 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
972 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
973 struct qla_hw_data *ha = vha->hw;
974 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
975 srb_t *sp;
976 int rval;
977
978 rval = fc_remote_port_chkready(rport);
979 if (rval) {
980 cmd->result = rval;
981 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
982 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
983 cmd, rval);
984 goto qc24_fail_command;
985 }
986
987 if (!fcport) {
988 cmd->result = DID_NO_CONNECT << 16;
989 goto qc24_fail_command;
990 }
991
992 if (atomic_read(&fcport->state) != FCS_ONLINE) {
993 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
994 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
995 ql_dbg(ql_dbg_io, vha, 0x3077,
996 "Returning DNC, fcport_state=%d loop_state=%d.\n",
997 atomic_read(&fcport->state),
998 atomic_read(&base_vha->loop_state));
999 cmd->result = DID_NO_CONNECT << 16;
1000 goto qc24_fail_command;
1001 }
1002 goto qc24_target_busy;
1003 }
1004
1005 /*
1006 * Return target busy if we've received a non-zero retry_delay_timer
1007 * in a FCP_RSP.
1008 */
1009 if (fcport->retry_delay_timestamp == 0) {
1010 /* retry delay not set */
1011 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1012 fcport->retry_delay_timestamp = 0;
1013 else
1014 goto qc24_target_busy;
1015
1016 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1017 if (!sp)
1018 goto qc24_host_busy;
1019
1020 sp->u.scmd.cmd = cmd;
1021 sp->type = SRB_SCSI_CMD;
1022 atomic_set(&sp->ref_count, 1);
1023 CMD_SP(cmd) = (void *)sp;
1024 sp->free = qla2xxx_qpair_sp_free_dma;
1025 sp->done = qla2xxx_qpair_sp_compl;
1026 sp->qpair = qpair;
1027
1028 rval = ha->isp_ops->start_scsi_mq(sp);
1029 if (rval != QLA_SUCCESS) {
1030 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1031 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1032 if (rval == QLA_INTERFACE_ERROR)
1033 goto qc24_fail_command;
1034 goto qc24_host_busy_free_sp;
1035 }
1036
1037 return 0;
1038
1039qc24_host_busy_free_sp:
f3caa990 1040 sp->free(sp);
d7459527
MH		 1041
1042qc24_host_busy:
1043 return SCSI_MLQUEUE_HOST_BUSY;
1044
1045qc24_target_busy:
1046 return SCSI_MLQUEUE_TARGET_BUSY;
1047
1048qc24_fail_command:
1049 cmd->scsi_done(cmd);
1050
1051 return 0;
1052}
1053
1da177e4
LT		 1054/*
1055 * qla2x00_eh_wait_on_command
1056 * Waits for the command to be returned by the Firmware for some
1057 * max time.
1058 *
1059 * Input:
1da177e4 1060 * cmd = Scsi Command to wait on.
1da177e4
LT		 1061 *
1062 * Return:
1063 * Not Found : 0
1064 * Found : 1
1065 */
1066static int
e315cd28 1067qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1068{
fe74c71f 1069#define ABORT_POLLING_PERIOD 1000
478c3b03 1070#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1071 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1072 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1073 struct qla_hw_data *ha = vha->hw;
f4f051eb 1074 int ret = QLA_SUCCESS;
1da177e4 1075
85880801 1076 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1077 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1078 "Return:eh_wait.\n");
85880801
AV		 1079 return ret;
1080 }
1081
d970432c 1082 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1083 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1084 }
1085 if (CMD_SP(cmd))
1086 ret = QLA_FUNCTION_FAILED;
1da177e4 1087
f4f051eb 1088 return ret;
1da177e4
LT		 1089}
1090
1091/*
1092 * qla2x00_wait_for_hba_online
fa2a1ce5 1093 * Wait till the HBA is online after going through
1da177e4
LT		 1094 * <= MAX_RETRIES_OF_ISP_ABORT or
1095 * finally HBA is disabled ie marked offline
1096 *
1097 * Input:
1098 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1099 *
1100 * Note:
1da177e4
LT		 1101 * Does context switching-Release SPIN_LOCK
1102 * (if any) before calling this routine.
1103 *
1104 * Return:
1105 * Success (Adapter is online) : 0
1106 * Failed (Adapter is offline/disabled) : 1
1107 */
854165f4 1108int
e315cd28 1109qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1110{
fca29703
AV		 1111 int return_status;
1112 unsigned long wait_online;
e315cd28
AC		 1113 struct qla_hw_data *ha = vha->hw;
1114 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1115
fa2a1ce5 1116 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1117 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1118 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1119 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1120 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1121
1122 msleep(1000);
1123 }
e315cd28 1124 if (base_vha->flags.online)
fa2a1ce5 1125 return_status = QLA_SUCCESS;
1da177e4
LT		 1126 else
1127 return_status = QLA_FUNCTION_FAILED;
1128
1da177e4
LT		 1129 return (return_status);
1130}
1131
726b8548
QT		 1132static inline int test_fcport_count(scsi_qla_host_t *vha)
1133{
1134 struct qla_hw_data *ha = vha->hw;
1135 unsigned long flags;
1136 int res;
1137
1138 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1139 ql_dbg(ql_dbg_init, vha, 0x00ec,
1140 "tgt %p, fcport_count=%d\n",
1141 vha, vha->fcport_count);
726b8548
QT		 1142 res = (vha->fcport_count == 0);
1143 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1144
1145 return res;
1146}
1147
1148/*
1149 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1150 * it has dependency on UNLOADING flag to stop device discovery
1151 */
efa93f48 1152void
726b8548
QT		 1153qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1154{
1155 qla2x00_mark_all_devices_lost(vha, 0);
1156
b85e0957 1157 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1158}
1159
86fbee86 1160/*
638a1a01
SC		 1161 * qla2x00_wait_for_hba_ready
1162 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1163 *
1164 * Input:
1165 * ha - pointer to host adapter structure
1166 *
1167 * Note:
1168 * Does context switching-Release SPIN_LOCK
1169 * (if any) before calling this routine.
1170 *
86fbee86 1171 */
638a1a01
SC		 1172static void
1173qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1174{
86fbee86 1175 struct qla_hw_data *ha = vha->hw;
783e0dc4 1176 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1177
1d483901
DC		 1178 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1179 ha->flags.mbox_busy) ||
1180 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1181 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1182 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1183 break;
86fbee86 1184 msleep(1000);
783e0dc4 1185 }
86fbee86
LC		 1186}
1187
2533cf67
LC		 1188int
1189qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1190{
1191 int return_status;
1192 unsigned long wait_reset;
1193 struct qla_hw_data *ha = vha->hw;
1194 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1195
1196 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1197 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1198 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1199 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1200 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1201
1202 msleep(1000);
1203
1204 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1205 ha->flags.chip_reset_done)
1206 break;
1207 }
1208 if (ha->flags.chip_reset_done)
1209 return_status = QLA_SUCCESS;
1210 else
1211 return_status = QLA_FUNCTION_FAILED;
1212
1213 return return_status;
1214}
1215
083a469d
GM		 1216static void
1217sp_get(struct srb *sp)
1218{
1219 atomic_inc(&sp->ref_count);
1220}
1221
a465537a
SC		 1222#define ISP_REG_DISCONNECT 0xffffffffU
1223/**************************************************************************
1224* qla2x00_isp_reg_stat
1225*
1226* Description:
1227* Read the host status register of ISP before aborting the command.
1228*
1229* Input:
1230* ha = pointer to host adapter structure.
1231*
1232*
1233* Returns:
1234* Either true or false.
1235*
1236* Note: Return true if there is register disconnect.
1237**************************************************************************/
1238static inline
1239uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1240{
1241 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1242 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1243
bf6061b1
SC		 1244 if (IS_P3P_TYPE(ha))
1245 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1246 else
1247 return ((RD_REG_DWORD(&reg->host_status)) ==
1248 ISP_REG_DISCONNECT);
a465537a
SC		 1249}
1250
1da177e4
LT		 1251/**************************************************************************
1252* qla2xxx_eh_abort
1253*
1254* Description:
1255* The abort function will abort the specified command.
1256*
1257* Input:
1258* cmd = Linux SCSI command packet to be aborted.
1259*
1260* Returns:
1261* Either SUCCESS or FAILED.
1262*
1263* Note:
2ea00202 1264* Only return FAILED if command not returned by firmware.
1da177e4 1265**************************************************************************/
e5f82ab8 1266static int
1da177e4
LT		 1267qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1268{
e315cd28 1269 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1270 srb_t *sp;
4e98d3b8 1271 int ret;
9cb78c16
HR		 1272 unsigned int id;
1273 uint64_t lun;
18e144d3 1274 unsigned long flags;
f934c9d0 1275 int rval, wait = 0;
e315cd28 1276 struct qla_hw_data *ha = vha->hw;
1da177e4 1277
a465537a
SC		 1278 if (qla2x00_isp_reg_stat(ha)) {
1279 ql_log(ql_log_info, vha, 0x8042,
1280 "PCI/Register disconnect, exiting.\n");
1281 return FAILED;
1282 }
f4f051eb 1283 if (!CMD_SP(cmd))
2ea00202 1284 return SUCCESS;
1da177e4 1285
4e98d3b8
AV		 1286 ret = fc_block_scsi_eh(cmd);
1287 if (ret != 0)
1288 return ret;
1289 ret = SUCCESS;
1290
f4f051eb
AV		 1291 id = cmd->device->id;
1292 lun = cmd->device->lun;
1da177e4 1293
e315cd28 1294 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1295 sp = (srb_t *) CMD_SP(cmd);
1296 if (!sp) {
1297 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1298 return SUCCESS;
1299 }
1da177e4 1300
7c3df132 1301 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1302 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1303 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1304
170babc3
MC		 1305 /* Get a reference to the sp and drop the lock.*/
1306 sp_get(sp);
083a469d 1307
e315cd28 1308 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1309 rval = ha->isp_ops->abort_command(sp);
1310 if (rval) {
96219424 1311 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1312 ret = SUCCESS;
96219424 1313 else
f934c9d0
CD		 1314 ret = FAILED;
1315
7c3df132 1316 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1317 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1318 } else {
7c3df132 1319 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1320 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1321 wait = 1;
1322 }
75942064
SK		 1323
1324 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1325 sp->done(sp, 0);
75942064 1326 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1327
bc91ade9
CD		 1328 /* Did the command return during mailbox execution? */
1329 if (ret == FAILED && !CMD_SP(cmd))
1330 ret = SUCCESS;
1331
f4f051eb 1332 /* Wait for the command to be returned. */
2ea00202 1333 if (wait) {
e315cd28 1334 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1335 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1336 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1337 ret = FAILED;
f4f051eb 1338 }
1da177e4 1339 }
1da177e4 1340
7c3df132 1341 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1342 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1343 vha->host_no, id, lun, wait, ret);
1da177e4 1344
f4f051eb
AV		 1345 return ret;
1346}
1da177e4 1347
4d78c973 1348int
e315cd28 1349qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1350 uint64_t l, enum nexus_wait_type type)
f4f051eb 1351{
17d98630 1352 int cnt, match, status;
18e144d3 1353 unsigned long flags;
e315cd28 1354 struct qla_hw_data *ha = vha->hw;
73208dfd 1355 struct req_que *req;
4d78c973 1356 srb_t *sp;
9ba56b95 1357 struct scsi_cmnd *cmd;
1da177e4 1358
523ec773 1359 status = QLA_SUCCESS;
17d98630 1360
e315cd28 1361 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1362 req = vha->req;
17d98630 1363 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1364 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1365 sp = req->outstanding_cmds[cnt];
1366 if (!sp)
523ec773 1367 continue;
9ba56b95 1368 if (sp->type != SRB_SCSI_CMD)
cf53b069 1369 continue;
25ff6af1 1370 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1371 continue;
1372 match = 0;
9ba56b95 1373 cmd = GET_CMD_SP(sp);
17d98630
AC		 1374 switch (type) {
1375 case WAIT_HOST:
1376 match = 1;
1377 break;
1378 case WAIT_TARGET:
9ba56b95 1379 match = cmd->device->id == t;
17d98630
AC		 1380 break;
1381 case WAIT_LUN:
9ba56b95
GM		 1382 match = (cmd->device->id == t &&
1383 cmd->device->lun == l);
17d98630 1384 break;
73208dfd 1385 }
17d98630
AC		 1386 if (!match)
1387 continue;
1388
1389 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1390 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1391 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1392 }
e315cd28 1393 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1394
1395 return status;
1da177e4
LT		 1396}
1397
523ec773
AV		 1398static char *reset_errors[] = {
1399 "HBA not online",
1400 "HBA not ready",
1401 "Task management failed",
1402 "Waiting for command completions",
1403};
1da177e4 1404
e5f82ab8 1405static int
523ec773 1406__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1407 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1408{
e315cd28 1409 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1410 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1411 int err;
1da177e4 1412
7c3df132 1413 if (!fcport) {
523ec773 1414 return FAILED;
7c3df132 1415 }
1da177e4 1416
4e98d3b8
AV		 1417 err = fc_block_scsi_eh(cmd);
1418 if (err != 0)
1419 return err;
1420
7c3df132 1421 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1422 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1423 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1424
523ec773 1425 err = 0;
7c3df132
SK		 1426 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1427 ql_log(ql_log_warn, vha, 0x800a,
1428 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1429 goto eh_reset_failed;
7c3df132 1430 }
523ec773 1431 err = 2;
2afa19a9 1432 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1433 != QLA_SUCCESS) {
1434 ql_log(ql_log_warn, vha, 0x800c,
1435 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1436 goto eh_reset_failed;
7c3df132 1437 }
523ec773 1438 err = 3;
e315cd28 1439 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1440 cmd->device->lun, type) != QLA_SUCCESS) {
1441 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1442 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1443 goto eh_reset_failed;
7c3df132 1444 }
523ec773 1445
7c3df132 1446 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1447 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1448 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1449
1450 return SUCCESS;
1451
4d78c973 1452eh_reset_failed:
7c3df132 1453 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1454 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1455 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1456 cmd);
523ec773
AV		 1457 return FAILED;
1458}
1da177e4 1459
523ec773
AV		 1460static int
1461qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1462{
e315cd28
AC		 1463 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1464 struct qla_hw_data *ha = vha->hw;
1da177e4 1465
a465537a
SC		 1466 if (qla2x00_isp_reg_stat(ha)) {
1467 ql_log(ql_log_info, vha, 0x803e,
1468 "PCI/Register disconnect, exiting.\n");
1469 return FAILED;
1470 }
1471
523ec773
AV		 1472 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1473 ha->isp_ops->lun_reset);
1da177e4
LT		 1474}
1475
1da177e4 1476static int
523ec773 1477qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1478{
e315cd28
AC		 1479 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1480 struct qla_hw_data *ha = vha->hw;
1da177e4 1481
a465537a
SC		 1482 if (qla2x00_isp_reg_stat(ha)) {
1483 ql_log(ql_log_info, vha, 0x803f,
1484 "PCI/Register disconnect, exiting.\n");
1485 return FAILED;
1486 }
1487
523ec773
AV		 1488 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1489 ha->isp_ops->target_reset);
1da177e4
LT		 1490}
1491
1da177e4
LT		 1492/**************************************************************************
1493* qla2xxx_eh_bus_reset
1494*
1495* Description:
1496* The bus reset function will reset the bus and abort any executing
1497* commands.
1498*
1499* Input:
1500* cmd = Linux SCSI command packet of the command that cause the
1501* bus reset.
1502*
1503* Returns:
1504* SUCCESS/FAILURE (defined as macro in scsi.h).
1505*
1506**************************************************************************/
e5f82ab8 1507static int
1da177e4
LT		 1508qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1509{
e315cd28 1510 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1511 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1512 int ret = FAILED;
9cb78c16
HR		 1513 unsigned int id;
1514 uint64_t lun;
a465537a
SC		 1515 struct qla_hw_data *ha = vha->hw;
1516
1517 if (qla2x00_isp_reg_stat(ha)) {
1518 ql_log(ql_log_info, vha, 0x8040,
1519 "PCI/Register disconnect, exiting.\n");
1520 return FAILED;
1521 }
f4f051eb 1522
f4f051eb
AV		 1523 id = cmd->device->id;
1524 lun = cmd->device->lun;
1da177e4 1525
7c3df132 1526 if (!fcport) {
f4f051eb 1527 return ret;
7c3df132 1528 }
1da177e4 1529
4e98d3b8
AV		 1530 ret = fc_block_scsi_eh(cmd);
1531 if (ret != 0)
1532 return ret;
1533 ret = FAILED;
1534
7c3df132 1535 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1536 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1537
e315cd28 1538 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1539 ql_log(ql_log_fatal, vha, 0x8013,
1540 "Wait for hba online failed board disabled.\n");
f4f051eb 1541 goto eh_bus_reset_done;
1da177e4
LT		 1542 }
1543
ad537689
SK		 1544 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1545 ret = SUCCESS;
1546
f4f051eb
AV		 1547 if (ret == FAILED)
1548 goto eh_bus_reset_done;
1da177e4 1549
9a41a62b 1550 /* Flush outstanding commands. */
4d78c973 1551 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1552 QLA_SUCCESS) {
1553 ql_log(ql_log_warn, vha, 0x8014,
1554 "Wait for pending commands failed.\n");
9a41a62b 1555 ret = FAILED;
7c3df132 1556 }
1da177e4 1557
f4f051eb 1558eh_bus_reset_done:
7c3df132 1559 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1560 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1561 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1562
f4f051eb 1563 return ret;
1da177e4
LT		 1564}
1565
1566/**************************************************************************
1567* qla2xxx_eh_host_reset
1568*
1569* Description:
1570* The reset function will reset the Adapter.
1571*
1572* Input:
1573* cmd = Linux SCSI command packet of the command that cause the
1574* adapter reset.
1575*
1576* Returns:
1577* Either SUCCESS or FAILED.
1578*
1579* Note:
1580**************************************************************************/
e5f82ab8 1581static int
1da177e4
LT		 1582qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1583{
e315cd28 1584 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1585 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1586 int ret = FAILED;
9cb78c16
HR		 1587 unsigned int id;
1588 uint64_t lun;
e315cd28 1589 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1590
a465537a
SC		 1591 if (qla2x00_isp_reg_stat(ha)) {
1592 ql_log(ql_log_info, vha, 0x8041,
1593 "PCI/Register disconnect, exiting.\n");
1594 schedule_work(&ha->board_disable);
1595 return SUCCESS;
1596 }
1597
f4f051eb
AV		 1598 id = cmd->device->id;
1599 lun = cmd->device->lun;
f4f051eb 1600
7c3df132 1601 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1602 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1603
63ee7072
CD		 1604 /*
1605 * No point in issuing another reset if one is active. Also do not
1606 * attempt a reset if we are updating flash.
1607 */
1608 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1609 goto eh_host_reset_lock;
1da177e4 1610
e315cd28
AC		 1611 if (vha != base_vha) {
1612 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1613 goto eh_host_reset_lock;
e315cd28 1614 } else {
7ec0effd 1615 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1616 if (!qla82xx_fcoe_ctx_reset(vha)) {
1617 /* Ctx reset success */
1618 ret = SUCCESS;
1619 goto eh_host_reset_lock;
1620 }
1621 /* fall thru if ctx reset failed */
1622 }
68ca949c
AC		 1623 if (ha->wq)
1624 flush_workqueue(ha->wq);
1625
e315cd28 1626 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1627 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1628 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1629 /* failed. schedule dpc to try */
1630 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1631
7c3df132
SK		 1632 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1633 ql_log(ql_log_warn, vha, 0x802a,
1634 "wait for hba online failed.\n");
e315cd28 1635 goto eh_host_reset_lock;
7c3df132 1636 }
e315cd28
AC		 1637 }
1638 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1639 }
1da177e4 1640
e315cd28 1641 /* Waiting for command to be returned to OS.*/
4d78c973 1642 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1643 QLA_SUCCESS)
f4f051eb 1644 ret = SUCCESS;
1da177e4 1645
f4f051eb 1646eh_host_reset_lock:
cfb0919c 1647 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1648 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1649 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1650
f4f051eb
AV		 1651 return ret;
1652}
1da177e4
LT		 1653
1654/*
1655* qla2x00_loop_reset
1656* Issue loop reset.
1657*
1658* Input:
1659* ha = adapter block pointer.
1660*
1661* Returns:
1662* 0 = success
1663*/
a4722cf2 1664int
e315cd28 1665qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1666{
0c8c39af 1667 int ret;
bdf79621 1668 struct fc_port *fcport;
e315cd28 1669 struct qla_hw_data *ha = vha->hw;
1da177e4 1670
5854771e
AB		 1671 if (IS_QLAFX00(ha)) {
1672 return qlafx00_loop_reset(vha);
1673 }
1674
f4c496c1 1675 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1676 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1677 if (fcport->port_type != FCT_TARGET)
1678 continue;
1679
1680 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1681 if (ret != QLA_SUCCESS) {
7c3df132 1682 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1683 "Bus Reset failed: Reset=%d "
7c3df132 1684 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1685 }
1686 }
1687 }
1688
8ae6d9c7 1689
6246b8a1 1690 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1691 atomic_set(&vha->loop_state, LOOP_DOWN);
1692 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1693 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1694 ret = qla2x00_full_login_lip(vha);
0c8c39af 1695 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1696 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1697 "full_login_lip=%d.\n", ret);
749af3d5 1698 }
0c8c39af
AV		 1699 }
1700
0d6e61bc 1701 if (ha->flags.enable_lip_reset) {
e315cd28 1702 ret = qla2x00_lip_reset(vha);
ad537689 1703 if (ret != QLA_SUCCESS)
7c3df132
SK		 1704 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1705 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1706 }
1707
1da177e4 1708 /* Issue marker command only when we are going to start the I/O */
e315cd28 1709 vha->marker_needed = 1;
1da177e4 1710
0c8c39af 1711 return QLA_SUCCESS;
1da177e4
LT		 1712}
1713
bbead493
QT		 1714static void
1715__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1716{
bbead493 1717 int cnt, status;
df4bf0bb
AV		 1718 unsigned long flags;
1719 srb_t *sp;
bbead493 1720 scsi_qla_host_t *vha = qp->vha;
e315cd28 1721 struct qla_hw_data *ha = vha->hw;
73208dfd 1722 struct req_que *req;
c5419e26
QT		 1723 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1724 struct qla_tgt_cmd *cmd;
1725 uint8_t trace = 0;
c0cb4496 1726
6a2cf8d3
BK		 1727 if (!ha->req_q_map)
1728 return;
bbead493
QT		 1729 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1730 req = qp->req;
1731 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1732 sp = req->outstanding_cmds[cnt];
1733 if (sp) {
1734 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1735 switch (sp->cmd_type) {
1736 case TYPE_SRB:
1737 if (sp->cmd_type == TYPE_SRB) {
1738 if (sp->type == SRB_NVME_CMD ||
1739 sp->type == SRB_NVME_LS) {
1740 sp_get(sp);
1741 spin_unlock_irqrestore
1742 (qp->qp_lock_ptr,
1743 flags);
1744 qla_nvme_abort(ha, sp, res);
1745 spin_lock_irqsave
1746 (qp->qp_lock_ptr,
1747 flags);
1748 } else if (GET_CMD_SP(sp) &&
1749 !ha->flags.eeh_busy &&
1750 (!test_bit(ABORT_ISP_ACTIVE,
1751 &vha->dpc_flags)) &&
1752 (sp->type == SRB_SCSI_CMD)) {
1753 /*
1754 * Don't abort commands in
1755 * adapter during EEH
1756 * recovery as it's not
1757 * accessible/responding.
1758 *
1759 * Get a reference to the sp
1760 * and drop the lock. The
1761 * reference ensures this
1762 * sp->done() call and not the
1763 * call in qla2xxx_eh_abort()
1764 * ends the SCSI command (with
1765 * result 'res').
1766 */
1767 sp_get(sp);
1768 spin_unlock_irqrestore
1769 (qp->qp_lock_ptr,
1770 flags);
1771 status = qla2xxx_eh_abort(
1772 GET_CMD_SP(sp));
1773 spin_lock_irqsave
1774 (qp->qp_lock_ptr,
1775 flags);
1776 /*
1777 * Get rid of extra reference
1778 * if immediate exit from
1779 * ql2xxx_eh_abort
1780 */
1781 if (status == FAILED &&
1782 (qla2x00_isp_reg_stat(ha)))
1783 atomic_dec(
1784 &sp->ref_count);
1785 }
1786 sp->done(sp, res);
1787 break;
1788 case TYPE_TGT_CMD:
1789 if (!vha->hw->tgt.tgt_ops ||
1790 !tgt || qla_ini_mode_enabled(vha)) {
1791 if (!trace)
1792 ql_dbg(ql_dbg_tgt_mgt,
1793 vha, 0xf003,
1794 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1795 vha->dpc_flags);
1796 continue;
1797 }
1798 cmd = (struct qla_tgt_cmd *)sp;
1799 qlt_abort_cmd_on_host_reset(cmd->vha,
1800 cmd);
1801 break;
1802 case TYPE_TGT_TMCMD:
bbead493 1803 /*
6b0431d6
QT		 1804 * Currently, only ABTS response gets on
1805 * the outstanding_cmds[]
bbead493 1806 */
6b0431d6
QT		 1807 ha->tgt.tgt_ops->free_mcmd(
1808 (struct qla_tgt_mgmt_cmd *)sp);
1809 break;
1810 default:
1811 break;
c733ab35 1812 }
73208dfd 1813 }
df4bf0bb
AV		 1814 }
1815 }
bbead493
QT		 1816 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1817}
1818
1819void
1820qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1821{
1822 int que;
1823 struct qla_hw_data *ha = vha->hw;
1824
1825 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1826
1827 for (que = 0; que < ha->max_qpairs; que++) {
1828 if (!ha->queue_pair_map[que])
1829 continue;
1830
1831 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1832 }
df4bf0bb
AV		 1833}
1834
f4f051eb
AV		 1835static int
1836qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1837{
bdf79621 1838 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1839
19a7b4ae 1840 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1841 return -ENXIO;
bdf79621 1842
19a7b4ae 1843 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1844
f4f051eb
AV		 1845 return 0;
1846}
1da177e4 1847
f4f051eb
AV		 1848static int
1849qla2xxx_slave_configure(struct scsi_device *sdev)
1850{
e315cd28 1851 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1852 struct req_que *req = vha->req;
8482e118 1853
9e522cd8
AE		 1854 if (IS_T10_PI_CAPABLE(vha->hw))
1855 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1856
db5ed4df 1857 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1858 return 0;
1859}
1da177e4 1860
f4f051eb
AV		 1861static void
1862qla2xxx_slave_destroy(struct scsi_device *sdev)
1863{
1864 sdev->hostdata = NULL;
1da177e4
LT		 1865}
1866
1867/**
1868 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1869 * @ha: HA context
1870 *
1871 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1872 * supported addressing method.
1873 */
1874static void
53303c42 1875qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1876{
7524f9b9 1877 /* Assume a 32bit DMA mask. */
1da177e4 1878 ha->flags.enable_64bit_addressing = 0;
1da177e4 1879
6a35528a 1880 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1881 /* Any upper-dword bits set? */
1882 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1883 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1884 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1885 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1886 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1887 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1888 return;
1da177e4 1889 }
1da177e4 1890 }
7524f9b9 1891
284901a9
YH		 1892 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1893 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1894}
1895
fd34f556 1896static void
e315cd28 1897qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1898{
1899 unsigned long flags = 0;
1900 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1901
1902 spin_lock_irqsave(&ha->hardware_lock, flags);
1903 ha->interrupts_on = 1;
1904 /* enable risc and host interrupts */
1905 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1906 RD_REG_WORD(&reg->ictrl);
1907 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1908
1909}
1910
1911static void
e315cd28 1912qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1913{
1914 unsigned long flags = 0;
1915 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1916
1917 spin_lock_irqsave(&ha->hardware_lock, flags);
1918 ha->interrupts_on = 0;
1919 /* disable risc and host interrupts */
1920 WRT_REG_WORD(&reg->ictrl, 0);
1921 RD_REG_WORD(&reg->ictrl);
1922 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1923}
1924
1925static void
e315cd28 1926qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1927{
1928 unsigned long flags = 0;
1929 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1930
1931 spin_lock_irqsave(&ha->hardware_lock, flags);
1932 ha->interrupts_on = 1;
1933 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1934 RD_REG_DWORD(&reg->ictrl);
1935 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1936}
1937
1938static void
e315cd28 1939qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1940{
1941 unsigned long flags = 0;
1942 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1943
124f85e6
AV		 1944 if (IS_NOPOLLING_TYPE(ha))
1945 return;
fd34f556
AV		 1946 spin_lock_irqsave(&ha->hardware_lock, flags);
1947 ha->interrupts_on = 0;
1948 WRT_REG_DWORD(&reg->ictrl, 0);
1949 RD_REG_DWORD(&reg->ictrl);
1950 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1951}
1952
706f457d
GM		 1953static int
1954qla2x00_iospace_config(struct qla_hw_data *ha)
1955{
1956 resource_size_t pio;
1957 uint16_t msix;
706f457d 1958
706f457d
GM		 1959 if (pci_request_selected_regions(ha->pdev, ha->bars,
1960 QLA2XXX_DRIVER_NAME)) {
1961 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1962 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1963 pci_name(ha->pdev));
1964 goto iospace_error_exit;
1965 }
1966 if (!(ha->bars & 1))
1967 goto skip_pio;
1968
1969 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1970 pio = pci_resource_start(ha->pdev, 0);
1971 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1972 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1973 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1974 "Invalid pci I/O region size (%s).\n",
1975 pci_name(ha->pdev));
1976 pio = 0;
1977 }
1978 } else {
1979 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1980 "Region #0 no a PIO resource (%s).\n",
1981 pci_name(ha->pdev));
1982 pio = 0;
1983 }
1984 ha->pio_address = pio;
1985 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1986 "PIO address=%llu.\n",
1987 (unsigned long long)ha->pio_address);
1988
1989skip_pio:
1990 /* Use MMIO operations for all accesses. */
1991 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1992 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1993 "Region #1 not an MMIO resource (%s), aborting.\n",
1994 pci_name(ha->pdev));
1995 goto iospace_error_exit;
1996 }
1997 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1998 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1999 "Invalid PCI mem region size (%s), aborting.\n",
2000 pci_name(ha->pdev));
2001 goto iospace_error_exit;
2002 }
2003
2004 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2005 if (!ha->iobase) {
2006 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2007 "Cannot remap MMIO (%s), aborting.\n",
2008 pci_name(ha->pdev));
2009 goto iospace_error_exit;
2010 }
2011
2012 /* Determine queue resources */
2013 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2014 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 2015 if (!ql2xmqsupport || !ql2xnvmeenable ||
2016 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 2017 goto mqiobase_exit;
2018
2019 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2020 pci_resource_len(ha->pdev, 3));
2021 if (ha->mqiobase) {
2022 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2023 "MQIO Base=%p.\n", ha->mqiobase);
2024 /* Read MSIX vector size of the board */
2025 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2026 ha->msix_count = msix + 1;
706f457d 2027 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2028 /* MB interrupt uses 1 vector */
2029 ha->max_req_queues = ha->msix_count - 1;
2030 ha->max_rsp_queues = ha->max_req_queues;
2031 /* Queue pairs is the max value minus the base queue pair */
2032 ha->max_qpairs = ha->max_rsp_queues - 1;
2033 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2034 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2035
706f457d 2036 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2037 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2038 } else
2039 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2040 "BAR 3 not enabled.\n");
2041
2042mqiobase_exit:
706f457d 2043 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2044 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2045 return (0);
2046
2047iospace_error_exit:
2048 return (-ENOMEM);
2049}
2050
2051
6246b8a1
GM		 2052static int
2053qla83xx_iospace_config(struct qla_hw_data *ha)
2054{
2055 uint16_t msix;
6246b8a1
GM		 2056
2057 if (pci_request_selected_regions(ha->pdev, ha->bars,
2058 QLA2XXX_DRIVER_NAME)) {
2059 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2060 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2061 pci_name(ha->pdev));
2062
2063 goto iospace_error_exit;
2064 }
2065
2066 /* Use MMIO operations for all accesses. */
2067 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2068 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2069 "Invalid pci I/O region size (%s).\n",
2070 pci_name(ha->pdev));
2071 goto iospace_error_exit;
2072 }
2073 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2074 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2075 "Invalid PCI mem region size (%s), aborting\n",
2076 pci_name(ha->pdev));
2077 goto iospace_error_exit;
2078 }
2079
2080 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2081 if (!ha->iobase) {
2082 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2083 "Cannot remap MMIO (%s), aborting.\n",
2084 pci_name(ha->pdev));
2085 goto iospace_error_exit;
2086 }
2087
2088 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2089 /* 83XX 26XX always use MQ type access for queues
2090 * - mbar 2, a.k.a region 4 */
2091 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2092 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2093 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2094 pci_resource_len(ha->pdev, 4));
2095
2096 if (!ha->mqiobase) {
2097 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2098 "BAR2/region4 not enabled\n");
2099 goto mqiobase_exit;
2100 }
2101
2102 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2103 pci_resource_len(ha->pdev, 2));
2104 if (ha->msixbase) {
2105 /* Read MSIX vector size of the board */
2106 pci_read_config_word(ha->pdev,
2107 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2108 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2109 /*
2110 * By default, driver uses at least two msix vectors
2111 * (default & rspq)
2112 */
c38d1baf 2113 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2114 /* MB interrupt uses 1 vector */
2115 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2116
2117 /* ATIOQ needs 1 vector. That's 1 less QPair */
2118 if (QLA_TGT_MODE_ENABLED())
2119 ha->max_req_queues--;
2120
d0d2c68b
MH		 2121 ha->max_rsp_queues = ha->max_req_queues;
2122
d7459527
MH		 2123 /* Queue pairs is the max value minus
2124 * the base queue pair */
2125 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2126 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2127 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2128 }
2129 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2130 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2131 } else
2132 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2133 "BAR 1 not enabled.\n");
2134
2135mqiobase_exit:
6246b8a1 2136 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2137 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2138 return 0;
2139
2140iospace_error_exit:
2141 return -ENOMEM;
2142}
2143
fd34f556
AV		 2144static struct isp_operations qla2100_isp_ops = {
2145 .pci_config = qla2100_pci_config,
2146 .reset_chip = qla2x00_reset_chip,
2147 .chip_diag = qla2x00_chip_diag,
2148 .config_rings = qla2x00_config_rings,
2149 .reset_adapter = qla2x00_reset_adapter,
2150 .nvram_config = qla2x00_nvram_config,
2151 .update_fw_options = qla2x00_update_fw_options,
2152 .load_risc = qla2x00_load_risc,
2153 .pci_info_str = qla2x00_pci_info_str,
2154 .fw_version_str = qla2x00_fw_version_str,
2155 .intr_handler = qla2100_intr_handler,
2156 .enable_intrs = qla2x00_enable_intrs,
2157 .disable_intrs = qla2x00_disable_intrs,
2158 .abort_command = qla2x00_abort_command,
523ec773
AV		 2159 .target_reset = qla2x00_abort_target,
2160 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2161 .fabric_login = qla2x00_login_fabric,
2162 .fabric_logout = qla2x00_fabric_logout,
2163 .calc_req_entries = qla2x00_calc_iocbs_32,
2164 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2165 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2166 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2167 .read_nvram = qla2x00_read_nvram_data,
2168 .write_nvram = qla2x00_write_nvram_data,
2169 .fw_dump = qla2100_fw_dump,
2170 .beacon_on = NULL,
2171 .beacon_off = NULL,
2172 .beacon_blink = NULL,
2173 .read_optrom = qla2x00_read_optrom_data,
2174 .write_optrom = qla2x00_write_optrom_data,
2175 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2176 .start_scsi = qla2x00_start_scsi,
d7459527 2177 .start_scsi_mq = NULL,
a9083016 2178 .abort_isp = qla2x00_abort_isp,
706f457d 2179 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2180 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2181};
2182
2183static struct isp_operations qla2300_isp_ops = {
2184 .pci_config = qla2300_pci_config,
2185 .reset_chip = qla2x00_reset_chip,
2186 .chip_diag = qla2x00_chip_diag,
2187 .config_rings = qla2x00_config_rings,
2188 .reset_adapter = qla2x00_reset_adapter,
2189 .nvram_config = qla2x00_nvram_config,
2190 .update_fw_options = qla2x00_update_fw_options,
2191 .load_risc = qla2x00_load_risc,
2192 .pci_info_str = qla2x00_pci_info_str,
2193 .fw_version_str = qla2x00_fw_version_str,
2194 .intr_handler = qla2300_intr_handler,
2195 .enable_intrs = qla2x00_enable_intrs,
2196 .disable_intrs = qla2x00_disable_intrs,
2197 .abort_command = qla2x00_abort_command,
523ec773
AV		 2198 .target_reset = qla2x00_abort_target,
2199 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2200 .fabric_login = qla2x00_login_fabric,
2201 .fabric_logout = qla2x00_fabric_logout,
2202 .calc_req_entries = qla2x00_calc_iocbs_32,
2203 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2204 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2205 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2206 .read_nvram = qla2x00_read_nvram_data,
2207 .write_nvram = qla2x00_write_nvram_data,
2208 .fw_dump = qla2300_fw_dump,
2209 .beacon_on = qla2x00_beacon_on,
2210 .beacon_off = qla2x00_beacon_off,
2211 .beacon_blink = qla2x00_beacon_blink,
2212 .read_optrom = qla2x00_read_optrom_data,
2213 .write_optrom = qla2x00_write_optrom_data,
2214 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2215 .start_scsi = qla2x00_start_scsi,
d7459527 2216 .start_scsi_mq = NULL,
a9083016 2217 .abort_isp = qla2x00_abort_isp,
7ec0effd 2218 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2219 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2220};
2221
2222static struct isp_operations qla24xx_isp_ops = {
2223 .pci_config = qla24xx_pci_config,
2224 .reset_chip = qla24xx_reset_chip,
2225 .chip_diag = qla24xx_chip_diag,
2226 .config_rings = qla24xx_config_rings,
2227 .reset_adapter = qla24xx_reset_adapter,
2228 .nvram_config = qla24xx_nvram_config,
2229 .update_fw_options = qla24xx_update_fw_options,
2230 .load_risc = qla24xx_load_risc,
2231 .pci_info_str = qla24xx_pci_info_str,
2232 .fw_version_str = qla24xx_fw_version_str,
2233 .intr_handler = qla24xx_intr_handler,
2234 .enable_intrs = qla24xx_enable_intrs,
2235 .disable_intrs = qla24xx_disable_intrs,
2236 .abort_command = qla24xx_abort_command,
523ec773
AV		 2237 .target_reset = qla24xx_abort_target,
2238 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2239 .fabric_login = qla24xx_login_fabric,
2240 .fabric_logout = qla24xx_fabric_logout,
2241 .calc_req_entries = NULL,
2242 .build_iocbs = NULL,
2243 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2244 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2245 .read_nvram = qla24xx_read_nvram_data,
2246 .write_nvram = qla24xx_write_nvram_data,
2247 .fw_dump = qla24xx_fw_dump,
2248 .beacon_on = qla24xx_beacon_on,
2249 .beacon_off = qla24xx_beacon_off,
2250 .beacon_blink = qla24xx_beacon_blink,
2251 .read_optrom = qla24xx_read_optrom_data,
2252 .write_optrom = qla24xx_write_optrom_data,
2253 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2254 .start_scsi = qla24xx_start_scsi,
d7459527 2255 .start_scsi_mq = NULL,
a9083016 2256 .abort_isp = qla2x00_abort_isp,
7ec0effd 2257 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2258 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2259};
2260
c3a2f0df
AV		 2261static struct isp_operations qla25xx_isp_ops = {
2262 .pci_config = qla25xx_pci_config,
2263 .reset_chip = qla24xx_reset_chip,
2264 .chip_diag = qla24xx_chip_diag,
2265 .config_rings = qla24xx_config_rings,
2266 .reset_adapter = qla24xx_reset_adapter,
2267 .nvram_config = qla24xx_nvram_config,
2268 .update_fw_options = qla24xx_update_fw_options,
2269 .load_risc = qla24xx_load_risc,
2270 .pci_info_str = qla24xx_pci_info_str,
2271 .fw_version_str = qla24xx_fw_version_str,
2272 .intr_handler = qla24xx_intr_handler,
2273 .enable_intrs = qla24xx_enable_intrs,
2274 .disable_intrs = qla24xx_disable_intrs,
2275 .abort_command = qla24xx_abort_command,
523ec773
AV		 2276 .target_reset = qla24xx_abort_target,
2277 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2278 .fabric_login = qla24xx_login_fabric,
2279 .fabric_logout = qla24xx_fabric_logout,
2280 .calc_req_entries = NULL,
2281 .build_iocbs = NULL,
2282 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2283 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2284 .read_nvram = qla25xx_read_nvram_data,
2285 .write_nvram = qla25xx_write_nvram_data,
2286 .fw_dump = qla25xx_fw_dump,
2287 .beacon_on = qla24xx_beacon_on,
2288 .beacon_off = qla24xx_beacon_off,
2289 .beacon_blink = qla24xx_beacon_blink,
338c9161 2290 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2291 .write_optrom = qla24xx_write_optrom_data,
2292 .get_flash_version = qla24xx_get_flash_version,
bad75002 2293 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2294 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2295 .abort_isp = qla2x00_abort_isp,
7ec0effd 2296 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2297 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2298};
2299
3a03eb79
AV		 2300static struct isp_operations qla81xx_isp_ops = {
2301 .pci_config = qla25xx_pci_config,
2302 .reset_chip = qla24xx_reset_chip,
2303 .chip_diag = qla24xx_chip_diag,
2304 .config_rings = qla24xx_config_rings,
2305 .reset_adapter = qla24xx_reset_adapter,
2306 .nvram_config = qla81xx_nvram_config,
2307 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2308 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2309 .pci_info_str = qla24xx_pci_info_str,
2310 .fw_version_str = qla24xx_fw_version_str,
2311 .intr_handler = qla24xx_intr_handler,
2312 .enable_intrs = qla24xx_enable_intrs,
2313 .disable_intrs = qla24xx_disable_intrs,
2314 .abort_command = qla24xx_abort_command,
2315 .target_reset = qla24xx_abort_target,
2316 .lun_reset = qla24xx_lun_reset,
2317 .fabric_login = qla24xx_login_fabric,
2318 .fabric_logout = qla24xx_fabric_logout,
2319 .calc_req_entries = NULL,
2320 .build_iocbs = NULL,
2321 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2322 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2323 .read_nvram = NULL,
2324 .write_nvram = NULL,
3a03eb79
AV		 2325 .fw_dump = qla81xx_fw_dump,
2326 .beacon_on = qla24xx_beacon_on,
2327 .beacon_off = qla24xx_beacon_off,
6246b8a1 2328 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2329 .read_optrom = qla25xx_read_optrom_data,
2330 .write_optrom = qla24xx_write_optrom_data,
2331 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2332 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2333 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2334 .abort_isp = qla2x00_abort_isp,
7ec0effd 2335 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2336 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2337};
2338
2339static struct isp_operations qla82xx_isp_ops = {
2340 .pci_config = qla82xx_pci_config,
2341 .reset_chip = qla82xx_reset_chip,
2342 .chip_diag = qla24xx_chip_diag,
2343 .config_rings = qla82xx_config_rings,
2344 .reset_adapter = qla24xx_reset_adapter,
2345 .nvram_config = qla81xx_nvram_config,
2346 .update_fw_options = qla24xx_update_fw_options,
2347 .load_risc = qla82xx_load_risc,
9d55ca66 2348 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2349 .fw_version_str = qla24xx_fw_version_str,
2350 .intr_handler = qla82xx_intr_handler,
2351 .enable_intrs = qla82xx_enable_intrs,
2352 .disable_intrs = qla82xx_disable_intrs,
2353 .abort_command = qla24xx_abort_command,
2354 .target_reset = qla24xx_abort_target,
2355 .lun_reset = qla24xx_lun_reset,
2356 .fabric_login = qla24xx_login_fabric,
2357 .fabric_logout = qla24xx_fabric_logout,
2358 .calc_req_entries = NULL,
2359 .build_iocbs = NULL,
2360 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2361 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2362 .read_nvram = qla24xx_read_nvram_data,
2363 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2364 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2365 .beacon_on = qla82xx_beacon_on,
2366 .beacon_off = qla82xx_beacon_off,
2367 .beacon_blink = NULL,
a9083016
GM		 2368 .read_optrom = qla82xx_read_optrom_data,
2369 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2370 .get_flash_version = qla82xx_get_flash_version,
a9083016 2371 .start_scsi = qla82xx_start_scsi,
d7459527 2372 .start_scsi_mq = NULL,
a9083016 2373 .abort_isp = qla82xx_abort_isp,
706f457d 2374 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2375 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2376};
2377
7ec0effd
AD		 2378static struct isp_operations qla8044_isp_ops = {
2379 .pci_config = qla82xx_pci_config,
2380 .reset_chip = qla82xx_reset_chip,
2381 .chip_diag = qla24xx_chip_diag,
2382 .config_rings = qla82xx_config_rings,
2383 .reset_adapter = qla24xx_reset_adapter,
2384 .nvram_config = qla81xx_nvram_config,
2385 .update_fw_options = qla24xx_update_fw_options,
2386 .load_risc = qla82xx_load_risc,
2387 .pci_info_str = qla24xx_pci_info_str,
2388 .fw_version_str = qla24xx_fw_version_str,
2389 .intr_handler = qla8044_intr_handler,
2390 .enable_intrs = qla82xx_enable_intrs,
2391 .disable_intrs = qla82xx_disable_intrs,
2392 .abort_command = qla24xx_abort_command,
2393 .target_reset = qla24xx_abort_target,
2394 .lun_reset = qla24xx_lun_reset,
2395 .fabric_login = qla24xx_login_fabric,
2396 .fabric_logout = qla24xx_fabric_logout,
2397 .calc_req_entries = NULL,
2398 .build_iocbs = NULL,
2399 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2400 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2401 .read_nvram = NULL,
2402 .write_nvram = NULL,
a1b23c5a 2403 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2404 .beacon_on = qla82xx_beacon_on,
2405 .beacon_off = qla82xx_beacon_off,
2406 .beacon_blink = NULL,
888e639d 2407 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2408 .write_optrom = qla8044_write_optrom_data,
2409 .get_flash_version = qla82xx_get_flash_version,
2410 .start_scsi = qla82xx_start_scsi,
d7459527 2411 .start_scsi_mq = NULL,
7ec0effd
AD		 2412 .abort_isp = qla8044_abort_isp,
2413 .iospace_config = qla82xx_iospace_config,
2414 .initialize_adapter = qla2x00_initialize_adapter,
2415};
2416
6246b8a1
GM		 2417static struct isp_operations qla83xx_isp_ops = {
2418 .pci_config = qla25xx_pci_config,
2419 .reset_chip = qla24xx_reset_chip,
2420 .chip_diag = qla24xx_chip_diag,
2421 .config_rings = qla24xx_config_rings,
2422 .reset_adapter = qla24xx_reset_adapter,
2423 .nvram_config = qla81xx_nvram_config,
2424 .update_fw_options = qla81xx_update_fw_options,
2425 .load_risc = qla81xx_load_risc,
2426 .pci_info_str = qla24xx_pci_info_str,
2427 .fw_version_str = qla24xx_fw_version_str,
2428 .intr_handler = qla24xx_intr_handler,
2429 .enable_intrs = qla24xx_enable_intrs,
2430 .disable_intrs = qla24xx_disable_intrs,
2431 .abort_command = qla24xx_abort_command,
2432 .target_reset = qla24xx_abort_target,
2433 .lun_reset = qla24xx_lun_reset,
2434 .fabric_login = qla24xx_login_fabric,
2435 .fabric_logout = qla24xx_fabric_logout,
2436 .calc_req_entries = NULL,
2437 .build_iocbs = NULL,
2438 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2439 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2440 .read_nvram = NULL,
2441 .write_nvram = NULL,
2442 .fw_dump = qla83xx_fw_dump,
2443 .beacon_on = qla24xx_beacon_on,
2444 .beacon_off = qla24xx_beacon_off,
2445 .beacon_blink = qla83xx_beacon_blink,
2446 .read_optrom = qla25xx_read_optrom_data,
2447 .write_optrom = qla24xx_write_optrom_data,
2448 .get_flash_version = qla24xx_get_flash_version,
2449 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2450 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2451 .abort_isp = qla2x00_abort_isp,
2452 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2453 .initialize_adapter = qla2x00_initialize_adapter,
2454};
2455
2456static struct isp_operations qlafx00_isp_ops = {
2457 .pci_config = qlafx00_pci_config,
2458 .reset_chip = qlafx00_soft_reset,
2459 .chip_diag = qlafx00_chip_diag,
2460 .config_rings = qlafx00_config_rings,
2461 .reset_adapter = qlafx00_soft_reset,
2462 .nvram_config = NULL,
2463 .update_fw_options = NULL,
2464 .load_risc = NULL,
2465 .pci_info_str = qlafx00_pci_info_str,
2466 .fw_version_str = qlafx00_fw_version_str,
2467 .intr_handler = qlafx00_intr_handler,
2468 .enable_intrs = qlafx00_enable_intrs,
2469 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2470 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2471 .target_reset = qlafx00_abort_target,
2472 .lun_reset = qlafx00_lun_reset,
2473 .fabric_login = NULL,
2474 .fabric_logout = NULL,
2475 .calc_req_entries = NULL,
2476 .build_iocbs = NULL,
2477 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2478 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2479 .read_nvram = qla24xx_read_nvram_data,
2480 .write_nvram = qla24xx_write_nvram_data,
2481 .fw_dump = NULL,
2482 .beacon_on = qla24xx_beacon_on,
2483 .beacon_off = qla24xx_beacon_off,
2484 .beacon_blink = NULL,
2485 .read_optrom = qla24xx_read_optrom_data,
2486 .write_optrom = qla24xx_write_optrom_data,
2487 .get_flash_version = qla24xx_get_flash_version,
2488 .start_scsi = qlafx00_start_scsi,
d7459527 2489 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2490 .abort_isp = qlafx00_abort_isp,
2491 .iospace_config = qlafx00_iospace_config,
2492 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2493};
2494
f73cb695
CD		 2495static struct isp_operations qla27xx_isp_ops = {
2496 .pci_config = qla25xx_pci_config,
2497 .reset_chip = qla24xx_reset_chip,
2498 .chip_diag = qla24xx_chip_diag,
2499 .config_rings = qla24xx_config_rings,
2500 .reset_adapter = qla24xx_reset_adapter,
2501 .nvram_config = qla81xx_nvram_config,
2502 .update_fw_options = qla81xx_update_fw_options,
2503 .load_risc = qla81xx_load_risc,
2504 .pci_info_str = qla24xx_pci_info_str,
2505 .fw_version_str = qla24xx_fw_version_str,
2506 .intr_handler = qla24xx_intr_handler,
2507 .enable_intrs = qla24xx_enable_intrs,
2508 .disable_intrs = qla24xx_disable_intrs,
2509 .abort_command = qla24xx_abort_command,
2510 .target_reset = qla24xx_abort_target,
2511 .lun_reset = qla24xx_lun_reset,
2512 .fabric_login = qla24xx_login_fabric,
2513 .fabric_logout = qla24xx_fabric_logout,
2514 .calc_req_entries = NULL,
2515 .build_iocbs = NULL,
2516 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2517 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2518 .read_nvram = NULL,
2519 .write_nvram = NULL,
2520 .fw_dump = qla27xx_fwdump,
2521 .beacon_on = qla24xx_beacon_on,
2522 .beacon_off = qla24xx_beacon_off,
2523 .beacon_blink = qla83xx_beacon_blink,
2524 .read_optrom = qla25xx_read_optrom_data,
2525 .write_optrom = qla24xx_write_optrom_data,
2526 .get_flash_version = qla24xx_get_flash_version,
2527 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2528 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2529 .abort_isp = qla2x00_abort_isp,
2530 .iospace_config = qla83xx_iospace_config,
2531 .initialize_adapter = qla2x00_initialize_adapter,
2532};
2533
ea5b6382 2534static inline void
e315cd28 2535qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2536{
2537 ha->device_type = DT_EXTENDED_IDS;
2538 switch (ha->pdev->device) {
2539 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2540 ha->isp_type |= DT_ISP2100;
ea5b6382 2541 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2542 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2543 break;
2544 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2545 ha->isp_type |= DT_ISP2200;
ea5b6382 2546 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2547 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2548 break;
2549 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2550 ha->isp_type |= DT_ISP2300;
4a59f71d 2551 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2552 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2553 break;
2554 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2555 ha->isp_type |= DT_ISP2312;
4a59f71d 2556 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2557 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2558 break;
2559 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2560 ha->isp_type |= DT_ISP2322;
4a59f71d 2561 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2562 if (ha->pdev->subsystem_vendor == 0x1028 &&
2563 ha->pdev->subsystem_device == 0x0170)
2564 ha->device_type |= DT_OEM_001;
441d1072 2565 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2566 break;
2567 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2568 ha->isp_type |= DT_ISP6312;
441d1072 2569 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2570 break;
2571 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2572 ha->isp_type |= DT_ISP6322;
441d1072 2573 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2574 break;
2575 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2576 ha->isp_type |= DT_ISP2422;
4a59f71d 2577 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2578 ha->device_type |= DT_FWI2;
c76f2c01 2579 ha->device_type |= DT_IIDMA;
441d1072 2580 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2581 break;
2582 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2583 ha->isp_type |= DT_ISP2432;
4a59f71d 2584 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2585 ha->device_type |= DT_FWI2;
c76f2c01 2586 ha->device_type |= DT_IIDMA;
441d1072 2587 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2588 break;
4d4df193 2589 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2590 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2591 ha->device_type |= DT_ZIO_SUPPORTED;
2592 ha->device_type |= DT_FWI2;
2593 ha->device_type |= DT_IIDMA;
2594 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2595 break;
044cc6c8 2596 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2597 ha->isp_type |= DT_ISP5422;
e428924c 2598 ha->device_type |= DT_FWI2;
441d1072 2599 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2600 break;
044cc6c8 2601 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2602 ha->isp_type |= DT_ISP5432;
e428924c 2603 ha->device_type |= DT_FWI2;
441d1072 2604 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2605 break;
c3a2f0df 2606 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2607 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2608 ha->device_type |= DT_ZIO_SUPPORTED;
2609 ha->device_type |= DT_FWI2;
2610 ha->device_type |= DT_IIDMA;
441d1072 2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2612 break;
3a03eb79 2613 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2614 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2615 ha->device_type |= DT_ZIO_SUPPORTED;
2616 ha->device_type |= DT_FWI2;
2617 ha->device_type |= DT_IIDMA;
2618 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2619 break;
a9083016 2620 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2621 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2622 ha->device_type |= DT_ZIO_SUPPORTED;
2623 ha->device_type |= DT_FWI2;
2624 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2625 /* Initialize 82XX ISP flags */
2626 qla82xx_init_flags(ha);
2627 break;
7ec0effd 2628 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2629 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2630 ha->device_type |= DT_ZIO_SUPPORTED;
2631 ha->device_type |= DT_FWI2;
2632 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2633 /* Initialize 82XX ISP flags */
2634 qla82xx_init_flags(ha);
2635 break;
6246b8a1 2636 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2637 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2638 ha->device_type |= DT_ZIO_SUPPORTED;
2639 ha->device_type |= DT_FWI2;
2640 ha->device_type |= DT_IIDMA;
2641 ha->device_type |= DT_T10_PI;
2642 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2643 break;
2644 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2645 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2646 ha->device_type |= DT_ZIO_SUPPORTED;
2647 ha->device_type |= DT_FWI2;
2648 ha->device_type |= DT_IIDMA;
2649 ha->device_type |= DT_T10_PI;
2650 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2651 break;
8ae6d9c7 2652 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2653 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2654 break;
f73cb695 2655 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2656 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2657 ha->device_type |= DT_ZIO_SUPPORTED;
2658 ha->device_type |= DT_FWI2;
2659 ha->device_type |= DT_IIDMA;
8ce3f570 2660 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2661 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2662 break;
2c5bbbb2 2663 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2664 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2665 ha->device_type |= DT_ZIO_SUPPORTED;
2666 ha->device_type |= DT_FWI2;
2667 ha->device_type |= DT_IIDMA;
8ce3f570 2668 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2669 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2670 break;
2b48992f 2671 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2672 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2673 ha->device_type |= DT_ZIO_SUPPORTED;
2674 ha->device_type |= DT_FWI2;
2675 ha->device_type |= DT_IIDMA;
8ce3f570 2676 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2677 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2678 break;
ea5b6382 2679 }
e5b68a61 2680
a9083016 2681 if (IS_QLA82XX(ha))
43a9c38b 2682 ha->port_no = ha->portnum & 1;
f73cb695 2683 else {
a9083016
GM		 2684 /* Get adapter physical port no from interrupt pin register. */
2685 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2686 if (IS_QLA27XX(ha))
2687 ha->port_no--;
2688 else
2689 ha->port_no = !(ha->port_no & 1);
2690 }
a9083016 2691
7c3df132 2692 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2693 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2694 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2695}
2696
1e99e33a
AV		 2697static void
2698qla2xxx_scan_start(struct Scsi_Host *shost)
2699{
e315cd28 2700 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2701
cbc8eb67
AV		 2702 if (vha->hw->flags.running_gold_fw)
2703 return;
2704
e315cd28
AC		 2705 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2706 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2707 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2708 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2709}
2710
2711static int
2712qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2713{
e315cd28 2714 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2715
a5dd506e
BK		 2716 if (test_bit(UNLOADING, &vha->dpc_flags))
2717 return 1;
e315cd28 2718 if (!vha->host)
1e99e33a 2719 return 1;
e315cd28 2720 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2721 return 1;
2722
e315cd28 2723 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2724}
2725
ec7193e2
QT		 2726static void qla2x00_iocb_work_fn(struct work_struct *work)
2727{
2728 struct scsi_qla_host *vha = container_of(work,
2729 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2730 struct qla_hw_data *ha = vha->hw;
2731 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2732 int i = 20;
2733 unsigned long flags;
2734
2735 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2736 return;
ec7193e2 2737
9b3e0f4d 2738 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2739 qla2x00_do_work(vha);
9b3e0f4d 2740 i--;
ec7193e2 2741 }
9b3e0f4d
QT		 2742
2743 spin_lock_irqsave(&vha->work_lock, flags);
2744 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2745 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2746}
2747
1da177e4
LT		 2748/*
2749 * PCI driver interface
2750 */
6f039790 2751static int
7ee61397 2752qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2753{
a1541d5a 2754 int ret = -ENODEV;
1da177e4 2755 struct Scsi_Host *host;
e315cd28
AC		 2756 scsi_qla_host_t *base_vha = NULL;
2757 struct qla_hw_data *ha;
29856e28 2758 char pci_info[30];
7d613ac6 2759 char fw_str[30], wq_name[30];
5433383e 2760 struct scsi_host_template *sht;
642ef983 2761 int bars, mem_only = 0;
e315cd28 2762 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2763 struct req_que *req = NULL;
2764 struct rsp_que *rsp = NULL;
5601236b 2765 int i;
d7459527 2766
285d0321 2767 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2768 sht = &qla2xxx_driver_template;
5433383e 2769 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2770 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2771 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2772 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2773 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2774 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2775 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2776 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2777 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2778 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2779 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2780 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2781 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2782 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2783 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2784 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2785 mem_only = 1;
7c3df132
SK		 2786 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2787 "Mem only adapter.\n");
285d0321 2788 }
7c3df132
SK		 2789 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2790 "Bars=%d.\n", bars);
285d0321 2791
09483916
BH		 2792 if (mem_only) {
2793 if (pci_enable_device_mem(pdev))
ddff7ed4 2794 return ret;
09483916
BH		 2795 } else {
2796 if (pci_enable_device(pdev))
ddff7ed4 2797 return ret;
09483916 2798 }
285d0321 2799
0927678f
JB		 2800 /* This may fail but that's ok */
2801 pci_enable_pcie_error_reporting(pdev);
285d0321 2802
e315cd28
AC		 2803 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2804 if (!ha) {
7c3df132
SK		 2805 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2806 "Unable to allocate memory for ha.\n");
ddff7ed4 2807 goto disable_device;
1da177e4 2808 }
7c3df132
SK		 2809 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2810 "Memory allocated for ha=%p.\n", ha);
e315cd28 2811 ha->pdev = pdev;
33e79977
QT		 2812 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2813 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2814 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2815 spin_lock_init(&ha->tgt.atio_lock);
2816
deeae7a6 2817 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2818
2819 /* Clear our data area */
285d0321 2820 ha->bars = bars;
09483916 2821 ha->mem_only = mem_only;
df4bf0bb 2822 spin_lock_init(&ha->hardware_lock);
339aa70e 2823 spin_lock_init(&ha->vport_slock);
a9b6f722 2824 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2825 mutex_init(&ha->optrom_mutex);
1da177e4 2826
ea5b6382
AV		 2827 /* Set ISP-type information. */
2828 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2829
2830 /* Set EEH reset type to fundamental if required by hba */
95676112 2831 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2832 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2833 pdev->needs_freset = 1;
ca79cf66 2834
cba1e47f
CD		 2835 ha->prev_topology = 0;
2836 ha->init_cb_size = sizeof(init_cb_t);
2837 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2838 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2839 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2840 atomic_set(&ha->num_pend_mbx_stage1, 0);
2841 atomic_set(&ha->num_pend_mbx_stage2, 0);
2842 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2843 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2844 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2845
abbd8870 2846 /* Assign ISP specific operations. */
1da177e4 2847 if (IS_QLA2100(ha)) {
642ef983 2848 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2849 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2850 req_length = REQUEST_ENTRY_CNT_2100;
2851 rsp_length = RESPONSE_ENTRY_CNT_2100;
2852 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2853 ha->gid_list_info_size = 4;
3a03eb79
AV		 2854 ha->flash_conf_off = ~0;
2855 ha->flash_data_off = ~0;
2856 ha->nvram_conf_off = ~0;
2857 ha->nvram_data_off = ~0;
fd34f556 2858 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2859 } else if (IS_QLA2200(ha)) {
642ef983 2860 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2861 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2862 req_length = REQUEST_ENTRY_CNT_2200;
2863 rsp_length = RESPONSE_ENTRY_CNT_2100;
2864 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2865 ha->gid_list_info_size = 4;
3a03eb79
AV		 2866 ha->flash_conf_off = ~0;
2867 ha->flash_data_off = ~0;
2868 ha->nvram_conf_off = ~0;
2869 ha->nvram_data_off = ~0;
fd34f556 2870 ha->isp_ops = &qla2100_isp_ops;
fca29703 2871 } else if (IS_QLA23XX(ha)) {
642ef983 2872 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2873 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2874 req_length = REQUEST_ENTRY_CNT_2200;
2875 rsp_length = RESPONSE_ENTRY_CNT_2300;
2876 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2877 ha->gid_list_info_size = 6;
854165f4
AV		 2878 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2879 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2880 ha->flash_conf_off = ~0;
2881 ha->flash_data_off = ~0;
2882 ha->nvram_conf_off = ~0;
2883 ha->nvram_data_off = ~0;
fd34f556 2884 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2885 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2886 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2887 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2888 req_length = REQUEST_ENTRY_CNT_24XX;
2889 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2890 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2891 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2892 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2893 ha->gid_list_info_size = 8;
854165f4 2894 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2895 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2896 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2897 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2898 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2899 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2900 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2901 } else if (IS_QLA25XX(ha)) {
642ef983 2902 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2903 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2904 req_length = REQUEST_ENTRY_CNT_24XX;
2905 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2906 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2907 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2908 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2909 ha->gid_list_info_size = 8;
2910 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2911 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2912 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2913 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2914 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2915 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2916 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2917 } else if (IS_QLA81XX(ha)) {
642ef983 2918 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2919 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2920 req_length = REQUEST_ENTRY_CNT_24XX;
2921 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2922 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2923 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2924 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2925 ha->gid_list_info_size = 8;
2926 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2927 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2928 ha->isp_ops = &qla81xx_isp_ops;
2929 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2930 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2931 ha->nvram_conf_off = ~0;
2932 ha->nvram_data_off = ~0;
a9083016 2933 } else if (IS_QLA82XX(ha)) {
642ef983 2934 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2935 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2936 req_length = REQUEST_ENTRY_CNT_82XX;
2937 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2938 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2939 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2940 ha->gid_list_info_size = 8;
2941 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2942 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2943 ha->isp_ops = &qla82xx_isp_ops;
2944 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2945 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2946 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2947 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2948 } else if (IS_QLA8044(ha)) {
2949 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2950 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2951 req_length = REQUEST_ENTRY_CNT_82XX;
2952 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2953 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2954 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2955 ha->gid_list_info_size = 8;
2956 ha->optrom_size = OPTROM_SIZE_83XX;
2957 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2958 ha->isp_ops = &qla8044_isp_ops;
2959 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2960 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2961 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2962 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2963 } else if (IS_QLA83XX(ha)) {
7d613ac6 2964 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2965 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2966 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2967 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2968 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2969 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2970 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2971 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2972 ha->gid_list_info_size = 8;
2973 ha->optrom_size = OPTROM_SIZE_83XX;
2974 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2975 ha->isp_ops = &qla83xx_isp_ops;
2976 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2977 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2978 ha->nvram_conf_off = ~0;
2979 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2980 } else if (IS_QLAFX00(ha)) {
2981 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2982 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2983 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2984 req_length = REQUEST_ENTRY_CNT_FX00;
2985 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2986 ha->isp_ops = &qlafx00_isp_ops;
2987 ha->port_down_retry_count = 30; /* default value */
2988 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2989 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2990 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2991 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2992 ha->mr.host_info_resend = false;
2993 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2994 } else if (IS_QLA27XX(ha)) {
2995 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2996 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2997 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2998 req_length = REQUEST_ENTRY_CNT_83XX;
2999 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3000 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3001 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3002 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3003 ha->gid_list_info_size = 8;
3004 ha->optrom_size = OPTROM_SIZE_83XX;
3005 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3006 ha->isp_ops = &qla27xx_isp_ops;
3007 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3008 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3009 ha->nvram_conf_off = ~0;
3010 ha->nvram_data_off = ~0;
1da177e4 3011 }
6246b8a1 3012
7c3df132
SK		 3013 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3014 "mbx_count=%d, req_length=%d, "
3015 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3016 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3017 "max_fibre_devices=%d.\n",
7c3df132
SK		 3018 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3019 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3020 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3021 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3022 "isp_ops=%p, flash_conf_off=%d, "
3023 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3024 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3025 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3026
3027 /* Configure PCI I/O space */
3028 ret = ha->isp_ops->iospace_config(ha);
3029 if (ret)
0a63ad12 3030 goto iospace_config_failed;
706f457d
GM		 3031
3032 ql_log_pci(ql_log_info, pdev, 0x001d,
3033 "Found an ISP%04X irq %d iobase 0x%p.\n",
3034 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3035 mutex_init(&ha->vport_lock);
d7459527 3036 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3037 init_completion(&ha->mbx_cmd_comp);
3038 complete(&ha->mbx_cmd_comp);
3039 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3040 init_completion(&ha->dcbx_comp);
f356bef1 3041 init_completion(&ha->lb_portup_comp);
1da177e4 3042
2c3dfe3f 3043 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3044
53303c42 3045 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3046 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3047 "64 Bit addressing is %s.\n",
3048 ha->flags.enable_64bit_addressing ? "enable" :
3049 "disable");
73208dfd 3050 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3051 if (ret) {
7c3df132
SK		 3052 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3053 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3054
e315cd28
AC		 3055 goto probe_hw_failed;
3056 }
3057
73208dfd 3058 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3059 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3060 req->max_q_depth = ql2xmaxqdepth;
3061
e315cd28
AC		 3062
3063 base_vha = qla2x00_create_host(sht, ha);
3064 if (!base_vha) {
a1541d5a 3065 ret = -ENOMEM;
e315cd28 3066 goto probe_hw_failed;
1da177e4
LT		 3067 }
3068
e315cd28 3069 pci_set_drvdata(pdev, base_vha);
6b383979 3070 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3071
e315cd28 3072 host = base_vha->host;
2afa19a9 3073 base_vha->req = req;
73208dfd 3074 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3075 base_vha->mgmt_svr_loop_id =
3076 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3077 else
e315cd28
AC		 3078 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3079 base_vha->vp_idx;
58548cb5 3080
8ae6d9c7
GM		 3081 /* Setup fcport template structure. */
3082 ha->mr.fcport.vha = base_vha;
3083 ha->mr.fcport.port_type = FCT_UNKNOWN;
3084 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3085 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3086 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3087 ha->mr.fcport.scan_state = 1;
3088
58548cb5
GM		 3089 /* Set the SG table size based on ISP type */
3090 if (!IS_FWI2_CAPABLE(ha)) {
3091 if (IS_QLA2100(ha))
3092 host->sg_tablesize = 32;
3093 } else {
3094 if (!IS_QLA82XX(ha))
3095 host->sg_tablesize = QLA_SG_ALL;
3096 }
642ef983 3097 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3098 host->cmd_per_lun = 3;
3099 host->unique_id = host->host_no;
e02587d7 3100 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3101 host->max_cmd_len = 32;
3102 else
3103 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3104 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3105 /* Older HBAs support only 16-bit LUNs */
3106 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3107 ql2xmaxlun > 0xffff)
3108 host->max_lun = 0xffff;
3109 else
3110 host->max_lun = ql2xmaxlun;
e315cd28 3111 host->transportt = qla2xxx_transport_template;
9a069e19 3112 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3113
7c3df132
SK		 3114 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3115 "max_id=%d this_id=%d "
3116 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3117 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3118 host->this_id, host->cmd_per_lun, host->unique_id,
3119 host->max_cmd_len, host->max_channel, host->max_lun,
3120 host->transportt, sht->vendor_id);
3121
1010f21e
HM		 3122 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3123
d7459527
MH		 3124 /* Set up the irqs */
3125 ret = qla2x00_request_irqs(ha, rsp);
3126 if (ret)
6a2cf8d3 3127 goto probe_failed;
d7459527 3128
9a347ff4 3129 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3130 ret = qla2x00_alloc_queues(ha, req, rsp);
3131 if (ret) {
9a347ff4
CD		 3132 ql_log(ql_log_fatal, base_vha, 0x003d,
3133 "Failed to allocate memory for queue pointers..."
3134 "aborting.\n");
6a2cf8d3 3135 goto probe_failed;
9a347ff4
CD		 3136 }
3137
5601236b
MH		 3138 if (ha->mqenable && shost_use_blk_mq(host)) {
3139 /* number of hardware queues supported by blk/scsi-mq*/
3140 host->nr_hw_queues = ha->max_qpairs;
3141
3142 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3143 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3144 } else {
3145 if (ql2xnvmeenable) {
3146 host->nr_hw_queues = ha->max_qpairs;
3147 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3148 "FC-NVMe support is enabled, HW queues=%d\n",
3149 host->nr_hw_queues);
3150 } else {
3151 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3152 "blk/scsi-mq disabled.\n");
3153 }
3154 }
5601236b 3155
2d70c103 3156 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3157
90a86fc0
JC		 3158 pci_save_state(pdev);
3159
9a347ff4 3160 /* Assign back pointers */
2afa19a9
AC		 3161 rsp->req = req;
3162 req->rsp = rsp;
9a347ff4 3163
8ae6d9c7
GM		 3164 if (IS_QLAFX00(ha)) {
3165 ha->rsp_q_map[0] = rsp;
3166 ha->req_q_map[0] = req;
3167 set_bit(0, ha->req_qid_map);
3168 set_bit(0, ha->rsp_qid_map);
3169 }
3170
08029990
AV		 3171 /* FWI2-capable only. */
3172 req->req_q_in = &ha->iobase->isp24.req_q_in;
3173 req->req_q_out = &ha->iobase->isp24.req_q_out;
3174 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3175 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3176 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3177 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3178 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3179 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3180 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3181 }
3182
8ae6d9c7
GM		 3183 if (IS_QLAFX00(ha)) {
3184 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3185 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3186 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3187 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3188 }
3189
7ec0effd 3190 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3191 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3192 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3193 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3194 }
3195
7c3df132
SK		 3196 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3197 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3198 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3199 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3200 "req->req_q_in=%p req->req_q_out=%p "
3201 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3202 req->req_q_in, req->req_q_out,
3203 rsp->rsp_q_in, rsp->rsp_q_out);
3204 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3205 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3206 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3207 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3208 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3209 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3210
d48cc67c 3211 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3212
8ae6d9c7 3213 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3214 ql_log(ql_log_fatal, base_vha, 0x00d6,
3215 "Failed to initialize adapter - Adapter flags %x.\n",
3216 base_vha->device_flags);
1da177e4 3217
a9083016
GM		 3218 if (IS_QLA82XX(ha)) {
3219 qla82xx_idc_lock(ha);
3220 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3221 QLA8XXX_DEV_FAILED);
a9083016 3222 qla82xx_idc_unlock(ha);
7c3df132
SK		 3223 ql_log(ql_log_fatal, base_vha, 0x00d7,
3224 "HW State: FAILED.\n");
7ec0effd
AD		 3225 } else if (IS_QLA8044(ha)) {
3226 qla8044_idc_lock(ha);
3227 qla8044_wr_direct(base_vha,
3228 QLA8044_CRB_DEV_STATE_INDEX,
3229 QLA8XXX_DEV_FAILED);
3230 qla8044_idc_unlock(ha);
3231 ql_log(ql_log_fatal, base_vha, 0x0150,
3232 "HW State: FAILED.\n");
a9083016
GM		 3233 }
3234
a1541d5a 3235 ret = -ENODEV;
1da177e4
LT		 3236 goto probe_failed;
3237 }
3238
3b1bef64
CD		 3239 if (IS_QLAFX00(ha))
3240 host->can_queue = QLAFX00_MAX_CANQUEUE;
3241 else
3242 host->can_queue = req->num_outstanding_cmds - 10;
3243
3244 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3245 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3246 host->can_queue, base_vha->req,
3247 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3248
e326d22a
QT		 3249 if (ha->mqenable) {
3250 bool mq = false;
3251 bool startit = false;
e326d22a
QT		 3252
3253 if (QLA_TGT_MODE_ENABLED()) {
3254 mq = true;
3255 startit = false;
3256 }
3257
3258 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3259 shost_use_blk_mq(host)) {
3260 mq = true;
3261 startit = true;
3262 }
3263
3264 if (mq) {
3265 /* Create start of day qpairs for Block MQ */
5601236b 3266 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3267 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3268 }
3269 }
68ca949c 3270
cbc8eb67
AV		 3271 if (ha->flags.running_gold_fw)
3272 goto skip_dpc;
3273
1da177e4
LT		 3274 /*
3275 * Startup the kernel thread for this host adapter
3276 */
39a11240 3277 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3278 "%s_dpc", base_vha->host_str);
39a11240 3279 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3280 ql_log(ql_log_fatal, base_vha, 0x00ed,
3281 "Failed to start DPC thread.\n");
39a11240 3282 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3283 ha->dpc_thread = NULL;
1da177e4
LT		 3284 goto probe_failed;
3285 }
7c3df132
SK		 3286 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3287 "DPC thread started successfully.\n");
1da177e4 3288
2d70c103
NB		 3289 /*
3290 * If we're not coming up in initiator mode, we might sit for
3291 * a while without waking up the dpc thread, which leads to a
3292 * stuck process warning. So just kick the dpc once here and
3293 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3294 */
3295 qla2xxx_wake_dpc(base_vha);
3296
f3ddac19
CD		 3297 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3298
81178772
SK		 3299 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3300 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3301 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3302 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3303
3304 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3305 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3306 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3307 INIT_WORK(&ha->idc_state_handler,
3308 qla83xx_idc_state_handler_work);
3309 INIT_WORK(&ha->nic_core_unrecoverable,
3310 qla83xx_nic_core_unrecoverable_work);
3311 }
3312
cbc8eb67 3313skip_dpc:
e315cd28
AC		 3314 list_add_tail(&base_vha->list, &ha->vp_list);
3315 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3316
3317 /* Initialized the timer */
8e5f4ba0 3318 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3319 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3320 "Started qla2x00_timer with "
3321 "interval=%d.\n", WATCH_INTERVAL);
3322 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3323 "Detected hba at address=%p.\n",
3324 ha);
d19044c3 3325
e02587d7 3326 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3327 if (ha->fw_attributes & BIT_4) {
9e522cd8 3328 int prot = 0, guard;
bad75002 3329 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3330 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3331 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3332 if (ql2xenabledif == 1)
3333 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3334 scsi_host_set_prot(host,
8cb2049c 3335 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3336 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3337 | SHOST_DIF_TYPE3_PROTECTION
3338 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3339 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3340 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3341
3342 guard = SHOST_DIX_GUARD_CRC;
3343
3344 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3345 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3346 guard |= SHOST_DIX_GUARD_IP;
3347
3348 scsi_host_set_guard(host, guard);
bad75002
AE		 3349 } else
3350 base_vha->flags.difdix_supported = 0;
3351 }
3352
a9083016
GM		 3353 ha->isp_ops->enable_intrs(ha);
3354
1fe19ee4
AB		 3355 if (IS_QLAFX00(ha)) {
3356 ret = qlafx00_fx_disc(base_vha,
3357 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3358 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3359 QLA_SG_ALL : 128;
3360 }
3361
a1541d5a
AV		 3362 ret = scsi_add_host(host, &pdev->dev);
3363 if (ret)
3364 goto probe_failed;
3365
1486400f
MR		 3366 base_vha->flags.init_done = 1;
3367 base_vha->flags.online = 1;
edaa5c74 3368 ha->prev_minidump_failed = 0;
1486400f 3369
7c3df132
SK		 3370 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3371 "Init done and hba is online.\n");
3372
726b8548
QT		 3373 if (qla_ini_mode_enabled(base_vha) ||
3374 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3375 scsi_scan_host(host);
3376 else
3377 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3378 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3379
e315cd28 3380 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3381
8ae6d9c7 3382 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3383 ret = qlafx00_fx_disc(base_vha,
3384 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3385
3386 /* Register system information */
3387 ret = qlafx00_fx_disc(base_vha,
3388 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3389 }
3390
e315cd28 3391 qla2x00_init_host_attr(base_vha);
a1541d5a 3392
e315cd28 3393 qla2x00_dfs_setup(base_vha);
df613b96 3394
03eb912a
AB		 3395 ql_log(ql_log_info, base_vha, 0x00fb,
3396 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3397 ql_log(ql_log_info, base_vha, 0x00fc,
3398 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3399 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3400 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3401 base_vha->host_no,
df57caba 3402 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3403
2d70c103
NB		 3404 qlt_add_target(ha, base_vha);
3405
6b383979 3406 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3407
3408 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3409 return -ENODEV;
3410
e4e3a2ce
QT		 3411 if (ha->flags.detected_lr_sfp) {
3412 ql_log(ql_log_info, base_vha, 0xffff,
3413 "Reset chip to pick up LR SFP setting\n");
3414 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3415 qla2xxx_wake_dpc(base_vha);
3416 }
3417
1da177e4
LT		 3418 return 0;
3419
3420probe_failed:
b9978769
AV		 3421 if (base_vha->timer_active)
3422 qla2x00_stop_timer(base_vha);
3423 base_vha->flags.online = 0;
3424 if (ha->dpc_thread) {
3425 struct task_struct *t = ha->dpc_thread;
3426
3427 ha->dpc_thread = NULL;
3428 kthread_stop(t);
3429 }
3430
e315cd28 3431 qla2x00_free_device(base_vha);
e315cd28 3432 scsi_host_put(base_vha->host);
6d634067
BK		 3433 /*
3434 * Need to NULL out local req/rsp after
3435 * qla2x00_free_device => qla2x00_free_queues frees
3436 * what these are pointing to. Or else we'll
3437 * fall over below in qla2x00_free_req/rsp_que.
3438 */
3439 req = NULL;
3440 rsp = NULL;
1da177e4 3441
e315cd28 3442probe_hw_failed:
d64d6c56 3443 qla2x00_mem_free(ha);
3444 qla2x00_free_req_que(ha, req);
3445 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3446 qla2x00_clear_drv_active(ha);
3447
0a63ad12 3448iospace_config_failed:
7ec0effd 3449 if (IS_P3P_TYPE(ha)) {
0a63ad12 3450 if (!ha->nx_pcibase)
f73cb695 3451 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3452 if (!ql2xdbwr)
f73cb695 3453 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3454 } else {
3455 if (ha->iobase)
3456 iounmap(ha->iobase);
8ae6d9c7
GM		 3457 if (ha->cregbase)
3458 iounmap(ha->cregbase);
a9083016 3459 }
e315cd28
AC		 3460 pci_release_selected_regions(ha->pdev, ha->bars);
3461 kfree(ha);
1da177e4 3462
ddff7ed4 3463disable_device:
e315cd28 3464 pci_disable_device(pdev);
a1541d5a 3465 return ret;
1da177e4 3466}
1da177e4 3467
e30d1756
MI		 3468static void
3469qla2x00_shutdown(struct pci_dev *pdev)
3470{
3471 scsi_qla_host_t *vha;
3472 struct qla_hw_data *ha;
3473
3474 vha = pci_get_drvdata(pdev);
3475 ha = vha->hw;
3476
efdb5760
SC		 3477 ql_log(ql_log_info, vha, 0xfffa,
3478 "Adapter shutdown\n");
3479
3480 /*
3481 * Prevent future board_disable and wait
3482 * until any pending board_disable has completed.
3483 */
3484 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3485 cancel_work_sync(&ha->board_disable);
3486
3487 if (!atomic_read(&pdev->enable_cnt))
3488 return;
3489
42479343
AB		 3490 /* Notify ISPFX00 firmware */
3491 if (IS_QLAFX00(ha))
3492 qlafx00_driver_shutdown(vha, 20);
3493
e30d1756
MI		 3494 /* Turn-off FCE trace */
3495 if (ha->flags.fce_enabled) {
3496 qla2x00_disable_fce_trace(vha, NULL, NULL);
3497 ha->flags.fce_enabled = 0;
3498 }
3499
3500 /* Turn-off EFT trace */
3501 if (ha->eft)
3502 qla2x00_disable_eft_trace(vha);
3503
3407fc37
QT		 3504 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3505 if (ha->flags.fw_started)
3506 qla2x00_abort_isp_cleanup(vha);
3507 } else {
3508 /* Stop currently executing firmware. */
3509 qla2x00_try_to_stop_firmware(vha);
3510 }
e30d1756
MI		 3511
3512 /* Turn adapter off line */
3513 vha->flags.online = 0;
3514
3515 /* turn-off interrupts on the card */
3516 if (ha->interrupts_on) {
3517 vha->flags.init_done = 0;
3518 ha->isp_ops->disable_intrs(ha);
3519 }
3520
3521 qla2x00_free_irqs(vha);
3522
3523 qla2x00_free_fw_dump(ha);
61d41f61 3524
61d41f61 3525 pci_disable_device(pdev);
efdb5760
SC		 3526 ql_log(ql_log_info, vha, 0xfffe,
3527 "Adapter shutdown successfully.\n");
e30d1756
MI		 3528}
3529
fe1b806f 3530/* Deletes all the virtual ports for a given ha */
4c993f76 3531static void
fe1b806f 3532qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3533{
fe1b806f 3534 scsi_qla_host_t *vha;
feafb7b1 3535 unsigned long flags;
e315cd28 3536
43ebf16d
AE		 3537 mutex_lock(&ha->vport_lock);
3538 while (ha->cur_vport_count) {
43ebf16d 3539 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3540
43ebf16d
AE		 3541 BUG_ON(base_vha->list.next == &ha->vp_list);
3542 /* This assumes first entry in ha->vp_list is always base vha */
3543 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3544 scsi_host_get(vha->host);
feafb7b1 3545
43ebf16d
AE		 3546 spin_unlock_irqrestore(&ha->vport_slock, flags);
3547 mutex_unlock(&ha->vport_lock);
3548
3549 fc_vport_terminate(vha->fc_vport);
3550 scsi_host_put(vha->host);
feafb7b1 3551
43ebf16d 3552 mutex_lock(&ha->vport_lock);
e315cd28 3553 }
43ebf16d 3554 mutex_unlock(&ha->vport_lock);
fe1b806f 3555}
1da177e4 3556
fe1b806f
CD		 3557/* Stops all deferred work threads */
3558static void
3559qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3560{
7d613ac6
SV		 3561 /* Cancel all work and destroy DPC workqueues */
3562 if (ha->dpc_lp_wq) {
3563 cancel_work_sync(&ha->idc_aen);
3564 destroy_workqueue(ha->dpc_lp_wq);
3565 ha->dpc_lp_wq = NULL;
3566 }
3567
3568 if (ha->dpc_hp_wq) {
3569 cancel_work_sync(&ha->nic_core_reset);
3570 cancel_work_sync(&ha->idc_state_handler);
3571 cancel_work_sync(&ha->nic_core_unrecoverable);
3572 destroy_workqueue(ha->dpc_hp_wq);
3573 ha->dpc_hp_wq = NULL;
3574 }
3575
b9978769
AV		 3576 /* Kill the kernel thread for this host */
3577 if (ha->dpc_thread) {
3578 struct task_struct *t = ha->dpc_thread;
3579
3580 /*
3581 * qla2xxx_wake_dpc checks for ->dpc_thread
3582 * so we need to zero it out.
3583 */
3584 ha->dpc_thread = NULL;
3585 kthread_stop(t);
3586 }
fe1b806f 3587}
1da177e4 3588
fe1b806f
CD		 3589static void
3590qla2x00_unmap_iobases(struct qla_hw_data *ha)
3591{
a9083016 3592 if (IS_QLA82XX(ha)) {
b963752f 3593
f73cb695 3594 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3595 if (!ql2xdbwr)
f73cb695 3596 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3597 } else {
3598 if (ha->iobase)
3599 iounmap(ha->iobase);
1da177e4 3600
8ae6d9c7
GM		 3601 if (ha->cregbase)
3602 iounmap(ha->cregbase);
3603
a9083016
GM		 3604 if (ha->mqiobase)
3605 iounmap(ha->mqiobase);
6246b8a1 3606
f73cb695 3607 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3608 iounmap(ha->msixbase);
a9083016 3609 }
fe1b806f
CD		 3610}
3611
3612static void
db7157d4 3613qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3614{
fe1b806f
CD		 3615 if (IS_QLA8044(ha)) {
3616 qla8044_idc_lock(ha);
c41afc9a 3617 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3618 qla8044_idc_unlock(ha);
3619 } else if (IS_QLA82XX(ha)) {
3620 qla82xx_idc_lock(ha);
3621 qla82xx_clear_drv_active(ha);
3622 qla82xx_idc_unlock(ha);
3623 }
3624}
3625
3626static void
3627qla2x00_remove_one(struct pci_dev *pdev)
3628{
3629 scsi_qla_host_t *base_vha;
3630 struct qla_hw_data *ha;
3631
beb9e315
JL		 3632 base_vha = pci_get_drvdata(pdev);
3633 ha = base_vha->hw;
45235022
QT		 3634 ql_log(ql_log_info, base_vha, 0xb079,
3635 "Removing driver\n");
beb9e315
JL		 3636
3637 /* Indicate device removal to prevent future board_disable and wait
3638 * until any pending board_disable has completed. */
3639 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3640 cancel_work_sync(&ha->board_disable);
3641
fe1b806f 3642 /*
beb9e315
JL		 3643 * If the PCI device is disabled then there was a PCI-disconnect and
3644 * qla2x00_disable_board_on_pci_error has taken care of most of the
3645 * resources.
fe1b806f 3646 */
beb9e315 3647 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3648 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3649 base_vha->gnl.l, base_vha->gnl.ldma);
3650
beb9e315
JL		 3651 scsi_host_put(base_vha->host);
3652 kfree(ha);
3653 pci_set_drvdata(pdev, NULL);
fe1b806f 3654 return;
beb9e315 3655 }
638a1a01
SC		 3656 qla2x00_wait_for_hba_ready(base_vha);
3657
45235022
QT		 3658 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3659 if (ha->flags.fw_started)
3660 qla2x00_abort_isp_cleanup(base_vha);
3661 } else if (!IS_QLAFX00(ha)) {
3662 if (IS_QLA8031(ha)) {
3663 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3664 "Clearing fcoe driver presence.\n");
3665 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3666 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3667 "Error while clearing DRV-Presence.\n");
3668 }
3669
3670 qla2x00_try_to_stop_firmware(base_vha);
3671 }
3672
2ce87cc5
QT		 3673 qla2x00_wait_for_sess_deletion(base_vha);
3674
726b8548
QT		 3675 /*
3676 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3677 * where it was set first.
3678 */
3679 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3680 return;
3681
fe1b806f 3682 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3683
3684 qla_nvme_delete(base_vha);
3685
726b8548
QT		 3686 dma_free_coherent(&ha->pdev->dev,
3687 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3688
a4239945
QT		 3689 vfree(base_vha->scan.l);
3690
fe1b806f
CD		 3691 if (IS_QLAFX00(ha))
3692 qlafx00_driver_shutdown(base_vha, 20);
3693
3694 qla2x00_delete_all_vps(ha, base_vha);
3695
fe1b806f
CD		 3696 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3697
3698 qla2x00_dfs_remove(base_vha);
3699
3700 qla84xx_put_chip(base_vha);
3701
3702 /* Disable timer */
3703 if (base_vha->timer_active)
3704 qla2x00_stop_timer(base_vha);
3705
3706 base_vha->flags.online = 0;
3707
b0d6cabd
HM		 3708 /* free DMA memory */
3709 if (ha->exlogin_buf)
3710 qla2x00_free_exlogin_buffer(ha);
3711
2f56a7f1
HM		 3712 /* free DMA memory */
3713 if (ha->exchoffld_buf)
3714 qla2x00_free_exchoffld_buffer(ha);
3715
fe1b806f
CD		 3716 qla2x00_destroy_deferred_work(ha);
3717
3718 qlt_remove_target(ha, base_vha);
3719
3720 qla2x00_free_sysfs_attr(base_vha, true);
3721
3722 fc_remove_host(base_vha->host);
482c9dc7 3723 qlt_remove_target_resources(ha);
fe1b806f
CD		 3724
3725 scsi_remove_host(base_vha->host);
3726
3727 qla2x00_free_device(base_vha);
3728
db7157d4 3729 qla2x00_clear_drv_active(ha);
fe1b806f 3730
d2749ffa
AE		 3731 scsi_host_put(base_vha->host);
3732
fe1b806f 3733 qla2x00_unmap_iobases(ha);
73208dfd 3734
e315cd28
AC		 3735 pci_release_selected_regions(ha->pdev, ha->bars);
3736 kfree(ha);
1da177e4 3737
90a86fc0
JC		 3738 pci_disable_pcie_error_reporting(pdev);
3739
665db93b 3740 pci_disable_device(pdev);
1da177e4 3741}
1da177e4
LT		 3742
3743static void
e315cd28 3744qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3745{
e315cd28 3746 struct qla_hw_data *ha = vha->hw;
1da177e4 3747
85880801
AV		 3748 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3749
3750 /* Disable timer */
3751 if (vha->timer_active)
3752 qla2x00_stop_timer(vha);
3753
2afa19a9 3754 qla25xx_delete_queues(vha);
85880801
AV		 3755 vha->flags.online = 0;
3756
f6ef3b18 3757 /* turn-off interrupts on the card */
a9083016
GM		 3758 if (ha->interrupts_on) {
3759 vha->flags.init_done = 0;
fd34f556 3760 ha->isp_ops->disable_intrs(ha);
a9083016 3761 }
f6ef3b18 3762
093df737
QT		 3763 qla2x00_free_fcports(vha);
3764
e315cd28 3765 qla2x00_free_irqs(vha);
1da177e4 3766
093df737
QT		 3767 /* Flush the work queue and remove it */
3768 if (ha->wq) {
3769 flush_workqueue(ha->wq);
3770 destroy_workqueue(ha->wq);
3771 ha->wq = NULL;
3772 }
3773
8867048b 3774
e315cd28 3775 qla2x00_mem_free(ha);
73208dfd 3776
08de2844
GM		 3777 qla82xx_md_free(vha);
3778
73208dfd 3779 qla2x00_free_queues(ha);
1da177e4
LT		 3780}
3781
8867048b
CD		 3782void qla2x00_free_fcports(struct scsi_qla_host *vha)
3783{
3784 fc_port_t *fcport, *tfcport;
3785
3786 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3787 list_del(&fcport->list);
5f16b331 3788 qla2x00_clear_loop_id(fcport);
8867048b 3789 kfree(fcport);
8867048b
CD		 3790 }
3791}
3792
d97994dc 3793static inline void
e315cd28 3794qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3795 int defer)
3796{
d97994dc 3797 struct fc_rport *rport;
67becc00 3798 scsi_qla_host_t *base_vha;
044d78e1 3799 unsigned long flags;
d97994dc
AV		 3800
3801 if (!fcport->rport)
3802 return;
3803
3804 rport = fcport->rport;
3805 if (defer) {
67becc00 3806 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3807 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3808 fcport->drport = rport;
044d78e1 3809 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3810 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3811 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3812 qla2xxx_wake_dpc(base_vha);
2d70c103 3813 } else {
df673274 3814 int now;
726b8548 3815 if (rport) {
83548fe2
QT		 3816 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3817 "%s %8phN. rport %p roles %x\n",
3818 __func__, fcport->port_name, rport,
3819 rport->roles);
d20ed91b 3820 fc_remote_port_delete(rport);
726b8548 3821 }
df673274 3822 qlt_do_generation_tick(vha, &now);
2d70c103 3823 }
d97994dc
AV		 3824}
3825
1da177e4
LT		 3826/*
3827 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3828 *
3829 * Input: ha = adapter block pointer. fcport = port structure pointer.
3830 *
3831 * Return: None.
3832 *
3833 * Context:
3834 */
e315cd28 3835void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3836 int do_login, int defer)
1da177e4 3837{
8ae6d9c7
GM		 3838 if (IS_QLAFX00(vha->hw)) {
3839 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3840 qla2x00_schedule_rport_del(vha, fcport, defer);
3841 return;
3842 }
3843
2c3dfe3f 3844 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3845 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3846 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3847 qla2x00_schedule_rport_del(vha, fcport, defer);
3848 }
fa2a1ce5 3849 /*
1da177e4
LT		 3850 * We may need to retry the login, so don't change the state of the
3851 * port but do the retries.
3852 */
3853 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3854 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3855
3856 if (!do_login)
3857 return;
3858
a1d0285e 3859 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3860}
3861
3862/*
3863 * qla2x00_mark_all_devices_lost
3864 * Updates fcport state when device goes offline.
3865 *
3866 * Input:
3867 * ha = adapter block pointer.
3868 * fcport = port structure pointer.
3869 *
3870 * Return:
3871 * None.
3872 *
3873 * Context:
3874 */
3875void
e315cd28 3876qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3877{
3878 fc_port_t *fcport;
3879
83548fe2
QT		 3880 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3881 "Mark all dev lost\n");
726b8548 3882
e315cd28 3883 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3884 fcport->scan_state = 0;
d8630bb9 3885 qlt_schedule_sess_for_deletion(fcport);
726b8548 3886
c6d39e23 3887 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3888 continue;
0d6e61bc 3889
1da177e4
LT		 3890 /*
3891 * No point in marking the device as lost, if the device is
3892 * already DEAD.
3893 */
3894 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3895 continue;
e315cd28 3896 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3897 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3898 if (defer)
3899 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3900 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3901 qla2x00_schedule_rport_del(vha, fcport, defer);
3902 }
1da177e4
LT		 3903 }
3904}
3905
3906/*
3907* qla2x00_mem_alloc
3908* Allocates adapter memory.
3909*
3910* Returns:
3911* 0 = success.
e8711085 3912* !0 = failure.
1da177e4 3913*/
e8711085 3914static int
73208dfd
AC		 3915qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3916 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3917{
3918 char name[16];
1da177e4 3919
e8711085 3920 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3921 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3922 if (!ha->init_cb)
e315cd28 3923 goto fail;
e8711085 3924
2d70c103
NB		 3925 if (qlt_mem_alloc(ha) < 0)
3926 goto fail_free_init_cb;
3927
642ef983
CD		 3928 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3929 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3930 if (!ha->gid_list)
2d70c103 3931 goto fail_free_tgt_mem;
1da177e4 3932
e8711085
AV		 3933 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3934 if (!ha->srb_mempool)
e315cd28 3935 goto fail_free_gid_list;
e8711085 3936
7ec0effd 3937 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3938 /* Allocate cache for CT6 Ctx. */
3939 if (!ctx_cachep) {
3940 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3941 sizeof(struct ct6_dsd), 0,
3942 SLAB_HWCACHE_ALIGN, NULL);
3943 if (!ctx_cachep)
fc1ffd6c 3944 goto fail_free_srb_mempool;
a9083016
GM		 3945 }
3946 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3947 ctx_cachep);
3948 if (!ha->ctx_mempool)
3949 goto fail_free_srb_mempool;
7c3df132
SK		 3950 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3951 "ctx_cachep=%p ctx_mempool=%p.\n",
3952 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3953 }
3954
e8711085
AV		 3955 /* Get memory for cached NVRAM */
3956 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3957 if (!ha->nvram)
a9083016 3958 goto fail_free_ctx_mempool;
e8711085 3959
e315cd28
AC		 3960 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3961 ha->pdev->device);
3962 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3963 DMA_POOL_SIZE, 8, 0);
3964 if (!ha->s_dma_pool)
3965 goto fail_free_nvram;
3966
7c3df132
SK		 3967 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3968 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3969 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3970
7ec0effd 3971 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3972 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3973 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3974 if (!ha->dl_dma_pool) {
7c3df132
SK		 3975 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3976 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3977 goto fail_s_dma_pool;
3978 }
3979
3980 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3981 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3982 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3983 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3984 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3985 goto fail_dl_dma_pool;
3986 }
7c3df132
SK		 3987 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3988 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3989 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3990 }
3991
e8711085
AV		 3992 /* Allocate memory for SNS commands */
3993 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3994 /* Get consistent memory allocated for SNS commands */
e8711085 3995 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3996 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3997 if (!ha->sns_cmd)
e315cd28 3998 goto fail_dma_pool;
7c3df132 3999 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4000 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4001 } else {
e315cd28 4002 /* Get consistent memory allocated for MS IOCB */
e8711085 4003 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4004 &ha->ms_iocb_dma);
e8711085 4005 if (!ha->ms_iocb)
e315cd28
AC		 4006 goto fail_dma_pool;
4007 /* Get consistent memory allocated for CT SNS commands */
e8711085 4008 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4009 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4010 if (!ha->ct_sns)
4011 goto fail_free_ms_iocb;
7c3df132
SK		 4012 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4013 "ms_iocb=%p ct_sns=%p.\n",
4014 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4015 }
4016
e315cd28 4017 /* Allocate memory for request ring */
73208dfd
AC		 4018 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4019 if (!*req) {
7c3df132
SK		 4020 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4021 "Failed to allocate memory for req.\n");
e315cd28
AC		 4022 goto fail_req;
4023 }
73208dfd
AC		 4024 (*req)->length = req_len;
4025 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4026 ((*req)->length + 1) * sizeof(request_t),
4027 &(*req)->dma, GFP_KERNEL);
4028 if (!(*req)->ring) {
7c3df132
SK		 4029 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4030 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4031 goto fail_req_ring;
4032 }
4033 /* Allocate memory for response ring */
73208dfd
AC		 4034 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4035 if (!*rsp) {
7c3df132
SK		 4036 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4037 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4038 goto fail_rsp;
4039 }
73208dfd
AC		 4040 (*rsp)->hw = ha;
4041 (*rsp)->length = rsp_len;
4042 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4043 ((*rsp)->length + 1) * sizeof(response_t),
4044 &(*rsp)->dma, GFP_KERNEL);
4045 if (!(*rsp)->ring) {
7c3df132
SK		 4046 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4047 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4048 goto fail_rsp_ring;
4049 }
73208dfd
AC		 4050 (*req)->rsp = *rsp;
4051 (*rsp)->req = *req;
7c3df132
SK		 4052 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4053 "req=%p req->length=%d req->ring=%p rsp=%p "
4054 "rsp->length=%d rsp->ring=%p.\n",
4055 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4056 (*rsp)->ring);
73208dfd
AC		 4057 /* Allocate memory for NVRAM data for vports */
4058 if (ha->nvram_npiv_size) {
6396bb22
KC		 4059 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4060 sizeof(struct qla_npiv_entry),
4061 GFP_KERNEL);
73208dfd 4062 if (!ha->npiv_info) {
7c3df132
SK		 4063 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4064 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4065 goto fail_npiv_info;
4066 }
4067 } else
4068 ha->npiv_info = NULL;
e8711085 4069
b64b0e8f 4070 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4071 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4072 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4073 &ha->ex_init_cb_dma);
4074 if (!ha->ex_init_cb)
4075 goto fail_ex_init_cb;
7c3df132
SK		 4076 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4077 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4078 }
4079
a9083016
GM		 4080 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4081
5ff1d584
AV		 4082 /* Get consistent memory allocated for Async Port-Database. */
4083 if (!IS_FWI2_CAPABLE(ha)) {
4084 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4085 &ha->async_pd_dma);
4086 if (!ha->async_pd)
4087 goto fail_async_pd;
7c3df132
SK		 4088 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4089 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4090 }
4091
e315cd28 4092 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4093
4094 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4095 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4096 sizeof(long),
4097 GFP_KERNEL);
5f16b331 4098 if (!ha->loop_id_map)
fc1ffd6c 4099 goto fail_loop_id_map;
5f16b331
CD		 4100 else {
4101 qla2x00_set_reserved_loop_ids(ha);
4102 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4103 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4104 }
4105
e4e3a2ce
QT		 4106 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4107 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4108 if (!ha->sfp_data) {
4109 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4110 "Unable to allocate memory for SFP read-data.\n");
4111 goto fail_sfp_data;
4112 }
4113
b2a72ec3 4114 return 0;
e315cd28 4115
e4e3a2ce
QT		 4116fail_sfp_data:
4117 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4118fail_loop_id_map:
4119 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4120fail_async_pd:
4121 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4122fail_ex_init_cb:
4123 kfree(ha->npiv_info);
73208dfd
AC		 4124fail_npiv_info:
4125 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4126 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4127 (*rsp)->ring = NULL;
4128 (*rsp)->dma = 0;
e315cd28 4129fail_rsp_ring:
73208dfd 4130 kfree(*rsp);
6d634067 4131 *rsp = NULL;
e315cd28 4132fail_rsp:
73208dfd
AC		 4133 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4134 sizeof(request_t), (*req)->ring, (*req)->dma);
4135 (*req)->ring = NULL;
4136 (*req)->dma = 0;
e315cd28 4137fail_req_ring:
73208dfd 4138 kfree(*req);
6d634067 4139 *req = NULL;
e315cd28
AC		 4140fail_req:
4141 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4142 ha->ct_sns, ha->ct_sns_dma);
4143 ha->ct_sns = NULL;
4144 ha->ct_sns_dma = 0;
e8711085
AV		 4145fail_free_ms_iocb:
4146 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4147 ha->ms_iocb = NULL;
4148 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4149
4150 if (ha->sns_cmd)
4151 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4152 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4153fail_dma_pool:
bad75002 4154 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4155 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4156 ha->fcp_cmnd_dma_pool = NULL;
4157 }
4158fail_dl_dma_pool:
bad75002 4159 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4160 dma_pool_destroy(ha->dl_dma_pool);
4161 ha->dl_dma_pool = NULL;
4162 }
4163fail_s_dma_pool:
e315cd28
AC		 4164 dma_pool_destroy(ha->s_dma_pool);
4165 ha->s_dma_pool = NULL;
e8711085
AV		 4166fail_free_nvram:
4167 kfree(ha->nvram);
4168 ha->nvram = NULL;
a9083016 4169fail_free_ctx_mempool:
fc1ffd6c
QT		 4170 if (ha->ctx_mempool)
4171 mempool_destroy(ha->ctx_mempool);
a9083016 4172 ha->ctx_mempool = NULL;
e8711085 4173fail_free_srb_mempool:
fc1ffd6c
QT		 4174 if (ha->srb_mempool)
4175 mempool_destroy(ha->srb_mempool);
e8711085 4176 ha->srb_mempool = NULL;
e8711085 4177fail_free_gid_list:
642ef983
CD		 4178 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4179 ha->gid_list,
e315cd28 4180 ha->gid_list_dma);
e8711085
AV		 4181 ha->gid_list = NULL;
4182 ha->gid_list_dma = 0;
2d70c103
NB		 4183fail_free_tgt_mem:
4184 qlt_mem_free(ha);
e315cd28
AC		 4185fail_free_init_cb:
4186 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4187 ha->init_cb_dma);
4188 ha->init_cb = NULL;
4189 ha->init_cb_dma = 0;
e8711085 4190fail:
7c3df132
SK		 4191 ql_log(ql_log_fatal, NULL, 0x0030,
4192 "Memory allocation failure.\n");
e8711085 4193 return -ENOMEM;
1da177e4
LT		 4194}
4195
b0d6cabd
HM		 4196int
4197qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4198{
4199 int rval;
4200 uint16_t size, max_cnt, temp;
4201 struct qla_hw_data *ha = vha->hw;
4202
4203 /* Return if we don't need to alloacate any extended logins */
4204 if (!ql2xexlogins)
4205 return QLA_SUCCESS;
4206
99e1b683
QT		 4207 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4208 return QLA_SUCCESS;
4209
b0d6cabd
HM		 4210 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4211 max_cnt = 0;
4212 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4213 if (rval != QLA_SUCCESS) {
4214 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4215 "Failed to get exlogin status.\n");
4216 return rval;
4217 }
4218
4219 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4220 temp *= size;
4221
4222 if (temp != ha->exlogin_size) {
4223 qla2x00_free_exlogin_buffer(ha);
4224 ha->exlogin_size = temp;
4225
4226 ql_log(ql_log_info, vha, 0xd024,
4227 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4228 max_cnt, size, temp);
4229
4230 ql_log(ql_log_info, vha, 0xd025,
4231 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4232
4233 /* Get consistent memory for extended logins */
4234 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4235 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4236 if (!ha->exlogin_buf) {
4237 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4238 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4239 return -ENOMEM;
4240 }
b0d6cabd
HM		 4241 }
4242
4243 /* Now configure the dma buffer */
4244 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4245 if (rval) {
83548fe2 4246 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4247 "Setup extended login buffer ****FAILED****.\n");
4248 qla2x00_free_exlogin_buffer(ha);
4249 }
4250
4251 return rval;
4252}
4253
4254/*
4255* qla2x00_free_exlogin_buffer
4256*
4257* Input:
4258* ha = adapter block pointer
4259*/
4260void
4261qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4262{
4263 if (ha->exlogin_buf) {
4264 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4265 ha->exlogin_buf, ha->exlogin_buf_dma);
4266 ha->exlogin_buf = NULL;
4267 ha->exlogin_size = 0;
4268 }
4269}
4270
99e1b683
QT		 4271static void
4272qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4273{
4274 u32 temp;
4275 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4276
d1e3635a
QT		 4277 if (max_cnt > vha->hw->max_exchg)
4278 max_cnt = vha->hw->max_exchg;
4279
99e1b683
QT		 4280 if (qla_ini_mode_enabled(vha)) {
4281 if (ql2xiniexchg > max_cnt)
4282 ql2xiniexchg = max_cnt;
4283
4284 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4285 *ret_cnt = ql2xiniexchg;
4286 } else if (qla_tgt_mode_enabled(vha)) {
4287 if (ql2xexchoffld > max_cnt)
4288 ql2xexchoffld = max_cnt;
4289
4290 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4291 *ret_cnt = ql2xexchoffld;
4292 } else if (qla_dual_mode_enabled(vha)) {
4293 temp = ql2xiniexchg + ql2xexchoffld;
4294 if (temp > max_cnt) {
4295 ql2xiniexchg -= (temp - max_cnt)/2;
4296 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4297 temp = max_cnt;
4298 }
4299
4300 if (temp > FW_DEF_EXCHANGES_CNT)
4301 *ret_cnt = temp;
4302 }
4303}
4304
2f56a7f1
HM		 4305int
4306qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4307{
4308 int rval;
d1e3635a
QT		 4309 u16 size, max_cnt;
4310 u32 actual_cnt, totsz;
2f56a7f1
HM		 4311 struct qla_hw_data *ha = vha->hw;
4312
99e1b683
QT		 4313 if (!ha->flags.exchoffld_enabled)
4314 return QLA_SUCCESS;
4315
4316 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4317 return QLA_SUCCESS;
4318
2f56a7f1
HM		 4319 max_cnt = 0;
4320 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4321 if (rval != QLA_SUCCESS) {
4322 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4323 "Failed to get exlogin status.\n");
4324 return rval;
4325 }
4326
d1e3635a
QT		 4327 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4328 ql_log(ql_log_info, vha, 0xd014,
4329 "Actual exchange offload count: %d.\n", actual_cnt);
4330
4331 totsz = actual_cnt * size;
2f56a7f1 4332
d1e3635a 4333 if (totsz != ha->exchoffld_size) {
99e1b683 4334 qla2x00_free_exchoffld_buffer(ha);
d1e3635a 4335 ha->exchoffld_size = totsz;
99e1b683
QT		 4336
4337 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4338 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4339 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4340
4341 ql_log(ql_log_info, vha, 0xd017,
4342 "Exchange Buffers requested size = 0x%x\n",
4343 ha->exchoffld_size);
4344
4345 /* Get consistent memory for extended logins */
4346 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4347 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4348 if (!ha->exchoffld_buf) {
4349 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4350 "Failed to allocate memory for Exchange Offload.\n");
4351
4352 if (ha->max_exchg >
4353 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4354 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4355 } else if (ha->max_exchg >
4356 (FW_DEF_EXCHANGES_CNT + 512)) {
4357 ha->max_exchg -= 512;
4358 } else {
4359 ha->flags.exchoffld_enabled = 0;
4360 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4361 "Disabling Exchange offload due to lack of memory\n");
4362 }
4363 ha->exchoffld_size = 0;
4364
99e1b683
QT		 4365 return -ENOMEM;
4366 }
2f56a7f1
HM		 4367 }
4368
4369 /* Now configure the dma buffer */
99e1b683 4370 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4371 if (rval) {
4372 ql_log(ql_log_fatal, vha, 0xd02e,
4373 "Setup exchange offload buffer ****FAILED****.\n");
4374 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4375 } else {
4376 /* re-adjust number of target exchange */
4377 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4378
4379 if (qla_ini_mode_enabled(vha))
4380 icb->exchange_count = 0;
4381 else
4382 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4383 }
4384
4385 return rval;
4386}
4387
4388/*
4389* qla2x00_free_exchoffld_buffer
4390*
4391* Input:
4392* ha = adapter block pointer
4393*/
4394void
4395qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4396{
4397 if (ha->exchoffld_buf) {
4398 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4399 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4400 ha->exchoffld_buf = NULL;
4401 ha->exchoffld_size = 0;
4402 }
4403}
4404
1da177e4 4405/*
e30d1756
MI		 4406* qla2x00_free_fw_dump
4407* Frees fw dump stuff.
1da177e4
LT		 4408*
4409* Input:
7ec0effd 4410* ha = adapter block pointer
1da177e4 4411*/
a824ebb3 4412static void
e30d1756 4413qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4414{
df613b96 4415 if (ha->fce)
f73cb695
CD		 4416 dma_free_coherent(&ha->pdev->dev,
4417 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4418
f73cb695
CD		 4419 if (ha->eft)
4420 dma_free_coherent(&ha->pdev->dev,
4421 EFT_SIZE, ha->eft, ha->eft_dma);
4422
4423 if (ha->fw_dump)
a7a167bf 4424 vfree(ha->fw_dump);
f73cb695
CD		 4425 if (ha->fw_dump_template)
4426 vfree(ha->fw_dump_template);
4427
e30d1756
MI		 4428 ha->fce = NULL;
4429 ha->fce_dma = 0;
4430 ha->eft = NULL;
4431 ha->eft_dma = 0;
e30d1756 4432 ha->fw_dumped = 0;
61f098dd 4433 ha->fw_dump_cap_flags = 0;
e30d1756 4434 ha->fw_dump_reading = 0;
f73cb695
CD		 4435 ha->fw_dump = NULL;
4436 ha->fw_dump_len = 0;
4437 ha->fw_dump_template = NULL;
4438 ha->fw_dump_template_len = 0;
e30d1756
MI		 4439}
4440
4441/*
4442* qla2x00_mem_free
4443* Frees all adapter allocated memory.
4444*
4445* Input:
4446* ha = adapter block pointer.
4447*/
4448static void
4449qla2x00_mem_free(struct qla_hw_data *ha)
4450{
4451 qla2x00_free_fw_dump(ha);
4452
81178772
SK		 4453 if (ha->mctp_dump)
4454 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4455 ha->mctp_dump_dma);
4456
e30d1756
MI		 4457 if (ha->srb_mempool)
4458 mempool_destroy(ha->srb_mempool);
a7a167bf 4459
11bbc1d8
AV		 4460 if (ha->dcbx_tlv)
4461 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4462 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4463
ce0423f4
AV		 4464 if (ha->xgmac_data)
4465 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4466 ha->xgmac_data, ha->xgmac_data_dma);
4467
1da177e4
LT		 4468 if (ha->sns_cmd)
4469 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4470 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4471
4472 if (ha->ct_sns)
4473 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4474 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4475
88729e53 4476 if (ha->sfp_data)
e4e3a2ce
QT		 4477 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4478 ha->sfp_data_dma);
88729e53 4479
1da177e4
LT		 4480 if (ha->ms_iocb)
4481 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4482
b64b0e8f 4483 if (ha->ex_init_cb)
a9083016
GM		 4484 dma_pool_free(ha->s_dma_pool,
4485 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4486
5ff1d584
AV		 4487 if (ha->async_pd)
4488 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4489
1da177e4
LT		 4490 if (ha->s_dma_pool)
4491 dma_pool_destroy(ha->s_dma_pool);
4492
1da177e4 4493 if (ha->gid_list)
642ef983
CD		 4494 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4495 ha->gid_list, ha->gid_list_dma);
1da177e4 4496
a9083016
GM		 4497 if (IS_QLA82XX(ha)) {
4498 if (!list_empty(&ha->gbl_dsd_list)) {
4499 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4500
4501 /* clean up allocated prev pool */
4502 list_for_each_entry_safe(dsd_ptr,
4503 tdsd_ptr, &ha->gbl_dsd_list, list) {
4504 dma_pool_free(ha->dl_dma_pool,
4505 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4506 list_del(&dsd_ptr->list);
4507 kfree(dsd_ptr);
4508 }
4509 }
4510 }
4511
4512 if (ha->dl_dma_pool)
4513 dma_pool_destroy(ha->dl_dma_pool);
4514
4515 if (ha->fcp_cmnd_dma_pool)
4516 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4517
4518 if (ha->ctx_mempool)
4519 mempool_destroy(ha->ctx_mempool);
4520
2d70c103
NB		 4521 qlt_mem_free(ha);
4522
e315cd28
AC		 4523 if (ha->init_cb)
4524 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4525 ha->init_cb, ha->init_cb_dma);
6a2cf8d3 4526
6d634067
BK		 4527 vfree(ha->optrom_buffer);
4528 kfree(ha->nvram);
4529 kfree(ha->npiv_info);
4530 kfree(ha->swl);
4531 kfree(ha->loop_id_map);
1da177e4 4532
e8711085 4533 ha->srb_mempool = NULL;
a9083016 4534 ha->ctx_mempool = NULL;
1da177e4
LT		 4535 ha->sns_cmd = NULL;
4536 ha->sns_cmd_dma = 0;
4537 ha->ct_sns = NULL;
4538 ha->ct_sns_dma = 0;
4539 ha->ms_iocb = NULL;
4540 ha->ms_iocb_dma = 0;
1da177e4
LT		 4541 ha->init_cb = NULL;
4542 ha->init_cb_dma = 0;
b64b0e8f
AV		 4543 ha->ex_init_cb = NULL;
4544 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4545 ha->async_pd = NULL;
4546 ha->async_pd_dma = 0;
6a2cf8d3
BK		 4547 ha->loop_id_map = NULL;
4548 ha->npiv_info = NULL;
4549 ha->optrom_buffer = NULL;
4550 ha->swl = NULL;
4551 ha->nvram = NULL;
4552 ha->mctp_dump = NULL;
4553 ha->dcbx_tlv = NULL;
4554 ha->xgmac_data = NULL;
4555 ha->sfp_data = NULL;
1da177e4
LT		 4556
4557 ha->s_dma_pool = NULL;
a9083016
GM		 4558 ha->dl_dma_pool = NULL;
4559 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4560
1da177e4
LT		 4561 ha->gid_list = NULL;
4562 ha->gid_list_dma = 0;
2d70c103
NB		 4563
4564 ha->tgt.atio_ring = NULL;
4565 ha->tgt.atio_dma = 0;
4566 ha->tgt.tgt_vp_map = NULL;
e315cd28 4567}
1da177e4 4568
e315cd28
AC		 4569struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4570 struct qla_hw_data *ha)
4571{
4572 struct Scsi_Host *host;
4573 struct scsi_qla_host *vha = NULL;
854165f4 4574
e315cd28 4575 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4576 if (!host) {
7c3df132
SK		 4577 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4578 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4579 return NULL;
e315cd28
AC		 4580 }
4581
4582 /* Clear our data area */
4583 vha = shost_priv(host);
4584 memset(vha, 0, sizeof(scsi_qla_host_t));
4585
4586 vha->host = host;
4587 vha->host_no = host->host_no;
4588 vha->hw = ha;
4589
4590 INIT_LIST_HEAD(&vha->vp_fcports);
4591 INIT_LIST_HEAD(&vha->work_list);
4592 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4593 INIT_LIST_HEAD(&vha->qla_cmd_list);
4594 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4595 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4596 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4597 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4598 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4599 INIT_LIST_HEAD(&vha->nvme_rport_list);
2d73ac61 4600 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4601 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4602
f999f4c1 4603 spin_lock_init(&vha->work_lock);
8b2f5ff3 4604 spin_lock_init(&vha->cmd_list_lock);
1c6cacf4 4605 spin_lock_init(&vha->gnl.fcports_lock);
726b8548 4606 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4607 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4608
2fdbc65e
BVA		 4609 vha->gnl.size = sizeof(struct get_name_list_extended) *
4610 (ha->max_loop_id + 1);
41dc529a
QT		 4611 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4612 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4613 if (!vha->gnl.l) {
83548fe2 4614 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4615 "Alloc failed for name list.\n");
4616 scsi_remove_host(vha->host);
4617 return NULL;
4618 }
f999f4c1 4619
a4239945
QT		 4620 /* todo: what about ext login? */
4621 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4622 vha->scan.l = vmalloc(vha->scan.size);
4623 if (!vha->scan.l) {
4624 ql_log(ql_log_fatal, vha, 0xd04a,
4625 "Alloc failed for scan database.\n");
4626 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4627 vha->gnl.l, vha->gnl.ldma);
4628 scsi_remove_host(vha->host);
4629 return NULL;
4630 }
f352eeb7 4631 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4632
e315cd28 4633 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4634 ql_dbg(ql_dbg_init, vha, 0x0041,
4635 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4636 vha->host, vha->hw, vha,
4637 dev_name(&(ha->pdev->dev)));
4638
e315cd28 4639 return vha;
1da177e4
LT		 4640}
4641
726b8548 4642struct qla_work_evt *
f999f4c1 4643qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4644{
4645 struct qla_work_evt *e;
feafb7b1
AE		 4646 uint8_t bail;
4647
4648 QLA_VHA_MARK_BUSY(vha, bail);
4649 if (bail)
4650 return NULL;
0971de7f 4651
f999f4c1 4652 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4653 if (!e) {
4654 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4655 return NULL;
feafb7b1 4656 }
0971de7f
AV		 4657
4658 INIT_LIST_HEAD(&e->list);
4659 e->type = type;
4660 e->flags = QLA_EVT_FLAG_FREE;
4661 return e;
4662}
4663
726b8548 4664int
f999f4c1 4665qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4666{
f999f4c1 4667 unsigned long flags;
9b3e0f4d 4668 bool q = false;
0971de7f 4669
f999f4c1 4670 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4671 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4672
4673 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4674 q = true;
4675
f999f4c1 4676 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4677
9b3e0f4d
QT		 4678 if (q)
4679 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4680
0971de7f
AV		 4681 return QLA_SUCCESS;
4682}
4683
4684int
e315cd28 4685qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4686 u32 data)
4687{
4688 struct qla_work_evt *e;
4689
f999f4c1 4690 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4691 if (!e)
4692 return QLA_FUNCTION_FAILED;
4693
4694 e->u.aen.code = code;
4695 e->u.aen.data = data;
f999f4c1 4696 return qla2x00_post_work(vha, e);
0971de7f
AV		 4697}
4698
8a659571
AV		 4699int
4700qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4701{
4702 struct qla_work_evt *e;
4703
f999f4c1 4704 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4705 if (!e)
4706 return QLA_FUNCTION_FAILED;
4707
4708 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4709 return qla2x00_post_work(vha, e);
8a659571
AV		 4710}
4711
ac280b67
AV		 4712#define qla2x00_post_async_work(name, type) \
4713int qla2x00_post_async_##name##_work( \
4714 struct scsi_qla_host *vha, \
4715 fc_port_t *fcport, uint16_t *data) \
4716{ \
4717 struct qla_work_evt *e; \
4718 \
4719 e = qla2x00_alloc_work(vha, type); \
4720 if (!e) \
4721 return QLA_FUNCTION_FAILED; \
4722 \
4723 e->u.logio.fcport = fcport; \
4724 if (data) { \
4725 e->u.logio.data[0] = data[0]; \
4726 e->u.logio.data[1] = data[1]; \
4727 } \
6d674927 4728 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4729 return qla2x00_post_work(vha, e); \
4730}
4731
4732qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4733qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4734qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4735qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4736qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
11aea16a
QT		 4737qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4738qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4739
3420d36c
AV		 4740int
4741qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4742{
4743 struct qla_work_evt *e;
4744
4745 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4746 if (!e)
4747 return QLA_FUNCTION_FAILED;
4748
4749 e->u.uevent.code = code;
4750 return qla2x00_post_work(vha, e);
4751}
4752
4753static void
4754qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4755{
4756 char event_string[40];
4757 char *envp[] = { event_string, NULL };
4758
4759 switch (code) {
4760 case QLA_UEVENT_CODE_FW_DUMP:
4761 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4762 vha->host_no);
4763 break;
4764 default:
4765 /* do nothing */
4766 break;
4767 }
4768 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4769}
4770
8ae6d9c7
GM		 4771int
4772qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4773 uint32_t *data, int cnt)
4774{
4775 struct qla_work_evt *e;
4776
4777 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4778 if (!e)
4779 return QLA_FUNCTION_FAILED;
4780
4781 e->u.aenfx.evtcode = evtcode;
4782 e->u.aenfx.count = cnt;
4783 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4784 return qla2x00_post_work(vha, e);
4785}
4786
cd4ed6b4 4787void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 4788{
cd4ed6b4 4789 unsigned long flags;
726b8548 4790
cd4ed6b4
QT		 4791 if (IS_SW_RESV_ADDR(fcport->d_id))
4792 return;
726b8548 4793
cd4ed6b4
QT		 4794 spin_lock_irqsave(&fcport->vha->work_lock, flags);
4795 if (fcport->disc_state == DSC_UPD_FCPORT) {
4796 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
4797 return;
4798 }
4799 fcport->jiffies_at_registration = jiffies;
4800 fcport->sec_since_registration = 0;
4801 fcport->next_disc_state = DSC_DELETED;
4802 fcport->disc_state = DSC_UPD_FCPORT;
4803 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
4804
4805 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 4806}
4807
4808static
4809void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4810{
4811 unsigned long flags;
b5d15312 4812 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4813 struct qlt_plogi_ack_t *pla =
4814 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4815 uint8_t free_fcport = 0;
726b8548 4816
9cd883f0
QT		 4817 ql_dbg(ql_dbg_disc, vha, 0xffff,
4818 "%s %d %8phC enter\n",
4819 __func__, __LINE__, e->u.new_sess.port_name);
4820
726b8548
QT		 4821 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4822 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4823 if (fcport) {
4824 fcport->d_id = e->u.new_sess.id;
4825 if (pla) {
4826 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 4827 memcpy(fcport->node_name,
4828 pla->iocb.u.isp24.u.plogi.node_name,
4829 WWN_SIZE);
726b8548
QT		 4830 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4831 /* we took an extra ref_count to prevent PLOGI ACK when
4832 * fcport/sess has not been created.
4833 */
4834 pla->ref_count--;
4835 }
4836 } else {
b5d15312 4837 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4838 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4839 if (fcport) {
4840 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 4841 fcport->flags |= FCF_FABRIC_DEVICE;
4842 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
8777e431 4843 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 4844 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 4845
8777e431 4846 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 4847 fcport->fc4_type = FC4_TYPE_OTHER;
4848 fcport->fc4f_nvme = FC4_TYPE_NVME;
4849 }
33b28357 4850
726b8548
QT		 4851 memcpy(fcport->port_name, e->u.new_sess.port_name,
4852 WWN_SIZE);
b5d15312
QT		 4853 } else {
4854 ql_dbg(ql_dbg_disc, vha, 0xffff,
4855 "%s %8phC mem alloc fail.\n",
4856 __func__, e->u.new_sess.port_name);
4857
4858 if (pla)
4859 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4860 return;
4861 }
4862
4863 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 4864 /* search again to make sure no one else got ahead */
b5d15312
QT		 4865 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4866 e->u.new_sess.port_name, 1);
4867 if (tfcp) {
4868 /* should rarily happen */
4869 ql_dbg(ql_dbg_disc, vha, 0xffff,
4870 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4871 __func__, tfcp->port_name, tfcp->disc_state,
4872 tfcp->fw_login_state);
4873
4874 free_fcport = 1;
4875 } else {
726b8548
QT		 4876 list_add_tail(&fcport->list, &vha->vp_fcports);
4877
19759033
QT		 4878 }
4879 if (pla) {
4880 qlt_plogi_ack_link(vha, pla, fcport,
4881 QLT_PLOGI_LINK_SAME_WWN);
4882 pla->ref_count--;
726b8548
QT		 4883 }
4884 }
4885 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4886
4887 if (fcport) {
a4239945
QT		 4888 fcport->id_changed = 1;
4889 fcport->scan_state = QLA_FCPORT_FOUND;
4890 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
4891
5ef696aa 4892 if (pla) {
9cd883f0
QT		 4893 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
4894 u16 wd3_lo;
4895
4896 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4897 fcport->local = 0;
4898 fcport->loop_id =
4899 le16_to_cpu(
4900 pla->iocb.u.isp24.nport_handle);
4901 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4902 wd3_lo =
4903 le16_to_cpu(
4904 pla->iocb.u.isp24.u.prli.wd3_lo);
4905
4906 if (wd3_lo & BIT_7)
4907 fcport->conf_compl_supported = 1;
4908
4909 if ((wd3_lo & BIT_4) == 0)
4910 fcport->port_type = FCT_INITIATOR;
4911 else
4912 fcport->port_type = FCT_TARGET;
4913 }
726b8548 4914 qlt_plogi_ack_unref(vha, pla);
5ef696aa 4915 } else {
1c6cacf4
HR		 4916 fc_port_t *dfcp = NULL;
4917
5ef696aa
QT		 4918 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4919 tfcp = qla2x00_find_fcport_by_nportid(vha,
4920 &e->u.new_sess.id, 1);
4921 if (tfcp && (tfcp != fcport)) {
4922 /*
4923 * We have a conflict fcport with same NportID.
4924 */
4925 ql_dbg(ql_dbg_disc, vha, 0xffff,
4926 "%s %8phC found conflict b4 add. DS %d LS %d\n",
4927 __func__, tfcp->port_name, tfcp->disc_state,
4928 tfcp->fw_login_state);
4929
4930 switch (tfcp->disc_state) {
4931 case DSC_DELETED:
4932 break;
4933 case DSC_DELETE_PEND:
4934 fcport->login_pause = 1;
4935 tfcp->conflict = fcport;
4936 break;
4937 default:
4938 fcport->login_pause = 1;
4939 tfcp->conflict = fcport;
1c6cacf4 4940 dfcp = tfcp;
5ef696aa
QT		 4941 break;
4942 }
4943 }
4944 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 4945 if (dfcp)
4946 qlt_schedule_sess_for_deletion(tfcp);
a4239945 4947
a4239945 4948
8777e431
QT		 4949 if (N2N_TOPO(vha->hw))
4950 fcport->flags &= ~FCF_FABRIC_DEVICE;
4951
4952 if (N2N_TOPO(vha->hw)) {
4953 if (vha->flags.nvme_enabled) {
4954 fcport->fc4f_nvme = 1;
4955 fcport->n2n_flag = 1;
4956 }
4957 fcport->fw_login_state = 0;
4958 /*
4959 * wait link init done before sending login
4960 */
4961 } else {
4962 qla24xx_fcport_handle_login(vha, fcport);
4963 }
5ef696aa 4964 }
726b8548 4965 }
b5d15312
QT		 4966
4967 if (free_fcport) {
4968 qla2x00_free_fcport(fcport);
4969 if (pla)
4970 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4971 }
726b8548
QT		 4972}
4973
e374f9f5
QT		 4974static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
4975{
4976 struct srb *sp = e->u.iosb.sp;
4977 int rval;
4978
4979 rval = qla2x00_start_sp(sp);
4980 if (rval != QLA_SUCCESS) {
4981 ql_dbg(ql_dbg_disc, vha, 0x2043,
4982 "%s: %s: Re-issue IOCB failed (%d).\n",
4983 __func__, sp->name, rval);
4984 qla24xx_sp_unmap(vha, sp);
4985 }
4986}
4987
ac280b67 4988void
e315cd28 4989qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4990{
f999f4c1
AV		 4991 struct qla_work_evt *e, *tmp;
4992 unsigned long flags;
4993 LIST_HEAD(work);
0971de7f 4994
f999f4c1
AV		 4995 spin_lock_irqsave(&vha->work_lock, flags);
4996 list_splice_init(&vha->work_list, &work);
4997 spin_unlock_irqrestore(&vha->work_lock, flags);
4998
4999 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 5000 list_del_init(&e->list);
0971de7f
AV		 5001
5002 switch (e->type) {
5003 case QLA_EVT_AEN:
e315cd28 5004 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5005 e->u.aen.code, e->u.aen.data);
5006 break;
8a659571
AV		 5007 case QLA_EVT_IDC_ACK:
5008 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5009 break;
ac280b67
AV		 5010 case QLA_EVT_ASYNC_LOGIN:
5011 qla2x00_async_login(vha, e->u.logio.fcport,
5012 e->u.logio.data);
5013 break;
ac280b67
AV		 5014 case QLA_EVT_ASYNC_LOGOUT:
5015 qla2x00_async_logout(vha, e->u.logio.fcport);
5016 break;
5017 case QLA_EVT_ASYNC_LOGOUT_DONE:
5018 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5019 e->u.logio.data);
5020 break;
5ff1d584
AV		 5021 case QLA_EVT_ASYNC_ADISC:
5022 qla2x00_async_adisc(vha, e->u.logio.fcport,
5023 e->u.logio.data);
5024 break;
5025 case QLA_EVT_ASYNC_ADISC_DONE:
5026 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
5027 e->u.logio.data);
5028 break;
3420d36c
AV		 5029 case QLA_EVT_UEVENT:
5030 qla2x00_uevent_emit(vha, e->u.uevent.code);
5031 break;
8ae6d9c7
GM		 5032 case QLA_EVT_AENFX:
5033 qlafx00_process_aen(vha, e);
5034 break;
726b8548
QT		 5035 case QLA_EVT_GIDPN:
5036 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
5037 break;
5038 case QLA_EVT_GPNID:
5039 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5040 break;
e374f9f5
QT		 5041 case QLA_EVT_UNMAP:
5042 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5043 break;
9b3e0f4d
QT		 5044 case QLA_EVT_RELOGIN:
5045 qla2x00_relogin(vha);
5046 break;
726b8548
QT		 5047 case QLA_EVT_NEW_SESS:
5048 qla24xx_create_new_sess(vha, e);
5049 break;
5050 case QLA_EVT_GPDB:
5051 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5052 e->u.fcport.opt);
5053 break;
a5d42f4c
DG		 5054 case QLA_EVT_PRLI:
5055 qla24xx_async_prli(vha, e->u.fcport.fcport);
5056 break;
726b8548
QT		 5057 case QLA_EVT_GPSC:
5058 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5059 break;
726b8548
QT		 5060 case QLA_EVT_GNL:
5061 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5062 break;
5063 case QLA_EVT_NACK:
5064 qla24xx_do_nack_work(vha, e);
5065 break;
11aea16a
QT		 5066 case QLA_EVT_ASYNC_PRLO:
5067 qla2x00_async_prlo(vha, e->u.logio.fcport);
5068 break;
5069 case QLA_EVT_ASYNC_PRLO_DONE:
5070 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5071 e->u.logio.data);
5072 break;
a4239945 5073 case QLA_EVT_GPNFT:
33b28357
QT		 5074 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5075 e->u.gpnft.sp);
a4239945
QT		 5076 break;
5077 case QLA_EVT_GPNFT_DONE:
5078 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5079 break;
5080 case QLA_EVT_GNNFT_DONE:
5081 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5082 break;
5083 case QLA_EVT_GNNID:
5084 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5085 break;
5086 case QLA_EVT_GFPNID:
5087 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5088 break;
e374f9f5
QT		 5089 case QLA_EVT_SP_RETRY:
5090 qla_sp_retry(vha, e);
cc28e0ac
QT		 5091 break;
5092 case QLA_EVT_IIDMA:
5093 qla_do_iidma_work(vha, e->u.fcport.fcport);
5094 break;
8777e431
QT		 5095 case QLA_EVT_ELS_PLOGI:
5096 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5097 e->u.fcport.fcport, false);
5098 break;
0971de7f
AV		 5099 }
5100 if (e->flags & QLA_EVT_FLAG_FREE)
5101 kfree(e);
feafb7b1
AE		 5102
5103 /* For each work completed decrement vha ref count */
5104 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5105 }
e315cd28 5106}
f999f4c1 5107
9b3e0f4d
QT		 5108int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5109{
5110 struct qla_work_evt *e;
5111
5112 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5113
5114 if (!e) {
5115 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5116 return QLA_FUNCTION_FAILED;
5117 }
5118
5119 return qla2x00_post_work(vha, e);
5120}
5121
e315cd28
AC		 5122/* Relogins all the fcports of a vport
5123 * Context: dpc thread
5124 */
5125void qla2x00_relogin(struct scsi_qla_host *vha)
5126{
5127 fc_port_t *fcport;
23dd98a6 5128 int status, relogin_needed = 0;
726b8548 5129 struct event_arg ea;
e315cd28
AC		 5130
5131 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5132 /*
5133 * If the port is not ONLINE then try to login
5134 * to it if we haven't run out of retries.
5135 */
5ff1d584 5136 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5137 fcport->login_retry) {
5138 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5139 fcport->disc_state == DSC_LOGIN_COMPLETE)
5140 continue;
e315cd28 5141
23dd98a6
QT		 5142 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5143 fcport->disc_state == DSC_DELETE_PEND) {
5144 relogin_needed = 1;
5145 } else {
5146 if (vha->hw->current_topology != ISP_CFG_NL) {
5147 memset(&ea, 0, sizeof(ea));
5148 ea.event = FCME_RELOGIN;
5149 ea.fcport = fcport;
5150 qla2x00_fcport_event_handler(vha, &ea);
5151 } else if (vha->hw->current_topology ==
5152 ISP_CFG_NL) {
5153 fcport->login_retry--;
5154 status =
5155 qla2x00_local_device_login(vha,
5156 fcport);
5157 if (status == QLA_SUCCESS) {
5158 fcport->old_loop_id =
5159 fcport->loop_id;
5160 ql_dbg(ql_dbg_disc, vha, 0x2003,
5161 "Port login OK: logged in ID 0x%x.\n",
5162 fcport->loop_id);
5163 qla2x00_update_fcport
5164 (vha, fcport);
5165 } else if (status == 1) {
5166 set_bit(RELOGIN_NEEDED,
5167 &vha->dpc_flags);
5168 /* retry the login again */
5169 ql_dbg(ql_dbg_disc, vha, 0x2007,
5170 "Retrying %d login again loop_id 0x%x.\n",
5171 fcport->login_retry,
5172 fcport->loop_id);
5173 } else {
5174 fcport->login_retry = 0;
5175 }
e315cd28 5176
23dd98a6
QT		 5177 if (fcport->login_retry == 0 &&
5178 status != QLA_SUCCESS)
5179 qla2x00_clear_loop_id(fcport);
5180 }
e315cd28 5181 }
e315cd28
AC		 5182 }
5183 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5184 break;
0971de7f 5185 }
9b3e0f4d 5186
23dd98a6
QT		 5187 if (relogin_needed)
5188 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5189
9b3e0f4d
QT		 5190 ql_dbg(ql_dbg_disc, vha, 0x400e,
5191 "Relogin end.\n");
0971de7f
AV		 5192}
5193
7d613ac6
SV		 5194/* Schedule work on any of the dpc-workqueues */
5195void
5196qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5197{
5198 struct qla_hw_data *ha = base_vha->hw;
5199
5200 switch (work_code) {
5201 case MBA_IDC_AEN: /* 0x8200 */
5202 if (ha->dpc_lp_wq)
5203 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5204 break;
5205
5206 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5207 if (!ha->flags.nic_core_reset_hdlr_active) {
5208 if (ha->dpc_hp_wq)
5209 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5210 } else
5211 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5212 "NIC Core reset is already active. Skip "
5213 "scheduling it again.\n");
5214 break;
5215 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5216 if (ha->dpc_hp_wq)
5217 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5218 break;
5219 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5220 if (ha->dpc_hp_wq)
5221 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5222 break;
5223 default:
5224 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5225 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5226 }
5227
5228 return;
5229}
5230
5231/* Work: Perform NIC Core Unrecoverable state handling */
5232void
5233qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5234{
5235 struct qla_hw_data *ha =
2ad1b67c 5236 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5237 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5238 uint32_t dev_state = 0;
5239
5240 qla83xx_idc_lock(base_vha, 0);
5241 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5242 qla83xx_reset_ownership(base_vha);
5243 if (ha->flags.nic_core_reset_owner) {
5244 ha->flags.nic_core_reset_owner = 0;
5245 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5246 QLA8XXX_DEV_FAILED);
5247 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5248 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5249 }
5250 qla83xx_idc_unlock(base_vha, 0);
5251}
5252
5253/* Work: Execute IDC state handler */
5254void
5255qla83xx_idc_state_handler_work(struct work_struct *work)
5256{
5257 struct qla_hw_data *ha =
2ad1b67c 5258 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5259 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5260 uint32_t dev_state = 0;
5261
5262 qla83xx_idc_lock(base_vha, 0);
5263 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5264 if (dev_state == QLA8XXX_DEV_FAILED ||
5265 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5266 qla83xx_idc_state_handler(base_vha);
5267 qla83xx_idc_unlock(base_vha, 0);
5268}
5269
fa492630 5270static int
7d613ac6
SV		 5271qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5272{
5273 int rval = QLA_SUCCESS;
5274 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5275 uint32_t heart_beat_counter1, heart_beat_counter2;
5276
5277 do {
5278 if (time_after(jiffies, heart_beat_wait)) {
5279 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5280 "Nic Core f/w is not alive.\n");
5281 rval = QLA_FUNCTION_FAILED;
5282 break;
5283 }
5284
5285 qla83xx_idc_lock(base_vha, 0);
5286 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5287 &heart_beat_counter1);
5288 qla83xx_idc_unlock(base_vha, 0);
5289 msleep(100);
5290 qla83xx_idc_lock(base_vha, 0);
5291 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5292 &heart_beat_counter2);
5293 qla83xx_idc_unlock(base_vha, 0);
5294 } while (heart_beat_counter1 == heart_beat_counter2);
5295
5296 return rval;
5297}
5298
5299/* Work: Perform NIC Core Reset handling */
5300void
5301qla83xx_nic_core_reset_work(struct work_struct *work)
5302{
5303 struct qla_hw_data *ha =
5304 container_of(work, struct qla_hw_data, nic_core_reset);
5305 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5306 uint32_t dev_state = 0;
5307
81178772
SK		 5308 if (IS_QLA2031(ha)) {
5309 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5310 ql_log(ql_log_warn, base_vha, 0xb081,
5311 "Failed to dump mctp\n");
5312 return;
5313 }
5314
7d613ac6
SV		 5315 if (!ha->flags.nic_core_reset_hdlr_active) {
5316 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5317 qla83xx_idc_lock(base_vha, 0);
5318 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5319 &dev_state);
5320 qla83xx_idc_unlock(base_vha, 0);
5321 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5322 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5323 "Nic Core f/w is alive.\n");
5324 return;
5325 }
5326 }
5327
5328 ha->flags.nic_core_reset_hdlr_active = 1;
5329 if (qla83xx_nic_core_reset(base_vha)) {
5330 /* NIC Core reset failed. */
5331 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5332 "NIC Core reset failed.\n");
5333 }
5334 ha->flags.nic_core_reset_hdlr_active = 0;
5335 }
5336}
5337
5338/* Work: Handle 8200 IDC aens */
5339void
5340qla83xx_service_idc_aen(struct work_struct *work)
5341{
5342 struct qla_hw_data *ha =
5343 container_of(work, struct qla_hw_data, idc_aen);
5344 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5345 uint32_t dev_state, idc_control;
5346
5347 qla83xx_idc_lock(base_vha, 0);
5348 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5349 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5350 qla83xx_idc_unlock(base_vha, 0);
5351 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5352 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5353 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5354 "Application requested NIC Core Reset.\n");
5355 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5356 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5357 QLA_SUCCESS) {
5358 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5359 "Other protocol driver requested NIC Core Reset.\n");
5360 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5361 }
5362 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5363 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5364 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5365 }
5366}
5367
5368static void
5369qla83xx_wait_logic(void)
5370{
5371 int i;
5372
5373 /* Yield CPU */
5374 if (!in_interrupt()) {
5375 /*
5376 * Wait about 200ms before retrying again.
5377 * This controls the number of retries for single
5378 * lock operation.
5379 */
5380 msleep(100);
5381 schedule();
5382 } else {
5383 for (i = 0; i < 20; i++)
5384 cpu_relax(); /* This a nop instr on i386 */
5385 }
5386}
5387
fa492630 5388static int
7d613ac6
SV		 5389qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5390{
5391 int rval;
5392 uint32_t data;
5393 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5394 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5395 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5396 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5397 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5398
5399 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5400 if (rval)
5401 return rval;
5402
5403 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5404 return QLA_SUCCESS;
5405 } else {
5406 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5407 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5408 data);
5409 if (rval)
5410 return rval;
5411
5412 msleep(200);
5413
5414 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5415 &data);
5416 if (rval)
5417 return rval;
5418
5419 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5420 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5421 ~(idc_lck_rcvry_stage_mask));
5422 rval = qla83xx_wr_reg(base_vha,
5423 QLA83XX_IDC_LOCK_RECOVERY, data);
5424 if (rval)
5425 return rval;
5426
5427 /* Forcefully perform IDC UnLock */
5428 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5429 &data);
5430 if (rval)
5431 return rval;
5432 /* Clear lock-id by setting 0xff */
5433 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5434 0xff);
5435 if (rval)
5436 return rval;
5437 /* Clear lock-recovery by setting 0x0 */
5438 rval = qla83xx_wr_reg(base_vha,
5439 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5440 if (rval)
5441 return rval;
5442 } else
5443 return QLA_SUCCESS;
5444 }
5445
5446 return rval;
5447}
5448
fa492630 5449static int
7d613ac6
SV		 5450qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5451{
5452 int rval = QLA_SUCCESS;
5453 uint32_t o_drv_lockid, n_drv_lockid;
5454 unsigned long lock_recovery_timeout;
5455
5456 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5457retry_lockid:
5458 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5459 if (rval)
5460 goto exit;
5461
5462 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5463 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5464 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5465 return QLA_SUCCESS;
5466 else
5467 return QLA_FUNCTION_FAILED;
5468 }
5469
5470 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5471 if (rval)
5472 goto exit;
5473
5474 if (o_drv_lockid == n_drv_lockid) {
5475 qla83xx_wait_logic();
5476 goto retry_lockid;
5477 } else
5478 return QLA_SUCCESS;
5479
5480exit:
5481 return rval;
5482}
5483
5484void
5485qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5486{
5487 uint16_t options = (requester_id << 15) | BIT_6;
5488 uint32_t data;
6c315553 5489 uint32_t lock_owner;
7d613ac6
SV		 5490 struct qla_hw_data *ha = base_vha->hw;
5491
5492 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5493retry_lock:
5494 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5495 == QLA_SUCCESS) {
5496 if (data) {
5497 /* Setting lock-id to our function-number */
5498 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5499 ha->portnum);
5500 } else {
6c315553
SK		 5501 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5502 &lock_owner);
7d613ac6 5503 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5504 "Failed to acquire IDC lock, acquired by %d, "
5505 "retrying...\n", lock_owner);
7d613ac6
SV		 5506
5507 /* Retry/Perform IDC-Lock recovery */
5508 if (qla83xx_idc_lock_recovery(base_vha)
5509 == QLA_SUCCESS) {
5510 qla83xx_wait_logic();
5511 goto retry_lock;
5512 } else
5513 ql_log(ql_log_warn, base_vha, 0xb075,
5514 "IDC Lock recovery FAILED.\n");
5515 }
5516
5517 }
5518
5519 return;
5520
5521 /* XXX: IDC-lock implementation using access-control mbx */
5522retry_lock2:
5523 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5524 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5525 "Failed to acquire IDC lock. retrying...\n");
5526 /* Retry/Perform IDC-Lock recovery */
5527 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5528 qla83xx_wait_logic();
5529 goto retry_lock2;
5530 } else
5531 ql_log(ql_log_warn, base_vha, 0xb076,
5532 "IDC Lock recovery FAILED.\n");
5533 }
5534
5535 return;
5536}
5537
5538void
5539qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5540{
5897cb2f
BVA		 5541#if 0
5542 uint16_t options = (requester_id << 15) | BIT_7;
5543#endif
5544 uint16_t retry;
7d613ac6
SV		 5545 uint32_t data;
5546 struct qla_hw_data *ha = base_vha->hw;
5547
5548 /* IDC-unlock implementation using driver-unlock/lock-id
5549 * remote registers
5550 */
5551 retry = 0;
5552retry_unlock:
5553 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5554 == QLA_SUCCESS) {
5555 if (data == ha->portnum) {
5556 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5557 /* Clearing lock-id by setting 0xff */
5558 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5559 } else if (retry < 10) {
5560 /* SV: XXX: IDC unlock retrying needed here? */
5561
5562 /* Retry for IDC-unlock */
5563 qla83xx_wait_logic();
5564 retry++;
5565 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5566 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5567 goto retry_unlock;
5568 }
5569 } else if (retry < 10) {
5570 /* Retry for IDC-unlock */
5571 qla83xx_wait_logic();
5572 retry++;
5573 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5574 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5575 goto retry_unlock;
5576 }
5577
5578 return;
5579
5897cb2f 5580#if 0
7d613ac6
SV		 5581 /* XXX: IDC-unlock implementation using access-control mbx */
5582 retry = 0;
5583retry_unlock2:
5584 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5585 if (retry < 10) {
5586 /* Retry for IDC-unlock */
5587 qla83xx_wait_logic();
5588 retry++;
5589 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5590 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5591 goto retry_unlock2;
5592 }
5593 }
5594
5595 return;
5897cb2f 5596#endif
7d613ac6
SV		 5597}
5598
5599int
5600__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5601{
5602 int rval = QLA_SUCCESS;
5603 struct qla_hw_data *ha = vha->hw;
5604 uint32_t drv_presence;
5605
5606 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5607 if (rval == QLA_SUCCESS) {
5608 drv_presence |= (1 << ha->portnum);
5609 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5610 drv_presence);
5611 }
5612
5613 return rval;
5614}
5615
5616int
5617qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5618{
5619 int rval = QLA_SUCCESS;
5620
5621 qla83xx_idc_lock(vha, 0);
5622 rval = __qla83xx_set_drv_presence(vha);
5623 qla83xx_idc_unlock(vha, 0);
5624
5625 return rval;
5626}
5627
5628int
5629__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5630{
5631 int rval = QLA_SUCCESS;
5632 struct qla_hw_data *ha = vha->hw;
5633 uint32_t drv_presence;
5634
5635 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5636 if (rval == QLA_SUCCESS) {
5637 drv_presence &= ~(1 << ha->portnum);
5638 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5639 drv_presence);
5640 }
5641
5642 return rval;
5643}
5644
5645int
5646qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5647{
5648 int rval = QLA_SUCCESS;
5649
5650 qla83xx_idc_lock(vha, 0);
5651 rval = __qla83xx_clear_drv_presence(vha);
5652 qla83xx_idc_unlock(vha, 0);
5653
5654 return rval;
5655}
5656
fa492630 5657static void
7d613ac6
SV		 5658qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5659{
5660 struct qla_hw_data *ha = vha->hw;
5661 uint32_t drv_ack, drv_presence;
5662 unsigned long ack_timeout;
5663
5664 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5665 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5666 while (1) {
5667 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5668 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5669 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5670 break;
5671
5672 if (time_after_eq(jiffies, ack_timeout)) {
5673 ql_log(ql_log_warn, vha, 0xb067,
5674 "RESET ACK TIMEOUT! drv_presence=0x%x "
5675 "drv_ack=0x%x\n", drv_presence, drv_ack);
5676 /*
5677 * The function(s) which did not ack in time are forced
5678 * to withdraw any further participation in the IDC
5679 * reset.
5680 */
5681 if (drv_ack != drv_presence)
5682 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5683 drv_ack);
5684 break;
5685 }
5686
5687 qla83xx_idc_unlock(vha, 0);
5688 msleep(1000);
5689 qla83xx_idc_lock(vha, 0);
5690 }
5691
5692 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5693 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5694}
5695
fa492630 5696static int
7d613ac6
SV		 5697qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5698{
5699 int rval = QLA_SUCCESS;
5700 uint32_t idc_control;
5701
5702 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5703 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5704
5705 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5706 __qla83xx_get_idc_control(vha, &idc_control);
5707 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5708 __qla83xx_set_idc_control(vha, 0);
5709
5710 qla83xx_idc_unlock(vha, 0);
5711 rval = qla83xx_restart_nic_firmware(vha);
5712 qla83xx_idc_lock(vha, 0);
5713
5714 if (rval != QLA_SUCCESS) {
5715 ql_log(ql_log_fatal, vha, 0xb06a,
5716 "Failed to restart NIC f/w.\n");
5717 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5718 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5719 } else {
5720 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5721 "Success in restarting nic f/w.\n");
5722 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5723 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5724 }
5725
5726 return rval;
5727}
5728
5729/* Assumes idc_lock always held on entry */
5730int
5731qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5732{
5733 struct qla_hw_data *ha = base_vha->hw;
5734 int rval = QLA_SUCCESS;
5735 unsigned long dev_init_timeout;
5736 uint32_t dev_state;
5737
5738 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5739 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5740
5741 while (1) {
5742
5743 if (time_after_eq(jiffies, dev_init_timeout)) {
5744 ql_log(ql_log_warn, base_vha, 0xb06e,
5745 "Initialization TIMEOUT!\n");
5746 /* Init timeout. Disable further NIC Core
5747 * communication.
5748 */
5749 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5750 QLA8XXX_DEV_FAILED);
5751 ql_log(ql_log_info, base_vha, 0xb06f,
5752 "HW State: FAILED.\n");
5753 }
5754
5755 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5756 switch (dev_state) {
5757 case QLA8XXX_DEV_READY:
5758 if (ha->flags.nic_core_reset_owner)
5759 qla83xx_idc_audit(base_vha,
5760 IDC_AUDIT_COMPLETION);
5761 ha->flags.nic_core_reset_owner = 0;
5762 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5763 "Reset_owner reset by 0x%x.\n",
5764 ha->portnum);
5765 goto exit;
5766 case QLA8XXX_DEV_COLD:
5767 if (ha->flags.nic_core_reset_owner)
5768 rval = qla83xx_device_bootstrap(base_vha);
5769 else {
5770 /* Wait for AEN to change device-state */
5771 qla83xx_idc_unlock(base_vha, 0);
5772 msleep(1000);
5773 qla83xx_idc_lock(base_vha, 0);
5774 }
5775 break;
5776 case QLA8XXX_DEV_INITIALIZING:
5777 /* Wait for AEN to change device-state */
5778 qla83xx_idc_unlock(base_vha, 0);
5779 msleep(1000);
5780 qla83xx_idc_lock(base_vha, 0);
5781 break;
5782 case QLA8XXX_DEV_NEED_RESET:
5783 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5784 qla83xx_need_reset_handler(base_vha);
5785 else {
5786 /* Wait for AEN to change device-state */
5787 qla83xx_idc_unlock(base_vha, 0);
5788 msleep(1000);
5789 qla83xx_idc_lock(base_vha, 0);
5790 }
5791 /* reset timeout value after need reset handler */
5792 dev_init_timeout = jiffies +
5793 (ha->fcoe_dev_init_timeout * HZ);
5794 break;
5795 case QLA8XXX_DEV_NEED_QUIESCENT:
5796 /* XXX: DEBUG for now */
5797 qla83xx_idc_unlock(base_vha, 0);
5798 msleep(1000);
5799 qla83xx_idc_lock(base_vha, 0);
5800 break;
5801 case QLA8XXX_DEV_QUIESCENT:
5802 /* XXX: DEBUG for now */
5803 if (ha->flags.quiesce_owner)
5804 goto exit;
5805
5806 qla83xx_idc_unlock(base_vha, 0);
5807 msleep(1000);
5808 qla83xx_idc_lock(base_vha, 0);
5809 dev_init_timeout = jiffies +
5810 (ha->fcoe_dev_init_timeout * HZ);
5811 break;
5812 case QLA8XXX_DEV_FAILED:
5813 if (ha->flags.nic_core_reset_owner)
5814 qla83xx_idc_audit(base_vha,
5815 IDC_AUDIT_COMPLETION);
5816 ha->flags.nic_core_reset_owner = 0;
5817 __qla83xx_clear_drv_presence(base_vha);
5818 qla83xx_idc_unlock(base_vha, 0);
5819 qla8xxx_dev_failed_handler(base_vha);
5820 rval = QLA_FUNCTION_FAILED;
5821 qla83xx_idc_lock(base_vha, 0);
5822 goto exit;
5823 case QLA8XXX_BAD_VALUE:
5824 qla83xx_idc_unlock(base_vha, 0);
5825 msleep(1000);
5826 qla83xx_idc_lock(base_vha, 0);
5827 break;
5828 default:
5829 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5830 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5831 qla83xx_idc_unlock(base_vha, 0);
5832 qla8xxx_dev_failed_handler(base_vha);
5833 rval = QLA_FUNCTION_FAILED;
5834 qla83xx_idc_lock(base_vha, 0);
5835 goto exit;
5836 }
5837 }
5838
5839exit:
5840 return rval;
5841}
5842
f3ddac19
CD		 5843void
5844qla2x00_disable_board_on_pci_error(struct work_struct *work)
5845{
5846 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5847 board_disable);
5848 struct pci_dev *pdev = ha->pdev;
5849 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5850
726b8548
QT		 5851 /*
5852 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5853 * where it was set first.
5854 */
5855 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5856 return;
5857
f3ddac19
CD		 5858 ql_log(ql_log_warn, base_vha, 0x015b,
5859 "Disabling adapter.\n");
5860
efdb5760
SC		 5861 if (!atomic_read(&pdev->enable_cnt)) {
5862 ql_log(ql_log_info, base_vha, 0xfffc,
5863 "PCI device disabled, no action req for PCI error=%lx\n",
5864 base_vha->pci_flags);
5865 return;
5866 }
5867
726b8548
QT		 5868 qla2x00_wait_for_sess_deletion(base_vha);
5869
f3ddac19
CD		 5870 set_bit(UNLOADING, &base_vha->dpc_flags);
5871
5872 qla2x00_delete_all_vps(ha, base_vha);
5873
5874 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5875
5876 qla2x00_dfs_remove(base_vha);
5877
5878 qla84xx_put_chip(base_vha);
5879
5880 if (base_vha->timer_active)
5881 qla2x00_stop_timer(base_vha);
5882
5883 base_vha->flags.online = 0;
5884
5885 qla2x00_destroy_deferred_work(ha);
5886
5887 /*
5888 * Do not try to stop beacon blink as it will issue a mailbox
5889 * command.
5890 */
5891 qla2x00_free_sysfs_attr(base_vha, false);
5892
5893 fc_remove_host(base_vha->host);
5894
5895 scsi_remove_host(base_vha->host);
5896
5897 base_vha->flags.init_done = 0;
5898 qla25xx_delete_queues(base_vha);
f3ddac19 5899 qla2x00_free_fcports(base_vha);
093df737 5900 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5901 qla2x00_mem_free(ha);
5902 qla82xx_md_free(base_vha);
5903 qla2x00_free_queues(ha);
5904
f3ddac19
CD		 5905 qla2x00_unmap_iobases(ha);
5906
5907 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5908 pci_disable_pcie_error_reporting(pdev);
5909 pci_disable_device(pdev);
f3ddac19 5910
beb9e315
JL		 5911 /*
5912 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5913 */
f3ddac19
CD		 5914}
5915
1da177e4
LT		 5916/**************************************************************************
5917* qla2x00_do_dpc
5918* This kernel thread is a task that is schedule by the interrupt handler
5919* to perform the background processing for interrupts.
5920*
5921* Notes:
5922* This task always run in the context of a kernel thread. It
5923* is kick-off by the driver's detect code and starts up
5924* up one per adapter. It immediately goes to sleep and waits for
5925* some fibre event. When either the interrupt handler or
5926* the timer routine detects a event it will one of the task
5927* bits then wake us up.
5928**************************************************************************/
5929static int
5930qla2x00_do_dpc(void *data)
5931{
e315cd28
AC		 5932 scsi_qla_host_t *base_vha;
5933 struct qla_hw_data *ha;
d7459527
MH		 5934 uint32_t online;
5935 struct qla_qpair *qpair;
1da177e4 5936
e315cd28
AC		 5937 ha = (struct qla_hw_data *)data;
5938 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5939
8698a745 5940 set_user_nice(current, MIN_NICE);
1da177e4 5941
563585ec 5942 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5943 while (!kthread_should_stop()) {
7c3df132
SK		 5944 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5945 "DPC handler sleeping.\n");
1da177e4 5946
39a11240 5947 schedule();
1da177e4 5948
c142caf0
AV		 5949 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5950 goto end_loop;
1da177e4 5951
85880801 5952 if (ha->flags.eeh_busy) {
7c3df132
SK		 5953 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5954 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5955 goto end_loop;
85880801
AV		 5956 }
5957
1da177e4
LT		 5958 ha->dpc_active = 1;
5959
5f28d2d7
SK		 5960 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5961 "DPC handler waking up, dpc_flags=0x%lx.\n",
5962 base_vha->dpc_flags);
1da177e4 5963
a29b3dd7
JC		 5964 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5965 break;
5966
7ec0effd
AD		 5967 if (IS_P3P_TYPE(ha)) {
5968 if (IS_QLA8044(ha)) {
5969 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5970 &base_vha->dpc_flags)) {
5971 qla8044_idc_lock(ha);
5972 qla8044_wr_direct(base_vha,
5973 QLA8044_CRB_DEV_STATE_INDEX,
5974 QLA8XXX_DEV_FAILED);
5975 qla8044_idc_unlock(ha);
5976 ql_log(ql_log_info, base_vha, 0x4004,
5977 "HW State: FAILED.\n");
5978 qla8044_device_state_handler(base_vha);
5979 continue;
5980 }
5981
5982 } else {
5983 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5984 &base_vha->dpc_flags)) {
5985 qla82xx_idc_lock(ha);
5986 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5987 QLA8XXX_DEV_FAILED);
5988 qla82xx_idc_unlock(ha);
5989 ql_log(ql_log_info, base_vha, 0x0151,
5990 "HW State: FAILED.\n");
5991 qla82xx_device_state_handler(base_vha);
5992 continue;
5993 }
a9083016
GM		 5994 }
5995
5996 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5997 &base_vha->dpc_flags)) {
5998
7c3df132
SK		 5999 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6000 "FCoE context reset scheduled.\n");
a9083016
GM		 6001 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6002 &base_vha->dpc_flags))) {
6003 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6004 /* FCoE-ctx reset failed.
6005 * Escalate to chip-reset
6006 */
6007 set_bit(ISP_ABORT_NEEDED,
6008 &base_vha->dpc_flags);
6009 }
6010 clear_bit(ABORT_ISP_ACTIVE,
6011 &base_vha->dpc_flags);
6012 }
6013
7c3df132
SK		 6014 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6015 "FCoE context reset end.\n");
a9083016 6016 }
8ae6d9c7
GM		 6017 } else if (IS_QLAFX00(ha)) {
6018 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6019 &base_vha->dpc_flags)) {
6020 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6021 "Firmware Reset Recovery\n");
6022 if (qlafx00_reset_initialize(base_vha)) {
6023 /* Failed. Abort isp later. */
6024 if (!test_bit(UNLOADING,
f92f82d6 6025 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6026 set_bit(ISP_UNRECOVERABLE,
6027 &base_vha->dpc_flags);
6028 ql_dbg(ql_dbg_dpc, base_vha,
6029 0x4021,
6030 "Reset Recovery Failed\n");
f92f82d6 6031 }
8ae6d9c7
GM		 6032 }
6033 }
6034
6035 if (test_and_clear_bit(FX00_TARGET_SCAN,
6036 &base_vha->dpc_flags)) {
6037 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6038 "ISPFx00 Target Scan scheduled\n");
6039 if (qlafx00_rescan_isp(base_vha)) {
6040 if (!test_bit(UNLOADING,
6041 &base_vha->dpc_flags))
6042 set_bit(ISP_UNRECOVERABLE,
6043 &base_vha->dpc_flags);
6044 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6045 "ISPFx00 Target Scan Failed\n");
6046 }
6047 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6048 "ISPFx00 Target Scan End\n");
6049 }
e8f5e95d
AB		 6050 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6051 &base_vha->dpc_flags)) {
6052 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6053 "ISPFx00 Host Info resend scheduled\n");
6054 qlafx00_fx_disc(base_vha,
6055 &base_vha->hw->mr.fcport,
6056 FXDISC_REG_HOST_INFO);
6057 }
a9083016
GM		 6058 }
6059
e4e3a2ce
QT		 6060 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6061 &base_vha->dpc_flags) &&
6062 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6063 qla24xx_detect_sfp(base_vha);
6064
6065 if (ha->flags.detected_lr_sfp !=
6066 ha->flags.using_lr_setting)
6067 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6068 }
6069
b08abbd9
QT		 6070 if (test_and_clear_bit
6071 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6072 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6073 bool do_reset = true;
6074
6075 switch (ql2x_ini_mode) {
6076 case QLA2XXX_INI_MODE_ENABLED:
6077 break;
6078 case QLA2XXX_INI_MODE_DISABLED:
6079 if (!qla_tgt_mode_enabled(base_vha))
6080 do_reset = false;
6081 break;
6082 case QLA2XXX_INI_MODE_DUAL:
6083 if (!qla_dual_mode_enabled(base_vha))
6084 do_reset = false;
6085 break;
6086 default:
6087 break;
6088 }
1da177e4 6089
93eca613 6090 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6091 &base_vha->dpc_flags))) {
93eca613
QT		 6092 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6093 "ISP abort scheduled.\n");
a9083016 6094 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6095 /* failed. retry later */
6096 set_bit(ISP_ABORT_NEEDED,
e315cd28 6097 &base_vha->dpc_flags);
99363ef8 6098 }
e315cd28
AC		 6099 clear_bit(ABORT_ISP_ACTIVE,
6100 &base_vha->dpc_flags);
93eca613
QT		 6101 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6102 "ISP abort end.\n");
99363ef8 6103 }
1da177e4
LT		 6104 }
6105
a394aac8
DJ		 6106 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6107 &base_vha->dpc_flags)) {
e315cd28 6108 qla2x00_update_fcports(base_vha);
c9c5ced9 6109 }
d97994dc 6110
8ae6d9c7
GM		 6111 if (IS_QLAFX00(ha))
6112 goto loop_resync_check;
6113
579d12b5 6114 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6115 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6116 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6117 if (IS_P3P_TYPE(ha)) {
6118 if (IS_QLA82XX(ha))
6119 qla82xx_device_state_handler(base_vha);
6120 if (IS_QLA8044(ha))
6121 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6122 clear_bit(ISP_QUIESCE_NEEDED,
6123 &base_vha->dpc_flags);
6124 if (!ha->flags.quiesce_owner) {
6125 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6126 if (IS_QLA82XX(ha)) {
6127 qla82xx_idc_lock(ha);
6128 qla82xx_clear_qsnt_ready(
6129 base_vha);
6130 qla82xx_idc_unlock(ha);
6131 } else if (IS_QLA8044(ha)) {
6132 qla8044_idc_lock(ha);
6133 qla8044_clear_qsnt_ready(
6134 base_vha);
6135 qla8044_idc_unlock(ha);
6136 }
8fcd6b8b
CD		 6137 }
6138 } else {
6139 clear_bit(ISP_QUIESCE_NEEDED,
6140 &base_vha->dpc_flags);
6141 qla2x00_quiesce_io(base_vha);
579d12b5 6142 }
7c3df132
SK		 6143 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6144 "Quiescence mode end.\n");
579d12b5
SK		 6145 }
6146
e315cd28 6147 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6148 &base_vha->dpc_flags) &&
e315cd28 6149 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6150
7c3df132
SK		 6151 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6152 "Reset marker scheduled.\n");
e315cd28
AC		 6153 qla2x00_rst_aen(base_vha);
6154 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6155 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6156 "Reset marker end.\n");
1da177e4
LT		 6157 }
6158
6159 /* Retry each device up to login retry count */
4005a995 6160 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6161 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6162 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6163
4005a995
QT		 6164 if (!base_vha->relogin_jif ||
6165 time_after_eq(jiffies, base_vha->relogin_jif)) {
6166 base_vha->relogin_jif = jiffies + HZ;
6167 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6168
9b3e0f4d 6169 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6170 "Relogin scheduled.\n");
9b3e0f4d 6171 qla24xx_post_relogin_work(base_vha);
4005a995 6172 }
1da177e4 6173 }
8ae6d9c7 6174loop_resync_check:
e315cd28 6175 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6176 &base_vha->dpc_flags)) {
1da177e4 6177
7c3df132
SK		 6178 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6179 "Loop resync scheduled.\n");
1da177e4
LT		 6180
6181 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6182 &base_vha->dpc_flags))) {
1da177e4 6183
52c82823 6184 qla2x00_loop_resync(base_vha);
1da177e4 6185
e315cd28
AC		 6186 clear_bit(LOOP_RESYNC_ACTIVE,
6187 &base_vha->dpc_flags);
1da177e4
LT		 6188 }
6189
7c3df132
SK		 6190 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6191 "Loop resync end.\n");
1da177e4
LT		 6192 }
6193
8ae6d9c7
GM		 6194 if (IS_QLAFX00(ha))
6195 goto intr_on_check;
6196
e315cd28
AC		 6197 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6198 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6199 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6200 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6201 }
6202
8ae6d9c7 6203intr_on_check:
1da177e4 6204 if (!ha->interrupts_on)
fd34f556 6205 ha->isp_ops->enable_intrs(ha);
1da177e4 6206
e315cd28 6207 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6208 &base_vha->dpc_flags)) {
6209 if (ha->beacon_blink_led == 1)
6210 ha->isp_ops->beacon_blink(base_vha);
6211 }
f6df144c 6212
d7459527
MH		 6213 /* qpair online check */
6214 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6215 &base_vha->dpc_flags)) {
6216 if (ha->flags.eeh_busy ||
6217 ha->flags.pci_channel_io_perm_failure)
6218 online = 0;
6219 else
6220 online = 1;
6221
6222 mutex_lock(&ha->mq_lock);
6223 list_for_each_entry(qpair, &base_vha->qp_list,
6224 qp_list_elem)
6225 qpair->online = online;
6226 mutex_unlock(&ha->mq_lock);
6227 }
6228
8b4673ba
QT		 6229 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6230 &base_vha->dpc_flags)) {
deeae7a6
DG		 6231 ql_log(ql_log_info, base_vha, 0xffffff,
6232 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6233 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6234 if (qla27xx_set_zio_threshold(base_vha,
6235 ha->nvme_last_rptd_aen)) {
deeae7a6 6236 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6237 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6238 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6239 }
6240 }
6241
8b4673ba
QT		 6242 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6243 &base_vha->dpc_flags)) {
6244 ql_log(ql_log_info, base_vha, 0xffffff,
6245 "SET ZIO Activity exchange threshold to %d.\n",
6246 ha->last_zio_threshold);
6247 qla27xx_set_zio_threshold(base_vha,
6248 ha->last_zio_threshold);
6249 }
6250
8ae6d9c7
GM		 6251 if (!IS_QLAFX00(ha))
6252 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6253
48acad09
QT		 6254 if (test_and_clear_bit(N2N_LINK_RESET,
6255 &base_vha->dpc_flags)) {
6256 qla2x00_lip_reset(base_vha);
6257 }
6258
1da177e4 6259 ha->dpc_active = 0;
c142caf0 6260end_loop:
563585ec 6261 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6262 } /* End of while(1) */
563585ec 6263 __set_current_state(TASK_RUNNING);
1da177e4 6264
7c3df132
SK		 6265 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6266 "DPC handler exiting.\n");
1da177e4
LT		 6267
6268 /*
6269 * Make sure that nobody tries to wake us up again.
6270 */
1da177e4
LT		 6271 ha->dpc_active = 0;
6272
ac280b67
AV		 6273 /* Cleanup any residual CTX SRBs. */
6274 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6275
39a11240
CH		 6276 return 0;
6277}
6278
6279void
e315cd28 6280qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6281{
e315cd28 6282 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6283 struct task_struct *t = ha->dpc_thread;
6284
e315cd28 6285 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6286 wake_up_process(t);
1da177e4
LT		 6287}
6288
1da177e4
LT		 6289/*
6290* qla2x00_rst_aen
6291* Processes asynchronous reset.
6292*
6293* Input:
6294* ha = adapter block pointer.
6295*/
6296static void
e315cd28 6297qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6298{
e315cd28
AC		 6299 if (vha->flags.online && !vha->flags.reset_active &&
6300 !atomic_read(&vha->loop_down_timer) &&
6301 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6302 do {
e315cd28 6303 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6304
6305 /*
6306 * Issue marker command only when we are going to start
6307 * the I/O.
6308 */
e315cd28
AC		 6309 vha->marker_needed = 1;
6310 } while (!atomic_read(&vha->loop_down_timer) &&
6311 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6312 }
6313}
6314
1da177e4
LT		 6315/**************************************************************************
6316* qla2x00_timer
6317*
6318* Description:
6319* One second timer
6320*
6321* Context: Interrupt
6322***************************************************************************/
2c3dfe3f 6323void
8e5f4ba0 6324qla2x00_timer(struct timer_list *t)
1da177e4 6325{
8e5f4ba0 6326 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6327 unsigned long cpu_flags = 0;
1da177e4
LT		 6328 int start_dpc = 0;
6329 int index;
6330 srb_t *sp;
85880801 6331 uint16_t w;
e315cd28 6332 struct qla_hw_data *ha = vha->hw;
73208dfd 6333 struct req_que *req;
85880801 6334
a5b36321 6335 if (ha->flags.eeh_busy) {
7c3df132
SK		 6336 ql_dbg(ql_dbg_timer, vha, 0x6000,
6337 "EEH = %d, restarting timer.\n",
6338 ha->flags.eeh_busy);
a5b36321
LC		 6339 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6340 return;
6341 }
6342
f3ddac19
CD		 6343 /*
6344 * Hardware read to raise pending EEH errors during mailbox waits. If
6345 * the read returns -1 then disable the board.
6346 */
6347 if (!pci_channel_offline(ha->pdev)) {
85880801 6348 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6349 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6350 }
1da177e4 6351
cefcaba6 6352 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6353 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6354 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6355 start_dpc++;
7ec0effd
AD		 6356 if (IS_QLA82XX(ha))
6357 qla82xx_watchdog(vha);
6358 else if (IS_QLA8044(ha))
6359 qla8044_watchdog(vha);
579d12b5
SK		 6360 }
6361
8ae6d9c7
GM		 6362 if (!vha->vp_idx && IS_QLAFX00(ha))
6363 qlafx00_timer_routine(vha);
6364
1da177e4 6365 /* Loop down handler. */
e315cd28 6366 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6367 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6368 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6369 && vha->flags.online) {
1da177e4 6370
e315cd28
AC		 6371 if (atomic_read(&vha->loop_down_timer) ==
6372 vha->loop_down_abort_time) {
1da177e4 6373
7c3df132
SK		 6374 ql_log(ql_log_info, vha, 0x6008,
6375 "Loop down - aborting the queues before time expires.\n");
1da177e4 6376
e315cd28
AC		 6377 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6378 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6379
f08b7251
AV		 6380 /*
6381 * Schedule an ISP abort to return any FCP2-device
6382 * commands.
6383 */
2c3dfe3f 6384 /* NPIV - scan physical port only */
e315cd28 6385 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6386 spin_lock_irqsave(&ha->hardware_lock,
6387 cpu_flags);
73208dfd 6388 req = ha->req_q_map[0];
2c3dfe3f 6389 for (index = 1;
8d93f550 6390 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6391 index++) {
6392 fc_port_t *sfcp;
6393
e315cd28 6394 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6395 if (!sp)
6396 continue;
c5419e26
QT		 6397 if (sp->cmd_type != TYPE_SRB)
6398 continue;
9ba56b95 6399 if (sp->type != SRB_SCSI_CMD)
cf53b069 6400 continue;
2c3dfe3f 6401 sfcp = sp->fcport;
f08b7251 6402 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6403 continue;
bdf79621 6404
8f7daead
GM		 6405 if (IS_QLA82XX(ha))
6406 set_bit(FCOE_CTX_RESET_NEEDED,
6407 &vha->dpc_flags);
6408 else
6409 set_bit(ISP_ABORT_NEEDED,
e315cd28 6410 &vha->dpc_flags);
2c3dfe3f
SJ		 6411 break;
6412 }
6413 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6414 cpu_flags);
1da177e4 6415 }
1da177e4
LT		 6416 start_dpc++;
6417 }
6418
6419 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6420 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6421 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6422 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6423 "Loop down - aborting ISP.\n");
6424
8f7daead
GM		 6425 if (IS_QLA82XX(ha))
6426 set_bit(FCOE_CTX_RESET_NEEDED,
6427 &vha->dpc_flags);
6428 else
6429 set_bit(ISP_ABORT_NEEDED,
6430 &vha->dpc_flags);
1da177e4
LT		 6431 }
6432 }
7c3df132
SK		 6433 ql_dbg(ql_dbg_timer, vha, 0x600a,
6434 "Loop down - seconds remaining %d.\n",
6435 atomic_read(&vha->loop_down_timer));
1da177e4 6436 }
cefcaba6
SK		 6437 /* Check if beacon LED needs to be blinked for physical host only */
6438 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6439 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6440 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6441 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6442 start_dpc++;
6443 }
f6df144c
AV		 6444 }
6445
550bf57d 6446 /* Process any deferred work. */
9b3e0f4d
QT		 6447 if (!list_empty(&vha->work_list)) {
6448 unsigned long flags;
6449 bool q = false;
6450
6451 spin_lock_irqsave(&vha->work_lock, flags);
6452 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6453 q = true;
6454 spin_unlock_irqrestore(&vha->work_lock, flags);
6455 if (q)
6456 queue_work(vha->hw->wq, &vha->iocb_work);
6457 }
550bf57d 6458
7401bc18
DG		 6459 /*
6460 * FC-NVME
6461 * see if the active AEN count has changed from what was last reported.
6462 */
8b4673ba
QT		 6463 if (!vha->vp_idx && (atomic_read(&ha->nvme_active_aen_cnt) !=
6464 ha->nvme_last_rptd_aen) && ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6465 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6466 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6467 ha->nvme_last_rptd_aen);
deeae7a6 6468 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6469 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6470 start_dpc++;
6471 }
6472
6473 if (!vha->vp_idx &&
6474 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6475 (ha->zio_mode == QLA_ZIO_MODE_6) &&
6476 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
6477 ql_log(ql_log_info, vha, 0x3002,
6478 "Sched: Set ZIO exchange threshold to %d.\n",
6479 ha->last_zio_threshold);
6480 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6481 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6482 start_dpc++;
7401bc18
DG		 6483 }
6484
1da177e4 6485 /* Schedule the DPC routine if needed */
e315cd28
AC		 6486 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6487 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6488 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6489 start_dpc ||
e315cd28
AC		 6490 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6491 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6492 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6493 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6494 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6495 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6496 ql_dbg(ql_dbg_timer, vha, 0x600b,
6497 "isp_abort_needed=%d loop_resync_needed=%d "
6498 "fcport_update_needed=%d start_dpc=%d "
6499 "reset_marker_needed=%d",
6500 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6501 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6502 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6503 start_dpc,
6504 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6505 ql_dbg(ql_dbg_timer, vha, 0x600c,
6506 "beacon_blink_needed=%d isp_unrecoverable=%d "
6507 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6508 "relogin_needed=%d.\n",
7c3df132
SK		 6509 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6510 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6511 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6512 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6513 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6514 qla2xxx_wake_dpc(vha);
7c3df132 6515 }
1da177e4 6516
e315cd28 6517 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6518}
6519
5433383e
AV		 6520/* Firmware interface routines. */
6521
f73cb695 6522#define FW_BLOBS 11
5433383e
AV		 6523#define FW_ISP21XX 0
6524#define FW_ISP22XX 1
6525#define FW_ISP2300 2
6526#define FW_ISP2322 3
48c02fde 6527#define FW_ISP24XX 4
c3a2f0df 6528#define FW_ISP25XX 5
3a03eb79 6529#define FW_ISP81XX 6
a9083016 6530#define FW_ISP82XX 7
6246b8a1
GM		 6531#define FW_ISP2031 8
6532#define FW_ISP8031 9
2c5bbbb2 6533#define FW_ISP27XX 10
5433383e 6534
bb8ee499
AV		 6535#define FW_FILE_ISP21XX "ql2100_fw.bin"
6536#define FW_FILE_ISP22XX "ql2200_fw.bin"
6537#define FW_FILE_ISP2300 "ql2300_fw.bin"
6538#define FW_FILE_ISP2322 "ql2322_fw.bin"
6539#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6540#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6541#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6542#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6543#define FW_FILE_ISP2031 "ql2600_fw.bin"
6544#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6545#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6546
bb8ee499 6547
e1e82b6f 6548static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6549
6550static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6551 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6552 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6553 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6554 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6555 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6556 { .name = FW_FILE_ISP25XX, },
3a03eb79 6557 { .name = FW_FILE_ISP81XX, },
a9083016 6558 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6559 { .name = FW_FILE_ISP2031, },
6560 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6561 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6562};
6563
6564struct fw_blob *
e315cd28 6565qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6566{
e315cd28 6567 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6568 struct fw_blob *blob;
6569
5433383e
AV		 6570 if (IS_QLA2100(ha)) {
6571 blob = &qla_fw_blobs[FW_ISP21XX];
6572 } else if (IS_QLA2200(ha)) {
6573 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6574 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6575 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6576 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6577 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6578 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6579 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6580 } else if (IS_QLA25XX(ha)) {
6581 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6582 } else if (IS_QLA81XX(ha)) {
6583 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6584 } else if (IS_QLA82XX(ha)) {
6585 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6586 } else if (IS_QLA2031(ha)) {
6587 blob = &qla_fw_blobs[FW_ISP2031];
6588 } else if (IS_QLA8031(ha)) {
6589 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6590 } else if (IS_QLA27XX(ha)) {
6591 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6592 } else {
6593 return NULL;
5433383e
AV		 6594 }
6595
e1e82b6f 6596 mutex_lock(&qla_fw_lock);
5433383e
AV		 6597 if (blob->fw)
6598 goto out;
6599
6600 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6601 ql_log(ql_log_warn, vha, 0x0063,
6602 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6603 blob->fw = NULL;
6604 blob = NULL;
6605 goto out;
6606 }
6607
6608out:
e1e82b6f 6609 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6610 return blob;
6611}
6612
6613static void
6614qla2x00_release_firmware(void)
6615{
6616 int idx;
6617
e1e82b6f 6618 mutex_lock(&qla_fw_lock);
5433383e 6619 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6620 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6621 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6622}
6623
14e660e6
SJ		 6624static pci_ers_result_t
6625qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6626{
85880801
AV		 6627 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6628 struct qla_hw_data *ha = vha->hw;
6629
7c3df132
SK		 6630 ql_dbg(ql_dbg_aer, vha, 0x9000,
6631 "PCI error detected, state %x.\n", state);
b9b12f73 6632
efdb5760
SC		 6633 if (!atomic_read(&pdev->enable_cnt)) {
6634 ql_log(ql_log_info, vha, 0xffff,
6635 "PCI device is disabled,state %x\n", state);
6636 return PCI_ERS_RESULT_NEED_RESET;
6637 }
6638
14e660e6
SJ		 6639 switch (state) {
6640 case pci_channel_io_normal:
85880801 6641 ha->flags.eeh_busy = 0;
c38d1baf 6642 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6643 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6644 qla2xxx_wake_dpc(vha);
6645 }
14e660e6
SJ		 6646 return PCI_ERS_RESULT_CAN_RECOVER;
6647 case pci_channel_io_frozen:
85880801 6648 ha->flags.eeh_busy = 1;
a5b36321
LC		 6649 /* For ISP82XX complete any pending mailbox cmd */
6650 if (IS_QLA82XX(ha)) {
7190575f 6651 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6652 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6653 qla82xx_clear_pending_mbx(vha);
a5b36321 6654 }
90a86fc0 6655 qla2x00_free_irqs(vha);
14e660e6 6656 pci_disable_device(pdev);
bddd2d65
LC		 6657 /* Return back all IOs */
6658 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6659 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6660 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6661 qla2xxx_wake_dpc(vha);
6662 }
14e660e6
SJ		 6663 return PCI_ERS_RESULT_NEED_RESET;
6664 case pci_channel_io_perm_failure:
85880801
AV		 6665 ha->flags.pci_channel_io_perm_failure = 1;
6666 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6667 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6668 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6669 qla2xxx_wake_dpc(vha);
6670 }
14e660e6
SJ		 6671 return PCI_ERS_RESULT_DISCONNECT;
6672 }
6673 return PCI_ERS_RESULT_NEED_RESET;
6674}
6675
6676static pci_ers_result_t
6677qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6678{
6679 int risc_paused = 0;
6680 uint32_t stat;
6681 unsigned long flags;
e315cd28
AC		 6682 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6683 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6684 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6685 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6686
bcc5b6d3
SK		 6687 if (IS_QLA82XX(ha))
6688 return PCI_ERS_RESULT_RECOVERED;
6689
14e660e6
SJ		 6690 spin_lock_irqsave(&ha->hardware_lock, flags);
6691 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6692 stat = RD_REG_DWORD(&reg->hccr);
6693 if (stat & HCCR_RISC_PAUSE)
6694 risc_paused = 1;
6695 } else if (IS_QLA23XX(ha)) {
6696 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6697 if (stat & HSR_RISC_PAUSED)
6698 risc_paused = 1;
6699 } else if (IS_FWI2_CAPABLE(ha)) {
6700 stat = RD_REG_DWORD(&reg24->host_status);
6701 if (stat & HSRX_RISC_PAUSED)
6702 risc_paused = 1;
6703 }
6704 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6705
6706 if (risc_paused) {
7c3df132
SK		 6707 ql_log(ql_log_info, base_vha, 0x9003,
6708 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6709 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6710
6711 return PCI_ERS_RESULT_NEED_RESET;
6712 } else
6713 return PCI_ERS_RESULT_RECOVERED;
6714}
6715
fa492630
SK		 6716static uint32_t
6717qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6718{
6719 uint32_t rval = QLA_FUNCTION_FAILED;
6720 uint32_t drv_active = 0;
6721 struct qla_hw_data *ha = base_vha->hw;
6722 int fn;
6723 struct pci_dev *other_pdev = NULL;
6724
7c3df132
SK		 6725 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6726 "Entered %s.\n", __func__);
a5b36321
LC		 6727
6728 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6729
6730 if (base_vha->flags.online) {
6731 /* Abort all outstanding commands,
6732 * so as to be requeued later */
6733 qla2x00_abort_isp_cleanup(base_vha);
6734 }
6735
6736
6737 fn = PCI_FUNC(ha->pdev->devfn);
6738 while (fn > 0) {
6739 fn--;
7c3df132
SK		 6740 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6741 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6742 other_pdev =
6743 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6744 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6745 fn));
6746
6747 if (!other_pdev)
6748 continue;
6749 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6750 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6751 "Found PCI func available and enable at 0x%x.\n",
6752 fn);
a5b36321
LC		 6753 pci_dev_put(other_pdev);
6754 break;
6755 }
6756 pci_dev_put(other_pdev);
6757 }
6758
6759 if (!fn) {
6760 /* Reset owner */
7c3df132
SK		 6761 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6762 "This devfn is reset owner = 0x%x.\n",
6763 ha->pdev->devfn);
a5b36321
LC		 6764 qla82xx_idc_lock(ha);
6765
6766 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6767 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6768
6769 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6770 QLA82XX_IDC_VERSION);
6771
6772 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6773 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6774 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6775
6776 qla82xx_idc_unlock(ha);
6777 /* Reset if device is not already reset
6778 * drv_active would be 0 if a reset has already been done
6779 */
6780 if (drv_active)
6781 rval = qla82xx_start_firmware(base_vha);
6782 else
6783 rval = QLA_SUCCESS;
6784 qla82xx_idc_lock(ha);
6785
6786 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6787 ql_log(ql_log_info, base_vha, 0x900b,
6788 "HW State: FAILED.\n");
a5b36321
LC		 6789 qla82xx_clear_drv_active(ha);
6790 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6791 QLA8XXX_DEV_FAILED);
a5b36321 6792 } else {
7c3df132
SK		 6793 ql_log(ql_log_info, base_vha, 0x900c,
6794 "HW State: READY.\n");
a5b36321 6795 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6796 QLA8XXX_DEV_READY);
a5b36321 6797 qla82xx_idc_unlock(ha);
7190575f 6798 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6799 rval = qla82xx_restart_isp(base_vha);
6800 qla82xx_idc_lock(ha);
6801 /* Clear driver state register */
6802 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6803 qla82xx_set_drv_active(base_vha);
6804 }
6805 qla82xx_idc_unlock(ha);
6806 } else {
7c3df132
SK		 6807 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6808 "This devfn is not reset owner = 0x%x.\n",
6809 ha->pdev->devfn);
a5b36321 6810 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6811 QLA8XXX_DEV_READY)) {
7190575f 6812 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6813 rval = qla82xx_restart_isp(base_vha);
6814 qla82xx_idc_lock(ha);
6815 qla82xx_set_drv_active(base_vha);
6816 qla82xx_idc_unlock(ha);
6817 }
6818 }
6819 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6820
6821 return rval;
6822}
6823
14e660e6
SJ		 6824static pci_ers_result_t
6825qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6826{
6827 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6828 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6829 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6830 struct rsp_que *rsp;
6831 int rc, retries = 10;
09483916 6832
7c3df132
SK		 6833 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6834 "Slot Reset.\n");
85880801 6835
90a86fc0
JC		 6836 /* Workaround: qla2xxx driver which access hardware earlier
6837 * needs error state to be pci_channel_io_online.
6838 * Otherwise mailbox command timesout.
6839 */
6840 pdev->error_state = pci_channel_io_normal;
6841
6842 pci_restore_state(pdev);
6843
8c1496bd
RL		 6844 /* pci_restore_state() clears the saved_state flag of the device
6845 * save restored state which resets saved_state flag
6846 */
6847 pci_save_state(pdev);
6848
09483916
BH		 6849 if (ha->mem_only)
6850 rc = pci_enable_device_mem(pdev);
6851 else
6852 rc = pci_enable_device(pdev);
14e660e6 6853
09483916 6854 if (rc) {
7c3df132 6855 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6856 "Can't re-enable PCI device after reset.\n");
a5b36321 6857 goto exit_slot_reset;
14e660e6 6858 }
14e660e6 6859
90a86fc0
JC		 6860 rsp = ha->rsp_q_map[0];
6861 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6862 goto exit_slot_reset;
90a86fc0 6863
e315cd28 6864 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6865 goto exit_slot_reset;
6866
6867 if (IS_QLA82XX(ha)) {
6868 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6869 ret = PCI_ERS_RESULT_RECOVERED;
6870 goto exit_slot_reset;
6871 } else
6872 goto exit_slot_reset;
6873 }
14e660e6 6874
90a86fc0
JC		 6875 while (ha->flags.mbox_busy && retries--)
6876 msleep(1000);
85880801 6877
e315cd28 6878 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6879 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6880 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6881 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6882
90a86fc0 6883
a5b36321 6884exit_slot_reset:
7c3df132
SK		 6885 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6886 "slot_reset return %x.\n", ret);
85880801 6887
14e660e6
SJ		 6888 return ret;
6889}
6890
6891static void
6892qla2xxx_pci_resume(struct pci_dev *pdev)
6893{
e315cd28
AC		 6894 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6895 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6896 int ret;
6897
7c3df132
SK		 6898 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6899 "pci_resume.\n");
85880801 6900
e315cd28 6901 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6902 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6903 ql_log(ql_log_fatal, base_vha, 0x9002,
6904 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6905 }
85880801 6906
3e46f031
LC		 6907 pci_cleanup_aer_uncorrect_error_status(pdev);
6908
85880801 6909 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6910}
6911
5601236b
MH		 6912static int qla2xxx_map_queues(struct Scsi_Host *shost)
6913{
d68b850e 6914 int rc;
5601236b
MH		 6915 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6916
d68b850e
QT		 6917 if (USER_CTRL_IRQ(vha->hw))
6918 rc = blk_mq_map_queues(&shost->tag_set);
6919 else
f23f5bec 6920 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0);
d68b850e 6921 return rc;
5601236b
MH		 6922}
6923
a55b2d21 6924static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6925 .error_detected = qla2xxx_pci_error_detected,
6926 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6927 .slot_reset = qla2xxx_pci_slot_reset,
6928 .resume = qla2xxx_pci_resume,
6929};
6930
5433383e 6931static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6932 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6933 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6934 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6935 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6936 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6937 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6938 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6939 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6940 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6941 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6942 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6943 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6944 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6945 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6946 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6947 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6948 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6949 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6950 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6951 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6952 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6953 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6954 { 0 },
6955};
6956MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6957
fca29703 6958static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6959 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6960 .driver = {
6961 .owner = THIS_MODULE,
6962 },
fca29703 6963 .id_table = qla2xxx_pci_tbl,
7ee61397 6964 .probe = qla2x00_probe_one,
4c993f76 6965 .remove = qla2x00_remove_one,
e30d1756 6966 .shutdown = qla2x00_shutdown,
14e660e6 6967 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6968};
6969
75ef9de1 6970static const struct file_operations apidev_fops = {
6a03b4cd 6971 .owner = THIS_MODULE,
6038f373 6972 .llseek = noop_llseek,
6a03b4cd
HZ		 6973};
6974
1da177e4
LT		 6975/**
6976 * qla2x00_module_init - Module initialization.
6977 **/
6978static int __init
6979qla2x00_module_init(void)
6980{
fca29703
AV		 6981 int ret = 0;
6982
1da177e4 6983 /* Allocate cache for SRBs. */
354d6b21 6984 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6985 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6986 if (srb_cachep == NULL) {
7c3df132
SK		 6987 ql_log(ql_log_fatal, NULL, 0x0001,
6988 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6989 return -ENOMEM;
6990 }
6991
2d70c103
NB		 6992 /* Initialize target kmem_cache and mem_pools */
6993 ret = qlt_init();
6994 if (ret < 0) {
6995 kmem_cache_destroy(srb_cachep);
6996 return ret;
6997 } else if (ret > 0) {
6998 /*
6999 * If initiator mode is explictly disabled by qlt_init(),
7000 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7001 * performing scsi_scan_target() during LOOP UP event.
7002 */
7003 qla2xxx_transport_functions.disable_target_scan = 1;
7004 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7005 }
7006
1da177e4
LT		 7007 /* Derive version string. */
7008 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7009 if (ql2xextended_error_logging)
0181944f 7010 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7011 if (ql2xextended_error_logging == 1)
7012 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7013
1c97a12a
AV		 7014 qla2xxx_transport_template =
7015 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 7016 if (!qla2xxx_transport_template) {
7017 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 7018 ql_log(ql_log_fatal, NULL, 0x0002,
7019 "fc_attach_transport failed...Failing load!.\n");
2d70c103 7020 qlt_exit();
1da177e4 7021 return -ENODEV;
2c3dfe3f 7022 }
6a03b4cd
HZ		 7023
7024 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7025 if (apidev_major < 0) {
7c3df132
SK		 7026 ql_log(ql_log_fatal, NULL, 0x0003,
7027 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7028 }
7029
2c3dfe3f
SJ		 7030 qla2xxx_transport_vport_template =
7031 fc_attach_transport(&qla2xxx_transport_vport_functions);
7032 if (!qla2xxx_transport_vport_template) {
7033 kmem_cache_destroy(srb_cachep);
2d70c103 7034 qlt_exit();
2c3dfe3f 7035 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 7036 ql_log(ql_log_fatal, NULL, 0x0004,
7037 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 7038 return -ENODEV;
2c3dfe3f 7039 }
7c3df132
SK		 7040 ql_log(ql_log_info, NULL, 0x0005,
7041 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7042 qla2x00_version_str);
7ee61397 7043 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 7044 if (ret) {
7045 kmem_cache_destroy(srb_cachep);
2d70c103 7046 qlt_exit();
fca29703 7047 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 7048 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 7049 ql_log(ql_log_fatal, NULL, 0x0006,
7050 "pci_register_driver failed...ret=%d Failing load!.\n",
7051 ret);
fca29703
AV		 7052 }
7053 return ret;
1da177e4
LT		 7054}
7055
7056/**
7057 * qla2x00_module_exit - Module cleanup.
7058 **/
7059static void __exit
7060qla2x00_module_exit(void)
7061{
6a03b4cd 7062 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 7063 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7064 qla2x00_release_firmware();
354d6b21 7065 kmem_cache_destroy(srb_cachep);
2d70c103 7066 qlt_exit();
a9083016
GM		 7067 if (ctx_cachep)
7068 kmem_cache_destroy(ctx_cachep);
1da177e4 7069 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 7070 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 7071}
7072
7073module_init(qla2x00_module_init);
7074module_exit(qla2x00_module_exit);
7075
7076MODULE_AUTHOR("QLogic Corporation");
7077MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7078MODULE_LICENSE("GPL");
7079MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7080MODULE_FIRMWARE(FW_FILE_ISP21XX);
7081MODULE_FIRMWARE(FW_FILE_ISP22XX);
7082MODULE_FIRMWARE(FW_FILE_ISP2300);
7083MODULE_FIRMWARE(FW_FILE_ISP2322);
7084MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7085MODULE_FIRMWARE(FW_FILE_ISP25XX);
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