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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[mirror_ubuntu-eoan-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
41dc529a
QT		 240int ql2xmvasynctoatio = 1;
241module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
242MODULE_PARM_DESC(ql2xmvasynctoatio,
243 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
244 "0 (Default). Do not move IOCBs"
245 "1 - Move IOCBs.");
246
1da177e4 247/*
fa2a1ce5 248 * SCSI host template entry points
1da177e4
LT		 249 */
250static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 251static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 252static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
253static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 254static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 255static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 256static int qla2xxx_eh_abort(struct scsi_cmnd *);
257static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 258static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 259static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
260static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 261
1a2fbf18 262static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 263static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 264static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 265static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 266
a5326f86 267struct scsi_host_template qla2xxx_driver_template = {
1da177e4 268 .module = THIS_MODULE,
cb63067a 269 .name = QLA2XXX_DRIVER_NAME,
a5326f86 270 .queuecommand = qla2xxx_queuecommand,
fca29703 271
b6a05c82 272 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 273 .eh_abort_handler = qla2xxx_eh_abort,
274 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 275 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 276 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
277 .eh_host_reset_handler = qla2xxx_eh_host_reset,
278
279 .slave_configure = qla2xxx_slave_configure,
280
281 .slave_alloc = qla2xxx_slave_alloc,
282 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 283 .scan_finished = qla2xxx_scan_finished,
284 .scan_start = qla2xxx_scan_start,
db5ed4df 285 .change_queue_depth = scsi_change_queue_depth,
5601236b 286 .map_queues = qla2xxx_map_queues,
fca29703
AV		 287 .this_id = -1,
288 .cmd_per_lun = 3,
289 .use_clustering = ENABLE_CLUSTERING,
290 .sg_tablesize = SG_ALL,
291
292 .max_sectors = 0xFFFF,
afb046e2 293 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 294
295 .supported_mode = MODE_INITIATOR,
c40ecc12 296 .track_queue_depth = 1,
fca29703
AV		 297};
298
1da177e4 299static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 300struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 301
1da177e4
LT		 302/* TODO Convert to inlines
303 *
304 * Timer routines
305 */
1da177e4 306
2c3dfe3f 307__inline__ void
e315cd28 308qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 309{
e315cd28
AC		 310 init_timer(&vha->timer);
311 vha->timer.expires = jiffies + interval * HZ;
312 vha->timer.data = (unsigned long)vha;
313 vha->timer.function = (void (*)(unsigned long))func;
314 add_timer(&vha->timer);
315 vha->timer_active = 1;
1da177e4
LT		 316}
317
318static inline void
e315cd28 319qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 320{
a9083016 321 /* Currently used for 82XX only. */
7c3df132
SK		 322 if (vha->device_flags & DFLG_DEV_FAILED) {
323 ql_dbg(ql_dbg_timer, vha, 0x600d,
324 "Device in a failed state, returning.\n");
a9083016 325 return;
7c3df132 326 }
a9083016 327
e315cd28 328 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 329}
330
a824ebb3 331static __inline__ void
e315cd28 332qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 333{
e315cd28
AC		 334 del_timer_sync(&vha->timer);
335 vha->timer_active = 0;
1da177e4
LT		 336}
337
1da177e4
LT		 338static int qla2x00_do_dpc(void *data);
339
340static void qla2x00_rst_aen(scsi_qla_host_t *);
341
73208dfd
AC		 342static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
343 struct req_que **, struct rsp_que **);
e30d1756 344static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 345static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 346int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
347 struct qla_qpair *qpair);
1da177e4 348
1da177e4 349/* -------------------------------------------------------------------------- */
9a347ff4
CD		 350static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
351 struct rsp_que *rsp)
73208dfd 352{
7c3df132 353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 354 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 355 GFP_KERNEL);
356 if (!ha->req_q_map) {
7c3df132
SK		 357 ql_log(ql_log_fatal, vha, 0x003b,
358 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 359 goto fail_req_map;
360 }
361
2afa19a9 362 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 363 GFP_KERNEL);
364 if (!ha->rsp_q_map) {
7c3df132
SK		 365 ql_log(ql_log_fatal, vha, 0x003c,
366 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 367 goto fail_rsp_map;
368 }
d7459527
MH		 369
370 if (ql2xmqsupport && ha->max_qpairs) {
371 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
372 GFP_KERNEL);
373 if (!ha->queue_pair_map) {
374 ql_log(ql_log_fatal, vha, 0x0180,
375 "Unable to allocate memory for queue pair ptrs.\n");
376 goto fail_qpair_map;
377 }
378 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
379 if (ha->base_qpair == NULL) {
380 ql_log(ql_log_warn, vha, 0x0182,
381 "Failed to allocate base queue pair memory.\n");
382 goto fail_base_qpair;
383 }
384 ha->base_qpair->req = req;
385 ha->base_qpair->rsp = rsp;
386 }
387
9a347ff4
CD		 388 /*
389 * Make sure we record at least the request and response queue zero in
390 * case we need to free them if part of the probe fails.
391 */
392 ha->rsp_q_map[0] = rsp;
393 ha->req_q_map[0] = req;
73208dfd
AC		 394 set_bit(0, ha->rsp_qid_map);
395 set_bit(0, ha->req_qid_map);
396 return 1;
397
d7459527
MH		 398fail_base_qpair:
399 kfree(ha->queue_pair_map);
400fail_qpair_map:
401 kfree(ha->rsp_q_map);
402 ha->rsp_q_map = NULL;
73208dfd
AC		 403fail_rsp_map:
404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
406fail_req_map:
407 return -ENOMEM;
408}
409
2afa19a9 410static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 411{
8ae6d9c7
GM		 412 if (IS_QLAFX00(ha)) {
413 if (req && req->ring_fx00)
414 dma_free_coherent(&ha->pdev->dev,
415 (req->length_fx00 + 1) * sizeof(request_t),
416 req->ring_fx00, req->dma_fx00);
417 } else if (req && req->ring)
73208dfd
AC		 418 dma_free_coherent(&ha->pdev->dev,
419 (req->length + 1) * sizeof(request_t),
420 req->ring, req->dma);
421
8d93f550
CD		 422 if (req)
423 kfree(req->outstanding_cmds);
424
73208dfd
AC		 425 kfree(req);
426 req = NULL;
427}
428
2afa19a9
AC		 429static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
430{
8ae6d9c7
GM		 431 if (IS_QLAFX00(ha)) {
432 if (rsp && rsp->ring)
433 dma_free_coherent(&ha->pdev->dev,
434 (rsp->length_fx00 + 1) * sizeof(request_t),
435 rsp->ring_fx00, rsp->dma_fx00);
436 } else if (rsp && rsp->ring) {
2afa19a9
AC		 437 dma_free_coherent(&ha->pdev->dev,
438 (rsp->length + 1) * sizeof(response_t),
439 rsp->ring, rsp->dma);
8ae6d9c7 440 }
2afa19a9
AC		 441 kfree(rsp);
442 rsp = NULL;
443}
444
73208dfd
AC		 445static void qla2x00_free_queues(struct qla_hw_data *ha)
446{
447 struct req_que *req;
448 struct rsp_que *rsp;
449 int cnt;
093df737 450 unsigned long flags;
73208dfd 451
093df737 452 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 453 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 454 if (!test_bit(cnt, ha->req_qid_map))
455 continue;
456
73208dfd 457 req = ha->req_q_map[cnt];
093df737
QT		 458 clear_bit(cnt, ha->req_qid_map);
459 ha->req_q_map[cnt] = NULL;
460
461 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 462 qla2x00_free_req_que(ha, req);
093df737 463 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 464 }
093df737
QT		 465 spin_unlock_irqrestore(&ha->hardware_lock, flags);
466
73208dfd
AC		 467 kfree(ha->req_q_map);
468 ha->req_q_map = NULL;
2afa19a9 469
093df737
QT		 470
471 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 472 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 473 if (!test_bit(cnt, ha->rsp_qid_map))
474 continue;
475
2afa19a9 476 rsp = ha->rsp_q_map[cnt];
c3c42394 477 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 478 ha->rsp_q_map[cnt] = NULL;
479 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 480 qla2x00_free_rsp_que(ha, rsp);
093df737 481 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 482 }
093df737
QT		 483 spin_unlock_irqrestore(&ha->hardware_lock, flags);
484
2afa19a9
AC		 485 kfree(ha->rsp_q_map);
486 ha->rsp_q_map = NULL;
73208dfd
AC		 487}
488
1da177e4 489static char *
e315cd28 490qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 491{
e315cd28 492 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 493 static char *pci_bus_modes[] = {
494 "33", "66", "100", "133",
495 };
496 uint16_t pci_bus;
497
498 strcpy(str, "PCI");
499 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
500 if (pci_bus) {
501 strcat(str, "-X (");
502 strcat(str, pci_bus_modes[pci_bus]);
503 } else {
504 pci_bus = (ha->pci_attr & BIT_8) >> 8;
505 strcat(str, " (");
506 strcat(str, pci_bus_modes[pci_bus]);
507 }
508 strcat(str, " MHz)");
509
510 return (str);
511}
512
fca29703 513static char *
e315cd28 514qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 515{
516 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 517 struct qla_hw_data *ha = vha->hw;
fca29703 518 uint32_t pci_bus;
fca29703 519
62a276f8 520 if (pci_is_pcie(ha->pdev)) {
fca29703 521 char lwstr[6];
62a276f8 522 uint32_t lstat, lspeed, lwidth;
fca29703 523
62a276f8
BH		 524 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
525 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
526 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 527
528 strcpy(str, "PCIe (");
49300af7
SK		 529 switch (lspeed) {
530 case 1:
c87a0d8c 531 strcat(str, "2.5GT/s ");
49300af7
SK		 532 break;
533 case 2:
c87a0d8c 534 strcat(str, "5.0GT/s ");
49300af7
SK		 535 break;
536 case 3:
537 strcat(str, "8.0GT/s ");
538 break;
539 default:
fca29703 540 strcat(str, "<unknown> ");
49300af7
SK		 541 break;
542 }
fca29703
AV		 543 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
544 strcat(str, lwstr);
545
546 return str;
547 }
548
549 strcpy(str, "PCI");
550 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
551 if (pci_bus == 0 || pci_bus == 8) {
552 strcat(str, " (");
553 strcat(str, pci_bus_modes[pci_bus >> 3]);
554 } else {
555 strcat(str, "-X ");
556 if (pci_bus & BIT_2)
557 strcat(str, "Mode 2");
558 else
559 strcat(str, "Mode 1");
560 strcat(str, " (");
561 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
562 }
563 strcat(str, " MHz)");
564
565 return str;
566}
567
e5f82ab8 568static char *
df57caba 569qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 570{
571 char un_str[10];
e315cd28 572 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 573
df57caba
HM		 574 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
575 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 576
577 if (ha->fw_attributes & BIT_9) {
578 strcat(str, "FLX");
579 return (str);
580 }
581
582 switch (ha->fw_attributes & 0xFF) {
583 case 0x7:
584 strcat(str, "EF");
585 break;
586 case 0x17:
587 strcat(str, "TP");
588 break;
589 case 0x37:
590 strcat(str, "IP");
591 break;
592 case 0x77:
593 strcat(str, "VI");
594 break;
595 default:
596 sprintf(un_str, "(%x)", ha->fw_attributes);
597 strcat(str, un_str);
598 break;
599 }
600 if (ha->fw_attributes & 0x100)
601 strcat(str, "X");
602
603 return (str);
604}
605
e5f82ab8 606static char *
df57caba 607qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 608{
e315cd28 609 struct qla_hw_data *ha = vha->hw;
f0883ac6 610
df57caba 611 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 612 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 613 return str;
fca29703
AV		 614}
615
9ba56b95 616void
25ff6af1 617qla2x00_sp_free_dma(void *ptr)
fca29703 618{
25ff6af1
JC		 619 srb_t *sp = ptr;
620 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 621 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 622 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 623
9ba56b95
GM		 624 if (sp->flags & SRB_DMA_VALID) {
625 scsi_dma_unmap(cmd);
626 sp->flags &= ~SRB_DMA_VALID;
7c3df132 627 }
fca29703 628
9ba56b95
GM		 629 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
630 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
631 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
632 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
633 }
634
635 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
636 /* List assured to be having elements */
f83adb61 637 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 638 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
639 }
640
641 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
642 dma_pool_free(ha->dl_dma_pool, ctx,
643 ((struct crc_context *)ctx)->crc_ctx_dma);
644 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
645 }
646
647 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
648 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 649
9ba56b95
GM		 650 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
651 ctx1->fcp_cmnd_dma);
652 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
653 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
654 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
655 mempool_free(ctx1, ha->ctx_mempool);
656 ctx1 = NULL;
657 }
658
659 CMD_SP(cmd) = NULL;
25ff6af1 660 qla2x00_rel_sp(sp);
9ba56b95
GM		 661}
662
d7459527 663void
25ff6af1 664qla2x00_sp_compl(void *ptr, int res)
9ba56b95 665{
25ff6af1 666 srb_t *sp = ptr;
9ba56b95
GM		 667 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
668
669 cmd->result = res;
670
671 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 672 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 673 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
674 sp, GET_CMD_SP(sp));
675 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 676 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 677 return;
678 }
679 if (!atomic_dec_and_test(&sp->ref_count))
680 return;
681
25ff6af1 682 qla2x00_sp_free_dma(sp);
9ba56b95 683 cmd->scsi_done(cmd);
fca29703
AV		 684}
685
d7459527 686void
25ff6af1 687qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 688{
689 srb_t *sp = (srb_t *)ptr;
690 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
691 struct qla_hw_data *ha = sp->fcport->vha->hw;
692 void *ctx = GET_CMD_CTX_SP(sp);
693
694 if (sp->flags & SRB_DMA_VALID) {
695 scsi_dma_unmap(cmd);
696 sp->flags &= ~SRB_DMA_VALID;
697 }
698
699 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
700 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
701 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
702 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
703 }
704
705 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
706 /* List assured to be having elements */
707 qla2x00_clean_dsd_pool(ha, sp, NULL);
708 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
709 }
710
711 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
712 dma_pool_free(ha->dl_dma_pool, ctx,
713 ((struct crc_context *)ctx)->crc_ctx_dma);
714 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
715 }
716
717 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
718 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
719
720 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
721 ctx1->fcp_cmnd_dma);
722 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
723 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
724 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
725 mempool_free(ctx1, ha->ctx_mempool);
726 }
727
728 CMD_SP(cmd) = NULL;
729 qla2xxx_rel_qpair_sp(sp->qpair, sp);
730}
731
732void
25ff6af1 733qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 734{
25ff6af1 735 srb_t *sp = ptr;
d7459527
MH		 736 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
737
738 cmd->result = res;
739
740 if (atomic_read(&sp->ref_count) == 0) {
741 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
742 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
743 sp, GET_CMD_SP(sp));
744 if (ql2xextended_error_logging & ql_dbg_io)
745 WARN_ON(atomic_read(&sp->ref_count) == 0);
746 return;
747 }
748 if (!atomic_dec_and_test(&sp->ref_count))
749 return;
750
25ff6af1 751 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 752 cmd->scsi_done(cmd);
753}
754
8ae6d9c7
GM		 755/* If we are SP1 here, we need to still take and release the host_lock as SP1
756 * does not have the changes necessary to avoid taking host->host_lock.
757 */
1da177e4 758static int
f5e3e40b 759qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 760{
134ae078 761 scsi_qla_host_t *vha = shost_priv(host);
fca29703 762 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 763 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 764 struct qla_hw_data *ha = vha->hw;
765 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 766 srb_t *sp;
767 int rval;
5601236b
MH		 768 struct qla_qpair *qpair = NULL;
769 uint32_t tag;
770 uint16_t hwq;
fca29703 771
04dfaa53
MFO		 772 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
773 cmd->result = DID_NO_CONNECT << 16;
774 goto qc24_fail_command;
775 }
776
5601236b
MH		 777 if (ha->mqenable) {
778 if (shost_use_blk_mq(vha->host)) {
779 tag = blk_mq_unique_tag(cmd->request);
780 hwq = blk_mq_unique_tag_to_hwq(tag);
781 qpair = ha->queue_pair_map[hwq];
782 } else if (vha->vp_idx && vha->qpair) {
783 qpair = vha->qpair;
784 }
785
786 if (qpair)
787 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 788 }
789
85880801 790 if (ha->flags.eeh_busy) {
7c3df132 791 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 792 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 793 "PCI Channel IO permanent failure, exiting "
794 "cmd=%p.\n", cmd);
b9b12f73 795 cmd->result = DID_NO_CONNECT << 16;
7c3df132 796 } else {
5f28d2d7 797 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 798 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 799 cmd->result = DID_REQUEUE << 16;
7c3df132 800 }
14e660e6
SJ		 801 goto qc24_fail_command;
802 }
803
19a7b4ae
JSEC		 804 rval = fc_remote_port_chkready(rport);
805 if (rval) {
806 cmd->result = rval;
5f28d2d7 807 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 808 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
809 cmd, rval);
fca29703
AV		 810 goto qc24_fail_command;
811 }
812
bad75002
AE		 813 if (!vha->flags.difdix_supported &&
814 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 815 ql_dbg(ql_dbg_io, vha, 0x3004,
816 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
817 cmd);
bad75002
AE		 818 cmd->result = DID_NO_CONNECT << 16;
819 goto qc24_fail_command;
820 }
aa651be8
CD		 821
822 if (!fcport) {
823 cmd->result = DID_NO_CONNECT << 16;
824 goto qc24_fail_command;
825 }
826
fca29703
AV		 827 if (atomic_read(&fcport->state) != FCS_ONLINE) {
828 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 829 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 830 ql_dbg(ql_dbg_io, vha, 0x3005,
831 "Returning DNC, fcport_state=%d loop_state=%d.\n",
832 atomic_read(&fcport->state),
833 atomic_read(&base_vha->loop_state));
fca29703
AV		 834 cmd->result = DID_NO_CONNECT << 16;
835 goto qc24_fail_command;
836 }
7b594131 837 goto qc24_target_busy;
fca29703
AV		 838 }
839
e05fe292
CD		 840 /*
841 * Return target busy if we've received a non-zero retry_delay_timer
842 * in a FCP_RSP.
843 */
975f7d46
BP		 844 if (fcport->retry_delay_timestamp == 0) {
845 /* retry delay not set */
846 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 847 fcport->retry_delay_timestamp = 0;
848 else
849 goto qc24_target_busy;
850
b00ee7d7 851 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 852 if (!sp)
f5e3e40b 853 goto qc24_host_busy;
fca29703 854
9ba56b95
GM		 855 sp->u.scmd.cmd = cmd;
856 sp->type = SRB_SCSI_CMD;
857 atomic_set(&sp->ref_count, 1);
858 CMD_SP(cmd) = (void *)sp;
859 sp->free = qla2x00_sp_free_dma;
860 sp->done = qla2x00_sp_compl;
861
e315cd28 862 rval = ha->isp_ops->start_scsi(sp);
7c3df132 863 if (rval != QLA_SUCCESS) {
53016ed3 864 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 865 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 866 goto qc24_host_busy_free_sp;
7c3df132 867 }
fca29703 868
fca29703
AV		 869 return 0;
870
871qc24_host_busy_free_sp:
25ff6af1 872 qla2x00_sp_free_dma(sp);
fca29703 873
f5e3e40b 874qc24_host_busy:
fca29703
AV		 875 return SCSI_MLQUEUE_HOST_BUSY;
876
7b594131
MC		 877qc24_target_busy:
878 return SCSI_MLQUEUE_TARGET_BUSY;
879
fca29703 880qc24_fail_command:
f5e3e40b 881 cmd->scsi_done(cmd);
fca29703
AV		 882
883 return 0;
884}
885
d7459527
MH		 886/* For MQ supported I/O */
887int
888qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
889 struct qla_qpair *qpair)
890{
891 scsi_qla_host_t *vha = shost_priv(host);
892 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
893 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
894 struct qla_hw_data *ha = vha->hw;
895 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
896 srb_t *sp;
897 int rval;
898
899 rval = fc_remote_port_chkready(rport);
900 if (rval) {
901 cmd->result = rval;
902 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
903 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
904 cmd, rval);
905 goto qc24_fail_command;
906 }
907
908 if (!fcport) {
909 cmd->result = DID_NO_CONNECT << 16;
910 goto qc24_fail_command;
911 }
912
913 if (atomic_read(&fcport->state) != FCS_ONLINE) {
914 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
915 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
916 ql_dbg(ql_dbg_io, vha, 0x3077,
917 "Returning DNC, fcport_state=%d loop_state=%d.\n",
918 atomic_read(&fcport->state),
919 atomic_read(&base_vha->loop_state));
920 cmd->result = DID_NO_CONNECT << 16;
921 goto qc24_fail_command;
922 }
923 goto qc24_target_busy;
924 }
925
926 /*
927 * Return target busy if we've received a non-zero retry_delay_timer
928 * in a FCP_RSP.
929 */
930 if (fcport->retry_delay_timestamp == 0) {
931 /* retry delay not set */
932 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
933 fcport->retry_delay_timestamp = 0;
934 else
935 goto qc24_target_busy;
936
937 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
938 if (!sp)
939 goto qc24_host_busy;
940
941 sp->u.scmd.cmd = cmd;
942 sp->type = SRB_SCSI_CMD;
943 atomic_set(&sp->ref_count, 1);
944 CMD_SP(cmd) = (void *)sp;
945 sp->free = qla2xxx_qpair_sp_free_dma;
946 sp->done = qla2xxx_qpair_sp_compl;
947 sp->qpair = qpair;
948
949 rval = ha->isp_ops->start_scsi_mq(sp);
950 if (rval != QLA_SUCCESS) {
951 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
952 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
953 if (rval == QLA_INTERFACE_ERROR)
954 goto qc24_fail_command;
955 goto qc24_host_busy_free_sp;
956 }
957
958 return 0;
959
960qc24_host_busy_free_sp:
25ff6af1 961 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 962
963qc24_host_busy:
964 return SCSI_MLQUEUE_HOST_BUSY;
965
966qc24_target_busy:
967 return SCSI_MLQUEUE_TARGET_BUSY;
968
969qc24_fail_command:
970 cmd->scsi_done(cmd);
971
972 return 0;
973}
974
1da177e4
LT		 975/*
976 * qla2x00_eh_wait_on_command
977 * Waits for the command to be returned by the Firmware for some
978 * max time.
979 *
980 * Input:
1da177e4 981 * cmd = Scsi Command to wait on.
1da177e4
LT		 982 *
983 * Return:
984 * Not Found : 0
985 * Found : 1
986 */
987static int
e315cd28 988qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 989{
fe74c71f 990#define ABORT_POLLING_PERIOD 1000
478c3b03 991#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 992 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 993 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
994 struct qla_hw_data *ha = vha->hw;
f4f051eb 995 int ret = QLA_SUCCESS;
1da177e4 996
85880801 997 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 998 ql_dbg(ql_dbg_taskm, vha, 0x8005,
999 "Return:eh_wait.\n");
85880801
AV		 1000 return ret;
1001 }
1002
d970432c 1003 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1004 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1005 }
1006 if (CMD_SP(cmd))
1007 ret = QLA_FUNCTION_FAILED;
1da177e4 1008
f4f051eb 1009 return ret;
1da177e4
LT		 1010}
1011
1012/*
1013 * qla2x00_wait_for_hba_online
fa2a1ce5 1014 * Wait till the HBA is online after going through
1da177e4
LT		 1015 * <= MAX_RETRIES_OF_ISP_ABORT or
1016 * finally HBA is disabled ie marked offline
1017 *
1018 * Input:
1019 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1020 *
1021 * Note:
1da177e4
LT		 1022 * Does context switching-Release SPIN_LOCK
1023 * (if any) before calling this routine.
1024 *
1025 * Return:
1026 * Success (Adapter is online) : 0
1027 * Failed (Adapter is offline/disabled) : 1
1028 */
854165f4 1029int
e315cd28 1030qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1031{
fca29703
AV		 1032 int return_status;
1033 unsigned long wait_online;
e315cd28
AC		 1034 struct qla_hw_data *ha = vha->hw;
1035 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1036
fa2a1ce5 1037 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1038 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1039 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1040 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1041 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1042
1043 msleep(1000);
1044 }
e315cd28 1045 if (base_vha->flags.online)
fa2a1ce5 1046 return_status = QLA_SUCCESS;
1da177e4
LT		 1047 else
1048 return_status = QLA_FUNCTION_FAILED;
1049
1da177e4
LT		 1050 return (return_status);
1051}
1052
726b8548
QT		 1053static inline int test_fcport_count(scsi_qla_host_t *vha)
1054{
1055 struct qla_hw_data *ha = vha->hw;
1056 unsigned long flags;
1057 int res;
1058
1059 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1060 ql_dbg(ql_dbg_init, vha, 0xffff,
1061 "tgt %p, fcport_count=%d\n",
1062 vha, vha->fcport_count);
1063 res = (vha->fcport_count == 0);
1064 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1065
1066 return res;
1067}
1068
1069/*
1070 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1071 * it has dependency on UNLOADING flag to stop device discovery
1072 */
1073static void
1074qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1075{
1076 qla2x00_mark_all_devices_lost(vha, 0);
1077
1078 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1079}
1080
86fbee86 1081/*
638a1a01
SC		 1082 * qla2x00_wait_for_hba_ready
1083 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1084 *
1085 * Input:
1086 * ha - pointer to host adapter structure
1087 *
1088 * Note:
1089 * Does context switching-Release SPIN_LOCK
1090 * (if any) before calling this routine.
1091 *
86fbee86 1092 */
638a1a01
SC		 1093static void
1094qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1095{
86fbee86 1096 struct qla_hw_data *ha = vha->hw;
783e0dc4 1097 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1098
1d483901
DC		 1099 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1100 ha->flags.mbox_busy) ||
1101 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1102 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1103 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1104 break;
86fbee86 1105 msleep(1000);
783e0dc4 1106 }
86fbee86
LC		 1107}
1108
2533cf67
LC		 1109int
1110qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1111{
1112 int return_status;
1113 unsigned long wait_reset;
1114 struct qla_hw_data *ha = vha->hw;
1115 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1116
1117 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1118 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1119 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1120 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1121 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1122
1123 msleep(1000);
1124
1125 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1126 ha->flags.chip_reset_done)
1127 break;
1128 }
1129 if (ha->flags.chip_reset_done)
1130 return_status = QLA_SUCCESS;
1131 else
1132 return_status = QLA_FUNCTION_FAILED;
1133
1134 return return_status;
1135}
1136
083a469d
GM		 1137static void
1138sp_get(struct srb *sp)
1139{
1140 atomic_inc(&sp->ref_count);
1141}
1142
a465537a
SC		 1143#define ISP_REG_DISCONNECT 0xffffffffU
1144/**************************************************************************
1145* qla2x00_isp_reg_stat
1146*
1147* Description:
1148* Read the host status register of ISP before aborting the command.
1149*
1150* Input:
1151* ha = pointer to host adapter structure.
1152*
1153*
1154* Returns:
1155* Either true or false.
1156*
1157* Note: Return true if there is register disconnect.
1158**************************************************************************/
1159static inline
1160uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1161{
1162 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1163
1164 return ((RD_REG_DWORD(&reg->host_status)) == ISP_REG_DISCONNECT);
1165}
1166
1da177e4
LT		 1167/**************************************************************************
1168* qla2xxx_eh_abort
1169*
1170* Description:
1171* The abort function will abort the specified command.
1172*
1173* Input:
1174* cmd = Linux SCSI command packet to be aborted.
1175*
1176* Returns:
1177* Either SUCCESS or FAILED.
1178*
1179* Note:
2ea00202 1180* Only return FAILED if command not returned by firmware.
1da177e4 1181**************************************************************************/
e5f82ab8 1182static int
1da177e4
LT		 1183qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1184{
e315cd28 1185 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1186 srb_t *sp;
4e98d3b8 1187 int ret;
9cb78c16
HR		 1188 unsigned int id;
1189 uint64_t lun;
18e144d3 1190 unsigned long flags;
f934c9d0 1191 int rval, wait = 0;
e315cd28 1192 struct qla_hw_data *ha = vha->hw;
1da177e4 1193
a465537a
SC		 1194 if (qla2x00_isp_reg_stat(ha)) {
1195 ql_log(ql_log_info, vha, 0x8042,
1196 "PCI/Register disconnect, exiting.\n");
1197 return FAILED;
1198 }
f4f051eb 1199 if (!CMD_SP(cmd))
2ea00202 1200 return SUCCESS;
1da177e4 1201
4e98d3b8
AV		 1202 ret = fc_block_scsi_eh(cmd);
1203 if (ret != 0)
1204 return ret;
1205 ret = SUCCESS;
1206
f4f051eb
AV		 1207 id = cmd->device->id;
1208 lun = cmd->device->lun;
1da177e4 1209
e315cd28 1210 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1211 sp = (srb_t *) CMD_SP(cmd);
1212 if (!sp) {
1213 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1214 return SUCCESS;
1215 }
1da177e4 1216
7c3df132 1217 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1218 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1219 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1220
170babc3
MC		 1221 /* Get a reference to the sp and drop the lock.*/
1222 sp_get(sp);
083a469d 1223
e315cd28 1224 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1225 rval = ha->isp_ops->abort_command(sp);
1226 if (rval) {
96219424 1227 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1228 ret = SUCCESS;
96219424 1229 else
f934c9d0
CD		 1230 ret = FAILED;
1231
7c3df132 1232 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1233 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1234 } else {
7c3df132 1235 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1236 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1237 wait = 1;
1238 }
75942064
SK		 1239
1240 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1241 sp->done(sp, 0);
75942064 1242 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1243
bc91ade9
CD		 1244 /* Did the command return during mailbox execution? */
1245 if (ret == FAILED && !CMD_SP(cmd))
1246 ret = SUCCESS;
1247
f4f051eb 1248 /* Wait for the command to be returned. */
2ea00202 1249 if (wait) {
e315cd28 1250 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1251 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1252 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1253 ret = FAILED;
f4f051eb 1254 }
1da177e4 1255 }
1da177e4 1256
7c3df132 1257 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1258 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1259 vha->host_no, id, lun, wait, ret);
1da177e4 1260
f4f051eb
AV		 1261 return ret;
1262}
1da177e4 1263
4d78c973 1264int
e315cd28 1265qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1266 uint64_t l, enum nexus_wait_type type)
f4f051eb 1267{
17d98630 1268 int cnt, match, status;
18e144d3 1269 unsigned long flags;
e315cd28 1270 struct qla_hw_data *ha = vha->hw;
73208dfd 1271 struct req_que *req;
4d78c973 1272 srb_t *sp;
9ba56b95 1273 struct scsi_cmnd *cmd;
1da177e4 1274
523ec773 1275 status = QLA_SUCCESS;
17d98630 1276
e315cd28 1277 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1278 req = vha->req;
17d98630 1279 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1280 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1281 sp = req->outstanding_cmds[cnt];
1282 if (!sp)
523ec773 1283 continue;
9ba56b95 1284 if (sp->type != SRB_SCSI_CMD)
cf53b069 1285 continue;
25ff6af1 1286 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1287 continue;
1288 match = 0;
9ba56b95 1289 cmd = GET_CMD_SP(sp);
17d98630
AC		 1290 switch (type) {
1291 case WAIT_HOST:
1292 match = 1;
1293 break;
1294 case WAIT_TARGET:
9ba56b95 1295 match = cmd->device->id == t;
17d98630
AC		 1296 break;
1297 case WAIT_LUN:
9ba56b95
GM		 1298 match = (cmd->device->id == t &&
1299 cmd->device->lun == l);
17d98630 1300 break;
73208dfd 1301 }
17d98630
AC		 1302 if (!match)
1303 continue;
1304
1305 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1306 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1307 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1308 }
e315cd28 1309 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1310
1311 return status;
1da177e4
LT		 1312}
1313
523ec773
AV		 1314static char *reset_errors[] = {
1315 "HBA not online",
1316 "HBA not ready",
1317 "Task management failed",
1318 "Waiting for command completions",
1319};
1da177e4 1320
e5f82ab8 1321static int
523ec773 1322__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1323 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1324{
e315cd28 1325 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1326 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1327 int err;
1da177e4 1328
7c3df132 1329 if (!fcport) {
523ec773 1330 return FAILED;
7c3df132 1331 }
1da177e4 1332
4e98d3b8
AV		 1333 err = fc_block_scsi_eh(cmd);
1334 if (err != 0)
1335 return err;
1336
7c3df132 1337 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1338 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1339 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1340
523ec773 1341 err = 0;
7c3df132
SK		 1342 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1343 ql_log(ql_log_warn, vha, 0x800a,
1344 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1345 goto eh_reset_failed;
7c3df132 1346 }
523ec773 1347 err = 2;
2afa19a9 1348 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1349 != QLA_SUCCESS) {
1350 ql_log(ql_log_warn, vha, 0x800c,
1351 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1352 goto eh_reset_failed;
7c3df132 1353 }
523ec773 1354 err = 3;
e315cd28 1355 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1356 cmd->device->lun, type) != QLA_SUCCESS) {
1357 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1358 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1359 goto eh_reset_failed;
7c3df132 1360 }
523ec773 1361
7c3df132 1362 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1363 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1364 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1365
1366 return SUCCESS;
1367
4d78c973 1368eh_reset_failed:
7c3df132 1369 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1370 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1371 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1372 cmd);
523ec773
AV		 1373 return FAILED;
1374}
1da177e4 1375
523ec773
AV		 1376static int
1377qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1378{
e315cd28
AC		 1379 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1380 struct qla_hw_data *ha = vha->hw;
1da177e4 1381
a465537a
SC		 1382 if (qla2x00_isp_reg_stat(ha)) {
1383 ql_log(ql_log_info, vha, 0x803e,
1384 "PCI/Register disconnect, exiting.\n");
1385 return FAILED;
1386 }
1387
523ec773
AV		 1388 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1389 ha->isp_ops->lun_reset);
1da177e4
LT		 1390}
1391
1da177e4 1392static int
523ec773 1393qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1394{
e315cd28
AC		 1395 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1396 struct qla_hw_data *ha = vha->hw;
1da177e4 1397
a465537a
SC		 1398 if (qla2x00_isp_reg_stat(ha)) {
1399 ql_log(ql_log_info, vha, 0x803f,
1400 "PCI/Register disconnect, exiting.\n");
1401 return FAILED;
1402 }
1403
523ec773
AV		 1404 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1405 ha->isp_ops->target_reset);
1da177e4
LT		 1406}
1407
1da177e4
LT		 1408/**************************************************************************
1409* qla2xxx_eh_bus_reset
1410*
1411* Description:
1412* The bus reset function will reset the bus and abort any executing
1413* commands.
1414*
1415* Input:
1416* cmd = Linux SCSI command packet of the command that cause the
1417* bus reset.
1418*
1419* Returns:
1420* SUCCESS/FAILURE (defined as macro in scsi.h).
1421*
1422**************************************************************************/
e5f82ab8 1423static int
1da177e4
LT		 1424qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1425{
e315cd28 1426 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1427 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1428 int ret = FAILED;
9cb78c16
HR		 1429 unsigned int id;
1430 uint64_t lun;
a465537a
SC		 1431 struct qla_hw_data *ha = vha->hw;
1432
1433 if (qla2x00_isp_reg_stat(ha)) {
1434 ql_log(ql_log_info, vha, 0x8040,
1435 "PCI/Register disconnect, exiting.\n");
1436 return FAILED;
1437 }
f4f051eb 1438
f4f051eb
AV		 1439 id = cmd->device->id;
1440 lun = cmd->device->lun;
1da177e4 1441
7c3df132 1442 if (!fcport) {
f4f051eb 1443 return ret;
7c3df132 1444 }
1da177e4 1445
4e98d3b8
AV		 1446 ret = fc_block_scsi_eh(cmd);
1447 if (ret != 0)
1448 return ret;
1449 ret = FAILED;
1450
7c3df132 1451 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1452 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1453
e315cd28 1454 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1455 ql_log(ql_log_fatal, vha, 0x8013,
1456 "Wait for hba online failed board disabled.\n");
f4f051eb 1457 goto eh_bus_reset_done;
1da177e4
LT		 1458 }
1459
ad537689
SK		 1460 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1461 ret = SUCCESS;
1462
f4f051eb
AV		 1463 if (ret == FAILED)
1464 goto eh_bus_reset_done;
1da177e4 1465
9a41a62b 1466 /* Flush outstanding commands. */
4d78c973 1467 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1468 QLA_SUCCESS) {
1469 ql_log(ql_log_warn, vha, 0x8014,
1470 "Wait for pending commands failed.\n");
9a41a62b 1471 ret = FAILED;
7c3df132 1472 }
1da177e4 1473
f4f051eb 1474eh_bus_reset_done:
7c3df132 1475 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1476 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1477 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1478
f4f051eb 1479 return ret;
1da177e4
LT		 1480}
1481
1482/**************************************************************************
1483* qla2xxx_eh_host_reset
1484*
1485* Description:
1486* The reset function will reset the Adapter.
1487*
1488* Input:
1489* cmd = Linux SCSI command packet of the command that cause the
1490* adapter reset.
1491*
1492* Returns:
1493* Either SUCCESS or FAILED.
1494*
1495* Note:
1496**************************************************************************/
e5f82ab8 1497static int
1da177e4
LT		 1498qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1499{
e315cd28 1500 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1501 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1502 int ret = FAILED;
9cb78c16
HR		 1503 unsigned int id;
1504 uint64_t lun;
e315cd28 1505 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1506
a465537a
SC		 1507 if (qla2x00_isp_reg_stat(ha)) {
1508 ql_log(ql_log_info, vha, 0x8041,
1509 "PCI/Register disconnect, exiting.\n");
1510 schedule_work(&ha->board_disable);
1511 return SUCCESS;
1512 }
1513
f4f051eb
AV		 1514 id = cmd->device->id;
1515 lun = cmd->device->lun;
f4f051eb 1516
7c3df132 1517 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1518 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1519
63ee7072
CD		 1520 /*
1521 * No point in issuing another reset if one is active. Also do not
1522 * attempt a reset if we are updating flash.
1523 */
1524 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1525 goto eh_host_reset_lock;
1da177e4 1526
e315cd28
AC		 1527 if (vha != base_vha) {
1528 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1529 goto eh_host_reset_lock;
e315cd28 1530 } else {
7ec0effd 1531 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1532 if (!qla82xx_fcoe_ctx_reset(vha)) {
1533 /* Ctx reset success */
1534 ret = SUCCESS;
1535 goto eh_host_reset_lock;
1536 }
1537 /* fall thru if ctx reset failed */
1538 }
68ca949c
AC		 1539 if (ha->wq)
1540 flush_workqueue(ha->wq);
1541
e315cd28 1542 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1543 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1544 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1545 /* failed. schedule dpc to try */
1546 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1547
7c3df132
SK		 1548 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1549 ql_log(ql_log_warn, vha, 0x802a,
1550 "wait for hba online failed.\n");
e315cd28 1551 goto eh_host_reset_lock;
7c3df132 1552 }
e315cd28
AC		 1553 }
1554 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1555 }
1da177e4 1556
e315cd28 1557 /* Waiting for command to be returned to OS.*/
4d78c973 1558 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1559 QLA_SUCCESS)
f4f051eb 1560 ret = SUCCESS;
1da177e4 1561
f4f051eb 1562eh_host_reset_lock:
cfb0919c 1563 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1564 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1565 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1566
f4f051eb
AV		 1567 return ret;
1568}
1da177e4
LT		 1569
1570/*
1571* qla2x00_loop_reset
1572* Issue loop reset.
1573*
1574* Input:
1575* ha = adapter block pointer.
1576*
1577* Returns:
1578* 0 = success
1579*/
a4722cf2 1580int
e315cd28 1581qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1582{
0c8c39af 1583 int ret;
bdf79621 1584 struct fc_port *fcport;
e315cd28 1585 struct qla_hw_data *ha = vha->hw;
1da177e4 1586
5854771e
AB		 1587 if (IS_QLAFX00(ha)) {
1588 return qlafx00_loop_reset(vha);
1589 }
1590
f4c496c1 1591 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1592 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1593 if (fcport->port_type != FCT_TARGET)
1594 continue;
1595
1596 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1597 if (ret != QLA_SUCCESS) {
7c3df132 1598 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1599 "Bus Reset failed: Reset=%d "
7c3df132 1600 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1601 }
1602 }
1603 }
1604
8ae6d9c7 1605
6246b8a1 1606 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1607 atomic_set(&vha->loop_state, LOOP_DOWN);
1608 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1609 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1610 ret = qla2x00_full_login_lip(vha);
0c8c39af 1611 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1612 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1613 "full_login_lip=%d.\n", ret);
749af3d5 1614 }
0c8c39af
AV		 1615 }
1616
0d6e61bc 1617 if (ha->flags.enable_lip_reset) {
e315cd28 1618 ret = qla2x00_lip_reset(vha);
ad537689 1619 if (ret != QLA_SUCCESS)
7c3df132
SK		 1620 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1621 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1622 }
1623
1da177e4 1624 /* Issue marker command only when we are going to start the I/O */
e315cd28 1625 vha->marker_needed = 1;
1da177e4 1626
0c8c39af 1627 return QLA_SUCCESS;
1da177e4
LT		 1628}
1629
df4bf0bb 1630void
e315cd28 1631qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1632{
73208dfd 1633 int que, cnt;
df4bf0bb
AV		 1634 unsigned long flags;
1635 srb_t *sp;
e315cd28 1636 struct qla_hw_data *ha = vha->hw;
73208dfd 1637 struct req_que *req;
df4bf0bb 1638
c0cb4496
AE		 1639 qlt_host_reset_handler(ha);
1640
df4bf0bb 1641 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1642 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1643 req = ha->req_q_map[que];
73208dfd
AC		 1644 if (!req)
1645 continue;
8d93f550
CD		 1646 if (!req->outstanding_cmds)
1647 continue;
1648 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1649 sp = req->outstanding_cmds[cnt];
e612d465 1650 if (sp) {
c733ab35
MFO		 1651 /* Don't abort commands in adapter during EEH
1652 * recovery as it's not accessible/responding.
1535aa75 1653 */
5f7c2bee
BK		 1654 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1655 (sp->type == SRB_SCSI_CMD)) {
c733ab35
MFO		 1656 /* Get a reference to the sp and drop the lock.
1657 * The reference ensures this sp->done() call
1658 * - and not the call in qla2xxx_eh_abort() -
1659 * ends the SCSI command (with result 'res').
1660 */
1661 sp_get(sp);
1662 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1663 qla2xxx_eh_abort(GET_CMD_SP(sp));
1664 spin_lock_irqsave(&ha->hardware_lock, flags);
1665 }
73208dfd 1666 req->outstanding_cmds[cnt] = NULL;
25ff6af1 1667 sp->done(sp, res);
73208dfd 1668 }
df4bf0bb
AV		 1669 }
1670 }
1671 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1672}
1673
f4f051eb
AV		 1674static int
1675qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1676{
bdf79621 1677 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1678
19a7b4ae 1679 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1680 return -ENXIO;
bdf79621 1681
19a7b4ae 1682 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1683
f4f051eb
AV		 1684 return 0;
1685}
1da177e4 1686
f4f051eb
AV		 1687static int
1688qla2xxx_slave_configure(struct scsi_device *sdev)
1689{
e315cd28 1690 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1691 struct req_que *req = vha->req;
8482e118 1692
9e522cd8
AE		 1693 if (IS_T10_PI_CAPABLE(vha->hw))
1694 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1695
db5ed4df 1696 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1697 return 0;
1698}
1da177e4 1699
f4f051eb
AV		 1700static void
1701qla2xxx_slave_destroy(struct scsi_device *sdev)
1702{
1703 sdev->hostdata = NULL;
1da177e4
LT		 1704}
1705
1706/**
1707 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1708 * @ha: HA context
1709 *
1710 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1711 * supported addressing method.
1712 */
1713static void
53303c42 1714qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1715{
7524f9b9 1716 /* Assume a 32bit DMA mask. */
1da177e4 1717 ha->flags.enable_64bit_addressing = 0;
1da177e4 1718
6a35528a 1719 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1720 /* Any upper-dword bits set? */
1721 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1722 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1723 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1724 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1725 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1726 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1727 return;
1da177e4 1728 }
1da177e4 1729 }
7524f9b9 1730
284901a9
YH		 1731 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1732 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1733}
1734
fd34f556 1735static void
e315cd28 1736qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1737{
1738 unsigned long flags = 0;
1739 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1740
1741 spin_lock_irqsave(&ha->hardware_lock, flags);
1742 ha->interrupts_on = 1;
1743 /* enable risc and host interrupts */
1744 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1745 RD_REG_WORD(&reg->ictrl);
1746 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1747
1748}
1749
1750static void
e315cd28 1751qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1752{
1753 unsigned long flags = 0;
1754 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1755
1756 spin_lock_irqsave(&ha->hardware_lock, flags);
1757 ha->interrupts_on = 0;
1758 /* disable risc and host interrupts */
1759 WRT_REG_WORD(&reg->ictrl, 0);
1760 RD_REG_WORD(&reg->ictrl);
1761 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1762}
1763
1764static void
e315cd28 1765qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1766{
1767 unsigned long flags = 0;
1768 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1769
1770 spin_lock_irqsave(&ha->hardware_lock, flags);
1771 ha->interrupts_on = 1;
1772 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1773 RD_REG_DWORD(&reg->ictrl);
1774 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1775}
1776
1777static void
e315cd28 1778qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1779{
1780 unsigned long flags = 0;
1781 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1782
124f85e6
AV		 1783 if (IS_NOPOLLING_TYPE(ha))
1784 return;
fd34f556
AV		 1785 spin_lock_irqsave(&ha->hardware_lock, flags);
1786 ha->interrupts_on = 0;
1787 WRT_REG_DWORD(&reg->ictrl, 0);
1788 RD_REG_DWORD(&reg->ictrl);
1789 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1790}
1791
706f457d
GM		 1792static int
1793qla2x00_iospace_config(struct qla_hw_data *ha)
1794{
1795 resource_size_t pio;
1796 uint16_t msix;
706f457d 1797
706f457d
GM		 1798 if (pci_request_selected_regions(ha->pdev, ha->bars,
1799 QLA2XXX_DRIVER_NAME)) {
1800 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1801 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1802 pci_name(ha->pdev));
1803 goto iospace_error_exit;
1804 }
1805 if (!(ha->bars & 1))
1806 goto skip_pio;
1807
1808 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1809 pio = pci_resource_start(ha->pdev, 0);
1810 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1811 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1812 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1813 "Invalid pci I/O region size (%s).\n",
1814 pci_name(ha->pdev));
1815 pio = 0;
1816 }
1817 } else {
1818 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1819 "Region #0 no a PIO resource (%s).\n",
1820 pci_name(ha->pdev));
1821 pio = 0;
1822 }
1823 ha->pio_address = pio;
1824 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1825 "PIO address=%llu.\n",
1826 (unsigned long long)ha->pio_address);
1827
1828skip_pio:
1829 /* Use MMIO operations for all accesses. */
1830 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1831 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1832 "Region #1 not an MMIO resource (%s), aborting.\n",
1833 pci_name(ha->pdev));
1834 goto iospace_error_exit;
1835 }
1836 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1837 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1838 "Invalid PCI mem region size (%s), aborting.\n",
1839 pci_name(ha->pdev));
1840 goto iospace_error_exit;
1841 }
1842
1843 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1844 if (!ha->iobase) {
1845 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1846 "Cannot remap MMIO (%s), aborting.\n",
1847 pci_name(ha->pdev));
1848 goto iospace_error_exit;
1849 }
1850
1851 /* Determine queue resources */
1852 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1853 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1854 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1855 goto mqiobase_exit;
1856
1857 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1858 pci_resource_len(ha->pdev, 3));
1859 if (ha->mqiobase) {
1860 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1861 "MQIO Base=%p.\n", ha->mqiobase);
1862 /* Read MSIX vector size of the board */
1863 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1864 ha->msix_count = msix + 1;
706f457d 1865 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1866 /* MB interrupt uses 1 vector */
1867 ha->max_req_queues = ha->msix_count - 1;
1868 ha->max_rsp_queues = ha->max_req_queues;
1869 /* Queue pairs is the max value minus the base queue pair */
1870 ha->max_qpairs = ha->max_rsp_queues - 1;
1871 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1872 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1873
706f457d 1874 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1875 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1876 } else
1877 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1878 "BAR 3 not enabled.\n");
1879
1880mqiobase_exit:
706f457d 1881 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1882 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1883 return (0);
1884
1885iospace_error_exit:
1886 return (-ENOMEM);
1887}
1888
1889
6246b8a1
GM		 1890static int
1891qla83xx_iospace_config(struct qla_hw_data *ha)
1892{
1893 uint16_t msix;
6246b8a1
GM		 1894
1895 if (pci_request_selected_regions(ha->pdev, ha->bars,
1896 QLA2XXX_DRIVER_NAME)) {
1897 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1898 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1899 pci_name(ha->pdev));
1900
1901 goto iospace_error_exit;
1902 }
1903
1904 /* Use MMIO operations for all accesses. */
1905 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1906 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1907 "Invalid pci I/O region size (%s).\n",
1908 pci_name(ha->pdev));
1909 goto iospace_error_exit;
1910 }
1911 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1912 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1913 "Invalid PCI mem region size (%s), aborting\n",
1914 pci_name(ha->pdev));
1915 goto iospace_error_exit;
1916 }
1917
1918 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1919 if (!ha->iobase) {
1920 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1921 "Cannot remap MMIO (%s), aborting.\n",
1922 pci_name(ha->pdev));
1923 goto iospace_error_exit;
1924 }
1925
1926 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1927 /* 83XX 26XX always use MQ type access for queues
1928 * - mbar 2, a.k.a region 4 */
1929 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1930 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 1931 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1932 pci_resource_len(ha->pdev, 4));
1933
1934 if (!ha->mqiobase) {
1935 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1936 "BAR2/region4 not enabled\n");
1937 goto mqiobase_exit;
1938 }
1939
1940 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1941 pci_resource_len(ha->pdev, 2));
1942 if (ha->msixbase) {
1943 /* Read MSIX vector size of the board */
1944 pci_read_config_word(ha->pdev,
1945 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1946 ha->msix_count = msix + 1;
093df737
QT		 1947 /*
1948 * By default, driver uses at least two msix vectors
1949 * (default & rspq)
1950 */
d7459527
MH		 1951 if (ql2xmqsupport) {
1952 /* MB interrupt uses 1 vector */
1953 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 1954
1955 /* ATIOQ needs 1 vector. That's 1 less QPair */
1956 if (QLA_TGT_MODE_ENABLED())
1957 ha->max_req_queues--;
1958
d0d2c68b
MH		 1959 ha->max_rsp_queues = ha->max_req_queues;
1960
d7459527
MH		 1961 /* Queue pairs is the max value minus
1962 * the base queue pair */
1963 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1965 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1966 }
1967 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1968 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1969 } else
1970 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1971 "BAR 1 not enabled.\n");
1972
1973mqiobase_exit:
6246b8a1 1974 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 1975 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 1976 return 0;
1977
1978iospace_error_exit:
1979 return -ENOMEM;
1980}
1981
fd34f556
AV		 1982static struct isp_operations qla2100_isp_ops = {
1983 .pci_config = qla2100_pci_config,
1984 .reset_chip = qla2x00_reset_chip,
1985 .chip_diag = qla2x00_chip_diag,
1986 .config_rings = qla2x00_config_rings,
1987 .reset_adapter = qla2x00_reset_adapter,
1988 .nvram_config = qla2x00_nvram_config,
1989 .update_fw_options = qla2x00_update_fw_options,
1990 .load_risc = qla2x00_load_risc,
1991 .pci_info_str = qla2x00_pci_info_str,
1992 .fw_version_str = qla2x00_fw_version_str,
1993 .intr_handler = qla2100_intr_handler,
1994 .enable_intrs = qla2x00_enable_intrs,
1995 .disable_intrs = qla2x00_disable_intrs,
1996 .abort_command = qla2x00_abort_command,
523ec773
AV		 1997 .target_reset = qla2x00_abort_target,
1998 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1999 .fabric_login = qla2x00_login_fabric,
2000 .fabric_logout = qla2x00_fabric_logout,
2001 .calc_req_entries = qla2x00_calc_iocbs_32,
2002 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2003 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2004 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2005 .read_nvram = qla2x00_read_nvram_data,
2006 .write_nvram = qla2x00_write_nvram_data,
2007 .fw_dump = qla2100_fw_dump,
2008 .beacon_on = NULL,
2009 .beacon_off = NULL,
2010 .beacon_blink = NULL,
2011 .read_optrom = qla2x00_read_optrom_data,
2012 .write_optrom = qla2x00_write_optrom_data,
2013 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2014 .start_scsi = qla2x00_start_scsi,
d7459527 2015 .start_scsi_mq = NULL,
a9083016 2016 .abort_isp = qla2x00_abort_isp,
706f457d 2017 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2018 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2019};
2020
2021static struct isp_operations qla2300_isp_ops = {
2022 .pci_config = qla2300_pci_config,
2023 .reset_chip = qla2x00_reset_chip,
2024 .chip_diag = qla2x00_chip_diag,
2025 .config_rings = qla2x00_config_rings,
2026 .reset_adapter = qla2x00_reset_adapter,
2027 .nvram_config = qla2x00_nvram_config,
2028 .update_fw_options = qla2x00_update_fw_options,
2029 .load_risc = qla2x00_load_risc,
2030 .pci_info_str = qla2x00_pci_info_str,
2031 .fw_version_str = qla2x00_fw_version_str,
2032 .intr_handler = qla2300_intr_handler,
2033 .enable_intrs = qla2x00_enable_intrs,
2034 .disable_intrs = qla2x00_disable_intrs,
2035 .abort_command = qla2x00_abort_command,
523ec773
AV		 2036 .target_reset = qla2x00_abort_target,
2037 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2038 .fabric_login = qla2x00_login_fabric,
2039 .fabric_logout = qla2x00_fabric_logout,
2040 .calc_req_entries = qla2x00_calc_iocbs_32,
2041 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2042 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2043 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2044 .read_nvram = qla2x00_read_nvram_data,
2045 .write_nvram = qla2x00_write_nvram_data,
2046 .fw_dump = qla2300_fw_dump,
2047 .beacon_on = qla2x00_beacon_on,
2048 .beacon_off = qla2x00_beacon_off,
2049 .beacon_blink = qla2x00_beacon_blink,
2050 .read_optrom = qla2x00_read_optrom_data,
2051 .write_optrom = qla2x00_write_optrom_data,
2052 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2053 .start_scsi = qla2x00_start_scsi,
d7459527 2054 .start_scsi_mq = NULL,
a9083016 2055 .abort_isp = qla2x00_abort_isp,
7ec0effd 2056 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2057 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2058};
2059
2060static struct isp_operations qla24xx_isp_ops = {
2061 .pci_config = qla24xx_pci_config,
2062 .reset_chip = qla24xx_reset_chip,
2063 .chip_diag = qla24xx_chip_diag,
2064 .config_rings = qla24xx_config_rings,
2065 .reset_adapter = qla24xx_reset_adapter,
2066 .nvram_config = qla24xx_nvram_config,
2067 .update_fw_options = qla24xx_update_fw_options,
2068 .load_risc = qla24xx_load_risc,
2069 .pci_info_str = qla24xx_pci_info_str,
2070 .fw_version_str = qla24xx_fw_version_str,
2071 .intr_handler = qla24xx_intr_handler,
2072 .enable_intrs = qla24xx_enable_intrs,
2073 .disable_intrs = qla24xx_disable_intrs,
2074 .abort_command = qla24xx_abort_command,
523ec773
AV		 2075 .target_reset = qla24xx_abort_target,
2076 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2077 .fabric_login = qla24xx_login_fabric,
2078 .fabric_logout = qla24xx_fabric_logout,
2079 .calc_req_entries = NULL,
2080 .build_iocbs = NULL,
2081 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2082 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2083 .read_nvram = qla24xx_read_nvram_data,
2084 .write_nvram = qla24xx_write_nvram_data,
2085 .fw_dump = qla24xx_fw_dump,
2086 .beacon_on = qla24xx_beacon_on,
2087 .beacon_off = qla24xx_beacon_off,
2088 .beacon_blink = qla24xx_beacon_blink,
2089 .read_optrom = qla24xx_read_optrom_data,
2090 .write_optrom = qla24xx_write_optrom_data,
2091 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2092 .start_scsi = qla24xx_start_scsi,
d7459527 2093 .start_scsi_mq = NULL,
a9083016 2094 .abort_isp = qla2x00_abort_isp,
7ec0effd 2095 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2096 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2097};
2098
c3a2f0df
AV		 2099static struct isp_operations qla25xx_isp_ops = {
2100 .pci_config = qla25xx_pci_config,
2101 .reset_chip = qla24xx_reset_chip,
2102 .chip_diag = qla24xx_chip_diag,
2103 .config_rings = qla24xx_config_rings,
2104 .reset_adapter = qla24xx_reset_adapter,
2105 .nvram_config = qla24xx_nvram_config,
2106 .update_fw_options = qla24xx_update_fw_options,
2107 .load_risc = qla24xx_load_risc,
2108 .pci_info_str = qla24xx_pci_info_str,
2109 .fw_version_str = qla24xx_fw_version_str,
2110 .intr_handler = qla24xx_intr_handler,
2111 .enable_intrs = qla24xx_enable_intrs,
2112 .disable_intrs = qla24xx_disable_intrs,
2113 .abort_command = qla24xx_abort_command,
523ec773
AV		 2114 .target_reset = qla24xx_abort_target,
2115 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2116 .fabric_login = qla24xx_login_fabric,
2117 .fabric_logout = qla24xx_fabric_logout,
2118 .calc_req_entries = NULL,
2119 .build_iocbs = NULL,
2120 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2121 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2122 .read_nvram = qla25xx_read_nvram_data,
2123 .write_nvram = qla25xx_write_nvram_data,
2124 .fw_dump = qla25xx_fw_dump,
2125 .beacon_on = qla24xx_beacon_on,
2126 .beacon_off = qla24xx_beacon_off,
2127 .beacon_blink = qla24xx_beacon_blink,
338c9161 2128 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2129 .write_optrom = qla24xx_write_optrom_data,
2130 .get_flash_version = qla24xx_get_flash_version,
bad75002 2131 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2132 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2133 .abort_isp = qla2x00_abort_isp,
7ec0effd 2134 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2135 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2136};
2137
3a03eb79
AV		 2138static struct isp_operations qla81xx_isp_ops = {
2139 .pci_config = qla25xx_pci_config,
2140 .reset_chip = qla24xx_reset_chip,
2141 .chip_diag = qla24xx_chip_diag,
2142 .config_rings = qla24xx_config_rings,
2143 .reset_adapter = qla24xx_reset_adapter,
2144 .nvram_config = qla81xx_nvram_config,
2145 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2146 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2147 .pci_info_str = qla24xx_pci_info_str,
2148 .fw_version_str = qla24xx_fw_version_str,
2149 .intr_handler = qla24xx_intr_handler,
2150 .enable_intrs = qla24xx_enable_intrs,
2151 .disable_intrs = qla24xx_disable_intrs,
2152 .abort_command = qla24xx_abort_command,
2153 .target_reset = qla24xx_abort_target,
2154 .lun_reset = qla24xx_lun_reset,
2155 .fabric_login = qla24xx_login_fabric,
2156 .fabric_logout = qla24xx_fabric_logout,
2157 .calc_req_entries = NULL,
2158 .build_iocbs = NULL,
2159 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2160 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2161 .read_nvram = NULL,
2162 .write_nvram = NULL,
3a03eb79
AV		 2163 .fw_dump = qla81xx_fw_dump,
2164 .beacon_on = qla24xx_beacon_on,
2165 .beacon_off = qla24xx_beacon_off,
6246b8a1 2166 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2167 .read_optrom = qla25xx_read_optrom_data,
2168 .write_optrom = qla24xx_write_optrom_data,
2169 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2170 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2171 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2172 .abort_isp = qla2x00_abort_isp,
7ec0effd 2173 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2174 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2175};
2176
2177static struct isp_operations qla82xx_isp_ops = {
2178 .pci_config = qla82xx_pci_config,
2179 .reset_chip = qla82xx_reset_chip,
2180 .chip_diag = qla24xx_chip_diag,
2181 .config_rings = qla82xx_config_rings,
2182 .reset_adapter = qla24xx_reset_adapter,
2183 .nvram_config = qla81xx_nvram_config,
2184 .update_fw_options = qla24xx_update_fw_options,
2185 .load_risc = qla82xx_load_risc,
9d55ca66 2186 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2187 .fw_version_str = qla24xx_fw_version_str,
2188 .intr_handler = qla82xx_intr_handler,
2189 .enable_intrs = qla82xx_enable_intrs,
2190 .disable_intrs = qla82xx_disable_intrs,
2191 .abort_command = qla24xx_abort_command,
2192 .target_reset = qla24xx_abort_target,
2193 .lun_reset = qla24xx_lun_reset,
2194 .fabric_login = qla24xx_login_fabric,
2195 .fabric_logout = qla24xx_fabric_logout,
2196 .calc_req_entries = NULL,
2197 .build_iocbs = NULL,
2198 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2199 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2200 .read_nvram = qla24xx_read_nvram_data,
2201 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2202 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2203 .beacon_on = qla82xx_beacon_on,
2204 .beacon_off = qla82xx_beacon_off,
2205 .beacon_blink = NULL,
a9083016
GM		 2206 .read_optrom = qla82xx_read_optrom_data,
2207 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2208 .get_flash_version = qla82xx_get_flash_version,
a9083016 2209 .start_scsi = qla82xx_start_scsi,
d7459527 2210 .start_scsi_mq = NULL,
a9083016 2211 .abort_isp = qla82xx_abort_isp,
706f457d 2212 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2213 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2214};
2215
7ec0effd
AD		 2216static struct isp_operations qla8044_isp_ops = {
2217 .pci_config = qla82xx_pci_config,
2218 .reset_chip = qla82xx_reset_chip,
2219 .chip_diag = qla24xx_chip_diag,
2220 .config_rings = qla82xx_config_rings,
2221 .reset_adapter = qla24xx_reset_adapter,
2222 .nvram_config = qla81xx_nvram_config,
2223 .update_fw_options = qla24xx_update_fw_options,
2224 .load_risc = qla82xx_load_risc,
2225 .pci_info_str = qla24xx_pci_info_str,
2226 .fw_version_str = qla24xx_fw_version_str,
2227 .intr_handler = qla8044_intr_handler,
2228 .enable_intrs = qla82xx_enable_intrs,
2229 .disable_intrs = qla82xx_disable_intrs,
2230 .abort_command = qla24xx_abort_command,
2231 .target_reset = qla24xx_abort_target,
2232 .lun_reset = qla24xx_lun_reset,
2233 .fabric_login = qla24xx_login_fabric,
2234 .fabric_logout = qla24xx_fabric_logout,
2235 .calc_req_entries = NULL,
2236 .build_iocbs = NULL,
2237 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2238 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2239 .read_nvram = NULL,
2240 .write_nvram = NULL,
a1b23c5a 2241 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2242 .beacon_on = qla82xx_beacon_on,
2243 .beacon_off = qla82xx_beacon_off,
2244 .beacon_blink = NULL,
888e639d 2245 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2246 .write_optrom = qla8044_write_optrom_data,
2247 .get_flash_version = qla82xx_get_flash_version,
2248 .start_scsi = qla82xx_start_scsi,
d7459527 2249 .start_scsi_mq = NULL,
7ec0effd
AD		 2250 .abort_isp = qla8044_abort_isp,
2251 .iospace_config = qla82xx_iospace_config,
2252 .initialize_adapter = qla2x00_initialize_adapter,
2253};
2254
6246b8a1
GM		 2255static struct isp_operations qla83xx_isp_ops = {
2256 .pci_config = qla25xx_pci_config,
2257 .reset_chip = qla24xx_reset_chip,
2258 .chip_diag = qla24xx_chip_diag,
2259 .config_rings = qla24xx_config_rings,
2260 .reset_adapter = qla24xx_reset_adapter,
2261 .nvram_config = qla81xx_nvram_config,
2262 .update_fw_options = qla81xx_update_fw_options,
2263 .load_risc = qla81xx_load_risc,
2264 .pci_info_str = qla24xx_pci_info_str,
2265 .fw_version_str = qla24xx_fw_version_str,
2266 .intr_handler = qla24xx_intr_handler,
2267 .enable_intrs = qla24xx_enable_intrs,
2268 .disable_intrs = qla24xx_disable_intrs,
2269 .abort_command = qla24xx_abort_command,
2270 .target_reset = qla24xx_abort_target,
2271 .lun_reset = qla24xx_lun_reset,
2272 .fabric_login = qla24xx_login_fabric,
2273 .fabric_logout = qla24xx_fabric_logout,
2274 .calc_req_entries = NULL,
2275 .build_iocbs = NULL,
2276 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2277 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2278 .read_nvram = NULL,
2279 .write_nvram = NULL,
2280 .fw_dump = qla83xx_fw_dump,
2281 .beacon_on = qla24xx_beacon_on,
2282 .beacon_off = qla24xx_beacon_off,
2283 .beacon_blink = qla83xx_beacon_blink,
2284 .read_optrom = qla25xx_read_optrom_data,
2285 .write_optrom = qla24xx_write_optrom_data,
2286 .get_flash_version = qla24xx_get_flash_version,
2287 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2288 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2289 .abort_isp = qla2x00_abort_isp,
2290 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2291 .initialize_adapter = qla2x00_initialize_adapter,
2292};
2293
2294static struct isp_operations qlafx00_isp_ops = {
2295 .pci_config = qlafx00_pci_config,
2296 .reset_chip = qlafx00_soft_reset,
2297 .chip_diag = qlafx00_chip_diag,
2298 .config_rings = qlafx00_config_rings,
2299 .reset_adapter = qlafx00_soft_reset,
2300 .nvram_config = NULL,
2301 .update_fw_options = NULL,
2302 .load_risc = NULL,
2303 .pci_info_str = qlafx00_pci_info_str,
2304 .fw_version_str = qlafx00_fw_version_str,
2305 .intr_handler = qlafx00_intr_handler,
2306 .enable_intrs = qlafx00_enable_intrs,
2307 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2308 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2309 .target_reset = qlafx00_abort_target,
2310 .lun_reset = qlafx00_lun_reset,
2311 .fabric_login = NULL,
2312 .fabric_logout = NULL,
2313 .calc_req_entries = NULL,
2314 .build_iocbs = NULL,
2315 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2316 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2317 .read_nvram = qla24xx_read_nvram_data,
2318 .write_nvram = qla24xx_write_nvram_data,
2319 .fw_dump = NULL,
2320 .beacon_on = qla24xx_beacon_on,
2321 .beacon_off = qla24xx_beacon_off,
2322 .beacon_blink = NULL,
2323 .read_optrom = qla24xx_read_optrom_data,
2324 .write_optrom = qla24xx_write_optrom_data,
2325 .get_flash_version = qla24xx_get_flash_version,
2326 .start_scsi = qlafx00_start_scsi,
d7459527 2327 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2328 .abort_isp = qlafx00_abort_isp,
2329 .iospace_config = qlafx00_iospace_config,
2330 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2331};
2332
f73cb695
CD		 2333static struct isp_operations qla27xx_isp_ops = {
2334 .pci_config = qla25xx_pci_config,
2335 .reset_chip = qla24xx_reset_chip,
2336 .chip_diag = qla24xx_chip_diag,
2337 .config_rings = qla24xx_config_rings,
2338 .reset_adapter = qla24xx_reset_adapter,
2339 .nvram_config = qla81xx_nvram_config,
2340 .update_fw_options = qla81xx_update_fw_options,
2341 .load_risc = qla81xx_load_risc,
2342 .pci_info_str = qla24xx_pci_info_str,
2343 .fw_version_str = qla24xx_fw_version_str,
2344 .intr_handler = qla24xx_intr_handler,
2345 .enable_intrs = qla24xx_enable_intrs,
2346 .disable_intrs = qla24xx_disable_intrs,
2347 .abort_command = qla24xx_abort_command,
2348 .target_reset = qla24xx_abort_target,
2349 .lun_reset = qla24xx_lun_reset,
2350 .fabric_login = qla24xx_login_fabric,
2351 .fabric_logout = qla24xx_fabric_logout,
2352 .calc_req_entries = NULL,
2353 .build_iocbs = NULL,
2354 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2355 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2356 .read_nvram = NULL,
2357 .write_nvram = NULL,
2358 .fw_dump = qla27xx_fwdump,
2359 .beacon_on = qla24xx_beacon_on,
2360 .beacon_off = qla24xx_beacon_off,
2361 .beacon_blink = qla83xx_beacon_blink,
2362 .read_optrom = qla25xx_read_optrom_data,
2363 .write_optrom = qla24xx_write_optrom_data,
2364 .get_flash_version = qla24xx_get_flash_version,
2365 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2366 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2367 .abort_isp = qla2x00_abort_isp,
2368 .iospace_config = qla83xx_iospace_config,
2369 .initialize_adapter = qla2x00_initialize_adapter,
2370};
2371
ea5b6382 2372static inline void
e315cd28 2373qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2374{
2375 ha->device_type = DT_EXTENDED_IDS;
2376 switch (ha->pdev->device) {
2377 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2378 ha->isp_type |= DT_ISP2100;
ea5b6382 2379 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2380 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2381 break;
2382 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2383 ha->isp_type |= DT_ISP2200;
ea5b6382 2384 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2385 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2386 break;
2387 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2388 ha->isp_type |= DT_ISP2300;
4a59f71d 2389 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2390 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2391 break;
2392 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2393 ha->isp_type |= DT_ISP2312;
4a59f71d 2394 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2395 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2396 break;
2397 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2398 ha->isp_type |= DT_ISP2322;
4a59f71d 2399 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2400 if (ha->pdev->subsystem_vendor == 0x1028 &&
2401 ha->pdev->subsystem_device == 0x0170)
2402 ha->device_type |= DT_OEM_001;
441d1072 2403 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2404 break;
2405 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2406 ha->isp_type |= DT_ISP6312;
441d1072 2407 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2408 break;
2409 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2410 ha->isp_type |= DT_ISP6322;
441d1072 2411 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2412 break;
2413 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2414 ha->isp_type |= DT_ISP2422;
4a59f71d 2415 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2416 ha->device_type |= DT_FWI2;
c76f2c01 2417 ha->device_type |= DT_IIDMA;
441d1072 2418 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2419 break;
2420 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2421 ha->isp_type |= DT_ISP2432;
4a59f71d 2422 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2423 ha->device_type |= DT_FWI2;
c76f2c01 2424 ha->device_type |= DT_IIDMA;
441d1072 2425 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2426 break;
4d4df193 2427 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2428 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2429 ha->device_type |= DT_ZIO_SUPPORTED;
2430 ha->device_type |= DT_FWI2;
2431 ha->device_type |= DT_IIDMA;
2432 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2433 break;
044cc6c8 2434 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2435 ha->isp_type |= DT_ISP5422;
e428924c 2436 ha->device_type |= DT_FWI2;
441d1072 2437 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2438 break;
044cc6c8 2439 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2440 ha->isp_type |= DT_ISP5432;
e428924c 2441 ha->device_type |= DT_FWI2;
441d1072 2442 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2443 break;
c3a2f0df 2444 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2445 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2446 ha->device_type |= DT_ZIO_SUPPORTED;
2447 ha->device_type |= DT_FWI2;
2448 ha->device_type |= DT_IIDMA;
441d1072 2449 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2450 break;
3a03eb79 2451 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2452 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2453 ha->device_type |= DT_ZIO_SUPPORTED;
2454 ha->device_type |= DT_FWI2;
2455 ha->device_type |= DT_IIDMA;
2456 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2457 break;
a9083016 2458 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2459 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2460 ha->device_type |= DT_ZIO_SUPPORTED;
2461 ha->device_type |= DT_FWI2;
2462 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2463 /* Initialize 82XX ISP flags */
2464 qla82xx_init_flags(ha);
2465 break;
7ec0effd 2466 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2467 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2468 ha->device_type |= DT_ZIO_SUPPORTED;
2469 ha->device_type |= DT_FWI2;
2470 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2471 /* Initialize 82XX ISP flags */
2472 qla82xx_init_flags(ha);
2473 break;
6246b8a1 2474 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2475 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2476 ha->device_type |= DT_ZIO_SUPPORTED;
2477 ha->device_type |= DT_FWI2;
2478 ha->device_type |= DT_IIDMA;
2479 ha->device_type |= DT_T10_PI;
2480 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2481 break;
2482 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2483 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2484 ha->device_type |= DT_ZIO_SUPPORTED;
2485 ha->device_type |= DT_FWI2;
2486 ha->device_type |= DT_IIDMA;
2487 ha->device_type |= DT_T10_PI;
2488 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2489 break;
8ae6d9c7 2490 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2491 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2492 break;
f73cb695 2493 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2494 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2495 ha->device_type |= DT_ZIO_SUPPORTED;
2496 ha->device_type |= DT_FWI2;
2497 ha->device_type |= DT_IIDMA;
8ce3f570 2498 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2499 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2500 break;
2c5bbbb2 2501 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2502 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2503 ha->device_type |= DT_ZIO_SUPPORTED;
2504 ha->device_type |= DT_FWI2;
2505 ha->device_type |= DT_IIDMA;
8ce3f570 2506 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2507 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2508 break;
2b48992f 2509 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2510 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2511 ha->device_type |= DT_ZIO_SUPPORTED;
2512 ha->device_type |= DT_FWI2;
2513 ha->device_type |= DT_IIDMA;
8ce3f570 2514 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2515 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2516 break;
ea5b6382 2517 }
e5b68a61 2518
a9083016 2519 if (IS_QLA82XX(ha))
43a9c38b 2520 ha->port_no = ha->portnum & 1;
f73cb695 2521 else {
a9083016
GM		 2522 /* Get adapter physical port no from interrupt pin register. */
2523 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2524 if (IS_QLA27XX(ha))
2525 ha->port_no--;
2526 else
2527 ha->port_no = !(ha->port_no & 1);
2528 }
a9083016 2529
7c3df132 2530 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2531 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2532 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2533}
2534
1e99e33a
AV		 2535static void
2536qla2xxx_scan_start(struct Scsi_Host *shost)
2537{
e315cd28 2538 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2539
cbc8eb67
AV		 2540 if (vha->hw->flags.running_gold_fw)
2541 return;
2542
e315cd28
AC		 2543 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2544 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2545 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2546 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2547}
2548
2549static int
2550qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2551{
e315cd28 2552 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2553
a5dd506e
BK		 2554 if (test_bit(UNLOADING, &vha->dpc_flags))
2555 return 1;
e315cd28 2556 if (!vha->host)
1e99e33a 2557 return 1;
e315cd28 2558 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2559 return 1;
2560
e315cd28 2561 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2562}
2563
ec7193e2
QT		 2564static void qla2x00_iocb_work_fn(struct work_struct *work)
2565{
2566 struct scsi_qla_host *vha = container_of(work,
2567 struct scsi_qla_host, iocb_work);
2568 int cnt = 0;
2569
2570 while (!list_empty(&vha->work_list)) {
2571 qla2x00_do_work(vha);
2572 cnt++;
2573 if (cnt > 10)
2574 break;
2575 }
2576}
2577
1da177e4
LT		 2578/*
2579 * PCI driver interface
2580 */
6f039790 2581static int
7ee61397 2582qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2583{
a1541d5a 2584 int ret = -ENODEV;
1da177e4 2585 struct Scsi_Host *host;
e315cd28
AC		 2586 scsi_qla_host_t *base_vha = NULL;
2587 struct qla_hw_data *ha;
29856e28 2588 char pci_info[30];
7d613ac6 2589 char fw_str[30], wq_name[30];
5433383e 2590 struct scsi_host_template *sht;
642ef983 2591 int bars, mem_only = 0;
e315cd28 2592 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2593 struct req_que *req = NULL;
2594 struct rsp_que *rsp = NULL;
5601236b 2595 int i;
d7459527 2596
285d0321 2597 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2598 sht = &qla2xxx_driver_template;
5433383e 2599 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2600 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2601 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2602 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2603 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2604 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2605 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2606 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2607 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2608 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2609 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2610 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2611 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2612 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2613 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2614 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2615 mem_only = 1;
7c3df132
SK		 2616 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2617 "Mem only adapter.\n");
285d0321 2618 }
7c3df132
SK		 2619 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2620 "Bars=%d.\n", bars);
285d0321 2621
09483916
BH		 2622 if (mem_only) {
2623 if (pci_enable_device_mem(pdev))
2624 goto probe_out;
2625 } else {
2626 if (pci_enable_device(pdev))
2627 goto probe_out;
2628 }
285d0321 2629
0927678f
JB		 2630 /* This may fail but that's ok */
2631 pci_enable_pcie_error_reporting(pdev);
285d0321 2632
e315cd28
AC		 2633 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2634 if (!ha) {
7c3df132
SK		 2635 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2636 "Unable to allocate memory for ha.\n");
e315cd28 2637 goto probe_out;
1da177e4 2638 }
7c3df132
SK		 2639 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2640 "Memory allocated for ha=%p.\n", ha);
e315cd28 2641 ha->pdev = pdev;
2d70c103 2642 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2643 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2644 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2645 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2646 spin_lock_init(&ha->tgt.atio_lock);
2647
1da177e4
LT		 2648
2649 /* Clear our data area */
285d0321 2650 ha->bars = bars;
09483916 2651 ha->mem_only = mem_only;
df4bf0bb 2652 spin_lock_init(&ha->hardware_lock);
339aa70e 2653 spin_lock_init(&ha->vport_slock);
a9b6f722 2654 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2655 mutex_init(&ha->optrom_mutex);
1da177e4 2656
ea5b6382
AV		 2657 /* Set ISP-type information. */
2658 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2659
2660 /* Set EEH reset type to fundamental if required by hba */
95676112 2661 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2662 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2663 pdev->needs_freset = 1;
ca79cf66 2664
cba1e47f
CD		 2665 ha->prev_topology = 0;
2666 ha->init_cb_size = sizeof(init_cb_t);
2667 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2668 ha->optrom_size = OPTROM_SIZE_2300;
2669
abbd8870 2670 /* Assign ISP specific operations. */
1da177e4 2671 if (IS_QLA2100(ha)) {
642ef983 2672 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2673 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2674 req_length = REQUEST_ENTRY_CNT_2100;
2675 rsp_length = RESPONSE_ENTRY_CNT_2100;
2676 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2677 ha->gid_list_info_size = 4;
3a03eb79
AV		 2678 ha->flash_conf_off = ~0;
2679 ha->flash_data_off = ~0;
2680 ha->nvram_conf_off = ~0;
2681 ha->nvram_data_off = ~0;
fd34f556 2682 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2683 } else if (IS_QLA2200(ha)) {
642ef983 2684 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2685 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2686 req_length = REQUEST_ENTRY_CNT_2200;
2687 rsp_length = RESPONSE_ENTRY_CNT_2100;
2688 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2689 ha->gid_list_info_size = 4;
3a03eb79
AV		 2690 ha->flash_conf_off = ~0;
2691 ha->flash_data_off = ~0;
2692 ha->nvram_conf_off = ~0;
2693 ha->nvram_data_off = ~0;
fd34f556 2694 ha->isp_ops = &qla2100_isp_ops;
fca29703 2695 } else if (IS_QLA23XX(ha)) {
642ef983 2696 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2697 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2698 req_length = REQUEST_ENTRY_CNT_2200;
2699 rsp_length = RESPONSE_ENTRY_CNT_2300;
2700 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2701 ha->gid_list_info_size = 6;
854165f4
AV		 2702 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2703 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2704 ha->flash_conf_off = ~0;
2705 ha->flash_data_off = ~0;
2706 ha->nvram_conf_off = ~0;
2707 ha->nvram_data_off = ~0;
fd34f556 2708 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2709 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2710 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2711 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2712 req_length = REQUEST_ENTRY_CNT_24XX;
2713 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2714 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2715 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2716 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2717 ha->gid_list_info_size = 8;
854165f4 2718 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2719 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2720 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2721 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2722 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2723 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2724 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2725 } else if (IS_QLA25XX(ha)) {
642ef983 2726 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2727 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2728 req_length = REQUEST_ENTRY_CNT_24XX;
2729 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2730 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2731 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2732 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2733 ha->gid_list_info_size = 8;
2734 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2735 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2736 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2737 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2738 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2739 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2740 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2741 } else if (IS_QLA81XX(ha)) {
642ef983 2742 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2743 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2744 req_length = REQUEST_ENTRY_CNT_24XX;
2745 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2746 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2747 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2748 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2749 ha->gid_list_info_size = 8;
2750 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2751 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2752 ha->isp_ops = &qla81xx_isp_ops;
2753 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2754 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2755 ha->nvram_conf_off = ~0;
2756 ha->nvram_data_off = ~0;
a9083016 2757 } else if (IS_QLA82XX(ha)) {
642ef983 2758 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2759 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2760 req_length = REQUEST_ENTRY_CNT_82XX;
2761 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2762 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2763 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2764 ha->gid_list_info_size = 8;
2765 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2766 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2767 ha->isp_ops = &qla82xx_isp_ops;
2768 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2769 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2770 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2771 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2772 } else if (IS_QLA8044(ha)) {
2773 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2774 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2775 req_length = REQUEST_ENTRY_CNT_82XX;
2776 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2777 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2778 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2779 ha->gid_list_info_size = 8;
2780 ha->optrom_size = OPTROM_SIZE_83XX;
2781 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2782 ha->isp_ops = &qla8044_isp_ops;
2783 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2784 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2785 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2786 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2787 } else if (IS_QLA83XX(ha)) {
7d613ac6 2788 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2789 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2790 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2791 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2792 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2793 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2794 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2795 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2796 ha->gid_list_info_size = 8;
2797 ha->optrom_size = OPTROM_SIZE_83XX;
2798 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2799 ha->isp_ops = &qla83xx_isp_ops;
2800 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2801 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2802 ha->nvram_conf_off = ~0;
2803 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2804 } else if (IS_QLAFX00(ha)) {
2805 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2806 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2807 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2808 req_length = REQUEST_ENTRY_CNT_FX00;
2809 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2810 ha->isp_ops = &qlafx00_isp_ops;
2811 ha->port_down_retry_count = 30; /* default value */
2812 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2813 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2814 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2815 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2816 ha->mr.host_info_resend = false;
2817 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2818 } else if (IS_QLA27XX(ha)) {
2819 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2820 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2821 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2822 req_length = REQUEST_ENTRY_CNT_83XX;
2823 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2824 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2825 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2826 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2827 ha->gid_list_info_size = 8;
2828 ha->optrom_size = OPTROM_SIZE_83XX;
2829 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2830 ha->isp_ops = &qla27xx_isp_ops;
2831 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2832 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2833 ha->nvram_conf_off = ~0;
2834 ha->nvram_data_off = ~0;
1da177e4 2835 }
6246b8a1 2836
7c3df132
SK		 2837 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2838 "mbx_count=%d, req_length=%d, "
2839 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2840 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2841 "max_fibre_devices=%d.\n",
7c3df132
SK		 2842 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2843 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2844 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2845 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2846 "isp_ops=%p, flash_conf_off=%d, "
2847 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2848 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2849 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2850
2851 /* Configure PCI I/O space */
2852 ret = ha->isp_ops->iospace_config(ha);
2853 if (ret)
0a63ad12 2854 goto iospace_config_failed;
706f457d
GM		 2855
2856 ql_log_pci(ql_log_info, pdev, 0x001d,
2857 "Found an ISP%04X irq %d iobase 0x%p.\n",
2858 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2859 mutex_init(&ha->vport_lock);
d7459527 2860 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2861 init_completion(&ha->mbx_cmd_comp);
2862 complete(&ha->mbx_cmd_comp);
2863 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2864 init_completion(&ha->dcbx_comp);
f356bef1 2865 init_completion(&ha->lb_portup_comp);
1da177e4 2866
2c3dfe3f 2867 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2868
53303c42 2869 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2870 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2871 "64 Bit addressing is %s.\n",
2872 ha->flags.enable_64bit_addressing ? "enable" :
2873 "disable");
73208dfd 2874 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2875 if (ret) {
7c3df132
SK		 2876 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2877 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2878
e315cd28
AC		 2879 goto probe_hw_failed;
2880 }
2881
73208dfd 2882 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2883 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2884 req->max_q_depth = ql2xmaxqdepth;
2885
e315cd28
AC		 2886
2887 base_vha = qla2x00_create_host(sht, ha);
2888 if (!base_vha) {
a1541d5a 2889 ret = -ENOMEM;
6e9f21f3 2890 qla2x00_mem_free(ha);
2afa19a9
AC		 2891 qla2x00_free_req_que(ha, req);
2892 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2893 goto probe_hw_failed;
1da177e4
LT		 2894 }
2895
e315cd28 2896 pci_set_drvdata(pdev, base_vha);
6b383979 2897 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2898
e315cd28 2899 host = base_vha->host;
2afa19a9 2900 base_vha->req = req;
73208dfd 2901 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2902 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2903 else
e315cd28
AC		 2904 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2905 base_vha->vp_idx;
58548cb5 2906
8ae6d9c7
GM		 2907 /* Setup fcport template structure. */
2908 ha->mr.fcport.vha = base_vha;
2909 ha->mr.fcport.port_type = FCT_UNKNOWN;
2910 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2911 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2912 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2913 ha->mr.fcport.scan_state = 1;
2914
58548cb5
GM		 2915 /* Set the SG table size based on ISP type */
2916 if (!IS_FWI2_CAPABLE(ha)) {
2917 if (IS_QLA2100(ha))
2918 host->sg_tablesize = 32;
2919 } else {
2920 if (!IS_QLA82XX(ha))
2921 host->sg_tablesize = QLA_SG_ALL;
2922 }
642ef983 2923 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2924 host->cmd_per_lun = 3;
2925 host->unique_id = host->host_no;
e02587d7 2926 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2927 host->max_cmd_len = 32;
2928 else
2929 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2930 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2931 /* Older HBAs support only 16-bit LUNs */
2932 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2933 ql2xmaxlun > 0xffff)
2934 host->max_lun = 0xffff;
2935 else
2936 host->max_lun = ql2xmaxlun;
e315cd28 2937 host->transportt = qla2xxx_transport_template;
9a069e19 2938 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2939
7c3df132
SK		 2940 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2941 "max_id=%d this_id=%d "
2942 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2943 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2944 host->this_id, host->cmd_per_lun, host->unique_id,
2945 host->max_cmd_len, host->max_channel, host->max_lun,
2946 host->transportt, sht->vendor_id);
2947
d7459527
MH		 2948 /* Set up the irqs */
2949 ret = qla2x00_request_irqs(ha, rsp);
2950 if (ret)
2951 goto probe_init_failed;
2952
9a347ff4
CD		 2953 /* Alloc arrays of request and response ring ptrs */
2954 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2955 ql_log(ql_log_fatal, base_vha, 0x003d,
2956 "Failed to allocate memory for queue pointers..."
2957 "aborting.\n");
2958 goto probe_init_failed;
2959 }
2960
5601236b
MH		 2961 if (ha->mqenable && shost_use_blk_mq(host)) {
2962 /* number of hardware queues supported by blk/scsi-mq*/
2963 host->nr_hw_queues = ha->max_qpairs;
2964
2965 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2966 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2967 } else
2968 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2969 "blk/scsi-mq disabled.\n");
2970
2d70c103 2971 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2972
90a86fc0
JC		 2973 pci_save_state(pdev);
2974
9a347ff4 2975 /* Assign back pointers */
2afa19a9
AC		 2976 rsp->req = req;
2977 req->rsp = rsp;
9a347ff4 2978
8ae6d9c7
GM		 2979 if (IS_QLAFX00(ha)) {
2980 ha->rsp_q_map[0] = rsp;
2981 ha->req_q_map[0] = req;
2982 set_bit(0, ha->req_qid_map);
2983 set_bit(0, ha->rsp_qid_map);
2984 }
2985
08029990
AV		 2986 /* FWI2-capable only. */
2987 req->req_q_in = &ha->iobase->isp24.req_q_in;
2988 req->req_q_out = &ha->iobase->isp24.req_q_out;
2989 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2990 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2991 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2992 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2993 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2994 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2995 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2996 }
2997
8ae6d9c7
GM		 2998 if (IS_QLAFX00(ha)) {
2999 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3000 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3001 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3002 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3003 }
3004
7ec0effd 3005 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3006 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3007 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3008 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3009 }
3010
7c3df132
SK		 3011 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3012 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3013 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3014 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3015 "req->req_q_in=%p req->req_q_out=%p "
3016 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3017 req->req_q_in, req->req_q_out,
3018 rsp->rsp_q_in, rsp->rsp_q_out);
3019 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3020 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3021 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3022 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3023 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3024 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3025
8ae6d9c7 3026 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3027 ql_log(ql_log_fatal, base_vha, 0x00d6,
3028 "Failed to initialize adapter - Adapter flags %x.\n",
3029 base_vha->device_flags);
1da177e4 3030
a9083016
GM		 3031 if (IS_QLA82XX(ha)) {
3032 qla82xx_idc_lock(ha);
3033 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3034 QLA8XXX_DEV_FAILED);
a9083016 3035 qla82xx_idc_unlock(ha);
7c3df132
SK		 3036 ql_log(ql_log_fatal, base_vha, 0x00d7,
3037 "HW State: FAILED.\n");
7ec0effd
AD		 3038 } else if (IS_QLA8044(ha)) {
3039 qla8044_idc_lock(ha);
3040 qla8044_wr_direct(base_vha,
3041 QLA8044_CRB_DEV_STATE_INDEX,
3042 QLA8XXX_DEV_FAILED);
3043 qla8044_idc_unlock(ha);
3044 ql_log(ql_log_fatal, base_vha, 0x0150,
3045 "HW State: FAILED.\n");
a9083016
GM		 3046 }
3047
a1541d5a 3048 ret = -ENODEV;
1da177e4
LT		 3049 goto probe_failed;
3050 }
3051
3b1bef64
CD		 3052 if (IS_QLAFX00(ha))
3053 host->can_queue = QLAFX00_MAX_CANQUEUE;
3054 else
3055 host->can_queue = req->num_outstanding_cmds - 10;
3056
3057 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3058 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3059 host->can_queue, base_vha->req,
3060 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3061
093df737 3062 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3063 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3064 /* Create start of day qpairs for Block MQ */
3065 if (shost_use_blk_mq(host)) {
3066 for (i = 0; i < ha->max_qpairs; i++)
3067 qla2xxx_create_qpair(base_vha, 5, 0);
3068 }
3069 }
68ca949c 3070
cbc8eb67
AV		 3071 if (ha->flags.running_gold_fw)
3072 goto skip_dpc;
3073
1da177e4
LT		 3074 /*
3075 * Startup the kernel thread for this host adapter
3076 */
39a11240 3077 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3078 "%s_dpc", base_vha->host_str);
39a11240 3079 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3080 ql_log(ql_log_fatal, base_vha, 0x00ed,
3081 "Failed to start DPC thread.\n");
39a11240 3082 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3083 goto probe_failed;
3084 }
7c3df132
SK		 3085 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3086 "DPC thread started successfully.\n");
1da177e4 3087
2d70c103
NB		 3088 /*
3089 * If we're not coming up in initiator mode, we might sit for
3090 * a while without waking up the dpc thread, which leads to a
3091 * stuck process warning. So just kick the dpc once here and
3092 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3093 */
3094 qla2xxx_wake_dpc(base_vha);
3095
ec7193e2 3096 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3097 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3098
81178772
SK		 3099 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3100 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3101 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3102 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3103
3104 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3105 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3106 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3107 INIT_WORK(&ha->idc_state_handler,
3108 qla83xx_idc_state_handler_work);
3109 INIT_WORK(&ha->nic_core_unrecoverable,
3110 qla83xx_nic_core_unrecoverable_work);
3111 }
3112
cbc8eb67 3113skip_dpc:
e315cd28
AC		 3114 list_add_tail(&base_vha->list, &ha->vp_list);
3115 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3116
3117 /* Initialized the timer */
e315cd28 3118 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3119 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3120 "Started qla2x00_timer with "
3121 "interval=%d.\n", WATCH_INTERVAL);
3122 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3123 "Detected hba at address=%p.\n",
3124 ha);
d19044c3 3125
e02587d7 3126 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3127 if (ha->fw_attributes & BIT_4) {
9e522cd8 3128 int prot = 0, guard;
bad75002 3129 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3130 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3131 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3132 if (ql2xenabledif == 1)
3133 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3134 scsi_host_set_prot(host,
8cb2049c 3135 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3136 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3137 | SHOST_DIF_TYPE3_PROTECTION
3138 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3139 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3140 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3141
3142 guard = SHOST_DIX_GUARD_CRC;
3143
3144 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3145 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3146 guard |= SHOST_DIX_GUARD_IP;
3147
3148 scsi_host_set_guard(host, guard);
bad75002
AE		 3149 } else
3150 base_vha->flags.difdix_supported = 0;
3151 }
3152
a9083016
GM		 3153 ha->isp_ops->enable_intrs(ha);
3154
1fe19ee4
AB		 3155 if (IS_QLAFX00(ha)) {
3156 ret = qlafx00_fx_disc(base_vha,
3157 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3158 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3159 QLA_SG_ALL : 128;
3160 }
3161
a1541d5a
AV		 3162 ret = scsi_add_host(host, &pdev->dev);
3163 if (ret)
3164 goto probe_failed;
3165
1486400f
MR		 3166 base_vha->flags.init_done = 1;
3167 base_vha->flags.online = 1;
edaa5c74 3168 ha->prev_minidump_failed = 0;
1486400f 3169
7c3df132
SK		 3170 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3171 "Init done and hba is online.\n");
3172
726b8548
QT		 3173 if (qla_ini_mode_enabled(base_vha) ||
3174 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3175 scsi_scan_host(host);
3176 else
3177 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3178 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3179
e315cd28 3180 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3181
8ae6d9c7 3182 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3183 ret = qlafx00_fx_disc(base_vha,
3184 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3185
3186 /* Register system information */
3187 ret = qlafx00_fx_disc(base_vha,
3188 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3189 }
3190
e315cd28 3191 qla2x00_init_host_attr(base_vha);
a1541d5a 3192
e315cd28 3193 qla2x00_dfs_setup(base_vha);
df613b96 3194
03eb912a
AB		 3195 ql_log(ql_log_info, base_vha, 0x00fb,
3196 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3197 ql_log(ql_log_info, base_vha, 0x00fc,
3198 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3199 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3200 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3201 base_vha->host_no,
df57caba 3202 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3203
2d70c103
NB		 3204 qlt_add_target(ha, base_vha);
3205
6b383979 3206 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3207
3208 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3209 return -ENODEV;
3210
1da177e4
LT		 3211 return 0;
3212
6e9f21f3 3213probe_init_failed:
2afa19a9 3214 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3215 ha->req_q_map[0] = NULL;
3216 clear_bit(0, ha->req_qid_map);
2afa19a9 3217 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3218 ha->rsp_q_map[0] = NULL;
3219 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3220 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3221
1da177e4 3222probe_failed:
b9978769
AV		 3223 if (base_vha->timer_active)
3224 qla2x00_stop_timer(base_vha);
3225 base_vha->flags.online = 0;
3226 if (ha->dpc_thread) {
3227 struct task_struct *t = ha->dpc_thread;
3228
3229 ha->dpc_thread = NULL;
3230 kthread_stop(t);
3231 }
3232
e315cd28 3233 qla2x00_free_device(base_vha);
1da177e4 3234
e315cd28 3235 scsi_host_put(base_vha->host);
1da177e4 3236
e315cd28 3237probe_hw_failed:
1a2fbf18
JL		 3238 qla2x00_clear_drv_active(ha);
3239
0a63ad12 3240iospace_config_failed:
7ec0effd 3241 if (IS_P3P_TYPE(ha)) {
0a63ad12 3242 if (!ha->nx_pcibase)
f73cb695 3243 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3244 if (!ql2xdbwr)
f73cb695 3245 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3246 } else {
3247 if (ha->iobase)
3248 iounmap(ha->iobase);
8ae6d9c7
GM		 3249 if (ha->cregbase)
3250 iounmap(ha->cregbase);
a9083016 3251 }
e315cd28
AC		 3252 pci_release_selected_regions(ha->pdev, ha->bars);
3253 kfree(ha);
3254 ha = NULL;
1da177e4 3255
a1541d5a 3256probe_out:
e315cd28 3257 pci_disable_device(pdev);
a1541d5a 3258 return ret;
1da177e4 3259}
1da177e4 3260
e30d1756
MI		 3261static void
3262qla2x00_shutdown(struct pci_dev *pdev)
3263{
3264 scsi_qla_host_t *vha;
3265 struct qla_hw_data *ha;
3266
552f3f9a
MI		 3267 if (!atomic_read(&pdev->enable_cnt))
3268 return;
3269
e30d1756
MI		 3270 vha = pci_get_drvdata(pdev);
3271 ha = vha->hw;
3272
42479343
AB		 3273 /* Notify ISPFX00 firmware */
3274 if (IS_QLAFX00(ha))
3275 qlafx00_driver_shutdown(vha, 20);
3276
e30d1756
MI		 3277 /* Turn-off FCE trace */
3278 if (ha->flags.fce_enabled) {
3279 qla2x00_disable_fce_trace(vha, NULL, NULL);
3280 ha->flags.fce_enabled = 0;
3281 }
3282
3283 /* Turn-off EFT trace */
3284 if (ha->eft)
3285 qla2x00_disable_eft_trace(vha);
3286
3287 /* Stop currently executing firmware. */
3288 qla2x00_try_to_stop_firmware(vha);
3289
3290 /* Turn adapter off line */
3291 vha->flags.online = 0;
3292
3293 /* turn-off interrupts on the card */
3294 if (ha->interrupts_on) {
3295 vha->flags.init_done = 0;
3296 ha->isp_ops->disable_intrs(ha);
3297 }
3298
3299 qla2x00_free_irqs(vha);
3300
3301 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3302
3303 pci_disable_pcie_error_reporting(pdev);
3304 pci_disable_device(pdev);
e30d1756
MI		 3305}
3306
fe1b806f 3307/* Deletes all the virtual ports for a given ha */
4c993f76 3308static void
fe1b806f 3309qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3310{
fe1b806f 3311 scsi_qla_host_t *vha;
feafb7b1 3312 unsigned long flags;
e315cd28 3313
43ebf16d
AE		 3314 mutex_lock(&ha->vport_lock);
3315 while (ha->cur_vport_count) {
43ebf16d 3316 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3317
43ebf16d
AE		 3318 BUG_ON(base_vha->list.next == &ha->vp_list);
3319 /* This assumes first entry in ha->vp_list is always base vha */
3320 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3321 scsi_host_get(vha->host);
feafb7b1 3322
43ebf16d
AE		 3323 spin_unlock_irqrestore(&ha->vport_slock, flags);
3324 mutex_unlock(&ha->vport_lock);
3325
3326 fc_vport_terminate(vha->fc_vport);
3327 scsi_host_put(vha->host);
feafb7b1 3328
43ebf16d 3329 mutex_lock(&ha->vport_lock);
e315cd28 3330 }
43ebf16d 3331 mutex_unlock(&ha->vport_lock);
fe1b806f 3332}
1da177e4 3333
fe1b806f
CD		 3334/* Stops all deferred work threads */
3335static void
3336qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3337{
7d613ac6
SV		 3338 /* Cancel all work and destroy DPC workqueues */
3339 if (ha->dpc_lp_wq) {
3340 cancel_work_sync(&ha->idc_aen);
3341 destroy_workqueue(ha->dpc_lp_wq);
3342 ha->dpc_lp_wq = NULL;
3343 }
3344
3345 if (ha->dpc_hp_wq) {
3346 cancel_work_sync(&ha->nic_core_reset);
3347 cancel_work_sync(&ha->idc_state_handler);
3348 cancel_work_sync(&ha->nic_core_unrecoverable);
3349 destroy_workqueue(ha->dpc_hp_wq);
3350 ha->dpc_hp_wq = NULL;
3351 }
3352
b9978769
AV		 3353 /* Kill the kernel thread for this host */
3354 if (ha->dpc_thread) {
3355 struct task_struct *t = ha->dpc_thread;
3356
3357 /*
3358 * qla2xxx_wake_dpc checks for ->dpc_thread
3359 * so we need to zero it out.
3360 */
3361 ha->dpc_thread = NULL;
3362 kthread_stop(t);
3363 }
fe1b806f 3364}
1da177e4 3365
fe1b806f
CD		 3366static void
3367qla2x00_unmap_iobases(struct qla_hw_data *ha)
3368{
a9083016 3369 if (IS_QLA82XX(ha)) {
b963752f 3370
f73cb695 3371 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3372 if (!ql2xdbwr)
f73cb695 3373 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3374 } else {
3375 if (ha->iobase)
3376 iounmap(ha->iobase);
1da177e4 3377
8ae6d9c7
GM		 3378 if (ha->cregbase)
3379 iounmap(ha->cregbase);
3380
a9083016
GM		 3381 if (ha->mqiobase)
3382 iounmap(ha->mqiobase);
6246b8a1 3383
f73cb695 3384 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3385 iounmap(ha->msixbase);
a9083016 3386 }
fe1b806f
CD		 3387}
3388
3389static void
db7157d4 3390qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3391{
fe1b806f
CD		 3392 if (IS_QLA8044(ha)) {
3393 qla8044_idc_lock(ha);
c41afc9a 3394 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3395 qla8044_idc_unlock(ha);
3396 } else if (IS_QLA82XX(ha)) {
3397 qla82xx_idc_lock(ha);
3398 qla82xx_clear_drv_active(ha);
3399 qla82xx_idc_unlock(ha);
3400 }
3401}
3402
3403static void
3404qla2x00_remove_one(struct pci_dev *pdev)
3405{
3406 scsi_qla_host_t *base_vha;
3407 struct qla_hw_data *ha;
3408
beb9e315
JL		 3409 base_vha = pci_get_drvdata(pdev);
3410 ha = base_vha->hw;
3411
3412 /* Indicate device removal to prevent future board_disable and wait
3413 * until any pending board_disable has completed. */
3414 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3415 cancel_work_sync(&ha->board_disable);
3416
fe1b806f 3417 /*
beb9e315
JL		 3418 * If the PCI device is disabled then there was a PCI-disconnect and
3419 * qla2x00_disable_board_on_pci_error has taken care of most of the
3420 * resources.
fe1b806f 3421 */
beb9e315 3422 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3423 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3424 base_vha->gnl.l, base_vha->gnl.ldma);
3425
beb9e315
JL		 3426 scsi_host_put(base_vha->host);
3427 kfree(ha);
3428 pci_set_drvdata(pdev, NULL);
fe1b806f 3429 return;
beb9e315 3430 }
638a1a01
SC		 3431 qla2x00_wait_for_hba_ready(base_vha);
3432
726b8548
QT		 3433 /*
3434 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3435 * where it was set first.
3436 */
3437 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3438 return;
3439
fe1b806f 3440 set_bit(UNLOADING, &base_vha->dpc_flags);
726b8548
QT		 3441 dma_free_coherent(&ha->pdev->dev,
3442 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3443
3444 if (IS_QLAFX00(ha))
3445 qlafx00_driver_shutdown(base_vha, 20);
3446
3447 qla2x00_delete_all_vps(ha, base_vha);
3448
3449 if (IS_QLA8031(ha)) {
3450 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3451 "Clearing fcoe driver presence.\n");
3452 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3453 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3454 "Error while clearing DRV-Presence.\n");
3455 }
3456
3457 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3458
3459 qla2x00_dfs_remove(base_vha);
3460
3461 qla84xx_put_chip(base_vha);
3462
2d5a4c34
HM		 3463 /* Laser should be disabled only for ISP2031 */
3464 if (IS_QLA2031(ha))
3465 qla83xx_disable_laser(base_vha);
3466
fe1b806f
CD		 3467 /* Disable timer */
3468 if (base_vha->timer_active)
3469 qla2x00_stop_timer(base_vha);
3470
3471 base_vha->flags.online = 0;
3472
b0d6cabd
HM		 3473 /* free DMA memory */
3474 if (ha->exlogin_buf)
3475 qla2x00_free_exlogin_buffer(ha);
3476
2f56a7f1
HM		 3477 /* free DMA memory */
3478 if (ha->exchoffld_buf)
3479 qla2x00_free_exchoffld_buffer(ha);
3480
fe1b806f
CD		 3481 qla2x00_destroy_deferred_work(ha);
3482
3483 qlt_remove_target(ha, base_vha);
3484
3485 qla2x00_free_sysfs_attr(base_vha, true);
3486
3487 fc_remove_host(base_vha->host);
482c9dc7 3488 qlt_remove_target_resources(ha);
fe1b806f
CD		 3489
3490 scsi_remove_host(base_vha->host);
3491
3492 qla2x00_free_device(base_vha);
3493
db7157d4 3494 qla2x00_clear_drv_active(ha);
fe1b806f 3495
d2749ffa
AE		 3496 scsi_host_put(base_vha->host);
3497
fe1b806f 3498 qla2x00_unmap_iobases(ha);
73208dfd 3499
e315cd28
AC		 3500 pci_release_selected_regions(ha->pdev, ha->bars);
3501 kfree(ha);
3502 ha = NULL;
1da177e4 3503
90a86fc0
JC		 3504 pci_disable_pcie_error_reporting(pdev);
3505
665db93b 3506 pci_disable_device(pdev);
1da177e4 3507}
1da177e4
LT		 3508
3509static void
e315cd28 3510qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3511{
e315cd28 3512 struct qla_hw_data *ha = vha->hw;
1da177e4 3513
85880801
AV		 3514 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3515
3516 /* Disable timer */
3517 if (vha->timer_active)
3518 qla2x00_stop_timer(vha);
3519
2afa19a9 3520 qla25xx_delete_queues(vha);
fe1b806f 3521
df613b96 3522 if (ha->flags.fce_enabled)
e315cd28 3523 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3524
a7a167bf 3525 if (ha->eft)
e315cd28 3526 qla2x00_disable_eft_trace(vha);
a7a167bf 3527
f6ef3b18 3528 /* Stop currently executing firmware. */
e315cd28 3529 qla2x00_try_to_stop_firmware(vha);
1da177e4 3530
85880801
AV		 3531 vha->flags.online = 0;
3532
f6ef3b18 3533 /* turn-off interrupts on the card */
a9083016
GM		 3534 if (ha->interrupts_on) {
3535 vha->flags.init_done = 0;
fd34f556 3536 ha->isp_ops->disable_intrs(ha);
a9083016 3537 }
f6ef3b18 3538
093df737
QT		 3539 qla2x00_free_fcports(vha);
3540
e315cd28 3541 qla2x00_free_irqs(vha);
1da177e4 3542
093df737
QT		 3543 /* Flush the work queue and remove it */
3544 if (ha->wq) {
3545 flush_workqueue(ha->wq);
3546 destroy_workqueue(ha->wq);
3547 ha->wq = NULL;
3548 }
3549
8867048b 3550
e315cd28 3551 qla2x00_mem_free(ha);
73208dfd 3552
08de2844
GM		 3553 qla82xx_md_free(vha);
3554
73208dfd 3555 qla2x00_free_queues(ha);
1da177e4
LT		 3556}
3557
8867048b
CD		 3558void qla2x00_free_fcports(struct scsi_qla_host *vha)
3559{
3560 fc_port_t *fcport, *tfcport;
3561
3562 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3563 list_del(&fcport->list);
5f16b331 3564 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3565 kfree(fcport);
3566 fcport = NULL;
3567 }
3568}
3569
d97994dc 3570static inline void
e315cd28 3571qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3572 int defer)
3573{
d97994dc 3574 struct fc_rport *rport;
67becc00 3575 scsi_qla_host_t *base_vha;
044d78e1 3576 unsigned long flags;
d97994dc
AV		 3577
3578 if (!fcport->rport)
3579 return;
3580
3581 rport = fcport->rport;
3582 if (defer) {
67becc00 3583 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3584 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3585 fcport->drport = rport;
044d78e1 3586 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3587 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3588 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3589 qla2xxx_wake_dpc(base_vha);
2d70c103 3590 } else {
df673274 3591 int now;
726b8548
QT		 3592 if (rport) {
3593 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3594 "%s %8phN. rport %p roles %x \n",
3595 __func__, fcport->port_name, rport,
3596 rport->roles);
d20ed91b 3597 fc_remote_port_delete(rport);
726b8548 3598 }
df673274 3599 qlt_do_generation_tick(vha, &now);
2d70c103 3600 }
d97994dc
AV		 3601}
3602
1da177e4
LT		 3603/*
3604 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3605 *
3606 * Input: ha = adapter block pointer. fcport = port structure pointer.
3607 *
3608 * Return: None.
3609 *
3610 * Context:
3611 */
e315cd28 3612void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3613 int do_login, int defer)
1da177e4 3614{
8ae6d9c7
GM		 3615 if (IS_QLAFX00(vha->hw)) {
3616 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3617 qla2x00_schedule_rport_del(vha, fcport, defer);
3618 return;
3619 }
3620
2c3dfe3f 3621 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3622 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3623 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3624 qla2x00_schedule_rport_del(vha, fcport, defer);
3625 }
fa2a1ce5 3626 /*
1da177e4
LT		 3627 * We may need to retry the login, so don't change the state of the
3628 * port but do the retries.
3629 */
3630 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3631 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3632
3633 if (!do_login)
3634 return;
3635
a1d0285e
AE		 3636 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3637
1da177e4 3638 if (fcport->login_retry == 0) {
e315cd28 3639 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3640
7c3df132 3641 ql_dbg(ql_dbg_disc, vha, 0x2067,
726b8548 3642 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3643 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3644 }
3645}
3646
3647/*
3648 * qla2x00_mark_all_devices_lost
3649 * Updates fcport state when device goes offline.
3650 *
3651 * Input:
3652 * ha = adapter block pointer.
3653 * fcport = port structure pointer.
3654 *
3655 * Return:
3656 * None.
3657 *
3658 * Context:
3659 */
3660void
e315cd28 3661qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3662{
3663 fc_port_t *fcport;
3664
726b8548
QT		 3665 ql_dbg(ql_dbg_disc, vha, 0xffff,
3666 "Mark all dev lost\n");
3667
e315cd28 3668 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3669 fcport->scan_state = 0;
3670 qlt_schedule_sess_for_deletion_lock(fcport);
3671
c6d39e23 3672 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3673 continue;
0d6e61bc 3674
1da177e4
LT		 3675 /*
3676 * No point in marking the device as lost, if the device is
3677 * already DEAD.
3678 */
3679 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3680 continue;
e315cd28 3681 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3682 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3683 if (defer)
3684 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3685 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3686 qla2x00_schedule_rport_del(vha, fcport, defer);
3687 }
1da177e4
LT		 3688 }
3689}
3690
3691/*
3692* qla2x00_mem_alloc
3693* Allocates adapter memory.
3694*
3695* Returns:
3696* 0 = success.
e8711085 3697* !0 = failure.
1da177e4 3698*/
e8711085 3699static int
73208dfd
AC		 3700qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3701 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3702{
3703 char name[16];
1da177e4 3704
e8711085 3705 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3706 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3707 if (!ha->init_cb)
e315cd28 3708 goto fail;
e8711085 3709
2d70c103
NB		 3710 if (qlt_mem_alloc(ha) < 0)
3711 goto fail_free_init_cb;
3712
642ef983
CD		 3713 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3714 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3715 if (!ha->gid_list)
2d70c103 3716 goto fail_free_tgt_mem;
1da177e4 3717
e8711085
AV		 3718 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3719 if (!ha->srb_mempool)
e315cd28 3720 goto fail_free_gid_list;
e8711085 3721
7ec0effd 3722 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3723 /* Allocate cache for CT6 Ctx. */
3724 if (!ctx_cachep) {
3725 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3726 sizeof(struct ct6_dsd), 0,
3727 SLAB_HWCACHE_ALIGN, NULL);
3728 if (!ctx_cachep)
fc1ffd6c 3729 goto fail_free_srb_mempool;
a9083016
GM		 3730 }
3731 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3732 ctx_cachep);
3733 if (!ha->ctx_mempool)
3734 goto fail_free_srb_mempool;
7c3df132
SK		 3735 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3736 "ctx_cachep=%p ctx_mempool=%p.\n",
3737 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3738 }
3739
e8711085
AV		 3740 /* Get memory for cached NVRAM */
3741 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3742 if (!ha->nvram)
a9083016 3743 goto fail_free_ctx_mempool;
e8711085 3744
e315cd28
AC		 3745 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3746 ha->pdev->device);
3747 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3748 DMA_POOL_SIZE, 8, 0);
3749 if (!ha->s_dma_pool)
3750 goto fail_free_nvram;
3751
7c3df132
SK		 3752 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3753 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3754 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3755
7ec0effd 3756 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3757 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3758 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3759 if (!ha->dl_dma_pool) {
7c3df132
SK		 3760 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3761 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3762 goto fail_s_dma_pool;
3763 }
3764
3765 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3766 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3767 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3768 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3769 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3770 goto fail_dl_dma_pool;
3771 }
7c3df132
SK		 3772 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3773 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3774 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3775 }
3776
e8711085
AV		 3777 /* Allocate memory for SNS commands */
3778 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3779 /* Get consistent memory allocated for SNS commands */
e8711085 3780 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3781 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3782 if (!ha->sns_cmd)
e315cd28 3783 goto fail_dma_pool;
7c3df132 3784 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3785 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3786 } else {
e315cd28 3787 /* Get consistent memory allocated for MS IOCB */
e8711085 3788 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3789 &ha->ms_iocb_dma);
e8711085 3790 if (!ha->ms_iocb)
e315cd28
AC		 3791 goto fail_dma_pool;
3792 /* Get consistent memory allocated for CT SNS commands */
e8711085 3793 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3794 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3795 if (!ha->ct_sns)
3796 goto fail_free_ms_iocb;
7c3df132
SK		 3797 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3798 "ms_iocb=%p ct_sns=%p.\n",
3799 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3800 }
3801
e315cd28 3802 /* Allocate memory for request ring */
73208dfd
AC		 3803 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3804 if (!*req) {
7c3df132
SK		 3805 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3806 "Failed to allocate memory for req.\n");
e315cd28
AC		 3807 goto fail_req;
3808 }
73208dfd
AC		 3809 (*req)->length = req_len;
3810 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3811 ((*req)->length + 1) * sizeof(request_t),
3812 &(*req)->dma, GFP_KERNEL);
3813 if (!(*req)->ring) {
7c3df132
SK		 3814 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3815 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3816 goto fail_req_ring;
3817 }
3818 /* Allocate memory for response ring */
73208dfd
AC		 3819 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3820 if (!*rsp) {
7c3df132
SK		 3821 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3822 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3823 goto fail_rsp;
3824 }
73208dfd
AC		 3825 (*rsp)->hw = ha;
3826 (*rsp)->length = rsp_len;
3827 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3828 ((*rsp)->length + 1) * sizeof(response_t),
3829 &(*rsp)->dma, GFP_KERNEL);
3830 if (!(*rsp)->ring) {
7c3df132
SK		 3831 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3832 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3833 goto fail_rsp_ring;
3834 }
73208dfd
AC		 3835 (*req)->rsp = *rsp;
3836 (*rsp)->req = *req;
7c3df132
SK		 3837 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3838 "req=%p req->length=%d req->ring=%p rsp=%p "
3839 "rsp->length=%d rsp->ring=%p.\n",
3840 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3841 (*rsp)->ring);
73208dfd
AC		 3842 /* Allocate memory for NVRAM data for vports */
3843 if (ha->nvram_npiv_size) {
3844 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3845 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3846 if (!ha->npiv_info) {
7c3df132
SK		 3847 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3848 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3849 goto fail_npiv_info;
3850 }
3851 } else
3852 ha->npiv_info = NULL;
e8711085 3853
b64b0e8f 3854 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3855 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3856 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3857 &ha->ex_init_cb_dma);
3858 if (!ha->ex_init_cb)
3859 goto fail_ex_init_cb;
7c3df132
SK		 3860 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3861 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3862 }
3863
a9083016
GM		 3864 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3865
5ff1d584
AV		 3866 /* Get consistent memory allocated for Async Port-Database. */
3867 if (!IS_FWI2_CAPABLE(ha)) {
3868 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3869 &ha->async_pd_dma);
3870 if (!ha->async_pd)
3871 goto fail_async_pd;
7c3df132
SK		 3872 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3873 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3874 }
3875
e315cd28 3876 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3877
3878 /* Allocate memory for our loop_id bitmap */
3879 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3880 GFP_KERNEL);
3881 if (!ha->loop_id_map)
fc1ffd6c 3882 goto fail_loop_id_map;
5f16b331
CD		 3883 else {
3884 qla2x00_set_reserved_loop_ids(ha);
3885 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3886 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3887 }
3888
b2a72ec3 3889 return 0;
e315cd28 3890
fc1ffd6c
QT		 3891fail_loop_id_map:
3892 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3893fail_async_pd:
3894 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3895fail_ex_init_cb:
3896 kfree(ha->npiv_info);
73208dfd
AC		 3897fail_npiv_info:
3898 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3899 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3900 (*rsp)->ring = NULL;
3901 (*rsp)->dma = 0;
e315cd28 3902fail_rsp_ring:
73208dfd 3903 kfree(*rsp);
e315cd28 3904fail_rsp:
73208dfd
AC		 3905 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3906 sizeof(request_t), (*req)->ring, (*req)->dma);
3907 (*req)->ring = NULL;
3908 (*req)->dma = 0;
e315cd28 3909fail_req_ring:
73208dfd 3910 kfree(*req);
e315cd28
AC		 3911fail_req:
3912 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3913 ha->ct_sns, ha->ct_sns_dma);
3914 ha->ct_sns = NULL;
3915 ha->ct_sns_dma = 0;
e8711085
AV		 3916fail_free_ms_iocb:
3917 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3918 ha->ms_iocb = NULL;
3919 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3920
3921 if (ha->sns_cmd)
3922 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3923 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3924fail_dma_pool:
bad75002 3925 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3926 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3927 ha->fcp_cmnd_dma_pool = NULL;
3928 }
3929fail_dl_dma_pool:
bad75002 3930 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3931 dma_pool_destroy(ha->dl_dma_pool);
3932 ha->dl_dma_pool = NULL;
3933 }
3934fail_s_dma_pool:
e315cd28
AC		 3935 dma_pool_destroy(ha->s_dma_pool);
3936 ha->s_dma_pool = NULL;
e8711085
AV		 3937fail_free_nvram:
3938 kfree(ha->nvram);
3939 ha->nvram = NULL;
a9083016 3940fail_free_ctx_mempool:
fc1ffd6c
QT		 3941 if (ha->ctx_mempool)
3942 mempool_destroy(ha->ctx_mempool);
a9083016 3943 ha->ctx_mempool = NULL;
e8711085 3944fail_free_srb_mempool:
fc1ffd6c
QT		 3945 if (ha->srb_mempool)
3946 mempool_destroy(ha->srb_mempool);
e8711085 3947 ha->srb_mempool = NULL;
e8711085 3948fail_free_gid_list:
642ef983
CD		 3949 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3950 ha->gid_list,
e315cd28 3951 ha->gid_list_dma);
e8711085
AV		 3952 ha->gid_list = NULL;
3953 ha->gid_list_dma = 0;
2d70c103
NB		 3954fail_free_tgt_mem:
3955 qlt_mem_free(ha);
e315cd28
AC		 3956fail_free_init_cb:
3957 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3958 ha->init_cb_dma);
3959 ha->init_cb = NULL;
3960 ha->init_cb_dma = 0;
e8711085 3961fail:
7c3df132
SK		 3962 ql_log(ql_log_fatal, NULL, 0x0030,
3963 "Memory allocation failure.\n");
e8711085 3964 return -ENOMEM;
1da177e4
LT		 3965}
3966
b0d6cabd
HM		 3967int
3968qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3969{
3970 int rval;
3971 uint16_t size, max_cnt, temp;
3972 struct qla_hw_data *ha = vha->hw;
3973
3974 /* Return if we don't need to alloacate any extended logins */
3975 if (!ql2xexlogins)
3976 return QLA_SUCCESS;
3977
3978 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3979 max_cnt = 0;
3980 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3981 if (rval != QLA_SUCCESS) {
3982 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3983 "Failed to get exlogin status.\n");
3984 return rval;
3985 }
3986
3987 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3988 ha->exlogin_size = (size * temp);
3989 ql_log(ql_log_info, vha, 0xd024,
3990 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3991 max_cnt, size, temp);
3992
3993 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3994 ha->exlogin_size);
3995
3996 /* Get consistent memory for extended logins */
3997 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3998 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3999 if (!ha->exlogin_buf) {
4000 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4001 "Failed to allocate memory for exlogin_buf_dma.\n");
4002 return -ENOMEM;
4003 }
4004
4005 /* Now configure the dma buffer */
4006 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4007 if (rval) {
4008 ql_log(ql_log_fatal, vha, 0x00cf,
4009 "Setup extended login buffer ****FAILED****.\n");
4010 qla2x00_free_exlogin_buffer(ha);
4011 }
4012
4013 return rval;
4014}
4015
4016/*
4017* qla2x00_free_exlogin_buffer
4018*
4019* Input:
4020* ha = adapter block pointer
4021*/
4022void
4023qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4024{
4025 if (ha->exlogin_buf) {
4026 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4027 ha->exlogin_buf, ha->exlogin_buf_dma);
4028 ha->exlogin_buf = NULL;
4029 ha->exlogin_size = 0;
4030 }
4031}
4032
2f56a7f1
HM		 4033int
4034qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4035{
4036 int rval;
4037 uint16_t size, max_cnt, temp;
4038 struct qla_hw_data *ha = vha->hw;
4039
4040 /* Return if we don't need to alloacate any extended logins */
4041 if (!ql2xexchoffld)
4042 return QLA_SUCCESS;
4043
4044 ql_log(ql_log_info, vha, 0xd014,
4045 "Exchange offload count: %d.\n", ql2xexlogins);
4046
4047 max_cnt = 0;
4048 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4049 if (rval != QLA_SUCCESS) {
4050 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4051 "Failed to get exlogin status.\n");
4052 return rval;
4053 }
4054
4055 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
4056 ha->exchoffld_size = (size * temp);
4057 ql_log(ql_log_info, vha, 0xd016,
4058 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4059 max_cnt, size, temp);
4060
4061 ql_log(ql_log_info, vha, 0xd017,
4062 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
4063
4064 /* Get consistent memory for extended logins */
4065 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4066 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4067 if (!ha->exchoffld_buf) {
4068 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4069 "Failed to allocate memory for exchoffld_buf_dma.\n");
4070 return -ENOMEM;
4071 }
4072
4073 /* Now configure the dma buffer */
4074 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4075 if (rval) {
4076 ql_log(ql_log_fatal, vha, 0xd02e,
4077 "Setup exchange offload buffer ****FAILED****.\n");
4078 qla2x00_free_exchoffld_buffer(ha);
4079 }
4080
4081 return rval;
4082}
4083
4084/*
4085* qla2x00_free_exchoffld_buffer
4086*
4087* Input:
4088* ha = adapter block pointer
4089*/
4090void
4091qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4092{
4093 if (ha->exchoffld_buf) {
4094 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4095 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4096 ha->exchoffld_buf = NULL;
4097 ha->exchoffld_size = 0;
4098 }
4099}
4100
1da177e4 4101/*
e30d1756
MI		 4102* qla2x00_free_fw_dump
4103* Frees fw dump stuff.
1da177e4
LT		 4104*
4105* Input:
7ec0effd 4106* ha = adapter block pointer
1da177e4 4107*/
a824ebb3 4108static void
e30d1756 4109qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4110{
df613b96 4111 if (ha->fce)
f73cb695
CD		 4112 dma_free_coherent(&ha->pdev->dev,
4113 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4114
f73cb695
CD		 4115 if (ha->eft)
4116 dma_free_coherent(&ha->pdev->dev,
4117 EFT_SIZE, ha->eft, ha->eft_dma);
4118
4119 if (ha->fw_dump)
a7a167bf 4120 vfree(ha->fw_dump);
f73cb695
CD		 4121 if (ha->fw_dump_template)
4122 vfree(ha->fw_dump_template);
4123
e30d1756
MI		 4124 ha->fce = NULL;
4125 ha->fce_dma = 0;
4126 ha->eft = NULL;
4127 ha->eft_dma = 0;
e30d1756 4128 ha->fw_dumped = 0;
61f098dd 4129 ha->fw_dump_cap_flags = 0;
e30d1756 4130 ha->fw_dump_reading = 0;
f73cb695
CD		 4131 ha->fw_dump = NULL;
4132 ha->fw_dump_len = 0;
4133 ha->fw_dump_template = NULL;
4134 ha->fw_dump_template_len = 0;
e30d1756
MI		 4135}
4136
4137/*
4138* qla2x00_mem_free
4139* Frees all adapter allocated memory.
4140*
4141* Input:
4142* ha = adapter block pointer.
4143*/
4144static void
4145qla2x00_mem_free(struct qla_hw_data *ha)
4146{
4147 qla2x00_free_fw_dump(ha);
4148
81178772
SK		 4149 if (ha->mctp_dump)
4150 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4151 ha->mctp_dump_dma);
4152
e30d1756
MI		 4153 if (ha->srb_mempool)
4154 mempool_destroy(ha->srb_mempool);
a7a167bf 4155
11bbc1d8
AV		 4156 if (ha->dcbx_tlv)
4157 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4158 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4159
ce0423f4
AV		 4160 if (ha->xgmac_data)
4161 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4162 ha->xgmac_data, ha->xgmac_data_dma);
4163
1da177e4
LT		 4164 if (ha->sns_cmd)
4165 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4166 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4167
4168 if (ha->ct_sns)
4169 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4170 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4171
88729e53
AV		 4172 if (ha->sfp_data)
4173 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4174
1da177e4
LT		 4175 if (ha->ms_iocb)
4176 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4177
b64b0e8f 4178 if (ha->ex_init_cb)
a9083016
GM		 4179 dma_pool_free(ha->s_dma_pool,
4180 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4181
5ff1d584
AV		 4182 if (ha->async_pd)
4183 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4184
1da177e4
LT		 4185 if (ha->s_dma_pool)
4186 dma_pool_destroy(ha->s_dma_pool);
4187
1da177e4 4188 if (ha->gid_list)
642ef983
CD		 4189 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4190 ha->gid_list, ha->gid_list_dma);
1da177e4 4191
a9083016
GM		 4192 if (IS_QLA82XX(ha)) {
4193 if (!list_empty(&ha->gbl_dsd_list)) {
4194 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4195
4196 /* clean up allocated prev pool */
4197 list_for_each_entry_safe(dsd_ptr,
4198 tdsd_ptr, &ha->gbl_dsd_list, list) {
4199 dma_pool_free(ha->dl_dma_pool,
4200 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4201 list_del(&dsd_ptr->list);
4202 kfree(dsd_ptr);
4203 }
4204 }
4205 }
4206
4207 if (ha->dl_dma_pool)
4208 dma_pool_destroy(ha->dl_dma_pool);
4209
4210 if (ha->fcp_cmnd_dma_pool)
4211 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4212
4213 if (ha->ctx_mempool)
4214 mempool_destroy(ha->ctx_mempool);
4215
2d70c103
NB		 4216 qlt_mem_free(ha);
4217
e315cd28
AC		 4218 if (ha->init_cb)
4219 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4220 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4221 vfree(ha->optrom_buffer);
4222 kfree(ha->nvram);
73208dfd 4223 kfree(ha->npiv_info);
7a67735b 4224 kfree(ha->swl);
5f16b331 4225 kfree(ha->loop_id_map);
1da177e4 4226
e8711085 4227 ha->srb_mempool = NULL;
a9083016 4228 ha->ctx_mempool = NULL;
1da177e4
LT		 4229 ha->sns_cmd = NULL;
4230 ha->sns_cmd_dma = 0;
4231 ha->ct_sns = NULL;
4232 ha->ct_sns_dma = 0;
4233 ha->ms_iocb = NULL;
4234 ha->ms_iocb_dma = 0;
1da177e4
LT		 4235 ha->init_cb = NULL;
4236 ha->init_cb_dma = 0;
b64b0e8f
AV		 4237 ha->ex_init_cb = NULL;
4238 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4239 ha->async_pd = NULL;
4240 ha->async_pd_dma = 0;
1da177e4
LT		 4241
4242 ha->s_dma_pool = NULL;
a9083016
GM		 4243 ha->dl_dma_pool = NULL;
4244 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4245
1da177e4
LT		 4246 ha->gid_list = NULL;
4247 ha->gid_list_dma = 0;
2d70c103
NB		 4248
4249 ha->tgt.atio_ring = NULL;
4250 ha->tgt.atio_dma = 0;
4251 ha->tgt.tgt_vp_map = NULL;
e315cd28 4252}
1da177e4 4253
e315cd28
AC		 4254struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4255 struct qla_hw_data *ha)
4256{
4257 struct Scsi_Host *host;
4258 struct scsi_qla_host *vha = NULL;
854165f4 4259
e315cd28 4260 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4261 if (!host) {
7c3df132
SK		 4262 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4263 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4264 return NULL;
e315cd28
AC		 4265 }
4266
4267 /* Clear our data area */
4268 vha = shost_priv(host);
4269 memset(vha, 0, sizeof(scsi_qla_host_t));
4270
4271 vha->host = host;
4272 vha->host_no = host->host_no;
4273 vha->hw = ha;
4274
4275 INIT_LIST_HEAD(&vha->vp_fcports);
4276 INIT_LIST_HEAD(&vha->work_list);
4277 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4278 INIT_LIST_HEAD(&vha->qla_cmd_list);
4279 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4280 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4281 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4282 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4283 INIT_LIST_HEAD(&vha->gnl.fcports);
e315cd28 4284
f999f4c1 4285 spin_lock_init(&vha->work_lock);
8b2f5ff3 4286 spin_lock_init(&vha->cmd_list_lock);
726b8548 4287 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4288 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4289
2fdbc65e
BVA		 4290 vha->gnl.size = sizeof(struct get_name_list_extended) *
4291 (ha->max_loop_id + 1);
41dc529a
QT		 4292 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4293 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4294 if (!vha->gnl.l) {
4295 ql_log(ql_log_fatal, vha, 0xffff,
4296 "Alloc failed for name list.\n");
4297 scsi_remove_host(vha->host);
4298 return NULL;
4299 }
f999f4c1 4300
e315cd28 4301 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4302 ql_dbg(ql_dbg_init, vha, 0x0041,
4303 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4304 vha->host, vha->hw, vha,
4305 dev_name(&(ha->pdev->dev)));
4306
e315cd28 4307 return vha;
1da177e4
LT		 4308}
4309
726b8548 4310struct qla_work_evt *
f999f4c1 4311qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4312{
4313 struct qla_work_evt *e;
feafb7b1
AE		 4314 uint8_t bail;
4315
4316 QLA_VHA_MARK_BUSY(vha, bail);
4317 if (bail)
4318 return NULL;
0971de7f 4319
f999f4c1 4320 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4321 if (!e) {
4322 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4323 return NULL;
feafb7b1 4324 }
0971de7f
AV		 4325
4326 INIT_LIST_HEAD(&e->list);
4327 e->type = type;
4328 e->flags = QLA_EVT_FLAG_FREE;
4329 return e;
4330}
4331
726b8548 4332int
f999f4c1 4333qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4334{
f999f4c1 4335 unsigned long flags;
0971de7f 4336
f999f4c1 4337 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4338 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4339 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4340
4341 if (QLA_EARLY_LINKUP(vha->hw))
4342 schedule_work(&vha->iocb_work);
4343 else
4344 qla2xxx_wake_dpc(vha);
f999f4c1 4345
0971de7f
AV		 4346 return QLA_SUCCESS;
4347}
4348
4349int
e315cd28 4350qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4351 u32 data)
4352{
4353 struct qla_work_evt *e;
4354
f999f4c1 4355 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4356 if (!e)
4357 return QLA_FUNCTION_FAILED;
4358
4359 e->u.aen.code = code;
4360 e->u.aen.data = data;
f999f4c1 4361 return qla2x00_post_work(vha, e);
0971de7f
AV		 4362}
4363
8a659571
AV		 4364int
4365qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4366{
4367 struct qla_work_evt *e;
4368
f999f4c1 4369 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4370 if (!e)
4371 return QLA_FUNCTION_FAILED;
4372
4373 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4374 return qla2x00_post_work(vha, e);
8a659571
AV		 4375}
4376
ac280b67
AV		 4377#define qla2x00_post_async_work(name, type) \
4378int qla2x00_post_async_##name##_work( \
4379 struct scsi_qla_host *vha, \
4380 fc_port_t *fcport, uint16_t *data) \
4381{ \
4382 struct qla_work_evt *e; \
4383 \
4384 e = qla2x00_alloc_work(vha, type); \
4385 if (!e) \
4386 return QLA_FUNCTION_FAILED; \
4387 \
4388 e->u.logio.fcport = fcport; \
4389 if (data) { \
4390 e->u.logio.data[0] = data[0]; \
4391 e->u.logio.data[1] = data[1]; \
4392 } \
4393 return qla2x00_post_work(vha, e); \
4394}
4395
4396qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4397qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4398qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4399qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4400qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4401
3420d36c
AV		 4402int
4403qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4404{
4405 struct qla_work_evt *e;
4406
4407 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4408 if (!e)
4409 return QLA_FUNCTION_FAILED;
4410
4411 e->u.uevent.code = code;
4412 return qla2x00_post_work(vha, e);
4413}
4414
4415static void
4416qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4417{
4418 char event_string[40];
4419 char *envp[] = { event_string, NULL };
4420
4421 switch (code) {
4422 case QLA_UEVENT_CODE_FW_DUMP:
4423 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4424 vha->host_no);
4425 break;
4426 default:
4427 /* do nothing */
4428 break;
4429 }
4430 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4431}
4432
8ae6d9c7
GM		 4433int
4434qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4435 uint32_t *data, int cnt)
4436{
4437 struct qla_work_evt *e;
4438
4439 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4440 if (!e)
4441 return QLA_FUNCTION_FAILED;
4442
4443 e->u.aenfx.evtcode = evtcode;
4444 e->u.aenfx.count = cnt;
4445 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4446 return qla2x00_post_work(vha, e);
4447}
4448
726b8548
QT		 4449int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4450{
4451 struct qla_work_evt *e;
4452
4453 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4454 if (!e)
4455 return QLA_FUNCTION_FAILED;
4456
4457 e->u.fcport.fcport = fcport;
4458 return qla2x00_post_work(vha, e);
4459}
4460
4461static
4462void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4463{
4464 unsigned long flags;
4465 fc_port_t *fcport = NULL;
4466 struct qlt_plogi_ack_t *pla =
4467 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4468
4469 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4470 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4471 if (fcport) {
4472 fcport->d_id = e->u.new_sess.id;
4473 if (pla) {
4474 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4475 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4476 /* we took an extra ref_count to prevent PLOGI ACK when
4477 * fcport/sess has not been created.
4478 */
4479 pla->ref_count--;
4480 }
4481 } else {
4482 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4483 if (fcport) {
4484 fcport->d_id = e->u.new_sess.id;
4485 fcport->scan_state = QLA_FCPORT_FOUND;
4486 fcport->flags |= FCF_FABRIC_DEVICE;
4487 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4488
4489 memcpy(fcport->port_name, e->u.new_sess.port_name,
4490 WWN_SIZE);
4491 list_add_tail(&fcport->list, &vha->vp_fcports);
4492
4493 if (pla) {
4494 qlt_plogi_ack_link(vha, pla, fcport,
4495 QLT_PLOGI_LINK_SAME_WWN);
4496 pla->ref_count--;
4497 }
4498 }
4499 }
4500 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4501
4502 if (fcport) {
4503 if (pla)
4504 qlt_plogi_ack_unref(vha, pla);
4505 else
4506 qla24xx_async_gnl(vha, fcport);
4507 }
4508}
4509
ac280b67 4510void
e315cd28 4511qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4512{
f999f4c1
AV		 4513 struct qla_work_evt *e, *tmp;
4514 unsigned long flags;
4515 LIST_HEAD(work);
0971de7f 4516
f999f4c1
AV		 4517 spin_lock_irqsave(&vha->work_lock, flags);
4518 list_splice_init(&vha->work_list, &work);
4519 spin_unlock_irqrestore(&vha->work_lock, flags);
4520
4521 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4522 list_del_init(&e->list);
0971de7f
AV		 4523
4524 switch (e->type) {
4525 case QLA_EVT_AEN:
e315cd28 4526 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4527 e->u.aen.code, e->u.aen.data);
4528 break;
8a659571
AV		 4529 case QLA_EVT_IDC_ACK:
4530 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4531 break;
ac280b67
AV		 4532 case QLA_EVT_ASYNC_LOGIN:
4533 qla2x00_async_login(vha, e->u.logio.fcport,
4534 e->u.logio.data);
4535 break;
ac280b67
AV		 4536 case QLA_EVT_ASYNC_LOGOUT:
4537 qla2x00_async_logout(vha, e->u.logio.fcport);
4538 break;
4539 case QLA_EVT_ASYNC_LOGOUT_DONE:
4540 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4541 e->u.logio.data);
4542 break;
5ff1d584
AV		 4543 case QLA_EVT_ASYNC_ADISC:
4544 qla2x00_async_adisc(vha, e->u.logio.fcport,
4545 e->u.logio.data);
4546 break;
4547 case QLA_EVT_ASYNC_ADISC_DONE:
4548 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4549 e->u.logio.data);
4550 break;
3420d36c
AV		 4551 case QLA_EVT_UEVENT:
4552 qla2x00_uevent_emit(vha, e->u.uevent.code);
4553 break;
8ae6d9c7
GM		 4554 case QLA_EVT_AENFX:
4555 qlafx00_process_aen(vha, e);
4556 break;
726b8548
QT		 4557 case QLA_EVT_GIDPN:
4558 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4559 break;
4560 case QLA_EVT_GPNID:
4561 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4562 break;
4563 case QLA_EVT_GPNID_DONE:
4564 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4565 break;
4566 case QLA_EVT_NEW_SESS:
4567 qla24xx_create_new_sess(vha, e);
4568 break;
4569 case QLA_EVT_GPDB:
4570 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4571 e->u.fcport.opt);
4572 break;
4573 case QLA_EVT_GPSC:
4574 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4575 break;
4576 case QLA_EVT_UPD_FCPORT:
4577 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4578 break;
4579 case QLA_EVT_GNL:
4580 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4581 break;
4582 case QLA_EVT_NACK:
4583 qla24xx_do_nack_work(vha, e);
4584 break;
0971de7f
AV		 4585 }
4586 if (e->flags & QLA_EVT_FLAG_FREE)
4587 kfree(e);
feafb7b1
AE		 4588
4589 /* For each work completed decrement vha ref count */
4590 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4591 }
e315cd28 4592}
f999f4c1 4593
e315cd28
AC		 4594/* Relogins all the fcports of a vport
4595 * Context: dpc thread
4596 */
4597void qla2x00_relogin(struct scsi_qla_host *vha)
4598{
4599 fc_port_t *fcport;
c6b2fca8 4600 int status;
726b8548 4601 struct event_arg ea;
e315cd28
AC		 4602
4603 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4604 /*
4605 * If the port is not ONLINE then try to login
4606 * to it if we haven't run out of retries.
4607 */
5ff1d584
AV		 4608 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4609 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4610 fcport->login_retry--;
e315cd28 4611 if (fcport->flags & FCF_FABRIC_DEVICE) {
726b8548
QT		 4612 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
4613 "%s %8phC DS %d LS %d\n", __func__,
4614 fcport->port_name, fcport->disc_state,
4615 fcport->fw_login_state);
4616 memset(&ea, 0, sizeof(ea));
4617 ea.event = FCME_RELOGIN;
4618 ea.fcport = fcport;
4619 qla2x00_fcport_event_handler(vha, &ea);
4620 } else {
e315cd28
AC		 4621 status = qla2x00_local_device_login(vha,
4622 fcport);
726b8548
QT		 4623 if (status == QLA_SUCCESS) {
4624 fcport->old_loop_id = fcport->loop_id;
4625 ql_dbg(ql_dbg_disc, vha, 0x2003,
4626 "Port login OK: logged in ID 0x%x.\n",
4627 fcport->loop_id);
4628 qla2x00_update_fcport(vha, fcport);
4629 } else if (status == 1) {
4630 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4631 /* retry the login again */
4632 ql_dbg(ql_dbg_disc, vha, 0x2007,
4633 "Retrying %d login again loop_id 0x%x.\n",
4634 fcport->login_retry,
4635 fcport->loop_id);
4636 } else {
4637 fcport->login_retry = 0;
4638 }
e315cd28 4639
726b8548
QT		 4640 if (fcport->login_retry == 0 &&
4641 status != QLA_SUCCESS)
4642 qla2x00_clear_loop_id(fcport);
e315cd28 4643 }
e315cd28
AC		 4644 }
4645 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4646 break;
0971de7f 4647 }
0971de7f
AV		 4648}
4649
7d613ac6
SV		 4650/* Schedule work on any of the dpc-workqueues */
4651void
4652qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4653{
4654 struct qla_hw_data *ha = base_vha->hw;
4655
4656 switch (work_code) {
4657 case MBA_IDC_AEN: /* 0x8200 */
4658 if (ha->dpc_lp_wq)
4659 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4660 break;
4661
4662 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4663 if (!ha->flags.nic_core_reset_hdlr_active) {
4664 if (ha->dpc_hp_wq)
4665 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4666 } else
4667 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4668 "NIC Core reset is already active. Skip "
4669 "scheduling it again.\n");
4670 break;
4671 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4672 if (ha->dpc_hp_wq)
4673 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4674 break;
4675 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4676 if (ha->dpc_hp_wq)
4677 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4678 break;
4679 default:
4680 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4681 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4682 }
4683
4684 return;
4685}
4686
4687/* Work: Perform NIC Core Unrecoverable state handling */
4688void
4689qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4690{
4691 struct qla_hw_data *ha =
2ad1b67c 4692 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4693 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4694 uint32_t dev_state = 0;
4695
4696 qla83xx_idc_lock(base_vha, 0);
4697 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4698 qla83xx_reset_ownership(base_vha);
4699 if (ha->flags.nic_core_reset_owner) {
4700 ha->flags.nic_core_reset_owner = 0;
4701 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4702 QLA8XXX_DEV_FAILED);
4703 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4704 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4705 }
4706 qla83xx_idc_unlock(base_vha, 0);
4707}
4708
4709/* Work: Execute IDC state handler */
4710void
4711qla83xx_idc_state_handler_work(struct work_struct *work)
4712{
4713 struct qla_hw_data *ha =
2ad1b67c 4714 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4715 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4716 uint32_t dev_state = 0;
4717
4718 qla83xx_idc_lock(base_vha, 0);
4719 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4720 if (dev_state == QLA8XXX_DEV_FAILED ||
4721 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4722 qla83xx_idc_state_handler(base_vha);
4723 qla83xx_idc_unlock(base_vha, 0);
4724}
4725
fa492630 4726static int
7d613ac6
SV		 4727qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4728{
4729 int rval = QLA_SUCCESS;
4730 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4731 uint32_t heart_beat_counter1, heart_beat_counter2;
4732
4733 do {
4734 if (time_after(jiffies, heart_beat_wait)) {
4735 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4736 "Nic Core f/w is not alive.\n");
4737 rval = QLA_FUNCTION_FAILED;
4738 break;
4739 }
4740
4741 qla83xx_idc_lock(base_vha, 0);
4742 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4743 &heart_beat_counter1);
4744 qla83xx_idc_unlock(base_vha, 0);
4745 msleep(100);
4746 qla83xx_idc_lock(base_vha, 0);
4747 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4748 &heart_beat_counter2);
4749 qla83xx_idc_unlock(base_vha, 0);
4750 } while (heart_beat_counter1 == heart_beat_counter2);
4751
4752 return rval;
4753}
4754
4755/* Work: Perform NIC Core Reset handling */
4756void
4757qla83xx_nic_core_reset_work(struct work_struct *work)
4758{
4759 struct qla_hw_data *ha =
4760 container_of(work, struct qla_hw_data, nic_core_reset);
4761 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4762 uint32_t dev_state = 0;
4763
81178772
SK		 4764 if (IS_QLA2031(ha)) {
4765 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4766 ql_log(ql_log_warn, base_vha, 0xb081,
4767 "Failed to dump mctp\n");
4768 return;
4769 }
4770
7d613ac6
SV		 4771 if (!ha->flags.nic_core_reset_hdlr_active) {
4772 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4773 qla83xx_idc_lock(base_vha, 0);
4774 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4775 &dev_state);
4776 qla83xx_idc_unlock(base_vha, 0);
4777 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4778 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4779 "Nic Core f/w is alive.\n");
4780 return;
4781 }
4782 }
4783
4784 ha->flags.nic_core_reset_hdlr_active = 1;
4785 if (qla83xx_nic_core_reset(base_vha)) {
4786 /* NIC Core reset failed. */
4787 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4788 "NIC Core reset failed.\n");
4789 }
4790 ha->flags.nic_core_reset_hdlr_active = 0;
4791 }
4792}
4793
4794/* Work: Handle 8200 IDC aens */
4795void
4796qla83xx_service_idc_aen(struct work_struct *work)
4797{
4798 struct qla_hw_data *ha =
4799 container_of(work, struct qla_hw_data, idc_aen);
4800 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4801 uint32_t dev_state, idc_control;
4802
4803 qla83xx_idc_lock(base_vha, 0);
4804 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4805 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4806 qla83xx_idc_unlock(base_vha, 0);
4807 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4808 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4809 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4810 "Application requested NIC Core Reset.\n");
4811 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4812 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4813 QLA_SUCCESS) {
4814 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4815 "Other protocol driver requested NIC Core Reset.\n");
4816 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4817 }
4818 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4819 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4820 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4821 }
4822}
4823
4824static void
4825qla83xx_wait_logic(void)
4826{
4827 int i;
4828
4829 /* Yield CPU */
4830 if (!in_interrupt()) {
4831 /*
4832 * Wait about 200ms before retrying again.
4833 * This controls the number of retries for single
4834 * lock operation.
4835 */
4836 msleep(100);
4837 schedule();
4838 } else {
4839 for (i = 0; i < 20; i++)
4840 cpu_relax(); /* This a nop instr on i386 */
4841 }
4842}
4843
fa492630 4844static int
7d613ac6
SV		 4845qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4846{
4847 int rval;
4848 uint32_t data;
4849 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4850 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4851 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4852 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4853 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4854
4855 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4856 if (rval)
4857 return rval;
4858
4859 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4860 return QLA_SUCCESS;
4861 } else {
4862 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4863 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4864 data);
4865 if (rval)
4866 return rval;
4867
4868 msleep(200);
4869
4870 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4871 &data);
4872 if (rval)
4873 return rval;
4874
4875 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4876 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4877 ~(idc_lck_rcvry_stage_mask));
4878 rval = qla83xx_wr_reg(base_vha,
4879 QLA83XX_IDC_LOCK_RECOVERY, data);
4880 if (rval)
4881 return rval;
4882
4883 /* Forcefully perform IDC UnLock */
4884 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4885 &data);
4886 if (rval)
4887 return rval;
4888 /* Clear lock-id by setting 0xff */
4889 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4890 0xff);
4891 if (rval)
4892 return rval;
4893 /* Clear lock-recovery by setting 0x0 */
4894 rval = qla83xx_wr_reg(base_vha,
4895 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4896 if (rval)
4897 return rval;
4898 } else
4899 return QLA_SUCCESS;
4900 }
4901
4902 return rval;
4903}
4904
fa492630 4905static int
7d613ac6
SV		 4906qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4907{
4908 int rval = QLA_SUCCESS;
4909 uint32_t o_drv_lockid, n_drv_lockid;
4910 unsigned long lock_recovery_timeout;
4911
4912 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4913retry_lockid:
4914 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4915 if (rval)
4916 goto exit;
4917
4918 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4919 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4920 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4921 return QLA_SUCCESS;
4922 else
4923 return QLA_FUNCTION_FAILED;
4924 }
4925
4926 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4927 if (rval)
4928 goto exit;
4929
4930 if (o_drv_lockid == n_drv_lockid) {
4931 qla83xx_wait_logic();
4932 goto retry_lockid;
4933 } else
4934 return QLA_SUCCESS;
4935
4936exit:
4937 return rval;
4938}
4939
4940void
4941qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4942{
4943 uint16_t options = (requester_id << 15) | BIT_6;
4944 uint32_t data;
6c315553 4945 uint32_t lock_owner;
7d613ac6
SV		 4946 struct qla_hw_data *ha = base_vha->hw;
4947
4948 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4949retry_lock:
4950 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4951 == QLA_SUCCESS) {
4952 if (data) {
4953 /* Setting lock-id to our function-number */
4954 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4955 ha->portnum);
4956 } else {
6c315553
SK		 4957 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4958 &lock_owner);
7d613ac6 4959 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4960 "Failed to acquire IDC lock, acquired by %d, "
4961 "retrying...\n", lock_owner);
7d613ac6
SV		 4962
4963 /* Retry/Perform IDC-Lock recovery */
4964 if (qla83xx_idc_lock_recovery(base_vha)
4965 == QLA_SUCCESS) {
4966 qla83xx_wait_logic();
4967 goto retry_lock;
4968 } else
4969 ql_log(ql_log_warn, base_vha, 0xb075,
4970 "IDC Lock recovery FAILED.\n");
4971 }
4972
4973 }
4974
4975 return;
4976
4977 /* XXX: IDC-lock implementation using access-control mbx */
4978retry_lock2:
4979 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4980 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4981 "Failed to acquire IDC lock. retrying...\n");
4982 /* Retry/Perform IDC-Lock recovery */
4983 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4984 qla83xx_wait_logic();
4985 goto retry_lock2;
4986 } else
4987 ql_log(ql_log_warn, base_vha, 0xb076,
4988 "IDC Lock recovery FAILED.\n");
4989 }
4990
4991 return;
4992}
4993
4994void
4995qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4996{
5897cb2f
BVA		 4997#if 0
4998 uint16_t options = (requester_id << 15) | BIT_7;
4999#endif
5000 uint16_t retry;
7d613ac6
SV		 5001 uint32_t data;
5002 struct qla_hw_data *ha = base_vha->hw;
5003
5004 /* IDC-unlock implementation using driver-unlock/lock-id
5005 * remote registers
5006 */
5007 retry = 0;
5008retry_unlock:
5009 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5010 == QLA_SUCCESS) {
5011 if (data == ha->portnum) {
5012 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5013 /* Clearing lock-id by setting 0xff */
5014 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5015 } else if (retry < 10) {
5016 /* SV: XXX: IDC unlock retrying needed here? */
5017
5018 /* Retry for IDC-unlock */
5019 qla83xx_wait_logic();
5020 retry++;
5021 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5022 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5023 goto retry_unlock;
5024 }
5025 } else if (retry < 10) {
5026 /* Retry for IDC-unlock */
5027 qla83xx_wait_logic();
5028 retry++;
5029 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5030 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5031 goto retry_unlock;
5032 }
5033
5034 return;
5035
5897cb2f 5036#if 0
7d613ac6
SV		 5037 /* XXX: IDC-unlock implementation using access-control mbx */
5038 retry = 0;
5039retry_unlock2:
5040 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5041 if (retry < 10) {
5042 /* Retry for IDC-unlock */
5043 qla83xx_wait_logic();
5044 retry++;
5045 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5046 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5047 goto retry_unlock2;
5048 }
5049 }
5050
5051 return;
5897cb2f 5052#endif
7d613ac6
SV		 5053}
5054
5055int
5056__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5057{
5058 int rval = QLA_SUCCESS;
5059 struct qla_hw_data *ha = vha->hw;
5060 uint32_t drv_presence;
5061
5062 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5063 if (rval == QLA_SUCCESS) {
5064 drv_presence |= (1 << ha->portnum);
5065 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5066 drv_presence);
5067 }
5068
5069 return rval;
5070}
5071
5072int
5073qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5074{
5075 int rval = QLA_SUCCESS;
5076
5077 qla83xx_idc_lock(vha, 0);
5078 rval = __qla83xx_set_drv_presence(vha);
5079 qla83xx_idc_unlock(vha, 0);
5080
5081 return rval;
5082}
5083
5084int
5085__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5086{
5087 int rval = QLA_SUCCESS;
5088 struct qla_hw_data *ha = vha->hw;
5089 uint32_t drv_presence;
5090
5091 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5092 if (rval == QLA_SUCCESS) {
5093 drv_presence &= ~(1 << ha->portnum);
5094 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5095 drv_presence);
5096 }
5097
5098 return rval;
5099}
5100
5101int
5102qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5103{
5104 int rval = QLA_SUCCESS;
5105
5106 qla83xx_idc_lock(vha, 0);
5107 rval = __qla83xx_clear_drv_presence(vha);
5108 qla83xx_idc_unlock(vha, 0);
5109
5110 return rval;
5111}
5112
fa492630 5113static void
7d613ac6
SV		 5114qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5115{
5116 struct qla_hw_data *ha = vha->hw;
5117 uint32_t drv_ack, drv_presence;
5118 unsigned long ack_timeout;
5119
5120 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5121 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5122 while (1) {
5123 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5124 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5125 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5126 break;
5127
5128 if (time_after_eq(jiffies, ack_timeout)) {
5129 ql_log(ql_log_warn, vha, 0xb067,
5130 "RESET ACK TIMEOUT! drv_presence=0x%x "
5131 "drv_ack=0x%x\n", drv_presence, drv_ack);
5132 /*
5133 * The function(s) which did not ack in time are forced
5134 * to withdraw any further participation in the IDC
5135 * reset.
5136 */
5137 if (drv_ack != drv_presence)
5138 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5139 drv_ack);
5140 break;
5141 }
5142
5143 qla83xx_idc_unlock(vha, 0);
5144 msleep(1000);
5145 qla83xx_idc_lock(vha, 0);
5146 }
5147
5148 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5149 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5150}
5151
fa492630 5152static int
7d613ac6
SV		 5153qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5154{
5155 int rval = QLA_SUCCESS;
5156 uint32_t idc_control;
5157
5158 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5159 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5160
5161 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5162 __qla83xx_get_idc_control(vha, &idc_control);
5163 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5164 __qla83xx_set_idc_control(vha, 0);
5165
5166 qla83xx_idc_unlock(vha, 0);
5167 rval = qla83xx_restart_nic_firmware(vha);
5168 qla83xx_idc_lock(vha, 0);
5169
5170 if (rval != QLA_SUCCESS) {
5171 ql_log(ql_log_fatal, vha, 0xb06a,
5172 "Failed to restart NIC f/w.\n");
5173 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5174 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5175 } else {
5176 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5177 "Success in restarting nic f/w.\n");
5178 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5179 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5180 }
5181
5182 return rval;
5183}
5184
5185/* Assumes idc_lock always held on entry */
5186int
5187qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5188{
5189 struct qla_hw_data *ha = base_vha->hw;
5190 int rval = QLA_SUCCESS;
5191 unsigned long dev_init_timeout;
5192 uint32_t dev_state;
5193
5194 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5195 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5196
5197 while (1) {
5198
5199 if (time_after_eq(jiffies, dev_init_timeout)) {
5200 ql_log(ql_log_warn, base_vha, 0xb06e,
5201 "Initialization TIMEOUT!\n");
5202 /* Init timeout. Disable further NIC Core
5203 * communication.
5204 */
5205 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5206 QLA8XXX_DEV_FAILED);
5207 ql_log(ql_log_info, base_vha, 0xb06f,
5208 "HW State: FAILED.\n");
5209 }
5210
5211 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5212 switch (dev_state) {
5213 case QLA8XXX_DEV_READY:
5214 if (ha->flags.nic_core_reset_owner)
5215 qla83xx_idc_audit(base_vha,
5216 IDC_AUDIT_COMPLETION);
5217 ha->flags.nic_core_reset_owner = 0;
5218 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5219 "Reset_owner reset by 0x%x.\n",
5220 ha->portnum);
5221 goto exit;
5222 case QLA8XXX_DEV_COLD:
5223 if (ha->flags.nic_core_reset_owner)
5224 rval = qla83xx_device_bootstrap(base_vha);
5225 else {
5226 /* Wait for AEN to change device-state */
5227 qla83xx_idc_unlock(base_vha, 0);
5228 msleep(1000);
5229 qla83xx_idc_lock(base_vha, 0);
5230 }
5231 break;
5232 case QLA8XXX_DEV_INITIALIZING:
5233 /* Wait for AEN to change device-state */
5234 qla83xx_idc_unlock(base_vha, 0);
5235 msleep(1000);
5236 qla83xx_idc_lock(base_vha, 0);
5237 break;
5238 case QLA8XXX_DEV_NEED_RESET:
5239 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5240 qla83xx_need_reset_handler(base_vha);
5241 else {
5242 /* Wait for AEN to change device-state */
5243 qla83xx_idc_unlock(base_vha, 0);
5244 msleep(1000);
5245 qla83xx_idc_lock(base_vha, 0);
5246 }
5247 /* reset timeout value after need reset handler */
5248 dev_init_timeout = jiffies +
5249 (ha->fcoe_dev_init_timeout * HZ);
5250 break;
5251 case QLA8XXX_DEV_NEED_QUIESCENT:
5252 /* XXX: DEBUG for now */
5253 qla83xx_idc_unlock(base_vha, 0);
5254 msleep(1000);
5255 qla83xx_idc_lock(base_vha, 0);
5256 break;
5257 case QLA8XXX_DEV_QUIESCENT:
5258 /* XXX: DEBUG for now */
5259 if (ha->flags.quiesce_owner)
5260 goto exit;
5261
5262 qla83xx_idc_unlock(base_vha, 0);
5263 msleep(1000);
5264 qla83xx_idc_lock(base_vha, 0);
5265 dev_init_timeout = jiffies +
5266 (ha->fcoe_dev_init_timeout * HZ);
5267 break;
5268 case QLA8XXX_DEV_FAILED:
5269 if (ha->flags.nic_core_reset_owner)
5270 qla83xx_idc_audit(base_vha,
5271 IDC_AUDIT_COMPLETION);
5272 ha->flags.nic_core_reset_owner = 0;
5273 __qla83xx_clear_drv_presence(base_vha);
5274 qla83xx_idc_unlock(base_vha, 0);
5275 qla8xxx_dev_failed_handler(base_vha);
5276 rval = QLA_FUNCTION_FAILED;
5277 qla83xx_idc_lock(base_vha, 0);
5278 goto exit;
5279 case QLA8XXX_BAD_VALUE:
5280 qla83xx_idc_unlock(base_vha, 0);
5281 msleep(1000);
5282 qla83xx_idc_lock(base_vha, 0);
5283 break;
5284 default:
5285 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5286 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5287 qla83xx_idc_unlock(base_vha, 0);
5288 qla8xxx_dev_failed_handler(base_vha);
5289 rval = QLA_FUNCTION_FAILED;
5290 qla83xx_idc_lock(base_vha, 0);
5291 goto exit;
5292 }
5293 }
5294
5295exit:
5296 return rval;
5297}
5298
f3ddac19
CD		 5299void
5300qla2x00_disable_board_on_pci_error(struct work_struct *work)
5301{
5302 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5303 board_disable);
5304 struct pci_dev *pdev = ha->pdev;
5305 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5306
726b8548
QT		 5307 /*
5308 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5309 * where it was set first.
5310 */
5311 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5312 return;
5313
f3ddac19
CD		 5314 ql_log(ql_log_warn, base_vha, 0x015b,
5315 "Disabling adapter.\n");
5316
726b8548
QT		 5317 qla2x00_wait_for_sess_deletion(base_vha);
5318
f3ddac19
CD		 5319 set_bit(UNLOADING, &base_vha->dpc_flags);
5320
5321 qla2x00_delete_all_vps(ha, base_vha);
5322
5323 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5324
5325 qla2x00_dfs_remove(base_vha);
5326
5327 qla84xx_put_chip(base_vha);
5328
5329 if (base_vha->timer_active)
5330 qla2x00_stop_timer(base_vha);
5331
5332 base_vha->flags.online = 0;
5333
5334 qla2x00_destroy_deferred_work(ha);
5335
5336 /*
5337 * Do not try to stop beacon blink as it will issue a mailbox
5338 * command.
5339 */
5340 qla2x00_free_sysfs_attr(base_vha, false);
5341
5342 fc_remove_host(base_vha->host);
5343
5344 scsi_remove_host(base_vha->host);
5345
5346 base_vha->flags.init_done = 0;
5347 qla25xx_delete_queues(base_vha);
f3ddac19 5348 qla2x00_free_fcports(base_vha);
093df737 5349 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5350 qla2x00_mem_free(ha);
5351 qla82xx_md_free(base_vha);
5352 qla2x00_free_queues(ha);
5353
f3ddac19
CD		 5354 qla2x00_unmap_iobases(ha);
5355
5356 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5357 pci_disable_pcie_error_reporting(pdev);
5358 pci_disable_device(pdev);
f3ddac19 5359
beb9e315
JL		 5360 /*
5361 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5362 */
f3ddac19
CD		 5363}
5364
1da177e4
LT		 5365/**************************************************************************
5366* qla2x00_do_dpc
5367* This kernel thread is a task that is schedule by the interrupt handler
5368* to perform the background processing for interrupts.
5369*
5370* Notes:
5371* This task always run in the context of a kernel thread. It
5372* is kick-off by the driver's detect code and starts up
5373* up one per adapter. It immediately goes to sleep and waits for
5374* some fibre event. When either the interrupt handler or
5375* the timer routine detects a event it will one of the task
5376* bits then wake us up.
5377**************************************************************************/
5378static int
5379qla2x00_do_dpc(void *data)
5380{
e315cd28
AC		 5381 scsi_qla_host_t *base_vha;
5382 struct qla_hw_data *ha;
d7459527
MH		 5383 uint32_t online;
5384 struct qla_qpair *qpair;
1da177e4 5385
e315cd28
AC		 5386 ha = (struct qla_hw_data *)data;
5387 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5388
8698a745 5389 set_user_nice(current, MIN_NICE);
1da177e4 5390
563585ec 5391 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5392 while (!kthread_should_stop()) {
7c3df132
SK		 5393 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5394 "DPC handler sleeping.\n");
1da177e4 5395
39a11240 5396 schedule();
1da177e4 5397
c142caf0
AV		 5398 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5399 goto end_loop;
1da177e4 5400
85880801 5401 if (ha->flags.eeh_busy) {
7c3df132
SK		 5402 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5403 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5404 goto end_loop;
85880801
AV		 5405 }
5406
1da177e4
LT		 5407 ha->dpc_active = 1;
5408
5f28d2d7
SK		 5409 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5410 "DPC handler waking up, dpc_flags=0x%lx.\n",
5411 base_vha->dpc_flags);
1da177e4 5412
a29b3dd7
JC		 5413 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5414 break;
5415
e315cd28 5416 qla2x00_do_work(base_vha);
0971de7f 5417
7ec0effd
AD		 5418 if (IS_P3P_TYPE(ha)) {
5419 if (IS_QLA8044(ha)) {
5420 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5421 &base_vha->dpc_flags)) {
5422 qla8044_idc_lock(ha);
5423 qla8044_wr_direct(base_vha,
5424 QLA8044_CRB_DEV_STATE_INDEX,
5425 QLA8XXX_DEV_FAILED);
5426 qla8044_idc_unlock(ha);
5427 ql_log(ql_log_info, base_vha, 0x4004,
5428 "HW State: FAILED.\n");
5429 qla8044_device_state_handler(base_vha);
5430 continue;
5431 }
5432
5433 } else {
5434 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5435 &base_vha->dpc_flags)) {
5436 qla82xx_idc_lock(ha);
5437 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5438 QLA8XXX_DEV_FAILED);
5439 qla82xx_idc_unlock(ha);
5440 ql_log(ql_log_info, base_vha, 0x0151,
5441 "HW State: FAILED.\n");
5442 qla82xx_device_state_handler(base_vha);
5443 continue;
5444 }
a9083016
GM		 5445 }
5446
5447 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5448 &base_vha->dpc_flags)) {
5449
7c3df132
SK		 5450 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5451 "FCoE context reset scheduled.\n");
a9083016
GM		 5452 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5453 &base_vha->dpc_flags))) {
5454 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5455 /* FCoE-ctx reset failed.
5456 * Escalate to chip-reset
5457 */
5458 set_bit(ISP_ABORT_NEEDED,
5459 &base_vha->dpc_flags);
5460 }
5461 clear_bit(ABORT_ISP_ACTIVE,
5462 &base_vha->dpc_flags);
5463 }
5464
7c3df132
SK		 5465 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5466 "FCoE context reset end.\n");
a9083016 5467 }
8ae6d9c7
GM		 5468 } else if (IS_QLAFX00(ha)) {
5469 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5470 &base_vha->dpc_flags)) {
5471 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5472 "Firmware Reset Recovery\n");
5473 if (qlafx00_reset_initialize(base_vha)) {
5474 /* Failed. Abort isp later. */
5475 if (!test_bit(UNLOADING,
f92f82d6 5476 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5477 set_bit(ISP_UNRECOVERABLE,
5478 &base_vha->dpc_flags);
5479 ql_dbg(ql_dbg_dpc, base_vha,
5480 0x4021,
5481 "Reset Recovery Failed\n");
f92f82d6 5482 }
8ae6d9c7
GM		 5483 }
5484 }
5485
5486 if (test_and_clear_bit(FX00_TARGET_SCAN,
5487 &base_vha->dpc_flags)) {
5488 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5489 "ISPFx00 Target Scan scheduled\n");
5490 if (qlafx00_rescan_isp(base_vha)) {
5491 if (!test_bit(UNLOADING,
5492 &base_vha->dpc_flags))
5493 set_bit(ISP_UNRECOVERABLE,
5494 &base_vha->dpc_flags);
5495 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5496 "ISPFx00 Target Scan Failed\n");
5497 }
5498 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5499 "ISPFx00 Target Scan End\n");
5500 }
e8f5e95d
AB		 5501 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5502 &base_vha->dpc_flags)) {
5503 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5504 "ISPFx00 Host Info resend scheduled\n");
5505 qlafx00_fx_disc(base_vha,
5506 &base_vha->hw->mr.fcport,
5507 FXDISC_REG_HOST_INFO);
5508 }
a9083016
GM		 5509 }
5510
e315cd28
AC		 5511 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5512 &base_vha->dpc_flags)) {
1da177e4 5513
7c3df132
SK		 5514 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5515 "ISP abort scheduled.\n");
1da177e4 5516 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5517 &base_vha->dpc_flags))) {
1da177e4 5518
a9083016 5519 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5520 /* failed. retry later */
5521 set_bit(ISP_ABORT_NEEDED,
e315cd28 5522 &base_vha->dpc_flags);
99363ef8 5523 }
e315cd28
AC		 5524 clear_bit(ABORT_ISP_ACTIVE,
5525 &base_vha->dpc_flags);
99363ef8
SJ		 5526 }
5527
7c3df132
SK		 5528 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5529 "ISP abort end.\n");
1da177e4
LT		 5530 }
5531
a394aac8
DJ		 5532 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5533 &base_vha->dpc_flags)) {
e315cd28 5534 qla2x00_update_fcports(base_vha);
c9c5ced9 5535 }
d97994dc 5536
8ae6d9c7
GM		 5537 if (IS_QLAFX00(ha))
5538 goto loop_resync_check;
5539
579d12b5 5540 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5541 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5542 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5543 if (IS_P3P_TYPE(ha)) {
5544 if (IS_QLA82XX(ha))
5545 qla82xx_device_state_handler(base_vha);
5546 if (IS_QLA8044(ha))
5547 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5548 clear_bit(ISP_QUIESCE_NEEDED,
5549 &base_vha->dpc_flags);
5550 if (!ha->flags.quiesce_owner) {
5551 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5552 if (IS_QLA82XX(ha)) {
5553 qla82xx_idc_lock(ha);
5554 qla82xx_clear_qsnt_ready(
5555 base_vha);
5556 qla82xx_idc_unlock(ha);
5557 } else if (IS_QLA8044(ha)) {
5558 qla8044_idc_lock(ha);
5559 qla8044_clear_qsnt_ready(
5560 base_vha);
5561 qla8044_idc_unlock(ha);
5562 }
8fcd6b8b
CD		 5563 }
5564 } else {
5565 clear_bit(ISP_QUIESCE_NEEDED,
5566 &base_vha->dpc_flags);
5567 qla2x00_quiesce_io(base_vha);
579d12b5 5568 }
7c3df132
SK		 5569 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5570 "Quiescence mode end.\n");
579d12b5
SK		 5571 }
5572
e315cd28 5573 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5574 &base_vha->dpc_flags) &&
e315cd28 5575 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5576
7c3df132
SK		 5577 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5578 "Reset marker scheduled.\n");
e315cd28
AC		 5579 qla2x00_rst_aen(base_vha);
5580 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5581 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5582 "Reset marker end.\n");
1da177e4
LT		 5583 }
5584
5585 /* Retry each device up to login retry count */
e315cd28
AC		 5586 if ((test_and_clear_bit(RELOGIN_NEEDED,
5587 &base_vha->dpc_flags)) &&
5588 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5589 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5590
7c3df132
SK		 5591 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5592 "Relogin scheduled.\n");
e315cd28 5593 qla2x00_relogin(base_vha);
7c3df132
SK		 5594 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5595 "Relogin end.\n");
1da177e4 5596 }
8ae6d9c7 5597loop_resync_check:
e315cd28 5598 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5599 &base_vha->dpc_flags)) {
1da177e4 5600
7c3df132
SK		 5601 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5602 "Loop resync scheduled.\n");
1da177e4
LT		 5603
5604 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5605 &base_vha->dpc_flags))) {
1da177e4 5606
52c82823 5607 qla2x00_loop_resync(base_vha);
1da177e4 5608
e315cd28
AC		 5609 clear_bit(LOOP_RESYNC_ACTIVE,
5610 &base_vha->dpc_flags);
1da177e4
LT		 5611 }
5612
7c3df132
SK		 5613 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5614 "Loop resync end.\n");
1da177e4
LT		 5615 }
5616
8ae6d9c7
GM		 5617 if (IS_QLAFX00(ha))
5618 goto intr_on_check;
5619
e315cd28
AC		 5620 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5621 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5622 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5623 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5624 }
5625
8ae6d9c7 5626intr_on_check:
1da177e4 5627 if (!ha->interrupts_on)
fd34f556 5628 ha->isp_ops->enable_intrs(ha);
1da177e4 5629
e315cd28 5630 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5631 &base_vha->dpc_flags)) {
5632 if (ha->beacon_blink_led == 1)
5633 ha->isp_ops->beacon_blink(base_vha);
5634 }
f6df144c 5635
d7459527
MH		 5636 /* qpair online check */
5637 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5638 &base_vha->dpc_flags)) {
5639 if (ha->flags.eeh_busy ||
5640 ha->flags.pci_channel_io_perm_failure)
5641 online = 0;
5642 else
5643 online = 1;
5644
5645 mutex_lock(&ha->mq_lock);
5646 list_for_each_entry(qpair, &base_vha->qp_list,
5647 qp_list_elem)
5648 qpair->online = online;
5649 mutex_unlock(&ha->mq_lock);
5650 }
5651
8ae6d9c7
GM		 5652 if (!IS_QLAFX00(ha))
5653 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5654
1da177e4 5655 ha->dpc_active = 0;
c142caf0 5656end_loop:
563585ec 5657 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5658 } /* End of while(1) */
563585ec 5659 __set_current_state(TASK_RUNNING);
1da177e4 5660
7c3df132
SK		 5661 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5662 "DPC handler exiting.\n");
1da177e4
LT		 5663
5664 /*
5665 * Make sure that nobody tries to wake us up again.
5666 */
1da177e4
LT		 5667 ha->dpc_active = 0;
5668
ac280b67
AV		 5669 /* Cleanup any residual CTX SRBs. */
5670 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5671
39a11240
CH		 5672 return 0;
5673}
5674
5675void
e315cd28 5676qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5677{
e315cd28 5678 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5679 struct task_struct *t = ha->dpc_thread;
5680
e315cd28 5681 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5682 wake_up_process(t);
1da177e4
LT		 5683}
5684
1da177e4
LT		 5685/*
5686* qla2x00_rst_aen
5687* Processes asynchronous reset.
5688*
5689* Input:
5690* ha = adapter block pointer.
5691*/
5692static void
e315cd28 5693qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5694{
e315cd28
AC		 5695 if (vha->flags.online && !vha->flags.reset_active &&
5696 !atomic_read(&vha->loop_down_timer) &&
5697 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5698 do {
e315cd28 5699 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5700
5701 /*
5702 * Issue marker command only when we are going to start
5703 * the I/O.
5704 */
e315cd28
AC		 5705 vha->marker_needed = 1;
5706 } while (!atomic_read(&vha->loop_down_timer) &&
5707 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5708 }
5709}
5710
1da177e4
LT		 5711/**************************************************************************
5712* qla2x00_timer
5713*
5714* Description:
5715* One second timer
5716*
5717* Context: Interrupt
5718***************************************************************************/
2c3dfe3f 5719void
e315cd28 5720qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5721{
1da177e4 5722 unsigned long cpu_flags = 0;
1da177e4
LT		 5723 int start_dpc = 0;
5724 int index;
5725 srb_t *sp;
85880801 5726 uint16_t w;
e315cd28 5727 struct qla_hw_data *ha = vha->hw;
73208dfd 5728 struct req_que *req;
85880801 5729
a5b36321 5730 if (ha->flags.eeh_busy) {
7c3df132
SK		 5731 ql_dbg(ql_dbg_timer, vha, 0x6000,
5732 "EEH = %d, restarting timer.\n",
5733 ha->flags.eeh_busy);
a5b36321
LC		 5734 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5735 return;
5736 }
5737
f3ddac19
CD		 5738 /*
5739 * Hardware read to raise pending EEH errors during mailbox waits. If
5740 * the read returns -1 then disable the board.
5741 */
5742 if (!pci_channel_offline(ha->pdev)) {
85880801 5743 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5744 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5745 }
1da177e4 5746
cefcaba6 5747 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5748 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5749 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5750 start_dpc++;
7ec0effd
AD		 5751 if (IS_QLA82XX(ha))
5752 qla82xx_watchdog(vha);
5753 else if (IS_QLA8044(ha))
5754 qla8044_watchdog(vha);
579d12b5
SK		 5755 }
5756
8ae6d9c7
GM		 5757 if (!vha->vp_idx && IS_QLAFX00(ha))
5758 qlafx00_timer_routine(vha);
5759
1da177e4 5760 /* Loop down handler. */
e315cd28 5761 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5762 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5763 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5764 && vha->flags.online) {
1da177e4 5765
e315cd28
AC		 5766 if (atomic_read(&vha->loop_down_timer) ==
5767 vha->loop_down_abort_time) {
1da177e4 5768
7c3df132
SK		 5769 ql_log(ql_log_info, vha, 0x6008,
5770 "Loop down - aborting the queues before time expires.\n");
1da177e4 5771
e315cd28
AC		 5772 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5773 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5774
f08b7251
AV		 5775 /*
5776 * Schedule an ISP abort to return any FCP2-device
5777 * commands.
5778 */
2c3dfe3f 5779 /* NPIV - scan physical port only */
e315cd28 5780 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5781 spin_lock_irqsave(&ha->hardware_lock,
5782 cpu_flags);
73208dfd 5783 req = ha->req_q_map[0];
2c3dfe3f 5784 for (index = 1;
8d93f550 5785 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5786 index++) {
5787 fc_port_t *sfcp;
5788
e315cd28 5789 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5790 if (!sp)
5791 continue;
9ba56b95 5792 if (sp->type != SRB_SCSI_CMD)
cf53b069 5793 continue;
2c3dfe3f 5794 sfcp = sp->fcport;
f08b7251 5795 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5796 continue;
bdf79621 5797
8f7daead
GM		 5798 if (IS_QLA82XX(ha))
5799 set_bit(FCOE_CTX_RESET_NEEDED,
5800 &vha->dpc_flags);
5801 else
5802 set_bit(ISP_ABORT_NEEDED,
e315cd28 5803 &vha->dpc_flags);
2c3dfe3f
SJ		 5804 break;
5805 }
5806 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5807 cpu_flags);
1da177e4 5808 }
1da177e4
LT		 5809 start_dpc++;
5810 }
5811
5812 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5813 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5814 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5815 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5816 "Loop down - aborting ISP.\n");
5817
8f7daead
GM		 5818 if (IS_QLA82XX(ha))
5819 set_bit(FCOE_CTX_RESET_NEEDED,
5820 &vha->dpc_flags);
5821 else
5822 set_bit(ISP_ABORT_NEEDED,
5823 &vha->dpc_flags);
1da177e4
LT		 5824 }
5825 }
7c3df132
SK		 5826 ql_dbg(ql_dbg_timer, vha, 0x600a,
5827 "Loop down - seconds remaining %d.\n",
5828 atomic_read(&vha->loop_down_timer));
1da177e4 5829 }
cefcaba6
SK		 5830 /* Check if beacon LED needs to be blinked for physical host only */
5831 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5832 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5833 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5834 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5835 start_dpc++;
5836 }
f6df144c
AV		 5837 }
5838
550bf57d 5839 /* Process any deferred work. */
e315cd28 5840 if (!list_empty(&vha->work_list))
550bf57d
AV		 5841 start_dpc++;
5842
1da177e4 5843 /* Schedule the DPC routine if needed */
e315cd28
AC		 5844 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5845 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5846 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5847 start_dpc ||
e315cd28
AC		 5848 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5849 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5850 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5851 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5852 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5853 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5854 ql_dbg(ql_dbg_timer, vha, 0x600b,
5855 "isp_abort_needed=%d loop_resync_needed=%d "
5856 "fcport_update_needed=%d start_dpc=%d "
5857 "reset_marker_needed=%d",
5858 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5859 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5860 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5861 start_dpc,
5862 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5863 ql_dbg(ql_dbg_timer, vha, 0x600c,
5864 "beacon_blink_needed=%d isp_unrecoverable=%d "
5865 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5866 "relogin_needed=%d.\n",
7c3df132
SK		 5867 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5868 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5869 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5870 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5871 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5872 qla2xxx_wake_dpc(vha);
7c3df132 5873 }
1da177e4 5874
e315cd28 5875 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5876}
5877
5433383e
AV		 5878/* Firmware interface routines. */
5879
f73cb695 5880#define FW_BLOBS 11
5433383e
AV		 5881#define FW_ISP21XX 0
5882#define FW_ISP22XX 1
5883#define FW_ISP2300 2
5884#define FW_ISP2322 3
48c02fde 5885#define FW_ISP24XX 4
c3a2f0df 5886#define FW_ISP25XX 5
3a03eb79 5887#define FW_ISP81XX 6
a9083016 5888#define FW_ISP82XX 7
6246b8a1
GM		 5889#define FW_ISP2031 8
5890#define FW_ISP8031 9
2c5bbbb2 5891#define FW_ISP27XX 10
5433383e 5892
bb8ee499
AV		 5893#define FW_FILE_ISP21XX "ql2100_fw.bin"
5894#define FW_FILE_ISP22XX "ql2200_fw.bin"
5895#define FW_FILE_ISP2300 "ql2300_fw.bin"
5896#define FW_FILE_ISP2322 "ql2322_fw.bin"
5897#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5898#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5899#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5900#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5901#define FW_FILE_ISP2031 "ql2600_fw.bin"
5902#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5903#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5904
bb8ee499 5905
e1e82b6f 5906static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5907
5908static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5909 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5910 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5911 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5912 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5913 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5914 { .name = FW_FILE_ISP25XX, },
3a03eb79 5915 { .name = FW_FILE_ISP81XX, },
a9083016 5916 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5917 { .name = FW_FILE_ISP2031, },
5918 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5919 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5920};
5921
5922struct fw_blob *
e315cd28 5923qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5924{
e315cd28 5925 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5926 struct fw_blob *blob;
5927
5433383e
AV		 5928 if (IS_QLA2100(ha)) {
5929 blob = &qla_fw_blobs[FW_ISP21XX];
5930 } else if (IS_QLA2200(ha)) {
5931 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5932 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5933 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5934 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5935 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5936 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5937 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5938 } else if (IS_QLA25XX(ha)) {
5939 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5940 } else if (IS_QLA81XX(ha)) {
5941 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5942 } else if (IS_QLA82XX(ha)) {
5943 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5944 } else if (IS_QLA2031(ha)) {
5945 blob = &qla_fw_blobs[FW_ISP2031];
5946 } else if (IS_QLA8031(ha)) {
5947 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5948 } else if (IS_QLA27XX(ha)) {
5949 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5950 } else {
5951 return NULL;
5433383e
AV		 5952 }
5953
e1e82b6f 5954 mutex_lock(&qla_fw_lock);
5433383e
AV		 5955 if (blob->fw)
5956 goto out;
5957
5958 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5959 ql_log(ql_log_warn, vha, 0x0063,
5960 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5961 blob->fw = NULL;
5962 blob = NULL;
5963 goto out;
5964 }
5965
5966out:
e1e82b6f 5967 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5968 return blob;
5969}
5970
5971static void
5972qla2x00_release_firmware(void)
5973{
5974 int idx;
5975
e1e82b6f 5976 mutex_lock(&qla_fw_lock);
5433383e 5977 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5978 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5979 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5980}
5981
14e660e6
SJ		 5982static pci_ers_result_t
5983qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5984{
85880801
AV		 5985 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5986 struct qla_hw_data *ha = vha->hw;
5987
7c3df132
SK		 5988 ql_dbg(ql_dbg_aer, vha, 0x9000,
5989 "PCI error detected, state %x.\n", state);
b9b12f73 5990
14e660e6
SJ		 5991 switch (state) {
5992 case pci_channel_io_normal:
85880801 5993 ha->flags.eeh_busy = 0;
d7459527
MH		 5994 if (ql2xmqsupport) {
5995 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5996 qla2xxx_wake_dpc(vha);
5997 }
14e660e6
SJ		 5998 return PCI_ERS_RESULT_CAN_RECOVER;
5999 case pci_channel_io_frozen:
85880801 6000 ha->flags.eeh_busy = 1;
a5b36321
LC		 6001 /* For ISP82XX complete any pending mailbox cmd */
6002 if (IS_QLA82XX(ha)) {
7190575f 6003 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6004 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6005 qla82xx_clear_pending_mbx(vha);
a5b36321 6006 }
90a86fc0 6007 qla2x00_free_irqs(vha);
14e660e6 6008 pci_disable_device(pdev);
bddd2d65
LC		 6009 /* Return back all IOs */
6010 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6011 if (ql2xmqsupport) {
6012 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6013 qla2xxx_wake_dpc(vha);
6014 }
14e660e6
SJ		 6015 return PCI_ERS_RESULT_NEED_RESET;
6016 case pci_channel_io_perm_failure:
85880801
AV		 6017 ha->flags.pci_channel_io_perm_failure = 1;
6018 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6019 if (ql2xmqsupport) {
6020 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6021 qla2xxx_wake_dpc(vha);
6022 }
14e660e6
SJ		 6023 return PCI_ERS_RESULT_DISCONNECT;
6024 }
6025 return PCI_ERS_RESULT_NEED_RESET;
6026}
6027
6028static pci_ers_result_t
6029qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6030{
6031 int risc_paused = 0;
6032 uint32_t stat;
6033 unsigned long flags;
e315cd28
AC		 6034 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6035 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6036 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6037 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6038
bcc5b6d3
SK		 6039 if (IS_QLA82XX(ha))
6040 return PCI_ERS_RESULT_RECOVERED;
6041
14e660e6
SJ		 6042 spin_lock_irqsave(&ha->hardware_lock, flags);
6043 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6044 stat = RD_REG_DWORD(&reg->hccr);
6045 if (stat & HCCR_RISC_PAUSE)
6046 risc_paused = 1;
6047 } else if (IS_QLA23XX(ha)) {
6048 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6049 if (stat & HSR_RISC_PAUSED)
6050 risc_paused = 1;
6051 } else if (IS_FWI2_CAPABLE(ha)) {
6052 stat = RD_REG_DWORD(&reg24->host_status);
6053 if (stat & HSRX_RISC_PAUSED)
6054 risc_paused = 1;
6055 }
6056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6057
6058 if (risc_paused) {
7c3df132
SK		 6059 ql_log(ql_log_info, base_vha, 0x9003,
6060 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6061 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6062
6063 return PCI_ERS_RESULT_NEED_RESET;
6064 } else
6065 return PCI_ERS_RESULT_RECOVERED;
6066}
6067
fa492630
SK		 6068static uint32_t
6069qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6070{
6071 uint32_t rval = QLA_FUNCTION_FAILED;
6072 uint32_t drv_active = 0;
6073 struct qla_hw_data *ha = base_vha->hw;
6074 int fn;
6075 struct pci_dev *other_pdev = NULL;
6076
7c3df132
SK		 6077 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6078 "Entered %s.\n", __func__);
a5b36321
LC		 6079
6080 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6081
6082 if (base_vha->flags.online) {
6083 /* Abort all outstanding commands,
6084 * so as to be requeued later */
6085 qla2x00_abort_isp_cleanup(base_vha);
6086 }
6087
6088
6089 fn = PCI_FUNC(ha->pdev->devfn);
6090 while (fn > 0) {
6091 fn--;
7c3df132
SK		 6092 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6093 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6094 other_pdev =
6095 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6096 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6097 fn));
6098
6099 if (!other_pdev)
6100 continue;
6101 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6102 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6103 "Found PCI func available and enable at 0x%x.\n",
6104 fn);
a5b36321
LC		 6105 pci_dev_put(other_pdev);
6106 break;
6107 }
6108 pci_dev_put(other_pdev);
6109 }
6110
6111 if (!fn) {
6112 /* Reset owner */
7c3df132
SK		 6113 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6114 "This devfn is reset owner = 0x%x.\n",
6115 ha->pdev->devfn);
a5b36321
LC		 6116 qla82xx_idc_lock(ha);
6117
6118 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6119 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6120
6121 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6122 QLA82XX_IDC_VERSION);
6123
6124 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6125 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6126 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6127
6128 qla82xx_idc_unlock(ha);
6129 /* Reset if device is not already reset
6130 * drv_active would be 0 if a reset has already been done
6131 */
6132 if (drv_active)
6133 rval = qla82xx_start_firmware(base_vha);
6134 else
6135 rval = QLA_SUCCESS;
6136 qla82xx_idc_lock(ha);
6137
6138 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6139 ql_log(ql_log_info, base_vha, 0x900b,
6140 "HW State: FAILED.\n");
a5b36321
LC		 6141 qla82xx_clear_drv_active(ha);
6142 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6143 QLA8XXX_DEV_FAILED);
a5b36321 6144 } else {
7c3df132
SK		 6145 ql_log(ql_log_info, base_vha, 0x900c,
6146 "HW State: READY.\n");
a5b36321 6147 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6148 QLA8XXX_DEV_READY);
a5b36321 6149 qla82xx_idc_unlock(ha);
7190575f 6150 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6151 rval = qla82xx_restart_isp(base_vha);
6152 qla82xx_idc_lock(ha);
6153 /* Clear driver state register */
6154 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6155 qla82xx_set_drv_active(base_vha);
6156 }
6157 qla82xx_idc_unlock(ha);
6158 } else {
7c3df132
SK		 6159 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6160 "This devfn is not reset owner = 0x%x.\n",
6161 ha->pdev->devfn);
a5b36321 6162 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6163 QLA8XXX_DEV_READY)) {
7190575f 6164 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6165 rval = qla82xx_restart_isp(base_vha);
6166 qla82xx_idc_lock(ha);
6167 qla82xx_set_drv_active(base_vha);
6168 qla82xx_idc_unlock(ha);
6169 }
6170 }
6171 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6172
6173 return rval;
6174}
6175
14e660e6
SJ		 6176static pci_ers_result_t
6177qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6178{
6179 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6180 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6181 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6182 struct rsp_que *rsp;
6183 int rc, retries = 10;
09483916 6184
7c3df132
SK		 6185 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6186 "Slot Reset.\n");
85880801 6187
90a86fc0
JC		 6188 /* Workaround: qla2xxx driver which access hardware earlier
6189 * needs error state to be pci_channel_io_online.
6190 * Otherwise mailbox command timesout.
6191 */
6192 pdev->error_state = pci_channel_io_normal;
6193
6194 pci_restore_state(pdev);
6195
8c1496bd
RL		 6196 /* pci_restore_state() clears the saved_state flag of the device
6197 * save restored state which resets saved_state flag
6198 */
6199 pci_save_state(pdev);
6200
09483916
BH		 6201 if (ha->mem_only)
6202 rc = pci_enable_device_mem(pdev);
6203 else
6204 rc = pci_enable_device(pdev);
14e660e6 6205
09483916 6206 if (rc) {
7c3df132 6207 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6208 "Can't re-enable PCI device after reset.\n");
a5b36321 6209 goto exit_slot_reset;
14e660e6 6210 }
14e660e6 6211
90a86fc0
JC		 6212 rsp = ha->rsp_q_map[0];
6213 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6214 goto exit_slot_reset;
90a86fc0 6215
e315cd28 6216 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6217 goto exit_slot_reset;
6218
6219 if (IS_QLA82XX(ha)) {
6220 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6221 ret = PCI_ERS_RESULT_RECOVERED;
6222 goto exit_slot_reset;
6223 } else
6224 goto exit_slot_reset;
6225 }
14e660e6 6226
90a86fc0
JC		 6227 while (ha->flags.mbox_busy && retries--)
6228 msleep(1000);
85880801 6229
e315cd28 6230 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6231 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6232 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6233 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6234
90a86fc0 6235
a5b36321 6236exit_slot_reset:
7c3df132
SK		 6237 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6238 "slot_reset return %x.\n", ret);
85880801 6239
14e660e6
SJ		 6240 return ret;
6241}
6242
6243static void
6244qla2xxx_pci_resume(struct pci_dev *pdev)
6245{
e315cd28
AC		 6246 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6247 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6248 int ret;
6249
7c3df132
SK		 6250 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6251 "pci_resume.\n");
85880801 6252
e315cd28 6253 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6254 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6255 ql_log(ql_log_fatal, base_vha, 0x9002,
6256 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6257 }
85880801 6258
3e46f031
LC		 6259 pci_cleanup_aer_uncorrect_error_status(pdev);
6260
85880801 6261 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6262}
6263
2d5a4c34
HM		 6264static void
6265qla83xx_disable_laser(scsi_qla_host_t *vha)
6266{
6267 uint32_t reg, data, fn;
6268 struct qla_hw_data *ha = vha->hw;
6269 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6270
6271 /* pci func #/port # */
6272 ql_dbg(ql_dbg_init, vha, 0x004b,
6273 "Disabling Laser for hba: %p\n", vha);
6274
6275 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6276 (BIT_15|BIT_14|BIT_13|BIT_12));
6277
6278 fn = (fn >> 12);
6279
6280 if (fn & 1)
6281 reg = PORT_1_2031;
6282 else
6283 reg = PORT_0_2031;
6284
6285 data = LASER_OFF_2031;
6286
6287 qla83xx_wr_reg(vha, reg, data);
6288}
6289
5601236b
MH		 6290static int qla2xxx_map_queues(struct Scsi_Host *shost)
6291{
6292 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6293
6294 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6295}
6296
a55b2d21 6297static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6298 .error_detected = qla2xxx_pci_error_detected,
6299 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6300 .slot_reset = qla2xxx_pci_slot_reset,
6301 .resume = qla2xxx_pci_resume,
6302};
6303
5433383e 6304static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6305 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6306 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6307 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6308 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6309 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6310 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6311 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6312 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6313 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6314 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6315 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6327 { 0 },
6328};
6329MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6330
fca29703 6331static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6332 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6333 .driver = {
6334 .owner = THIS_MODULE,
6335 },
fca29703 6336 .id_table = qla2xxx_pci_tbl,
7ee61397 6337 .probe = qla2x00_probe_one,
4c993f76 6338 .remove = qla2x00_remove_one,
e30d1756 6339 .shutdown = qla2x00_shutdown,
14e660e6 6340 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6341};
6342
75ef9de1 6343static const struct file_operations apidev_fops = {
6a03b4cd 6344 .owner = THIS_MODULE,
6038f373 6345 .llseek = noop_llseek,
6a03b4cd
HZ		 6346};
6347
1da177e4
LT		 6348/**
6349 * qla2x00_module_init - Module initialization.
6350 **/
6351static int __init
6352qla2x00_module_init(void)
6353{
fca29703
AV		 6354 int ret = 0;
6355
1da177e4 6356 /* Allocate cache for SRBs. */
354d6b21 6357 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6358 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6359 if (srb_cachep == NULL) {
7c3df132
SK		 6360 ql_log(ql_log_fatal, NULL, 0x0001,
6361 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6362 return -ENOMEM;
6363 }
6364
2d70c103
NB		 6365 /* Initialize target kmem_cache and mem_pools */
6366 ret = qlt_init();
6367 if (ret < 0) {
6368 kmem_cache_destroy(srb_cachep);
6369 return ret;
6370 } else if (ret > 0) {
6371 /*
6372 * If initiator mode is explictly disabled by qlt_init(),
6373 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6374 * performing scsi_scan_target() during LOOP UP event.
6375 */
6376 qla2xxx_transport_functions.disable_target_scan = 1;
6377 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6378 }
6379
1da177e4
LT		 6380 /* Derive version string. */
6381 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6382 if (ql2xextended_error_logging)
0181944f
AV		 6383 strcat(qla2x00_version_str, "-debug");
6384
1c97a12a
AV		 6385 qla2xxx_transport_template =
6386 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6387 if (!qla2xxx_transport_template) {
6388 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6389 ql_log(ql_log_fatal, NULL, 0x0002,
6390 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6391 qlt_exit();
1da177e4 6392 return -ENODEV;
2c3dfe3f 6393 }
6a03b4cd
HZ		 6394
6395 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6396 if (apidev_major < 0) {
7c3df132
SK		 6397 ql_log(ql_log_fatal, NULL, 0x0003,
6398 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6399 }
6400
2c3dfe3f
SJ		 6401 qla2xxx_transport_vport_template =
6402 fc_attach_transport(&qla2xxx_transport_vport_functions);
6403 if (!qla2xxx_transport_vport_template) {
6404 kmem_cache_destroy(srb_cachep);
2d70c103 6405 qlt_exit();
2c3dfe3f 6406 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6407 ql_log(ql_log_fatal, NULL, 0x0004,
6408 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6409 return -ENODEV;
2c3dfe3f 6410 }
7c3df132
SK		 6411 ql_log(ql_log_info, NULL, 0x0005,
6412 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6413 qla2x00_version_str);
7ee61397 6414 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6415 if (ret) {
6416 kmem_cache_destroy(srb_cachep);
2d70c103 6417 qlt_exit();
fca29703 6418 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6419 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6420 ql_log(ql_log_fatal, NULL, 0x0006,
6421 "pci_register_driver failed...ret=%d Failing load!.\n",
6422 ret);
fca29703
AV		 6423 }
6424 return ret;
1da177e4
LT		 6425}
6426
6427/**
6428 * qla2x00_module_exit - Module cleanup.
6429 **/
6430static void __exit
6431qla2x00_module_exit(void)
6432{
6a03b4cd 6433 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6434 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6435 qla2x00_release_firmware();
354d6b21 6436 kmem_cache_destroy(srb_cachep);
2d70c103 6437 qlt_exit();
a9083016
GM		 6438 if (ctx_cachep)
6439 kmem_cache_destroy(ctx_cachep);
1da177e4 6440 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6441 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6442}
6443
6444module_init(qla2x00_module_init);
6445module_exit(qla2x00_module_exit);
6446
6447MODULE_AUTHOR("QLogic Corporation");
6448MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6449MODULE_LICENSE("GPL");
6450MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6451MODULE_FIRMWARE(FW_FILE_ISP21XX);
6452MODULE_FIRMWARE(FW_FILE_ISP22XX);
6453MODULE_FIRMWARE(FW_FILE_ISP2300);
6454MODULE_FIRMWARE(FW_FILE_ISP2322);
6455MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6456MODULE_FIRMWARE(FW_FILE_ISP25XX);
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