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scsi: qedf: Fix crash due to unsolicited FIP VLAN response.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
1da177e4 240/*
fa2a1ce5 241 * SCSI host template entry points
1da177e4
LT		 242 */
243static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 244static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 245static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
246static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 247static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 248static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 249static int qla2xxx_eh_abort(struct scsi_cmnd *);
250static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 251static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 252static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
253static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 254
1a2fbf18 255static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 256static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 257static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 258static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 259
a5326f86 260struct scsi_host_template qla2xxx_driver_template = {
1da177e4 261 .module = THIS_MODULE,
cb63067a 262 .name = QLA2XXX_DRIVER_NAME,
a5326f86 263 .queuecommand = qla2xxx_queuecommand,
fca29703 264
b6a05c82 265 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 266 .eh_abort_handler = qla2xxx_eh_abort,
267 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 268 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 269 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
270 .eh_host_reset_handler = qla2xxx_eh_host_reset,
271
272 .slave_configure = qla2xxx_slave_configure,
273
274 .slave_alloc = qla2xxx_slave_alloc,
275 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 276 .scan_finished = qla2xxx_scan_finished,
277 .scan_start = qla2xxx_scan_start,
db5ed4df 278 .change_queue_depth = scsi_change_queue_depth,
5601236b 279 .map_queues = qla2xxx_map_queues,
fca29703
AV		 280 .this_id = -1,
281 .cmd_per_lun = 3,
282 .use_clustering = ENABLE_CLUSTERING,
283 .sg_tablesize = SG_ALL,
284
285 .max_sectors = 0xFFFF,
afb046e2 286 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 287
288 .supported_mode = MODE_INITIATOR,
c40ecc12 289 .track_queue_depth = 1,
fca29703
AV		 290};
291
1da177e4 292static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 293struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 294
1da177e4
LT		 295/* TODO Convert to inlines
296 *
297 * Timer routines
298 */
1da177e4 299
2c3dfe3f 300__inline__ void
e315cd28 301qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 302{
e315cd28
AC		 303 init_timer(&vha->timer);
304 vha->timer.expires = jiffies + interval * HZ;
305 vha->timer.data = (unsigned long)vha;
306 vha->timer.function = (void (*)(unsigned long))func;
307 add_timer(&vha->timer);
308 vha->timer_active = 1;
1da177e4
LT		 309}
310
311static inline void
e315cd28 312qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 313{
a9083016 314 /* Currently used for 82XX only. */
7c3df132
SK		 315 if (vha->device_flags & DFLG_DEV_FAILED) {
316 ql_dbg(ql_dbg_timer, vha, 0x600d,
317 "Device in a failed state, returning.\n");
a9083016 318 return;
7c3df132 319 }
a9083016 320
e315cd28 321 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 322}
323
a824ebb3 324static __inline__ void
e315cd28 325qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 326{
e315cd28
AC		 327 del_timer_sync(&vha->timer);
328 vha->timer_active = 0;
1da177e4
LT		 329}
330
1da177e4
LT		 331static int qla2x00_do_dpc(void *data);
332
333static void qla2x00_rst_aen(scsi_qla_host_t *);
334
73208dfd
AC		 335static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
336 struct req_que **, struct rsp_que **);
e30d1756 337static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 338static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 339int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
340 struct qla_qpair *qpair);
1da177e4 341
1da177e4 342/* -------------------------------------------------------------------------- */
9a347ff4
CD		 343static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
344 struct rsp_que *rsp)
73208dfd 345{
7c3df132 346 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 347 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 348 GFP_KERNEL);
349 if (!ha->req_q_map) {
7c3df132
SK		 350 ql_log(ql_log_fatal, vha, 0x003b,
351 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 352 goto fail_req_map;
353 }
354
2afa19a9 355 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 356 GFP_KERNEL);
357 if (!ha->rsp_q_map) {
7c3df132
SK		 358 ql_log(ql_log_fatal, vha, 0x003c,
359 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 360 goto fail_rsp_map;
361 }
d7459527
MH		 362
363 if (ql2xmqsupport && ha->max_qpairs) {
364 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
365 GFP_KERNEL);
366 if (!ha->queue_pair_map) {
367 ql_log(ql_log_fatal, vha, 0x0180,
368 "Unable to allocate memory for queue pair ptrs.\n");
369 goto fail_qpair_map;
370 }
371 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
372 if (ha->base_qpair == NULL) {
373 ql_log(ql_log_warn, vha, 0x0182,
374 "Failed to allocate base queue pair memory.\n");
375 goto fail_base_qpair;
376 }
377 ha->base_qpair->req = req;
378 ha->base_qpair->rsp = rsp;
379 }
380
9a347ff4
CD		 381 /*
382 * Make sure we record at least the request and response queue zero in
383 * case we need to free them if part of the probe fails.
384 */
385 ha->rsp_q_map[0] = rsp;
386 ha->req_q_map[0] = req;
73208dfd
AC		 387 set_bit(0, ha->rsp_qid_map);
388 set_bit(0, ha->req_qid_map);
389 return 1;
390
d7459527
MH		 391fail_base_qpair:
392 kfree(ha->queue_pair_map);
393fail_qpair_map:
394 kfree(ha->rsp_q_map);
395 ha->rsp_q_map = NULL;
73208dfd
AC		 396fail_rsp_map:
397 kfree(ha->req_q_map);
398 ha->req_q_map = NULL;
399fail_req_map:
400 return -ENOMEM;
401}
402
2afa19a9 403static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 404{
8ae6d9c7
GM		 405 if (IS_QLAFX00(ha)) {
406 if (req && req->ring_fx00)
407 dma_free_coherent(&ha->pdev->dev,
408 (req->length_fx00 + 1) * sizeof(request_t),
409 req->ring_fx00, req->dma_fx00);
410 } else if (req && req->ring)
73208dfd
AC		 411 dma_free_coherent(&ha->pdev->dev,
412 (req->length + 1) * sizeof(request_t),
413 req->ring, req->dma);
414
8d93f550
CD		 415 if (req)
416 kfree(req->outstanding_cmds);
417
73208dfd
AC		 418 kfree(req);
419 req = NULL;
420}
421
2afa19a9
AC		 422static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
423{
8ae6d9c7
GM		 424 if (IS_QLAFX00(ha)) {
425 if (rsp && rsp->ring)
426 dma_free_coherent(&ha->pdev->dev,
427 (rsp->length_fx00 + 1) * sizeof(request_t),
428 rsp->ring_fx00, rsp->dma_fx00);
429 } else if (rsp && rsp->ring) {
2afa19a9
AC		 430 dma_free_coherent(&ha->pdev->dev,
431 (rsp->length + 1) * sizeof(response_t),
432 rsp->ring, rsp->dma);
8ae6d9c7 433 }
2afa19a9
AC		 434 kfree(rsp);
435 rsp = NULL;
436}
437
73208dfd
AC		 438static void qla2x00_free_queues(struct qla_hw_data *ha)
439{
440 struct req_que *req;
441 struct rsp_que *rsp;
442 int cnt;
093df737 443 unsigned long flags;
73208dfd 444
093df737 445 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 446 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 447 if (!test_bit(cnt, ha->req_qid_map))
448 continue;
449
73208dfd 450 req = ha->req_q_map[cnt];
093df737
QT		 451 clear_bit(cnt, ha->req_qid_map);
452 ha->req_q_map[cnt] = NULL;
453
454 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 455 qla2x00_free_req_que(ha, req);
093df737 456 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 457 }
093df737
QT		 458 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459
73208dfd
AC		 460 kfree(ha->req_q_map);
461 ha->req_q_map = NULL;
2afa19a9 462
093df737
QT		 463
464 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 465 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 466 if (!test_bit(cnt, ha->rsp_qid_map))
467 continue;
468
2afa19a9 469 rsp = ha->rsp_q_map[cnt];
c3c42394 470 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 471 ha->rsp_q_map[cnt] = NULL;
472 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 473 qla2x00_free_rsp_que(ha, rsp);
093df737 474 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 475 }
093df737
QT		 476 spin_unlock_irqrestore(&ha->hardware_lock, flags);
477
2afa19a9
AC		 478 kfree(ha->rsp_q_map);
479 ha->rsp_q_map = NULL;
73208dfd
AC		 480}
481
1da177e4 482static char *
e315cd28 483qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 484{
e315cd28 485 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 486 static char *pci_bus_modes[] = {
487 "33", "66", "100", "133",
488 };
489 uint16_t pci_bus;
490
491 strcpy(str, "PCI");
492 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
493 if (pci_bus) {
494 strcat(str, "-X (");
495 strcat(str, pci_bus_modes[pci_bus]);
496 } else {
497 pci_bus = (ha->pci_attr & BIT_8) >> 8;
498 strcat(str, " (");
499 strcat(str, pci_bus_modes[pci_bus]);
500 }
501 strcat(str, " MHz)");
502
503 return (str);
504}
505
fca29703 506static char *
e315cd28 507qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 508{
509 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 510 struct qla_hw_data *ha = vha->hw;
fca29703 511 uint32_t pci_bus;
fca29703 512
62a276f8 513 if (pci_is_pcie(ha->pdev)) {
fca29703 514 char lwstr[6];
62a276f8 515 uint32_t lstat, lspeed, lwidth;
fca29703 516
62a276f8
BH		 517 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
518 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
519 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 520
521 strcpy(str, "PCIe (");
49300af7
SK		 522 switch (lspeed) {
523 case 1:
c87a0d8c 524 strcat(str, "2.5GT/s ");
49300af7
SK		 525 break;
526 case 2:
c87a0d8c 527 strcat(str, "5.0GT/s ");
49300af7
SK		 528 break;
529 case 3:
530 strcat(str, "8.0GT/s ");
531 break;
532 default:
fca29703 533 strcat(str, "<unknown> ");
49300af7
SK		 534 break;
535 }
fca29703
AV		 536 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
537 strcat(str, lwstr);
538
539 return str;
540 }
541
542 strcpy(str, "PCI");
543 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
544 if (pci_bus == 0 || pci_bus == 8) {
545 strcat(str, " (");
546 strcat(str, pci_bus_modes[pci_bus >> 3]);
547 } else {
548 strcat(str, "-X ");
549 if (pci_bus & BIT_2)
550 strcat(str, "Mode 2");
551 else
552 strcat(str, "Mode 1");
553 strcat(str, " (");
554 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
555 }
556 strcat(str, " MHz)");
557
558 return str;
559}
560
e5f82ab8 561static char *
df57caba 562qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 563{
564 char un_str[10];
e315cd28 565 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 566
df57caba
HM		 567 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
568 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 569
570 if (ha->fw_attributes & BIT_9) {
571 strcat(str, "FLX");
572 return (str);
573 }
574
575 switch (ha->fw_attributes & 0xFF) {
576 case 0x7:
577 strcat(str, "EF");
578 break;
579 case 0x17:
580 strcat(str, "TP");
581 break;
582 case 0x37:
583 strcat(str, "IP");
584 break;
585 case 0x77:
586 strcat(str, "VI");
587 break;
588 default:
589 sprintf(un_str, "(%x)", ha->fw_attributes);
590 strcat(str, un_str);
591 break;
592 }
593 if (ha->fw_attributes & 0x100)
594 strcat(str, "X");
595
596 return (str);
597}
598
e5f82ab8 599static char *
df57caba 600qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 601{
e315cd28 602 struct qla_hw_data *ha = vha->hw;
f0883ac6 603
df57caba 604 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 605 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 606 return str;
fca29703
AV		 607}
608
9ba56b95
GM		 609void
610qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 611{
9ba56b95
GM		 612 srb_t *sp = (srb_t *)ptr;
613 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
614 struct qla_hw_data *ha = sp->fcport->vha->hw;
615 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 616
9ba56b95
GM		 617 if (sp->flags & SRB_DMA_VALID) {
618 scsi_dma_unmap(cmd);
619 sp->flags &= ~SRB_DMA_VALID;
7c3df132 620 }
fca29703 621
9ba56b95
GM		 622 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
623 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
624 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
625 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
626 }
627
628 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
629 /* List assured to be having elements */
f83adb61 630 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 631 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
632 }
633
634 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
635 dma_pool_free(ha->dl_dma_pool, ctx,
636 ((struct crc_context *)ctx)->crc_ctx_dma);
637 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
638 }
639
640 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
641 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 642
9ba56b95
GM		 643 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
644 ctx1->fcp_cmnd_dma);
645 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
646 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
647 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
648 mempool_free(ctx1, ha->ctx_mempool);
649 ctx1 = NULL;
650 }
651
652 CMD_SP(cmd) = NULL;
b00ee7d7 653 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 654}
655
d7459527 656void
9ba56b95
GM		 657qla2x00_sp_compl(void *data, void *ptr, int res)
658{
659 struct qla_hw_data *ha = (struct qla_hw_data *)data;
660 srb_t *sp = (srb_t *)ptr;
661 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
662
663 cmd->result = res;
664
665 if (atomic_read(&sp->ref_count) == 0) {
666 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
667 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
668 sp, GET_CMD_SP(sp));
669 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 670 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 671 return;
672 }
673 if (!atomic_dec_and_test(&sp->ref_count))
674 return;
675
676 qla2x00_sp_free_dma(ha, sp);
677 cmd->scsi_done(cmd);
fca29703
AV		 678}
679
d7459527
MH		 680void
681qla2xxx_qpair_sp_free_dma(void *vha, void *ptr)
682{
683 srb_t *sp = (srb_t *)ptr;
684 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
685 struct qla_hw_data *ha = sp->fcport->vha->hw;
686 void *ctx = GET_CMD_CTX_SP(sp);
687
688 if (sp->flags & SRB_DMA_VALID) {
689 scsi_dma_unmap(cmd);
690 sp->flags &= ~SRB_DMA_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
694 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
695 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
696 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
697 }
698
699 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
700 /* List assured to be having elements */
701 qla2x00_clean_dsd_pool(ha, sp, NULL);
702 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
703 }
704
705 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
706 dma_pool_free(ha->dl_dma_pool, ctx,
707 ((struct crc_context *)ctx)->crc_ctx_dma);
708 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
709 }
710
711 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
712 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
713
714 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
715 ctx1->fcp_cmnd_dma);
716 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
717 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
718 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
719 mempool_free(ctx1, ha->ctx_mempool);
720 }
721
722 CMD_SP(cmd) = NULL;
723 qla2xxx_rel_qpair_sp(sp->qpair, sp);
724}
725
726void
727qla2xxx_qpair_sp_compl(void *data, void *ptr, int res)
728{
729 srb_t *sp = (srb_t *)ptr;
730 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
731
732 cmd->result = res;
733
734 if (atomic_read(&sp->ref_count) == 0) {
735 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
736 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
737 sp, GET_CMD_SP(sp));
738 if (ql2xextended_error_logging & ql_dbg_io)
739 WARN_ON(atomic_read(&sp->ref_count) == 0);
740 return;
741 }
742 if (!atomic_dec_and_test(&sp->ref_count))
743 return;
744
745 qla2xxx_qpair_sp_free_dma(sp->fcport->vha, sp);
746 cmd->scsi_done(cmd);
747}
748
8ae6d9c7
GM		 749/* If we are SP1 here, we need to still take and release the host_lock as SP1
750 * does not have the changes necessary to avoid taking host->host_lock.
751 */
1da177e4 752static int
f5e3e40b 753qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 754{
134ae078 755 scsi_qla_host_t *vha = shost_priv(host);
fca29703 756 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 757 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 758 struct qla_hw_data *ha = vha->hw;
759 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 760 srb_t *sp;
761 int rval;
5601236b
MH		 762 struct qla_qpair *qpair = NULL;
763 uint32_t tag;
764 uint16_t hwq;
fca29703 765
04dfaa53
MFO		 766 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
767 cmd->result = DID_NO_CONNECT << 16;
768 goto qc24_fail_command;
769 }
770
5601236b
MH		 771 if (ha->mqenable) {
772 if (shost_use_blk_mq(vha->host)) {
773 tag = blk_mq_unique_tag(cmd->request);
774 hwq = blk_mq_unique_tag_to_hwq(tag);
775 qpair = ha->queue_pair_map[hwq];
776 } else if (vha->vp_idx && vha->qpair) {
777 qpair = vha->qpair;
778 }
779
780 if (qpair)
781 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 782 }
783
85880801 784 if (ha->flags.eeh_busy) {
7c3df132 785 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 786 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 787 "PCI Channel IO permanent failure, exiting "
788 "cmd=%p.\n", cmd);
b9b12f73 789 cmd->result = DID_NO_CONNECT << 16;
7c3df132 790 } else {
5f28d2d7 791 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 792 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 793 cmd->result = DID_REQUEUE << 16;
7c3df132 794 }
14e660e6
SJ		 795 goto qc24_fail_command;
796 }
797
19a7b4ae
JSEC		 798 rval = fc_remote_port_chkready(rport);
799 if (rval) {
800 cmd->result = rval;
5f28d2d7 801 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 802 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
803 cmd, rval);
fca29703
AV		 804 goto qc24_fail_command;
805 }
806
bad75002
AE		 807 if (!vha->flags.difdix_supported &&
808 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 809 ql_dbg(ql_dbg_io, vha, 0x3004,
810 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
811 cmd);
bad75002
AE		 812 cmd->result = DID_NO_CONNECT << 16;
813 goto qc24_fail_command;
814 }
aa651be8
CD		 815
816 if (!fcport) {
817 cmd->result = DID_NO_CONNECT << 16;
818 goto qc24_fail_command;
819 }
820
fca29703
AV		 821 if (atomic_read(&fcport->state) != FCS_ONLINE) {
822 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 823 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 824 ql_dbg(ql_dbg_io, vha, 0x3005,
825 "Returning DNC, fcport_state=%d loop_state=%d.\n",
826 atomic_read(&fcport->state),
827 atomic_read(&base_vha->loop_state));
fca29703
AV		 828 cmd->result = DID_NO_CONNECT << 16;
829 goto qc24_fail_command;
830 }
7b594131 831 goto qc24_target_busy;
fca29703
AV		 832 }
833
e05fe292
CD		 834 /*
835 * Return target busy if we've received a non-zero retry_delay_timer
836 * in a FCP_RSP.
837 */
975f7d46
BP		 838 if (fcport->retry_delay_timestamp == 0) {
839 /* retry delay not set */
840 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 841 fcport->retry_delay_timestamp = 0;
842 else
843 goto qc24_target_busy;
844
b00ee7d7 845 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 846 if (!sp)
f5e3e40b 847 goto qc24_host_busy;
fca29703 848
9ba56b95
GM		 849 sp->u.scmd.cmd = cmd;
850 sp->type = SRB_SCSI_CMD;
851 atomic_set(&sp->ref_count, 1);
852 CMD_SP(cmd) = (void *)sp;
853 sp->free = qla2x00_sp_free_dma;
854 sp->done = qla2x00_sp_compl;
855
e315cd28 856 rval = ha->isp_ops->start_scsi(sp);
7c3df132 857 if (rval != QLA_SUCCESS) {
53016ed3 858 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 859 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 860 goto qc24_host_busy_free_sp;
7c3df132 861 }
fca29703 862
fca29703
AV		 863 return 0;
864
865qc24_host_busy_free_sp:
9ba56b95 866 qla2x00_sp_free_dma(ha, sp);
fca29703 867
f5e3e40b 868qc24_host_busy:
fca29703
AV		 869 return SCSI_MLQUEUE_HOST_BUSY;
870
7b594131
MC		 871qc24_target_busy:
872 return SCSI_MLQUEUE_TARGET_BUSY;
873
fca29703 874qc24_fail_command:
f5e3e40b 875 cmd->scsi_done(cmd);
fca29703
AV		 876
877 return 0;
878}
879
d7459527
MH		 880/* For MQ supported I/O */
881int
882qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
883 struct qla_qpair *qpair)
884{
885 scsi_qla_host_t *vha = shost_priv(host);
886 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
887 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
888 struct qla_hw_data *ha = vha->hw;
889 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
890 srb_t *sp;
891 int rval;
892
893 rval = fc_remote_port_chkready(rport);
894 if (rval) {
895 cmd->result = rval;
896 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
897 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
898 cmd, rval);
899 goto qc24_fail_command;
900 }
901
902 if (!fcport) {
903 cmd->result = DID_NO_CONNECT << 16;
904 goto qc24_fail_command;
905 }
906
907 if (atomic_read(&fcport->state) != FCS_ONLINE) {
908 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
909 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
910 ql_dbg(ql_dbg_io, vha, 0x3077,
911 "Returning DNC, fcport_state=%d loop_state=%d.\n",
912 atomic_read(&fcport->state),
913 atomic_read(&base_vha->loop_state));
914 cmd->result = DID_NO_CONNECT << 16;
915 goto qc24_fail_command;
916 }
917 goto qc24_target_busy;
918 }
919
920 /*
921 * Return target busy if we've received a non-zero retry_delay_timer
922 * in a FCP_RSP.
923 */
924 if (fcport->retry_delay_timestamp == 0) {
925 /* retry delay not set */
926 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
927 fcport->retry_delay_timestamp = 0;
928 else
929 goto qc24_target_busy;
930
931 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
932 if (!sp)
933 goto qc24_host_busy;
934
935 sp->u.scmd.cmd = cmd;
936 sp->type = SRB_SCSI_CMD;
937 atomic_set(&sp->ref_count, 1);
938 CMD_SP(cmd) = (void *)sp;
939 sp->free = qla2xxx_qpair_sp_free_dma;
940 sp->done = qla2xxx_qpair_sp_compl;
941 sp->qpair = qpair;
942
943 rval = ha->isp_ops->start_scsi_mq(sp);
944 if (rval != QLA_SUCCESS) {
945 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
946 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
947 if (rval == QLA_INTERFACE_ERROR)
948 goto qc24_fail_command;
949 goto qc24_host_busy_free_sp;
950 }
951
952 return 0;
953
954qc24_host_busy_free_sp:
955 qla2xxx_qpair_sp_free_dma(vha, sp);
956
957qc24_host_busy:
958 return SCSI_MLQUEUE_HOST_BUSY;
959
960qc24_target_busy:
961 return SCSI_MLQUEUE_TARGET_BUSY;
962
963qc24_fail_command:
964 cmd->scsi_done(cmd);
965
966 return 0;
967}
968
1da177e4
LT		 969/*
970 * qla2x00_eh_wait_on_command
971 * Waits for the command to be returned by the Firmware for some
972 * max time.
973 *
974 * Input:
1da177e4 975 * cmd = Scsi Command to wait on.
1da177e4
LT		 976 *
977 * Return:
978 * Not Found : 0
979 * Found : 1
980 */
981static int
e315cd28 982qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 983{
fe74c71f 984#define ABORT_POLLING_PERIOD 1000
478c3b03 985#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 986 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 987 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
988 struct qla_hw_data *ha = vha->hw;
f4f051eb 989 int ret = QLA_SUCCESS;
1da177e4 990
85880801 991 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 992 ql_dbg(ql_dbg_taskm, vha, 0x8005,
993 "Return:eh_wait.\n");
85880801
AV		 994 return ret;
995 }
996
d970432c 997 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 998 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 999 }
1000 if (CMD_SP(cmd))
1001 ret = QLA_FUNCTION_FAILED;
1da177e4 1002
f4f051eb 1003 return ret;
1da177e4
LT		 1004}
1005
1006/*
1007 * qla2x00_wait_for_hba_online
fa2a1ce5 1008 * Wait till the HBA is online after going through
1da177e4
LT		 1009 * <= MAX_RETRIES_OF_ISP_ABORT or
1010 * finally HBA is disabled ie marked offline
1011 *
1012 * Input:
1013 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1014 *
1015 * Note:
1da177e4
LT		 1016 * Does context switching-Release SPIN_LOCK
1017 * (if any) before calling this routine.
1018 *
1019 * Return:
1020 * Success (Adapter is online) : 0
1021 * Failed (Adapter is offline/disabled) : 1
1022 */
854165f4 1023int
e315cd28 1024qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1025{
fca29703
AV		 1026 int return_status;
1027 unsigned long wait_online;
e315cd28
AC		 1028 struct qla_hw_data *ha = vha->hw;
1029 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1030
fa2a1ce5 1031 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1032 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1033 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1034 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1035 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1036
1037 msleep(1000);
1038 }
e315cd28 1039 if (base_vha->flags.online)
fa2a1ce5 1040 return_status = QLA_SUCCESS;
1da177e4
LT		 1041 else
1042 return_status = QLA_FUNCTION_FAILED;
1043
1da177e4
LT		 1044 return (return_status);
1045}
1046
86fbee86 1047/*
638a1a01
SC		 1048 * qla2x00_wait_for_hba_ready
1049 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1050 *
1051 * Input:
1052 * ha - pointer to host adapter structure
1053 *
1054 * Note:
1055 * Does context switching-Release SPIN_LOCK
1056 * (if any) before calling this routine.
1057 *
86fbee86 1058 */
638a1a01
SC		 1059static void
1060qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1061{
86fbee86 1062 struct qla_hw_data *ha = vha->hw;
783e0dc4 1063 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1064
1d483901
DC		 1065 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1066 ha->flags.mbox_busy) ||
1067 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1068 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1069 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1070 break;
86fbee86 1071 msleep(1000);
783e0dc4 1072 }
86fbee86
LC		 1073}
1074
2533cf67
LC		 1075int
1076qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1077{
1078 int return_status;
1079 unsigned long wait_reset;
1080 struct qla_hw_data *ha = vha->hw;
1081 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1082
1083 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1084 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1085 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1086 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1087 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1088
1089 msleep(1000);
1090
1091 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1092 ha->flags.chip_reset_done)
1093 break;
1094 }
1095 if (ha->flags.chip_reset_done)
1096 return_status = QLA_SUCCESS;
1097 else
1098 return_status = QLA_FUNCTION_FAILED;
1099
1100 return return_status;
1101}
1102
083a469d
GM		 1103static void
1104sp_get(struct srb *sp)
1105{
1106 atomic_inc(&sp->ref_count);
1107}
1108
a465537a
SC		 1109#define ISP_REG_DISCONNECT 0xffffffffU
1110/**************************************************************************
1111* qla2x00_isp_reg_stat
1112*
1113* Description:
1114* Read the host status register of ISP before aborting the command.
1115*
1116* Input:
1117* ha = pointer to host adapter structure.
1118*
1119*
1120* Returns:
1121* Either true or false.
1122*
1123* Note: Return true if there is register disconnect.
1124**************************************************************************/
1125static inline
1126uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1127{
1128 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1129
1130 return ((RD_REG_DWORD(&reg->host_status)) == ISP_REG_DISCONNECT);
1131}
1132
1da177e4
LT		 1133/**************************************************************************
1134* qla2xxx_eh_abort
1135*
1136* Description:
1137* The abort function will abort the specified command.
1138*
1139* Input:
1140* cmd = Linux SCSI command packet to be aborted.
1141*
1142* Returns:
1143* Either SUCCESS or FAILED.
1144*
1145* Note:
2ea00202 1146* Only return FAILED if command not returned by firmware.
1da177e4 1147**************************************************************************/
e5f82ab8 1148static int
1da177e4
LT		 1149qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1150{
e315cd28 1151 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1152 srb_t *sp;
4e98d3b8 1153 int ret;
9cb78c16
HR		 1154 unsigned int id;
1155 uint64_t lun;
18e144d3 1156 unsigned long flags;
f934c9d0 1157 int rval, wait = 0;
e315cd28 1158 struct qla_hw_data *ha = vha->hw;
1da177e4 1159
a465537a
SC		 1160 if (qla2x00_isp_reg_stat(ha)) {
1161 ql_log(ql_log_info, vha, 0x8042,
1162 "PCI/Register disconnect, exiting.\n");
1163 return FAILED;
1164 }
f4f051eb 1165 if (!CMD_SP(cmd))
2ea00202 1166 return SUCCESS;
1da177e4 1167
4e98d3b8
AV		 1168 ret = fc_block_scsi_eh(cmd);
1169 if (ret != 0)
1170 return ret;
1171 ret = SUCCESS;
1172
f4f051eb
AV		 1173 id = cmd->device->id;
1174 lun = cmd->device->lun;
1da177e4 1175
e315cd28 1176 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1177 sp = (srb_t *) CMD_SP(cmd);
1178 if (!sp) {
1179 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1180 return SUCCESS;
1181 }
1da177e4 1182
7c3df132 1183 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1184 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1185 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1186
170babc3
MC		 1187 /* Get a reference to the sp and drop the lock.*/
1188 sp_get(sp);
083a469d 1189
e315cd28 1190 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1191 rval = ha->isp_ops->abort_command(sp);
1192 if (rval) {
96219424 1193 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1194 ret = SUCCESS;
96219424 1195 else
f934c9d0
CD		 1196 ret = FAILED;
1197
7c3df132 1198 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1199 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1200 } else {
7c3df132 1201 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1202 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1203 wait = 1;
1204 }
75942064
SK		 1205
1206 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 1207 sp->done(ha, sp, 0);
75942064 1208 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1209
bc91ade9
CD		 1210 /* Did the command return during mailbox execution? */
1211 if (ret == FAILED && !CMD_SP(cmd))
1212 ret = SUCCESS;
1213
f4f051eb 1214 /* Wait for the command to be returned. */
2ea00202 1215 if (wait) {
e315cd28 1216 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1217 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1218 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1219 ret = FAILED;
f4f051eb 1220 }
1da177e4 1221 }
1da177e4 1222
7c3df132 1223 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1224 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1225 vha->host_no, id, lun, wait, ret);
1da177e4 1226
f4f051eb
AV		 1227 return ret;
1228}
1da177e4 1229
4d78c973 1230int
e315cd28 1231qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1232 uint64_t l, enum nexus_wait_type type)
f4f051eb 1233{
17d98630 1234 int cnt, match, status;
18e144d3 1235 unsigned long flags;
e315cd28 1236 struct qla_hw_data *ha = vha->hw;
73208dfd 1237 struct req_que *req;
4d78c973 1238 srb_t *sp;
9ba56b95 1239 struct scsi_cmnd *cmd;
1da177e4 1240
523ec773 1241 status = QLA_SUCCESS;
17d98630 1242
e315cd28 1243 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1244 req = vha->req;
17d98630 1245 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1246 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1247 sp = req->outstanding_cmds[cnt];
1248 if (!sp)
523ec773 1249 continue;
9ba56b95 1250 if (sp->type != SRB_SCSI_CMD)
cf53b069 1251 continue;
17d98630
AC		 1252 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1253 continue;
1254 match = 0;
9ba56b95 1255 cmd = GET_CMD_SP(sp);
17d98630
AC		 1256 switch (type) {
1257 case WAIT_HOST:
1258 match = 1;
1259 break;
1260 case WAIT_TARGET:
9ba56b95 1261 match = cmd->device->id == t;
17d98630
AC		 1262 break;
1263 case WAIT_LUN:
9ba56b95
GM		 1264 match = (cmd->device->id == t &&
1265 cmd->device->lun == l);
17d98630 1266 break;
73208dfd 1267 }
17d98630
AC		 1268 if (!match)
1269 continue;
1270
1271 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1272 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1273 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1274 }
e315cd28 1275 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1276
1277 return status;
1da177e4
LT		 1278}
1279
523ec773
AV		 1280static char *reset_errors[] = {
1281 "HBA not online",
1282 "HBA not ready",
1283 "Task management failed",
1284 "Waiting for command completions",
1285};
1da177e4 1286
e5f82ab8 1287static int
523ec773 1288__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1289 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1290{
e315cd28 1291 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1292 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1293 int err;
1da177e4 1294
7c3df132 1295 if (!fcport) {
523ec773 1296 return FAILED;
7c3df132 1297 }
1da177e4 1298
4e98d3b8
AV		 1299 err = fc_block_scsi_eh(cmd);
1300 if (err != 0)
1301 return err;
1302
7c3df132 1303 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1304 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1305 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1306
523ec773 1307 err = 0;
7c3df132
SK		 1308 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1309 ql_log(ql_log_warn, vha, 0x800a,
1310 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1311 goto eh_reset_failed;
7c3df132 1312 }
523ec773 1313 err = 2;
2afa19a9 1314 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1315 != QLA_SUCCESS) {
1316 ql_log(ql_log_warn, vha, 0x800c,
1317 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1318 goto eh_reset_failed;
7c3df132 1319 }
523ec773 1320 err = 3;
e315cd28 1321 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1322 cmd->device->lun, type) != QLA_SUCCESS) {
1323 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1324 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1325 goto eh_reset_failed;
7c3df132 1326 }
523ec773 1327
7c3df132 1328 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1329 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1330 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1331
1332 return SUCCESS;
1333
4d78c973 1334eh_reset_failed:
7c3df132 1335 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1336 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1337 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1338 cmd);
523ec773
AV		 1339 return FAILED;
1340}
1da177e4 1341
523ec773
AV		 1342static int
1343qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1344{
e315cd28
AC		 1345 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1346 struct qla_hw_data *ha = vha->hw;
1da177e4 1347
a465537a
SC		 1348 if (qla2x00_isp_reg_stat(ha)) {
1349 ql_log(ql_log_info, vha, 0x803e,
1350 "PCI/Register disconnect, exiting.\n");
1351 return FAILED;
1352 }
1353
523ec773
AV		 1354 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1355 ha->isp_ops->lun_reset);
1da177e4
LT		 1356}
1357
1da177e4 1358static int
523ec773 1359qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1360{
e315cd28
AC		 1361 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1362 struct qla_hw_data *ha = vha->hw;
1da177e4 1363
a465537a
SC		 1364 if (qla2x00_isp_reg_stat(ha)) {
1365 ql_log(ql_log_info, vha, 0x803f,
1366 "PCI/Register disconnect, exiting.\n");
1367 return FAILED;
1368 }
1369
523ec773
AV		 1370 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1371 ha->isp_ops->target_reset);
1da177e4
LT		 1372}
1373
1da177e4
LT		 1374/**************************************************************************
1375* qla2xxx_eh_bus_reset
1376*
1377* Description:
1378* The bus reset function will reset the bus and abort any executing
1379* commands.
1380*
1381* Input:
1382* cmd = Linux SCSI command packet of the command that cause the
1383* bus reset.
1384*
1385* Returns:
1386* SUCCESS/FAILURE (defined as macro in scsi.h).
1387*
1388**************************************************************************/
e5f82ab8 1389static int
1da177e4
LT		 1390qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1391{
e315cd28 1392 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1393 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1394 int ret = FAILED;
9cb78c16
HR		 1395 unsigned int id;
1396 uint64_t lun;
a465537a
SC		 1397 struct qla_hw_data *ha = vha->hw;
1398
1399 if (qla2x00_isp_reg_stat(ha)) {
1400 ql_log(ql_log_info, vha, 0x8040,
1401 "PCI/Register disconnect, exiting.\n");
1402 return FAILED;
1403 }
f4f051eb 1404
f4f051eb
AV		 1405 id = cmd->device->id;
1406 lun = cmd->device->lun;
1da177e4 1407
7c3df132 1408 if (!fcport) {
f4f051eb 1409 return ret;
7c3df132 1410 }
1da177e4 1411
4e98d3b8
AV		 1412 ret = fc_block_scsi_eh(cmd);
1413 if (ret != 0)
1414 return ret;
1415 ret = FAILED;
1416
7c3df132 1417 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1418 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1419
e315cd28 1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1421 ql_log(ql_log_fatal, vha, 0x8013,
1422 "Wait for hba online failed board disabled.\n");
f4f051eb 1423 goto eh_bus_reset_done;
1da177e4
LT		 1424 }
1425
ad537689
SK		 1426 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1427 ret = SUCCESS;
1428
f4f051eb
AV		 1429 if (ret == FAILED)
1430 goto eh_bus_reset_done;
1da177e4 1431
9a41a62b 1432 /* Flush outstanding commands. */
4d78c973 1433 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1434 QLA_SUCCESS) {
1435 ql_log(ql_log_warn, vha, 0x8014,
1436 "Wait for pending commands failed.\n");
9a41a62b 1437 ret = FAILED;
7c3df132 1438 }
1da177e4 1439
f4f051eb 1440eh_bus_reset_done:
7c3df132 1441 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1442 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1443 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1444
f4f051eb 1445 return ret;
1da177e4
LT		 1446}
1447
1448/**************************************************************************
1449* qla2xxx_eh_host_reset
1450*
1451* Description:
1452* The reset function will reset the Adapter.
1453*
1454* Input:
1455* cmd = Linux SCSI command packet of the command that cause the
1456* adapter reset.
1457*
1458* Returns:
1459* Either SUCCESS or FAILED.
1460*
1461* Note:
1462**************************************************************************/
e5f82ab8 1463static int
1da177e4
LT		 1464qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1465{
e315cd28 1466 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1467 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1468 int ret = FAILED;
9cb78c16
HR		 1469 unsigned int id;
1470 uint64_t lun;
e315cd28 1471 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1472
a465537a
SC		 1473 if (qla2x00_isp_reg_stat(ha)) {
1474 ql_log(ql_log_info, vha, 0x8041,
1475 "PCI/Register disconnect, exiting.\n");
1476 schedule_work(&ha->board_disable);
1477 return SUCCESS;
1478 }
1479
f4f051eb
AV		 1480 id = cmd->device->id;
1481 lun = cmd->device->lun;
f4f051eb 1482
7c3df132 1483 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1484 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1485
63ee7072
CD		 1486 /*
1487 * No point in issuing another reset if one is active. Also do not
1488 * attempt a reset if we are updating flash.
1489 */
1490 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1491 goto eh_host_reset_lock;
1da177e4 1492
e315cd28
AC		 1493 if (vha != base_vha) {
1494 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1495 goto eh_host_reset_lock;
e315cd28 1496 } else {
7ec0effd 1497 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1498 if (!qla82xx_fcoe_ctx_reset(vha)) {
1499 /* Ctx reset success */
1500 ret = SUCCESS;
1501 goto eh_host_reset_lock;
1502 }
1503 /* fall thru if ctx reset failed */
1504 }
68ca949c
AC		 1505 if (ha->wq)
1506 flush_workqueue(ha->wq);
1507
e315cd28 1508 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1509 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1510 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1511 /* failed. schedule dpc to try */
1512 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1513
7c3df132
SK		 1514 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1515 ql_log(ql_log_warn, vha, 0x802a,
1516 "wait for hba online failed.\n");
e315cd28 1517 goto eh_host_reset_lock;
7c3df132 1518 }
e315cd28
AC		 1519 }
1520 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1521 }
1da177e4 1522
e315cd28 1523 /* Waiting for command to be returned to OS.*/
4d78c973 1524 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1525 QLA_SUCCESS)
f4f051eb 1526 ret = SUCCESS;
1da177e4 1527
f4f051eb 1528eh_host_reset_lock:
cfb0919c 1529 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1530 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1531 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1532
f4f051eb
AV		 1533 return ret;
1534}
1da177e4
LT		 1535
1536/*
1537* qla2x00_loop_reset
1538* Issue loop reset.
1539*
1540* Input:
1541* ha = adapter block pointer.
1542*
1543* Returns:
1544* 0 = success
1545*/
a4722cf2 1546int
e315cd28 1547qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1548{
0c8c39af 1549 int ret;
bdf79621 1550 struct fc_port *fcport;
e315cd28 1551 struct qla_hw_data *ha = vha->hw;
1da177e4 1552
5854771e
AB		 1553 if (IS_QLAFX00(ha)) {
1554 return qlafx00_loop_reset(vha);
1555 }
1556
f4c496c1 1557 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1558 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1559 if (fcport->port_type != FCT_TARGET)
1560 continue;
1561
1562 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1563 if (ret != QLA_SUCCESS) {
7c3df132 1564 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1565 "Bus Reset failed: Reset=%d "
7c3df132 1566 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1567 }
1568 }
1569 }
1570
8ae6d9c7 1571
6246b8a1 1572 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1573 atomic_set(&vha->loop_state, LOOP_DOWN);
1574 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1575 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1576 ret = qla2x00_full_login_lip(vha);
0c8c39af 1577 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1578 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1579 "full_login_lip=%d.\n", ret);
749af3d5 1580 }
0c8c39af
AV		 1581 }
1582
0d6e61bc 1583 if (ha->flags.enable_lip_reset) {
e315cd28 1584 ret = qla2x00_lip_reset(vha);
ad537689 1585 if (ret != QLA_SUCCESS)
7c3df132
SK		 1586 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1587 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1588 }
1589
1da177e4 1590 /* Issue marker command only when we are going to start the I/O */
e315cd28 1591 vha->marker_needed = 1;
1da177e4 1592
0c8c39af 1593 return QLA_SUCCESS;
1da177e4
LT		 1594}
1595
df4bf0bb 1596void
e315cd28 1597qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1598{
73208dfd 1599 int que, cnt;
df4bf0bb
AV		 1600 unsigned long flags;
1601 srb_t *sp;
e315cd28 1602 struct qla_hw_data *ha = vha->hw;
73208dfd 1603 struct req_que *req;
df4bf0bb 1604
c0cb4496
AE		 1605 qlt_host_reset_handler(ha);
1606
df4bf0bb 1607 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1608 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1609 req = ha->req_q_map[que];
73208dfd
AC		 1610 if (!req)
1611 continue;
8d93f550
CD		 1612 if (!req->outstanding_cmds)
1613 continue;
1614 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1615 sp = req->outstanding_cmds[cnt];
e612d465 1616 if (sp) {
c733ab35
MFO		 1617 /* Don't abort commands in adapter during EEH
1618 * recovery as it's not accessible/responding.
1535aa75 1619 */
5f7c2bee
BK		 1620 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1621 (sp->type == SRB_SCSI_CMD)) {
c733ab35
MFO		 1622 /* Get a reference to the sp and drop the lock.
1623 * The reference ensures this sp->done() call
1624 * - and not the call in qla2xxx_eh_abort() -
1625 * ends the SCSI command (with result 'res').
1626 */
1627 sp_get(sp);
1628 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1629 qla2xxx_eh_abort(GET_CMD_SP(sp));
1630 spin_lock_irqsave(&ha->hardware_lock, flags);
1631 }
73208dfd 1632 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1633 sp->done(vha, sp, res);
73208dfd 1634 }
df4bf0bb
AV		 1635 }
1636 }
1637 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1638}
1639
f4f051eb
AV		 1640static int
1641qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1642{
bdf79621 1643 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1644
19a7b4ae 1645 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1646 return -ENXIO;
bdf79621 1647
19a7b4ae 1648 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1649
f4f051eb
AV		 1650 return 0;
1651}
1da177e4 1652
f4f051eb
AV		 1653static int
1654qla2xxx_slave_configure(struct scsi_device *sdev)
1655{
e315cd28 1656 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1657 struct req_que *req = vha->req;
8482e118 1658
9e522cd8
AE		 1659 if (IS_T10_PI_CAPABLE(vha->hw))
1660 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1661
db5ed4df 1662 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1663 return 0;
1664}
1da177e4 1665
f4f051eb
AV		 1666static void
1667qla2xxx_slave_destroy(struct scsi_device *sdev)
1668{
1669 sdev->hostdata = NULL;
1da177e4
LT		 1670}
1671
1672/**
1673 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1674 * @ha: HA context
1675 *
1676 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1677 * supported addressing method.
1678 */
1679static void
53303c42 1680qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1681{
7524f9b9 1682 /* Assume a 32bit DMA mask. */
1da177e4 1683 ha->flags.enable_64bit_addressing = 0;
1da177e4 1684
6a35528a 1685 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1686 /* Any upper-dword bits set? */
1687 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1688 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1689 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1690 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1691 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1692 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1693 return;
1da177e4 1694 }
1da177e4 1695 }
7524f9b9 1696
284901a9
YH		 1697 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1698 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1699}
1700
fd34f556 1701static void
e315cd28 1702qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1703{
1704 unsigned long flags = 0;
1705 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1706
1707 spin_lock_irqsave(&ha->hardware_lock, flags);
1708 ha->interrupts_on = 1;
1709 /* enable risc and host interrupts */
1710 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1711 RD_REG_WORD(&reg->ictrl);
1712 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1713
1714}
1715
1716static void
e315cd28 1717qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1718{
1719 unsigned long flags = 0;
1720 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1721
1722 spin_lock_irqsave(&ha->hardware_lock, flags);
1723 ha->interrupts_on = 0;
1724 /* disable risc and host interrupts */
1725 WRT_REG_WORD(&reg->ictrl, 0);
1726 RD_REG_WORD(&reg->ictrl);
1727 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1728}
1729
1730static void
e315cd28 1731qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1732{
1733 unsigned long flags = 0;
1734 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1735
1736 spin_lock_irqsave(&ha->hardware_lock, flags);
1737 ha->interrupts_on = 1;
1738 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1739 RD_REG_DWORD(&reg->ictrl);
1740 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1741}
1742
1743static void
e315cd28 1744qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1745{
1746 unsigned long flags = 0;
1747 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1748
124f85e6
AV		 1749 if (IS_NOPOLLING_TYPE(ha))
1750 return;
fd34f556
AV		 1751 spin_lock_irqsave(&ha->hardware_lock, flags);
1752 ha->interrupts_on = 0;
1753 WRT_REG_DWORD(&reg->ictrl, 0);
1754 RD_REG_DWORD(&reg->ictrl);
1755 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1756}
1757
706f457d
GM		 1758static int
1759qla2x00_iospace_config(struct qla_hw_data *ha)
1760{
1761 resource_size_t pio;
1762 uint16_t msix;
706f457d 1763
706f457d
GM		 1764 if (pci_request_selected_regions(ha->pdev, ha->bars,
1765 QLA2XXX_DRIVER_NAME)) {
1766 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1767 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1768 pci_name(ha->pdev));
1769 goto iospace_error_exit;
1770 }
1771 if (!(ha->bars & 1))
1772 goto skip_pio;
1773
1774 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1775 pio = pci_resource_start(ha->pdev, 0);
1776 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1777 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1778 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1779 "Invalid pci I/O region size (%s).\n",
1780 pci_name(ha->pdev));
1781 pio = 0;
1782 }
1783 } else {
1784 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1785 "Region #0 no a PIO resource (%s).\n",
1786 pci_name(ha->pdev));
1787 pio = 0;
1788 }
1789 ha->pio_address = pio;
1790 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1791 "PIO address=%llu.\n",
1792 (unsigned long long)ha->pio_address);
1793
1794skip_pio:
1795 /* Use MMIO operations for all accesses. */
1796 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1797 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1798 "Region #1 not an MMIO resource (%s), aborting.\n",
1799 pci_name(ha->pdev));
1800 goto iospace_error_exit;
1801 }
1802 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1803 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1804 "Invalid PCI mem region size (%s), aborting.\n",
1805 pci_name(ha->pdev));
1806 goto iospace_error_exit;
1807 }
1808
1809 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1810 if (!ha->iobase) {
1811 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1812 "Cannot remap MMIO (%s), aborting.\n",
1813 pci_name(ha->pdev));
1814 goto iospace_error_exit;
1815 }
1816
1817 /* Determine queue resources */
1818 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1819 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1820 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1821 goto mqiobase_exit;
1822
1823 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1824 pci_resource_len(ha->pdev, 3));
1825 if (ha->mqiobase) {
1826 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1827 "MQIO Base=%p.\n", ha->mqiobase);
1828 /* Read MSIX vector size of the board */
1829 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1830 ha->msix_count = msix + 1;
706f457d 1831 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1832 /* MB interrupt uses 1 vector */
1833 ha->max_req_queues = ha->msix_count - 1;
1834 ha->max_rsp_queues = ha->max_req_queues;
1835 /* Queue pairs is the max value minus the base queue pair */
1836 ha->max_qpairs = ha->max_rsp_queues - 1;
1837 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1838 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1839
706f457d 1840 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1841 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1842 } else
1843 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1844 "BAR 3 not enabled.\n");
1845
1846mqiobase_exit:
706f457d 1847 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1848 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1849 return (0);
1850
1851iospace_error_exit:
1852 return (-ENOMEM);
1853}
1854
1855
6246b8a1
GM		 1856static int
1857qla83xx_iospace_config(struct qla_hw_data *ha)
1858{
1859 uint16_t msix;
6246b8a1
GM		 1860
1861 if (pci_request_selected_regions(ha->pdev, ha->bars,
1862 QLA2XXX_DRIVER_NAME)) {
1863 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1864 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1865 pci_name(ha->pdev));
1866
1867 goto iospace_error_exit;
1868 }
1869
1870 /* Use MMIO operations for all accesses. */
1871 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1872 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1873 "Invalid pci I/O region size (%s).\n",
1874 pci_name(ha->pdev));
1875 goto iospace_error_exit;
1876 }
1877 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1878 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1879 "Invalid PCI mem region size (%s), aborting\n",
1880 pci_name(ha->pdev));
1881 goto iospace_error_exit;
1882 }
1883
1884 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1885 if (!ha->iobase) {
1886 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1887 "Cannot remap MMIO (%s), aborting.\n",
1888 pci_name(ha->pdev));
1889 goto iospace_error_exit;
1890 }
1891
1892 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1893 /* 83XX 26XX always use MQ type access for queues
1894 * - mbar 2, a.k.a region 4 */
1895 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1896 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 1897 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1898 pci_resource_len(ha->pdev, 4));
1899
1900 if (!ha->mqiobase) {
1901 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1902 "BAR2/region4 not enabled\n");
1903 goto mqiobase_exit;
1904 }
1905
1906 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1907 pci_resource_len(ha->pdev, 2));
1908 if (ha->msixbase) {
1909 /* Read MSIX vector size of the board */
1910 pci_read_config_word(ha->pdev,
1911 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1912 ha->msix_count = msix + 1;
093df737
QT		 1913 /*
1914 * By default, driver uses at least two msix vectors
1915 * (default & rspq)
1916 */
d7459527
MH		 1917 if (ql2xmqsupport) {
1918 /* MB interrupt uses 1 vector */
1919 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 1920
1921 /* ATIOQ needs 1 vector. That's 1 less QPair */
1922 if (QLA_TGT_MODE_ENABLED())
1923 ha->max_req_queues--;
1924
d0d2c68b
MH		 1925 ha->max_rsp_queues = ha->max_req_queues;
1926
d7459527
MH		 1927 /* Queue pairs is the max value minus
1928 * the base queue pair */
1929 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1930 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1931 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1932 }
1933 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1934 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1935 } else
1936 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1937 "BAR 1 not enabled.\n");
1938
1939mqiobase_exit:
6246b8a1 1940 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 1941 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 1942 return 0;
1943
1944iospace_error_exit:
1945 return -ENOMEM;
1946}
1947
fd34f556
AV		 1948static struct isp_operations qla2100_isp_ops = {
1949 .pci_config = qla2100_pci_config,
1950 .reset_chip = qla2x00_reset_chip,
1951 .chip_diag = qla2x00_chip_diag,
1952 .config_rings = qla2x00_config_rings,
1953 .reset_adapter = qla2x00_reset_adapter,
1954 .nvram_config = qla2x00_nvram_config,
1955 .update_fw_options = qla2x00_update_fw_options,
1956 .load_risc = qla2x00_load_risc,
1957 .pci_info_str = qla2x00_pci_info_str,
1958 .fw_version_str = qla2x00_fw_version_str,
1959 .intr_handler = qla2100_intr_handler,
1960 .enable_intrs = qla2x00_enable_intrs,
1961 .disable_intrs = qla2x00_disable_intrs,
1962 .abort_command = qla2x00_abort_command,
523ec773
AV		 1963 .target_reset = qla2x00_abort_target,
1964 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1965 .fabric_login = qla2x00_login_fabric,
1966 .fabric_logout = qla2x00_fabric_logout,
1967 .calc_req_entries = qla2x00_calc_iocbs_32,
1968 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1969 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1970 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1971 .read_nvram = qla2x00_read_nvram_data,
1972 .write_nvram = qla2x00_write_nvram_data,
1973 .fw_dump = qla2100_fw_dump,
1974 .beacon_on = NULL,
1975 .beacon_off = NULL,
1976 .beacon_blink = NULL,
1977 .read_optrom = qla2x00_read_optrom_data,
1978 .write_optrom = qla2x00_write_optrom_data,
1979 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1980 .start_scsi = qla2x00_start_scsi,
d7459527 1981 .start_scsi_mq = NULL,
a9083016 1982 .abort_isp = qla2x00_abort_isp,
706f457d 1983 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1984 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1985};
1986
1987static struct isp_operations qla2300_isp_ops = {
1988 .pci_config = qla2300_pci_config,
1989 .reset_chip = qla2x00_reset_chip,
1990 .chip_diag = qla2x00_chip_diag,
1991 .config_rings = qla2x00_config_rings,
1992 .reset_adapter = qla2x00_reset_adapter,
1993 .nvram_config = qla2x00_nvram_config,
1994 .update_fw_options = qla2x00_update_fw_options,
1995 .load_risc = qla2x00_load_risc,
1996 .pci_info_str = qla2x00_pci_info_str,
1997 .fw_version_str = qla2x00_fw_version_str,
1998 .intr_handler = qla2300_intr_handler,
1999 .enable_intrs = qla2x00_enable_intrs,
2000 .disable_intrs = qla2x00_disable_intrs,
2001 .abort_command = qla2x00_abort_command,
523ec773
AV		 2002 .target_reset = qla2x00_abort_target,
2003 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2004 .fabric_login = qla2x00_login_fabric,
2005 .fabric_logout = qla2x00_fabric_logout,
2006 .calc_req_entries = qla2x00_calc_iocbs_32,
2007 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2008 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2009 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2010 .read_nvram = qla2x00_read_nvram_data,
2011 .write_nvram = qla2x00_write_nvram_data,
2012 .fw_dump = qla2300_fw_dump,
2013 .beacon_on = qla2x00_beacon_on,
2014 .beacon_off = qla2x00_beacon_off,
2015 .beacon_blink = qla2x00_beacon_blink,
2016 .read_optrom = qla2x00_read_optrom_data,
2017 .write_optrom = qla2x00_write_optrom_data,
2018 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2019 .start_scsi = qla2x00_start_scsi,
d7459527 2020 .start_scsi_mq = NULL,
a9083016 2021 .abort_isp = qla2x00_abort_isp,
7ec0effd 2022 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2023 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2024};
2025
2026static struct isp_operations qla24xx_isp_ops = {
2027 .pci_config = qla24xx_pci_config,
2028 .reset_chip = qla24xx_reset_chip,
2029 .chip_diag = qla24xx_chip_diag,
2030 .config_rings = qla24xx_config_rings,
2031 .reset_adapter = qla24xx_reset_adapter,
2032 .nvram_config = qla24xx_nvram_config,
2033 .update_fw_options = qla24xx_update_fw_options,
2034 .load_risc = qla24xx_load_risc,
2035 .pci_info_str = qla24xx_pci_info_str,
2036 .fw_version_str = qla24xx_fw_version_str,
2037 .intr_handler = qla24xx_intr_handler,
2038 .enable_intrs = qla24xx_enable_intrs,
2039 .disable_intrs = qla24xx_disable_intrs,
2040 .abort_command = qla24xx_abort_command,
523ec773
AV		 2041 .target_reset = qla24xx_abort_target,
2042 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2043 .fabric_login = qla24xx_login_fabric,
2044 .fabric_logout = qla24xx_fabric_logout,
2045 .calc_req_entries = NULL,
2046 .build_iocbs = NULL,
2047 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2048 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2049 .read_nvram = qla24xx_read_nvram_data,
2050 .write_nvram = qla24xx_write_nvram_data,
2051 .fw_dump = qla24xx_fw_dump,
2052 .beacon_on = qla24xx_beacon_on,
2053 .beacon_off = qla24xx_beacon_off,
2054 .beacon_blink = qla24xx_beacon_blink,
2055 .read_optrom = qla24xx_read_optrom_data,
2056 .write_optrom = qla24xx_write_optrom_data,
2057 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2058 .start_scsi = qla24xx_start_scsi,
d7459527 2059 .start_scsi_mq = NULL,
a9083016 2060 .abort_isp = qla2x00_abort_isp,
7ec0effd 2061 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2062 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2063};
2064
c3a2f0df
AV		 2065static struct isp_operations qla25xx_isp_ops = {
2066 .pci_config = qla25xx_pci_config,
2067 .reset_chip = qla24xx_reset_chip,
2068 .chip_diag = qla24xx_chip_diag,
2069 .config_rings = qla24xx_config_rings,
2070 .reset_adapter = qla24xx_reset_adapter,
2071 .nvram_config = qla24xx_nvram_config,
2072 .update_fw_options = qla24xx_update_fw_options,
2073 .load_risc = qla24xx_load_risc,
2074 .pci_info_str = qla24xx_pci_info_str,
2075 .fw_version_str = qla24xx_fw_version_str,
2076 .intr_handler = qla24xx_intr_handler,
2077 .enable_intrs = qla24xx_enable_intrs,
2078 .disable_intrs = qla24xx_disable_intrs,
2079 .abort_command = qla24xx_abort_command,
523ec773
AV		 2080 .target_reset = qla24xx_abort_target,
2081 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2082 .fabric_login = qla24xx_login_fabric,
2083 .fabric_logout = qla24xx_fabric_logout,
2084 .calc_req_entries = NULL,
2085 .build_iocbs = NULL,
2086 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2087 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2088 .read_nvram = qla25xx_read_nvram_data,
2089 .write_nvram = qla25xx_write_nvram_data,
2090 .fw_dump = qla25xx_fw_dump,
2091 .beacon_on = qla24xx_beacon_on,
2092 .beacon_off = qla24xx_beacon_off,
2093 .beacon_blink = qla24xx_beacon_blink,
338c9161 2094 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2095 .write_optrom = qla24xx_write_optrom_data,
2096 .get_flash_version = qla24xx_get_flash_version,
bad75002 2097 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2098 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2099 .abort_isp = qla2x00_abort_isp,
7ec0effd 2100 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2101 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2102};
2103
3a03eb79
AV		 2104static struct isp_operations qla81xx_isp_ops = {
2105 .pci_config = qla25xx_pci_config,
2106 .reset_chip = qla24xx_reset_chip,
2107 .chip_diag = qla24xx_chip_diag,
2108 .config_rings = qla24xx_config_rings,
2109 .reset_adapter = qla24xx_reset_adapter,
2110 .nvram_config = qla81xx_nvram_config,
2111 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2112 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2113 .pci_info_str = qla24xx_pci_info_str,
2114 .fw_version_str = qla24xx_fw_version_str,
2115 .intr_handler = qla24xx_intr_handler,
2116 .enable_intrs = qla24xx_enable_intrs,
2117 .disable_intrs = qla24xx_disable_intrs,
2118 .abort_command = qla24xx_abort_command,
2119 .target_reset = qla24xx_abort_target,
2120 .lun_reset = qla24xx_lun_reset,
2121 .fabric_login = qla24xx_login_fabric,
2122 .fabric_logout = qla24xx_fabric_logout,
2123 .calc_req_entries = NULL,
2124 .build_iocbs = NULL,
2125 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2126 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2127 .read_nvram = NULL,
2128 .write_nvram = NULL,
3a03eb79
AV		 2129 .fw_dump = qla81xx_fw_dump,
2130 .beacon_on = qla24xx_beacon_on,
2131 .beacon_off = qla24xx_beacon_off,
6246b8a1 2132 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2133 .read_optrom = qla25xx_read_optrom_data,
2134 .write_optrom = qla24xx_write_optrom_data,
2135 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2136 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2137 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2138 .abort_isp = qla2x00_abort_isp,
7ec0effd 2139 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2140 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2141};
2142
2143static struct isp_operations qla82xx_isp_ops = {
2144 .pci_config = qla82xx_pci_config,
2145 .reset_chip = qla82xx_reset_chip,
2146 .chip_diag = qla24xx_chip_diag,
2147 .config_rings = qla82xx_config_rings,
2148 .reset_adapter = qla24xx_reset_adapter,
2149 .nvram_config = qla81xx_nvram_config,
2150 .update_fw_options = qla24xx_update_fw_options,
2151 .load_risc = qla82xx_load_risc,
9d55ca66 2152 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2153 .fw_version_str = qla24xx_fw_version_str,
2154 .intr_handler = qla82xx_intr_handler,
2155 .enable_intrs = qla82xx_enable_intrs,
2156 .disable_intrs = qla82xx_disable_intrs,
2157 .abort_command = qla24xx_abort_command,
2158 .target_reset = qla24xx_abort_target,
2159 .lun_reset = qla24xx_lun_reset,
2160 .fabric_login = qla24xx_login_fabric,
2161 .fabric_logout = qla24xx_fabric_logout,
2162 .calc_req_entries = NULL,
2163 .build_iocbs = NULL,
2164 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2165 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2166 .read_nvram = qla24xx_read_nvram_data,
2167 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2168 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2169 .beacon_on = qla82xx_beacon_on,
2170 .beacon_off = qla82xx_beacon_off,
2171 .beacon_blink = NULL,
a9083016
GM		 2172 .read_optrom = qla82xx_read_optrom_data,
2173 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2174 .get_flash_version = qla82xx_get_flash_version,
a9083016 2175 .start_scsi = qla82xx_start_scsi,
d7459527 2176 .start_scsi_mq = NULL,
a9083016 2177 .abort_isp = qla82xx_abort_isp,
706f457d 2178 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2179 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2180};
2181
7ec0effd
AD		 2182static struct isp_operations qla8044_isp_ops = {
2183 .pci_config = qla82xx_pci_config,
2184 .reset_chip = qla82xx_reset_chip,
2185 .chip_diag = qla24xx_chip_diag,
2186 .config_rings = qla82xx_config_rings,
2187 .reset_adapter = qla24xx_reset_adapter,
2188 .nvram_config = qla81xx_nvram_config,
2189 .update_fw_options = qla24xx_update_fw_options,
2190 .load_risc = qla82xx_load_risc,
2191 .pci_info_str = qla24xx_pci_info_str,
2192 .fw_version_str = qla24xx_fw_version_str,
2193 .intr_handler = qla8044_intr_handler,
2194 .enable_intrs = qla82xx_enable_intrs,
2195 .disable_intrs = qla82xx_disable_intrs,
2196 .abort_command = qla24xx_abort_command,
2197 .target_reset = qla24xx_abort_target,
2198 .lun_reset = qla24xx_lun_reset,
2199 .fabric_login = qla24xx_login_fabric,
2200 .fabric_logout = qla24xx_fabric_logout,
2201 .calc_req_entries = NULL,
2202 .build_iocbs = NULL,
2203 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2204 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2205 .read_nvram = NULL,
2206 .write_nvram = NULL,
a1b23c5a 2207 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2208 .beacon_on = qla82xx_beacon_on,
2209 .beacon_off = qla82xx_beacon_off,
2210 .beacon_blink = NULL,
888e639d 2211 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2212 .write_optrom = qla8044_write_optrom_data,
2213 .get_flash_version = qla82xx_get_flash_version,
2214 .start_scsi = qla82xx_start_scsi,
d7459527 2215 .start_scsi_mq = NULL,
7ec0effd
AD		 2216 .abort_isp = qla8044_abort_isp,
2217 .iospace_config = qla82xx_iospace_config,
2218 .initialize_adapter = qla2x00_initialize_adapter,
2219};
2220
6246b8a1
GM		 2221static struct isp_operations qla83xx_isp_ops = {
2222 .pci_config = qla25xx_pci_config,
2223 .reset_chip = qla24xx_reset_chip,
2224 .chip_diag = qla24xx_chip_diag,
2225 .config_rings = qla24xx_config_rings,
2226 .reset_adapter = qla24xx_reset_adapter,
2227 .nvram_config = qla81xx_nvram_config,
2228 .update_fw_options = qla81xx_update_fw_options,
2229 .load_risc = qla81xx_load_risc,
2230 .pci_info_str = qla24xx_pci_info_str,
2231 .fw_version_str = qla24xx_fw_version_str,
2232 .intr_handler = qla24xx_intr_handler,
2233 .enable_intrs = qla24xx_enable_intrs,
2234 .disable_intrs = qla24xx_disable_intrs,
2235 .abort_command = qla24xx_abort_command,
2236 .target_reset = qla24xx_abort_target,
2237 .lun_reset = qla24xx_lun_reset,
2238 .fabric_login = qla24xx_login_fabric,
2239 .fabric_logout = qla24xx_fabric_logout,
2240 .calc_req_entries = NULL,
2241 .build_iocbs = NULL,
2242 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2243 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2244 .read_nvram = NULL,
2245 .write_nvram = NULL,
2246 .fw_dump = qla83xx_fw_dump,
2247 .beacon_on = qla24xx_beacon_on,
2248 .beacon_off = qla24xx_beacon_off,
2249 .beacon_blink = qla83xx_beacon_blink,
2250 .read_optrom = qla25xx_read_optrom_data,
2251 .write_optrom = qla24xx_write_optrom_data,
2252 .get_flash_version = qla24xx_get_flash_version,
2253 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2254 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2255 .abort_isp = qla2x00_abort_isp,
2256 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2257 .initialize_adapter = qla2x00_initialize_adapter,
2258};
2259
2260static struct isp_operations qlafx00_isp_ops = {
2261 .pci_config = qlafx00_pci_config,
2262 .reset_chip = qlafx00_soft_reset,
2263 .chip_diag = qlafx00_chip_diag,
2264 .config_rings = qlafx00_config_rings,
2265 .reset_adapter = qlafx00_soft_reset,
2266 .nvram_config = NULL,
2267 .update_fw_options = NULL,
2268 .load_risc = NULL,
2269 .pci_info_str = qlafx00_pci_info_str,
2270 .fw_version_str = qlafx00_fw_version_str,
2271 .intr_handler = qlafx00_intr_handler,
2272 .enable_intrs = qlafx00_enable_intrs,
2273 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2274 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2275 .target_reset = qlafx00_abort_target,
2276 .lun_reset = qlafx00_lun_reset,
2277 .fabric_login = NULL,
2278 .fabric_logout = NULL,
2279 .calc_req_entries = NULL,
2280 .build_iocbs = NULL,
2281 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2282 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2283 .read_nvram = qla24xx_read_nvram_data,
2284 .write_nvram = qla24xx_write_nvram_data,
2285 .fw_dump = NULL,
2286 .beacon_on = qla24xx_beacon_on,
2287 .beacon_off = qla24xx_beacon_off,
2288 .beacon_blink = NULL,
2289 .read_optrom = qla24xx_read_optrom_data,
2290 .write_optrom = qla24xx_write_optrom_data,
2291 .get_flash_version = qla24xx_get_flash_version,
2292 .start_scsi = qlafx00_start_scsi,
d7459527 2293 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2294 .abort_isp = qlafx00_abort_isp,
2295 .iospace_config = qlafx00_iospace_config,
2296 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2297};
2298
f73cb695
CD		 2299static struct isp_operations qla27xx_isp_ops = {
2300 .pci_config = qla25xx_pci_config,
2301 .reset_chip = qla24xx_reset_chip,
2302 .chip_diag = qla24xx_chip_diag,
2303 .config_rings = qla24xx_config_rings,
2304 .reset_adapter = qla24xx_reset_adapter,
2305 .nvram_config = qla81xx_nvram_config,
2306 .update_fw_options = qla81xx_update_fw_options,
2307 .load_risc = qla81xx_load_risc,
2308 .pci_info_str = qla24xx_pci_info_str,
2309 .fw_version_str = qla24xx_fw_version_str,
2310 .intr_handler = qla24xx_intr_handler,
2311 .enable_intrs = qla24xx_enable_intrs,
2312 .disable_intrs = qla24xx_disable_intrs,
2313 .abort_command = qla24xx_abort_command,
2314 .target_reset = qla24xx_abort_target,
2315 .lun_reset = qla24xx_lun_reset,
2316 .fabric_login = qla24xx_login_fabric,
2317 .fabric_logout = qla24xx_fabric_logout,
2318 .calc_req_entries = NULL,
2319 .build_iocbs = NULL,
2320 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2321 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2322 .read_nvram = NULL,
2323 .write_nvram = NULL,
2324 .fw_dump = qla27xx_fwdump,
2325 .beacon_on = qla24xx_beacon_on,
2326 .beacon_off = qla24xx_beacon_off,
2327 .beacon_blink = qla83xx_beacon_blink,
2328 .read_optrom = qla25xx_read_optrom_data,
2329 .write_optrom = qla24xx_write_optrom_data,
2330 .get_flash_version = qla24xx_get_flash_version,
2331 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2332 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2333 .abort_isp = qla2x00_abort_isp,
2334 .iospace_config = qla83xx_iospace_config,
2335 .initialize_adapter = qla2x00_initialize_adapter,
2336};
2337
ea5b6382 2338static inline void
e315cd28 2339qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2340{
2341 ha->device_type = DT_EXTENDED_IDS;
2342 switch (ha->pdev->device) {
2343 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2344 ha->isp_type |= DT_ISP2100;
ea5b6382 2345 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2346 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2347 break;
2348 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2349 ha->isp_type |= DT_ISP2200;
ea5b6382 2350 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2351 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2352 break;
2353 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2354 ha->isp_type |= DT_ISP2300;
4a59f71d 2355 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2356 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2357 break;
2358 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2359 ha->isp_type |= DT_ISP2312;
4a59f71d 2360 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2361 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2362 break;
2363 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2364 ha->isp_type |= DT_ISP2322;
4a59f71d 2365 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2366 if (ha->pdev->subsystem_vendor == 0x1028 &&
2367 ha->pdev->subsystem_device == 0x0170)
2368 ha->device_type |= DT_OEM_001;
441d1072 2369 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2370 break;
2371 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2372 ha->isp_type |= DT_ISP6312;
441d1072 2373 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2374 break;
2375 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2376 ha->isp_type |= DT_ISP6322;
441d1072 2377 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2378 break;
2379 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2380 ha->isp_type |= DT_ISP2422;
4a59f71d 2381 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2382 ha->device_type |= DT_FWI2;
c76f2c01 2383 ha->device_type |= DT_IIDMA;
441d1072 2384 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2385 break;
2386 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2387 ha->isp_type |= DT_ISP2432;
4a59f71d 2388 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2389 ha->device_type |= DT_FWI2;
c76f2c01 2390 ha->device_type |= DT_IIDMA;
441d1072 2391 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2392 break;
4d4df193 2393 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2394 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2395 ha->device_type |= DT_ZIO_SUPPORTED;
2396 ha->device_type |= DT_FWI2;
2397 ha->device_type |= DT_IIDMA;
2398 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2399 break;
044cc6c8 2400 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2401 ha->isp_type |= DT_ISP5422;
e428924c 2402 ha->device_type |= DT_FWI2;
441d1072 2403 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2404 break;
044cc6c8 2405 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2406 ha->isp_type |= DT_ISP5432;
e428924c 2407 ha->device_type |= DT_FWI2;
441d1072 2408 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2409 break;
c3a2f0df 2410 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2411 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2412 ha->device_type |= DT_ZIO_SUPPORTED;
2413 ha->device_type |= DT_FWI2;
2414 ha->device_type |= DT_IIDMA;
441d1072 2415 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2416 break;
3a03eb79 2417 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2418 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2419 ha->device_type |= DT_ZIO_SUPPORTED;
2420 ha->device_type |= DT_FWI2;
2421 ha->device_type |= DT_IIDMA;
2422 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2423 break;
a9083016 2424 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2425 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2426 ha->device_type |= DT_ZIO_SUPPORTED;
2427 ha->device_type |= DT_FWI2;
2428 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2429 /* Initialize 82XX ISP flags */
2430 qla82xx_init_flags(ha);
2431 break;
7ec0effd 2432 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2433 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2434 ha->device_type |= DT_ZIO_SUPPORTED;
2435 ha->device_type |= DT_FWI2;
2436 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2437 /* Initialize 82XX ISP flags */
2438 qla82xx_init_flags(ha);
2439 break;
6246b8a1 2440 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2441 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2442 ha->device_type |= DT_ZIO_SUPPORTED;
2443 ha->device_type |= DT_FWI2;
2444 ha->device_type |= DT_IIDMA;
2445 ha->device_type |= DT_T10_PI;
2446 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2447 break;
2448 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2449 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2450 ha->device_type |= DT_ZIO_SUPPORTED;
2451 ha->device_type |= DT_FWI2;
2452 ha->device_type |= DT_IIDMA;
2453 ha->device_type |= DT_T10_PI;
2454 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2455 break;
8ae6d9c7 2456 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2457 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2458 break;
f73cb695 2459 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2460 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2461 ha->device_type |= DT_ZIO_SUPPORTED;
2462 ha->device_type |= DT_FWI2;
2463 ha->device_type |= DT_IIDMA;
8ce3f570 2464 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2465 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2466 break;
2c5bbbb2 2467 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2468 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2469 ha->device_type |= DT_ZIO_SUPPORTED;
2470 ha->device_type |= DT_FWI2;
2471 ha->device_type |= DT_IIDMA;
8ce3f570 2472 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2473 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2474 break;
2b48992f 2475 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2476 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2477 ha->device_type |= DT_ZIO_SUPPORTED;
2478 ha->device_type |= DT_FWI2;
2479 ha->device_type |= DT_IIDMA;
8ce3f570 2480 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2481 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2482 break;
ea5b6382 2483 }
e5b68a61 2484
a9083016 2485 if (IS_QLA82XX(ha))
43a9c38b 2486 ha->port_no = ha->portnum & 1;
f73cb695 2487 else {
a9083016
GM		 2488 /* Get adapter physical port no from interrupt pin register. */
2489 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2490 if (IS_QLA27XX(ha))
2491 ha->port_no--;
2492 else
2493 ha->port_no = !(ha->port_no & 1);
2494 }
a9083016 2495
7c3df132 2496 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2497 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2498 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2499}
2500
1e99e33a
AV		 2501static void
2502qla2xxx_scan_start(struct Scsi_Host *shost)
2503{
e315cd28 2504 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2505
cbc8eb67
AV		 2506 if (vha->hw->flags.running_gold_fw)
2507 return;
2508
e315cd28
AC		 2509 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2510 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2511 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2512 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2513}
2514
2515static int
2516qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2517{
e315cd28 2518 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2519
a5dd506e
BK		 2520 if (test_bit(UNLOADING, &vha->dpc_flags))
2521 return 1;
e315cd28 2522 if (!vha->host)
1e99e33a 2523 return 1;
e315cd28 2524 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2525 return 1;
2526
e315cd28 2527 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2528}
2529
1da177e4
LT		 2530/*
2531 * PCI driver interface
2532 */
6f039790 2533static int
7ee61397 2534qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2535{
a1541d5a 2536 int ret = -ENODEV;
1da177e4 2537 struct Scsi_Host *host;
e315cd28
AC		 2538 scsi_qla_host_t *base_vha = NULL;
2539 struct qla_hw_data *ha;
29856e28 2540 char pci_info[30];
7d613ac6 2541 char fw_str[30], wq_name[30];
5433383e 2542 struct scsi_host_template *sht;
642ef983 2543 int bars, mem_only = 0;
e315cd28 2544 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2545 struct req_que *req = NULL;
2546 struct rsp_que *rsp = NULL;
5601236b 2547 int i;
d7459527 2548
285d0321 2549 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2550 sht = &qla2xxx_driver_template;
5433383e 2551 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2552 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2553 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2554 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2555 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2556 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2557 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2558 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2559 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2560 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2561 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2562 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2563 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2564 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2565 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2566 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2567 mem_only = 1;
7c3df132
SK		 2568 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2569 "Mem only adapter.\n");
285d0321 2570 }
7c3df132
SK		 2571 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2572 "Bars=%d.\n", bars);
285d0321 2573
09483916
BH		 2574 if (mem_only) {
2575 if (pci_enable_device_mem(pdev))
2576 goto probe_out;
2577 } else {
2578 if (pci_enable_device(pdev))
2579 goto probe_out;
2580 }
285d0321 2581
0927678f
JB		 2582 /* This may fail but that's ok */
2583 pci_enable_pcie_error_reporting(pdev);
285d0321 2584
e315cd28
AC		 2585 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2586 if (!ha) {
7c3df132
SK		 2587 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2588 "Unable to allocate memory for ha.\n");
e315cd28 2589 goto probe_out;
1da177e4 2590 }
7c3df132
SK		 2591 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2592 "Memory allocated for ha=%p.\n", ha);
e315cd28 2593 ha->pdev = pdev;
2d70c103 2594 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2595 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2596 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2597 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2598 spin_lock_init(&ha->tgt.atio_lock);
2599
1da177e4
LT		 2600
2601 /* Clear our data area */
285d0321 2602 ha->bars = bars;
09483916 2603 ha->mem_only = mem_only;
df4bf0bb 2604 spin_lock_init(&ha->hardware_lock);
339aa70e 2605 spin_lock_init(&ha->vport_slock);
a9b6f722 2606 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2607 mutex_init(&ha->optrom_mutex);
1da177e4 2608
ea5b6382
AV		 2609 /* Set ISP-type information. */
2610 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2611
2612 /* Set EEH reset type to fundamental if required by hba */
95676112 2613 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2614 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2615 pdev->needs_freset = 1;
ca79cf66 2616
cba1e47f
CD		 2617 ha->prev_topology = 0;
2618 ha->init_cb_size = sizeof(init_cb_t);
2619 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2620 ha->optrom_size = OPTROM_SIZE_2300;
2621
abbd8870 2622 /* Assign ISP specific operations. */
1da177e4 2623 if (IS_QLA2100(ha)) {
642ef983 2624 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2625 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2626 req_length = REQUEST_ENTRY_CNT_2100;
2627 rsp_length = RESPONSE_ENTRY_CNT_2100;
2628 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2629 ha->gid_list_info_size = 4;
3a03eb79
AV		 2630 ha->flash_conf_off = ~0;
2631 ha->flash_data_off = ~0;
2632 ha->nvram_conf_off = ~0;
2633 ha->nvram_data_off = ~0;
fd34f556 2634 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2635 } else if (IS_QLA2200(ha)) {
642ef983 2636 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2637 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2638 req_length = REQUEST_ENTRY_CNT_2200;
2639 rsp_length = RESPONSE_ENTRY_CNT_2100;
2640 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2641 ha->gid_list_info_size = 4;
3a03eb79
AV		 2642 ha->flash_conf_off = ~0;
2643 ha->flash_data_off = ~0;
2644 ha->nvram_conf_off = ~0;
2645 ha->nvram_data_off = ~0;
fd34f556 2646 ha->isp_ops = &qla2100_isp_ops;
fca29703 2647 } else if (IS_QLA23XX(ha)) {
642ef983 2648 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2649 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2650 req_length = REQUEST_ENTRY_CNT_2200;
2651 rsp_length = RESPONSE_ENTRY_CNT_2300;
2652 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2653 ha->gid_list_info_size = 6;
854165f4
AV		 2654 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2655 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2656 ha->flash_conf_off = ~0;
2657 ha->flash_data_off = ~0;
2658 ha->nvram_conf_off = ~0;
2659 ha->nvram_data_off = ~0;
fd34f556 2660 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2661 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2662 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2663 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2664 req_length = REQUEST_ENTRY_CNT_24XX;
2665 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2666 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2667 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2668 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2669 ha->gid_list_info_size = 8;
854165f4 2670 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2671 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2672 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2673 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2674 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2675 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2676 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2677 } else if (IS_QLA25XX(ha)) {
642ef983 2678 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2679 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2680 req_length = REQUEST_ENTRY_CNT_24XX;
2681 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2682 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2683 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2684 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2685 ha->gid_list_info_size = 8;
2686 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2687 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2688 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2689 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2690 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2691 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2692 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2693 } else if (IS_QLA81XX(ha)) {
642ef983 2694 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2695 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2696 req_length = REQUEST_ENTRY_CNT_24XX;
2697 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2698 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2699 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2700 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2701 ha->gid_list_info_size = 8;
2702 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2703 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2704 ha->isp_ops = &qla81xx_isp_ops;
2705 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2706 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2707 ha->nvram_conf_off = ~0;
2708 ha->nvram_data_off = ~0;
a9083016 2709 } else if (IS_QLA82XX(ha)) {
642ef983 2710 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2711 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2712 req_length = REQUEST_ENTRY_CNT_82XX;
2713 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2714 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2715 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2716 ha->gid_list_info_size = 8;
2717 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2718 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2719 ha->isp_ops = &qla82xx_isp_ops;
2720 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2721 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2722 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2723 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2724 } else if (IS_QLA8044(ha)) {
2725 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2726 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2727 req_length = REQUEST_ENTRY_CNT_82XX;
2728 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2729 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2730 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2731 ha->gid_list_info_size = 8;
2732 ha->optrom_size = OPTROM_SIZE_83XX;
2733 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2734 ha->isp_ops = &qla8044_isp_ops;
2735 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2736 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2737 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2738 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2739 } else if (IS_QLA83XX(ha)) {
7d613ac6 2740 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2741 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2742 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2743 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2744 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2745 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2746 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2747 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2748 ha->gid_list_info_size = 8;
2749 ha->optrom_size = OPTROM_SIZE_83XX;
2750 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2751 ha->isp_ops = &qla83xx_isp_ops;
2752 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2753 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2754 ha->nvram_conf_off = ~0;
2755 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2756 } else if (IS_QLAFX00(ha)) {
2757 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2758 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2759 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2760 req_length = REQUEST_ENTRY_CNT_FX00;
2761 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2762 ha->isp_ops = &qlafx00_isp_ops;
2763 ha->port_down_retry_count = 30; /* default value */
2764 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2765 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2766 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2767 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2768 ha->mr.host_info_resend = false;
2769 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2770 } else if (IS_QLA27XX(ha)) {
2771 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2772 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2773 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2774 req_length = REQUEST_ENTRY_CNT_83XX;
2775 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2776 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2777 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2778 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2779 ha->gid_list_info_size = 8;
2780 ha->optrom_size = OPTROM_SIZE_83XX;
2781 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2782 ha->isp_ops = &qla27xx_isp_ops;
2783 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2784 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2785 ha->nvram_conf_off = ~0;
2786 ha->nvram_data_off = ~0;
1da177e4 2787 }
6246b8a1 2788
7c3df132
SK		 2789 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2790 "mbx_count=%d, req_length=%d, "
2791 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2792 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2793 "max_fibre_devices=%d.\n",
7c3df132
SK		 2794 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2795 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2796 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2797 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2798 "isp_ops=%p, flash_conf_off=%d, "
2799 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2800 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2801 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2802
2803 /* Configure PCI I/O space */
2804 ret = ha->isp_ops->iospace_config(ha);
2805 if (ret)
0a63ad12 2806 goto iospace_config_failed;
706f457d
GM		 2807
2808 ql_log_pci(ql_log_info, pdev, 0x001d,
2809 "Found an ISP%04X irq %d iobase 0x%p.\n",
2810 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2811 mutex_init(&ha->vport_lock);
d7459527 2812 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2813 init_completion(&ha->mbx_cmd_comp);
2814 complete(&ha->mbx_cmd_comp);
2815 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2816 init_completion(&ha->dcbx_comp);
f356bef1 2817 init_completion(&ha->lb_portup_comp);
1da177e4 2818
2c3dfe3f 2819 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2820
53303c42 2821 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2822 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2823 "64 Bit addressing is %s.\n",
2824 ha->flags.enable_64bit_addressing ? "enable" :
2825 "disable");
73208dfd 2826 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2827 if (ret) {
7c3df132
SK		 2828 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2829 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2830
e315cd28
AC		 2831 goto probe_hw_failed;
2832 }
2833
73208dfd 2834 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2835 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2836 req->max_q_depth = ql2xmaxqdepth;
2837
e315cd28
AC		 2838
2839 base_vha = qla2x00_create_host(sht, ha);
2840 if (!base_vha) {
a1541d5a 2841 ret = -ENOMEM;
6e9f21f3 2842 qla2x00_mem_free(ha);
2afa19a9
AC		 2843 qla2x00_free_req_que(ha, req);
2844 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2845 goto probe_hw_failed;
1da177e4
LT		 2846 }
2847
e315cd28 2848 pci_set_drvdata(pdev, base_vha);
6b383979 2849 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2850
e315cd28 2851 host = base_vha->host;
2afa19a9 2852 base_vha->req = req;
73208dfd 2853 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2854 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2855 else
e315cd28
AC		 2856 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2857 base_vha->vp_idx;
58548cb5 2858
8ae6d9c7
GM		 2859 /* Setup fcport template structure. */
2860 ha->mr.fcport.vha = base_vha;
2861 ha->mr.fcport.port_type = FCT_UNKNOWN;
2862 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2863 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2864 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2865 ha->mr.fcport.scan_state = 1;
2866
58548cb5
GM		 2867 /* Set the SG table size based on ISP type */
2868 if (!IS_FWI2_CAPABLE(ha)) {
2869 if (IS_QLA2100(ha))
2870 host->sg_tablesize = 32;
2871 } else {
2872 if (!IS_QLA82XX(ha))
2873 host->sg_tablesize = QLA_SG_ALL;
2874 }
642ef983 2875 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2876 host->cmd_per_lun = 3;
2877 host->unique_id = host->host_no;
e02587d7 2878 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2879 host->max_cmd_len = 32;
2880 else
2881 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2882 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2883 /* Older HBAs support only 16-bit LUNs */
2884 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2885 ql2xmaxlun > 0xffff)
2886 host->max_lun = 0xffff;
2887 else
2888 host->max_lun = ql2xmaxlun;
e315cd28 2889 host->transportt = qla2xxx_transport_template;
9a069e19 2890 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2891
7c3df132
SK		 2892 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2893 "max_id=%d this_id=%d "
2894 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2895 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2896 host->this_id, host->cmd_per_lun, host->unique_id,
2897 host->max_cmd_len, host->max_channel, host->max_lun,
2898 host->transportt, sht->vendor_id);
2899
d7459527
MH		 2900 /* Set up the irqs */
2901 ret = qla2x00_request_irqs(ha, rsp);
2902 if (ret)
2903 goto probe_init_failed;
2904
9a347ff4
CD		 2905 /* Alloc arrays of request and response ring ptrs */
2906 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2907 ql_log(ql_log_fatal, base_vha, 0x003d,
2908 "Failed to allocate memory for queue pointers..."
2909 "aborting.\n");
2910 goto probe_init_failed;
2911 }
2912
5601236b
MH		 2913 if (ha->mqenable && shost_use_blk_mq(host)) {
2914 /* number of hardware queues supported by blk/scsi-mq*/
2915 host->nr_hw_queues = ha->max_qpairs;
2916
2917 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2918 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2919 } else
2920 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2921 "blk/scsi-mq disabled.\n");
2922
2d70c103 2923 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2924
90a86fc0
JC		 2925 pci_save_state(pdev);
2926
9a347ff4 2927 /* Assign back pointers */
2afa19a9
AC		 2928 rsp->req = req;
2929 req->rsp = rsp;
9a347ff4 2930
8ae6d9c7
GM		 2931 if (IS_QLAFX00(ha)) {
2932 ha->rsp_q_map[0] = rsp;
2933 ha->req_q_map[0] = req;
2934 set_bit(0, ha->req_qid_map);
2935 set_bit(0, ha->rsp_qid_map);
2936 }
2937
08029990
AV		 2938 /* FWI2-capable only. */
2939 req->req_q_in = &ha->iobase->isp24.req_q_in;
2940 req->req_q_out = &ha->iobase->isp24.req_q_out;
2941 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2942 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2943 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2944 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2945 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2946 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2947 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2948 }
2949
8ae6d9c7
GM		 2950 if (IS_QLAFX00(ha)) {
2951 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2952 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2953 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2954 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2955 }
2956
7ec0effd 2957 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2958 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2959 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2960 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2961 }
2962
7c3df132
SK		 2963 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2964 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2965 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2966 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2967 "req->req_q_in=%p req->req_q_out=%p "
2968 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2969 req->req_q_in, req->req_q_out,
2970 rsp->rsp_q_in, rsp->rsp_q_out);
2971 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2972 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2973 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2974 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2975 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2976 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2977
8ae6d9c7 2978 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2979 ql_log(ql_log_fatal, base_vha, 0x00d6,
2980 "Failed to initialize adapter - Adapter flags %x.\n",
2981 base_vha->device_flags);
1da177e4 2982
a9083016
GM		 2983 if (IS_QLA82XX(ha)) {
2984 qla82xx_idc_lock(ha);
2985 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2986 QLA8XXX_DEV_FAILED);
a9083016 2987 qla82xx_idc_unlock(ha);
7c3df132
SK		 2988 ql_log(ql_log_fatal, base_vha, 0x00d7,
2989 "HW State: FAILED.\n");
7ec0effd
AD		 2990 } else if (IS_QLA8044(ha)) {
2991 qla8044_idc_lock(ha);
2992 qla8044_wr_direct(base_vha,
2993 QLA8044_CRB_DEV_STATE_INDEX,
2994 QLA8XXX_DEV_FAILED);
2995 qla8044_idc_unlock(ha);
2996 ql_log(ql_log_fatal, base_vha, 0x0150,
2997 "HW State: FAILED.\n");
a9083016
GM		 2998 }
2999
a1541d5a 3000 ret = -ENODEV;
1da177e4
LT		 3001 goto probe_failed;
3002 }
3003
3b1bef64
CD		 3004 if (IS_QLAFX00(ha))
3005 host->can_queue = QLAFX00_MAX_CANQUEUE;
3006 else
3007 host->can_queue = req->num_outstanding_cmds - 10;
3008
3009 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3010 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3011 host->can_queue, base_vha->req,
3012 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3013
093df737 3014 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3015 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3016 /* Create start of day qpairs for Block MQ */
3017 if (shost_use_blk_mq(host)) {
3018 for (i = 0; i < ha->max_qpairs; i++)
3019 qla2xxx_create_qpair(base_vha, 5, 0);
3020 }
3021 }
68ca949c 3022
cbc8eb67
AV		 3023 if (ha->flags.running_gold_fw)
3024 goto skip_dpc;
3025
1da177e4
LT		 3026 /*
3027 * Startup the kernel thread for this host adapter
3028 */
39a11240 3029 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3030 "%s_dpc", base_vha->host_str);
39a11240 3031 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3032 ql_log(ql_log_fatal, base_vha, 0x00ed,
3033 "Failed to start DPC thread.\n");
39a11240 3034 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3035 goto probe_failed;
3036 }
7c3df132
SK		 3037 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3038 "DPC thread started successfully.\n");
1da177e4 3039
2d70c103
NB		 3040 /*
3041 * If we're not coming up in initiator mode, we might sit for
3042 * a while without waking up the dpc thread, which leads to a
3043 * stuck process warning. So just kick the dpc once here and
3044 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3045 */
3046 qla2xxx_wake_dpc(base_vha);
3047
f3ddac19
CD		 3048 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3049
81178772
SK		 3050 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3051 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3052 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3053 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3054
3055 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3056 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3057 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3058 INIT_WORK(&ha->idc_state_handler,
3059 qla83xx_idc_state_handler_work);
3060 INIT_WORK(&ha->nic_core_unrecoverable,
3061 qla83xx_nic_core_unrecoverable_work);
3062 }
3063
cbc8eb67 3064skip_dpc:
e315cd28
AC		 3065 list_add_tail(&base_vha->list, &ha->vp_list);
3066 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3067
3068 /* Initialized the timer */
e315cd28 3069 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3070 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3071 "Started qla2x00_timer with "
3072 "interval=%d.\n", WATCH_INTERVAL);
3073 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3074 "Detected hba at address=%p.\n",
3075 ha);
d19044c3 3076
e02587d7 3077 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3078 if (ha->fw_attributes & BIT_4) {
9e522cd8 3079 int prot = 0, guard;
bad75002 3080 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3081 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3082 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3083 if (ql2xenabledif == 1)
3084 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3085 scsi_host_set_prot(host,
8cb2049c 3086 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3087 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3088 | SHOST_DIF_TYPE3_PROTECTION
3089 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3090 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3091 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3092
3093 guard = SHOST_DIX_GUARD_CRC;
3094
3095 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3096 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3097 guard |= SHOST_DIX_GUARD_IP;
3098
3099 scsi_host_set_guard(host, guard);
bad75002
AE		 3100 } else
3101 base_vha->flags.difdix_supported = 0;
3102 }
3103
a9083016
GM		 3104 ha->isp_ops->enable_intrs(ha);
3105
1fe19ee4
AB		 3106 if (IS_QLAFX00(ha)) {
3107 ret = qlafx00_fx_disc(base_vha,
3108 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3109 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3110 QLA_SG_ALL : 128;
3111 }
3112
a1541d5a
AV		 3113 ret = scsi_add_host(host, &pdev->dev);
3114 if (ret)
3115 goto probe_failed;
3116
1486400f
MR		 3117 base_vha->flags.init_done = 1;
3118 base_vha->flags.online = 1;
edaa5c74 3119 ha->prev_minidump_failed = 0;
1486400f 3120
7c3df132
SK		 3121 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3122 "Init done and hba is online.\n");
3123
2d70c103
NB		 3124 if (qla_ini_mode_enabled(base_vha))
3125 scsi_scan_host(host);
3126 else
3127 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3128 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3129
e315cd28 3130 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3131
8ae6d9c7 3132 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3133 ret = qlafx00_fx_disc(base_vha,
3134 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3135
3136 /* Register system information */
3137 ret = qlafx00_fx_disc(base_vha,
3138 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3139 }
3140
e315cd28 3141 qla2x00_init_host_attr(base_vha);
a1541d5a 3142
e315cd28 3143 qla2x00_dfs_setup(base_vha);
df613b96 3144
03eb912a
AB		 3145 ql_log(ql_log_info, base_vha, 0x00fb,
3146 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3147 ql_log(ql_log_info, base_vha, 0x00fc,
3148 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3149 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3150 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3151 base_vha->host_no,
df57caba 3152 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3153
2d70c103
NB		 3154 qlt_add_target(ha, base_vha);
3155
6b383979 3156 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3157
3158 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3159 return -ENODEV;
3160
1da177e4
LT		 3161 return 0;
3162
6e9f21f3 3163probe_init_failed:
2afa19a9 3164 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3165 ha->req_q_map[0] = NULL;
3166 clear_bit(0, ha->req_qid_map);
2afa19a9 3167 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3168 ha->rsp_q_map[0] = NULL;
3169 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3170 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3171
1da177e4 3172probe_failed:
b9978769
AV		 3173 if (base_vha->timer_active)
3174 qla2x00_stop_timer(base_vha);
3175 base_vha->flags.online = 0;
3176 if (ha->dpc_thread) {
3177 struct task_struct *t = ha->dpc_thread;
3178
3179 ha->dpc_thread = NULL;
3180 kthread_stop(t);
3181 }
3182
e315cd28 3183 qla2x00_free_device(base_vha);
1da177e4 3184
e315cd28 3185 scsi_host_put(base_vha->host);
1da177e4 3186
e315cd28 3187probe_hw_failed:
1a2fbf18
JL		 3188 qla2x00_clear_drv_active(ha);
3189
0a63ad12 3190iospace_config_failed:
7ec0effd 3191 if (IS_P3P_TYPE(ha)) {
0a63ad12 3192 if (!ha->nx_pcibase)
f73cb695 3193 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3194 if (!ql2xdbwr)
f73cb695 3195 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3196 } else {
3197 if (ha->iobase)
3198 iounmap(ha->iobase);
8ae6d9c7
GM		 3199 if (ha->cregbase)
3200 iounmap(ha->cregbase);
a9083016 3201 }
e315cd28
AC		 3202 pci_release_selected_regions(ha->pdev, ha->bars);
3203 kfree(ha);
3204 ha = NULL;
1da177e4 3205
a1541d5a 3206probe_out:
e315cd28 3207 pci_disable_device(pdev);
a1541d5a 3208 return ret;
1da177e4 3209}
1da177e4 3210
e30d1756
MI		 3211static void
3212qla2x00_shutdown(struct pci_dev *pdev)
3213{
3214 scsi_qla_host_t *vha;
3215 struct qla_hw_data *ha;
3216
552f3f9a
MI		 3217 if (!atomic_read(&pdev->enable_cnt))
3218 return;
3219
e30d1756
MI		 3220 vha = pci_get_drvdata(pdev);
3221 ha = vha->hw;
3222
42479343
AB		 3223 /* Notify ISPFX00 firmware */
3224 if (IS_QLAFX00(ha))
3225 qlafx00_driver_shutdown(vha, 20);
3226
e30d1756
MI		 3227 /* Turn-off FCE trace */
3228 if (ha->flags.fce_enabled) {
3229 qla2x00_disable_fce_trace(vha, NULL, NULL);
3230 ha->flags.fce_enabled = 0;
3231 }
3232
3233 /* Turn-off EFT trace */
3234 if (ha->eft)
3235 qla2x00_disable_eft_trace(vha);
3236
3237 /* Stop currently executing firmware. */
3238 qla2x00_try_to_stop_firmware(vha);
3239
3240 /* Turn adapter off line */
3241 vha->flags.online = 0;
3242
3243 /* turn-off interrupts on the card */
3244 if (ha->interrupts_on) {
3245 vha->flags.init_done = 0;
3246 ha->isp_ops->disable_intrs(ha);
3247 }
3248
3249 qla2x00_free_irqs(vha);
3250
3251 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3252
3253 pci_disable_pcie_error_reporting(pdev);
3254 pci_disable_device(pdev);
e30d1756
MI		 3255}
3256
fe1b806f 3257/* Deletes all the virtual ports for a given ha */
4c993f76 3258static void
fe1b806f 3259qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3260{
fe1b806f 3261 scsi_qla_host_t *vha;
feafb7b1 3262 unsigned long flags;
e315cd28 3263
43ebf16d
AE		 3264 mutex_lock(&ha->vport_lock);
3265 while (ha->cur_vport_count) {
43ebf16d 3266 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3267
43ebf16d
AE		 3268 BUG_ON(base_vha->list.next == &ha->vp_list);
3269 /* This assumes first entry in ha->vp_list is always base vha */
3270 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3271 scsi_host_get(vha->host);
feafb7b1 3272
43ebf16d
AE		 3273 spin_unlock_irqrestore(&ha->vport_slock, flags);
3274 mutex_unlock(&ha->vport_lock);
3275
3276 fc_vport_terminate(vha->fc_vport);
3277 scsi_host_put(vha->host);
feafb7b1 3278
43ebf16d 3279 mutex_lock(&ha->vport_lock);
e315cd28 3280 }
43ebf16d 3281 mutex_unlock(&ha->vport_lock);
fe1b806f 3282}
1da177e4 3283
fe1b806f
CD		 3284/* Stops all deferred work threads */
3285static void
3286qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3287{
7d613ac6
SV		 3288 /* Cancel all work and destroy DPC workqueues */
3289 if (ha->dpc_lp_wq) {
3290 cancel_work_sync(&ha->idc_aen);
3291 destroy_workqueue(ha->dpc_lp_wq);
3292 ha->dpc_lp_wq = NULL;
3293 }
3294
3295 if (ha->dpc_hp_wq) {
3296 cancel_work_sync(&ha->nic_core_reset);
3297 cancel_work_sync(&ha->idc_state_handler);
3298 cancel_work_sync(&ha->nic_core_unrecoverable);
3299 destroy_workqueue(ha->dpc_hp_wq);
3300 ha->dpc_hp_wq = NULL;
3301 }
3302
b9978769
AV		 3303 /* Kill the kernel thread for this host */
3304 if (ha->dpc_thread) {
3305 struct task_struct *t = ha->dpc_thread;
3306
3307 /*
3308 * qla2xxx_wake_dpc checks for ->dpc_thread
3309 * so we need to zero it out.
3310 */
3311 ha->dpc_thread = NULL;
3312 kthread_stop(t);
3313 }
fe1b806f 3314}
1da177e4 3315
fe1b806f
CD		 3316static void
3317qla2x00_unmap_iobases(struct qla_hw_data *ha)
3318{
a9083016 3319 if (IS_QLA82XX(ha)) {
b963752f 3320
f73cb695 3321 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3322 if (!ql2xdbwr)
f73cb695 3323 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3324 } else {
3325 if (ha->iobase)
3326 iounmap(ha->iobase);
1da177e4 3327
8ae6d9c7
GM		 3328 if (ha->cregbase)
3329 iounmap(ha->cregbase);
3330
a9083016
GM		 3331 if (ha->mqiobase)
3332 iounmap(ha->mqiobase);
6246b8a1 3333
f73cb695 3334 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3335 iounmap(ha->msixbase);
a9083016 3336 }
fe1b806f
CD		 3337}
3338
3339static void
db7157d4 3340qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3341{
fe1b806f
CD		 3342 if (IS_QLA8044(ha)) {
3343 qla8044_idc_lock(ha);
c41afc9a 3344 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3345 qla8044_idc_unlock(ha);
3346 } else if (IS_QLA82XX(ha)) {
3347 qla82xx_idc_lock(ha);
3348 qla82xx_clear_drv_active(ha);
3349 qla82xx_idc_unlock(ha);
3350 }
3351}
3352
3353static void
3354qla2x00_remove_one(struct pci_dev *pdev)
3355{
3356 scsi_qla_host_t *base_vha;
3357 struct qla_hw_data *ha;
3358
beb9e315
JL		 3359 base_vha = pci_get_drvdata(pdev);
3360 ha = base_vha->hw;
3361
3362 /* Indicate device removal to prevent future board_disable and wait
3363 * until any pending board_disable has completed. */
3364 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3365 cancel_work_sync(&ha->board_disable);
3366
fe1b806f 3367 /*
beb9e315
JL		 3368 * If the PCI device is disabled then there was a PCI-disconnect and
3369 * qla2x00_disable_board_on_pci_error has taken care of most of the
3370 * resources.
fe1b806f 3371 */
beb9e315
JL		 3372 if (!atomic_read(&pdev->enable_cnt)) {
3373 scsi_host_put(base_vha->host);
3374 kfree(ha);
3375 pci_set_drvdata(pdev, NULL);
fe1b806f 3376 return;
beb9e315 3377 }
fe1b806f 3378
638a1a01
SC		 3379 qla2x00_wait_for_hba_ready(base_vha);
3380
783e0dc4
SC		 3381 /* if UNLOAD flag is already set, then continue unload,
3382 * where it was set first.
3383 */
3384 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3385 return;
3386
fe1b806f
CD		 3387 set_bit(UNLOADING, &base_vha->dpc_flags);
3388
3389 if (IS_QLAFX00(ha))
3390 qlafx00_driver_shutdown(base_vha, 20);
3391
3392 qla2x00_delete_all_vps(ha, base_vha);
3393
3394 if (IS_QLA8031(ha)) {
3395 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3396 "Clearing fcoe driver presence.\n");
3397 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3398 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3399 "Error while clearing DRV-Presence.\n");
3400 }
3401
3402 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3403
3404 qla2x00_dfs_remove(base_vha);
3405
3406 qla84xx_put_chip(base_vha);
3407
2d5a4c34
HM		 3408 /* Laser should be disabled only for ISP2031 */
3409 if (IS_QLA2031(ha))
3410 qla83xx_disable_laser(base_vha);
3411
fe1b806f
CD		 3412 /* Disable timer */
3413 if (base_vha->timer_active)
3414 qla2x00_stop_timer(base_vha);
3415
3416 base_vha->flags.online = 0;
3417
b0d6cabd
HM		 3418 /* free DMA memory */
3419 if (ha->exlogin_buf)
3420 qla2x00_free_exlogin_buffer(ha);
3421
2f56a7f1
HM		 3422 /* free DMA memory */
3423 if (ha->exchoffld_buf)
3424 qla2x00_free_exchoffld_buffer(ha);
3425
fe1b806f
CD		 3426 qla2x00_destroy_deferred_work(ha);
3427
3428 qlt_remove_target(ha, base_vha);
3429
3430 qla2x00_free_sysfs_attr(base_vha, true);
3431
3432 fc_remove_host(base_vha->host);
3433
3434 scsi_remove_host(base_vha->host);
3435
3436 qla2x00_free_device(base_vha);
3437
db7157d4 3438 qla2x00_clear_drv_active(ha);
fe1b806f 3439
d2749ffa
AE		 3440 scsi_host_put(base_vha->host);
3441
fe1b806f 3442 qla2x00_unmap_iobases(ha);
73208dfd 3443
e315cd28
AC		 3444 pci_release_selected_regions(ha->pdev, ha->bars);
3445 kfree(ha);
3446 ha = NULL;
1da177e4 3447
90a86fc0
JC		 3448 pci_disable_pcie_error_reporting(pdev);
3449
665db93b 3450 pci_disable_device(pdev);
1da177e4 3451}
1da177e4
LT		 3452
3453static void
e315cd28 3454qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3455{
e315cd28 3456 struct qla_hw_data *ha = vha->hw;
1da177e4 3457
85880801
AV		 3458 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3459
3460 /* Disable timer */
3461 if (vha->timer_active)
3462 qla2x00_stop_timer(vha);
3463
2afa19a9 3464 qla25xx_delete_queues(vha);
fe1b806f 3465
df613b96 3466 if (ha->flags.fce_enabled)
e315cd28 3467 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3468
a7a167bf 3469 if (ha->eft)
e315cd28 3470 qla2x00_disable_eft_trace(vha);
a7a167bf 3471
f6ef3b18 3472 /* Stop currently executing firmware. */
e315cd28 3473 qla2x00_try_to_stop_firmware(vha);
1da177e4 3474
85880801
AV		 3475 vha->flags.online = 0;
3476
f6ef3b18 3477 /* turn-off interrupts on the card */
a9083016
GM		 3478 if (ha->interrupts_on) {
3479 vha->flags.init_done = 0;
fd34f556 3480 ha->isp_ops->disable_intrs(ha);
a9083016 3481 }
f6ef3b18 3482
093df737
QT		 3483 qla2x00_free_fcports(vha);
3484
e315cd28 3485 qla2x00_free_irqs(vha);
1da177e4 3486
093df737
QT		 3487 /* Flush the work queue and remove it */
3488 if (ha->wq) {
3489 flush_workqueue(ha->wq);
3490 destroy_workqueue(ha->wq);
3491 ha->wq = NULL;
3492 }
3493
8867048b 3494
e315cd28 3495 qla2x00_mem_free(ha);
73208dfd 3496
08de2844
GM		 3497 qla82xx_md_free(vha);
3498
73208dfd 3499 qla2x00_free_queues(ha);
1da177e4
LT		 3500}
3501
8867048b
CD		 3502void qla2x00_free_fcports(struct scsi_qla_host *vha)
3503{
3504 fc_port_t *fcport, *tfcport;
3505
3506 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3507 list_del(&fcport->list);
5f16b331 3508 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3509 kfree(fcport);
3510 fcport = NULL;
3511 }
3512}
3513
d97994dc 3514static inline void
e315cd28 3515qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3516 int defer)
3517{
d97994dc 3518 struct fc_rport *rport;
67becc00 3519 scsi_qla_host_t *base_vha;
044d78e1 3520 unsigned long flags;
d97994dc
AV		 3521
3522 if (!fcport->rport)
3523 return;
3524
3525 rport = fcport->rport;
3526 if (defer) {
67becc00 3527 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3528 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3529 fcport->drport = rport;
044d78e1 3530 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3531 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3532 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3533 qla2xxx_wake_dpc(base_vha);
2d70c103 3534 } else {
df673274 3535 int now;
d20ed91b
AP		 3536 if (rport)
3537 fc_remote_port_delete(rport);
df673274
AP		 3538 qlt_do_generation_tick(vha, &now);
3539 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3540 }
d97994dc
AV		 3541}
3542
1da177e4
LT		 3543/*
3544 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3545 *
3546 * Input: ha = adapter block pointer. fcport = port structure pointer.
3547 *
3548 * Return: None.
3549 *
3550 * Context:
3551 */
e315cd28 3552void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3553 int do_login, int defer)
1da177e4 3554{
8ae6d9c7
GM		 3555 if (IS_QLAFX00(vha->hw)) {
3556 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3557 qla2x00_schedule_rport_del(vha, fcport, defer);
3558 return;
3559 }
3560
2c3dfe3f 3561 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3562 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3563 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3564 qla2x00_schedule_rport_del(vha, fcport, defer);
3565 }
fa2a1ce5 3566 /*
1da177e4
LT		 3567 * We may need to retry the login, so don't change the state of the
3568 * port but do the retries.
3569 */
3570 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3571 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3572
3573 if (!do_login)
3574 return;
3575
a1d0285e
AE		 3576 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3577
1da177e4 3578 if (fcport->login_retry == 0) {
e315cd28 3579 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3580
7c3df132 3581 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3582 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3583 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3584 }
3585}
3586
3587/*
3588 * qla2x00_mark_all_devices_lost
3589 * Updates fcport state when device goes offline.
3590 *
3591 * Input:
3592 * ha = adapter block pointer.
3593 * fcport = port structure pointer.
3594 *
3595 * Return:
3596 * None.
3597 *
3598 * Context:
3599 */
3600void
e315cd28 3601qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3602{
3603 fc_port_t *fcport;
3604
e315cd28 3605 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3606 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3607 continue;
0d6e61bc 3608
1da177e4
LT		 3609 /*
3610 * No point in marking the device as lost, if the device is
3611 * already DEAD.
3612 */
3613 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3614 continue;
e315cd28 3615 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3616 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3617 if (defer)
3618 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3619 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3620 qla2x00_schedule_rport_del(vha, fcport, defer);
3621 }
1da177e4
LT		 3622 }
3623}
3624
3625/*
3626* qla2x00_mem_alloc
3627* Allocates adapter memory.
3628*
3629* Returns:
3630* 0 = success.
e8711085 3631* !0 = failure.
1da177e4 3632*/
e8711085 3633static int
73208dfd
AC		 3634qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3635 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3636{
3637 char name[16];
1da177e4 3638
e8711085 3639 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3640 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3641 if (!ha->init_cb)
e315cd28 3642 goto fail;
e8711085 3643
2d70c103
NB		 3644 if (qlt_mem_alloc(ha) < 0)
3645 goto fail_free_init_cb;
3646
642ef983
CD		 3647 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3648 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3649 if (!ha->gid_list)
2d70c103 3650 goto fail_free_tgt_mem;
1da177e4 3651
e8711085
AV		 3652 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3653 if (!ha->srb_mempool)
e315cd28 3654 goto fail_free_gid_list;
e8711085 3655
7ec0effd 3656 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3657 /* Allocate cache for CT6 Ctx. */
3658 if (!ctx_cachep) {
3659 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3660 sizeof(struct ct6_dsd), 0,
3661 SLAB_HWCACHE_ALIGN, NULL);
3662 if (!ctx_cachep)
fc1ffd6c 3663 goto fail_free_srb_mempool;
a9083016
GM		 3664 }
3665 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3666 ctx_cachep);
3667 if (!ha->ctx_mempool)
3668 goto fail_free_srb_mempool;
7c3df132
SK		 3669 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3670 "ctx_cachep=%p ctx_mempool=%p.\n",
3671 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3672 }
3673
e8711085
AV		 3674 /* Get memory for cached NVRAM */
3675 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3676 if (!ha->nvram)
a9083016 3677 goto fail_free_ctx_mempool;
e8711085 3678
e315cd28
AC		 3679 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3680 ha->pdev->device);
3681 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3682 DMA_POOL_SIZE, 8, 0);
3683 if (!ha->s_dma_pool)
3684 goto fail_free_nvram;
3685
7c3df132
SK		 3686 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3687 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3688 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3689
7ec0effd 3690 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3691 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3692 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3693 if (!ha->dl_dma_pool) {
7c3df132
SK		 3694 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3695 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3696 goto fail_s_dma_pool;
3697 }
3698
3699 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3700 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3701 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3702 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3703 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3704 goto fail_dl_dma_pool;
3705 }
7c3df132
SK		 3706 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3707 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3708 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3709 }
3710
e8711085
AV		 3711 /* Allocate memory for SNS commands */
3712 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3713 /* Get consistent memory allocated for SNS commands */
e8711085 3714 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3715 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3716 if (!ha->sns_cmd)
e315cd28 3717 goto fail_dma_pool;
7c3df132 3718 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3719 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3720 } else {
e315cd28 3721 /* Get consistent memory allocated for MS IOCB */
e8711085 3722 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3723 &ha->ms_iocb_dma);
e8711085 3724 if (!ha->ms_iocb)
e315cd28
AC		 3725 goto fail_dma_pool;
3726 /* Get consistent memory allocated for CT SNS commands */
e8711085 3727 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3728 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3729 if (!ha->ct_sns)
3730 goto fail_free_ms_iocb;
7c3df132
SK		 3731 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3732 "ms_iocb=%p ct_sns=%p.\n",
3733 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3734 }
3735
e315cd28 3736 /* Allocate memory for request ring */
73208dfd
AC		 3737 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3738 if (!*req) {
7c3df132
SK		 3739 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3740 "Failed to allocate memory for req.\n");
e315cd28
AC		 3741 goto fail_req;
3742 }
73208dfd
AC		 3743 (*req)->length = req_len;
3744 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3745 ((*req)->length + 1) * sizeof(request_t),
3746 &(*req)->dma, GFP_KERNEL);
3747 if (!(*req)->ring) {
7c3df132
SK		 3748 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3749 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3750 goto fail_req_ring;
3751 }
3752 /* Allocate memory for response ring */
73208dfd
AC		 3753 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3754 if (!*rsp) {
7c3df132
SK		 3755 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3756 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3757 goto fail_rsp;
3758 }
73208dfd
AC		 3759 (*rsp)->hw = ha;
3760 (*rsp)->length = rsp_len;
3761 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3762 ((*rsp)->length + 1) * sizeof(response_t),
3763 &(*rsp)->dma, GFP_KERNEL);
3764 if (!(*rsp)->ring) {
7c3df132
SK		 3765 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3766 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3767 goto fail_rsp_ring;
3768 }
73208dfd
AC		 3769 (*req)->rsp = *rsp;
3770 (*rsp)->req = *req;
7c3df132
SK		 3771 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3772 "req=%p req->length=%d req->ring=%p rsp=%p "
3773 "rsp->length=%d rsp->ring=%p.\n",
3774 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3775 (*rsp)->ring);
73208dfd
AC		 3776 /* Allocate memory for NVRAM data for vports */
3777 if (ha->nvram_npiv_size) {
3778 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3779 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3780 if (!ha->npiv_info) {
7c3df132
SK		 3781 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3782 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3783 goto fail_npiv_info;
3784 }
3785 } else
3786 ha->npiv_info = NULL;
e8711085 3787
b64b0e8f 3788 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3789 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3790 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3791 &ha->ex_init_cb_dma);
3792 if (!ha->ex_init_cb)
3793 goto fail_ex_init_cb;
7c3df132
SK		 3794 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3795 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3796 }
3797
a9083016
GM		 3798 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3799
5ff1d584
AV		 3800 /* Get consistent memory allocated for Async Port-Database. */
3801 if (!IS_FWI2_CAPABLE(ha)) {
3802 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3803 &ha->async_pd_dma);
3804 if (!ha->async_pd)
3805 goto fail_async_pd;
7c3df132
SK		 3806 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3807 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3808 }
3809
e315cd28 3810 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3811
3812 /* Allocate memory for our loop_id bitmap */
3813 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3814 GFP_KERNEL);
3815 if (!ha->loop_id_map)
fc1ffd6c 3816 goto fail_loop_id_map;
5f16b331
CD		 3817 else {
3818 qla2x00_set_reserved_loop_ids(ha);
3819 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3820 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3821 }
3822
b2a72ec3 3823 return 0;
e315cd28 3824
fc1ffd6c
QT		 3825fail_loop_id_map:
3826 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3827fail_async_pd:
3828 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3829fail_ex_init_cb:
3830 kfree(ha->npiv_info);
73208dfd
AC		 3831fail_npiv_info:
3832 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3833 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3834 (*rsp)->ring = NULL;
3835 (*rsp)->dma = 0;
e315cd28 3836fail_rsp_ring:
73208dfd 3837 kfree(*rsp);
e315cd28 3838fail_rsp:
73208dfd
AC		 3839 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3840 sizeof(request_t), (*req)->ring, (*req)->dma);
3841 (*req)->ring = NULL;
3842 (*req)->dma = 0;
e315cd28 3843fail_req_ring:
73208dfd 3844 kfree(*req);
e315cd28
AC		 3845fail_req:
3846 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3847 ha->ct_sns, ha->ct_sns_dma);
3848 ha->ct_sns = NULL;
3849 ha->ct_sns_dma = 0;
e8711085
AV		 3850fail_free_ms_iocb:
3851 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3852 ha->ms_iocb = NULL;
3853 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3854
3855 if (ha->sns_cmd)
3856 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3857 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3858fail_dma_pool:
bad75002 3859 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3860 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3861 ha->fcp_cmnd_dma_pool = NULL;
3862 }
3863fail_dl_dma_pool:
bad75002 3864 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3865 dma_pool_destroy(ha->dl_dma_pool);
3866 ha->dl_dma_pool = NULL;
3867 }
3868fail_s_dma_pool:
e315cd28
AC		 3869 dma_pool_destroy(ha->s_dma_pool);
3870 ha->s_dma_pool = NULL;
e8711085
AV		 3871fail_free_nvram:
3872 kfree(ha->nvram);
3873 ha->nvram = NULL;
a9083016 3874fail_free_ctx_mempool:
fc1ffd6c
QT		 3875 if (ha->ctx_mempool)
3876 mempool_destroy(ha->ctx_mempool);
a9083016 3877 ha->ctx_mempool = NULL;
e8711085 3878fail_free_srb_mempool:
fc1ffd6c
QT		 3879 if (ha->srb_mempool)
3880 mempool_destroy(ha->srb_mempool);
e8711085 3881 ha->srb_mempool = NULL;
e8711085 3882fail_free_gid_list:
642ef983
CD		 3883 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3884 ha->gid_list,
e315cd28 3885 ha->gid_list_dma);
e8711085
AV		 3886 ha->gid_list = NULL;
3887 ha->gid_list_dma = 0;
2d70c103
NB		 3888fail_free_tgt_mem:
3889 qlt_mem_free(ha);
e315cd28
AC		 3890fail_free_init_cb:
3891 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3892 ha->init_cb_dma);
3893 ha->init_cb = NULL;
3894 ha->init_cb_dma = 0;
e8711085 3895fail:
7c3df132
SK		 3896 ql_log(ql_log_fatal, NULL, 0x0030,
3897 "Memory allocation failure.\n");
e8711085 3898 return -ENOMEM;
1da177e4
LT		 3899}
3900
b0d6cabd
HM		 3901int
3902qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3903{
3904 int rval;
3905 uint16_t size, max_cnt, temp;
3906 struct qla_hw_data *ha = vha->hw;
3907
3908 /* Return if we don't need to alloacate any extended logins */
3909 if (!ql2xexlogins)
3910 return QLA_SUCCESS;
3911
3912 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3913 max_cnt = 0;
3914 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3915 if (rval != QLA_SUCCESS) {
3916 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3917 "Failed to get exlogin status.\n");
3918 return rval;
3919 }
3920
3921 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3922 ha->exlogin_size = (size * temp);
3923 ql_log(ql_log_info, vha, 0xd024,
3924 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3925 max_cnt, size, temp);
3926
3927 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3928 ha->exlogin_size);
3929
3930 /* Get consistent memory for extended logins */
3931 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3932 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3933 if (!ha->exlogin_buf) {
3934 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3935 "Failed to allocate memory for exlogin_buf_dma.\n");
3936 return -ENOMEM;
3937 }
3938
3939 /* Now configure the dma buffer */
3940 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3941 if (rval) {
3942 ql_log(ql_log_fatal, vha, 0x00cf,
3943 "Setup extended login buffer ****FAILED****.\n");
3944 qla2x00_free_exlogin_buffer(ha);
3945 }
3946
3947 return rval;
3948}
3949
3950/*
3951* qla2x00_free_exlogin_buffer
3952*
3953* Input:
3954* ha = adapter block pointer
3955*/
3956void
3957qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3958{
3959 if (ha->exlogin_buf) {
3960 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3961 ha->exlogin_buf, ha->exlogin_buf_dma);
3962 ha->exlogin_buf = NULL;
3963 ha->exlogin_size = 0;
3964 }
3965}
3966
2f56a7f1
HM		 3967int
3968qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3969{
3970 int rval;
3971 uint16_t size, max_cnt, temp;
3972 struct qla_hw_data *ha = vha->hw;
3973
3974 /* Return if we don't need to alloacate any extended logins */
3975 if (!ql2xexchoffld)
3976 return QLA_SUCCESS;
3977
3978 ql_log(ql_log_info, vha, 0xd014,
3979 "Exchange offload count: %d.\n", ql2xexlogins);
3980
3981 max_cnt = 0;
3982 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3983 if (rval != QLA_SUCCESS) {
3984 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3985 "Failed to get exlogin status.\n");
3986 return rval;
3987 }
3988
3989 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3990 ha->exchoffld_size = (size * temp);
3991 ql_log(ql_log_info, vha, 0xd016,
3992 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3993 max_cnt, size, temp);
3994
3995 ql_log(ql_log_info, vha, 0xd017,
3996 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3997
3998 /* Get consistent memory for extended logins */
3999 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4000 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4001 if (!ha->exchoffld_buf) {
4002 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4003 "Failed to allocate memory for exchoffld_buf_dma.\n");
4004 return -ENOMEM;
4005 }
4006
4007 /* Now configure the dma buffer */
4008 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4009 if (rval) {
4010 ql_log(ql_log_fatal, vha, 0xd02e,
4011 "Setup exchange offload buffer ****FAILED****.\n");
4012 qla2x00_free_exchoffld_buffer(ha);
4013 }
4014
4015 return rval;
4016}
4017
4018/*
4019* qla2x00_free_exchoffld_buffer
4020*
4021* Input:
4022* ha = adapter block pointer
4023*/
4024void
4025qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4026{
4027 if (ha->exchoffld_buf) {
4028 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4029 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4030 ha->exchoffld_buf = NULL;
4031 ha->exchoffld_size = 0;
4032 }
4033}
4034
1da177e4 4035/*
e30d1756
MI		 4036* qla2x00_free_fw_dump
4037* Frees fw dump stuff.
1da177e4
LT		 4038*
4039* Input:
7ec0effd 4040* ha = adapter block pointer
1da177e4 4041*/
a824ebb3 4042static void
e30d1756 4043qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4044{
df613b96 4045 if (ha->fce)
f73cb695
CD		 4046 dma_free_coherent(&ha->pdev->dev,
4047 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4048
f73cb695
CD		 4049 if (ha->eft)
4050 dma_free_coherent(&ha->pdev->dev,
4051 EFT_SIZE, ha->eft, ha->eft_dma);
4052
4053 if (ha->fw_dump)
a7a167bf 4054 vfree(ha->fw_dump);
f73cb695
CD		 4055 if (ha->fw_dump_template)
4056 vfree(ha->fw_dump_template);
4057
e30d1756
MI		 4058 ha->fce = NULL;
4059 ha->fce_dma = 0;
4060 ha->eft = NULL;
4061 ha->eft_dma = 0;
e30d1756 4062 ha->fw_dumped = 0;
61f098dd 4063 ha->fw_dump_cap_flags = 0;
e30d1756 4064 ha->fw_dump_reading = 0;
f73cb695
CD		 4065 ha->fw_dump = NULL;
4066 ha->fw_dump_len = 0;
4067 ha->fw_dump_template = NULL;
4068 ha->fw_dump_template_len = 0;
e30d1756
MI		 4069}
4070
4071/*
4072* qla2x00_mem_free
4073* Frees all adapter allocated memory.
4074*
4075* Input:
4076* ha = adapter block pointer.
4077*/
4078static void
4079qla2x00_mem_free(struct qla_hw_data *ha)
4080{
4081 qla2x00_free_fw_dump(ha);
4082
81178772
SK		 4083 if (ha->mctp_dump)
4084 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4085 ha->mctp_dump_dma);
4086
e30d1756
MI		 4087 if (ha->srb_mempool)
4088 mempool_destroy(ha->srb_mempool);
a7a167bf 4089
11bbc1d8
AV		 4090 if (ha->dcbx_tlv)
4091 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4092 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4093
ce0423f4
AV		 4094 if (ha->xgmac_data)
4095 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4096 ha->xgmac_data, ha->xgmac_data_dma);
4097
1da177e4
LT		 4098 if (ha->sns_cmd)
4099 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4100 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4101
4102 if (ha->ct_sns)
4103 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4104 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4105
88729e53
AV		 4106 if (ha->sfp_data)
4107 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4108
1da177e4
LT		 4109 if (ha->ms_iocb)
4110 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4111
b64b0e8f 4112 if (ha->ex_init_cb)
a9083016
GM		 4113 dma_pool_free(ha->s_dma_pool,
4114 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4115
5ff1d584
AV		 4116 if (ha->async_pd)
4117 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4118
1da177e4
LT		 4119 if (ha->s_dma_pool)
4120 dma_pool_destroy(ha->s_dma_pool);
4121
1da177e4 4122 if (ha->gid_list)
642ef983
CD		 4123 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4124 ha->gid_list, ha->gid_list_dma);
1da177e4 4125
a9083016
GM		 4126 if (IS_QLA82XX(ha)) {
4127 if (!list_empty(&ha->gbl_dsd_list)) {
4128 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4129
4130 /* clean up allocated prev pool */
4131 list_for_each_entry_safe(dsd_ptr,
4132 tdsd_ptr, &ha->gbl_dsd_list, list) {
4133 dma_pool_free(ha->dl_dma_pool,
4134 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4135 list_del(&dsd_ptr->list);
4136 kfree(dsd_ptr);
4137 }
4138 }
4139 }
4140
4141 if (ha->dl_dma_pool)
4142 dma_pool_destroy(ha->dl_dma_pool);
4143
4144 if (ha->fcp_cmnd_dma_pool)
4145 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4146
4147 if (ha->ctx_mempool)
4148 mempool_destroy(ha->ctx_mempool);
4149
2d70c103
NB		 4150 qlt_mem_free(ha);
4151
e315cd28
AC		 4152 if (ha->init_cb)
4153 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4154 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4155 vfree(ha->optrom_buffer);
4156 kfree(ha->nvram);
73208dfd 4157 kfree(ha->npiv_info);
7a67735b 4158 kfree(ha->swl);
5f16b331 4159 kfree(ha->loop_id_map);
1da177e4 4160
e8711085 4161 ha->srb_mempool = NULL;
a9083016 4162 ha->ctx_mempool = NULL;
1da177e4
LT		 4163 ha->sns_cmd = NULL;
4164 ha->sns_cmd_dma = 0;
4165 ha->ct_sns = NULL;
4166 ha->ct_sns_dma = 0;
4167 ha->ms_iocb = NULL;
4168 ha->ms_iocb_dma = 0;
1da177e4
LT		 4169 ha->init_cb = NULL;
4170 ha->init_cb_dma = 0;
b64b0e8f
AV		 4171 ha->ex_init_cb = NULL;
4172 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4173 ha->async_pd = NULL;
4174 ha->async_pd_dma = 0;
1da177e4
LT		 4175
4176 ha->s_dma_pool = NULL;
a9083016
GM		 4177 ha->dl_dma_pool = NULL;
4178 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4179
1da177e4
LT		 4180 ha->gid_list = NULL;
4181 ha->gid_list_dma = 0;
2d70c103
NB		 4182
4183 ha->tgt.atio_ring = NULL;
4184 ha->tgt.atio_dma = 0;
4185 ha->tgt.tgt_vp_map = NULL;
e315cd28 4186}
1da177e4 4187
e315cd28
AC		 4188struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4189 struct qla_hw_data *ha)
4190{
4191 struct Scsi_Host *host;
4192 struct scsi_qla_host *vha = NULL;
854165f4 4193
e315cd28
AC		 4194 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4195 if (host == NULL) {
7c3df132
SK		 4196 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4197 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 4198 goto fail;
4199 }
4200
4201 /* Clear our data area */
4202 vha = shost_priv(host);
4203 memset(vha, 0, sizeof(scsi_qla_host_t));
4204
4205 vha->host = host;
4206 vha->host_no = host->host_no;
4207 vha->hw = ha;
4208
4209 INIT_LIST_HEAD(&vha->vp_fcports);
4210 INIT_LIST_HEAD(&vha->work_list);
4211 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4212 INIT_LIST_HEAD(&vha->qla_cmd_list);
4213 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4214 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4215 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4216 INIT_LIST_HEAD(&vha->qp_list);
e315cd28 4217
f999f4c1 4218 spin_lock_init(&vha->work_lock);
8b2f5ff3 4219 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 4220
e315cd28 4221 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4222 ql_dbg(ql_dbg_init, vha, 0x0041,
4223 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4224 vha->host, vha->hw, vha,
4225 dev_name(&(ha->pdev->dev)));
4226
e315cd28
AC		 4227 return vha;
4228
4229fail:
4230 return vha;
1da177e4
LT		 4231}
4232
01ef66bb 4233static struct qla_work_evt *
f999f4c1 4234qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4235{
4236 struct qla_work_evt *e;
feafb7b1
AE		 4237 uint8_t bail;
4238
4239 QLA_VHA_MARK_BUSY(vha, bail);
4240 if (bail)
4241 return NULL;
0971de7f 4242
f999f4c1 4243 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4244 if (!e) {
4245 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4246 return NULL;
feafb7b1 4247 }
0971de7f
AV		 4248
4249 INIT_LIST_HEAD(&e->list);
4250 e->type = type;
4251 e->flags = QLA_EVT_FLAG_FREE;
4252 return e;
4253}
4254
01ef66bb 4255static int
f999f4c1 4256qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4257{
f999f4c1 4258 unsigned long flags;
0971de7f 4259
f999f4c1 4260 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4261 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4262 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 4263 qla2xxx_wake_dpc(vha);
f999f4c1 4264
0971de7f
AV		 4265 return QLA_SUCCESS;
4266}
4267
4268int
e315cd28 4269qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4270 u32 data)
4271{
4272 struct qla_work_evt *e;
4273
f999f4c1 4274 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4275 if (!e)
4276 return QLA_FUNCTION_FAILED;
4277
4278 e->u.aen.code = code;
4279 e->u.aen.data = data;
f999f4c1 4280 return qla2x00_post_work(vha, e);
0971de7f
AV		 4281}
4282
8a659571
AV		 4283int
4284qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4285{
4286 struct qla_work_evt *e;
4287
f999f4c1 4288 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4289 if (!e)
4290 return QLA_FUNCTION_FAILED;
4291
4292 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4293 return qla2x00_post_work(vha, e);
8a659571
AV		 4294}
4295
ac280b67
AV		 4296#define qla2x00_post_async_work(name, type) \
4297int qla2x00_post_async_##name##_work( \
4298 struct scsi_qla_host *vha, \
4299 fc_port_t *fcport, uint16_t *data) \
4300{ \
4301 struct qla_work_evt *e; \
4302 \
4303 e = qla2x00_alloc_work(vha, type); \
4304 if (!e) \
4305 return QLA_FUNCTION_FAILED; \
4306 \
4307 e->u.logio.fcport = fcport; \
4308 if (data) { \
4309 e->u.logio.data[0] = data[0]; \
4310 e->u.logio.data[1] = data[1]; \
4311 } \
4312 return qla2x00_post_work(vha, e); \
4313}
4314
4315qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4316qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4317qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4318qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4319qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4320qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4321
3420d36c
AV		 4322int
4323qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4324{
4325 struct qla_work_evt *e;
4326
4327 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4328 if (!e)
4329 return QLA_FUNCTION_FAILED;
4330
4331 e->u.uevent.code = code;
4332 return qla2x00_post_work(vha, e);
4333}
4334
4335static void
4336qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4337{
4338 char event_string[40];
4339 char *envp[] = { event_string, NULL };
4340
4341 switch (code) {
4342 case QLA_UEVENT_CODE_FW_DUMP:
4343 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4344 vha->host_no);
4345 break;
4346 default:
4347 /* do nothing */
4348 break;
4349 }
4350 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4351}
4352
8ae6d9c7
GM		 4353int
4354qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4355 uint32_t *data, int cnt)
4356{
4357 struct qla_work_evt *e;
4358
4359 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4360 if (!e)
4361 return QLA_FUNCTION_FAILED;
4362
4363 e->u.aenfx.evtcode = evtcode;
4364 e->u.aenfx.count = cnt;
4365 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4366 return qla2x00_post_work(vha, e);
4367}
4368
ac280b67 4369void
e315cd28 4370qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4371{
f999f4c1
AV		 4372 struct qla_work_evt *e, *tmp;
4373 unsigned long flags;
4374 LIST_HEAD(work);
0971de7f 4375
f999f4c1
AV		 4376 spin_lock_irqsave(&vha->work_lock, flags);
4377 list_splice_init(&vha->work_list, &work);
4378 spin_unlock_irqrestore(&vha->work_lock, flags);
4379
4380 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4381 list_del_init(&e->list);
0971de7f
AV		 4382
4383 switch (e->type) {
4384 case QLA_EVT_AEN:
e315cd28 4385 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4386 e->u.aen.code, e->u.aen.data);
4387 break;
8a659571
AV		 4388 case QLA_EVT_IDC_ACK:
4389 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4390 break;
ac280b67
AV		 4391 case QLA_EVT_ASYNC_LOGIN:
4392 qla2x00_async_login(vha, e->u.logio.fcport,
4393 e->u.logio.data);
4394 break;
4395 case QLA_EVT_ASYNC_LOGIN_DONE:
4396 qla2x00_async_login_done(vha, e->u.logio.fcport,
4397 e->u.logio.data);
4398 break;
4399 case QLA_EVT_ASYNC_LOGOUT:
4400 qla2x00_async_logout(vha, e->u.logio.fcport);
4401 break;
4402 case QLA_EVT_ASYNC_LOGOUT_DONE:
4403 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4404 e->u.logio.data);
4405 break;
5ff1d584
AV		 4406 case QLA_EVT_ASYNC_ADISC:
4407 qla2x00_async_adisc(vha, e->u.logio.fcport,
4408 e->u.logio.data);
4409 break;
4410 case QLA_EVT_ASYNC_ADISC_DONE:
4411 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4412 e->u.logio.data);
4413 break;
3420d36c
AV		 4414 case QLA_EVT_UEVENT:
4415 qla2x00_uevent_emit(vha, e->u.uevent.code);
4416 break;
8ae6d9c7
GM		 4417 case QLA_EVT_AENFX:
4418 qlafx00_process_aen(vha, e);
4419 break;
0971de7f
AV		 4420 }
4421 if (e->flags & QLA_EVT_FLAG_FREE)
4422 kfree(e);
feafb7b1
AE		 4423
4424 /* For each work completed decrement vha ref count */
4425 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4426 }
e315cd28 4427}
f999f4c1 4428
e315cd28
AC		 4429/* Relogins all the fcports of a vport
4430 * Context: dpc thread
4431 */
4432void qla2x00_relogin(struct scsi_qla_host *vha)
4433{
4434 fc_port_t *fcport;
c6b2fca8 4435 int status;
e315cd28
AC		 4436 uint16_t next_loopid = 0;
4437 struct qla_hw_data *ha = vha->hw;
ac280b67 4438 uint16_t data[2];
e315cd28
AC		 4439
4440 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4441 /*
4442 * If the port is not ONLINE then try to login
4443 * to it if we haven't run out of retries.
4444 */
5ff1d584
AV		 4445 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4446 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4447 fcport->login_retry--;
e315cd28 4448 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4449 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4450 ha->isp_ops->fabric_logout(vha,
4451 fcport->loop_id,
4452 fcport->d_id.b.domain,
4453 fcport->d_id.b.area,
4454 fcport->d_id.b.al_pa);
4455
03bcfb57
JC		 4456 if (fcport->loop_id == FC_NO_LOOP_ID) {
4457 fcport->loop_id = next_loopid =
4458 ha->min_external_loopid;
4459 status = qla2x00_find_new_loop_id(
4460 vha, fcport);
4461 if (status != QLA_SUCCESS) {
4462 /* Ran out of IDs to use */
4463 break;
4464 }
4465 }
4466
ac280b67 4467 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4468 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4469 data[0] = 0;
4470 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4471 status = qla2x00_post_async_login_work(
4472 vha, fcport, data);
4473 if (status == QLA_SUCCESS)
4474 continue;
4475 /* Attempt a retry. */
4476 status = 1;
aaf4d3e2 4477 } else {
ac280b67
AV		 4478 status = qla2x00_fabric_login(vha,
4479 fcport, &next_loopid);
aaf4d3e2
SK		 4480 if (status == QLA_SUCCESS) {
4481 int status2;
4482 uint8_t opts;
4483
4484 opts = 0;
4485 if (fcport->flags &
4486 FCF_FCP2_DEVICE)
4487 opts |= BIT_1;
03003960
SK		 4488 status2 =
4489 qla2x00_get_port_database(
4490 vha, fcport, opts);
aaf4d3e2
SK		 4491 if (status2 != QLA_SUCCESS)
4492 status = 1;
4493 }
4494 }
e315cd28
AC		 4495 } else
4496 status = qla2x00_local_device_login(vha,
4497 fcport);
4498
e315cd28
AC		 4499 if (status == QLA_SUCCESS) {
4500 fcport->old_loop_id = fcport->loop_id;
4501
7c3df132
SK		 4502 ql_dbg(ql_dbg_disc, vha, 0x2003,
4503 "Port login OK: logged in ID 0x%x.\n",
4504 fcport->loop_id);
e315cd28
AC		 4505
4506 qla2x00_update_fcport(vha, fcport);
4507
4508 } else if (status == 1) {
4509 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4510 /* retry the login again */
7c3df132
SK		 4511 ql_dbg(ql_dbg_disc, vha, 0x2007,
4512 "Retrying %d login again loop_id 0x%x.\n",
4513 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4514 } else {
4515 fcport->login_retry = 0;
4516 }
4517
4518 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4519 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4520 }
4521 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4522 break;
0971de7f 4523 }
0971de7f
AV		 4524}
4525
7d613ac6
SV		 4526/* Schedule work on any of the dpc-workqueues */
4527void
4528qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4529{
4530 struct qla_hw_data *ha = base_vha->hw;
4531
4532 switch (work_code) {
4533 case MBA_IDC_AEN: /* 0x8200 */
4534 if (ha->dpc_lp_wq)
4535 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4536 break;
4537
4538 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4539 if (!ha->flags.nic_core_reset_hdlr_active) {
4540 if (ha->dpc_hp_wq)
4541 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4542 } else
4543 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4544 "NIC Core reset is already active. Skip "
4545 "scheduling it again.\n");
4546 break;
4547 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4548 if (ha->dpc_hp_wq)
4549 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4550 break;
4551 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4552 if (ha->dpc_hp_wq)
4553 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4554 break;
4555 default:
4556 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4557 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4558 }
4559
4560 return;
4561}
4562
4563/* Work: Perform NIC Core Unrecoverable state handling */
4564void
4565qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4566{
4567 struct qla_hw_data *ha =
2ad1b67c 4568 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4569 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4570 uint32_t dev_state = 0;
4571
4572 qla83xx_idc_lock(base_vha, 0);
4573 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4574 qla83xx_reset_ownership(base_vha);
4575 if (ha->flags.nic_core_reset_owner) {
4576 ha->flags.nic_core_reset_owner = 0;
4577 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4578 QLA8XXX_DEV_FAILED);
4579 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4580 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4581 }
4582 qla83xx_idc_unlock(base_vha, 0);
4583}
4584
4585/* Work: Execute IDC state handler */
4586void
4587qla83xx_idc_state_handler_work(struct work_struct *work)
4588{
4589 struct qla_hw_data *ha =
2ad1b67c 4590 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4591 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4592 uint32_t dev_state = 0;
4593
4594 qla83xx_idc_lock(base_vha, 0);
4595 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4596 if (dev_state == QLA8XXX_DEV_FAILED ||
4597 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4598 qla83xx_idc_state_handler(base_vha);
4599 qla83xx_idc_unlock(base_vha, 0);
4600}
4601
fa492630 4602static int
7d613ac6
SV		 4603qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4604{
4605 int rval = QLA_SUCCESS;
4606 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4607 uint32_t heart_beat_counter1, heart_beat_counter2;
4608
4609 do {
4610 if (time_after(jiffies, heart_beat_wait)) {
4611 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4612 "Nic Core f/w is not alive.\n");
4613 rval = QLA_FUNCTION_FAILED;
4614 break;
4615 }
4616
4617 qla83xx_idc_lock(base_vha, 0);
4618 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4619 &heart_beat_counter1);
4620 qla83xx_idc_unlock(base_vha, 0);
4621 msleep(100);
4622 qla83xx_idc_lock(base_vha, 0);
4623 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4624 &heart_beat_counter2);
4625 qla83xx_idc_unlock(base_vha, 0);
4626 } while (heart_beat_counter1 == heart_beat_counter2);
4627
4628 return rval;
4629}
4630
4631/* Work: Perform NIC Core Reset handling */
4632void
4633qla83xx_nic_core_reset_work(struct work_struct *work)
4634{
4635 struct qla_hw_data *ha =
4636 container_of(work, struct qla_hw_data, nic_core_reset);
4637 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4638 uint32_t dev_state = 0;
4639
81178772
SK		 4640 if (IS_QLA2031(ha)) {
4641 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4642 ql_log(ql_log_warn, base_vha, 0xb081,
4643 "Failed to dump mctp\n");
4644 return;
4645 }
4646
7d613ac6
SV		 4647 if (!ha->flags.nic_core_reset_hdlr_active) {
4648 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4649 qla83xx_idc_lock(base_vha, 0);
4650 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4651 &dev_state);
4652 qla83xx_idc_unlock(base_vha, 0);
4653 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4654 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4655 "Nic Core f/w is alive.\n");
4656 return;
4657 }
4658 }
4659
4660 ha->flags.nic_core_reset_hdlr_active = 1;
4661 if (qla83xx_nic_core_reset(base_vha)) {
4662 /* NIC Core reset failed. */
4663 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4664 "NIC Core reset failed.\n");
4665 }
4666 ha->flags.nic_core_reset_hdlr_active = 0;
4667 }
4668}
4669
4670/* Work: Handle 8200 IDC aens */
4671void
4672qla83xx_service_idc_aen(struct work_struct *work)
4673{
4674 struct qla_hw_data *ha =
4675 container_of(work, struct qla_hw_data, idc_aen);
4676 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4677 uint32_t dev_state, idc_control;
4678
4679 qla83xx_idc_lock(base_vha, 0);
4680 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4681 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4682 qla83xx_idc_unlock(base_vha, 0);
4683 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4684 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4685 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4686 "Application requested NIC Core Reset.\n");
4687 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4688 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4689 QLA_SUCCESS) {
4690 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4691 "Other protocol driver requested NIC Core Reset.\n");
4692 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4693 }
4694 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4695 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4696 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4697 }
4698}
4699
4700static void
4701qla83xx_wait_logic(void)
4702{
4703 int i;
4704
4705 /* Yield CPU */
4706 if (!in_interrupt()) {
4707 /*
4708 * Wait about 200ms before retrying again.
4709 * This controls the number of retries for single
4710 * lock operation.
4711 */
4712 msleep(100);
4713 schedule();
4714 } else {
4715 for (i = 0; i < 20; i++)
4716 cpu_relax(); /* This a nop instr on i386 */
4717 }
4718}
4719
fa492630 4720static int
7d613ac6
SV		 4721qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4722{
4723 int rval;
4724 uint32_t data;
4725 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4726 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4727 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4728 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4729 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4730
4731 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4732 if (rval)
4733 return rval;
4734
4735 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4736 return QLA_SUCCESS;
4737 } else {
4738 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4739 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4740 data);
4741 if (rval)
4742 return rval;
4743
4744 msleep(200);
4745
4746 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4747 &data);
4748 if (rval)
4749 return rval;
4750
4751 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4752 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4753 ~(idc_lck_rcvry_stage_mask));
4754 rval = qla83xx_wr_reg(base_vha,
4755 QLA83XX_IDC_LOCK_RECOVERY, data);
4756 if (rval)
4757 return rval;
4758
4759 /* Forcefully perform IDC UnLock */
4760 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4761 &data);
4762 if (rval)
4763 return rval;
4764 /* Clear lock-id by setting 0xff */
4765 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4766 0xff);
4767 if (rval)
4768 return rval;
4769 /* Clear lock-recovery by setting 0x0 */
4770 rval = qla83xx_wr_reg(base_vha,
4771 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4772 if (rval)
4773 return rval;
4774 } else
4775 return QLA_SUCCESS;
4776 }
4777
4778 return rval;
4779}
4780
fa492630 4781static int
7d613ac6
SV		 4782qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4783{
4784 int rval = QLA_SUCCESS;
4785 uint32_t o_drv_lockid, n_drv_lockid;
4786 unsigned long lock_recovery_timeout;
4787
4788 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4789retry_lockid:
4790 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4791 if (rval)
4792 goto exit;
4793
4794 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4795 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4796 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4797 return QLA_SUCCESS;
4798 else
4799 return QLA_FUNCTION_FAILED;
4800 }
4801
4802 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4803 if (rval)
4804 goto exit;
4805
4806 if (o_drv_lockid == n_drv_lockid) {
4807 qla83xx_wait_logic();
4808 goto retry_lockid;
4809 } else
4810 return QLA_SUCCESS;
4811
4812exit:
4813 return rval;
4814}
4815
4816void
4817qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4818{
4819 uint16_t options = (requester_id << 15) | BIT_6;
4820 uint32_t data;
6c315553 4821 uint32_t lock_owner;
7d613ac6
SV		 4822 struct qla_hw_data *ha = base_vha->hw;
4823
4824 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4825retry_lock:
4826 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4827 == QLA_SUCCESS) {
4828 if (data) {
4829 /* Setting lock-id to our function-number */
4830 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4831 ha->portnum);
4832 } else {
6c315553
SK		 4833 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4834 &lock_owner);
7d613ac6 4835 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4836 "Failed to acquire IDC lock, acquired by %d, "
4837 "retrying...\n", lock_owner);
7d613ac6
SV		 4838
4839 /* Retry/Perform IDC-Lock recovery */
4840 if (qla83xx_idc_lock_recovery(base_vha)
4841 == QLA_SUCCESS) {
4842 qla83xx_wait_logic();
4843 goto retry_lock;
4844 } else
4845 ql_log(ql_log_warn, base_vha, 0xb075,
4846 "IDC Lock recovery FAILED.\n");
4847 }
4848
4849 }
4850
4851 return;
4852
4853 /* XXX: IDC-lock implementation using access-control mbx */
4854retry_lock2:
4855 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4856 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4857 "Failed to acquire IDC lock. retrying...\n");
4858 /* Retry/Perform IDC-Lock recovery */
4859 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4860 qla83xx_wait_logic();
4861 goto retry_lock2;
4862 } else
4863 ql_log(ql_log_warn, base_vha, 0xb076,
4864 "IDC Lock recovery FAILED.\n");
4865 }
4866
4867 return;
4868}
4869
4870void
4871qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4872{
5897cb2f
BVA		 4873#if 0
4874 uint16_t options = (requester_id << 15) | BIT_7;
4875#endif
4876 uint16_t retry;
7d613ac6
SV		 4877 uint32_t data;
4878 struct qla_hw_data *ha = base_vha->hw;
4879
4880 /* IDC-unlock implementation using driver-unlock/lock-id
4881 * remote registers
4882 */
4883 retry = 0;
4884retry_unlock:
4885 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4886 == QLA_SUCCESS) {
4887 if (data == ha->portnum) {
4888 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4889 /* Clearing lock-id by setting 0xff */
4890 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4891 } else if (retry < 10) {
4892 /* SV: XXX: IDC unlock retrying needed here? */
4893
4894 /* Retry for IDC-unlock */
4895 qla83xx_wait_logic();
4896 retry++;
4897 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 4898 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4899 goto retry_unlock;
4900 }
4901 } else if (retry < 10) {
4902 /* Retry for IDC-unlock */
4903 qla83xx_wait_logic();
4904 retry++;
4905 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 4906 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 4907 goto retry_unlock;
4908 }
4909
4910 return;
4911
5897cb2f 4912#if 0
7d613ac6
SV		 4913 /* XXX: IDC-unlock implementation using access-control mbx */
4914 retry = 0;
4915retry_unlock2:
4916 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4917 if (retry < 10) {
4918 /* Retry for IDC-unlock */
4919 qla83xx_wait_logic();
4920 retry++;
4921 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 4922 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4923 goto retry_unlock2;
4924 }
4925 }
4926
4927 return;
5897cb2f 4928#endif
7d613ac6
SV		 4929}
4930
4931int
4932__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4933{
4934 int rval = QLA_SUCCESS;
4935 struct qla_hw_data *ha = vha->hw;
4936 uint32_t drv_presence;
4937
4938 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4939 if (rval == QLA_SUCCESS) {
4940 drv_presence |= (1 << ha->portnum);
4941 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4942 drv_presence);
4943 }
4944
4945 return rval;
4946}
4947
4948int
4949qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4950{
4951 int rval = QLA_SUCCESS;
4952
4953 qla83xx_idc_lock(vha, 0);
4954 rval = __qla83xx_set_drv_presence(vha);
4955 qla83xx_idc_unlock(vha, 0);
4956
4957 return rval;
4958}
4959
4960int
4961__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4962{
4963 int rval = QLA_SUCCESS;
4964 struct qla_hw_data *ha = vha->hw;
4965 uint32_t drv_presence;
4966
4967 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4968 if (rval == QLA_SUCCESS) {
4969 drv_presence &= ~(1 << ha->portnum);
4970 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4971 drv_presence);
4972 }
4973
4974 return rval;
4975}
4976
4977int
4978qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4979{
4980 int rval = QLA_SUCCESS;
4981
4982 qla83xx_idc_lock(vha, 0);
4983 rval = __qla83xx_clear_drv_presence(vha);
4984 qla83xx_idc_unlock(vha, 0);
4985
4986 return rval;
4987}
4988
fa492630 4989static void
7d613ac6
SV		 4990qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4991{
4992 struct qla_hw_data *ha = vha->hw;
4993 uint32_t drv_ack, drv_presence;
4994 unsigned long ack_timeout;
4995
4996 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4997 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4998 while (1) {
4999 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5000 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5001 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5002 break;
5003
5004 if (time_after_eq(jiffies, ack_timeout)) {
5005 ql_log(ql_log_warn, vha, 0xb067,
5006 "RESET ACK TIMEOUT! drv_presence=0x%x "
5007 "drv_ack=0x%x\n", drv_presence, drv_ack);
5008 /*
5009 * The function(s) which did not ack in time are forced
5010 * to withdraw any further participation in the IDC
5011 * reset.
5012 */
5013 if (drv_ack != drv_presence)
5014 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5015 drv_ack);
5016 break;
5017 }
5018
5019 qla83xx_idc_unlock(vha, 0);
5020 msleep(1000);
5021 qla83xx_idc_lock(vha, 0);
5022 }
5023
5024 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5025 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5026}
5027
fa492630 5028static int
7d613ac6
SV		 5029qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5030{
5031 int rval = QLA_SUCCESS;
5032 uint32_t idc_control;
5033
5034 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5035 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5036
5037 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5038 __qla83xx_get_idc_control(vha, &idc_control);
5039 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5040 __qla83xx_set_idc_control(vha, 0);
5041
5042 qla83xx_idc_unlock(vha, 0);
5043 rval = qla83xx_restart_nic_firmware(vha);
5044 qla83xx_idc_lock(vha, 0);
5045
5046 if (rval != QLA_SUCCESS) {
5047 ql_log(ql_log_fatal, vha, 0xb06a,
5048 "Failed to restart NIC f/w.\n");
5049 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5050 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5051 } else {
5052 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5053 "Success in restarting nic f/w.\n");
5054 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5055 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5056 }
5057
5058 return rval;
5059}
5060
5061/* Assumes idc_lock always held on entry */
5062int
5063qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5064{
5065 struct qla_hw_data *ha = base_vha->hw;
5066 int rval = QLA_SUCCESS;
5067 unsigned long dev_init_timeout;
5068 uint32_t dev_state;
5069
5070 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5071 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5072
5073 while (1) {
5074
5075 if (time_after_eq(jiffies, dev_init_timeout)) {
5076 ql_log(ql_log_warn, base_vha, 0xb06e,
5077 "Initialization TIMEOUT!\n");
5078 /* Init timeout. Disable further NIC Core
5079 * communication.
5080 */
5081 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5082 QLA8XXX_DEV_FAILED);
5083 ql_log(ql_log_info, base_vha, 0xb06f,
5084 "HW State: FAILED.\n");
5085 }
5086
5087 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5088 switch (dev_state) {
5089 case QLA8XXX_DEV_READY:
5090 if (ha->flags.nic_core_reset_owner)
5091 qla83xx_idc_audit(base_vha,
5092 IDC_AUDIT_COMPLETION);
5093 ha->flags.nic_core_reset_owner = 0;
5094 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5095 "Reset_owner reset by 0x%x.\n",
5096 ha->portnum);
5097 goto exit;
5098 case QLA8XXX_DEV_COLD:
5099 if (ha->flags.nic_core_reset_owner)
5100 rval = qla83xx_device_bootstrap(base_vha);
5101 else {
5102 /* Wait for AEN to change device-state */
5103 qla83xx_idc_unlock(base_vha, 0);
5104 msleep(1000);
5105 qla83xx_idc_lock(base_vha, 0);
5106 }
5107 break;
5108 case QLA8XXX_DEV_INITIALIZING:
5109 /* Wait for AEN to change device-state */
5110 qla83xx_idc_unlock(base_vha, 0);
5111 msleep(1000);
5112 qla83xx_idc_lock(base_vha, 0);
5113 break;
5114 case QLA8XXX_DEV_NEED_RESET:
5115 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5116 qla83xx_need_reset_handler(base_vha);
5117 else {
5118 /* Wait for AEN to change device-state */
5119 qla83xx_idc_unlock(base_vha, 0);
5120 msleep(1000);
5121 qla83xx_idc_lock(base_vha, 0);
5122 }
5123 /* reset timeout value after need reset handler */
5124 dev_init_timeout = jiffies +
5125 (ha->fcoe_dev_init_timeout * HZ);
5126 break;
5127 case QLA8XXX_DEV_NEED_QUIESCENT:
5128 /* XXX: DEBUG for now */
5129 qla83xx_idc_unlock(base_vha, 0);
5130 msleep(1000);
5131 qla83xx_idc_lock(base_vha, 0);
5132 break;
5133 case QLA8XXX_DEV_QUIESCENT:
5134 /* XXX: DEBUG for now */
5135 if (ha->flags.quiesce_owner)
5136 goto exit;
5137
5138 qla83xx_idc_unlock(base_vha, 0);
5139 msleep(1000);
5140 qla83xx_idc_lock(base_vha, 0);
5141 dev_init_timeout = jiffies +
5142 (ha->fcoe_dev_init_timeout * HZ);
5143 break;
5144 case QLA8XXX_DEV_FAILED:
5145 if (ha->flags.nic_core_reset_owner)
5146 qla83xx_idc_audit(base_vha,
5147 IDC_AUDIT_COMPLETION);
5148 ha->flags.nic_core_reset_owner = 0;
5149 __qla83xx_clear_drv_presence(base_vha);
5150 qla83xx_idc_unlock(base_vha, 0);
5151 qla8xxx_dev_failed_handler(base_vha);
5152 rval = QLA_FUNCTION_FAILED;
5153 qla83xx_idc_lock(base_vha, 0);
5154 goto exit;
5155 case QLA8XXX_BAD_VALUE:
5156 qla83xx_idc_unlock(base_vha, 0);
5157 msleep(1000);
5158 qla83xx_idc_lock(base_vha, 0);
5159 break;
5160 default:
5161 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5162 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5163 qla83xx_idc_unlock(base_vha, 0);
5164 qla8xxx_dev_failed_handler(base_vha);
5165 rval = QLA_FUNCTION_FAILED;
5166 qla83xx_idc_lock(base_vha, 0);
5167 goto exit;
5168 }
5169 }
5170
5171exit:
5172 return rval;
5173}
5174
f3ddac19
CD		 5175void
5176qla2x00_disable_board_on_pci_error(struct work_struct *work)
5177{
5178 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5179 board_disable);
5180 struct pci_dev *pdev = ha->pdev;
5181 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5182
783e0dc4
SC		 5183 /* if UNLOAD flag is already set, then continue unload,
5184 * where it was set first.
5185 */
5186 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5187 return;
5188
f3ddac19
CD		 5189 ql_log(ql_log_warn, base_vha, 0x015b,
5190 "Disabling adapter.\n");
5191
5192 set_bit(UNLOADING, &base_vha->dpc_flags);
5193
5194 qla2x00_delete_all_vps(ha, base_vha);
5195
5196 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5197
5198 qla2x00_dfs_remove(base_vha);
5199
5200 qla84xx_put_chip(base_vha);
5201
5202 if (base_vha->timer_active)
5203 qla2x00_stop_timer(base_vha);
5204
5205 base_vha->flags.online = 0;
5206
5207 qla2x00_destroy_deferred_work(ha);
5208
5209 /*
5210 * Do not try to stop beacon blink as it will issue a mailbox
5211 * command.
5212 */
5213 qla2x00_free_sysfs_attr(base_vha, false);
5214
5215 fc_remove_host(base_vha->host);
5216
5217 scsi_remove_host(base_vha->host);
5218
5219 base_vha->flags.init_done = 0;
5220 qla25xx_delete_queues(base_vha);
f3ddac19 5221 qla2x00_free_fcports(base_vha);
093df737 5222 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5223 qla2x00_mem_free(ha);
5224 qla82xx_md_free(base_vha);
5225 qla2x00_free_queues(ha);
5226
f3ddac19
CD		 5227 qla2x00_unmap_iobases(ha);
5228
5229 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5230 pci_disable_pcie_error_reporting(pdev);
5231 pci_disable_device(pdev);
f3ddac19 5232
beb9e315
JL		 5233 /*
5234 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5235 */
f3ddac19
CD		 5236}
5237
1da177e4
LT		 5238/**************************************************************************
5239* qla2x00_do_dpc
5240* This kernel thread is a task that is schedule by the interrupt handler
5241* to perform the background processing for interrupts.
5242*
5243* Notes:
5244* This task always run in the context of a kernel thread. It
5245* is kick-off by the driver's detect code and starts up
5246* up one per adapter. It immediately goes to sleep and waits for
5247* some fibre event. When either the interrupt handler or
5248* the timer routine detects a event it will one of the task
5249* bits then wake us up.
5250**************************************************************************/
5251static int
5252qla2x00_do_dpc(void *data)
5253{
e315cd28
AC		 5254 scsi_qla_host_t *base_vha;
5255 struct qla_hw_data *ha;
d7459527
MH		 5256 uint32_t online;
5257 struct qla_qpair *qpair;
1da177e4 5258
e315cd28
AC		 5259 ha = (struct qla_hw_data *)data;
5260 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5261
8698a745 5262 set_user_nice(current, MIN_NICE);
1da177e4 5263
563585ec 5264 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5265 while (!kthread_should_stop()) {
7c3df132
SK		 5266 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5267 "DPC handler sleeping.\n");
1da177e4 5268
39a11240 5269 schedule();
1da177e4 5270
c142caf0
AV		 5271 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5272 goto end_loop;
1da177e4 5273
85880801 5274 if (ha->flags.eeh_busy) {
7c3df132
SK		 5275 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5276 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5277 goto end_loop;
85880801
AV		 5278 }
5279
1da177e4
LT		 5280 ha->dpc_active = 1;
5281
5f28d2d7
SK		 5282 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5283 "DPC handler waking up, dpc_flags=0x%lx.\n",
5284 base_vha->dpc_flags);
1da177e4 5285
a29b3dd7
JC		 5286 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5287 break;
5288
e315cd28 5289 qla2x00_do_work(base_vha);
0971de7f 5290
7ec0effd
AD		 5291 if (IS_P3P_TYPE(ha)) {
5292 if (IS_QLA8044(ha)) {
5293 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5294 &base_vha->dpc_flags)) {
5295 qla8044_idc_lock(ha);
5296 qla8044_wr_direct(base_vha,
5297 QLA8044_CRB_DEV_STATE_INDEX,
5298 QLA8XXX_DEV_FAILED);
5299 qla8044_idc_unlock(ha);
5300 ql_log(ql_log_info, base_vha, 0x4004,
5301 "HW State: FAILED.\n");
5302 qla8044_device_state_handler(base_vha);
5303 continue;
5304 }
5305
5306 } else {
5307 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5308 &base_vha->dpc_flags)) {
5309 qla82xx_idc_lock(ha);
5310 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5311 QLA8XXX_DEV_FAILED);
5312 qla82xx_idc_unlock(ha);
5313 ql_log(ql_log_info, base_vha, 0x0151,
5314 "HW State: FAILED.\n");
5315 qla82xx_device_state_handler(base_vha);
5316 continue;
5317 }
a9083016
GM		 5318 }
5319
5320 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5321 &base_vha->dpc_flags)) {
5322
7c3df132
SK		 5323 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5324 "FCoE context reset scheduled.\n");
a9083016
GM		 5325 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5326 &base_vha->dpc_flags))) {
5327 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5328 /* FCoE-ctx reset failed.
5329 * Escalate to chip-reset
5330 */
5331 set_bit(ISP_ABORT_NEEDED,
5332 &base_vha->dpc_flags);
5333 }
5334 clear_bit(ABORT_ISP_ACTIVE,
5335 &base_vha->dpc_flags);
5336 }
5337
7c3df132
SK		 5338 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5339 "FCoE context reset end.\n");
a9083016 5340 }
8ae6d9c7
GM		 5341 } else if (IS_QLAFX00(ha)) {
5342 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5343 &base_vha->dpc_flags)) {
5344 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5345 "Firmware Reset Recovery\n");
5346 if (qlafx00_reset_initialize(base_vha)) {
5347 /* Failed. Abort isp later. */
5348 if (!test_bit(UNLOADING,
f92f82d6 5349 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5350 set_bit(ISP_UNRECOVERABLE,
5351 &base_vha->dpc_flags);
5352 ql_dbg(ql_dbg_dpc, base_vha,
5353 0x4021,
5354 "Reset Recovery Failed\n");
f92f82d6 5355 }
8ae6d9c7
GM		 5356 }
5357 }
5358
5359 if (test_and_clear_bit(FX00_TARGET_SCAN,
5360 &base_vha->dpc_flags)) {
5361 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5362 "ISPFx00 Target Scan scheduled\n");
5363 if (qlafx00_rescan_isp(base_vha)) {
5364 if (!test_bit(UNLOADING,
5365 &base_vha->dpc_flags))
5366 set_bit(ISP_UNRECOVERABLE,
5367 &base_vha->dpc_flags);
5368 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5369 "ISPFx00 Target Scan Failed\n");
5370 }
5371 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5372 "ISPFx00 Target Scan End\n");
5373 }
e8f5e95d
AB		 5374 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5375 &base_vha->dpc_flags)) {
5376 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5377 "ISPFx00 Host Info resend scheduled\n");
5378 qlafx00_fx_disc(base_vha,
5379 &base_vha->hw->mr.fcport,
5380 FXDISC_REG_HOST_INFO);
5381 }
a9083016
GM		 5382 }
5383
e315cd28
AC		 5384 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5385 &base_vha->dpc_flags)) {
1da177e4 5386
7c3df132
SK		 5387 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5388 "ISP abort scheduled.\n");
1da177e4 5389 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5390 &base_vha->dpc_flags))) {
1da177e4 5391
a9083016 5392 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5393 /* failed. retry later */
5394 set_bit(ISP_ABORT_NEEDED,
e315cd28 5395 &base_vha->dpc_flags);
99363ef8 5396 }
e315cd28
AC		 5397 clear_bit(ABORT_ISP_ACTIVE,
5398 &base_vha->dpc_flags);
99363ef8
SJ		 5399 }
5400
7c3df132
SK		 5401 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5402 "ISP abort end.\n");
1da177e4
LT		 5403 }
5404
a394aac8
DJ		 5405 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5406 &base_vha->dpc_flags)) {
e315cd28 5407 qla2x00_update_fcports(base_vha);
c9c5ced9 5408 }
d97994dc 5409
2d70c103
NB		 5410 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5411 int ret;
5412 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5413 if (ret != QLA_SUCCESS)
5414 ql_log(ql_log_warn, base_vha, 0x121,
5415 "Failed to enable receiving of RSCN "
5416 "requests: 0x%x.\n", ret);
5417 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5418 }
5419
8ae6d9c7
GM		 5420 if (IS_QLAFX00(ha))
5421 goto loop_resync_check;
5422
579d12b5 5423 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5424 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5425 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5426 if (IS_P3P_TYPE(ha)) {
5427 if (IS_QLA82XX(ha))
5428 qla82xx_device_state_handler(base_vha);
5429 if (IS_QLA8044(ha))
5430 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5431 clear_bit(ISP_QUIESCE_NEEDED,
5432 &base_vha->dpc_flags);
5433 if (!ha->flags.quiesce_owner) {
5434 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5435 if (IS_QLA82XX(ha)) {
5436 qla82xx_idc_lock(ha);
5437 qla82xx_clear_qsnt_ready(
5438 base_vha);
5439 qla82xx_idc_unlock(ha);
5440 } else if (IS_QLA8044(ha)) {
5441 qla8044_idc_lock(ha);
5442 qla8044_clear_qsnt_ready(
5443 base_vha);
5444 qla8044_idc_unlock(ha);
5445 }
8fcd6b8b
CD		 5446 }
5447 } else {
5448 clear_bit(ISP_QUIESCE_NEEDED,
5449 &base_vha->dpc_flags);
5450 qla2x00_quiesce_io(base_vha);
579d12b5 5451 }
7c3df132
SK		 5452 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5453 "Quiescence mode end.\n");
579d12b5
SK		 5454 }
5455
e315cd28 5456 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5457 &base_vha->dpc_flags) &&
e315cd28 5458 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5459
7c3df132
SK		 5460 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5461 "Reset marker scheduled.\n");
e315cd28
AC		 5462 qla2x00_rst_aen(base_vha);
5463 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5464 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5465 "Reset marker end.\n");
1da177e4
LT		 5466 }
5467
5468 /* Retry each device up to login retry count */
e315cd28
AC		 5469 if ((test_and_clear_bit(RELOGIN_NEEDED,
5470 &base_vha->dpc_flags)) &&
5471 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5472 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5473
7c3df132
SK		 5474 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5475 "Relogin scheduled.\n");
e315cd28 5476 qla2x00_relogin(base_vha);
7c3df132
SK		 5477 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5478 "Relogin end.\n");
1da177e4 5479 }
8ae6d9c7 5480loop_resync_check:
e315cd28 5481 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5482 &base_vha->dpc_flags)) {
1da177e4 5483
7c3df132
SK		 5484 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5485 "Loop resync scheduled.\n");
1da177e4
LT		 5486
5487 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5488 &base_vha->dpc_flags))) {
1da177e4 5489
52c82823 5490 qla2x00_loop_resync(base_vha);
1da177e4 5491
e315cd28
AC		 5492 clear_bit(LOOP_RESYNC_ACTIVE,
5493 &base_vha->dpc_flags);
1da177e4
LT		 5494 }
5495
7c3df132
SK		 5496 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5497 "Loop resync end.\n");
1da177e4
LT		 5498 }
5499
8ae6d9c7
GM		 5500 if (IS_QLAFX00(ha))
5501 goto intr_on_check;
5502
e315cd28
AC		 5503 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5504 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5505 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5506 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5507 }
5508
8ae6d9c7 5509intr_on_check:
1da177e4 5510 if (!ha->interrupts_on)
fd34f556 5511 ha->isp_ops->enable_intrs(ha);
1da177e4 5512
e315cd28 5513 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5514 &base_vha->dpc_flags)) {
5515 if (ha->beacon_blink_led == 1)
5516 ha->isp_ops->beacon_blink(base_vha);
5517 }
f6df144c 5518
d7459527
MH		 5519 /* qpair online check */
5520 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5521 &base_vha->dpc_flags)) {
5522 if (ha->flags.eeh_busy ||
5523 ha->flags.pci_channel_io_perm_failure)
5524 online = 0;
5525 else
5526 online = 1;
5527
5528 mutex_lock(&ha->mq_lock);
5529 list_for_each_entry(qpair, &base_vha->qp_list,
5530 qp_list_elem)
5531 qpair->online = online;
5532 mutex_unlock(&ha->mq_lock);
5533 }
5534
8ae6d9c7
GM		 5535 if (!IS_QLAFX00(ha))
5536 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5537
1da177e4 5538 ha->dpc_active = 0;
c142caf0 5539end_loop:
563585ec 5540 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5541 } /* End of while(1) */
563585ec 5542 __set_current_state(TASK_RUNNING);
1da177e4 5543
7c3df132
SK		 5544 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5545 "DPC handler exiting.\n");
1da177e4
LT		 5546
5547 /*
5548 * Make sure that nobody tries to wake us up again.
5549 */
1da177e4
LT		 5550 ha->dpc_active = 0;
5551
ac280b67
AV		 5552 /* Cleanup any residual CTX SRBs. */
5553 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5554
39a11240
CH		 5555 return 0;
5556}
5557
5558void
e315cd28 5559qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5560{
e315cd28 5561 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5562 struct task_struct *t = ha->dpc_thread;
5563
e315cd28 5564 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5565 wake_up_process(t);
1da177e4
LT		 5566}
5567
1da177e4
LT		 5568/*
5569* qla2x00_rst_aen
5570* Processes asynchronous reset.
5571*
5572* Input:
5573* ha = adapter block pointer.
5574*/
5575static void
e315cd28 5576qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5577{
e315cd28
AC		 5578 if (vha->flags.online && !vha->flags.reset_active &&
5579 !atomic_read(&vha->loop_down_timer) &&
5580 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5581 do {
e315cd28 5582 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5583
5584 /*
5585 * Issue marker command only when we are going to start
5586 * the I/O.
5587 */
e315cd28
AC		 5588 vha->marker_needed = 1;
5589 } while (!atomic_read(&vha->loop_down_timer) &&
5590 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5591 }
5592}
5593
1da177e4
LT		 5594/**************************************************************************
5595* qla2x00_timer
5596*
5597* Description:
5598* One second timer
5599*
5600* Context: Interrupt
5601***************************************************************************/
2c3dfe3f 5602void
e315cd28 5603qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5604{
1da177e4 5605 unsigned long cpu_flags = 0;
1da177e4
LT		 5606 int start_dpc = 0;
5607 int index;
5608 srb_t *sp;
85880801 5609 uint16_t w;
e315cd28 5610 struct qla_hw_data *ha = vha->hw;
73208dfd 5611 struct req_que *req;
85880801 5612
a5b36321 5613 if (ha->flags.eeh_busy) {
7c3df132
SK		 5614 ql_dbg(ql_dbg_timer, vha, 0x6000,
5615 "EEH = %d, restarting timer.\n",
5616 ha->flags.eeh_busy);
a5b36321
LC		 5617 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5618 return;
5619 }
5620
f3ddac19
CD		 5621 /*
5622 * Hardware read to raise pending EEH errors during mailbox waits. If
5623 * the read returns -1 then disable the board.
5624 */
5625 if (!pci_channel_offline(ha->pdev)) {
85880801 5626 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5627 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5628 }
1da177e4 5629
cefcaba6 5630 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5631 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5632 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5633 start_dpc++;
7ec0effd
AD		 5634 if (IS_QLA82XX(ha))
5635 qla82xx_watchdog(vha);
5636 else if (IS_QLA8044(ha))
5637 qla8044_watchdog(vha);
579d12b5
SK		 5638 }
5639
8ae6d9c7
GM		 5640 if (!vha->vp_idx && IS_QLAFX00(ha))
5641 qlafx00_timer_routine(vha);
5642
1da177e4 5643 /* Loop down handler. */
e315cd28 5644 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5645 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5646 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5647 && vha->flags.online) {
1da177e4 5648
e315cd28
AC		 5649 if (atomic_read(&vha->loop_down_timer) ==
5650 vha->loop_down_abort_time) {
1da177e4 5651
7c3df132
SK		 5652 ql_log(ql_log_info, vha, 0x6008,
5653 "Loop down - aborting the queues before time expires.\n");
1da177e4 5654
e315cd28
AC		 5655 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5656 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5657
f08b7251
AV		 5658 /*
5659 * Schedule an ISP abort to return any FCP2-device
5660 * commands.
5661 */
2c3dfe3f 5662 /* NPIV - scan physical port only */
e315cd28 5663 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5664 spin_lock_irqsave(&ha->hardware_lock,
5665 cpu_flags);
73208dfd 5666 req = ha->req_q_map[0];
2c3dfe3f 5667 for (index = 1;
8d93f550 5668 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5669 index++) {
5670 fc_port_t *sfcp;
5671
e315cd28 5672 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5673 if (!sp)
5674 continue;
9ba56b95 5675 if (sp->type != SRB_SCSI_CMD)
cf53b069 5676 continue;
2c3dfe3f 5677 sfcp = sp->fcport;
f08b7251 5678 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5679 continue;
bdf79621 5680
8f7daead
GM		 5681 if (IS_QLA82XX(ha))
5682 set_bit(FCOE_CTX_RESET_NEEDED,
5683 &vha->dpc_flags);
5684 else
5685 set_bit(ISP_ABORT_NEEDED,
e315cd28 5686 &vha->dpc_flags);
2c3dfe3f
SJ		 5687 break;
5688 }
5689 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5690 cpu_flags);
1da177e4 5691 }
1da177e4
LT		 5692 start_dpc++;
5693 }
5694
5695 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5696 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5697 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5698 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5699 "Loop down - aborting ISP.\n");
5700
8f7daead
GM		 5701 if (IS_QLA82XX(ha))
5702 set_bit(FCOE_CTX_RESET_NEEDED,
5703 &vha->dpc_flags);
5704 else
5705 set_bit(ISP_ABORT_NEEDED,
5706 &vha->dpc_flags);
1da177e4
LT		 5707 }
5708 }
7c3df132
SK		 5709 ql_dbg(ql_dbg_timer, vha, 0x600a,
5710 "Loop down - seconds remaining %d.\n",
5711 atomic_read(&vha->loop_down_timer));
1da177e4 5712 }
cefcaba6
SK		 5713 /* Check if beacon LED needs to be blinked for physical host only */
5714 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5715 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5716 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5717 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5718 start_dpc++;
5719 }
f6df144c
AV		 5720 }
5721
550bf57d 5722 /* Process any deferred work. */
e315cd28 5723 if (!list_empty(&vha->work_list))
550bf57d
AV		 5724 start_dpc++;
5725
1da177e4 5726 /* Schedule the DPC routine if needed */
e315cd28
AC		 5727 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5728 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5729 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5730 start_dpc ||
e315cd28
AC		 5731 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5732 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5733 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5734 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5735 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5736 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5737 ql_dbg(ql_dbg_timer, vha, 0x600b,
5738 "isp_abort_needed=%d loop_resync_needed=%d "
5739 "fcport_update_needed=%d start_dpc=%d "
5740 "reset_marker_needed=%d",
5741 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5742 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5743 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5744 start_dpc,
5745 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5746 ql_dbg(ql_dbg_timer, vha, 0x600c,
5747 "beacon_blink_needed=%d isp_unrecoverable=%d "
5748 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5749 "relogin_needed=%d.\n",
7c3df132
SK		 5750 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5751 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5752 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5753 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5754 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5755 qla2xxx_wake_dpc(vha);
7c3df132 5756 }
1da177e4 5757
e315cd28 5758 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5759}
5760
5433383e
AV		 5761/* Firmware interface routines. */
5762
f73cb695 5763#define FW_BLOBS 11
5433383e
AV		 5764#define FW_ISP21XX 0
5765#define FW_ISP22XX 1
5766#define FW_ISP2300 2
5767#define FW_ISP2322 3
48c02fde 5768#define FW_ISP24XX 4
c3a2f0df 5769#define FW_ISP25XX 5
3a03eb79 5770#define FW_ISP81XX 6
a9083016 5771#define FW_ISP82XX 7
6246b8a1
GM		 5772#define FW_ISP2031 8
5773#define FW_ISP8031 9
2c5bbbb2 5774#define FW_ISP27XX 10
5433383e 5775
bb8ee499
AV		 5776#define FW_FILE_ISP21XX "ql2100_fw.bin"
5777#define FW_FILE_ISP22XX "ql2200_fw.bin"
5778#define FW_FILE_ISP2300 "ql2300_fw.bin"
5779#define FW_FILE_ISP2322 "ql2322_fw.bin"
5780#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5781#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5782#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5783#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5784#define FW_FILE_ISP2031 "ql2600_fw.bin"
5785#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5786#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5787
bb8ee499 5788
e1e82b6f 5789static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5790
5791static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5792 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5793 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5794 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5795 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5796 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5797 { .name = FW_FILE_ISP25XX, },
3a03eb79 5798 { .name = FW_FILE_ISP81XX, },
a9083016 5799 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5800 { .name = FW_FILE_ISP2031, },
5801 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5802 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5803};
5804
5805struct fw_blob *
e315cd28 5806qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5807{
e315cd28 5808 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5809 struct fw_blob *blob;
5810
5433383e
AV		 5811 if (IS_QLA2100(ha)) {
5812 blob = &qla_fw_blobs[FW_ISP21XX];
5813 } else if (IS_QLA2200(ha)) {
5814 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5815 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5816 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5817 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5818 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5819 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5820 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5821 } else if (IS_QLA25XX(ha)) {
5822 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5823 } else if (IS_QLA81XX(ha)) {
5824 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5825 } else if (IS_QLA82XX(ha)) {
5826 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5827 } else if (IS_QLA2031(ha)) {
5828 blob = &qla_fw_blobs[FW_ISP2031];
5829 } else if (IS_QLA8031(ha)) {
5830 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5831 } else if (IS_QLA27XX(ha)) {
5832 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5833 } else {
5834 return NULL;
5433383e
AV		 5835 }
5836
e1e82b6f 5837 mutex_lock(&qla_fw_lock);
5433383e
AV		 5838 if (blob->fw)
5839 goto out;
5840
5841 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5842 ql_log(ql_log_warn, vha, 0x0063,
5843 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5844 blob->fw = NULL;
5845 blob = NULL;
5846 goto out;
5847 }
5848
5849out:
e1e82b6f 5850 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5851 return blob;
5852}
5853
5854static void
5855qla2x00_release_firmware(void)
5856{
5857 int idx;
5858
e1e82b6f 5859 mutex_lock(&qla_fw_lock);
5433383e 5860 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5861 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5862 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5863}
5864
14e660e6
SJ		 5865static pci_ers_result_t
5866qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5867{
85880801
AV		 5868 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5869 struct qla_hw_data *ha = vha->hw;
5870
7c3df132
SK		 5871 ql_dbg(ql_dbg_aer, vha, 0x9000,
5872 "PCI error detected, state %x.\n", state);
b9b12f73 5873
14e660e6
SJ		 5874 switch (state) {
5875 case pci_channel_io_normal:
85880801 5876 ha->flags.eeh_busy = 0;
d7459527
MH		 5877 if (ql2xmqsupport) {
5878 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5879 qla2xxx_wake_dpc(vha);
5880 }
14e660e6
SJ		 5881 return PCI_ERS_RESULT_CAN_RECOVER;
5882 case pci_channel_io_frozen:
85880801 5883 ha->flags.eeh_busy = 1;
a5b36321
LC		 5884 /* For ISP82XX complete any pending mailbox cmd */
5885 if (IS_QLA82XX(ha)) {
7190575f 5886 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5887 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5888 qla82xx_clear_pending_mbx(vha);
a5b36321 5889 }
90a86fc0 5890 qla2x00_free_irqs(vha);
14e660e6 5891 pci_disable_device(pdev);
bddd2d65
LC		 5892 /* Return back all IOs */
5893 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 5894 if (ql2xmqsupport) {
5895 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5896 qla2xxx_wake_dpc(vha);
5897 }
14e660e6
SJ		 5898 return PCI_ERS_RESULT_NEED_RESET;
5899 case pci_channel_io_perm_failure:
85880801
AV		 5900 ha->flags.pci_channel_io_perm_failure = 1;
5901 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 5902 if (ql2xmqsupport) {
5903 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5904 qla2xxx_wake_dpc(vha);
5905 }
14e660e6
SJ		 5906 return PCI_ERS_RESULT_DISCONNECT;
5907 }
5908 return PCI_ERS_RESULT_NEED_RESET;
5909}
5910
5911static pci_ers_result_t
5912qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5913{
5914 int risc_paused = 0;
5915 uint32_t stat;
5916 unsigned long flags;
e315cd28
AC		 5917 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5918 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5919 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5920 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5921
bcc5b6d3
SK		 5922 if (IS_QLA82XX(ha))
5923 return PCI_ERS_RESULT_RECOVERED;
5924
14e660e6
SJ		 5925 spin_lock_irqsave(&ha->hardware_lock, flags);
5926 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5927 stat = RD_REG_DWORD(&reg->hccr);
5928 if (stat & HCCR_RISC_PAUSE)
5929 risc_paused = 1;
5930 } else if (IS_QLA23XX(ha)) {
5931 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5932 if (stat & HSR_RISC_PAUSED)
5933 risc_paused = 1;
5934 } else if (IS_FWI2_CAPABLE(ha)) {
5935 stat = RD_REG_DWORD(&reg24->host_status);
5936 if (stat & HSRX_RISC_PAUSED)
5937 risc_paused = 1;
5938 }
5939 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5940
5941 if (risc_paused) {
7c3df132
SK		 5942 ql_log(ql_log_info, base_vha, 0x9003,
5943 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5944 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5945
5946 return PCI_ERS_RESULT_NEED_RESET;
5947 } else
5948 return PCI_ERS_RESULT_RECOVERED;
5949}
5950
fa492630
SK		 5951static uint32_t
5952qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5953{
5954 uint32_t rval = QLA_FUNCTION_FAILED;
5955 uint32_t drv_active = 0;
5956 struct qla_hw_data *ha = base_vha->hw;
5957 int fn;
5958 struct pci_dev *other_pdev = NULL;
5959
7c3df132
SK		 5960 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5961 "Entered %s.\n", __func__);
a5b36321
LC		 5962
5963 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5964
5965 if (base_vha->flags.online) {
5966 /* Abort all outstanding commands,
5967 * so as to be requeued later */
5968 qla2x00_abort_isp_cleanup(base_vha);
5969 }
5970
5971
5972 fn = PCI_FUNC(ha->pdev->devfn);
5973 while (fn > 0) {
5974 fn--;
7c3df132
SK		 5975 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5976 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5977 other_pdev =
5978 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5979 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5980 fn));
5981
5982 if (!other_pdev)
5983 continue;
5984 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5985 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5986 "Found PCI func available and enable at 0x%x.\n",
5987 fn);
a5b36321
LC		 5988 pci_dev_put(other_pdev);
5989 break;
5990 }
5991 pci_dev_put(other_pdev);
5992 }
5993
5994 if (!fn) {
5995 /* Reset owner */
7c3df132
SK		 5996 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5997 "This devfn is reset owner = 0x%x.\n",
5998 ha->pdev->devfn);
a5b36321
LC		 5999 qla82xx_idc_lock(ha);
6000
6001 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6002 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6003
6004 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6005 QLA82XX_IDC_VERSION);
6006
6007 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6008 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6009 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6010
6011 qla82xx_idc_unlock(ha);
6012 /* Reset if device is not already reset
6013 * drv_active would be 0 if a reset has already been done
6014 */
6015 if (drv_active)
6016 rval = qla82xx_start_firmware(base_vha);
6017 else
6018 rval = QLA_SUCCESS;
6019 qla82xx_idc_lock(ha);
6020
6021 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6022 ql_log(ql_log_info, base_vha, 0x900b,
6023 "HW State: FAILED.\n");
a5b36321
LC		 6024 qla82xx_clear_drv_active(ha);
6025 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6026 QLA8XXX_DEV_FAILED);
a5b36321 6027 } else {
7c3df132
SK		 6028 ql_log(ql_log_info, base_vha, 0x900c,
6029 "HW State: READY.\n");
a5b36321 6030 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6031 QLA8XXX_DEV_READY);
a5b36321 6032 qla82xx_idc_unlock(ha);
7190575f 6033 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6034 rval = qla82xx_restart_isp(base_vha);
6035 qla82xx_idc_lock(ha);
6036 /* Clear driver state register */
6037 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6038 qla82xx_set_drv_active(base_vha);
6039 }
6040 qla82xx_idc_unlock(ha);
6041 } else {
7c3df132
SK		 6042 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6043 "This devfn is not reset owner = 0x%x.\n",
6044 ha->pdev->devfn);
a5b36321 6045 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6046 QLA8XXX_DEV_READY)) {
7190575f 6047 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6048 rval = qla82xx_restart_isp(base_vha);
6049 qla82xx_idc_lock(ha);
6050 qla82xx_set_drv_active(base_vha);
6051 qla82xx_idc_unlock(ha);
6052 }
6053 }
6054 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6055
6056 return rval;
6057}
6058
14e660e6
SJ		 6059static pci_ers_result_t
6060qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6061{
6062 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6063 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6064 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6065 struct rsp_que *rsp;
6066 int rc, retries = 10;
09483916 6067
7c3df132
SK		 6068 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6069 "Slot Reset.\n");
85880801 6070
90a86fc0
JC		 6071 /* Workaround: qla2xxx driver which access hardware earlier
6072 * needs error state to be pci_channel_io_online.
6073 * Otherwise mailbox command timesout.
6074 */
6075 pdev->error_state = pci_channel_io_normal;
6076
6077 pci_restore_state(pdev);
6078
8c1496bd
RL		 6079 /* pci_restore_state() clears the saved_state flag of the device
6080 * save restored state which resets saved_state flag
6081 */
6082 pci_save_state(pdev);
6083
09483916
BH		 6084 if (ha->mem_only)
6085 rc = pci_enable_device_mem(pdev);
6086 else
6087 rc = pci_enable_device(pdev);
14e660e6 6088
09483916 6089 if (rc) {
7c3df132 6090 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6091 "Can't re-enable PCI device after reset.\n");
a5b36321 6092 goto exit_slot_reset;
14e660e6 6093 }
14e660e6 6094
90a86fc0
JC		 6095 rsp = ha->rsp_q_map[0];
6096 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6097 goto exit_slot_reset;
90a86fc0 6098
e315cd28 6099 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6100 goto exit_slot_reset;
6101
6102 if (IS_QLA82XX(ha)) {
6103 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6104 ret = PCI_ERS_RESULT_RECOVERED;
6105 goto exit_slot_reset;
6106 } else
6107 goto exit_slot_reset;
6108 }
14e660e6 6109
90a86fc0
JC		 6110 while (ha->flags.mbox_busy && retries--)
6111 msleep(1000);
85880801 6112
e315cd28 6113 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6114 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6115 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6116 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6117
90a86fc0 6118
a5b36321 6119exit_slot_reset:
7c3df132
SK		 6120 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6121 "slot_reset return %x.\n", ret);
85880801 6122
14e660e6
SJ		 6123 return ret;
6124}
6125
6126static void
6127qla2xxx_pci_resume(struct pci_dev *pdev)
6128{
e315cd28
AC		 6129 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6130 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6131 int ret;
6132
7c3df132
SK		 6133 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6134 "pci_resume.\n");
85880801 6135
e315cd28 6136 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6137 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6138 ql_log(ql_log_fatal, base_vha, 0x9002,
6139 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6140 }
85880801 6141
3e46f031
LC		 6142 pci_cleanup_aer_uncorrect_error_status(pdev);
6143
85880801 6144 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6145}
6146
2d5a4c34
HM		 6147static void
6148qla83xx_disable_laser(scsi_qla_host_t *vha)
6149{
6150 uint32_t reg, data, fn;
6151 struct qla_hw_data *ha = vha->hw;
6152 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6153
6154 /* pci func #/port # */
6155 ql_dbg(ql_dbg_init, vha, 0x004b,
6156 "Disabling Laser for hba: %p\n", vha);
6157
6158 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6159 (BIT_15|BIT_14|BIT_13|BIT_12));
6160
6161 fn = (fn >> 12);
6162
6163 if (fn & 1)
6164 reg = PORT_1_2031;
6165 else
6166 reg = PORT_0_2031;
6167
6168 data = LASER_OFF_2031;
6169
6170 qla83xx_wr_reg(vha, reg, data);
6171}
6172
5601236b
MH		 6173static int qla2xxx_map_queues(struct Scsi_Host *shost)
6174{
6175 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6176
6177 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6178}
6179
a55b2d21 6180static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6181 .error_detected = qla2xxx_pci_error_detected,
6182 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6183 .slot_reset = qla2xxx_pci_slot_reset,
6184 .resume = qla2xxx_pci_resume,
6185};
6186
5433383e 6187static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6188 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6189 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6190 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6199 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6210 { 0 },
6211};
6212MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6213
fca29703 6214static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6215 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6216 .driver = {
6217 .owner = THIS_MODULE,
6218 },
fca29703 6219 .id_table = qla2xxx_pci_tbl,
7ee61397 6220 .probe = qla2x00_probe_one,
4c993f76 6221 .remove = qla2x00_remove_one,
e30d1756 6222 .shutdown = qla2x00_shutdown,
14e660e6 6223 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6224};
6225
75ef9de1 6226static const struct file_operations apidev_fops = {
6a03b4cd 6227 .owner = THIS_MODULE,
6038f373 6228 .llseek = noop_llseek,
6a03b4cd
HZ		 6229};
6230
1da177e4
LT		 6231/**
6232 * qla2x00_module_init - Module initialization.
6233 **/
6234static int __init
6235qla2x00_module_init(void)
6236{
fca29703
AV		 6237 int ret = 0;
6238
1da177e4 6239 /* Allocate cache for SRBs. */
354d6b21 6240 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6241 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6242 if (srb_cachep == NULL) {
7c3df132
SK		 6243 ql_log(ql_log_fatal, NULL, 0x0001,
6244 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6245 return -ENOMEM;
6246 }
6247
2d70c103
NB		 6248 /* Initialize target kmem_cache and mem_pools */
6249 ret = qlt_init();
6250 if (ret < 0) {
6251 kmem_cache_destroy(srb_cachep);
6252 return ret;
6253 } else if (ret > 0) {
6254 /*
6255 * If initiator mode is explictly disabled by qlt_init(),
6256 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6257 * performing scsi_scan_target() during LOOP UP event.
6258 */
6259 qla2xxx_transport_functions.disable_target_scan = 1;
6260 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6261 }
6262
1da177e4
LT		 6263 /* Derive version string. */
6264 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6265 if (ql2xextended_error_logging)
0181944f
AV		 6266 strcat(qla2x00_version_str, "-debug");
6267
1c97a12a
AV		 6268 qla2xxx_transport_template =
6269 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6270 if (!qla2xxx_transport_template) {
6271 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6272 ql_log(ql_log_fatal, NULL, 0x0002,
6273 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6274 qlt_exit();
1da177e4 6275 return -ENODEV;
2c3dfe3f 6276 }
6a03b4cd
HZ		 6277
6278 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6279 if (apidev_major < 0) {
7c3df132
SK		 6280 ql_log(ql_log_fatal, NULL, 0x0003,
6281 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6282 }
6283
2c3dfe3f
SJ		 6284 qla2xxx_transport_vport_template =
6285 fc_attach_transport(&qla2xxx_transport_vport_functions);
6286 if (!qla2xxx_transport_vport_template) {
6287 kmem_cache_destroy(srb_cachep);
2d70c103 6288 qlt_exit();
2c3dfe3f 6289 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6290 ql_log(ql_log_fatal, NULL, 0x0004,
6291 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6292 return -ENODEV;
2c3dfe3f 6293 }
7c3df132
SK		 6294 ql_log(ql_log_info, NULL, 0x0005,
6295 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6296 qla2x00_version_str);
7ee61397 6297 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6298 if (ret) {
6299 kmem_cache_destroy(srb_cachep);
2d70c103 6300 qlt_exit();
fca29703 6301 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6302 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6303 ql_log(ql_log_fatal, NULL, 0x0006,
6304 "pci_register_driver failed...ret=%d Failing load!.\n",
6305 ret);
fca29703
AV		 6306 }
6307 return ret;
1da177e4
LT		 6308}
6309
6310/**
6311 * qla2x00_module_exit - Module cleanup.
6312 **/
6313static void __exit
6314qla2x00_module_exit(void)
6315{
6a03b4cd 6316 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6317 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6318 qla2x00_release_firmware();
354d6b21 6319 kmem_cache_destroy(srb_cachep);
2d70c103 6320 qlt_exit();
a9083016
GM		 6321 if (ctx_cachep)
6322 kmem_cache_destroy(ctx_cachep);
1da177e4 6323 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6324 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6325}
6326
6327module_init(qla2x00_module_init);
6328module_exit(qla2x00_module_exit);
6329
6330MODULE_AUTHOR("QLogic Corporation");
6331MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6332MODULE_LICENSE("GPL");
6333MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6334MODULE_FIRMWARE(FW_FILE_ISP21XX);
6335MODULE_FIRMWARE(FW_FILE_ISP22XX);
6336MODULE_FIRMWARE(FW_FILE_ISP2300);
6337MODULE_FIRMWARE(FW_FILE_ISP2322);
6338MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6339MODULE_FIRMWARE(FW_FILE_ISP25XX);
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