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qla2xxx: Separate ISP type bits out from device type.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 83module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 84MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 85 "Option to enable extended error logging,\n"
86 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
87 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
88 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
89 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
90 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
91 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
92 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
93 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 94 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
95 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 96 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 97 "\t\t0x1e400000 - Preferred value for capturing essential "
98 "debug information (equivalent to old "
99 "ql2xextended_error_logging=1).\n"
3ce8866c 100 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 101
a9083016 102int ql2xshiftctondsd = 6;
f2019cb1 103module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 104MODULE_PARM_DESC(ql2xshiftctondsd,
105 "Set to control shifting of command type processing "
106 "based on total number of SG elements.");
107
7e47e5ca 108int ql2xfdmienable=1;
de187df8 109module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 110module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 111MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 112 "Enables FDMI registrations. "
113 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 114
50280c01
CD		 115#define MAX_Q_DEPTH 32
116static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 117module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 119 "Maximum queue depth to set for each LUN. "
120 "Default is 32.");
df7baa50 121
9e522cd8
AE		 122int ql2xenabledif = 2;
123module_param(ql2xenabledif, int, S_IRUGO);
bad75002 124MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 125 " Enable T10-CRC-DIF:\n"
126 " Default is 2.\n"
127 " 0 -- No DIF Support\n"
128 " 1 -- Enable DIF for all types\n"
129 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 130
8cb2049c 131int ql2xenablehba_err_chk = 2;
bad75002
AE		 132module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
133MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 134 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 135 " Default is 2.\n"
8cb2049c
AE		 136 " 0 -- Error isolation disabled\n"
137 " 1 -- Error isolation enabled only for DIX Type 0\n"
138 " 2 -- Error isolation enabled for all Types\n");
bad75002 139
e5896bd5 140int ql2xiidmaenable=1;
f2019cb1 141module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 142MODULE_PARM_DESC(ql2xiidmaenable,
143 "Enables iIDMA settings "
144 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
145
73208dfd 146int ql2xmaxqueues = 1;
f2019cb1 147module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 148MODULE_PARM_DESC(ql2xmaxqueues,
149 "Enables MQ settings "
ae68230c
JP		 150 "Default is 1 for single queue. Set it to number "
151 "of queues in MQ mode.");
68ca949c
AC		 152
153int ql2xmultique_tag;
f2019cb1 154module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 155MODULE_PARM_DESC(ql2xmultique_tag,
156 "Enables CPU affinity settings for the driver "
157 "Default is 0 for no affinity of request and response IO. "
158 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 159
160int ql2xfwloadbin;
86e45bf6 161module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 162module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 163MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 164 "Option to specify location from which to load ISP firmware:.\n"
165 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 166 " interface.\n"
167 " 1 -- load firmware from flash.\n"
168 " 0 -- use default semantics.\n");
169
ae97c91e 170int ql2xetsenable;
f2019cb1 171module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 172MODULE_PARM_DESC(ql2xetsenable,
173 "Enables firmware ETS burst."
174 "Default is 0 - skip ETS enablement.");
175
6907869d 176int ql2xdbwr = 1;
86e45bf6 177module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 178MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 179 "Option to specify scheme for request queue posting.\n"
180 " 0 -- Regular doorbell.\n"
181 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 182
f4c496c1 183int ql2xtargetreset = 1;
f2019cb1 184module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 185MODULE_PARM_DESC(ql2xtargetreset,
186 "Enable target reset."
187 "Default is 1 - use hw defaults.");
188
4da26e16 189int ql2xgffidenable;
f2019cb1 190module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 191MODULE_PARM_DESC(ql2xgffidenable,
192 "Enables GFF_ID checks of port type. "
193 "Default is 0 - Do not use GFF_ID information.");
a9083016 194
3822263e 195int ql2xasynctmfenable;
f2019cb1 196module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 197MODULE_PARM_DESC(ql2xasynctmfenable,
198 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
199 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 200
201int ql2xdontresethba;
86e45bf6 202module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 203MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 204 "Option to specify reset behaviour.\n"
205 " 0 (Default) -- Reset on failure.\n"
206 " 1 -- Do not reset on failure.\n");
ed0de87c 207
1abf635d
HR		 208uint64_t ql2xmaxlun = MAX_LUNS;
209module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 210MODULE_PARM_DESC(ql2xmaxlun,
211 "Defines the maximum LU number to register with the SCSI "
212 "midlayer. Default is 65535.");
213
08de2844
GM		 214int ql2xmdcapmask = 0x1F;
215module_param(ql2xmdcapmask, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdcapmask,
217 "Set the Minidump driver capture mask level. "
6e96fa7b 218 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 219
3aadff35 220int ql2xmdenable = 1;
08de2844
GM		 221module_param(ql2xmdenable, int, S_IRUGO);
222MODULE_PARM_DESC(ql2xmdenable,
223 "Enable/disable MiniDump. "
3aadff35
GM		 224 "0 - MiniDump disabled. "
225 "1 (Default) - MiniDump enabled.");
08de2844 226
b0d6cabd
HM		 227int ql2xexlogins = 0;
228module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexlogins,
230 "Number of extended Logins. "
231 "0 (Default)- Disabled.");
232
2f56a7f1
HM		 233int ql2xexchoffld = 0;
234module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
235MODULE_PARM_DESC(ql2xexchoffld,
236 "Number of exchanges to offload. "
237 "0 (Default)- Disabled.");
238
f198cafa
HM		 239int ql2xfwholdabts = 0;
240module_param(ql2xfwholdabts, int, S_IRUGO);
241MODULE_PARM_DESC(ql2xfwholdabts,
242 "Allow FW to hold status IOCB until ABTS rsp received. "
243 "0 (Default) Do not set fw option. "
244 "1 - Set fw option to hold ABTS.");
245
1da177e4 246/*
fa2a1ce5 247 * SCSI host template entry points
1da177e4
LT		 248 */
249static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 250static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 251static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
252static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 253static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 254static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 255static int qla2xxx_eh_abort(struct scsi_cmnd *);
256static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 257static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 258static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
259static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 260
1a2fbf18 261static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 262static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 263static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 264
a5326f86 265struct scsi_host_template qla2xxx_driver_template = {
1da177e4 266 .module = THIS_MODULE,
cb63067a 267 .name = QLA2XXX_DRIVER_NAME,
a5326f86 268 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 269
270 .eh_abort_handler = qla2xxx_eh_abort,
271 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 272 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 273 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
274 .eh_host_reset_handler = qla2xxx_eh_host_reset,
275
276 .slave_configure = qla2xxx_slave_configure,
277
278 .slave_alloc = qla2xxx_slave_alloc,
279 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 280 .scan_finished = qla2xxx_scan_finished,
281 .scan_start = qla2xxx_scan_start,
db5ed4df 282 .change_queue_depth = scsi_change_queue_depth,
fca29703
AV		 283 .this_id = -1,
284 .cmd_per_lun = 3,
285 .use_clustering = ENABLE_CLUSTERING,
286 .sg_tablesize = SG_ALL,
287
288 .max_sectors = 0xFFFF,
afb046e2 289 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 290
291 .supported_mode = MODE_INITIATOR,
c40ecc12 292 .track_queue_depth = 1,
fca29703
AV		 293};
294
1da177e4 295static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 296struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 297
1da177e4
LT		 298/* TODO Convert to inlines
299 *
300 * Timer routines
301 */
1da177e4 302
2c3dfe3f 303__inline__ void
e315cd28 304qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 305{
e315cd28
AC		 306 init_timer(&vha->timer);
307 vha->timer.expires = jiffies + interval * HZ;
308 vha->timer.data = (unsigned long)vha;
309 vha->timer.function = (void (*)(unsigned long))func;
310 add_timer(&vha->timer);
311 vha->timer_active = 1;
1da177e4
LT		 312}
313
314static inline void
e315cd28 315qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 316{
a9083016 317 /* Currently used for 82XX only. */
7c3df132
SK		 318 if (vha->device_flags & DFLG_DEV_FAILED) {
319 ql_dbg(ql_dbg_timer, vha, 0x600d,
320 "Device in a failed state, returning.\n");
a9083016 321 return;
7c3df132 322 }
a9083016 323
e315cd28 324 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 325}
326
a824ebb3 327static __inline__ void
e315cd28 328qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 329{
e315cd28
AC		 330 del_timer_sync(&vha->timer);
331 vha->timer_active = 0;
1da177e4
LT		 332}
333
1da177e4
LT		 334static int qla2x00_do_dpc(void *data);
335
336static void qla2x00_rst_aen(scsi_qla_host_t *);
337
73208dfd
AC		 338static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
339 struct req_que **, struct rsp_que **);
e30d1756 340static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 341static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 342
1da177e4 343/* -------------------------------------------------------------------------- */
9a347ff4
CD		 344static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
345 struct rsp_que *rsp)
73208dfd 346{
7c3df132 347 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 348 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 349 GFP_KERNEL);
350 if (!ha->req_q_map) {
7c3df132
SK		 351 ql_log(ql_log_fatal, vha, 0x003b,
352 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 353 goto fail_req_map;
354 }
355
2afa19a9 356 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 357 GFP_KERNEL);
358 if (!ha->rsp_q_map) {
7c3df132
SK		 359 ql_log(ql_log_fatal, vha, 0x003c,
360 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 361 goto fail_rsp_map;
362 }
9a347ff4
CD		 363 /*
364 * Make sure we record at least the request and response queue zero in
365 * case we need to free them if part of the probe fails.
366 */
367 ha->rsp_q_map[0] = rsp;
368 ha->req_q_map[0] = req;
73208dfd
AC		 369 set_bit(0, ha->rsp_qid_map);
370 set_bit(0, ha->req_qid_map);
371 return 1;
372
373fail_rsp_map:
374 kfree(ha->req_q_map);
375 ha->req_q_map = NULL;
376fail_req_map:
377 return -ENOMEM;
378}
379
2afa19a9 380static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 381{
8ae6d9c7
GM		 382 if (IS_QLAFX00(ha)) {
383 if (req && req->ring_fx00)
384 dma_free_coherent(&ha->pdev->dev,
385 (req->length_fx00 + 1) * sizeof(request_t),
386 req->ring_fx00, req->dma_fx00);
387 } else if (req && req->ring)
73208dfd
AC		 388 dma_free_coherent(&ha->pdev->dev,
389 (req->length + 1) * sizeof(request_t),
390 req->ring, req->dma);
391
8d93f550
CD		 392 if (req)
393 kfree(req->outstanding_cmds);
394
73208dfd
AC		 395 kfree(req);
396 req = NULL;
397}
398
2afa19a9
AC		 399static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
400{
8ae6d9c7
GM		 401 if (IS_QLAFX00(ha)) {
402 if (rsp && rsp->ring)
403 dma_free_coherent(&ha->pdev->dev,
404 (rsp->length_fx00 + 1) * sizeof(request_t),
405 rsp->ring_fx00, rsp->dma_fx00);
406 } else if (rsp && rsp->ring) {
2afa19a9
AC		 407 dma_free_coherent(&ha->pdev->dev,
408 (rsp->length + 1) * sizeof(response_t),
409 rsp->ring, rsp->dma);
8ae6d9c7 410 }
2afa19a9
AC		 411 kfree(rsp);
412 rsp = NULL;
413}
414
73208dfd
AC		 415static void qla2x00_free_queues(struct qla_hw_data *ha)
416{
417 struct req_que *req;
418 struct rsp_que *rsp;
419 int cnt;
420
2afa19a9 421 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 422 if (!test_bit(cnt, ha->req_qid_map))
423 continue;
424
73208dfd 425 req = ha->req_q_map[cnt];
2afa19a9 426 qla2x00_free_req_que(ha, req);
73208dfd 427 }
73208dfd
AC		 428 kfree(ha->req_q_map);
429 ha->req_q_map = NULL;
2afa19a9
AC		 430
431 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 432 if (!test_bit(cnt, ha->rsp_qid_map))
433 continue;
434
2afa19a9
AC		 435 rsp = ha->rsp_q_map[cnt];
436 qla2x00_free_rsp_que(ha, rsp);
437 }
438 kfree(ha->rsp_q_map);
439 ha->rsp_q_map = NULL;
73208dfd
AC		 440}
441
68ca949c
AC		 442static int qla25xx_setup_mode(struct scsi_qla_host *vha)
443{
444 uint16_t options = 0;
445 int ques, req, ret;
446 struct qla_hw_data *ha = vha->hw;
447
7163ea81 448 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 449 ql_log(ql_log_warn, vha, 0x00d8,
450 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 451 goto fail;
452 }
68ca949c 453 if (ql2xmultique_tag) {
68ca949c
AC		 454 /* create a request queue for IO */
455 options |= BIT_7;
456 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
457 QLA_DEFAULT_QUE_QOS);
458 if (!req) {
7c3df132
SK		 459 ql_log(ql_log_warn, vha, 0x00e0,
460 "Failed to create request queue.\n");
68ca949c
AC		 461 goto fail;
462 }
278274d5 463 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 464 vha->req = ha->req_q_map[req];
465 options |= BIT_1;
466 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
467 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
468 if (!ret) {
7c3df132
SK		 469 ql_log(ql_log_warn, vha, 0x00e8,
470 "Failed to create response queue.\n");
68ca949c
AC		 471 goto fail2;
472 }
473 }
7163ea81 474 ha->flags.cpu_affinity_enabled = 1;
7c3df132 475 ql_dbg(ql_dbg_multiq, vha, 0xc007,
6ef68da7 476 "CPU affinity mode enabled, "
7c3df132
SK		 477 "no. of response queues:%d no. of request queues:%d.\n",
478 ha->max_rsp_queues, ha->max_req_queues);
479 ql_dbg(ql_dbg_init, vha, 0x00e9,
6ef68da7 480 "CPU affinity mode enabled, "
7c3df132
SK		 481 "no. of response queues:%d no. of request queues:%d.\n",
482 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 483 }
484 return 0;
485fail2:
486 qla25xx_delete_queues(vha);
7163ea81
AC		 487 destroy_workqueue(ha->wq);
488 ha->wq = NULL;
0cd33fcf 489 vha->req = ha->req_q_map[0];
68ca949c
AC		 490fail:
491 ha->mqenable = 0;
7163ea81
AC		 492 kfree(ha->req_q_map);
493 kfree(ha->rsp_q_map);
494 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 495 return 1;
496}
497
1da177e4 498static char *
e315cd28 499qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 500{
e315cd28 501 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 502 static char *pci_bus_modes[] = {
503 "33", "66", "100", "133",
504 };
505 uint16_t pci_bus;
506
507 strcpy(str, "PCI");
508 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
509 if (pci_bus) {
510 strcat(str, "-X (");
511 strcat(str, pci_bus_modes[pci_bus]);
512 } else {
513 pci_bus = (ha->pci_attr & BIT_8) >> 8;
514 strcat(str, " (");
515 strcat(str, pci_bus_modes[pci_bus]);
516 }
517 strcat(str, " MHz)");
518
519 return (str);
520}
521
fca29703 522static char *
e315cd28 523qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 524{
525 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 526 struct qla_hw_data *ha = vha->hw;
fca29703 527 uint32_t pci_bus;
fca29703 528
62a276f8 529 if (pci_is_pcie(ha->pdev)) {
fca29703 530 char lwstr[6];
62a276f8 531 uint32_t lstat, lspeed, lwidth;
fca29703 532
62a276f8
BH		 533 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
534 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
535 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 536
537 strcpy(str, "PCIe (");
49300af7
SK		 538 switch (lspeed) {
539 case 1:
c87a0d8c 540 strcat(str, "2.5GT/s ");
49300af7
SK		 541 break;
542 case 2:
c87a0d8c 543 strcat(str, "5.0GT/s ");
49300af7
SK		 544 break;
545 case 3:
546 strcat(str, "8.0GT/s ");
547 break;
548 default:
fca29703 549 strcat(str, "<unknown> ");
49300af7
SK		 550 break;
551 }
fca29703
AV		 552 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
553 strcat(str, lwstr);
554
555 return str;
556 }
557
558 strcpy(str, "PCI");
559 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
560 if (pci_bus == 0 || pci_bus == 8) {
561 strcat(str, " (");
562 strcat(str, pci_bus_modes[pci_bus >> 3]);
563 } else {
564 strcat(str, "-X ");
565 if (pci_bus & BIT_2)
566 strcat(str, "Mode 2");
567 else
568 strcat(str, "Mode 1");
569 strcat(str, " (");
570 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
571 }
572 strcat(str, " MHz)");
573
574 return str;
575}
576
e5f82ab8 577static char *
df57caba 578qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 579{
580 char un_str[10];
e315cd28 581 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 582
df57caba
HM		 583 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
584 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 585
586 if (ha->fw_attributes & BIT_9) {
587 strcat(str, "FLX");
588 return (str);
589 }
590
591 switch (ha->fw_attributes & 0xFF) {
592 case 0x7:
593 strcat(str, "EF");
594 break;
595 case 0x17:
596 strcat(str, "TP");
597 break;
598 case 0x37:
599 strcat(str, "IP");
600 break;
601 case 0x77:
602 strcat(str, "VI");
603 break;
604 default:
605 sprintf(un_str, "(%x)", ha->fw_attributes);
606 strcat(str, un_str);
607 break;
608 }
609 if (ha->fw_attributes & 0x100)
610 strcat(str, "X");
611
612 return (str);
613}
614
e5f82ab8 615static char *
df57caba 616qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 617{
e315cd28 618 struct qla_hw_data *ha = vha->hw;
f0883ac6 619
df57caba 620 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 621 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 622 return str;
fca29703
AV		 623}
624
9ba56b95
GM		 625void
626qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 627{
9ba56b95
GM		 628 srb_t *sp = (srb_t *)ptr;
629 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
630 struct qla_hw_data *ha = sp->fcport->vha->hw;
631 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 632
9ba56b95
GM		 633 if (sp->flags & SRB_DMA_VALID) {
634 scsi_dma_unmap(cmd);
635 sp->flags &= ~SRB_DMA_VALID;
7c3df132 636 }
fca29703 637
9ba56b95
GM		 638 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
639 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
640 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
641 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
642 }
643
644 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
645 /* List assured to be having elements */
f83adb61 646 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 647 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
648 }
649
650 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
651 dma_pool_free(ha->dl_dma_pool, ctx,
652 ((struct crc_context *)ctx)->crc_ctx_dma);
653 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
654 }
655
656 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
657 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 658
9ba56b95
GM		 659 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
660 ctx1->fcp_cmnd_dma);
661 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
662 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
663 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
664 mempool_free(ctx1, ha->ctx_mempool);
665 ctx1 = NULL;
666 }
667
668 CMD_SP(cmd) = NULL;
b00ee7d7 669 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 670}
671
14b06808 672static void
9ba56b95
GM		 673qla2x00_sp_compl(void *data, void *ptr, int res)
674{
675 struct qla_hw_data *ha = (struct qla_hw_data *)data;
676 srb_t *sp = (srb_t *)ptr;
677 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
678
679 cmd->result = res;
680
681 if (atomic_read(&sp->ref_count) == 0) {
682 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
683 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
684 sp, GET_CMD_SP(sp));
685 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 686 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 687 return;
688 }
689 if (!atomic_dec_and_test(&sp->ref_count))
690 return;
691
692 qla2x00_sp_free_dma(ha, sp);
693 cmd->scsi_done(cmd);
fca29703
AV		 694}
695
8ae6d9c7
GM		 696/* If we are SP1 here, we need to still take and release the host_lock as SP1
697 * does not have the changes necessary to avoid taking host->host_lock.
698 */
1da177e4 699static int
f5e3e40b 700qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 701{
134ae078 702 scsi_qla_host_t *vha = shost_priv(host);
fca29703 703 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 704 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 705 struct qla_hw_data *ha = vha->hw;
706 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 707 srb_t *sp;
708 int rval;
709
85880801 710 if (ha->flags.eeh_busy) {
7c3df132 711 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 712 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 713 "PCI Channel IO permanent failure, exiting "
714 "cmd=%p.\n", cmd);
b9b12f73 715 cmd->result = DID_NO_CONNECT << 16;
7c3df132 716 } else {
5f28d2d7 717 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 718 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 719 cmd->result = DID_REQUEUE << 16;
7c3df132 720 }
14e660e6
SJ		 721 goto qc24_fail_command;
722 }
723
19a7b4ae
JSEC		 724 rval = fc_remote_port_chkready(rport);
725 if (rval) {
726 cmd->result = rval;
5f28d2d7 727 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 728 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
729 cmd, rval);
fca29703
AV		 730 goto qc24_fail_command;
731 }
732
bad75002
AE		 733 if (!vha->flags.difdix_supported &&
734 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 735 ql_dbg(ql_dbg_io, vha, 0x3004,
736 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
737 cmd);
bad75002
AE		 738 cmd->result = DID_NO_CONNECT << 16;
739 goto qc24_fail_command;
740 }
aa651be8
CD		 741
742 if (!fcport) {
743 cmd->result = DID_NO_CONNECT << 16;
744 goto qc24_fail_command;
745 }
746
fca29703
AV		 747 if (atomic_read(&fcport->state) != FCS_ONLINE) {
748 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 749 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 750 ql_dbg(ql_dbg_io, vha, 0x3005,
751 "Returning DNC, fcport_state=%d loop_state=%d.\n",
752 atomic_read(&fcport->state),
753 atomic_read(&base_vha->loop_state));
fca29703
AV		 754 cmd->result = DID_NO_CONNECT << 16;
755 goto qc24_fail_command;
756 }
7b594131 757 goto qc24_target_busy;
fca29703
AV		 758 }
759
e05fe292
CD		 760 /*
761 * Return target busy if we've received a non-zero retry_delay_timer
762 * in a FCP_RSP.
763 */
975f7d46
BP		 764 if (fcport->retry_delay_timestamp == 0) {
765 /* retry delay not set */
766 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 767 fcport->retry_delay_timestamp = 0;
768 else
769 goto qc24_target_busy;
770
b00ee7d7 771 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 772 if (!sp)
f5e3e40b 773 goto qc24_host_busy;
fca29703 774
9ba56b95
GM		 775 sp->u.scmd.cmd = cmd;
776 sp->type = SRB_SCSI_CMD;
777 atomic_set(&sp->ref_count, 1);
778 CMD_SP(cmd) = (void *)sp;
779 sp->free = qla2x00_sp_free_dma;
780 sp->done = qla2x00_sp_compl;
781
e315cd28 782 rval = ha->isp_ops->start_scsi(sp);
7c3df132 783 if (rval != QLA_SUCCESS) {
53016ed3 784 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 785 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 786 goto qc24_host_busy_free_sp;
7c3df132 787 }
fca29703 788
fca29703
AV		 789 return 0;
790
791qc24_host_busy_free_sp:
9ba56b95 792 qla2x00_sp_free_dma(ha, sp);
fca29703 793
f5e3e40b 794qc24_host_busy:
fca29703
AV		 795 return SCSI_MLQUEUE_HOST_BUSY;
796
7b594131
MC		 797qc24_target_busy:
798 return SCSI_MLQUEUE_TARGET_BUSY;
799
fca29703 800qc24_fail_command:
f5e3e40b 801 cmd->scsi_done(cmd);
fca29703
AV		 802
803 return 0;
804}
805
1da177e4
LT		 806/*
807 * qla2x00_eh_wait_on_command
808 * Waits for the command to be returned by the Firmware for some
809 * max time.
810 *
811 * Input:
1da177e4 812 * cmd = Scsi Command to wait on.
1da177e4
LT		 813 *
814 * Return:
815 * Not Found : 0
816 * Found : 1
817 */
818static int
e315cd28 819qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 820{
fe74c71f 821#define ABORT_POLLING_PERIOD 1000
478c3b03 822#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 823 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 824 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
825 struct qla_hw_data *ha = vha->hw;
f4f051eb 826 int ret = QLA_SUCCESS;
1da177e4 827
85880801 828 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 829 ql_dbg(ql_dbg_taskm, vha, 0x8005,
830 "Return:eh_wait.\n");
85880801
AV		 831 return ret;
832 }
833
d970432c 834 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 835 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 836 }
837 if (CMD_SP(cmd))
838 ret = QLA_FUNCTION_FAILED;
1da177e4 839
f4f051eb 840 return ret;
1da177e4
LT		 841}
842
843/*
844 * qla2x00_wait_for_hba_online
fa2a1ce5 845 * Wait till the HBA is online after going through
1da177e4
LT		 846 * <= MAX_RETRIES_OF_ISP_ABORT or
847 * finally HBA is disabled ie marked offline
848 *
849 * Input:
850 * ha - pointer to host adapter structure
fa2a1ce5
AV		 851 *
852 * Note:
1da177e4
LT		 853 * Does context switching-Release SPIN_LOCK
854 * (if any) before calling this routine.
855 *
856 * Return:
857 * Success (Adapter is online) : 0
858 * Failed (Adapter is offline/disabled) : 1
859 */
854165f4 860int
e315cd28 861qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 862{
fca29703
AV		 863 int return_status;
864 unsigned long wait_online;
e315cd28
AC		 865 struct qla_hw_data *ha = vha->hw;
866 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 867
fa2a1ce5 868 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 869 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
870 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
871 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
872 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 873
874 msleep(1000);
875 }
e315cd28 876 if (base_vha->flags.online)
fa2a1ce5 877 return_status = QLA_SUCCESS;
1da177e4
LT		 878 else
879 return_status = QLA_FUNCTION_FAILED;
880
1da177e4
LT		 881 return (return_status);
882}
883
86fbee86 884/*
638a1a01
SC		 885 * qla2x00_wait_for_hba_ready
886 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 887 *
888 * Input:
889 * ha - pointer to host adapter structure
890 *
891 * Note:
892 * Does context switching-Release SPIN_LOCK
893 * (if any) before calling this routine.
894 *
86fbee86 895 */
638a1a01
SC		 896static void
897qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 898{
86fbee86 899 struct qla_hw_data *ha = vha->hw;
783e0dc4 900 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 901
9d35894d
SC		 902 while (((qla2x00_reset_active(vha)) || ha->dpc_active ||
903 ha->flags.mbox_busy) ||
904 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
783e0dc4
SC		 905 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
906 if (test_bit(UNLOADING, &base_vha->dpc_flags))
907 break;
86fbee86 908 msleep(1000);
783e0dc4 909 }
86fbee86
LC		 910}
911
2533cf67
LC		 912int
913qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
914{
915 int return_status;
916 unsigned long wait_reset;
917 struct qla_hw_data *ha = vha->hw;
918 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
919
920 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
921 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
922 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
923 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
924 ha->dpc_active) && time_before(jiffies, wait_reset)) {
925
926 msleep(1000);
927
928 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
929 ha->flags.chip_reset_done)
930 break;
931 }
932 if (ha->flags.chip_reset_done)
933 return_status = QLA_SUCCESS;
934 else
935 return_status = QLA_FUNCTION_FAILED;
936
937 return return_status;
938}
939
083a469d
GM		 940static void
941sp_get(struct srb *sp)
942{
943 atomic_inc(&sp->ref_count);
944}
945
1da177e4
LT		 946/**************************************************************************
947* qla2xxx_eh_abort
948*
949* Description:
950* The abort function will abort the specified command.
951*
952* Input:
953* cmd = Linux SCSI command packet to be aborted.
954*
955* Returns:
956* Either SUCCESS or FAILED.
957*
958* Note:
2ea00202 959* Only return FAILED if command not returned by firmware.
1da177e4 960**************************************************************************/
e5f82ab8 961static int
1da177e4
LT		 962qla2xxx_eh_abort(struct scsi_cmnd *cmd)
963{
e315cd28 964 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 965 srb_t *sp;
4e98d3b8 966 int ret;
9cb78c16
HR		 967 unsigned int id;
968 uint64_t lun;
18e144d3 969 unsigned long flags;
f934c9d0 970 int rval, wait = 0;
e315cd28 971 struct qla_hw_data *ha = vha->hw;
1da177e4 972
f4f051eb 973 if (!CMD_SP(cmd))
2ea00202 974 return SUCCESS;
1da177e4 975
4e98d3b8
AV		 976 ret = fc_block_scsi_eh(cmd);
977 if (ret != 0)
978 return ret;
979 ret = SUCCESS;
980
f4f051eb
AV		 981 id = cmd->device->id;
982 lun = cmd->device->lun;
1da177e4 983
e315cd28 984 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 985 sp = (srb_t *) CMD_SP(cmd);
986 if (!sp) {
987 spin_unlock_irqrestore(&ha->hardware_lock, flags);
988 return SUCCESS;
989 }
1da177e4 990
7c3df132 991 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 992 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
993 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 994
170babc3
MC		 995 /* Get a reference to the sp and drop the lock.*/
996 sp_get(sp);
083a469d 997
e315cd28 998 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 999 rval = ha->isp_ops->abort_command(sp);
1000 if (rval) {
96219424 1001 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1002 ret = SUCCESS;
96219424 1003 else
f934c9d0
CD		 1004 ret = FAILED;
1005
7c3df132 1006 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1007 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1008 } else {
7c3df132 1009 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1010 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1011 wait = 1;
1012 }
75942064
SK		 1013
1014 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 1015 sp->done(ha, sp, 0);
75942064 1016 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1017
bc91ade9
CD		 1018 /* Did the command return during mailbox execution? */
1019 if (ret == FAILED && !CMD_SP(cmd))
1020 ret = SUCCESS;
1021
f4f051eb 1022 /* Wait for the command to be returned. */
2ea00202 1023 if (wait) {
e315cd28 1024 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1025 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1026 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1027 ret = FAILED;
f4f051eb 1028 }
1da177e4 1029 }
1da177e4 1030
7c3df132 1031 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1032 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1033 vha->host_no, id, lun, wait, ret);
1da177e4 1034
f4f051eb
AV		 1035 return ret;
1036}
1da177e4 1037
4d78c973 1038int
e315cd28 1039qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1040 uint64_t l, enum nexus_wait_type type)
f4f051eb 1041{
17d98630 1042 int cnt, match, status;
18e144d3 1043 unsigned long flags;
e315cd28 1044 struct qla_hw_data *ha = vha->hw;
73208dfd 1045 struct req_que *req;
4d78c973 1046 srb_t *sp;
9ba56b95 1047 struct scsi_cmnd *cmd;
1da177e4 1048
523ec773 1049 status = QLA_SUCCESS;
17d98630 1050
e315cd28 1051 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1052 req = vha->req;
17d98630 1053 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1054 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1055 sp = req->outstanding_cmds[cnt];
1056 if (!sp)
523ec773 1057 continue;
9ba56b95 1058 if (sp->type != SRB_SCSI_CMD)
cf53b069 1059 continue;
17d98630
AC		 1060 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1061 continue;
1062 match = 0;
9ba56b95 1063 cmd = GET_CMD_SP(sp);
17d98630
AC		 1064 switch (type) {
1065 case WAIT_HOST:
1066 match = 1;
1067 break;
1068 case WAIT_TARGET:
9ba56b95 1069 match = cmd->device->id == t;
17d98630
AC		 1070 break;
1071 case WAIT_LUN:
9ba56b95
GM		 1072 match = (cmd->device->id == t &&
1073 cmd->device->lun == l);
17d98630 1074 break;
73208dfd 1075 }
17d98630
AC		 1076 if (!match)
1077 continue;
1078
1079 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1080 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1081 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1082 }
e315cd28 1083 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1084
1085 return status;
1da177e4
LT		 1086}
1087
523ec773
AV		 1088static char *reset_errors[] = {
1089 "HBA not online",
1090 "HBA not ready",
1091 "Task management failed",
1092 "Waiting for command completions",
1093};
1da177e4 1094
e5f82ab8 1095static int
523ec773 1096__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1097 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1098{
e315cd28 1099 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1100 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1101 int err;
1da177e4 1102
7c3df132 1103 if (!fcport) {
523ec773 1104 return FAILED;
7c3df132 1105 }
1da177e4 1106
4e98d3b8
AV		 1107 err = fc_block_scsi_eh(cmd);
1108 if (err != 0)
1109 return err;
1110
7c3df132 1111 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1112 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1113 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1114
523ec773 1115 err = 0;
7c3df132
SK		 1116 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1117 ql_log(ql_log_warn, vha, 0x800a,
1118 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1119 goto eh_reset_failed;
7c3df132 1120 }
523ec773 1121 err = 2;
2afa19a9 1122 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1123 != QLA_SUCCESS) {
1124 ql_log(ql_log_warn, vha, 0x800c,
1125 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1126 goto eh_reset_failed;
7c3df132 1127 }
523ec773 1128 err = 3;
e315cd28 1129 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1130 cmd->device->lun, type) != QLA_SUCCESS) {
1131 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1132 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1133 goto eh_reset_failed;
7c3df132 1134 }
523ec773 1135
7c3df132 1136 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1137 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1138 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1139
1140 return SUCCESS;
1141
4d78c973 1142eh_reset_failed:
7c3df132 1143 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1144 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1145 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1146 cmd);
523ec773
AV		 1147 return FAILED;
1148}
1da177e4 1149
523ec773
AV		 1150static int
1151qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1152{
e315cd28
AC		 1153 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1154 struct qla_hw_data *ha = vha->hw;
1da177e4 1155
523ec773
AV		 1156 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1157 ha->isp_ops->lun_reset);
1da177e4
LT		 1158}
1159
1da177e4 1160static int
523ec773 1161qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1162{
e315cd28
AC		 1163 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1164 struct qla_hw_data *ha = vha->hw;
1da177e4 1165
523ec773
AV		 1166 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1167 ha->isp_ops->target_reset);
1da177e4
LT		 1168}
1169
1da177e4
LT		 1170/**************************************************************************
1171* qla2xxx_eh_bus_reset
1172*
1173* Description:
1174* The bus reset function will reset the bus and abort any executing
1175* commands.
1176*
1177* Input:
1178* cmd = Linux SCSI command packet of the command that cause the
1179* bus reset.
1180*
1181* Returns:
1182* SUCCESS/FAILURE (defined as macro in scsi.h).
1183*
1184**************************************************************************/
e5f82ab8 1185static int
1da177e4
LT		 1186qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1187{
e315cd28 1188 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1189 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1190 int ret = FAILED;
9cb78c16
HR		 1191 unsigned int id;
1192 uint64_t lun;
f4f051eb 1193
f4f051eb
AV		 1194 id = cmd->device->id;
1195 lun = cmd->device->lun;
1da177e4 1196
7c3df132 1197 if (!fcport) {
f4f051eb 1198 return ret;
7c3df132 1199 }
1da177e4 1200
4e98d3b8
AV		 1201 ret = fc_block_scsi_eh(cmd);
1202 if (ret != 0)
1203 return ret;
1204 ret = FAILED;
1205
7c3df132 1206 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1207 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1208
e315cd28 1209 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1210 ql_log(ql_log_fatal, vha, 0x8013,
1211 "Wait for hba online failed board disabled.\n");
f4f051eb 1212 goto eh_bus_reset_done;
1da177e4
LT		 1213 }
1214
ad537689
SK		 1215 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1216 ret = SUCCESS;
1217
f4f051eb
AV		 1218 if (ret == FAILED)
1219 goto eh_bus_reset_done;
1da177e4 1220
9a41a62b 1221 /* Flush outstanding commands. */
4d78c973 1222 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1223 QLA_SUCCESS) {
1224 ql_log(ql_log_warn, vha, 0x8014,
1225 "Wait for pending commands failed.\n");
9a41a62b 1226 ret = FAILED;
7c3df132 1227 }
1da177e4 1228
f4f051eb 1229eh_bus_reset_done:
7c3df132 1230 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1231 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1232 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1233
f4f051eb 1234 return ret;
1da177e4
LT		 1235}
1236
1237/**************************************************************************
1238* qla2xxx_eh_host_reset
1239*
1240* Description:
1241* The reset function will reset the Adapter.
1242*
1243* Input:
1244* cmd = Linux SCSI command packet of the command that cause the
1245* adapter reset.
1246*
1247* Returns:
1248* Either SUCCESS or FAILED.
1249*
1250* Note:
1251**************************************************************************/
e5f82ab8 1252static int
1da177e4
LT		 1253qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1254{
e315cd28 1255 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1256 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1257 int ret = FAILED;
9cb78c16
HR		 1258 unsigned int id;
1259 uint64_t lun;
e315cd28 1260 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1261
f4f051eb
AV		 1262 id = cmd->device->id;
1263 lun = cmd->device->lun;
f4f051eb 1264
7c3df132 1265 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1266 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1267
63ee7072
CD		 1268 /*
1269 * No point in issuing another reset if one is active. Also do not
1270 * attempt a reset if we are updating flash.
1271 */
1272 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1273 goto eh_host_reset_lock;
1da177e4 1274
e315cd28
AC		 1275 if (vha != base_vha) {
1276 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1277 goto eh_host_reset_lock;
e315cd28 1278 } else {
7ec0effd 1279 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1280 if (!qla82xx_fcoe_ctx_reset(vha)) {
1281 /* Ctx reset success */
1282 ret = SUCCESS;
1283 goto eh_host_reset_lock;
1284 }
1285 /* fall thru if ctx reset failed */
1286 }
68ca949c
AC		 1287 if (ha->wq)
1288 flush_workqueue(ha->wq);
1289
e315cd28 1290 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1291 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1292 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1293 /* failed. schedule dpc to try */
1294 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1295
7c3df132
SK		 1296 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1297 ql_log(ql_log_warn, vha, 0x802a,
1298 "wait for hba online failed.\n");
e315cd28 1299 goto eh_host_reset_lock;
7c3df132 1300 }
e315cd28
AC		 1301 }
1302 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1303 }
1da177e4 1304
e315cd28 1305 /* Waiting for command to be returned to OS.*/
4d78c973 1306 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1307 QLA_SUCCESS)
f4f051eb 1308 ret = SUCCESS;
1da177e4 1309
f4f051eb 1310eh_host_reset_lock:
cfb0919c 1311 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1312 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1313 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1314
f4f051eb
AV		 1315 return ret;
1316}
1da177e4
LT		 1317
1318/*
1319* qla2x00_loop_reset
1320* Issue loop reset.
1321*
1322* Input:
1323* ha = adapter block pointer.
1324*
1325* Returns:
1326* 0 = success
1327*/
a4722cf2 1328int
e315cd28 1329qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1330{
0c8c39af 1331 int ret;
bdf79621 1332 struct fc_port *fcport;
e315cd28 1333 struct qla_hw_data *ha = vha->hw;
1da177e4 1334
5854771e
AB		 1335 if (IS_QLAFX00(ha)) {
1336 return qlafx00_loop_reset(vha);
1337 }
1338
f4c496c1 1339 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1340 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1341 if (fcport->port_type != FCT_TARGET)
1342 continue;
1343
1344 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1345 if (ret != QLA_SUCCESS) {
7c3df132 1346 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1347 "Bus Reset failed: Reset=%d "
7c3df132 1348 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1349 }
1350 }
1351 }
1352
8ae6d9c7 1353
6246b8a1 1354 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1355 atomic_set(&vha->loop_state, LOOP_DOWN);
1356 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1357 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1358 ret = qla2x00_full_login_lip(vha);
0c8c39af 1359 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1360 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1361 "full_login_lip=%d.\n", ret);
749af3d5 1362 }
0c8c39af
AV		 1363 }
1364
0d6e61bc 1365 if (ha->flags.enable_lip_reset) {
e315cd28 1366 ret = qla2x00_lip_reset(vha);
ad537689 1367 if (ret != QLA_SUCCESS)
7c3df132
SK		 1368 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1369 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1370 }
1371
1da177e4 1372 /* Issue marker command only when we are going to start the I/O */
e315cd28 1373 vha->marker_needed = 1;
1da177e4 1374
0c8c39af 1375 return QLA_SUCCESS;
1da177e4
LT		 1376}
1377
df4bf0bb 1378void
e315cd28 1379qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1380{
73208dfd 1381 int que, cnt;
df4bf0bb
AV		 1382 unsigned long flags;
1383 srb_t *sp;
e315cd28 1384 struct qla_hw_data *ha = vha->hw;
73208dfd 1385 struct req_que *req;
df4bf0bb 1386
c0cb4496
AE		 1387 qlt_host_reset_handler(ha);
1388
df4bf0bb 1389 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1390 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1391 req = ha->req_q_map[que];
73208dfd
AC		 1392 if (!req)
1393 continue;
8d93f550
CD		 1394 if (!req->outstanding_cmds)
1395 continue;
1396 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1397 sp = req->outstanding_cmds[cnt];
e612d465 1398 if (sp) {
73208dfd 1399 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1400 sp->done(vha, sp, res);
73208dfd 1401 }
df4bf0bb
AV		 1402 }
1403 }
1404 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1405}
1406
f4f051eb
AV		 1407static int
1408qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1409{
bdf79621 1410 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1411
19a7b4ae 1412 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1413 return -ENXIO;
bdf79621 1414
19a7b4ae 1415 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1416
f4f051eb
AV		 1417 return 0;
1418}
1da177e4 1419
f4f051eb
AV		 1420static int
1421qla2xxx_slave_configure(struct scsi_device *sdev)
1422{
e315cd28 1423 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1424 struct req_que *req = vha->req;
8482e118 1425
9e522cd8
AE		 1426 if (IS_T10_PI_CAPABLE(vha->hw))
1427 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1428
db5ed4df 1429 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1430 return 0;
1431}
1da177e4 1432
f4f051eb
AV		 1433static void
1434qla2xxx_slave_destroy(struct scsi_device *sdev)
1435{
1436 sdev->hostdata = NULL;
1da177e4
LT		 1437}
1438
1439/**
1440 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1441 * @ha: HA context
1442 *
1443 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1444 * supported addressing method.
1445 */
1446static void
53303c42 1447qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1448{
7524f9b9 1449 /* Assume a 32bit DMA mask. */
1da177e4 1450 ha->flags.enable_64bit_addressing = 0;
1da177e4 1451
6a35528a 1452 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1453 /* Any upper-dword bits set? */
1454 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1455 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1456 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1457 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1458 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1459 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1460 return;
1da177e4 1461 }
1da177e4 1462 }
7524f9b9 1463
284901a9
YH		 1464 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1465 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1466}
1467
fd34f556 1468static void
e315cd28 1469qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1470{
1471 unsigned long flags = 0;
1472 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1473
1474 spin_lock_irqsave(&ha->hardware_lock, flags);
1475 ha->interrupts_on = 1;
1476 /* enable risc and host interrupts */
1477 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1478 RD_REG_WORD(&reg->ictrl);
1479 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1480
1481}
1482
1483static void
e315cd28 1484qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1485{
1486 unsigned long flags = 0;
1487 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1488
1489 spin_lock_irqsave(&ha->hardware_lock, flags);
1490 ha->interrupts_on = 0;
1491 /* disable risc and host interrupts */
1492 WRT_REG_WORD(&reg->ictrl, 0);
1493 RD_REG_WORD(&reg->ictrl);
1494 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1495}
1496
1497static void
e315cd28 1498qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1499{
1500 unsigned long flags = 0;
1501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1502
1503 spin_lock_irqsave(&ha->hardware_lock, flags);
1504 ha->interrupts_on = 1;
1505 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1506 RD_REG_DWORD(&reg->ictrl);
1507 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1508}
1509
1510static void
e315cd28 1511qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1512{
1513 unsigned long flags = 0;
1514 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1515
124f85e6
AV		 1516 if (IS_NOPOLLING_TYPE(ha))
1517 return;
fd34f556
AV		 1518 spin_lock_irqsave(&ha->hardware_lock, flags);
1519 ha->interrupts_on = 0;
1520 WRT_REG_DWORD(&reg->ictrl, 0);
1521 RD_REG_DWORD(&reg->ictrl);
1522 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1523}
1524
706f457d
GM		 1525static int
1526qla2x00_iospace_config(struct qla_hw_data *ha)
1527{
1528 resource_size_t pio;
1529 uint16_t msix;
1530 int cpus;
1531
706f457d
GM		 1532 if (pci_request_selected_regions(ha->pdev, ha->bars,
1533 QLA2XXX_DRIVER_NAME)) {
1534 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1535 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1536 pci_name(ha->pdev));
1537 goto iospace_error_exit;
1538 }
1539 if (!(ha->bars & 1))
1540 goto skip_pio;
1541
1542 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1543 pio = pci_resource_start(ha->pdev, 0);
1544 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1545 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1546 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1547 "Invalid pci I/O region size (%s).\n",
1548 pci_name(ha->pdev));
1549 pio = 0;
1550 }
1551 } else {
1552 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1553 "Region #0 no a PIO resource (%s).\n",
1554 pci_name(ha->pdev));
1555 pio = 0;
1556 }
1557 ha->pio_address = pio;
1558 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1559 "PIO address=%llu.\n",
1560 (unsigned long long)ha->pio_address);
1561
1562skip_pio:
1563 /* Use MMIO operations for all accesses. */
1564 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1565 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1566 "Region #1 not an MMIO resource (%s), aborting.\n",
1567 pci_name(ha->pdev));
1568 goto iospace_error_exit;
1569 }
1570 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1571 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1572 "Invalid PCI mem region size (%s), aborting.\n",
1573 pci_name(ha->pdev));
1574 goto iospace_error_exit;
1575 }
1576
1577 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1578 if (!ha->iobase) {
1579 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1580 "Cannot remap MMIO (%s), aborting.\n",
1581 pci_name(ha->pdev));
1582 goto iospace_error_exit;
1583 }
1584
1585 /* Determine queue resources */
1586 ha->max_req_queues = ha->max_rsp_queues = 1;
1587 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1588 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1589 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1590 goto mqiobase_exit;
1591
1592 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1593 pci_resource_len(ha->pdev, 3));
1594 if (ha->mqiobase) {
1595 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1596 "MQIO Base=%p.\n", ha->mqiobase);
1597 /* Read MSIX vector size of the board */
1598 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1599 ha->msix_count = msix;
1600 /* Max queues are bounded by available msix vectors */
1601 /* queue 0 uses two msix vectors */
1602 if (ql2xmultique_tag) {
1603 cpus = num_online_cpus();
1604 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1605 (cpus + 1) : (ha->msix_count - 1);
1606 ha->max_req_queues = 2;
1607 } else if (ql2xmaxqueues > 1) {
1608 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1609 QLA_MQ_SIZE : ql2xmaxqueues;
1610 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1611 "QoS mode set, max no of request queues:%d.\n",
1612 ha->max_req_queues);
1613 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1614 "QoS mode set, max no of request queues:%d.\n",
1615 ha->max_req_queues);
1616 }
1617 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1618 "MSI-X vector count: %d.\n", msix);
1619 } else
1620 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1621 "BAR 3 not enabled.\n");
1622
1623mqiobase_exit:
1624 ha->msix_count = ha->max_rsp_queues + 1;
1625 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1626 "MSIX Count:%d.\n", ha->msix_count);
1627 return (0);
1628
1629iospace_error_exit:
1630 return (-ENOMEM);
1631}
1632
1633
6246b8a1
GM		 1634static int
1635qla83xx_iospace_config(struct qla_hw_data *ha)
1636{
1637 uint16_t msix;
1638 int cpus;
1639
1640 if (pci_request_selected_regions(ha->pdev, ha->bars,
1641 QLA2XXX_DRIVER_NAME)) {
1642 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1643 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1644 pci_name(ha->pdev));
1645
1646 goto iospace_error_exit;
1647 }
1648
1649 /* Use MMIO operations for all accesses. */
1650 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1651 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1652 "Invalid pci I/O region size (%s).\n",
1653 pci_name(ha->pdev));
1654 goto iospace_error_exit;
1655 }
1656 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1657 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1658 "Invalid PCI mem region size (%s), aborting\n",
1659 pci_name(ha->pdev));
1660 goto iospace_error_exit;
1661 }
1662
1663 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1664 if (!ha->iobase) {
1665 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1666 "Cannot remap MMIO (%s), aborting.\n",
1667 pci_name(ha->pdev));
1668 goto iospace_error_exit;
1669 }
1670
1671 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1672 /* 83XX 26XX always use MQ type access for queues
1673 * - mbar 2, a.k.a region 4 */
1674 ha->max_req_queues = ha->max_rsp_queues = 1;
1675 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1676 pci_resource_len(ha->pdev, 4));
1677
1678 if (!ha->mqiobase) {
1679 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1680 "BAR2/region4 not enabled\n");
1681 goto mqiobase_exit;
1682 }
1683
1684 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1685 pci_resource_len(ha->pdev, 2));
1686 if (ha->msixbase) {
1687 /* Read MSIX vector size of the board */
1688 pci_read_config_word(ha->pdev,
1689 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1690 ha->msix_count = msix;
1691 /* Max queues are bounded by available msix vectors */
1692 /* queue 0 uses two msix vectors */
1693 if (ql2xmultique_tag) {
1694 cpus = num_online_cpus();
1695 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1696 (cpus + 1) : (ha->msix_count - 1);
1697 ha->max_req_queues = 2;
1698 } else if (ql2xmaxqueues > 1) {
1699 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1700 QLA_MQ_SIZE : ql2xmaxqueues;
1701 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1702 "QoS mode set, max no of request queues:%d.\n",
1703 ha->max_req_queues);
1704 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1705 "QoS mode set, max no of request queues:%d.\n",
1706 ha->max_req_queues);
1707 }
1708 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1709 "MSI-X vector count: %d.\n", msix);
1710 } else
1711 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1712 "BAR 1 not enabled.\n");
1713
1714mqiobase_exit:
1715 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1716
1717 qlt_83xx_iospace_config(ha);
1718
6246b8a1
GM		 1719 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1720 "MSIX Count:%d.\n", ha->msix_count);
1721 return 0;
1722
1723iospace_error_exit:
1724 return -ENOMEM;
1725}
1726
fd34f556
AV		 1727static struct isp_operations qla2100_isp_ops = {
1728 .pci_config = qla2100_pci_config,
1729 .reset_chip = qla2x00_reset_chip,
1730 .chip_diag = qla2x00_chip_diag,
1731 .config_rings = qla2x00_config_rings,
1732 .reset_adapter = qla2x00_reset_adapter,
1733 .nvram_config = qla2x00_nvram_config,
1734 .update_fw_options = qla2x00_update_fw_options,
1735 .load_risc = qla2x00_load_risc,
1736 .pci_info_str = qla2x00_pci_info_str,
1737 .fw_version_str = qla2x00_fw_version_str,
1738 .intr_handler = qla2100_intr_handler,
1739 .enable_intrs = qla2x00_enable_intrs,
1740 .disable_intrs = qla2x00_disable_intrs,
1741 .abort_command = qla2x00_abort_command,
523ec773
AV		 1742 .target_reset = qla2x00_abort_target,
1743 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1744 .fabric_login = qla2x00_login_fabric,
1745 .fabric_logout = qla2x00_fabric_logout,
1746 .calc_req_entries = qla2x00_calc_iocbs_32,
1747 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1748 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1749 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1750 .read_nvram = qla2x00_read_nvram_data,
1751 .write_nvram = qla2x00_write_nvram_data,
1752 .fw_dump = qla2100_fw_dump,
1753 .beacon_on = NULL,
1754 .beacon_off = NULL,
1755 .beacon_blink = NULL,
1756 .read_optrom = qla2x00_read_optrom_data,
1757 .write_optrom = qla2x00_write_optrom_data,
1758 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1759 .start_scsi = qla2x00_start_scsi,
a9083016 1760 .abort_isp = qla2x00_abort_isp,
706f457d 1761 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1762 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1763};
1764
1765static struct isp_operations qla2300_isp_ops = {
1766 .pci_config = qla2300_pci_config,
1767 .reset_chip = qla2x00_reset_chip,
1768 .chip_diag = qla2x00_chip_diag,
1769 .config_rings = qla2x00_config_rings,
1770 .reset_adapter = qla2x00_reset_adapter,
1771 .nvram_config = qla2x00_nvram_config,
1772 .update_fw_options = qla2x00_update_fw_options,
1773 .load_risc = qla2x00_load_risc,
1774 .pci_info_str = qla2x00_pci_info_str,
1775 .fw_version_str = qla2x00_fw_version_str,
1776 .intr_handler = qla2300_intr_handler,
1777 .enable_intrs = qla2x00_enable_intrs,
1778 .disable_intrs = qla2x00_disable_intrs,
1779 .abort_command = qla2x00_abort_command,
523ec773
AV		 1780 .target_reset = qla2x00_abort_target,
1781 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1782 .fabric_login = qla2x00_login_fabric,
1783 .fabric_logout = qla2x00_fabric_logout,
1784 .calc_req_entries = qla2x00_calc_iocbs_32,
1785 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1786 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1787 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1788 .read_nvram = qla2x00_read_nvram_data,
1789 .write_nvram = qla2x00_write_nvram_data,
1790 .fw_dump = qla2300_fw_dump,
1791 .beacon_on = qla2x00_beacon_on,
1792 .beacon_off = qla2x00_beacon_off,
1793 .beacon_blink = qla2x00_beacon_blink,
1794 .read_optrom = qla2x00_read_optrom_data,
1795 .write_optrom = qla2x00_write_optrom_data,
1796 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1797 .start_scsi = qla2x00_start_scsi,
a9083016 1798 .abort_isp = qla2x00_abort_isp,
7ec0effd 1799 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1800 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1801};
1802
1803static struct isp_operations qla24xx_isp_ops = {
1804 .pci_config = qla24xx_pci_config,
1805 .reset_chip = qla24xx_reset_chip,
1806 .chip_diag = qla24xx_chip_diag,
1807 .config_rings = qla24xx_config_rings,
1808 .reset_adapter = qla24xx_reset_adapter,
1809 .nvram_config = qla24xx_nvram_config,
1810 .update_fw_options = qla24xx_update_fw_options,
1811 .load_risc = qla24xx_load_risc,
1812 .pci_info_str = qla24xx_pci_info_str,
1813 .fw_version_str = qla24xx_fw_version_str,
1814 .intr_handler = qla24xx_intr_handler,
1815 .enable_intrs = qla24xx_enable_intrs,
1816 .disable_intrs = qla24xx_disable_intrs,
1817 .abort_command = qla24xx_abort_command,
523ec773
AV		 1818 .target_reset = qla24xx_abort_target,
1819 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1820 .fabric_login = qla24xx_login_fabric,
1821 .fabric_logout = qla24xx_fabric_logout,
1822 .calc_req_entries = NULL,
1823 .build_iocbs = NULL,
1824 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1825 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1826 .read_nvram = qla24xx_read_nvram_data,
1827 .write_nvram = qla24xx_write_nvram_data,
1828 .fw_dump = qla24xx_fw_dump,
1829 .beacon_on = qla24xx_beacon_on,
1830 .beacon_off = qla24xx_beacon_off,
1831 .beacon_blink = qla24xx_beacon_blink,
1832 .read_optrom = qla24xx_read_optrom_data,
1833 .write_optrom = qla24xx_write_optrom_data,
1834 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1835 .start_scsi = qla24xx_start_scsi,
a9083016 1836 .abort_isp = qla2x00_abort_isp,
7ec0effd 1837 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1838 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1839};
1840
c3a2f0df
AV		 1841static struct isp_operations qla25xx_isp_ops = {
1842 .pci_config = qla25xx_pci_config,
1843 .reset_chip = qla24xx_reset_chip,
1844 .chip_diag = qla24xx_chip_diag,
1845 .config_rings = qla24xx_config_rings,
1846 .reset_adapter = qla24xx_reset_adapter,
1847 .nvram_config = qla24xx_nvram_config,
1848 .update_fw_options = qla24xx_update_fw_options,
1849 .load_risc = qla24xx_load_risc,
1850 .pci_info_str = qla24xx_pci_info_str,
1851 .fw_version_str = qla24xx_fw_version_str,
1852 .intr_handler = qla24xx_intr_handler,
1853 .enable_intrs = qla24xx_enable_intrs,
1854 .disable_intrs = qla24xx_disable_intrs,
1855 .abort_command = qla24xx_abort_command,
523ec773
AV		 1856 .target_reset = qla24xx_abort_target,
1857 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1858 .fabric_login = qla24xx_login_fabric,
1859 .fabric_logout = qla24xx_fabric_logout,
1860 .calc_req_entries = NULL,
1861 .build_iocbs = NULL,
1862 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1863 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1864 .read_nvram = qla25xx_read_nvram_data,
1865 .write_nvram = qla25xx_write_nvram_data,
1866 .fw_dump = qla25xx_fw_dump,
1867 .beacon_on = qla24xx_beacon_on,
1868 .beacon_off = qla24xx_beacon_off,
1869 .beacon_blink = qla24xx_beacon_blink,
338c9161 1870 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1871 .write_optrom = qla24xx_write_optrom_data,
1872 .get_flash_version = qla24xx_get_flash_version,
bad75002 1873 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1874 .abort_isp = qla2x00_abort_isp,
7ec0effd 1875 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1876 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1877};
1878
3a03eb79
AV		 1879static struct isp_operations qla81xx_isp_ops = {
1880 .pci_config = qla25xx_pci_config,
1881 .reset_chip = qla24xx_reset_chip,
1882 .chip_diag = qla24xx_chip_diag,
1883 .config_rings = qla24xx_config_rings,
1884 .reset_adapter = qla24xx_reset_adapter,
1885 .nvram_config = qla81xx_nvram_config,
1886 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1887 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1888 .pci_info_str = qla24xx_pci_info_str,
1889 .fw_version_str = qla24xx_fw_version_str,
1890 .intr_handler = qla24xx_intr_handler,
1891 .enable_intrs = qla24xx_enable_intrs,
1892 .disable_intrs = qla24xx_disable_intrs,
1893 .abort_command = qla24xx_abort_command,
1894 .target_reset = qla24xx_abort_target,
1895 .lun_reset = qla24xx_lun_reset,
1896 .fabric_login = qla24xx_login_fabric,
1897 .fabric_logout = qla24xx_fabric_logout,
1898 .calc_req_entries = NULL,
1899 .build_iocbs = NULL,
1900 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1901 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1902 .read_nvram = NULL,
1903 .write_nvram = NULL,
3a03eb79
AV		 1904 .fw_dump = qla81xx_fw_dump,
1905 .beacon_on = qla24xx_beacon_on,
1906 .beacon_off = qla24xx_beacon_off,
6246b8a1 1907 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1908 .read_optrom = qla25xx_read_optrom_data,
1909 .write_optrom = qla24xx_write_optrom_data,
1910 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1911 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1912 .abort_isp = qla2x00_abort_isp,
7ec0effd 1913 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1914 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 1915};
1916
1917static struct isp_operations qla82xx_isp_ops = {
1918 .pci_config = qla82xx_pci_config,
1919 .reset_chip = qla82xx_reset_chip,
1920 .chip_diag = qla24xx_chip_diag,
1921 .config_rings = qla82xx_config_rings,
1922 .reset_adapter = qla24xx_reset_adapter,
1923 .nvram_config = qla81xx_nvram_config,
1924 .update_fw_options = qla24xx_update_fw_options,
1925 .load_risc = qla82xx_load_risc,
9d55ca66 1926 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1927 .fw_version_str = qla24xx_fw_version_str,
1928 .intr_handler = qla82xx_intr_handler,
1929 .enable_intrs = qla82xx_enable_intrs,
1930 .disable_intrs = qla82xx_disable_intrs,
1931 .abort_command = qla24xx_abort_command,
1932 .target_reset = qla24xx_abort_target,
1933 .lun_reset = qla24xx_lun_reset,
1934 .fabric_login = qla24xx_login_fabric,
1935 .fabric_logout = qla24xx_fabric_logout,
1936 .calc_req_entries = NULL,
1937 .build_iocbs = NULL,
1938 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1939 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1940 .read_nvram = qla24xx_read_nvram_data,
1941 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 1942 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 1943 .beacon_on = qla82xx_beacon_on,
1944 .beacon_off = qla82xx_beacon_off,
1945 .beacon_blink = NULL,
a9083016
GM		 1946 .read_optrom = qla82xx_read_optrom_data,
1947 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 1948 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 1949 .start_scsi = qla82xx_start_scsi,
1950 .abort_isp = qla82xx_abort_isp,
706f457d 1951 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 1952 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 1953};
1954
7ec0effd
AD		 1955static struct isp_operations qla8044_isp_ops = {
1956 .pci_config = qla82xx_pci_config,
1957 .reset_chip = qla82xx_reset_chip,
1958 .chip_diag = qla24xx_chip_diag,
1959 .config_rings = qla82xx_config_rings,
1960 .reset_adapter = qla24xx_reset_adapter,
1961 .nvram_config = qla81xx_nvram_config,
1962 .update_fw_options = qla24xx_update_fw_options,
1963 .load_risc = qla82xx_load_risc,
1964 .pci_info_str = qla24xx_pci_info_str,
1965 .fw_version_str = qla24xx_fw_version_str,
1966 .intr_handler = qla8044_intr_handler,
1967 .enable_intrs = qla82xx_enable_intrs,
1968 .disable_intrs = qla82xx_disable_intrs,
1969 .abort_command = qla24xx_abort_command,
1970 .target_reset = qla24xx_abort_target,
1971 .lun_reset = qla24xx_lun_reset,
1972 .fabric_login = qla24xx_login_fabric,
1973 .fabric_logout = qla24xx_fabric_logout,
1974 .calc_req_entries = NULL,
1975 .build_iocbs = NULL,
1976 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1977 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1978 .read_nvram = NULL,
1979 .write_nvram = NULL,
a1b23c5a 1980 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 1981 .beacon_on = qla82xx_beacon_on,
1982 .beacon_off = qla82xx_beacon_off,
1983 .beacon_blink = NULL,
888e639d 1984 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 1985 .write_optrom = qla8044_write_optrom_data,
1986 .get_flash_version = qla82xx_get_flash_version,
1987 .start_scsi = qla82xx_start_scsi,
1988 .abort_isp = qla8044_abort_isp,
1989 .iospace_config = qla82xx_iospace_config,
1990 .initialize_adapter = qla2x00_initialize_adapter,
1991};
1992
6246b8a1
GM		 1993static struct isp_operations qla83xx_isp_ops = {
1994 .pci_config = qla25xx_pci_config,
1995 .reset_chip = qla24xx_reset_chip,
1996 .chip_diag = qla24xx_chip_diag,
1997 .config_rings = qla24xx_config_rings,
1998 .reset_adapter = qla24xx_reset_adapter,
1999 .nvram_config = qla81xx_nvram_config,
2000 .update_fw_options = qla81xx_update_fw_options,
2001 .load_risc = qla81xx_load_risc,
2002 .pci_info_str = qla24xx_pci_info_str,
2003 .fw_version_str = qla24xx_fw_version_str,
2004 .intr_handler = qla24xx_intr_handler,
2005 .enable_intrs = qla24xx_enable_intrs,
2006 .disable_intrs = qla24xx_disable_intrs,
2007 .abort_command = qla24xx_abort_command,
2008 .target_reset = qla24xx_abort_target,
2009 .lun_reset = qla24xx_lun_reset,
2010 .fabric_login = qla24xx_login_fabric,
2011 .fabric_logout = qla24xx_fabric_logout,
2012 .calc_req_entries = NULL,
2013 .build_iocbs = NULL,
2014 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2015 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2016 .read_nvram = NULL,
2017 .write_nvram = NULL,
2018 .fw_dump = qla83xx_fw_dump,
2019 .beacon_on = qla24xx_beacon_on,
2020 .beacon_off = qla24xx_beacon_off,
2021 .beacon_blink = qla83xx_beacon_blink,
2022 .read_optrom = qla25xx_read_optrom_data,
2023 .write_optrom = qla24xx_write_optrom_data,
2024 .get_flash_version = qla24xx_get_flash_version,
2025 .start_scsi = qla24xx_dif_start_scsi,
2026 .abort_isp = qla2x00_abort_isp,
2027 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2028 .initialize_adapter = qla2x00_initialize_adapter,
2029};
2030
2031static struct isp_operations qlafx00_isp_ops = {
2032 .pci_config = qlafx00_pci_config,
2033 .reset_chip = qlafx00_soft_reset,
2034 .chip_diag = qlafx00_chip_diag,
2035 .config_rings = qlafx00_config_rings,
2036 .reset_adapter = qlafx00_soft_reset,
2037 .nvram_config = NULL,
2038 .update_fw_options = NULL,
2039 .load_risc = NULL,
2040 .pci_info_str = qlafx00_pci_info_str,
2041 .fw_version_str = qlafx00_fw_version_str,
2042 .intr_handler = qlafx00_intr_handler,
2043 .enable_intrs = qlafx00_enable_intrs,
2044 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2045 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2046 .target_reset = qlafx00_abort_target,
2047 .lun_reset = qlafx00_lun_reset,
2048 .fabric_login = NULL,
2049 .fabric_logout = NULL,
2050 .calc_req_entries = NULL,
2051 .build_iocbs = NULL,
2052 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2053 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2054 .read_nvram = qla24xx_read_nvram_data,
2055 .write_nvram = qla24xx_write_nvram_data,
2056 .fw_dump = NULL,
2057 .beacon_on = qla24xx_beacon_on,
2058 .beacon_off = qla24xx_beacon_off,
2059 .beacon_blink = NULL,
2060 .read_optrom = qla24xx_read_optrom_data,
2061 .write_optrom = qla24xx_write_optrom_data,
2062 .get_flash_version = qla24xx_get_flash_version,
2063 .start_scsi = qlafx00_start_scsi,
2064 .abort_isp = qlafx00_abort_isp,
2065 .iospace_config = qlafx00_iospace_config,
2066 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2067};
2068
f73cb695
CD		 2069static struct isp_operations qla27xx_isp_ops = {
2070 .pci_config = qla25xx_pci_config,
2071 .reset_chip = qla24xx_reset_chip,
2072 .chip_diag = qla24xx_chip_diag,
2073 .config_rings = qla24xx_config_rings,
2074 .reset_adapter = qla24xx_reset_adapter,
2075 .nvram_config = qla81xx_nvram_config,
2076 .update_fw_options = qla81xx_update_fw_options,
2077 .load_risc = qla81xx_load_risc,
2078 .pci_info_str = qla24xx_pci_info_str,
2079 .fw_version_str = qla24xx_fw_version_str,
2080 .intr_handler = qla24xx_intr_handler,
2081 .enable_intrs = qla24xx_enable_intrs,
2082 .disable_intrs = qla24xx_disable_intrs,
2083 .abort_command = qla24xx_abort_command,
2084 .target_reset = qla24xx_abort_target,
2085 .lun_reset = qla24xx_lun_reset,
2086 .fabric_login = qla24xx_login_fabric,
2087 .fabric_logout = qla24xx_fabric_logout,
2088 .calc_req_entries = NULL,
2089 .build_iocbs = NULL,
2090 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2091 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2092 .read_nvram = NULL,
2093 .write_nvram = NULL,
2094 .fw_dump = qla27xx_fwdump,
2095 .beacon_on = qla24xx_beacon_on,
2096 .beacon_off = qla24xx_beacon_off,
2097 .beacon_blink = qla83xx_beacon_blink,
2098 .read_optrom = qla25xx_read_optrom_data,
2099 .write_optrom = qla24xx_write_optrom_data,
2100 .get_flash_version = qla24xx_get_flash_version,
2101 .start_scsi = qla24xx_dif_start_scsi,
2102 .abort_isp = qla2x00_abort_isp,
2103 .iospace_config = qla83xx_iospace_config,
2104 .initialize_adapter = qla2x00_initialize_adapter,
2105};
2106
ea5b6382 2107static inline void
e315cd28 2108qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2109{
2110 ha->device_type = DT_EXTENDED_IDS;
2111 switch (ha->pdev->device) {
2112 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2113 ha->isp_type |= DT_ISP2100;
ea5b6382 2114 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2115 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2116 break;
2117 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2118 ha->isp_type |= DT_ISP2200;
ea5b6382 2119 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2120 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2121 break;
2122 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2123 ha->isp_type |= DT_ISP2300;
4a59f71d 2124 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2125 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2126 break;
2127 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2128 ha->isp_type |= DT_ISP2312;
4a59f71d 2129 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2130 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2131 break;
2132 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2133 ha->isp_type |= DT_ISP2322;
4a59f71d 2134 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2135 if (ha->pdev->subsystem_vendor == 0x1028 &&
2136 ha->pdev->subsystem_device == 0x0170)
2137 ha->device_type |= DT_OEM_001;
441d1072 2138 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2139 break;
2140 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2141 ha->isp_type |= DT_ISP6312;
441d1072 2142 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2143 break;
2144 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2145 ha->isp_type |= DT_ISP6322;
441d1072 2146 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2147 break;
2148 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2149 ha->isp_type |= DT_ISP2422;
4a59f71d 2150 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2151 ha->device_type |= DT_FWI2;
c76f2c01 2152 ha->device_type |= DT_IIDMA;
441d1072 2153 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2154 break;
2155 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2156 ha->isp_type |= DT_ISP2432;
4a59f71d 2157 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2158 ha->device_type |= DT_FWI2;
c76f2c01 2159 ha->device_type |= DT_IIDMA;
441d1072 2160 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2161 break;
4d4df193 2162 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2163 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2164 ha->device_type |= DT_ZIO_SUPPORTED;
2165 ha->device_type |= DT_FWI2;
2166 ha->device_type |= DT_IIDMA;
2167 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2168 break;
044cc6c8 2169 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2170 ha->isp_type |= DT_ISP5422;
e428924c 2171 ha->device_type |= DT_FWI2;
441d1072 2172 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2173 break;
044cc6c8 2174 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2175 ha->isp_type |= DT_ISP5432;
e428924c 2176 ha->device_type |= DT_FWI2;
441d1072 2177 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2178 break;
c3a2f0df 2179 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2180 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2181 ha->device_type |= DT_ZIO_SUPPORTED;
2182 ha->device_type |= DT_FWI2;
2183 ha->device_type |= DT_IIDMA;
441d1072 2184 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2185 break;
3a03eb79 2186 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2187 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2188 ha->device_type |= DT_ZIO_SUPPORTED;
2189 ha->device_type |= DT_FWI2;
2190 ha->device_type |= DT_IIDMA;
2191 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2192 break;
a9083016 2193 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2194 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2195 ha->device_type |= DT_ZIO_SUPPORTED;
2196 ha->device_type |= DT_FWI2;
2197 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2198 /* Initialize 82XX ISP flags */
2199 qla82xx_init_flags(ha);
2200 break;
7ec0effd 2201 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2202 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2203 ha->device_type |= DT_ZIO_SUPPORTED;
2204 ha->device_type |= DT_FWI2;
2205 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2206 /* Initialize 82XX ISP flags */
2207 qla82xx_init_flags(ha);
2208 break;
6246b8a1 2209 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2210 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2211 ha->device_type |= DT_ZIO_SUPPORTED;
2212 ha->device_type |= DT_FWI2;
2213 ha->device_type |= DT_IIDMA;
2214 ha->device_type |= DT_T10_PI;
2215 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2216 break;
2217 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2218 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2219 ha->device_type |= DT_ZIO_SUPPORTED;
2220 ha->device_type |= DT_FWI2;
2221 ha->device_type |= DT_IIDMA;
2222 ha->device_type |= DT_T10_PI;
2223 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2224 break;
8ae6d9c7 2225 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2226 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2227 break;
f73cb695 2228 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2229 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2230 ha->device_type |= DT_ZIO_SUPPORTED;
2231 ha->device_type |= DT_FWI2;
2232 ha->device_type |= DT_IIDMA;
8ce3f570 2233 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2234 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2235 break;
2c5bbbb2 2236 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2237 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2238 ha->device_type |= DT_ZIO_SUPPORTED;
2239 ha->device_type |= DT_FWI2;
2240 ha->device_type |= DT_IIDMA;
8ce3f570 2241 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2242 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2243 break;
2b48992f 2244 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2245 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2246 ha->device_type |= DT_ZIO_SUPPORTED;
2247 ha->device_type |= DT_FWI2;
2248 ha->device_type |= DT_IIDMA;
8ce3f570 2249 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2250 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2251 break;
ea5b6382 2252 }
e5b68a61 2253
a9083016 2254 if (IS_QLA82XX(ha))
43a9c38b 2255 ha->port_no = ha->portnum & 1;
f73cb695 2256 else {
a9083016
GM		 2257 /* Get adapter physical port no from interrupt pin register. */
2258 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2259 if (IS_QLA27XX(ha))
2260 ha->port_no--;
2261 else
2262 ha->port_no = !(ha->port_no & 1);
2263 }
a9083016 2264
7c3df132 2265 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2266 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2267 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2268}
2269
1e99e33a
AV		 2270static void
2271qla2xxx_scan_start(struct Scsi_Host *shost)
2272{
e315cd28 2273 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2274
cbc8eb67
AV		 2275 if (vha->hw->flags.running_gold_fw)
2276 return;
2277
e315cd28
AC		 2278 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2279 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2280 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2281 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2282}
2283
2284static int
2285qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2286{
e315cd28 2287 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2288
e315cd28 2289 if (!vha->host)
1e99e33a 2290 return 1;
e315cd28 2291 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2292 return 1;
2293
e315cd28 2294 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2295}
2296
1da177e4
LT		 2297/*
2298 * PCI driver interface
2299 */
6f039790 2300static int
7ee61397 2301qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2302{
a1541d5a 2303 int ret = -ENODEV;
1da177e4 2304 struct Scsi_Host *host;
e315cd28
AC		 2305 scsi_qla_host_t *base_vha = NULL;
2306 struct qla_hw_data *ha;
29856e28 2307 char pci_info[30];
7d613ac6 2308 char fw_str[30], wq_name[30];
5433383e 2309 struct scsi_host_template *sht;
642ef983 2310 int bars, mem_only = 0;
e315cd28 2311 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2312 struct req_que *req = NULL;
2313 struct rsp_que *rsp = NULL;
285d0321 2314 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2315 sht = &qla2xxx_driver_template;
5433383e 2316 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2317 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2318 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2319 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2320 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2321 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2322 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2323 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2324 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2325 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2326 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2327 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2328 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2329 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2330 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2331 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2332 mem_only = 1;
7c3df132
SK		 2333 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2334 "Mem only adapter.\n");
285d0321 2335 }
7c3df132
SK		 2336 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2337 "Bars=%d.\n", bars);
285d0321 2338
09483916
BH		 2339 if (mem_only) {
2340 if (pci_enable_device_mem(pdev))
2341 goto probe_out;
2342 } else {
2343 if (pci_enable_device(pdev))
2344 goto probe_out;
2345 }
285d0321 2346
0927678f
JB		 2347 /* This may fail but that's ok */
2348 pci_enable_pcie_error_reporting(pdev);
285d0321 2349
e315cd28
AC		 2350 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2351 if (!ha) {
7c3df132
SK		 2352 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2353 "Unable to allocate memory for ha.\n");
e315cd28 2354 goto probe_out;
1da177e4 2355 }
7c3df132
SK		 2356 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2357 "Memory allocated for ha=%p.\n", ha);
e315cd28 2358 ha->pdev = pdev;
2d70c103 2359 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2360 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2361 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2362 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2363 spin_lock_init(&ha->tgt.atio_lock);
2364
1da177e4
LT		 2365
2366 /* Clear our data area */
285d0321 2367 ha->bars = bars;
09483916 2368 ha->mem_only = mem_only;
df4bf0bb 2369 spin_lock_init(&ha->hardware_lock);
339aa70e 2370 spin_lock_init(&ha->vport_slock);
a9b6f722 2371 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2372 mutex_init(&ha->optrom_mutex);
1da177e4 2373
ea5b6382
AV		 2374 /* Set ISP-type information. */
2375 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2376
2377 /* Set EEH reset type to fundamental if required by hba */
95676112 2378 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2379 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2380 pdev->needs_freset = 1;
ca79cf66 2381
cba1e47f
CD		 2382 ha->prev_topology = 0;
2383 ha->init_cb_size = sizeof(init_cb_t);
2384 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2385 ha->optrom_size = OPTROM_SIZE_2300;
2386
abbd8870 2387 /* Assign ISP specific operations. */
1da177e4 2388 if (IS_QLA2100(ha)) {
642ef983 2389 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2390 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2391 req_length = REQUEST_ENTRY_CNT_2100;
2392 rsp_length = RESPONSE_ENTRY_CNT_2100;
2393 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2394 ha->gid_list_info_size = 4;
3a03eb79
AV		 2395 ha->flash_conf_off = ~0;
2396 ha->flash_data_off = ~0;
2397 ha->nvram_conf_off = ~0;
2398 ha->nvram_data_off = ~0;
fd34f556 2399 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2400 } else if (IS_QLA2200(ha)) {
642ef983 2401 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2402 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2403 req_length = REQUEST_ENTRY_CNT_2200;
2404 rsp_length = RESPONSE_ENTRY_CNT_2100;
2405 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2406 ha->gid_list_info_size = 4;
3a03eb79
AV		 2407 ha->flash_conf_off = ~0;
2408 ha->flash_data_off = ~0;
2409 ha->nvram_conf_off = ~0;
2410 ha->nvram_data_off = ~0;
fd34f556 2411 ha->isp_ops = &qla2100_isp_ops;
fca29703 2412 } else if (IS_QLA23XX(ha)) {
642ef983 2413 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2414 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2415 req_length = REQUEST_ENTRY_CNT_2200;
2416 rsp_length = RESPONSE_ENTRY_CNT_2300;
2417 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2418 ha->gid_list_info_size = 6;
854165f4
AV		 2419 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2420 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2421 ha->flash_conf_off = ~0;
2422 ha->flash_data_off = ~0;
2423 ha->nvram_conf_off = ~0;
2424 ha->nvram_data_off = ~0;
fd34f556 2425 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2426 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2427 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2428 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2429 req_length = REQUEST_ENTRY_CNT_24XX;
2430 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2431 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2432 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2433 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2434 ha->gid_list_info_size = 8;
854165f4 2435 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2436 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2437 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2438 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2439 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2440 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2441 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2442 } else if (IS_QLA25XX(ha)) {
642ef983 2443 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2444 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2445 req_length = REQUEST_ENTRY_CNT_24XX;
2446 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2447 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2448 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2449 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2450 ha->gid_list_info_size = 8;
2451 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2452 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2453 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2454 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2455 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2456 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2457 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2458 } else if (IS_QLA81XX(ha)) {
642ef983 2459 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2460 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2461 req_length = REQUEST_ENTRY_CNT_24XX;
2462 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2463 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2464 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2465 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2466 ha->gid_list_info_size = 8;
2467 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2468 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2469 ha->isp_ops = &qla81xx_isp_ops;
2470 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2471 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2472 ha->nvram_conf_off = ~0;
2473 ha->nvram_data_off = ~0;
a9083016 2474 } else if (IS_QLA82XX(ha)) {
642ef983 2475 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2476 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2477 req_length = REQUEST_ENTRY_CNT_82XX;
2478 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2479 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2480 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2481 ha->gid_list_info_size = 8;
2482 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2483 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2484 ha->isp_ops = &qla82xx_isp_ops;
2485 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2486 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2487 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2488 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2489 } else if (IS_QLA8044(ha)) {
2490 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2491 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2492 req_length = REQUEST_ENTRY_CNT_82XX;
2493 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2494 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2495 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2496 ha->gid_list_info_size = 8;
2497 ha->optrom_size = OPTROM_SIZE_83XX;
2498 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2499 ha->isp_ops = &qla8044_isp_ops;
2500 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2501 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2502 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2503 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2504 } else if (IS_QLA83XX(ha)) {
7d613ac6 2505 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2506 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2507 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2508 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2509 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2510 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2511 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2512 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2513 ha->gid_list_info_size = 8;
2514 ha->optrom_size = OPTROM_SIZE_83XX;
2515 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2516 ha->isp_ops = &qla83xx_isp_ops;
2517 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2518 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2519 ha->nvram_conf_off = ~0;
2520 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2521 } else if (IS_QLAFX00(ha)) {
2522 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2523 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2524 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2525 req_length = REQUEST_ENTRY_CNT_FX00;
2526 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2527 ha->isp_ops = &qlafx00_isp_ops;
2528 ha->port_down_retry_count = 30; /* default value */
2529 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2530 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2531 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2532 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2533 ha->mr.host_info_resend = false;
2534 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2535 } else if (IS_QLA27XX(ha)) {
2536 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2537 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2538 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2539 req_length = REQUEST_ENTRY_CNT_83XX;
2540 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2541 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2542 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2543 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2544 ha->gid_list_info_size = 8;
2545 ha->optrom_size = OPTROM_SIZE_83XX;
2546 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2547 ha->isp_ops = &qla27xx_isp_ops;
2548 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2549 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2550 ha->nvram_conf_off = ~0;
2551 ha->nvram_data_off = ~0;
1da177e4 2552 }
6246b8a1 2553
7c3df132
SK		 2554 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2555 "mbx_count=%d, req_length=%d, "
2556 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2557 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2558 "max_fibre_devices=%d.\n",
7c3df132
SK		 2559 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2560 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2561 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2562 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2563 "isp_ops=%p, flash_conf_off=%d, "
2564 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2565 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2566 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2567
2568 /* Configure PCI I/O space */
2569 ret = ha->isp_ops->iospace_config(ha);
2570 if (ret)
0a63ad12 2571 goto iospace_config_failed;
706f457d
GM		 2572
2573 ql_log_pci(ql_log_info, pdev, 0x001d,
2574 "Found an ISP%04X irq %d iobase 0x%p.\n",
2575 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2576 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2577 init_completion(&ha->mbx_cmd_comp);
2578 complete(&ha->mbx_cmd_comp);
2579 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2580 init_completion(&ha->dcbx_comp);
f356bef1 2581 init_completion(&ha->lb_portup_comp);
1da177e4 2582
2c3dfe3f 2583 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2584
53303c42 2585 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2586 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2587 "64 Bit addressing is %s.\n",
2588 ha->flags.enable_64bit_addressing ? "enable" :
2589 "disable");
73208dfd 2590 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2591 if (ret) {
7c3df132
SK		 2592 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2593 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2594
e315cd28
AC		 2595 goto probe_hw_failed;
2596 }
2597
73208dfd 2598 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2599 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2600 req->max_q_depth = ql2xmaxqdepth;
2601
e315cd28
AC		 2602
2603 base_vha = qla2x00_create_host(sht, ha);
2604 if (!base_vha) {
a1541d5a 2605 ret = -ENOMEM;
6e9f21f3 2606 qla2x00_mem_free(ha);
2afa19a9
AC		 2607 qla2x00_free_req_que(ha, req);
2608 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2609 goto probe_hw_failed;
1da177e4
LT		 2610 }
2611
e315cd28 2612 pci_set_drvdata(pdev, base_vha);
6b383979 2613 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2614
e315cd28 2615 host = base_vha->host;
2afa19a9 2616 base_vha->req = req;
73208dfd 2617 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2618 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2619 else
e315cd28
AC		 2620 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2621 base_vha->vp_idx;
58548cb5 2622
8ae6d9c7
GM		 2623 /* Setup fcport template structure. */
2624 ha->mr.fcport.vha = base_vha;
2625 ha->mr.fcport.port_type = FCT_UNKNOWN;
2626 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2627 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2628 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2629 ha->mr.fcport.scan_state = 1;
2630
58548cb5
GM		 2631 /* Set the SG table size based on ISP type */
2632 if (!IS_FWI2_CAPABLE(ha)) {
2633 if (IS_QLA2100(ha))
2634 host->sg_tablesize = 32;
2635 } else {
2636 if (!IS_QLA82XX(ha))
2637 host->sg_tablesize = QLA_SG_ALL;
2638 }
642ef983 2639 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2640 host->cmd_per_lun = 3;
2641 host->unique_id = host->host_no;
e02587d7 2642 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2643 host->max_cmd_len = 32;
2644 else
2645 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2646 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2647 /* Older HBAs support only 16-bit LUNs */
2648 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2649 ql2xmaxlun > 0xffff)
2650 host->max_lun = 0xffff;
2651 else
2652 host->max_lun = ql2xmaxlun;
e315cd28 2653 host->transportt = qla2xxx_transport_template;
9a069e19 2654 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2655
7c3df132
SK		 2656 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2657 "max_id=%d this_id=%d "
2658 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2659 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2660 host->this_id, host->cmd_per_lun, host->unique_id,
2661 host->max_cmd_len, host->max_channel, host->max_lun,
2662 host->transportt, sht->vendor_id);
2663
9a347ff4
CD		 2664que_init:
2665 /* Alloc arrays of request and response ring ptrs */
2666 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2667 ql_log(ql_log_fatal, base_vha, 0x003d,
2668 "Failed to allocate memory for queue pointers..."
2669 "aborting.\n");
2670 goto probe_init_failed;
2671 }
2672
2d70c103 2673 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2674
73208dfd
AC		 2675 /* Set up the irqs */
2676 ret = qla2x00_request_irqs(ha, rsp);
2677 if (ret)
6e9f21f3 2678 goto probe_init_failed;
90a86fc0
JC		 2679
2680 pci_save_state(pdev);
2681
9a347ff4 2682 /* Assign back pointers */
2afa19a9
AC		 2683 rsp->req = req;
2684 req->rsp = rsp;
9a347ff4 2685
8ae6d9c7
GM		 2686 if (IS_QLAFX00(ha)) {
2687 ha->rsp_q_map[0] = rsp;
2688 ha->req_q_map[0] = req;
2689 set_bit(0, ha->req_qid_map);
2690 set_bit(0, ha->rsp_qid_map);
2691 }
2692
08029990
AV		 2693 /* FWI2-capable only. */
2694 req->req_q_in = &ha->iobase->isp24.req_q_in;
2695 req->req_q_out = &ha->iobase->isp24.req_q_out;
2696 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2697 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2698 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2699 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2700 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2701 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2702 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2703 }
2704
8ae6d9c7
GM		 2705 if (IS_QLAFX00(ha)) {
2706 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2707 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2708 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2709 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2710 }
2711
7ec0effd 2712 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2713 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2714 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2715 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2716 }
2717
7c3df132
SK		 2718 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2719 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2720 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2721 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2722 "req->req_q_in=%p req->req_q_out=%p "
2723 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2724 req->req_q_in, req->req_q_out,
2725 rsp->rsp_q_in, rsp->rsp_q_out);
2726 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2727 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2728 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2729 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2730 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2731 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2732
8ae6d9c7 2733 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2734 ql_log(ql_log_fatal, base_vha, 0x00d6,
2735 "Failed to initialize adapter - Adapter flags %x.\n",
2736 base_vha->device_flags);
1da177e4 2737
a9083016
GM		 2738 if (IS_QLA82XX(ha)) {
2739 qla82xx_idc_lock(ha);
2740 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2741 QLA8XXX_DEV_FAILED);
a9083016 2742 qla82xx_idc_unlock(ha);
7c3df132
SK		 2743 ql_log(ql_log_fatal, base_vha, 0x00d7,
2744 "HW State: FAILED.\n");
7ec0effd
AD		 2745 } else if (IS_QLA8044(ha)) {
2746 qla8044_idc_lock(ha);
2747 qla8044_wr_direct(base_vha,
2748 QLA8044_CRB_DEV_STATE_INDEX,
2749 QLA8XXX_DEV_FAILED);
2750 qla8044_idc_unlock(ha);
2751 ql_log(ql_log_fatal, base_vha, 0x0150,
2752 "HW State: FAILED.\n");
a9083016
GM		 2753 }
2754
a1541d5a 2755 ret = -ENODEV;
1da177e4
LT		 2756 goto probe_failed;
2757 }
2758
3b1bef64
CD		 2759 if (IS_QLAFX00(ha))
2760 host->can_queue = QLAFX00_MAX_CANQUEUE;
2761 else
2762 host->can_queue = req->num_outstanding_cmds - 10;
2763
2764 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2765 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2766 host->can_queue, base_vha->req,
2767 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2768
7163ea81
AC		 2769 if (ha->mqenable) {
2770 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2771 ql_log(ql_log_warn, base_vha, 0x00ec,
2772 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2773 goto que_init;
2774 }
2775 }
68ca949c 2776
cbc8eb67
AV		 2777 if (ha->flags.running_gold_fw)
2778 goto skip_dpc;
2779
1da177e4
LT		 2780 /*
2781 * Startup the kernel thread for this host adapter
2782 */
39a11240 2783 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2784 "%s_dpc", base_vha->host_str);
39a11240 2785 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2786 ql_log(ql_log_fatal, base_vha, 0x00ed,
2787 "Failed to start DPC thread.\n");
39a11240 2788 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2789 goto probe_failed;
2790 }
7c3df132
SK		 2791 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2792 "DPC thread started successfully.\n");
1da177e4 2793
2d70c103
NB		 2794 /*
2795 * If we're not coming up in initiator mode, we might sit for
2796 * a while without waking up the dpc thread, which leads to a
2797 * stuck process warning. So just kick the dpc once here and
2798 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2799 */
2800 qla2xxx_wake_dpc(base_vha);
2801
f3ddac19
CD		 2802 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2803
81178772
SK		 2804 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2805 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2806 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2807 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2808
2809 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2810 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2811 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2812 INIT_WORK(&ha->idc_state_handler,
2813 qla83xx_idc_state_handler_work);
2814 INIT_WORK(&ha->nic_core_unrecoverable,
2815 qla83xx_nic_core_unrecoverable_work);
2816 }
2817
cbc8eb67 2818skip_dpc:
e315cd28
AC		 2819 list_add_tail(&base_vha->list, &ha->vp_list);
2820 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2821
2822 /* Initialized the timer */
e315cd28 2823 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2824 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2825 "Started qla2x00_timer with "
2826 "interval=%d.\n", WATCH_INTERVAL);
2827 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2828 "Detected hba at address=%p.\n",
2829 ha);
d19044c3 2830
e02587d7 2831 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2832 if (ha->fw_attributes & BIT_4) {
9e522cd8 2833 int prot = 0, guard;
bad75002 2834 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2835 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2836 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2837 if (ql2xenabledif == 1)
2838 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2839 scsi_host_set_prot(host,
8cb2049c 2840 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2841 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2842 | SHOST_DIF_TYPE3_PROTECTION
2843 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2844 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2845 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2846
2847 guard = SHOST_DIX_GUARD_CRC;
2848
2849 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2850 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2851 guard |= SHOST_DIX_GUARD_IP;
2852
2853 scsi_host_set_guard(host, guard);
bad75002
AE		 2854 } else
2855 base_vha->flags.difdix_supported = 0;
2856 }
2857
a9083016
GM		 2858 ha->isp_ops->enable_intrs(ha);
2859
1fe19ee4
AB		 2860 if (IS_QLAFX00(ha)) {
2861 ret = qlafx00_fx_disc(base_vha,
2862 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2863 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
2864 QLA_SG_ALL : 128;
2865 }
2866
a1541d5a
AV		 2867 ret = scsi_add_host(host, &pdev->dev);
2868 if (ret)
2869 goto probe_failed;
2870
1486400f
MR		 2871 base_vha->flags.init_done = 1;
2872 base_vha->flags.online = 1;
edaa5c74 2873 ha->prev_minidump_failed = 0;
1486400f 2874
7c3df132
SK		 2875 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2876 "Init done and hba is online.\n");
2877
2d70c103
NB		 2878 if (qla_ini_mode_enabled(base_vha))
2879 scsi_scan_host(host);
2880 else
2881 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2882 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2883
e315cd28 2884 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2885
8ae6d9c7 2886 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 2887 ret = qlafx00_fx_disc(base_vha,
2888 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2889
2890 /* Register system information */
2891 ret = qlafx00_fx_disc(base_vha,
2892 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2893 }
2894
e315cd28 2895 qla2x00_init_host_attr(base_vha);
a1541d5a 2896
e315cd28 2897 qla2x00_dfs_setup(base_vha);
df613b96 2898
03eb912a
AB		 2899 ql_log(ql_log_info, base_vha, 0x00fb,
2900 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2901 ql_log(ql_log_info, base_vha, 0x00fc,
2902 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2903 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2904 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2905 base_vha->host_no,
df57caba 2906 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 2907
2d70c103
NB		 2908 qlt_add_target(ha, base_vha);
2909
6b383979 2910 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 2911
2912 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2913 return -ENODEV;
2914
1da177e4
LT		 2915 return 0;
2916
6e9f21f3 2917probe_init_failed:
2afa19a9 2918 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2919 ha->req_q_map[0] = NULL;
2920 clear_bit(0, ha->req_qid_map);
2afa19a9 2921 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2922 ha->rsp_q_map[0] = NULL;
2923 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2924 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2925
1da177e4 2926probe_failed:
b9978769
AV		 2927 if (base_vha->timer_active)
2928 qla2x00_stop_timer(base_vha);
2929 base_vha->flags.online = 0;
2930 if (ha->dpc_thread) {
2931 struct task_struct *t = ha->dpc_thread;
2932
2933 ha->dpc_thread = NULL;
2934 kthread_stop(t);
2935 }
2936
e315cd28 2937 qla2x00_free_device(base_vha);
1da177e4 2938
e315cd28 2939 scsi_host_put(base_vha->host);
1da177e4 2940
e315cd28 2941probe_hw_failed:
1a2fbf18
JL		 2942 qla2x00_clear_drv_active(ha);
2943
0a63ad12 2944iospace_config_failed:
7ec0effd 2945 if (IS_P3P_TYPE(ha)) {
0a63ad12 2946 if (!ha->nx_pcibase)
f73cb695 2947 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 2948 if (!ql2xdbwr)
f73cb695 2949 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 2950 } else {
2951 if (ha->iobase)
2952 iounmap(ha->iobase);
8ae6d9c7
GM		 2953 if (ha->cregbase)
2954 iounmap(ha->cregbase);
a9083016 2955 }
e315cd28
AC		 2956 pci_release_selected_regions(ha->pdev, ha->bars);
2957 kfree(ha);
2958 ha = NULL;
1da177e4 2959
a1541d5a 2960probe_out:
e315cd28 2961 pci_disable_device(pdev);
a1541d5a 2962 return ret;
1da177e4 2963}
1da177e4 2964
e30d1756
MI		 2965static void
2966qla2x00_shutdown(struct pci_dev *pdev)
2967{
2968 scsi_qla_host_t *vha;
2969 struct qla_hw_data *ha;
2970
552f3f9a
MI		 2971 if (!atomic_read(&pdev->enable_cnt))
2972 return;
2973
e30d1756
MI		 2974 vha = pci_get_drvdata(pdev);
2975 ha = vha->hw;
2976
42479343
AB		 2977 /* Notify ISPFX00 firmware */
2978 if (IS_QLAFX00(ha))
2979 qlafx00_driver_shutdown(vha, 20);
2980
e30d1756
MI		 2981 /* Turn-off FCE trace */
2982 if (ha->flags.fce_enabled) {
2983 qla2x00_disable_fce_trace(vha, NULL, NULL);
2984 ha->flags.fce_enabled = 0;
2985 }
2986
2987 /* Turn-off EFT trace */
2988 if (ha->eft)
2989 qla2x00_disable_eft_trace(vha);
2990
2991 /* Stop currently executing firmware. */
2992 qla2x00_try_to_stop_firmware(vha);
2993
2994 /* Turn adapter off line */
2995 vha->flags.online = 0;
2996
2997 /* turn-off interrupts on the card */
2998 if (ha->interrupts_on) {
2999 vha->flags.init_done = 0;
3000 ha->isp_ops->disable_intrs(ha);
3001 }
3002
3003 qla2x00_free_irqs(vha);
3004
3005 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3006
3007 pci_disable_pcie_error_reporting(pdev);
3008 pci_disable_device(pdev);
e30d1756
MI		 3009}
3010
fe1b806f 3011/* Deletes all the virtual ports for a given ha */
4c993f76 3012static void
fe1b806f 3013qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3014{
fe1b806f 3015 scsi_qla_host_t *vha;
feafb7b1 3016 unsigned long flags;
e315cd28 3017
43ebf16d
AE		 3018 mutex_lock(&ha->vport_lock);
3019 while (ha->cur_vport_count) {
43ebf16d 3020 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3021
43ebf16d
AE		 3022 BUG_ON(base_vha->list.next == &ha->vp_list);
3023 /* This assumes first entry in ha->vp_list is always base vha */
3024 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3025 scsi_host_get(vha->host);
feafb7b1 3026
43ebf16d
AE		 3027 spin_unlock_irqrestore(&ha->vport_slock, flags);
3028 mutex_unlock(&ha->vport_lock);
3029
3030 fc_vport_terminate(vha->fc_vport);
3031 scsi_host_put(vha->host);
feafb7b1 3032
43ebf16d 3033 mutex_lock(&ha->vport_lock);
e315cd28 3034 }
43ebf16d 3035 mutex_unlock(&ha->vport_lock);
fe1b806f 3036}
1da177e4 3037
fe1b806f
CD		 3038/* Stops all deferred work threads */
3039static void
3040qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3041{
68ca949c
AC		 3042 /* Flush the work queue and remove it */
3043 if (ha->wq) {
3044 flush_workqueue(ha->wq);
3045 destroy_workqueue(ha->wq);
3046 ha->wq = NULL;
3047 }
3048
7d613ac6
SV		 3049 /* Cancel all work and destroy DPC workqueues */
3050 if (ha->dpc_lp_wq) {
3051 cancel_work_sync(&ha->idc_aen);
3052 destroy_workqueue(ha->dpc_lp_wq);
3053 ha->dpc_lp_wq = NULL;
3054 }
3055
3056 if (ha->dpc_hp_wq) {
3057 cancel_work_sync(&ha->nic_core_reset);
3058 cancel_work_sync(&ha->idc_state_handler);
3059 cancel_work_sync(&ha->nic_core_unrecoverable);
3060 destroy_workqueue(ha->dpc_hp_wq);
3061 ha->dpc_hp_wq = NULL;
3062 }
3063
b9978769
AV		 3064 /* Kill the kernel thread for this host */
3065 if (ha->dpc_thread) {
3066 struct task_struct *t = ha->dpc_thread;
3067
3068 /*
3069 * qla2xxx_wake_dpc checks for ->dpc_thread
3070 * so we need to zero it out.
3071 */
3072 ha->dpc_thread = NULL;
3073 kthread_stop(t);
3074 }
fe1b806f 3075}
1da177e4 3076
fe1b806f
CD		 3077static void
3078qla2x00_unmap_iobases(struct qla_hw_data *ha)
3079{
a9083016 3080 if (IS_QLA82XX(ha)) {
b963752f 3081
f73cb695 3082 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3083 if (!ql2xdbwr)
f73cb695 3084 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3085 } else {
3086 if (ha->iobase)
3087 iounmap(ha->iobase);
1da177e4 3088
8ae6d9c7
GM		 3089 if (ha->cregbase)
3090 iounmap(ha->cregbase);
3091
a9083016
GM		 3092 if (ha->mqiobase)
3093 iounmap(ha->mqiobase);
6246b8a1 3094
f73cb695 3095 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3096 iounmap(ha->msixbase);
a9083016 3097 }
fe1b806f
CD		 3098}
3099
3100static void
db7157d4 3101qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3102{
fe1b806f
CD		 3103 if (IS_QLA8044(ha)) {
3104 qla8044_idc_lock(ha);
c41afc9a 3105 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3106 qla8044_idc_unlock(ha);
3107 } else if (IS_QLA82XX(ha)) {
3108 qla82xx_idc_lock(ha);
3109 qla82xx_clear_drv_active(ha);
3110 qla82xx_idc_unlock(ha);
3111 }
3112}
3113
3114static void
3115qla2x00_remove_one(struct pci_dev *pdev)
3116{
3117 scsi_qla_host_t *base_vha;
3118 struct qla_hw_data *ha;
3119
beb9e315
JL		 3120 base_vha = pci_get_drvdata(pdev);
3121 ha = base_vha->hw;
3122
3123 /* Indicate device removal to prevent future board_disable and wait
3124 * until any pending board_disable has completed. */
3125 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3126 cancel_work_sync(&ha->board_disable);
3127
fe1b806f 3128 /*
beb9e315
JL		 3129 * If the PCI device is disabled then there was a PCI-disconnect and
3130 * qla2x00_disable_board_on_pci_error has taken care of most of the
3131 * resources.
fe1b806f 3132 */
beb9e315
JL		 3133 if (!atomic_read(&pdev->enable_cnt)) {
3134 scsi_host_put(base_vha->host);
3135 kfree(ha);
3136 pci_set_drvdata(pdev, NULL);
fe1b806f 3137 return;
beb9e315 3138 }
fe1b806f 3139
638a1a01
SC		 3140 qla2x00_wait_for_hba_ready(base_vha);
3141
783e0dc4
SC		 3142 /* if UNLOAD flag is already set, then continue unload,
3143 * where it was set first.
3144 */
3145 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3146 return;
3147
fe1b806f
CD		 3148 set_bit(UNLOADING, &base_vha->dpc_flags);
3149
3150 if (IS_QLAFX00(ha))
3151 qlafx00_driver_shutdown(base_vha, 20);
3152
3153 qla2x00_delete_all_vps(ha, base_vha);
3154
3155 if (IS_QLA8031(ha)) {
3156 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3157 "Clearing fcoe driver presence.\n");
3158 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3159 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3160 "Error while clearing DRV-Presence.\n");
3161 }
3162
3163 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3164
3165 qla2x00_dfs_remove(base_vha);
3166
3167 qla84xx_put_chip(base_vha);
3168
2d5a4c34
HM		 3169 /* Laser should be disabled only for ISP2031 */
3170 if (IS_QLA2031(ha))
3171 qla83xx_disable_laser(base_vha);
3172
fe1b806f
CD		 3173 /* Disable timer */
3174 if (base_vha->timer_active)
3175 qla2x00_stop_timer(base_vha);
3176
3177 base_vha->flags.online = 0;
3178
b0d6cabd
HM		 3179 /* free DMA memory */
3180 if (ha->exlogin_buf)
3181 qla2x00_free_exlogin_buffer(ha);
3182
2f56a7f1
HM		 3183 /* free DMA memory */
3184 if (ha->exchoffld_buf)
3185 qla2x00_free_exchoffld_buffer(ha);
3186
fe1b806f
CD		 3187 qla2x00_destroy_deferred_work(ha);
3188
3189 qlt_remove_target(ha, base_vha);
3190
3191 qla2x00_free_sysfs_attr(base_vha, true);
3192
3193 fc_remove_host(base_vha->host);
3194
3195 scsi_remove_host(base_vha->host);
3196
3197 qla2x00_free_device(base_vha);
3198
db7157d4 3199 qla2x00_clear_drv_active(ha);
fe1b806f 3200
d2749ffa
AE		 3201 scsi_host_put(base_vha->host);
3202
fe1b806f 3203 qla2x00_unmap_iobases(ha);
73208dfd 3204
e315cd28
AC		 3205 pci_release_selected_regions(ha->pdev, ha->bars);
3206 kfree(ha);
3207 ha = NULL;
1da177e4 3208
90a86fc0
JC		 3209 pci_disable_pcie_error_reporting(pdev);
3210
665db93b 3211 pci_disable_device(pdev);
1da177e4 3212}
1da177e4
LT		 3213
3214static void
e315cd28 3215qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3216{
e315cd28 3217 struct qla_hw_data *ha = vha->hw;
1da177e4 3218
85880801
AV		 3219 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3220
3221 /* Disable timer */
3222 if (vha->timer_active)
3223 qla2x00_stop_timer(vha);
3224
2afa19a9 3225 qla25xx_delete_queues(vha);
fe1b806f 3226
df613b96 3227 if (ha->flags.fce_enabled)
e315cd28 3228 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3229
a7a167bf 3230 if (ha->eft)
e315cd28 3231 qla2x00_disable_eft_trace(vha);
a7a167bf 3232
f6ef3b18 3233 /* Stop currently executing firmware. */
e315cd28 3234 qla2x00_try_to_stop_firmware(vha);
1da177e4 3235
85880801
AV		 3236 vha->flags.online = 0;
3237
f6ef3b18 3238 /* turn-off interrupts on the card */
a9083016
GM		 3239 if (ha->interrupts_on) {
3240 vha->flags.init_done = 0;
fd34f556 3241 ha->isp_ops->disable_intrs(ha);
a9083016 3242 }
f6ef3b18 3243
e315cd28 3244 qla2x00_free_irqs(vha);
1da177e4 3245
8867048b
CD		 3246 qla2x00_free_fcports(vha);
3247
e315cd28 3248 qla2x00_mem_free(ha);
73208dfd 3249
08de2844
GM		 3250 qla82xx_md_free(vha);
3251
73208dfd 3252 qla2x00_free_queues(ha);
1da177e4
LT		 3253}
3254
8867048b
CD		 3255void qla2x00_free_fcports(struct scsi_qla_host *vha)
3256{
3257 fc_port_t *fcport, *tfcport;
3258
3259 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3260 list_del(&fcport->list);
5f16b331 3261 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3262 kfree(fcport);
3263 fcport = NULL;
3264 }
3265}
3266
d97994dc 3267static inline void
e315cd28 3268qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3269 int defer)
3270{
d97994dc 3271 struct fc_rport *rport;
67becc00 3272 scsi_qla_host_t *base_vha;
044d78e1 3273 unsigned long flags;
d97994dc
AV		 3274
3275 if (!fcport->rport)
3276 return;
3277
3278 rport = fcport->rport;
3279 if (defer) {
67becc00 3280 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3281 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3282 fcport->drport = rport;
044d78e1 3283 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3284 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3285 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3286 qla2xxx_wake_dpc(base_vha);
2d70c103 3287 } else {
df673274 3288 int now;
d20ed91b
AP		 3289 if (rport)
3290 fc_remote_port_delete(rport);
df673274
AP		 3291 qlt_do_generation_tick(vha, &now);
3292 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3293 }
d97994dc
AV		 3294}
3295
1da177e4
LT		 3296/*
3297 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3298 *
3299 * Input: ha = adapter block pointer. fcport = port structure pointer.
3300 *
3301 * Return: None.
3302 *
3303 * Context:
3304 */
e315cd28 3305void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3306 int do_login, int defer)
1da177e4 3307{
8ae6d9c7
GM		 3308 if (IS_QLAFX00(vha->hw)) {
3309 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3310 qla2x00_schedule_rport_del(vha, fcport, defer);
3311 return;
3312 }
3313
2c3dfe3f 3314 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3315 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3316 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3317 qla2x00_schedule_rport_del(vha, fcport, defer);
3318 }
fa2a1ce5 3319 /*
1da177e4
LT		 3320 * We may need to retry the login, so don't change the state of the
3321 * port but do the retries.
3322 */
3323 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3324 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3325
3326 if (!do_login)
3327 return;
3328
a1d0285e
AE		 3329 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3330
1da177e4 3331 if (fcport->login_retry == 0) {
e315cd28 3332 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3333
7c3df132 3334 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3335 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3336 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3337 }
3338}
3339
3340/*
3341 * qla2x00_mark_all_devices_lost
3342 * Updates fcport state when device goes offline.
3343 *
3344 * Input:
3345 * ha = adapter block pointer.
3346 * fcport = port structure pointer.
3347 *
3348 * Return:
3349 * None.
3350 *
3351 * Context:
3352 */
3353void
e315cd28 3354qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3355{
3356 fc_port_t *fcport;
3357
e315cd28 3358 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3359 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3360 continue;
0d6e61bc 3361
1da177e4
LT		 3362 /*
3363 * No point in marking the device as lost, if the device is
3364 * already DEAD.
3365 */
3366 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3367 continue;
e315cd28 3368 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3369 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3370 if (defer)
3371 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3372 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3373 qla2x00_schedule_rport_del(vha, fcport, defer);
3374 }
1da177e4
LT		 3375 }
3376}
3377
3378/*
3379* qla2x00_mem_alloc
3380* Allocates adapter memory.
3381*
3382* Returns:
3383* 0 = success.
e8711085 3384* !0 = failure.
1da177e4 3385*/
e8711085 3386static int
73208dfd
AC		 3387qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3388 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3389{
3390 char name[16];
1da177e4 3391
e8711085 3392 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3393 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3394 if (!ha->init_cb)
e315cd28 3395 goto fail;
e8711085 3396
2d70c103
NB		 3397 if (qlt_mem_alloc(ha) < 0)
3398 goto fail_free_init_cb;
3399
642ef983
CD		 3400 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3401 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3402 if (!ha->gid_list)
2d70c103 3403 goto fail_free_tgt_mem;
1da177e4 3404
e8711085
AV		 3405 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3406 if (!ha->srb_mempool)
e315cd28 3407 goto fail_free_gid_list;
e8711085 3408
7ec0effd 3409 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3410 /* Allocate cache for CT6 Ctx. */
3411 if (!ctx_cachep) {
3412 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3413 sizeof(struct ct6_dsd), 0,
3414 SLAB_HWCACHE_ALIGN, NULL);
3415 if (!ctx_cachep)
3416 goto fail_free_gid_list;
3417 }
3418 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3419 ctx_cachep);
3420 if (!ha->ctx_mempool)
3421 goto fail_free_srb_mempool;
7c3df132
SK		 3422 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3423 "ctx_cachep=%p ctx_mempool=%p.\n",
3424 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3425 }
3426
e8711085
AV		 3427 /* Get memory for cached NVRAM */
3428 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3429 if (!ha->nvram)
a9083016 3430 goto fail_free_ctx_mempool;
e8711085 3431
e315cd28
AC		 3432 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3433 ha->pdev->device);
3434 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3435 DMA_POOL_SIZE, 8, 0);
3436 if (!ha->s_dma_pool)
3437 goto fail_free_nvram;
3438
7c3df132
SK		 3439 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3440 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3441 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3442
7ec0effd 3443 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3444 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3445 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3446 if (!ha->dl_dma_pool) {
7c3df132
SK		 3447 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3448 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3449 goto fail_s_dma_pool;
3450 }
3451
3452 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3453 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3454 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3455 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3456 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3457 goto fail_dl_dma_pool;
3458 }
7c3df132
SK		 3459 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3460 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3461 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3462 }
3463
e8711085
AV		 3464 /* Allocate memory for SNS commands */
3465 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3466 /* Get consistent memory allocated for SNS commands */
e8711085 3467 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3468 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3469 if (!ha->sns_cmd)
e315cd28 3470 goto fail_dma_pool;
7c3df132 3471 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3472 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3473 } else {
e315cd28 3474 /* Get consistent memory allocated for MS IOCB */
e8711085 3475 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3476 &ha->ms_iocb_dma);
e8711085 3477 if (!ha->ms_iocb)
e315cd28
AC		 3478 goto fail_dma_pool;
3479 /* Get consistent memory allocated for CT SNS commands */
e8711085 3480 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3481 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3482 if (!ha->ct_sns)
3483 goto fail_free_ms_iocb;
7c3df132
SK		 3484 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3485 "ms_iocb=%p ct_sns=%p.\n",
3486 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3487 }
3488
e315cd28 3489 /* Allocate memory for request ring */
73208dfd
AC		 3490 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3491 if (!*req) {
7c3df132
SK		 3492 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3493 "Failed to allocate memory for req.\n");
e315cd28
AC		 3494 goto fail_req;
3495 }
73208dfd
AC		 3496 (*req)->length = req_len;
3497 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3498 ((*req)->length + 1) * sizeof(request_t),
3499 &(*req)->dma, GFP_KERNEL);
3500 if (!(*req)->ring) {
7c3df132
SK		 3501 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3502 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3503 goto fail_req_ring;
3504 }
3505 /* Allocate memory for response ring */
73208dfd
AC		 3506 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3507 if (!*rsp) {
7c3df132
SK		 3508 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3509 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3510 goto fail_rsp;
3511 }
73208dfd
AC		 3512 (*rsp)->hw = ha;
3513 (*rsp)->length = rsp_len;
3514 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3515 ((*rsp)->length + 1) * sizeof(response_t),
3516 &(*rsp)->dma, GFP_KERNEL);
3517 if (!(*rsp)->ring) {
7c3df132
SK		 3518 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3519 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3520 goto fail_rsp_ring;
3521 }
73208dfd
AC		 3522 (*req)->rsp = *rsp;
3523 (*rsp)->req = *req;
7c3df132
SK		 3524 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3525 "req=%p req->length=%d req->ring=%p rsp=%p "
3526 "rsp->length=%d rsp->ring=%p.\n",
3527 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3528 (*rsp)->ring);
73208dfd
AC		 3529 /* Allocate memory for NVRAM data for vports */
3530 if (ha->nvram_npiv_size) {
3531 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3532 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3533 if (!ha->npiv_info) {
7c3df132
SK		 3534 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3535 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3536 goto fail_npiv_info;
3537 }
3538 } else
3539 ha->npiv_info = NULL;
e8711085 3540
b64b0e8f 3541 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3542 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3543 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3544 &ha->ex_init_cb_dma);
3545 if (!ha->ex_init_cb)
3546 goto fail_ex_init_cb;
7c3df132
SK		 3547 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3548 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3549 }
3550
a9083016
GM		 3551 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3552
5ff1d584
AV		 3553 /* Get consistent memory allocated for Async Port-Database. */
3554 if (!IS_FWI2_CAPABLE(ha)) {
3555 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3556 &ha->async_pd_dma);
3557 if (!ha->async_pd)
3558 goto fail_async_pd;
7c3df132
SK		 3559 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3560 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3561 }
3562
e315cd28 3563 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3564
3565 /* Allocate memory for our loop_id bitmap */
3566 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3567 GFP_KERNEL);
3568 if (!ha->loop_id_map)
3569 goto fail_async_pd;
3570 else {
3571 qla2x00_set_reserved_loop_ids(ha);
3572 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3573 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3574 }
3575
b2a72ec3 3576 return 0;
e315cd28 3577
5ff1d584
AV		 3578fail_async_pd:
3579 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3580fail_ex_init_cb:
3581 kfree(ha->npiv_info);
73208dfd
AC		 3582fail_npiv_info:
3583 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3584 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3585 (*rsp)->ring = NULL;
3586 (*rsp)->dma = 0;
e315cd28 3587fail_rsp_ring:
73208dfd 3588 kfree(*rsp);
e315cd28 3589fail_rsp:
73208dfd
AC		 3590 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3591 sizeof(request_t), (*req)->ring, (*req)->dma);
3592 (*req)->ring = NULL;
3593 (*req)->dma = 0;
e315cd28 3594fail_req_ring:
73208dfd 3595 kfree(*req);
e315cd28
AC		 3596fail_req:
3597 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3598 ha->ct_sns, ha->ct_sns_dma);
3599 ha->ct_sns = NULL;
3600 ha->ct_sns_dma = 0;
e8711085
AV		 3601fail_free_ms_iocb:
3602 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3603 ha->ms_iocb = NULL;
3604 ha->ms_iocb_dma = 0;
e315cd28 3605fail_dma_pool:
bad75002 3606 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3607 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3608 ha->fcp_cmnd_dma_pool = NULL;
3609 }
3610fail_dl_dma_pool:
bad75002 3611 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3612 dma_pool_destroy(ha->dl_dma_pool);
3613 ha->dl_dma_pool = NULL;
3614 }
3615fail_s_dma_pool:
e315cd28
AC		 3616 dma_pool_destroy(ha->s_dma_pool);
3617 ha->s_dma_pool = NULL;
e8711085
AV		 3618fail_free_nvram:
3619 kfree(ha->nvram);
3620 ha->nvram = NULL;
a9083016
GM		 3621fail_free_ctx_mempool:
3622 mempool_destroy(ha->ctx_mempool);
3623 ha->ctx_mempool = NULL;
e8711085
AV		 3624fail_free_srb_mempool:
3625 mempool_destroy(ha->srb_mempool);
3626 ha->srb_mempool = NULL;
e8711085 3627fail_free_gid_list:
642ef983
CD		 3628 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3629 ha->gid_list,
e315cd28 3630 ha->gid_list_dma);
e8711085
AV		 3631 ha->gid_list = NULL;
3632 ha->gid_list_dma = 0;
2d70c103
NB		 3633fail_free_tgt_mem:
3634 qlt_mem_free(ha);
e315cd28
AC		 3635fail_free_init_cb:
3636 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3637 ha->init_cb_dma);
3638 ha->init_cb = NULL;
3639 ha->init_cb_dma = 0;
e8711085 3640fail:
7c3df132
SK		 3641 ql_log(ql_log_fatal, NULL, 0x0030,
3642 "Memory allocation failure.\n");
e8711085 3643 return -ENOMEM;
1da177e4
LT		 3644}
3645
b0d6cabd
HM		 3646int
3647qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3648{
3649 int rval;
3650 uint16_t size, max_cnt, temp;
3651 struct qla_hw_data *ha = vha->hw;
3652
3653 /* Return if we don't need to alloacate any extended logins */
3654 if (!ql2xexlogins)
3655 return QLA_SUCCESS;
3656
3657 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3658 max_cnt = 0;
3659 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3660 if (rval != QLA_SUCCESS) {
3661 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3662 "Failed to get exlogin status.\n");
3663 return rval;
3664 }
3665
3666 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3667 ha->exlogin_size = (size * temp);
3668 ql_log(ql_log_info, vha, 0xd024,
3669 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3670 max_cnt, size, temp);
3671
3672 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3673 ha->exlogin_size);
3674
3675 /* Get consistent memory for extended logins */
3676 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3677 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3678 if (!ha->exlogin_buf) {
3679 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3680 "Failed to allocate memory for exlogin_buf_dma.\n");
3681 return -ENOMEM;
3682 }
3683
3684 /* Now configure the dma buffer */
3685 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3686 if (rval) {
3687 ql_log(ql_log_fatal, vha, 0x00cf,
3688 "Setup extended login buffer ****FAILED****.\n");
3689 qla2x00_free_exlogin_buffer(ha);
3690 }
3691
3692 return rval;
3693}
3694
3695/*
3696* qla2x00_free_exlogin_buffer
3697*
3698* Input:
3699* ha = adapter block pointer
3700*/
3701void
3702qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3703{
3704 if (ha->exlogin_buf) {
3705 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3706 ha->exlogin_buf, ha->exlogin_buf_dma);
3707 ha->exlogin_buf = NULL;
3708 ha->exlogin_size = 0;
3709 }
3710}
3711
2f56a7f1
HM		 3712int
3713qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3714{
3715 int rval;
3716 uint16_t size, max_cnt, temp;
3717 struct qla_hw_data *ha = vha->hw;
3718
3719 /* Return if we don't need to alloacate any extended logins */
3720 if (!ql2xexchoffld)
3721 return QLA_SUCCESS;
3722
3723 ql_log(ql_log_info, vha, 0xd014,
3724 "Exchange offload count: %d.\n", ql2xexlogins);
3725
3726 max_cnt = 0;
3727 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3728 if (rval != QLA_SUCCESS) {
3729 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3730 "Failed to get exlogin status.\n");
3731 return rval;
3732 }
3733
3734 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3735 ha->exchoffld_size = (size * temp);
3736 ql_log(ql_log_info, vha, 0xd016,
3737 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3738 max_cnt, size, temp);
3739
3740 ql_log(ql_log_info, vha, 0xd017,
3741 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3742
3743 /* Get consistent memory for extended logins */
3744 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3745 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3746 if (!ha->exchoffld_buf) {
3747 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
3748 "Failed to allocate memory for exchoffld_buf_dma.\n");
3749 return -ENOMEM;
3750 }
3751
3752 /* Now configure the dma buffer */
3753 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
3754 if (rval) {
3755 ql_log(ql_log_fatal, vha, 0xd02e,
3756 "Setup exchange offload buffer ****FAILED****.\n");
3757 qla2x00_free_exchoffld_buffer(ha);
3758 }
3759
3760 return rval;
3761}
3762
3763/*
3764* qla2x00_free_exchoffld_buffer
3765*
3766* Input:
3767* ha = adapter block pointer
3768*/
3769void
3770qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
3771{
3772 if (ha->exchoffld_buf) {
3773 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
3774 ha->exchoffld_buf, ha->exchoffld_buf_dma);
3775 ha->exchoffld_buf = NULL;
3776 ha->exchoffld_size = 0;
3777 }
3778}
3779
1da177e4 3780/*
e30d1756
MI		 3781* qla2x00_free_fw_dump
3782* Frees fw dump stuff.
1da177e4
LT		 3783*
3784* Input:
7ec0effd 3785* ha = adapter block pointer
1da177e4 3786*/
a824ebb3 3787static void
e30d1756 3788qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3789{
df613b96 3790 if (ha->fce)
f73cb695
CD		 3791 dma_free_coherent(&ha->pdev->dev,
3792 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3793
f73cb695
CD		 3794 if (ha->eft)
3795 dma_free_coherent(&ha->pdev->dev,
3796 EFT_SIZE, ha->eft, ha->eft_dma);
3797
3798 if (ha->fw_dump)
a7a167bf 3799 vfree(ha->fw_dump);
f73cb695
CD		 3800 if (ha->fw_dump_template)
3801 vfree(ha->fw_dump_template);
3802
e30d1756
MI		 3803 ha->fce = NULL;
3804 ha->fce_dma = 0;
3805 ha->eft = NULL;
3806 ha->eft_dma = 0;
e30d1756 3807 ha->fw_dumped = 0;
61f098dd 3808 ha->fw_dump_cap_flags = 0;
e30d1756 3809 ha->fw_dump_reading = 0;
f73cb695
CD		 3810 ha->fw_dump = NULL;
3811 ha->fw_dump_len = 0;
3812 ha->fw_dump_template = NULL;
3813 ha->fw_dump_template_len = 0;
e30d1756
MI		 3814}
3815
3816/*
3817* qla2x00_mem_free
3818* Frees all adapter allocated memory.
3819*
3820* Input:
3821* ha = adapter block pointer.
3822*/
3823static void
3824qla2x00_mem_free(struct qla_hw_data *ha)
3825{
3826 qla2x00_free_fw_dump(ha);
3827
81178772
SK		 3828 if (ha->mctp_dump)
3829 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3830 ha->mctp_dump_dma);
3831
e30d1756
MI		 3832 if (ha->srb_mempool)
3833 mempool_destroy(ha->srb_mempool);
a7a167bf 3834
11bbc1d8
AV		 3835 if (ha->dcbx_tlv)
3836 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3837 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3838
ce0423f4
AV		 3839 if (ha->xgmac_data)
3840 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3841 ha->xgmac_data, ha->xgmac_data_dma);
3842
1da177e4
LT		 3843 if (ha->sns_cmd)
3844 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3845 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3846
3847 if (ha->ct_sns)
3848 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3849 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3850
88729e53
AV		 3851 if (ha->sfp_data)
3852 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3853
1da177e4
LT		 3854 if (ha->ms_iocb)
3855 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3856
b64b0e8f 3857 if (ha->ex_init_cb)
a9083016
GM		 3858 dma_pool_free(ha->s_dma_pool,
3859 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3860
5ff1d584
AV		 3861 if (ha->async_pd)
3862 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3863
1da177e4
LT		 3864 if (ha->s_dma_pool)
3865 dma_pool_destroy(ha->s_dma_pool);
3866
1da177e4 3867 if (ha->gid_list)
642ef983
CD		 3868 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3869 ha->gid_list, ha->gid_list_dma);
1da177e4 3870
a9083016
GM		 3871 if (IS_QLA82XX(ha)) {
3872 if (!list_empty(&ha->gbl_dsd_list)) {
3873 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3874
3875 /* clean up allocated prev pool */
3876 list_for_each_entry_safe(dsd_ptr,
3877 tdsd_ptr, &ha->gbl_dsd_list, list) {
3878 dma_pool_free(ha->dl_dma_pool,
3879 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3880 list_del(&dsd_ptr->list);
3881 kfree(dsd_ptr);
3882 }
3883 }
3884 }
3885
3886 if (ha->dl_dma_pool)
3887 dma_pool_destroy(ha->dl_dma_pool);
3888
3889 if (ha->fcp_cmnd_dma_pool)
3890 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3891
3892 if (ha->ctx_mempool)
3893 mempool_destroy(ha->ctx_mempool);
3894
2d70c103
NB		 3895 qlt_mem_free(ha);
3896
e315cd28
AC		 3897 if (ha->init_cb)
3898 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3899 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3900 vfree(ha->optrom_buffer);
3901 kfree(ha->nvram);
73208dfd 3902 kfree(ha->npiv_info);
7a67735b 3903 kfree(ha->swl);
5f16b331 3904 kfree(ha->loop_id_map);
1da177e4 3905
e8711085 3906 ha->srb_mempool = NULL;
a9083016 3907 ha->ctx_mempool = NULL;
1da177e4
LT		 3908 ha->sns_cmd = NULL;
3909 ha->sns_cmd_dma = 0;
3910 ha->ct_sns = NULL;
3911 ha->ct_sns_dma = 0;
3912 ha->ms_iocb = NULL;
3913 ha->ms_iocb_dma = 0;
1da177e4
LT		 3914 ha->init_cb = NULL;
3915 ha->init_cb_dma = 0;
b64b0e8f
AV		 3916 ha->ex_init_cb = NULL;
3917 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3918 ha->async_pd = NULL;
3919 ha->async_pd_dma = 0;
1da177e4
LT		 3920
3921 ha->s_dma_pool = NULL;
a9083016
GM		 3922 ha->dl_dma_pool = NULL;
3923 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3924
1da177e4
LT		 3925 ha->gid_list = NULL;
3926 ha->gid_list_dma = 0;
2d70c103
NB		 3927
3928 ha->tgt.atio_ring = NULL;
3929 ha->tgt.atio_dma = 0;
3930 ha->tgt.tgt_vp_map = NULL;
e315cd28 3931}
1da177e4 3932
e315cd28
AC		 3933struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3934 struct qla_hw_data *ha)
3935{
3936 struct Scsi_Host *host;
3937 struct scsi_qla_host *vha = NULL;
854165f4 3938
e315cd28
AC		 3939 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3940 if (host == NULL) {
7c3df132
SK		 3941 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3942 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3943 goto fail;
3944 }
3945
3946 /* Clear our data area */
3947 vha = shost_priv(host);
3948 memset(vha, 0, sizeof(scsi_qla_host_t));
3949
3950 vha->host = host;
3951 vha->host_no = host->host_no;
3952 vha->hw = ha;
3953
3954 INIT_LIST_HEAD(&vha->vp_fcports);
3955 INIT_LIST_HEAD(&vha->work_list);
3956 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 3957 INIT_LIST_HEAD(&vha->qla_cmd_list);
3958 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 3959 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 3960 INIT_LIST_HEAD(&vha->plogi_ack_list);
e315cd28 3961
f999f4c1 3962 spin_lock_init(&vha->work_lock);
8b2f5ff3 3963 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 3964
e315cd28 3965 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3966 ql_dbg(ql_dbg_init, vha, 0x0041,
3967 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3968 vha->host, vha->hw, vha,
3969 dev_name(&(ha->pdev->dev)));
3970
e315cd28
AC		 3971 return vha;
3972
3973fail:
3974 return vha;
1da177e4
LT		 3975}
3976
01ef66bb 3977static struct qla_work_evt *
f999f4c1 3978qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3979{
3980 struct qla_work_evt *e;
feafb7b1
AE		 3981 uint8_t bail;
3982
3983 QLA_VHA_MARK_BUSY(vha, bail);
3984 if (bail)
3985 return NULL;
0971de7f 3986
f999f4c1 3987 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3988 if (!e) {
3989 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3990 return NULL;
feafb7b1 3991 }
0971de7f
AV		 3992
3993 INIT_LIST_HEAD(&e->list);
3994 e->type = type;
3995 e->flags = QLA_EVT_FLAG_FREE;
3996 return e;
3997}
3998
01ef66bb 3999static int
f999f4c1 4000qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4001{
f999f4c1 4002 unsigned long flags;
0971de7f 4003
f999f4c1 4004 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4005 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4006 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 4007 qla2xxx_wake_dpc(vha);
f999f4c1 4008
0971de7f
AV		 4009 return QLA_SUCCESS;
4010}
4011
4012int
e315cd28 4013qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4014 u32 data)
4015{
4016 struct qla_work_evt *e;
4017
f999f4c1 4018 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4019 if (!e)
4020 return QLA_FUNCTION_FAILED;
4021
4022 e->u.aen.code = code;
4023 e->u.aen.data = data;
f999f4c1 4024 return qla2x00_post_work(vha, e);
0971de7f
AV		 4025}
4026
8a659571
AV		 4027int
4028qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4029{
4030 struct qla_work_evt *e;
4031
f999f4c1 4032 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4033 if (!e)
4034 return QLA_FUNCTION_FAILED;
4035
4036 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4037 return qla2x00_post_work(vha, e);
8a659571
AV		 4038}
4039
ac280b67
AV		 4040#define qla2x00_post_async_work(name, type) \
4041int qla2x00_post_async_##name##_work( \
4042 struct scsi_qla_host *vha, \
4043 fc_port_t *fcport, uint16_t *data) \
4044{ \
4045 struct qla_work_evt *e; \
4046 \
4047 e = qla2x00_alloc_work(vha, type); \
4048 if (!e) \
4049 return QLA_FUNCTION_FAILED; \
4050 \
4051 e->u.logio.fcport = fcport; \
4052 if (data) { \
4053 e->u.logio.data[0] = data[0]; \
4054 e->u.logio.data[1] = data[1]; \
4055 } \
4056 return qla2x00_post_work(vha, e); \
4057}
4058
4059qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4060qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4061qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4062qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4063qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4064qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4065
3420d36c
AV		 4066int
4067qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4068{
4069 struct qla_work_evt *e;
4070
4071 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4072 if (!e)
4073 return QLA_FUNCTION_FAILED;
4074
4075 e->u.uevent.code = code;
4076 return qla2x00_post_work(vha, e);
4077}
4078
4079static void
4080qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4081{
4082 char event_string[40];
4083 char *envp[] = { event_string, NULL };
4084
4085 switch (code) {
4086 case QLA_UEVENT_CODE_FW_DUMP:
4087 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4088 vha->host_no);
4089 break;
4090 default:
4091 /* do nothing */
4092 break;
4093 }
4094 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4095}
4096
8ae6d9c7
GM		 4097int
4098qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4099 uint32_t *data, int cnt)
4100{
4101 struct qla_work_evt *e;
4102
4103 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4104 if (!e)
4105 return QLA_FUNCTION_FAILED;
4106
4107 e->u.aenfx.evtcode = evtcode;
4108 e->u.aenfx.count = cnt;
4109 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4110 return qla2x00_post_work(vha, e);
4111}
4112
ac280b67 4113void
e315cd28 4114qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4115{
f999f4c1
AV		 4116 struct qla_work_evt *e, *tmp;
4117 unsigned long flags;
4118 LIST_HEAD(work);
0971de7f 4119
f999f4c1
AV		 4120 spin_lock_irqsave(&vha->work_lock, flags);
4121 list_splice_init(&vha->work_list, &work);
4122 spin_unlock_irqrestore(&vha->work_lock, flags);
4123
4124 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4125 list_del_init(&e->list);
0971de7f
AV		 4126
4127 switch (e->type) {
4128 case QLA_EVT_AEN:
e315cd28 4129 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4130 e->u.aen.code, e->u.aen.data);
4131 break;
8a659571
AV		 4132 case QLA_EVT_IDC_ACK:
4133 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4134 break;
ac280b67
AV		 4135 case QLA_EVT_ASYNC_LOGIN:
4136 qla2x00_async_login(vha, e->u.logio.fcport,
4137 e->u.logio.data);
4138 break;
4139 case QLA_EVT_ASYNC_LOGIN_DONE:
4140 qla2x00_async_login_done(vha, e->u.logio.fcport,
4141 e->u.logio.data);
4142 break;
4143 case QLA_EVT_ASYNC_LOGOUT:
4144 qla2x00_async_logout(vha, e->u.logio.fcport);
4145 break;
4146 case QLA_EVT_ASYNC_LOGOUT_DONE:
4147 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4148 e->u.logio.data);
4149 break;
5ff1d584
AV		 4150 case QLA_EVT_ASYNC_ADISC:
4151 qla2x00_async_adisc(vha, e->u.logio.fcport,
4152 e->u.logio.data);
4153 break;
4154 case QLA_EVT_ASYNC_ADISC_DONE:
4155 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4156 e->u.logio.data);
4157 break;
3420d36c
AV		 4158 case QLA_EVT_UEVENT:
4159 qla2x00_uevent_emit(vha, e->u.uevent.code);
4160 break;
8ae6d9c7
GM		 4161 case QLA_EVT_AENFX:
4162 qlafx00_process_aen(vha, e);
4163 break;
0971de7f
AV		 4164 }
4165 if (e->flags & QLA_EVT_FLAG_FREE)
4166 kfree(e);
feafb7b1
AE		 4167
4168 /* For each work completed decrement vha ref count */
4169 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4170 }
e315cd28 4171}
f999f4c1 4172
e315cd28
AC		 4173/* Relogins all the fcports of a vport
4174 * Context: dpc thread
4175 */
4176void qla2x00_relogin(struct scsi_qla_host *vha)
4177{
4178 fc_port_t *fcport;
c6b2fca8 4179 int status;
e315cd28
AC		 4180 uint16_t next_loopid = 0;
4181 struct qla_hw_data *ha = vha->hw;
ac280b67 4182 uint16_t data[2];
e315cd28
AC		 4183
4184 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4185 /*
4186 * If the port is not ONLINE then try to login
4187 * to it if we haven't run out of retries.
4188 */
5ff1d584
AV		 4189 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4190 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4191 fcport->login_retry--;
e315cd28 4192 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4193 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4194 ha->isp_ops->fabric_logout(vha,
4195 fcport->loop_id,
4196 fcport->d_id.b.domain,
4197 fcport->d_id.b.area,
4198 fcport->d_id.b.al_pa);
4199
03bcfb57
JC		 4200 if (fcport->loop_id == FC_NO_LOOP_ID) {
4201 fcport->loop_id = next_loopid =
4202 ha->min_external_loopid;
4203 status = qla2x00_find_new_loop_id(
4204 vha, fcport);
4205 if (status != QLA_SUCCESS) {
4206 /* Ran out of IDs to use */
4207 break;
4208 }
4209 }
4210
ac280b67 4211 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4212 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4213 data[0] = 0;
4214 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4215 status = qla2x00_post_async_login_work(
4216 vha, fcport, data);
4217 if (status == QLA_SUCCESS)
4218 continue;
4219 /* Attempt a retry. */
4220 status = 1;
aaf4d3e2 4221 } else {
ac280b67
AV		 4222 status = qla2x00_fabric_login(vha,
4223 fcport, &next_loopid);
aaf4d3e2
SK		 4224 if (status == QLA_SUCCESS) {
4225 int status2;
4226 uint8_t opts;
4227
4228 opts = 0;
4229 if (fcport->flags &
4230 FCF_FCP2_DEVICE)
4231 opts |= BIT_1;
03003960
SK		 4232 status2 =
4233 qla2x00_get_port_database(
4234 vha, fcport, opts);
aaf4d3e2
SK		 4235 if (status2 != QLA_SUCCESS)
4236 status = 1;
4237 }
4238 }
e315cd28
AC		 4239 } else
4240 status = qla2x00_local_device_login(vha,
4241 fcport);
4242
e315cd28
AC		 4243 if (status == QLA_SUCCESS) {
4244 fcport->old_loop_id = fcport->loop_id;
4245
7c3df132
SK		 4246 ql_dbg(ql_dbg_disc, vha, 0x2003,
4247 "Port login OK: logged in ID 0x%x.\n",
4248 fcport->loop_id);
e315cd28
AC		 4249
4250 qla2x00_update_fcport(vha, fcport);
4251
4252 } else if (status == 1) {
4253 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4254 /* retry the login again */
7c3df132
SK		 4255 ql_dbg(ql_dbg_disc, vha, 0x2007,
4256 "Retrying %d login again loop_id 0x%x.\n",
4257 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4258 } else {
4259 fcport->login_retry = 0;
4260 }
4261
4262 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4263 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4264 }
4265 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4266 break;
0971de7f 4267 }
0971de7f
AV		 4268}
4269
7d613ac6
SV		 4270/* Schedule work on any of the dpc-workqueues */
4271void
4272qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4273{
4274 struct qla_hw_data *ha = base_vha->hw;
4275
4276 switch (work_code) {
4277 case MBA_IDC_AEN: /* 0x8200 */
4278 if (ha->dpc_lp_wq)
4279 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4280 break;
4281
4282 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4283 if (!ha->flags.nic_core_reset_hdlr_active) {
4284 if (ha->dpc_hp_wq)
4285 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4286 } else
4287 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4288 "NIC Core reset is already active. Skip "
4289 "scheduling it again.\n");
4290 break;
4291 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4292 if (ha->dpc_hp_wq)
4293 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4294 break;
4295 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4296 if (ha->dpc_hp_wq)
4297 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4298 break;
4299 default:
4300 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4301 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4302 }
4303
4304 return;
4305}
4306
4307/* Work: Perform NIC Core Unrecoverable state handling */
4308void
4309qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4310{
4311 struct qla_hw_data *ha =
2ad1b67c 4312 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4313 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4314 uint32_t dev_state = 0;
4315
4316 qla83xx_idc_lock(base_vha, 0);
4317 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4318 qla83xx_reset_ownership(base_vha);
4319 if (ha->flags.nic_core_reset_owner) {
4320 ha->flags.nic_core_reset_owner = 0;
4321 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4322 QLA8XXX_DEV_FAILED);
4323 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4324 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4325 }
4326 qla83xx_idc_unlock(base_vha, 0);
4327}
4328
4329/* Work: Execute IDC state handler */
4330void
4331qla83xx_idc_state_handler_work(struct work_struct *work)
4332{
4333 struct qla_hw_data *ha =
2ad1b67c 4334 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4335 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4336 uint32_t dev_state = 0;
4337
4338 qla83xx_idc_lock(base_vha, 0);
4339 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4340 if (dev_state == QLA8XXX_DEV_FAILED ||
4341 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4342 qla83xx_idc_state_handler(base_vha);
4343 qla83xx_idc_unlock(base_vha, 0);
4344}
4345
fa492630 4346static int
7d613ac6
SV		 4347qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4348{
4349 int rval = QLA_SUCCESS;
4350 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4351 uint32_t heart_beat_counter1, heart_beat_counter2;
4352
4353 do {
4354 if (time_after(jiffies, heart_beat_wait)) {
4355 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4356 "Nic Core f/w is not alive.\n");
4357 rval = QLA_FUNCTION_FAILED;
4358 break;
4359 }
4360
4361 qla83xx_idc_lock(base_vha, 0);
4362 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4363 &heart_beat_counter1);
4364 qla83xx_idc_unlock(base_vha, 0);
4365 msleep(100);
4366 qla83xx_idc_lock(base_vha, 0);
4367 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4368 &heart_beat_counter2);
4369 qla83xx_idc_unlock(base_vha, 0);
4370 } while (heart_beat_counter1 == heart_beat_counter2);
4371
4372 return rval;
4373}
4374
4375/* Work: Perform NIC Core Reset handling */
4376void
4377qla83xx_nic_core_reset_work(struct work_struct *work)
4378{
4379 struct qla_hw_data *ha =
4380 container_of(work, struct qla_hw_data, nic_core_reset);
4381 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4382 uint32_t dev_state = 0;
4383
81178772
SK		 4384 if (IS_QLA2031(ha)) {
4385 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4386 ql_log(ql_log_warn, base_vha, 0xb081,
4387 "Failed to dump mctp\n");
4388 return;
4389 }
4390
7d613ac6
SV		 4391 if (!ha->flags.nic_core_reset_hdlr_active) {
4392 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4393 qla83xx_idc_lock(base_vha, 0);
4394 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4395 &dev_state);
4396 qla83xx_idc_unlock(base_vha, 0);
4397 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4398 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4399 "Nic Core f/w is alive.\n");
4400 return;
4401 }
4402 }
4403
4404 ha->flags.nic_core_reset_hdlr_active = 1;
4405 if (qla83xx_nic_core_reset(base_vha)) {
4406 /* NIC Core reset failed. */
4407 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4408 "NIC Core reset failed.\n");
4409 }
4410 ha->flags.nic_core_reset_hdlr_active = 0;
4411 }
4412}
4413
4414/* Work: Handle 8200 IDC aens */
4415void
4416qla83xx_service_idc_aen(struct work_struct *work)
4417{
4418 struct qla_hw_data *ha =
4419 container_of(work, struct qla_hw_data, idc_aen);
4420 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4421 uint32_t dev_state, idc_control;
4422
4423 qla83xx_idc_lock(base_vha, 0);
4424 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4425 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4426 qla83xx_idc_unlock(base_vha, 0);
4427 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4428 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4429 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4430 "Application requested NIC Core Reset.\n");
4431 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4432 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4433 QLA_SUCCESS) {
4434 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4435 "Other protocol driver requested NIC Core Reset.\n");
4436 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4437 }
4438 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4439 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4440 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4441 }
4442}
4443
4444static void
4445qla83xx_wait_logic(void)
4446{
4447 int i;
4448
4449 /* Yield CPU */
4450 if (!in_interrupt()) {
4451 /*
4452 * Wait about 200ms before retrying again.
4453 * This controls the number of retries for single
4454 * lock operation.
4455 */
4456 msleep(100);
4457 schedule();
4458 } else {
4459 for (i = 0; i < 20; i++)
4460 cpu_relax(); /* This a nop instr on i386 */
4461 }
4462}
4463
fa492630 4464static int
7d613ac6
SV		 4465qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4466{
4467 int rval;
4468 uint32_t data;
4469 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4470 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4471 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4472 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4473 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4474
4475 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4476 if (rval)
4477 return rval;
4478
4479 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4480 return QLA_SUCCESS;
4481 } else {
4482 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4483 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4484 data);
4485 if (rval)
4486 return rval;
4487
4488 msleep(200);
4489
4490 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4491 &data);
4492 if (rval)
4493 return rval;
4494
4495 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4496 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4497 ~(idc_lck_rcvry_stage_mask));
4498 rval = qla83xx_wr_reg(base_vha,
4499 QLA83XX_IDC_LOCK_RECOVERY, data);
4500 if (rval)
4501 return rval;
4502
4503 /* Forcefully perform IDC UnLock */
4504 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4505 &data);
4506 if (rval)
4507 return rval;
4508 /* Clear lock-id by setting 0xff */
4509 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4510 0xff);
4511 if (rval)
4512 return rval;
4513 /* Clear lock-recovery by setting 0x0 */
4514 rval = qla83xx_wr_reg(base_vha,
4515 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4516 if (rval)
4517 return rval;
4518 } else
4519 return QLA_SUCCESS;
4520 }
4521
4522 return rval;
4523}
4524
fa492630 4525static int
7d613ac6
SV		 4526qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4527{
4528 int rval = QLA_SUCCESS;
4529 uint32_t o_drv_lockid, n_drv_lockid;
4530 unsigned long lock_recovery_timeout;
4531
4532 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4533retry_lockid:
4534 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4535 if (rval)
4536 goto exit;
4537
4538 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4539 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4540 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4541 return QLA_SUCCESS;
4542 else
4543 return QLA_FUNCTION_FAILED;
4544 }
4545
4546 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4547 if (rval)
4548 goto exit;
4549
4550 if (o_drv_lockid == n_drv_lockid) {
4551 qla83xx_wait_logic();
4552 goto retry_lockid;
4553 } else
4554 return QLA_SUCCESS;
4555
4556exit:
4557 return rval;
4558}
4559
4560void
4561qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4562{
4563 uint16_t options = (requester_id << 15) | BIT_6;
4564 uint32_t data;
6c315553 4565 uint32_t lock_owner;
7d613ac6
SV		 4566 struct qla_hw_data *ha = base_vha->hw;
4567
4568 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4569retry_lock:
4570 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4571 == QLA_SUCCESS) {
4572 if (data) {
4573 /* Setting lock-id to our function-number */
4574 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4575 ha->portnum);
4576 } else {
6c315553
SK		 4577 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4578 &lock_owner);
7d613ac6 4579 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4580 "Failed to acquire IDC lock, acquired by %d, "
4581 "retrying...\n", lock_owner);
7d613ac6
SV		 4582
4583 /* Retry/Perform IDC-Lock recovery */
4584 if (qla83xx_idc_lock_recovery(base_vha)
4585 == QLA_SUCCESS) {
4586 qla83xx_wait_logic();
4587 goto retry_lock;
4588 } else
4589 ql_log(ql_log_warn, base_vha, 0xb075,
4590 "IDC Lock recovery FAILED.\n");
4591 }
4592
4593 }
4594
4595 return;
4596
4597 /* XXX: IDC-lock implementation using access-control mbx */
4598retry_lock2:
4599 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4600 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4601 "Failed to acquire IDC lock. retrying...\n");
4602 /* Retry/Perform IDC-Lock recovery */
4603 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4604 qla83xx_wait_logic();
4605 goto retry_lock2;
4606 } else
4607 ql_log(ql_log_warn, base_vha, 0xb076,
4608 "IDC Lock recovery FAILED.\n");
4609 }
4610
4611 return;
4612}
4613
4614void
4615qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4616{
5897cb2f
BVA		 4617#if 0
4618 uint16_t options = (requester_id << 15) | BIT_7;
4619#endif
4620 uint16_t retry;
7d613ac6
SV		 4621 uint32_t data;
4622 struct qla_hw_data *ha = base_vha->hw;
4623
4624 /* IDC-unlock implementation using driver-unlock/lock-id
4625 * remote registers
4626 */
4627 retry = 0;
4628retry_unlock:
4629 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4630 == QLA_SUCCESS) {
4631 if (data == ha->portnum) {
4632 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4633 /* Clearing lock-id by setting 0xff */
4634 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4635 } else if (retry < 10) {
4636 /* SV: XXX: IDC unlock retrying needed here? */
4637
4638 /* Retry for IDC-unlock */
4639 qla83xx_wait_logic();
4640 retry++;
4641 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4642 "Failed to release IDC lock, retyring=%d\n", retry);
4643 goto retry_unlock;
4644 }
4645 } else if (retry < 10) {
4646 /* Retry for IDC-unlock */
4647 qla83xx_wait_logic();
4648 retry++;
4649 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4650 "Failed to read drv-lockid, retyring=%d\n", retry);
4651 goto retry_unlock;
4652 }
4653
4654 return;
4655
5897cb2f 4656#if 0
7d613ac6
SV		 4657 /* XXX: IDC-unlock implementation using access-control mbx */
4658 retry = 0;
4659retry_unlock2:
4660 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4661 if (retry < 10) {
4662 /* Retry for IDC-unlock */
4663 qla83xx_wait_logic();
4664 retry++;
4665 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4666 "Failed to release IDC lock, retyring=%d\n", retry);
4667 goto retry_unlock2;
4668 }
4669 }
4670
4671 return;
5897cb2f 4672#endif
7d613ac6
SV		 4673}
4674
4675int
4676__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4677{
4678 int rval = QLA_SUCCESS;
4679 struct qla_hw_data *ha = vha->hw;
4680 uint32_t drv_presence;
4681
4682 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4683 if (rval == QLA_SUCCESS) {
4684 drv_presence |= (1 << ha->portnum);
4685 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4686 drv_presence);
4687 }
4688
4689 return rval;
4690}
4691
4692int
4693qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4694{
4695 int rval = QLA_SUCCESS;
4696
4697 qla83xx_idc_lock(vha, 0);
4698 rval = __qla83xx_set_drv_presence(vha);
4699 qla83xx_idc_unlock(vha, 0);
4700
4701 return rval;
4702}
4703
4704int
4705__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4706{
4707 int rval = QLA_SUCCESS;
4708 struct qla_hw_data *ha = vha->hw;
4709 uint32_t drv_presence;
4710
4711 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4712 if (rval == QLA_SUCCESS) {
4713 drv_presence &= ~(1 << ha->portnum);
4714 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4715 drv_presence);
4716 }
4717
4718 return rval;
4719}
4720
4721int
4722qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4723{
4724 int rval = QLA_SUCCESS;
4725
4726 qla83xx_idc_lock(vha, 0);
4727 rval = __qla83xx_clear_drv_presence(vha);
4728 qla83xx_idc_unlock(vha, 0);
4729
4730 return rval;
4731}
4732
fa492630 4733static void
7d613ac6
SV		 4734qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4735{
4736 struct qla_hw_data *ha = vha->hw;
4737 uint32_t drv_ack, drv_presence;
4738 unsigned long ack_timeout;
4739
4740 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4741 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4742 while (1) {
4743 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4744 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4745 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4746 break;
4747
4748 if (time_after_eq(jiffies, ack_timeout)) {
4749 ql_log(ql_log_warn, vha, 0xb067,
4750 "RESET ACK TIMEOUT! drv_presence=0x%x "
4751 "drv_ack=0x%x\n", drv_presence, drv_ack);
4752 /*
4753 * The function(s) which did not ack in time are forced
4754 * to withdraw any further participation in the IDC
4755 * reset.
4756 */
4757 if (drv_ack != drv_presence)
4758 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4759 drv_ack);
4760 break;
4761 }
4762
4763 qla83xx_idc_unlock(vha, 0);
4764 msleep(1000);
4765 qla83xx_idc_lock(vha, 0);
4766 }
4767
4768 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4769 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4770}
4771
fa492630 4772static int
7d613ac6
SV		 4773qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4774{
4775 int rval = QLA_SUCCESS;
4776 uint32_t idc_control;
4777
4778 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4779 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4780
4781 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4782 __qla83xx_get_idc_control(vha, &idc_control);
4783 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4784 __qla83xx_set_idc_control(vha, 0);
4785
4786 qla83xx_idc_unlock(vha, 0);
4787 rval = qla83xx_restart_nic_firmware(vha);
4788 qla83xx_idc_lock(vha, 0);
4789
4790 if (rval != QLA_SUCCESS) {
4791 ql_log(ql_log_fatal, vha, 0xb06a,
4792 "Failed to restart NIC f/w.\n");
4793 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4794 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4795 } else {
4796 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4797 "Success in restarting nic f/w.\n");
4798 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4799 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4800 }
4801
4802 return rval;
4803}
4804
4805/* Assumes idc_lock always held on entry */
4806int
4807qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4808{
4809 struct qla_hw_data *ha = base_vha->hw;
4810 int rval = QLA_SUCCESS;
4811 unsigned long dev_init_timeout;
4812 uint32_t dev_state;
4813
4814 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4815 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4816
4817 while (1) {
4818
4819 if (time_after_eq(jiffies, dev_init_timeout)) {
4820 ql_log(ql_log_warn, base_vha, 0xb06e,
4821 "Initialization TIMEOUT!\n");
4822 /* Init timeout. Disable further NIC Core
4823 * communication.
4824 */
4825 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4826 QLA8XXX_DEV_FAILED);
4827 ql_log(ql_log_info, base_vha, 0xb06f,
4828 "HW State: FAILED.\n");
4829 }
4830
4831 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4832 switch (dev_state) {
4833 case QLA8XXX_DEV_READY:
4834 if (ha->flags.nic_core_reset_owner)
4835 qla83xx_idc_audit(base_vha,
4836 IDC_AUDIT_COMPLETION);
4837 ha->flags.nic_core_reset_owner = 0;
4838 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4839 "Reset_owner reset by 0x%x.\n",
4840 ha->portnum);
4841 goto exit;
4842 case QLA8XXX_DEV_COLD:
4843 if (ha->flags.nic_core_reset_owner)
4844 rval = qla83xx_device_bootstrap(base_vha);
4845 else {
4846 /* Wait for AEN to change device-state */
4847 qla83xx_idc_unlock(base_vha, 0);
4848 msleep(1000);
4849 qla83xx_idc_lock(base_vha, 0);
4850 }
4851 break;
4852 case QLA8XXX_DEV_INITIALIZING:
4853 /* Wait for AEN to change device-state */
4854 qla83xx_idc_unlock(base_vha, 0);
4855 msleep(1000);
4856 qla83xx_idc_lock(base_vha, 0);
4857 break;
4858 case QLA8XXX_DEV_NEED_RESET:
4859 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4860 qla83xx_need_reset_handler(base_vha);
4861 else {
4862 /* Wait for AEN to change device-state */
4863 qla83xx_idc_unlock(base_vha, 0);
4864 msleep(1000);
4865 qla83xx_idc_lock(base_vha, 0);
4866 }
4867 /* reset timeout value after need reset handler */
4868 dev_init_timeout = jiffies +
4869 (ha->fcoe_dev_init_timeout * HZ);
4870 break;
4871 case QLA8XXX_DEV_NEED_QUIESCENT:
4872 /* XXX: DEBUG for now */
4873 qla83xx_idc_unlock(base_vha, 0);
4874 msleep(1000);
4875 qla83xx_idc_lock(base_vha, 0);
4876 break;
4877 case QLA8XXX_DEV_QUIESCENT:
4878 /* XXX: DEBUG for now */
4879 if (ha->flags.quiesce_owner)
4880 goto exit;
4881
4882 qla83xx_idc_unlock(base_vha, 0);
4883 msleep(1000);
4884 qla83xx_idc_lock(base_vha, 0);
4885 dev_init_timeout = jiffies +
4886 (ha->fcoe_dev_init_timeout * HZ);
4887 break;
4888 case QLA8XXX_DEV_FAILED:
4889 if (ha->flags.nic_core_reset_owner)
4890 qla83xx_idc_audit(base_vha,
4891 IDC_AUDIT_COMPLETION);
4892 ha->flags.nic_core_reset_owner = 0;
4893 __qla83xx_clear_drv_presence(base_vha);
4894 qla83xx_idc_unlock(base_vha, 0);
4895 qla8xxx_dev_failed_handler(base_vha);
4896 rval = QLA_FUNCTION_FAILED;
4897 qla83xx_idc_lock(base_vha, 0);
4898 goto exit;
4899 case QLA8XXX_BAD_VALUE:
4900 qla83xx_idc_unlock(base_vha, 0);
4901 msleep(1000);
4902 qla83xx_idc_lock(base_vha, 0);
4903 break;
4904 default:
4905 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 4906 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 4907 qla83xx_idc_unlock(base_vha, 0);
4908 qla8xxx_dev_failed_handler(base_vha);
4909 rval = QLA_FUNCTION_FAILED;
4910 qla83xx_idc_lock(base_vha, 0);
4911 goto exit;
4912 }
4913 }
4914
4915exit:
4916 return rval;
4917}
4918
f3ddac19
CD		 4919void
4920qla2x00_disable_board_on_pci_error(struct work_struct *work)
4921{
4922 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
4923 board_disable);
4924 struct pci_dev *pdev = ha->pdev;
4925 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4926
783e0dc4
SC		 4927 /* if UNLOAD flag is already set, then continue unload,
4928 * where it was set first.
4929 */
4930 if (test_bit(UNLOADING, &base_vha->dpc_flags))
4931 return;
4932
f3ddac19
CD		 4933 ql_log(ql_log_warn, base_vha, 0x015b,
4934 "Disabling adapter.\n");
4935
4936 set_bit(UNLOADING, &base_vha->dpc_flags);
4937
4938 qla2x00_delete_all_vps(ha, base_vha);
4939
4940 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4941
4942 qla2x00_dfs_remove(base_vha);
4943
4944 qla84xx_put_chip(base_vha);
4945
4946 if (base_vha->timer_active)
4947 qla2x00_stop_timer(base_vha);
4948
4949 base_vha->flags.online = 0;
4950
4951 qla2x00_destroy_deferred_work(ha);
4952
4953 /*
4954 * Do not try to stop beacon blink as it will issue a mailbox
4955 * command.
4956 */
4957 qla2x00_free_sysfs_attr(base_vha, false);
4958
4959 fc_remove_host(base_vha->host);
4960
4961 scsi_remove_host(base_vha->host);
4962
4963 base_vha->flags.init_done = 0;
4964 qla25xx_delete_queues(base_vha);
4965 qla2x00_free_irqs(base_vha);
4966 qla2x00_free_fcports(base_vha);
4967 qla2x00_mem_free(ha);
4968 qla82xx_md_free(base_vha);
4969 qla2x00_free_queues(ha);
4970
f3ddac19
CD		 4971 qla2x00_unmap_iobases(ha);
4972
4973 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 4974 pci_disable_pcie_error_reporting(pdev);
4975 pci_disable_device(pdev);
f3ddac19 4976
beb9e315
JL		 4977 /*
4978 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
4979 */
f3ddac19
CD		 4980}
4981
1da177e4
LT		 4982/**************************************************************************
4983* qla2x00_do_dpc
4984* This kernel thread is a task that is schedule by the interrupt handler
4985* to perform the background processing for interrupts.
4986*
4987* Notes:
4988* This task always run in the context of a kernel thread. It
4989* is kick-off by the driver's detect code and starts up
4990* up one per adapter. It immediately goes to sleep and waits for
4991* some fibre event. When either the interrupt handler or
4992* the timer routine detects a event it will one of the task
4993* bits then wake us up.
4994**************************************************************************/
4995static int
4996qla2x00_do_dpc(void *data)
4997{
e315cd28
AC		 4998 scsi_qla_host_t *base_vha;
4999 struct qla_hw_data *ha;
1da177e4 5000
e315cd28
AC		 5001 ha = (struct qla_hw_data *)data;
5002 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5003
8698a745 5004 set_user_nice(current, MIN_NICE);
1da177e4 5005
563585ec 5006 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5007 while (!kthread_should_stop()) {
7c3df132
SK		 5008 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5009 "DPC handler sleeping.\n");
1da177e4 5010
39a11240 5011 schedule();
1da177e4 5012
c142caf0
AV		 5013 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5014 goto end_loop;
1da177e4 5015
85880801 5016 if (ha->flags.eeh_busy) {
7c3df132
SK		 5017 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5018 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5019 goto end_loop;
85880801
AV		 5020 }
5021
1da177e4
LT		 5022 ha->dpc_active = 1;
5023
5f28d2d7
SK		 5024 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5025 "DPC handler waking up, dpc_flags=0x%lx.\n",
5026 base_vha->dpc_flags);
1da177e4 5027
a29b3dd7
JC		 5028 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5029 break;
5030
e315cd28 5031 qla2x00_do_work(base_vha);
0971de7f 5032
7ec0effd
AD		 5033 if (IS_P3P_TYPE(ha)) {
5034 if (IS_QLA8044(ha)) {
5035 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5036 &base_vha->dpc_flags)) {
5037 qla8044_idc_lock(ha);
5038 qla8044_wr_direct(base_vha,
5039 QLA8044_CRB_DEV_STATE_INDEX,
5040 QLA8XXX_DEV_FAILED);
5041 qla8044_idc_unlock(ha);
5042 ql_log(ql_log_info, base_vha, 0x4004,
5043 "HW State: FAILED.\n");
5044 qla8044_device_state_handler(base_vha);
5045 continue;
5046 }
5047
5048 } else {
5049 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5050 &base_vha->dpc_flags)) {
5051 qla82xx_idc_lock(ha);
5052 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5053 QLA8XXX_DEV_FAILED);
5054 qla82xx_idc_unlock(ha);
5055 ql_log(ql_log_info, base_vha, 0x0151,
5056 "HW State: FAILED.\n");
5057 qla82xx_device_state_handler(base_vha);
5058 continue;
5059 }
a9083016
GM		 5060 }
5061
5062 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5063 &base_vha->dpc_flags)) {
5064
7c3df132
SK		 5065 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5066 "FCoE context reset scheduled.\n");
a9083016
GM		 5067 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5068 &base_vha->dpc_flags))) {
5069 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5070 /* FCoE-ctx reset failed.
5071 * Escalate to chip-reset
5072 */
5073 set_bit(ISP_ABORT_NEEDED,
5074 &base_vha->dpc_flags);
5075 }
5076 clear_bit(ABORT_ISP_ACTIVE,
5077 &base_vha->dpc_flags);
5078 }
5079
7c3df132
SK		 5080 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5081 "FCoE context reset end.\n");
a9083016 5082 }
8ae6d9c7
GM		 5083 } else if (IS_QLAFX00(ha)) {
5084 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5085 &base_vha->dpc_flags)) {
5086 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5087 "Firmware Reset Recovery\n");
5088 if (qlafx00_reset_initialize(base_vha)) {
5089 /* Failed. Abort isp later. */
5090 if (!test_bit(UNLOADING,
f92f82d6 5091 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5092 set_bit(ISP_UNRECOVERABLE,
5093 &base_vha->dpc_flags);
5094 ql_dbg(ql_dbg_dpc, base_vha,
5095 0x4021,
5096 "Reset Recovery Failed\n");
f92f82d6 5097 }
8ae6d9c7
GM		 5098 }
5099 }
5100
5101 if (test_and_clear_bit(FX00_TARGET_SCAN,
5102 &base_vha->dpc_flags)) {
5103 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5104 "ISPFx00 Target Scan scheduled\n");
5105 if (qlafx00_rescan_isp(base_vha)) {
5106 if (!test_bit(UNLOADING,
5107 &base_vha->dpc_flags))
5108 set_bit(ISP_UNRECOVERABLE,
5109 &base_vha->dpc_flags);
5110 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5111 "ISPFx00 Target Scan Failed\n");
5112 }
5113 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5114 "ISPFx00 Target Scan End\n");
5115 }
e8f5e95d
AB		 5116 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5117 &base_vha->dpc_flags)) {
5118 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5119 "ISPFx00 Host Info resend scheduled\n");
5120 qlafx00_fx_disc(base_vha,
5121 &base_vha->hw->mr.fcport,
5122 FXDISC_REG_HOST_INFO);
5123 }
a9083016
GM		 5124 }
5125
e315cd28
AC		 5126 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5127 &base_vha->dpc_flags)) {
1da177e4 5128
7c3df132
SK		 5129 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5130 "ISP abort scheduled.\n");
1da177e4 5131 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5132 &base_vha->dpc_flags))) {
1da177e4 5133
a9083016 5134 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5135 /* failed. retry later */
5136 set_bit(ISP_ABORT_NEEDED,
e315cd28 5137 &base_vha->dpc_flags);
99363ef8 5138 }
e315cd28
AC		 5139 clear_bit(ABORT_ISP_ACTIVE,
5140 &base_vha->dpc_flags);
99363ef8
SJ		 5141 }
5142
7c3df132
SK		 5143 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5144 "ISP abort end.\n");
1da177e4
LT		 5145 }
5146
a394aac8
DJ		 5147 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5148 &base_vha->dpc_flags)) {
e315cd28 5149 qla2x00_update_fcports(base_vha);
c9c5ced9 5150 }
d97994dc 5151
2d70c103
NB		 5152 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5153 int ret;
5154 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5155 if (ret != QLA_SUCCESS)
5156 ql_log(ql_log_warn, base_vha, 0x121,
5157 "Failed to enable receiving of RSCN "
5158 "requests: 0x%x.\n", ret);
5159 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5160 }
5161
8ae6d9c7
GM		 5162 if (IS_QLAFX00(ha))
5163 goto loop_resync_check;
5164
579d12b5 5165 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5166 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5167 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5168 if (IS_P3P_TYPE(ha)) {
5169 if (IS_QLA82XX(ha))
5170 qla82xx_device_state_handler(base_vha);
5171 if (IS_QLA8044(ha))
5172 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5173 clear_bit(ISP_QUIESCE_NEEDED,
5174 &base_vha->dpc_flags);
5175 if (!ha->flags.quiesce_owner) {
5176 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5177 if (IS_QLA82XX(ha)) {
5178 qla82xx_idc_lock(ha);
5179 qla82xx_clear_qsnt_ready(
5180 base_vha);
5181 qla82xx_idc_unlock(ha);
5182 } else if (IS_QLA8044(ha)) {
5183 qla8044_idc_lock(ha);
5184 qla8044_clear_qsnt_ready(
5185 base_vha);
5186 qla8044_idc_unlock(ha);
5187 }
8fcd6b8b
CD		 5188 }
5189 } else {
5190 clear_bit(ISP_QUIESCE_NEEDED,
5191 &base_vha->dpc_flags);
5192 qla2x00_quiesce_io(base_vha);
579d12b5 5193 }
7c3df132
SK		 5194 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5195 "Quiescence mode end.\n");
579d12b5
SK		 5196 }
5197
e315cd28 5198 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5199 &base_vha->dpc_flags) &&
e315cd28 5200 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5201
7c3df132
SK		 5202 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5203 "Reset marker scheduled.\n");
e315cd28
AC		 5204 qla2x00_rst_aen(base_vha);
5205 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5206 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5207 "Reset marker end.\n");
1da177e4
LT		 5208 }
5209
5210 /* Retry each device up to login retry count */
e315cd28
AC		 5211 if ((test_and_clear_bit(RELOGIN_NEEDED,
5212 &base_vha->dpc_flags)) &&
5213 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5214 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5215
7c3df132
SK		 5216 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5217 "Relogin scheduled.\n");
e315cd28 5218 qla2x00_relogin(base_vha);
7c3df132
SK		 5219 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5220 "Relogin end.\n");
1da177e4 5221 }
8ae6d9c7 5222loop_resync_check:
e315cd28 5223 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5224 &base_vha->dpc_flags)) {
1da177e4 5225
7c3df132
SK		 5226 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5227 "Loop resync scheduled.\n");
1da177e4
LT		 5228
5229 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5230 &base_vha->dpc_flags))) {
1da177e4 5231
52c82823 5232 qla2x00_loop_resync(base_vha);
1da177e4 5233
e315cd28
AC		 5234 clear_bit(LOOP_RESYNC_ACTIVE,
5235 &base_vha->dpc_flags);
1da177e4
LT		 5236 }
5237
7c3df132
SK		 5238 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5239 "Loop resync end.\n");
1da177e4
LT		 5240 }
5241
8ae6d9c7
GM		 5242 if (IS_QLAFX00(ha))
5243 goto intr_on_check;
5244
e315cd28
AC		 5245 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5246 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5247 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5248 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5249 }
5250
8ae6d9c7 5251intr_on_check:
1da177e4 5252 if (!ha->interrupts_on)
fd34f556 5253 ha->isp_ops->enable_intrs(ha);
1da177e4 5254
e315cd28 5255 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5256 &base_vha->dpc_flags)) {
5257 if (ha->beacon_blink_led == 1)
5258 ha->isp_ops->beacon_blink(base_vha);
5259 }
f6df144c 5260
8ae6d9c7
GM		 5261 if (!IS_QLAFX00(ha))
5262 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5263
1da177e4 5264 ha->dpc_active = 0;
c142caf0 5265end_loop:
563585ec 5266 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5267 } /* End of while(1) */
563585ec 5268 __set_current_state(TASK_RUNNING);
1da177e4 5269
7c3df132
SK		 5270 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5271 "DPC handler exiting.\n");
1da177e4
LT		 5272
5273 /*
5274 * Make sure that nobody tries to wake us up again.
5275 */
1da177e4
LT		 5276 ha->dpc_active = 0;
5277
ac280b67
AV		 5278 /* Cleanup any residual CTX SRBs. */
5279 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5280
39a11240
CH		 5281 return 0;
5282}
5283
5284void
e315cd28 5285qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5286{
e315cd28 5287 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5288 struct task_struct *t = ha->dpc_thread;
5289
e315cd28 5290 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5291 wake_up_process(t);
1da177e4
LT		 5292}
5293
1da177e4
LT		 5294/*
5295* qla2x00_rst_aen
5296* Processes asynchronous reset.
5297*
5298* Input:
5299* ha = adapter block pointer.
5300*/
5301static void
e315cd28 5302qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5303{
e315cd28
AC		 5304 if (vha->flags.online && !vha->flags.reset_active &&
5305 !atomic_read(&vha->loop_down_timer) &&
5306 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5307 do {
e315cd28 5308 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5309
5310 /*
5311 * Issue marker command only when we are going to start
5312 * the I/O.
5313 */
e315cd28
AC		 5314 vha->marker_needed = 1;
5315 } while (!atomic_read(&vha->loop_down_timer) &&
5316 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5317 }
5318}
5319
1da177e4
LT		 5320/**************************************************************************
5321* qla2x00_timer
5322*
5323* Description:
5324* One second timer
5325*
5326* Context: Interrupt
5327***************************************************************************/
2c3dfe3f 5328void
e315cd28 5329qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5330{
1da177e4 5331 unsigned long cpu_flags = 0;
1da177e4
LT		 5332 int start_dpc = 0;
5333 int index;
5334 srb_t *sp;
85880801 5335 uint16_t w;
e315cd28 5336 struct qla_hw_data *ha = vha->hw;
73208dfd 5337 struct req_que *req;
85880801 5338
a5b36321 5339 if (ha->flags.eeh_busy) {
7c3df132
SK		 5340 ql_dbg(ql_dbg_timer, vha, 0x6000,
5341 "EEH = %d, restarting timer.\n",
5342 ha->flags.eeh_busy);
a5b36321
LC		 5343 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5344 return;
5345 }
5346
f3ddac19
CD		 5347 /*
5348 * Hardware read to raise pending EEH errors during mailbox waits. If
5349 * the read returns -1 then disable the board.
5350 */
5351 if (!pci_channel_offline(ha->pdev)) {
85880801 5352 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5353 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5354 }
1da177e4 5355
cefcaba6 5356 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5357 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5358 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5359 start_dpc++;
7ec0effd
AD		 5360 if (IS_QLA82XX(ha))
5361 qla82xx_watchdog(vha);
5362 else if (IS_QLA8044(ha))
5363 qla8044_watchdog(vha);
579d12b5
SK		 5364 }
5365
8ae6d9c7
GM		 5366 if (!vha->vp_idx && IS_QLAFX00(ha))
5367 qlafx00_timer_routine(vha);
5368
1da177e4 5369 /* Loop down handler. */
e315cd28 5370 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5371 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5372 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5373 && vha->flags.online) {
1da177e4 5374
e315cd28
AC		 5375 if (atomic_read(&vha->loop_down_timer) ==
5376 vha->loop_down_abort_time) {
1da177e4 5377
7c3df132
SK		 5378 ql_log(ql_log_info, vha, 0x6008,
5379 "Loop down - aborting the queues before time expires.\n");
1da177e4 5380
e315cd28
AC		 5381 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5382 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5383
f08b7251
AV		 5384 /*
5385 * Schedule an ISP abort to return any FCP2-device
5386 * commands.
5387 */
2c3dfe3f 5388 /* NPIV - scan physical port only */
e315cd28 5389 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5390 spin_lock_irqsave(&ha->hardware_lock,
5391 cpu_flags);
73208dfd 5392 req = ha->req_q_map[0];
2c3dfe3f 5393 for (index = 1;
8d93f550 5394 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5395 index++) {
5396 fc_port_t *sfcp;
5397
e315cd28 5398 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5399 if (!sp)
5400 continue;
9ba56b95 5401 if (sp->type != SRB_SCSI_CMD)
cf53b069 5402 continue;
2c3dfe3f 5403 sfcp = sp->fcport;
f08b7251 5404 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5405 continue;
bdf79621 5406
8f7daead
GM		 5407 if (IS_QLA82XX(ha))
5408 set_bit(FCOE_CTX_RESET_NEEDED,
5409 &vha->dpc_flags);
5410 else
5411 set_bit(ISP_ABORT_NEEDED,
e315cd28 5412 &vha->dpc_flags);
2c3dfe3f
SJ		 5413 break;
5414 }
5415 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5416 cpu_flags);
1da177e4 5417 }
1da177e4
LT		 5418 start_dpc++;
5419 }
5420
5421 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5422 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5423 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5424 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5425 "Loop down - aborting ISP.\n");
5426
8f7daead
GM		 5427 if (IS_QLA82XX(ha))
5428 set_bit(FCOE_CTX_RESET_NEEDED,
5429 &vha->dpc_flags);
5430 else
5431 set_bit(ISP_ABORT_NEEDED,
5432 &vha->dpc_flags);
1da177e4
LT		 5433 }
5434 }
7c3df132
SK		 5435 ql_dbg(ql_dbg_timer, vha, 0x600a,
5436 "Loop down - seconds remaining %d.\n",
5437 atomic_read(&vha->loop_down_timer));
1da177e4 5438 }
cefcaba6
SK		 5439 /* Check if beacon LED needs to be blinked for physical host only */
5440 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5441 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5442 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5443 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5444 start_dpc++;
5445 }
f6df144c
AV		 5446 }
5447
550bf57d 5448 /* Process any deferred work. */
e315cd28 5449 if (!list_empty(&vha->work_list))
550bf57d
AV		 5450 start_dpc++;
5451
1da177e4 5452 /* Schedule the DPC routine if needed */
e315cd28
AC		 5453 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5454 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5455 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5456 start_dpc ||
e315cd28
AC		 5457 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5458 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5459 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5460 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5461 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5462 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5463 ql_dbg(ql_dbg_timer, vha, 0x600b,
5464 "isp_abort_needed=%d loop_resync_needed=%d "
5465 "fcport_update_needed=%d start_dpc=%d "
5466 "reset_marker_needed=%d",
5467 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5468 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5469 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5470 start_dpc,
5471 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5472 ql_dbg(ql_dbg_timer, vha, 0x600c,
5473 "beacon_blink_needed=%d isp_unrecoverable=%d "
5474 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5475 "relogin_needed=%d.\n",
7c3df132
SK		 5476 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5477 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5478 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5479 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5480 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5481 qla2xxx_wake_dpc(vha);
7c3df132 5482 }
1da177e4 5483
e315cd28 5484 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5485}
5486
5433383e
AV		 5487/* Firmware interface routines. */
5488
f73cb695 5489#define FW_BLOBS 11
5433383e
AV		 5490#define FW_ISP21XX 0
5491#define FW_ISP22XX 1
5492#define FW_ISP2300 2
5493#define FW_ISP2322 3
48c02fde 5494#define FW_ISP24XX 4
c3a2f0df 5495#define FW_ISP25XX 5
3a03eb79 5496#define FW_ISP81XX 6
a9083016 5497#define FW_ISP82XX 7
6246b8a1
GM		 5498#define FW_ISP2031 8
5499#define FW_ISP8031 9
2c5bbbb2 5500#define FW_ISP27XX 10
5433383e 5501
bb8ee499
AV		 5502#define FW_FILE_ISP21XX "ql2100_fw.bin"
5503#define FW_FILE_ISP22XX "ql2200_fw.bin"
5504#define FW_FILE_ISP2300 "ql2300_fw.bin"
5505#define FW_FILE_ISP2322 "ql2322_fw.bin"
5506#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5507#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5508#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5509#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5510#define FW_FILE_ISP2031 "ql2600_fw.bin"
5511#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5512#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5513
bb8ee499 5514
e1e82b6f 5515static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5516
5517static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5518 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5519 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5520 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5521 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5522 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5523 { .name = FW_FILE_ISP25XX, },
3a03eb79 5524 { .name = FW_FILE_ISP81XX, },
a9083016 5525 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5526 { .name = FW_FILE_ISP2031, },
5527 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5528 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5529};
5530
5531struct fw_blob *
e315cd28 5532qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5533{
e315cd28 5534 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5535 struct fw_blob *blob;
5536
5433383e
AV		 5537 if (IS_QLA2100(ha)) {
5538 blob = &qla_fw_blobs[FW_ISP21XX];
5539 } else if (IS_QLA2200(ha)) {
5540 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5541 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5542 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5543 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5544 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5545 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5546 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5547 } else if (IS_QLA25XX(ha)) {
5548 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5549 } else if (IS_QLA81XX(ha)) {
5550 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5551 } else if (IS_QLA82XX(ha)) {
5552 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5553 } else if (IS_QLA2031(ha)) {
5554 blob = &qla_fw_blobs[FW_ISP2031];
5555 } else if (IS_QLA8031(ha)) {
5556 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5557 } else if (IS_QLA27XX(ha)) {
5558 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5559 } else {
5560 return NULL;
5433383e
AV		 5561 }
5562
e1e82b6f 5563 mutex_lock(&qla_fw_lock);
5433383e
AV		 5564 if (blob->fw)
5565 goto out;
5566
5567 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5568 ql_log(ql_log_warn, vha, 0x0063,
5569 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5570 blob->fw = NULL;
5571 blob = NULL;
5572 goto out;
5573 }
5574
5575out:
e1e82b6f 5576 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5577 return blob;
5578}
5579
5580static void
5581qla2x00_release_firmware(void)
5582{
5583 int idx;
5584
e1e82b6f 5585 mutex_lock(&qla_fw_lock);
5433383e 5586 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5587 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5588 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5589}
5590
14e660e6
SJ		 5591static pci_ers_result_t
5592qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5593{
85880801
AV		 5594 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5595 struct qla_hw_data *ha = vha->hw;
5596
7c3df132
SK		 5597 ql_dbg(ql_dbg_aer, vha, 0x9000,
5598 "PCI error detected, state %x.\n", state);
b9b12f73 5599
14e660e6
SJ		 5600 switch (state) {
5601 case pci_channel_io_normal:
85880801 5602 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5603 return PCI_ERS_RESULT_CAN_RECOVER;
5604 case pci_channel_io_frozen:
85880801 5605 ha->flags.eeh_busy = 1;
a5b36321
LC		 5606 /* For ISP82XX complete any pending mailbox cmd */
5607 if (IS_QLA82XX(ha)) {
7190575f 5608 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5609 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5610 qla82xx_clear_pending_mbx(vha);
a5b36321 5611 }
90a86fc0 5612 qla2x00_free_irqs(vha);
14e660e6 5613 pci_disable_device(pdev);
bddd2d65
LC		 5614 /* Return back all IOs */
5615 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5616 return PCI_ERS_RESULT_NEED_RESET;
5617 case pci_channel_io_perm_failure:
85880801
AV		 5618 ha->flags.pci_channel_io_perm_failure = 1;
5619 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5620 return PCI_ERS_RESULT_DISCONNECT;
5621 }
5622 return PCI_ERS_RESULT_NEED_RESET;
5623}
5624
5625static pci_ers_result_t
5626qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5627{
5628 int risc_paused = 0;
5629 uint32_t stat;
5630 unsigned long flags;
e315cd28
AC		 5631 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5632 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5633 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5634 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5635
bcc5b6d3
SK		 5636 if (IS_QLA82XX(ha))
5637 return PCI_ERS_RESULT_RECOVERED;
5638
14e660e6
SJ		 5639 spin_lock_irqsave(&ha->hardware_lock, flags);
5640 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5641 stat = RD_REG_DWORD(&reg->hccr);
5642 if (stat & HCCR_RISC_PAUSE)
5643 risc_paused = 1;
5644 } else if (IS_QLA23XX(ha)) {
5645 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5646 if (stat & HSR_RISC_PAUSED)
5647 risc_paused = 1;
5648 } else if (IS_FWI2_CAPABLE(ha)) {
5649 stat = RD_REG_DWORD(&reg24->host_status);
5650 if (stat & HSRX_RISC_PAUSED)
5651 risc_paused = 1;
5652 }
5653 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5654
5655 if (risc_paused) {
7c3df132
SK		 5656 ql_log(ql_log_info, base_vha, 0x9003,
5657 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5658 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5659
5660 return PCI_ERS_RESULT_NEED_RESET;
5661 } else
5662 return PCI_ERS_RESULT_RECOVERED;
5663}
5664
fa492630
SK		 5665static uint32_t
5666qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5667{
5668 uint32_t rval = QLA_FUNCTION_FAILED;
5669 uint32_t drv_active = 0;
5670 struct qla_hw_data *ha = base_vha->hw;
5671 int fn;
5672 struct pci_dev *other_pdev = NULL;
5673
7c3df132
SK		 5674 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5675 "Entered %s.\n", __func__);
a5b36321
LC		 5676
5677 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5678
5679 if (base_vha->flags.online) {
5680 /* Abort all outstanding commands,
5681 * so as to be requeued later */
5682 qla2x00_abort_isp_cleanup(base_vha);
5683 }
5684
5685
5686 fn = PCI_FUNC(ha->pdev->devfn);
5687 while (fn > 0) {
5688 fn--;
7c3df132
SK		 5689 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5690 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5691 other_pdev =
5692 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5693 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5694 fn));
5695
5696 if (!other_pdev)
5697 continue;
5698 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5699 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5700 "Found PCI func available and enable at 0x%x.\n",
5701 fn);
a5b36321
LC		 5702 pci_dev_put(other_pdev);
5703 break;
5704 }
5705 pci_dev_put(other_pdev);
5706 }
5707
5708 if (!fn) {
5709 /* Reset owner */
7c3df132
SK		 5710 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5711 "This devfn is reset owner = 0x%x.\n",
5712 ha->pdev->devfn);
a5b36321
LC		 5713 qla82xx_idc_lock(ha);
5714
5715 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5716 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5717
5718 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5719 QLA82XX_IDC_VERSION);
5720
5721 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5722 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5723 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5724
5725 qla82xx_idc_unlock(ha);
5726 /* Reset if device is not already reset
5727 * drv_active would be 0 if a reset has already been done
5728 */
5729 if (drv_active)
5730 rval = qla82xx_start_firmware(base_vha);
5731 else
5732 rval = QLA_SUCCESS;
5733 qla82xx_idc_lock(ha);
5734
5735 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5736 ql_log(ql_log_info, base_vha, 0x900b,
5737 "HW State: FAILED.\n");
a5b36321
LC		 5738 qla82xx_clear_drv_active(ha);
5739 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5740 QLA8XXX_DEV_FAILED);
a5b36321 5741 } else {
7c3df132
SK		 5742 ql_log(ql_log_info, base_vha, 0x900c,
5743 "HW State: READY.\n");
a5b36321 5744 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5745 QLA8XXX_DEV_READY);
a5b36321 5746 qla82xx_idc_unlock(ha);
7190575f 5747 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5748 rval = qla82xx_restart_isp(base_vha);
5749 qla82xx_idc_lock(ha);
5750 /* Clear driver state register */
5751 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5752 qla82xx_set_drv_active(base_vha);
5753 }
5754 qla82xx_idc_unlock(ha);
5755 } else {
7c3df132
SK		 5756 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5757 "This devfn is not reset owner = 0x%x.\n",
5758 ha->pdev->devfn);
a5b36321 5759 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5760 QLA8XXX_DEV_READY)) {
7190575f 5761 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5762 rval = qla82xx_restart_isp(base_vha);
5763 qla82xx_idc_lock(ha);
5764 qla82xx_set_drv_active(base_vha);
5765 qla82xx_idc_unlock(ha);
5766 }
5767 }
5768 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5769
5770 return rval;
5771}
5772
14e660e6
SJ		 5773static pci_ers_result_t
5774qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5775{
5776 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5777 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5778 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5779 struct rsp_que *rsp;
5780 int rc, retries = 10;
09483916 5781
7c3df132
SK		 5782 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5783 "Slot Reset.\n");
85880801 5784
90a86fc0
JC		 5785 /* Workaround: qla2xxx driver which access hardware earlier
5786 * needs error state to be pci_channel_io_online.
5787 * Otherwise mailbox command timesout.
5788 */
5789 pdev->error_state = pci_channel_io_normal;
5790
5791 pci_restore_state(pdev);
5792
8c1496bd
RL		 5793 /* pci_restore_state() clears the saved_state flag of the device
5794 * save restored state which resets saved_state flag
5795 */
5796 pci_save_state(pdev);
5797
09483916
BH		 5798 if (ha->mem_only)
5799 rc = pci_enable_device_mem(pdev);
5800 else
5801 rc = pci_enable_device(pdev);
14e660e6 5802
09483916 5803 if (rc) {
7c3df132 5804 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5805 "Can't re-enable PCI device after reset.\n");
a5b36321 5806 goto exit_slot_reset;
14e660e6 5807 }
14e660e6 5808
90a86fc0
JC		 5809 rsp = ha->rsp_q_map[0];
5810 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5811 goto exit_slot_reset;
90a86fc0 5812
e315cd28 5813 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5814 goto exit_slot_reset;
5815
5816 if (IS_QLA82XX(ha)) {
5817 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5818 ret = PCI_ERS_RESULT_RECOVERED;
5819 goto exit_slot_reset;
5820 } else
5821 goto exit_slot_reset;
5822 }
14e660e6 5823
90a86fc0
JC		 5824 while (ha->flags.mbox_busy && retries--)
5825 msleep(1000);
85880801 5826
e315cd28 5827 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5828 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5829 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5830 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5831
90a86fc0 5832
a5b36321 5833exit_slot_reset:
7c3df132
SK		 5834 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5835 "slot_reset return %x.\n", ret);
85880801 5836
14e660e6
SJ		 5837 return ret;
5838}
5839
5840static void
5841qla2xxx_pci_resume(struct pci_dev *pdev)
5842{
e315cd28
AC		 5843 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5844 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5845 int ret;
5846
7c3df132
SK		 5847 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5848 "pci_resume.\n");
85880801 5849
e315cd28 5850 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5851 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5852 ql_log(ql_log_fatal, base_vha, 0x9002,
5853 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5854 }
85880801 5855
3e46f031
LC		 5856 pci_cleanup_aer_uncorrect_error_status(pdev);
5857
85880801 5858 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5859}
5860
2d5a4c34
HM		 5861static void
5862qla83xx_disable_laser(scsi_qla_host_t *vha)
5863{
5864 uint32_t reg, data, fn;
5865 struct qla_hw_data *ha = vha->hw;
5866 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
5867
5868 /* pci func #/port # */
5869 ql_dbg(ql_dbg_init, vha, 0x004b,
5870 "Disabling Laser for hba: %p\n", vha);
5871
5872 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
5873 (BIT_15|BIT_14|BIT_13|BIT_12));
5874
5875 fn = (fn >> 12);
5876
5877 if (fn & 1)
5878 reg = PORT_1_2031;
5879 else
5880 reg = PORT_0_2031;
5881
5882 data = LASER_OFF_2031;
5883
5884 qla83xx_wr_reg(vha, reg, data);
5885}
5886
a55b2d21 5887static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5888 .error_detected = qla2xxx_pci_error_detected,
5889 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5890 .slot_reset = qla2xxx_pci_slot_reset,
5891 .resume = qla2xxx_pci_resume,
5892};
5893
5433383e 5894static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5895 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5896 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5897 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5898 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5899 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5900 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5901 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5902 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5903 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5904 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5905 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5906 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5907 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5908 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5909 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5910 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5911 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5912 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5913 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 5914 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 5915 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 5916 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 5917 { 0 },
5918};
5919MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5920
fca29703 5921static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5922 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5923 .driver = {
5924 .owner = THIS_MODULE,
5925 },
fca29703 5926 .id_table = qla2xxx_pci_tbl,
7ee61397 5927 .probe = qla2x00_probe_one,
4c993f76 5928 .remove = qla2x00_remove_one,
e30d1756 5929 .shutdown = qla2x00_shutdown,
14e660e6 5930 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5931};
5932
75ef9de1 5933static const struct file_operations apidev_fops = {
6a03b4cd 5934 .owner = THIS_MODULE,
6038f373 5935 .llseek = noop_llseek,
6a03b4cd
HZ		 5936};
5937
1da177e4
LT		 5938/**
5939 * qla2x00_module_init - Module initialization.
5940 **/
5941static int __init
5942qla2x00_module_init(void)
5943{
fca29703
AV		 5944 int ret = 0;
5945
1da177e4 5946 /* Allocate cache for SRBs. */
354d6b21 5947 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5948 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5949 if (srb_cachep == NULL) {
7c3df132
SK		 5950 ql_log(ql_log_fatal, NULL, 0x0001,
5951 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5952 return -ENOMEM;
5953 }
5954
2d70c103
NB		 5955 /* Initialize target kmem_cache and mem_pools */
5956 ret = qlt_init();
5957 if (ret < 0) {
5958 kmem_cache_destroy(srb_cachep);
5959 return ret;
5960 } else if (ret > 0) {
5961 /*
5962 * If initiator mode is explictly disabled by qlt_init(),
5963 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5964 * performing scsi_scan_target() during LOOP UP event.
5965 */
5966 qla2xxx_transport_functions.disable_target_scan = 1;
5967 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5968 }
5969
1da177e4
LT		 5970 /* Derive version string. */
5971 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5972 if (ql2xextended_error_logging)
0181944f
AV		 5973 strcat(qla2x00_version_str, "-debug");
5974
1c97a12a
AV		 5975 qla2xxx_transport_template =
5976 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5977 if (!qla2xxx_transport_template) {
5978 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5979 ql_log(ql_log_fatal, NULL, 0x0002,
5980 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5981 qlt_exit();
1da177e4 5982 return -ENODEV;
2c3dfe3f 5983 }
6a03b4cd
HZ		 5984
5985 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5986 if (apidev_major < 0) {
7c3df132
SK		 5987 ql_log(ql_log_fatal, NULL, 0x0003,
5988 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5989 }
5990
2c3dfe3f
SJ		 5991 qla2xxx_transport_vport_template =
5992 fc_attach_transport(&qla2xxx_transport_vport_functions);
5993 if (!qla2xxx_transport_vport_template) {
5994 kmem_cache_destroy(srb_cachep);
2d70c103 5995 qlt_exit();
2c3dfe3f 5996 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5997 ql_log(ql_log_fatal, NULL, 0x0004,
5998 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5999 return -ENODEV;
2c3dfe3f 6000 }
7c3df132
SK		 6001 ql_log(ql_log_info, NULL, 0x0005,
6002 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6003 qla2x00_version_str);
7ee61397 6004 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6005 if (ret) {
6006 kmem_cache_destroy(srb_cachep);
2d70c103 6007 qlt_exit();
fca29703 6008 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6009 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6010 ql_log(ql_log_fatal, NULL, 0x0006,
6011 "pci_register_driver failed...ret=%d Failing load!.\n",
6012 ret);
fca29703
AV		 6013 }
6014 return ret;
1da177e4
LT		 6015}
6016
6017/**
6018 * qla2x00_module_exit - Module cleanup.
6019 **/
6020static void __exit
6021qla2x00_module_exit(void)
6022{
6a03b4cd 6023 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6024 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6025 qla2x00_release_firmware();
354d6b21 6026 kmem_cache_destroy(srb_cachep);
2d70c103 6027 qlt_exit();
a9083016
GM		 6028 if (ctx_cachep)
6029 kmem_cache_destroy(ctx_cachep);
1da177e4 6030 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6031 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6032}
6033
6034module_init(qla2x00_module_init);
6035module_exit(qla2x00_module_exit);
6036
6037MODULE_AUTHOR("QLogic Corporation");
6038MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6039MODULE_LICENSE("GPL");
6040MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6041MODULE_FIRMWARE(FW_FILE_ISP21XX);
6042MODULE_FIRMWARE(FW_FILE_ISP22XX);
6043MODULE_FIRMWARE(FW_FILE_ISP2300);
6044MODULE_FIRMWARE(FW_FILE_ISP2322);
6045MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6046MODULE_FIRMWARE(FW_FILE_ISP25XX);
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