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scsi: qla2xxx: Add FC-NVMe port discovery and PRLI handling
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
99e1b683
QT		 227int ql2xexchoffld = 1024;
228module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 229MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 230 "Number of target exchanges.");
231
232int ql2xiniexchg = 1024;
233module_param(ql2xiniexchg, uint, 0644);
234MODULE_PARM_DESC(ql2xiniexchg,
235 "Number of initiator exchanges.");
2f56a7f1 236
f198cafa
HM		 237int ql2xfwholdabts = 0;
238module_param(ql2xfwholdabts, int, S_IRUGO);
239MODULE_PARM_DESC(ql2xfwholdabts,
240 "Allow FW to hold status IOCB until ABTS rsp received. "
241 "0 (Default) Do not set fw option. "
242 "1 - Set fw option to hold ABTS.");
243
41dc529a
QT		 244int ql2xmvasynctoatio = 1;
245module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
246MODULE_PARM_DESC(ql2xmvasynctoatio,
247 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
248 "0 (Default). Do not move IOCBs"
249 "1 - Move IOCBs.");
250
1da177e4 251/*
fa2a1ce5 252 * SCSI host template entry points
1da177e4
LT		 253 */
254static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 255static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 256static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
257static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 258static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 259static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 260static int qla2xxx_eh_abort(struct scsi_cmnd *);
261static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 262static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 263static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
264static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 265
1a2fbf18 266static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 267static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 268static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 269static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 270
a5326f86 271struct scsi_host_template qla2xxx_driver_template = {
1da177e4 272 .module = THIS_MODULE,
cb63067a 273 .name = QLA2XXX_DRIVER_NAME,
a5326f86 274 .queuecommand = qla2xxx_queuecommand,
fca29703 275
b6a05c82 276 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 277 .eh_abort_handler = qla2xxx_eh_abort,
278 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 279 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 280 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
281 .eh_host_reset_handler = qla2xxx_eh_host_reset,
282
283 .slave_configure = qla2xxx_slave_configure,
284
285 .slave_alloc = qla2xxx_slave_alloc,
286 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 287 .scan_finished = qla2xxx_scan_finished,
288 .scan_start = qla2xxx_scan_start,
db5ed4df 289 .change_queue_depth = scsi_change_queue_depth,
5601236b 290 .map_queues = qla2xxx_map_queues,
fca29703
AV		 291 .this_id = -1,
292 .cmd_per_lun = 3,
293 .use_clustering = ENABLE_CLUSTERING,
294 .sg_tablesize = SG_ALL,
295
296 .max_sectors = 0xFFFF,
afb046e2 297 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 298
299 .supported_mode = MODE_INITIATOR,
c40ecc12 300 .track_queue_depth = 1,
fca29703
AV		 301};
302
1da177e4 303static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 304struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 305
1da177e4
LT		 306/* TODO Convert to inlines
307 *
308 * Timer routines
309 */
1da177e4 310
2c3dfe3f 311__inline__ void
e315cd28 312qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 313{
e315cd28
AC		 314 init_timer(&vha->timer);
315 vha->timer.expires = jiffies + interval * HZ;
316 vha->timer.data = (unsigned long)vha;
317 vha->timer.function = (void (*)(unsigned long))func;
318 add_timer(&vha->timer);
319 vha->timer_active = 1;
1da177e4
LT		 320}
321
322static inline void
e315cd28 323qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 324{
a9083016 325 /* Currently used for 82XX only. */
7c3df132
SK		 326 if (vha->device_flags & DFLG_DEV_FAILED) {
327 ql_dbg(ql_dbg_timer, vha, 0x600d,
328 "Device in a failed state, returning.\n");
a9083016 329 return;
7c3df132 330 }
a9083016 331
e315cd28 332 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 333}
334
a824ebb3 335static __inline__ void
e315cd28 336qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 337{
e315cd28
AC		 338 del_timer_sync(&vha->timer);
339 vha->timer_active = 0;
1da177e4
LT		 340}
341
1da177e4
LT		 342static int qla2x00_do_dpc(void *data);
343
344static void qla2x00_rst_aen(scsi_qla_host_t *);
345
73208dfd
AC		 346static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
347 struct req_que **, struct rsp_que **);
e30d1756 348static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 349static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 350int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
351 struct qla_qpair *qpair);
1da177e4 352
1da177e4 353/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 354static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
355 struct rsp_que *rsp)
356{
357 struct qla_hw_data *ha = vha->hw;
358 rsp->qpair = ha->base_qpair;
359 rsp->req = req;
360 ha->base_qpair->req = req;
361 ha->base_qpair->rsp = rsp;
362 ha->base_qpair->vha = vha;
363 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
364 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
365 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
366 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
367 ha->base_qpair->enable_class_2 = ql2xenableclass2;
368 /* init qpair to this cpu. Will adjust at run time. */
369 qla_cpu_update(rsp->qpair, smp_processor_id());
370 ha->base_qpair->pdev = ha->pdev;
371
372 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
373 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
374}
375
9a347ff4
CD		 376static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
377 struct rsp_que *rsp)
73208dfd 378{
7c3df132 379 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 380 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 381 GFP_KERNEL);
382 if (!ha->req_q_map) {
7c3df132
SK		 383 ql_log(ql_log_fatal, vha, 0x003b,
384 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 385 goto fail_req_map;
386 }
387
2afa19a9 388 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 389 GFP_KERNEL);
390 if (!ha->rsp_q_map) {
7c3df132
SK		 391 ql_log(ql_log_fatal, vha, 0x003c,
392 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 393 goto fail_rsp_map;
394 }
d7459527 395
e326d22a
QT		 396 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
397 if (ha->base_qpair == NULL) {
398 ql_log(ql_log_warn, vha, 0x00e0,
399 "Failed to allocate base queue pair memory.\n");
400 goto fail_base_qpair;
401 }
402
8abfa9e2 403 qla_init_base_qpair(vha, req, rsp);
e326d22a 404
d7459527
MH		 405 if (ql2xmqsupport && ha->max_qpairs) {
406 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
407 GFP_KERNEL);
408 if (!ha->queue_pair_map) {
409 ql_log(ql_log_fatal, vha, 0x0180,
410 "Unable to allocate memory for queue pair ptrs.\n");
411 goto fail_qpair_map;
412 }
d7459527
MH		 413 }
414
9a347ff4
CD		 415 /*
416 * Make sure we record at least the request and response queue zero in
417 * case we need to free them if part of the probe fails.
418 */
419 ha->rsp_q_map[0] = rsp;
420 ha->req_q_map[0] = req;
73208dfd
AC		 421 set_bit(0, ha->rsp_qid_map);
422 set_bit(0, ha->req_qid_map);
423 return 1;
424
d7459527 425fail_qpair_map:
82de802a
QT		 426 kfree(ha->base_qpair);
427 ha->base_qpair = NULL;
428fail_base_qpair:
d7459527
MH		 429 kfree(ha->rsp_q_map);
430 ha->rsp_q_map = NULL;
73208dfd
AC		 431fail_rsp_map:
432 kfree(ha->req_q_map);
433 ha->req_q_map = NULL;
434fail_req_map:
435 return -ENOMEM;
436}
437
2afa19a9 438static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 439{
8ae6d9c7
GM		 440 if (IS_QLAFX00(ha)) {
441 if (req && req->ring_fx00)
442 dma_free_coherent(&ha->pdev->dev,
443 (req->length_fx00 + 1) * sizeof(request_t),
444 req->ring_fx00, req->dma_fx00);
445 } else if (req && req->ring)
73208dfd
AC		 446 dma_free_coherent(&ha->pdev->dev,
447 (req->length + 1) * sizeof(request_t),
448 req->ring, req->dma);
449
8d93f550
CD		 450 if (req)
451 kfree(req->outstanding_cmds);
452
73208dfd 453 kfree(req);
73208dfd
AC		 454}
455
2afa19a9
AC		 456static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
457{
8ae6d9c7
GM		 458 if (IS_QLAFX00(ha)) {
459 if (rsp && rsp->ring)
460 dma_free_coherent(&ha->pdev->dev,
461 (rsp->length_fx00 + 1) * sizeof(request_t),
462 rsp->ring_fx00, rsp->dma_fx00);
463 } else if (rsp && rsp->ring) {
2afa19a9
AC		 464 dma_free_coherent(&ha->pdev->dev,
465 (rsp->length + 1) * sizeof(response_t),
466 rsp->ring, rsp->dma);
8ae6d9c7 467 }
2afa19a9 468 kfree(rsp);
2afa19a9
AC		 469}
470
73208dfd
AC		 471static void qla2x00_free_queues(struct qla_hw_data *ha)
472{
473 struct req_que *req;
474 struct rsp_que *rsp;
475 int cnt;
093df737 476 unsigned long flags;
73208dfd 477
82de802a
QT		 478 if (ha->queue_pair_map) {
479 kfree(ha->queue_pair_map);
480 ha->queue_pair_map = NULL;
481 }
482 if (ha->base_qpair) {
483 kfree(ha->base_qpair);
484 ha->base_qpair = NULL;
485 }
486
093df737 487 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 488 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 489 if (!test_bit(cnt, ha->req_qid_map))
490 continue;
491
73208dfd 492 req = ha->req_q_map[cnt];
093df737
QT		 493 clear_bit(cnt, ha->req_qid_map);
494 ha->req_q_map[cnt] = NULL;
495
496 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 497 qla2x00_free_req_que(ha, req);
093df737 498 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 499 }
093df737
QT		 500 spin_unlock_irqrestore(&ha->hardware_lock, flags);
501
73208dfd
AC		 502 kfree(ha->req_q_map);
503 ha->req_q_map = NULL;
2afa19a9 504
093df737
QT		 505
506 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 507 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 508 if (!test_bit(cnt, ha->rsp_qid_map))
509 continue;
510
2afa19a9 511 rsp = ha->rsp_q_map[cnt];
c3c42394 512 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 513 ha->rsp_q_map[cnt] = NULL;
514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 515 qla2x00_free_rsp_que(ha, rsp);
093df737 516 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 517 }
093df737
QT		 518 spin_unlock_irqrestore(&ha->hardware_lock, flags);
519
2afa19a9
AC		 520 kfree(ha->rsp_q_map);
521 ha->rsp_q_map = NULL;
73208dfd
AC		 522}
523
1da177e4 524static char *
e315cd28 525qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 526{
e315cd28 527 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 528 static char *pci_bus_modes[] = {
529 "33", "66", "100", "133",
530 };
531 uint16_t pci_bus;
532
533 strcpy(str, "PCI");
534 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
535 if (pci_bus) {
536 strcat(str, "-X (");
537 strcat(str, pci_bus_modes[pci_bus]);
538 } else {
539 pci_bus = (ha->pci_attr & BIT_8) >> 8;
540 strcat(str, " (");
541 strcat(str, pci_bus_modes[pci_bus]);
542 }
543 strcat(str, " MHz)");
544
545 return (str);
546}
547
fca29703 548static char *
e315cd28 549qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 550{
551 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 552 struct qla_hw_data *ha = vha->hw;
fca29703 553 uint32_t pci_bus;
fca29703 554
62a276f8 555 if (pci_is_pcie(ha->pdev)) {
fca29703 556 char lwstr[6];
62a276f8 557 uint32_t lstat, lspeed, lwidth;
fca29703 558
62a276f8
BH		 559 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
560 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
561 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 562
563 strcpy(str, "PCIe (");
49300af7
SK		 564 switch (lspeed) {
565 case 1:
c87a0d8c 566 strcat(str, "2.5GT/s ");
49300af7
SK		 567 break;
568 case 2:
c87a0d8c 569 strcat(str, "5.0GT/s ");
49300af7
SK		 570 break;
571 case 3:
572 strcat(str, "8.0GT/s ");
573 break;
574 default:
fca29703 575 strcat(str, "<unknown> ");
49300af7
SK		 576 break;
577 }
fca29703
AV		 578 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
579 strcat(str, lwstr);
580
581 return str;
582 }
583
584 strcpy(str, "PCI");
585 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
586 if (pci_bus == 0 || pci_bus == 8) {
587 strcat(str, " (");
588 strcat(str, pci_bus_modes[pci_bus >> 3]);
589 } else {
590 strcat(str, "-X ");
591 if (pci_bus & BIT_2)
592 strcat(str, "Mode 2");
593 else
594 strcat(str, "Mode 1");
595 strcat(str, " (");
596 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
597 }
598 strcat(str, " MHz)");
599
600 return str;
601}
602
e5f82ab8 603static char *
df57caba 604qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 605{
606 char un_str[10];
e315cd28 607 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 608
df57caba
HM		 609 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
610 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 611
612 if (ha->fw_attributes & BIT_9) {
613 strcat(str, "FLX");
614 return (str);
615 }
616
617 switch (ha->fw_attributes & 0xFF) {
618 case 0x7:
619 strcat(str, "EF");
620 break;
621 case 0x17:
622 strcat(str, "TP");
623 break;
624 case 0x37:
625 strcat(str, "IP");
626 break;
627 case 0x77:
628 strcat(str, "VI");
629 break;
630 default:
631 sprintf(un_str, "(%x)", ha->fw_attributes);
632 strcat(str, un_str);
633 break;
634 }
635 if (ha->fw_attributes & 0x100)
636 strcat(str, "X");
637
638 return (str);
639}
640
e5f82ab8 641static char *
df57caba 642qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 643{
e315cd28 644 struct qla_hw_data *ha = vha->hw;
f0883ac6 645
df57caba 646 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 647 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 648 return str;
fca29703
AV		 649}
650
9ba56b95 651void
25ff6af1 652qla2x00_sp_free_dma(void *ptr)
fca29703 653{
25ff6af1
JC		 654 srb_t *sp = ptr;
655 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 656 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 657 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 658
9ba56b95
GM		 659 if (sp->flags & SRB_DMA_VALID) {
660 scsi_dma_unmap(cmd);
661 sp->flags &= ~SRB_DMA_VALID;
7c3df132 662 }
fca29703 663
9ba56b95
GM		 664 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
665 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
666 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
667 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
668 }
669
d5ff0eed
JC		 670 if (!ctx)
671 goto end;
672
9ba56b95
GM		 673 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
674 /* List assured to be having elements */
d5ff0eed 675 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 676 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
677 }
678
679 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 680 struct crc_context *ctx0 = ctx;
681
682 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 683 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
684 }
685
686 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 687 struct ct6_dsd *ctx1 = ctx;
fca29703 688
9ba56b95 689 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 690 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 691 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
692 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
693 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
694 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 695 }
696
d5ff0eed 697end:
9ba56b95 698 CMD_SP(cmd) = NULL;
25ff6af1 699 qla2x00_rel_sp(sp);
9ba56b95
GM		 700}
701
d7459527 702void
25ff6af1 703qla2x00_sp_compl(void *ptr, int res)
9ba56b95 704{
25ff6af1 705 srb_t *sp = ptr;
9ba56b95
GM		 706 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
707
708 cmd->result = res;
709
710 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 711 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 712 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
713 sp, GET_CMD_SP(sp));
714 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 715 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 716 return;
717 }
718 if (!atomic_dec_and_test(&sp->ref_count))
719 return;
720
25ff6af1 721 qla2x00_sp_free_dma(sp);
9ba56b95 722 cmd->scsi_done(cmd);
fca29703
AV		 723}
724
d7459527 725void
25ff6af1 726qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 727{
728 srb_t *sp = (srb_t *)ptr;
729 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
730 struct qla_hw_data *ha = sp->fcport->vha->hw;
731 void *ctx = GET_CMD_CTX_SP(sp);
732
733 if (sp->flags & SRB_DMA_VALID) {
734 scsi_dma_unmap(cmd);
735 sp->flags &= ~SRB_DMA_VALID;
736 }
737
738 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
739 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
740 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
741 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
742 }
743
d5ff0eed
JC		 744 if (!ctx)
745 goto end;
746
d7459527
MH		 747 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
748 /* List assured to be having elements */
d5ff0eed 749 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 750 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
751 }
752
753 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 754 struct crc_context *ctx0 = ctx;
755
756 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 757 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
758 }
759
760 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 761 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 762 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
763 ctx1->fcp_cmnd_dma);
764 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
765 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
766 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
767 mempool_free(ctx1, ha->ctx_mempool);
768 }
d5ff0eed 769end:
d7459527
MH		 770 CMD_SP(cmd) = NULL;
771 qla2xxx_rel_qpair_sp(sp->qpair, sp);
772}
773
774void
25ff6af1 775qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 776{
25ff6af1 777 srb_t *sp = ptr;
d7459527
MH		 778 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
779
780 cmd->result = res;
781
782 if (atomic_read(&sp->ref_count) == 0) {
783 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
784 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
785 sp, GET_CMD_SP(sp));
786 if (ql2xextended_error_logging & ql_dbg_io)
787 WARN_ON(atomic_read(&sp->ref_count) == 0);
788 return;
789 }
790 if (!atomic_dec_and_test(&sp->ref_count))
791 return;
792
25ff6af1 793 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 794 cmd->scsi_done(cmd);
795}
796
8ae6d9c7
GM		 797/* If we are SP1 here, we need to still take and release the host_lock as SP1
798 * does not have the changes necessary to avoid taking host->host_lock.
799 */
1da177e4 800static int
f5e3e40b 801qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 802{
134ae078 803 scsi_qla_host_t *vha = shost_priv(host);
fca29703 804 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 805 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 806 struct qla_hw_data *ha = vha->hw;
807 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 808 srb_t *sp;
809 int rval;
5601236b
MH		 810 struct qla_qpair *qpair = NULL;
811 uint32_t tag;
812 uint16_t hwq;
fca29703 813
04dfaa53
MFO		 814 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
815 cmd->result = DID_NO_CONNECT << 16;
816 goto qc24_fail_command;
817 }
818
5601236b
MH		 819 if (ha->mqenable) {
820 if (shost_use_blk_mq(vha->host)) {
821 tag = blk_mq_unique_tag(cmd->request);
822 hwq = blk_mq_unique_tag_to_hwq(tag);
823 qpair = ha->queue_pair_map[hwq];
824 } else if (vha->vp_idx && vha->qpair) {
825 qpair = vha->qpair;
826 }
827
828 if (qpair)
829 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 830 }
831
85880801 832 if (ha->flags.eeh_busy) {
7c3df132 833 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 834 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 835 "PCI Channel IO permanent failure, exiting "
836 "cmd=%p.\n", cmd);
b9b12f73 837 cmd->result = DID_NO_CONNECT << 16;
7c3df132 838 } else {
5f28d2d7 839 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 840 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 841 cmd->result = DID_REQUEUE << 16;
7c3df132 842 }
14e660e6
SJ		 843 goto qc24_fail_command;
844 }
845
19a7b4ae
JSEC		 846 rval = fc_remote_port_chkready(rport);
847 if (rval) {
848 cmd->result = rval;
5f28d2d7 849 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 850 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
851 cmd, rval);
fca29703
AV		 852 goto qc24_fail_command;
853 }
854
bad75002
AE		 855 if (!vha->flags.difdix_supported &&
856 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 857 ql_dbg(ql_dbg_io, vha, 0x3004,
858 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
859 cmd);
bad75002
AE		 860 cmd->result = DID_NO_CONNECT << 16;
861 goto qc24_fail_command;
862 }
aa651be8
CD		 863
864 if (!fcport) {
865 cmd->result = DID_NO_CONNECT << 16;
866 goto qc24_fail_command;
867 }
868
fca29703
AV		 869 if (atomic_read(&fcport->state) != FCS_ONLINE) {
870 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 871 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 872 ql_dbg(ql_dbg_io, vha, 0x3005,
873 "Returning DNC, fcport_state=%d loop_state=%d.\n",
874 atomic_read(&fcport->state),
875 atomic_read(&base_vha->loop_state));
fca29703
AV		 876 cmd->result = DID_NO_CONNECT << 16;
877 goto qc24_fail_command;
878 }
7b594131 879 goto qc24_target_busy;
fca29703
AV		 880 }
881
e05fe292
CD		 882 /*
883 * Return target busy if we've received a non-zero retry_delay_timer
884 * in a FCP_RSP.
885 */
975f7d46
BP		 886 if (fcport->retry_delay_timestamp == 0) {
887 /* retry delay not set */
888 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 889 fcport->retry_delay_timestamp = 0;
890 else
891 goto qc24_target_busy;
892
b00ee7d7 893 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 894 if (!sp)
f5e3e40b 895 goto qc24_host_busy;
fca29703 896
9ba56b95
GM		 897 sp->u.scmd.cmd = cmd;
898 sp->type = SRB_SCSI_CMD;
899 atomic_set(&sp->ref_count, 1);
900 CMD_SP(cmd) = (void *)sp;
901 sp->free = qla2x00_sp_free_dma;
902 sp->done = qla2x00_sp_compl;
903
e315cd28 904 rval = ha->isp_ops->start_scsi(sp);
7c3df132 905 if (rval != QLA_SUCCESS) {
53016ed3 906 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 907 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 908 goto qc24_host_busy_free_sp;
7c3df132 909 }
fca29703 910
fca29703
AV		 911 return 0;
912
913qc24_host_busy_free_sp:
25ff6af1 914 qla2x00_sp_free_dma(sp);
fca29703 915
f5e3e40b 916qc24_host_busy:
fca29703
AV		 917 return SCSI_MLQUEUE_HOST_BUSY;
918
7b594131
MC		 919qc24_target_busy:
920 return SCSI_MLQUEUE_TARGET_BUSY;
921
fca29703 922qc24_fail_command:
f5e3e40b 923 cmd->scsi_done(cmd);
fca29703
AV		 924
925 return 0;
926}
927
d7459527
MH		 928/* For MQ supported I/O */
929int
930qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
931 struct qla_qpair *qpair)
932{
933 scsi_qla_host_t *vha = shost_priv(host);
934 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
935 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
936 struct qla_hw_data *ha = vha->hw;
937 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
938 srb_t *sp;
939 int rval;
940
941 rval = fc_remote_port_chkready(rport);
942 if (rval) {
943 cmd->result = rval;
944 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
945 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
946 cmd, rval);
947 goto qc24_fail_command;
948 }
949
950 if (!fcport) {
951 cmd->result = DID_NO_CONNECT << 16;
952 goto qc24_fail_command;
953 }
954
955 if (atomic_read(&fcport->state) != FCS_ONLINE) {
956 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
957 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
958 ql_dbg(ql_dbg_io, vha, 0x3077,
959 "Returning DNC, fcport_state=%d loop_state=%d.\n",
960 atomic_read(&fcport->state),
961 atomic_read(&base_vha->loop_state));
962 cmd->result = DID_NO_CONNECT << 16;
963 goto qc24_fail_command;
964 }
965 goto qc24_target_busy;
966 }
967
968 /*
969 * Return target busy if we've received a non-zero retry_delay_timer
970 * in a FCP_RSP.
971 */
972 if (fcport->retry_delay_timestamp == 0) {
973 /* retry delay not set */
974 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
975 fcport->retry_delay_timestamp = 0;
976 else
977 goto qc24_target_busy;
978
979 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
980 if (!sp)
981 goto qc24_host_busy;
982
983 sp->u.scmd.cmd = cmd;
984 sp->type = SRB_SCSI_CMD;
985 atomic_set(&sp->ref_count, 1);
986 CMD_SP(cmd) = (void *)sp;
987 sp->free = qla2xxx_qpair_sp_free_dma;
988 sp->done = qla2xxx_qpair_sp_compl;
989 sp->qpair = qpair;
990
991 rval = ha->isp_ops->start_scsi_mq(sp);
992 if (rval != QLA_SUCCESS) {
993 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
994 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
995 if (rval == QLA_INTERFACE_ERROR)
996 goto qc24_fail_command;
997 goto qc24_host_busy_free_sp;
998 }
999
1000 return 0;
1001
1002qc24_host_busy_free_sp:
25ff6af1 1003 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 1004
1005qc24_host_busy:
1006 return SCSI_MLQUEUE_HOST_BUSY;
1007
1008qc24_target_busy:
1009 return SCSI_MLQUEUE_TARGET_BUSY;
1010
1011qc24_fail_command:
1012 cmd->scsi_done(cmd);
1013
1014 return 0;
1015}
1016
1da177e4
LT		 1017/*
1018 * qla2x00_eh_wait_on_command
1019 * Waits for the command to be returned by the Firmware for some
1020 * max time.
1021 *
1022 * Input:
1da177e4 1023 * cmd = Scsi Command to wait on.
1da177e4
LT		 1024 *
1025 * Return:
1026 * Not Found : 0
1027 * Found : 1
1028 */
1029static int
e315cd28 1030qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1031{
fe74c71f 1032#define ABORT_POLLING_PERIOD 1000
478c3b03 1033#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1034 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1035 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1036 struct qla_hw_data *ha = vha->hw;
f4f051eb 1037 int ret = QLA_SUCCESS;
1da177e4 1038
85880801 1039 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1040 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1041 "Return:eh_wait.\n");
85880801
AV		 1042 return ret;
1043 }
1044
d970432c 1045 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1046 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1047 }
1048 if (CMD_SP(cmd))
1049 ret = QLA_FUNCTION_FAILED;
1da177e4 1050
f4f051eb 1051 return ret;
1da177e4
LT		 1052}
1053
1054/*
1055 * qla2x00_wait_for_hba_online
fa2a1ce5 1056 * Wait till the HBA is online after going through
1da177e4
LT		 1057 * <= MAX_RETRIES_OF_ISP_ABORT or
1058 * finally HBA is disabled ie marked offline
1059 *
1060 * Input:
1061 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1062 *
1063 * Note:
1da177e4
LT		 1064 * Does context switching-Release SPIN_LOCK
1065 * (if any) before calling this routine.
1066 *
1067 * Return:
1068 * Success (Adapter is online) : 0
1069 * Failed (Adapter is offline/disabled) : 1
1070 */
854165f4 1071int
e315cd28 1072qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1073{
fca29703
AV		 1074 int return_status;
1075 unsigned long wait_online;
e315cd28
AC		 1076 struct qla_hw_data *ha = vha->hw;
1077 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1078
fa2a1ce5 1079 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1080 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1081 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1082 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1083 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1084
1085 msleep(1000);
1086 }
e315cd28 1087 if (base_vha->flags.online)
fa2a1ce5 1088 return_status = QLA_SUCCESS;
1da177e4
LT		 1089 else
1090 return_status = QLA_FUNCTION_FAILED;
1091
1da177e4
LT		 1092 return (return_status);
1093}
1094
726b8548
QT		 1095static inline int test_fcport_count(scsi_qla_host_t *vha)
1096{
1097 struct qla_hw_data *ha = vha->hw;
1098 unsigned long flags;
1099 int res;
1100
1101 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1102 ql_dbg(ql_dbg_init, vha, 0x00ec,
1103 "tgt %p, fcport_count=%d\n",
1104 vha, vha->fcport_count);
726b8548
QT		 1105 res = (vha->fcport_count == 0);
1106 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1107
1108 return res;
1109}
1110
1111/*
1112 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1113 * it has dependency on UNLOADING flag to stop device discovery
1114 */
1115static void
1116qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1117{
1118 qla2x00_mark_all_devices_lost(vha, 0);
1119
1120 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1121}
1122
86fbee86 1123/*
638a1a01
SC		 1124 * qla2x00_wait_for_hba_ready
1125 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1126 *
1127 * Input:
1128 * ha - pointer to host adapter structure
1129 *
1130 * Note:
1131 * Does context switching-Release SPIN_LOCK
1132 * (if any) before calling this routine.
1133 *
86fbee86 1134 */
638a1a01
SC		 1135static void
1136qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1137{
86fbee86 1138 struct qla_hw_data *ha = vha->hw;
783e0dc4 1139 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1140
1d483901
DC		 1141 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1142 ha->flags.mbox_busy) ||
1143 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1144 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1145 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1146 break;
86fbee86 1147 msleep(1000);
783e0dc4 1148 }
86fbee86
LC		 1149}
1150
2533cf67
LC		 1151int
1152qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1153{
1154 int return_status;
1155 unsigned long wait_reset;
1156 struct qla_hw_data *ha = vha->hw;
1157 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1158
1159 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1160 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1161 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1162 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1163 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1164
1165 msleep(1000);
1166
1167 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1168 ha->flags.chip_reset_done)
1169 break;
1170 }
1171 if (ha->flags.chip_reset_done)
1172 return_status = QLA_SUCCESS;
1173 else
1174 return_status = QLA_FUNCTION_FAILED;
1175
1176 return return_status;
1177}
1178
083a469d
GM		 1179static void
1180sp_get(struct srb *sp)
1181{
1182 atomic_inc(&sp->ref_count);
1183}
1184
a465537a
SC		 1185#define ISP_REG_DISCONNECT 0xffffffffU
1186/**************************************************************************
1187* qla2x00_isp_reg_stat
1188*
1189* Description:
1190* Read the host status register of ISP before aborting the command.
1191*
1192* Input:
1193* ha = pointer to host adapter structure.
1194*
1195*
1196* Returns:
1197* Either true or false.
1198*
1199* Note: Return true if there is register disconnect.
1200**************************************************************************/
1201static inline
1202uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1203{
1204 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1205 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1206
bf6061b1
SC		 1207 if (IS_P3P_TYPE(ha))
1208 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1209 else
1210 return ((RD_REG_DWORD(&reg->host_status)) ==
1211 ISP_REG_DISCONNECT);
a465537a
SC		 1212}
1213
1da177e4
LT		 1214/**************************************************************************
1215* qla2xxx_eh_abort
1216*
1217* Description:
1218* The abort function will abort the specified command.
1219*
1220* Input:
1221* cmd = Linux SCSI command packet to be aborted.
1222*
1223* Returns:
1224* Either SUCCESS or FAILED.
1225*
1226* Note:
2ea00202 1227* Only return FAILED if command not returned by firmware.
1da177e4 1228**************************************************************************/
e5f82ab8 1229static int
1da177e4
LT		 1230qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1231{
e315cd28 1232 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1233 srb_t *sp;
4e98d3b8 1234 int ret;
9cb78c16
HR		 1235 unsigned int id;
1236 uint64_t lun;
18e144d3 1237 unsigned long flags;
f934c9d0 1238 int rval, wait = 0;
e315cd28 1239 struct qla_hw_data *ha = vha->hw;
1da177e4 1240
a465537a
SC		 1241 if (qla2x00_isp_reg_stat(ha)) {
1242 ql_log(ql_log_info, vha, 0x8042,
1243 "PCI/Register disconnect, exiting.\n");
1244 return FAILED;
1245 }
f4f051eb 1246 if (!CMD_SP(cmd))
2ea00202 1247 return SUCCESS;
1da177e4 1248
4e98d3b8
AV		 1249 ret = fc_block_scsi_eh(cmd);
1250 if (ret != 0)
1251 return ret;
1252 ret = SUCCESS;
1253
f4f051eb
AV		 1254 id = cmd->device->id;
1255 lun = cmd->device->lun;
1da177e4 1256
e315cd28 1257 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1258 sp = (srb_t *) CMD_SP(cmd);
1259 if (!sp) {
1260 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1261 return SUCCESS;
1262 }
1da177e4 1263
7c3df132 1264 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1265 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1266 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1267
170babc3
MC		 1268 /* Get a reference to the sp and drop the lock.*/
1269 sp_get(sp);
083a469d 1270
e315cd28 1271 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1272 rval = ha->isp_ops->abort_command(sp);
1273 if (rval) {
96219424 1274 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1275 ret = SUCCESS;
96219424 1276 else
f934c9d0
CD		 1277 ret = FAILED;
1278
7c3df132 1279 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1280 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1281 } else {
7c3df132 1282 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1283 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1284 wait = 1;
1285 }
75942064
SK		 1286
1287 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1288 sp->done(sp, 0);
75942064 1289 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1290
bc91ade9
CD		 1291 /* Did the command return during mailbox execution? */
1292 if (ret == FAILED && !CMD_SP(cmd))
1293 ret = SUCCESS;
1294
f4f051eb 1295 /* Wait for the command to be returned. */
2ea00202 1296 if (wait) {
e315cd28 1297 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1298 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1299 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1300 ret = FAILED;
f4f051eb 1301 }
1da177e4 1302 }
1da177e4 1303
7c3df132 1304 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1305 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1306 vha->host_no, id, lun, wait, ret);
1da177e4 1307
f4f051eb
AV		 1308 return ret;
1309}
1da177e4 1310
4d78c973 1311int
e315cd28 1312qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1313 uint64_t l, enum nexus_wait_type type)
f4f051eb 1314{
17d98630 1315 int cnt, match, status;
18e144d3 1316 unsigned long flags;
e315cd28 1317 struct qla_hw_data *ha = vha->hw;
73208dfd 1318 struct req_que *req;
4d78c973 1319 srb_t *sp;
9ba56b95 1320 struct scsi_cmnd *cmd;
1da177e4 1321
523ec773 1322 status = QLA_SUCCESS;
17d98630 1323
e315cd28 1324 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1325 req = vha->req;
17d98630 1326 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1327 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1328 sp = req->outstanding_cmds[cnt];
1329 if (!sp)
523ec773 1330 continue;
9ba56b95 1331 if (sp->type != SRB_SCSI_CMD)
cf53b069 1332 continue;
25ff6af1 1333 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1334 continue;
1335 match = 0;
9ba56b95 1336 cmd = GET_CMD_SP(sp);
17d98630
AC		 1337 switch (type) {
1338 case WAIT_HOST:
1339 match = 1;
1340 break;
1341 case WAIT_TARGET:
9ba56b95 1342 match = cmd->device->id == t;
17d98630
AC		 1343 break;
1344 case WAIT_LUN:
9ba56b95
GM		 1345 match = (cmd->device->id == t &&
1346 cmd->device->lun == l);
17d98630 1347 break;
73208dfd 1348 }
17d98630
AC		 1349 if (!match)
1350 continue;
1351
1352 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1353 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1354 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1355 }
e315cd28 1356 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1357
1358 return status;
1da177e4
LT		 1359}
1360
523ec773
AV		 1361static char *reset_errors[] = {
1362 "HBA not online",
1363 "HBA not ready",
1364 "Task management failed",
1365 "Waiting for command completions",
1366};
1da177e4 1367
e5f82ab8 1368static int
523ec773 1369__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1370 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1371{
e315cd28 1372 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1373 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1374 int err;
1da177e4 1375
7c3df132 1376 if (!fcport) {
523ec773 1377 return FAILED;
7c3df132 1378 }
1da177e4 1379
4e98d3b8
AV		 1380 err = fc_block_scsi_eh(cmd);
1381 if (err != 0)
1382 return err;
1383
7c3df132 1384 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1385 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1386 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1387
523ec773 1388 err = 0;
7c3df132
SK		 1389 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1390 ql_log(ql_log_warn, vha, 0x800a,
1391 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1392 goto eh_reset_failed;
7c3df132 1393 }
523ec773 1394 err = 2;
2afa19a9 1395 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1396 != QLA_SUCCESS) {
1397 ql_log(ql_log_warn, vha, 0x800c,
1398 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1399 goto eh_reset_failed;
7c3df132 1400 }
523ec773 1401 err = 3;
e315cd28 1402 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1403 cmd->device->lun, type) != QLA_SUCCESS) {
1404 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1405 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1406 goto eh_reset_failed;
7c3df132 1407 }
523ec773 1408
7c3df132 1409 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1410 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1411 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1412
1413 return SUCCESS;
1414
4d78c973 1415eh_reset_failed:
7c3df132 1416 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1417 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1418 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1419 cmd);
523ec773
AV		 1420 return FAILED;
1421}
1da177e4 1422
523ec773
AV		 1423static int
1424qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1425{
e315cd28
AC		 1426 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1427 struct qla_hw_data *ha = vha->hw;
1da177e4 1428
a465537a
SC		 1429 if (qla2x00_isp_reg_stat(ha)) {
1430 ql_log(ql_log_info, vha, 0x803e,
1431 "PCI/Register disconnect, exiting.\n");
1432 return FAILED;
1433 }
1434
523ec773
AV		 1435 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1436 ha->isp_ops->lun_reset);
1da177e4
LT		 1437}
1438
1da177e4 1439static int
523ec773 1440qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1441{
e315cd28
AC		 1442 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1443 struct qla_hw_data *ha = vha->hw;
1da177e4 1444
a465537a
SC		 1445 if (qla2x00_isp_reg_stat(ha)) {
1446 ql_log(ql_log_info, vha, 0x803f,
1447 "PCI/Register disconnect, exiting.\n");
1448 return FAILED;
1449 }
1450
523ec773
AV		 1451 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1452 ha->isp_ops->target_reset);
1da177e4
LT		 1453}
1454
1da177e4
LT		 1455/**************************************************************************
1456* qla2xxx_eh_bus_reset
1457*
1458* Description:
1459* The bus reset function will reset the bus and abort any executing
1460* commands.
1461*
1462* Input:
1463* cmd = Linux SCSI command packet of the command that cause the
1464* bus reset.
1465*
1466* Returns:
1467* SUCCESS/FAILURE (defined as macro in scsi.h).
1468*
1469**************************************************************************/
e5f82ab8 1470static int
1da177e4
LT		 1471qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1472{
e315cd28 1473 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1474 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1475 int ret = FAILED;
9cb78c16
HR		 1476 unsigned int id;
1477 uint64_t lun;
a465537a
SC		 1478 struct qla_hw_data *ha = vha->hw;
1479
1480 if (qla2x00_isp_reg_stat(ha)) {
1481 ql_log(ql_log_info, vha, 0x8040,
1482 "PCI/Register disconnect, exiting.\n");
1483 return FAILED;
1484 }
f4f051eb 1485
f4f051eb
AV		 1486 id = cmd->device->id;
1487 lun = cmd->device->lun;
1da177e4 1488
7c3df132 1489 if (!fcport) {
f4f051eb 1490 return ret;
7c3df132 1491 }
1da177e4 1492
4e98d3b8
AV		 1493 ret = fc_block_scsi_eh(cmd);
1494 if (ret != 0)
1495 return ret;
1496 ret = FAILED;
1497
7c3df132 1498 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1499 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1500
e315cd28 1501 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1502 ql_log(ql_log_fatal, vha, 0x8013,
1503 "Wait for hba online failed board disabled.\n");
f4f051eb 1504 goto eh_bus_reset_done;
1da177e4
LT		 1505 }
1506
ad537689
SK		 1507 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1508 ret = SUCCESS;
1509
f4f051eb
AV		 1510 if (ret == FAILED)
1511 goto eh_bus_reset_done;
1da177e4 1512
9a41a62b 1513 /* Flush outstanding commands. */
4d78c973 1514 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1515 QLA_SUCCESS) {
1516 ql_log(ql_log_warn, vha, 0x8014,
1517 "Wait for pending commands failed.\n");
9a41a62b 1518 ret = FAILED;
7c3df132 1519 }
1da177e4 1520
f4f051eb 1521eh_bus_reset_done:
7c3df132 1522 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1523 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1524 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1525
f4f051eb 1526 return ret;
1da177e4
LT		 1527}
1528
1529/**************************************************************************
1530* qla2xxx_eh_host_reset
1531*
1532* Description:
1533* The reset function will reset the Adapter.
1534*
1535* Input:
1536* cmd = Linux SCSI command packet of the command that cause the
1537* adapter reset.
1538*
1539* Returns:
1540* Either SUCCESS or FAILED.
1541*
1542* Note:
1543**************************************************************************/
e5f82ab8 1544static int
1da177e4
LT		 1545qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1546{
e315cd28 1547 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1548 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1549 int ret = FAILED;
9cb78c16
HR		 1550 unsigned int id;
1551 uint64_t lun;
e315cd28 1552 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1553
a465537a
SC		 1554 if (qla2x00_isp_reg_stat(ha)) {
1555 ql_log(ql_log_info, vha, 0x8041,
1556 "PCI/Register disconnect, exiting.\n");
1557 schedule_work(&ha->board_disable);
1558 return SUCCESS;
1559 }
1560
f4f051eb
AV		 1561 id = cmd->device->id;
1562 lun = cmd->device->lun;
f4f051eb 1563
7c3df132 1564 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1565 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1566
63ee7072
CD		 1567 /*
1568 * No point in issuing another reset if one is active. Also do not
1569 * attempt a reset if we are updating flash.
1570 */
1571 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1572 goto eh_host_reset_lock;
1da177e4 1573
e315cd28
AC		 1574 if (vha != base_vha) {
1575 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1576 goto eh_host_reset_lock;
e315cd28 1577 } else {
7ec0effd 1578 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1579 if (!qla82xx_fcoe_ctx_reset(vha)) {
1580 /* Ctx reset success */
1581 ret = SUCCESS;
1582 goto eh_host_reset_lock;
1583 }
1584 /* fall thru if ctx reset failed */
1585 }
68ca949c
AC		 1586 if (ha->wq)
1587 flush_workqueue(ha->wq);
1588
e315cd28 1589 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1590 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1591 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1592 /* failed. schedule dpc to try */
1593 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1594
7c3df132
SK		 1595 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1596 ql_log(ql_log_warn, vha, 0x802a,
1597 "wait for hba online failed.\n");
e315cd28 1598 goto eh_host_reset_lock;
7c3df132 1599 }
e315cd28
AC		 1600 }
1601 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1602 }
1da177e4 1603
e315cd28 1604 /* Waiting for command to be returned to OS.*/
4d78c973 1605 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1606 QLA_SUCCESS)
f4f051eb 1607 ret = SUCCESS;
1da177e4 1608
f4f051eb 1609eh_host_reset_lock:
cfb0919c 1610 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1611 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1612 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1613
f4f051eb
AV		 1614 return ret;
1615}
1da177e4
LT		 1616
1617/*
1618* qla2x00_loop_reset
1619* Issue loop reset.
1620*
1621* Input:
1622* ha = adapter block pointer.
1623*
1624* Returns:
1625* 0 = success
1626*/
a4722cf2 1627int
e315cd28 1628qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1629{
0c8c39af 1630 int ret;
bdf79621 1631 struct fc_port *fcport;
e315cd28 1632 struct qla_hw_data *ha = vha->hw;
1da177e4 1633
5854771e
AB		 1634 if (IS_QLAFX00(ha)) {
1635 return qlafx00_loop_reset(vha);
1636 }
1637
f4c496c1 1638 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1639 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1640 if (fcport->port_type != FCT_TARGET)
1641 continue;
1642
1643 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1644 if (ret != QLA_SUCCESS) {
7c3df132 1645 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1646 "Bus Reset failed: Reset=%d "
7c3df132 1647 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1648 }
1649 }
1650 }
1651
8ae6d9c7 1652
6246b8a1 1653 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1654 atomic_set(&vha->loop_state, LOOP_DOWN);
1655 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1656 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1657 ret = qla2x00_full_login_lip(vha);
0c8c39af 1658 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1659 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1660 "full_login_lip=%d.\n", ret);
749af3d5 1661 }
0c8c39af
AV		 1662 }
1663
0d6e61bc 1664 if (ha->flags.enable_lip_reset) {
e315cd28 1665 ret = qla2x00_lip_reset(vha);
ad537689 1666 if (ret != QLA_SUCCESS)
7c3df132
SK		 1667 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1668 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1669 }
1670
1da177e4 1671 /* Issue marker command only when we are going to start the I/O */
e315cd28 1672 vha->marker_needed = 1;
1da177e4 1673
0c8c39af 1674 return QLA_SUCCESS;
1da177e4
LT		 1675}
1676
df4bf0bb 1677void
e315cd28 1678qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1679{
4cd3b6eb 1680 int que, cnt, status;
df4bf0bb
AV		 1681 unsigned long flags;
1682 srb_t *sp;
e315cd28 1683 struct qla_hw_data *ha = vha->hw;
73208dfd 1684 struct req_que *req;
c5419e26
QT		 1685 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1686 struct qla_tgt_cmd *cmd;
1687 uint8_t trace = 0;
c0cb4496 1688
df4bf0bb 1689 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1690 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1691 req = ha->req_q_map[que];
73208dfd
AC		 1692 if (!req)
1693 continue;
8d93f550
CD		 1694 if (!req->outstanding_cmds)
1695 continue;
1696 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1697 sp = req->outstanding_cmds[cnt];
e612d465 1698 if (sp) {
c5419e26
QT		 1699 req->outstanding_cmds[cnt] = NULL;
1700 if (sp->cmd_type == TYPE_SRB) {
1701 /*
1702 * Don't abort commands in adapter
1703 * during EEH recovery as it's not
1704 * accessible/responding.
c733ab35 1705 */
c5419e26
QT		 1706 if (GET_CMD_SP(sp) &&
1707 !ha->flags.eeh_busy &&
1708 (sp->type == SRB_SCSI_CMD)) {
1709 /*
1710 * Get a reference to the sp
1711 * and drop the lock. The
1712 * reference ensures this
1713 * sp->done() call and not the
1714 * call in qla2xxx_eh_abort()
1715 * ends the SCSI command (with
1716 * result 'res').
1717 */
1718 sp_get(sp);
1719 spin_unlock_irqrestore(
1720 &ha->hardware_lock, flags);
1721 status = qla2xxx_eh_abort(
1722 GET_CMD_SP(sp));
1723 spin_lock_irqsave(
1724 &ha->hardware_lock, flags);
1725 /*
1726 * Get rid of extra reference
1727 * if immediate exit from
1728 * ql2xxx_eh_abort
1729 */
1730 if (status == FAILED &&
1731 (qla2x00_isp_reg_stat(ha)))
1732 atomic_dec(
1733 &sp->ref_count);
1734 }
1735 sp->done(sp, res);
1736 } else {
1737 if (!vha->hw->tgt.tgt_ops || !tgt ||
1738 qla_ini_mode_enabled(vha)) {
1739 if (!trace)
1740 ql_dbg(ql_dbg_tgt_mgt,
1741 vha, 0xf003,
1742 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1743 vha->dpc_flags);
1744 continue;
1745 }
1746 cmd = (struct qla_tgt_cmd *)sp;
1747 qlt_abort_cmd_on_host_reset(cmd->vha,
1748 cmd);
c733ab35 1749 }
73208dfd 1750 }
df4bf0bb
AV		 1751 }
1752 }
1753 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1754}
1755
f4f051eb
AV		 1756static int
1757qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1758{
bdf79621 1759 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1760
19a7b4ae 1761 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1762 return -ENXIO;
bdf79621 1763
19a7b4ae 1764 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1765
f4f051eb
AV		 1766 return 0;
1767}
1da177e4 1768
f4f051eb
AV		 1769static int
1770qla2xxx_slave_configure(struct scsi_device *sdev)
1771{
e315cd28 1772 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1773 struct req_que *req = vha->req;
8482e118 1774
9e522cd8
AE		 1775 if (IS_T10_PI_CAPABLE(vha->hw))
1776 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1777
db5ed4df 1778 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1779 return 0;
1780}
1da177e4 1781
f4f051eb
AV		 1782static void
1783qla2xxx_slave_destroy(struct scsi_device *sdev)
1784{
1785 sdev->hostdata = NULL;
1da177e4
LT		 1786}
1787
1788/**
1789 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1790 * @ha: HA context
1791 *
1792 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1793 * supported addressing method.
1794 */
1795static void
53303c42 1796qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1797{
7524f9b9 1798 /* Assume a 32bit DMA mask. */
1da177e4 1799 ha->flags.enable_64bit_addressing = 0;
1da177e4 1800
6a35528a 1801 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1802 /* Any upper-dword bits set? */
1803 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1804 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1805 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1806 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1807 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1808 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1809 return;
1da177e4 1810 }
1da177e4 1811 }
7524f9b9 1812
284901a9
YH		 1813 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1814 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1815}
1816
fd34f556 1817static void
e315cd28 1818qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1819{
1820 unsigned long flags = 0;
1821 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1822
1823 spin_lock_irqsave(&ha->hardware_lock, flags);
1824 ha->interrupts_on = 1;
1825 /* enable risc and host interrupts */
1826 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1827 RD_REG_WORD(&reg->ictrl);
1828 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1829
1830}
1831
1832static void
e315cd28 1833qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1834{
1835 unsigned long flags = 0;
1836 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1837
1838 spin_lock_irqsave(&ha->hardware_lock, flags);
1839 ha->interrupts_on = 0;
1840 /* disable risc and host interrupts */
1841 WRT_REG_WORD(&reg->ictrl, 0);
1842 RD_REG_WORD(&reg->ictrl);
1843 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1844}
1845
1846static void
e315cd28 1847qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1848{
1849 unsigned long flags = 0;
1850 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1851
1852 spin_lock_irqsave(&ha->hardware_lock, flags);
1853 ha->interrupts_on = 1;
1854 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1855 RD_REG_DWORD(&reg->ictrl);
1856 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1857}
1858
1859static void
e315cd28 1860qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1861{
1862 unsigned long flags = 0;
1863 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1864
124f85e6
AV		 1865 if (IS_NOPOLLING_TYPE(ha))
1866 return;
fd34f556
AV		 1867 spin_lock_irqsave(&ha->hardware_lock, flags);
1868 ha->interrupts_on = 0;
1869 WRT_REG_DWORD(&reg->ictrl, 0);
1870 RD_REG_DWORD(&reg->ictrl);
1871 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1872}
1873
706f457d
GM		 1874static int
1875qla2x00_iospace_config(struct qla_hw_data *ha)
1876{
1877 resource_size_t pio;
1878 uint16_t msix;
706f457d 1879
706f457d
GM		 1880 if (pci_request_selected_regions(ha->pdev, ha->bars,
1881 QLA2XXX_DRIVER_NAME)) {
1882 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1883 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1884 pci_name(ha->pdev));
1885 goto iospace_error_exit;
1886 }
1887 if (!(ha->bars & 1))
1888 goto skip_pio;
1889
1890 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1891 pio = pci_resource_start(ha->pdev, 0);
1892 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1893 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1894 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1895 "Invalid pci I/O region size (%s).\n",
1896 pci_name(ha->pdev));
1897 pio = 0;
1898 }
1899 } else {
1900 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1901 "Region #0 no a PIO resource (%s).\n",
1902 pci_name(ha->pdev));
1903 pio = 0;
1904 }
1905 ha->pio_address = pio;
1906 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1907 "PIO address=%llu.\n",
1908 (unsigned long long)ha->pio_address);
1909
1910skip_pio:
1911 /* Use MMIO operations for all accesses. */
1912 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1913 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1914 "Region #1 not an MMIO resource (%s), aborting.\n",
1915 pci_name(ha->pdev));
1916 goto iospace_error_exit;
1917 }
1918 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1919 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1920 "Invalid PCI mem region size (%s), aborting.\n",
1921 pci_name(ha->pdev));
1922 goto iospace_error_exit;
1923 }
1924
1925 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1926 if (!ha->iobase) {
1927 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1928 "Cannot remap MMIO (%s), aborting.\n",
1929 pci_name(ha->pdev));
1930 goto iospace_error_exit;
1931 }
1932
1933 /* Determine queue resources */
1934 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1935 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1936 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1937 goto mqiobase_exit;
1938
1939 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1940 pci_resource_len(ha->pdev, 3));
1941 if (ha->mqiobase) {
1942 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1943 "MQIO Base=%p.\n", ha->mqiobase);
1944 /* Read MSIX vector size of the board */
1945 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1946 ha->msix_count = msix + 1;
706f457d 1947 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1948 /* MB interrupt uses 1 vector */
1949 ha->max_req_queues = ha->msix_count - 1;
1950 ha->max_rsp_queues = ha->max_req_queues;
1951 /* Queue pairs is the max value minus the base queue pair */
1952 ha->max_qpairs = ha->max_rsp_queues - 1;
1953 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1954 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1955
706f457d 1956 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1957 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1958 } else
1959 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1960 "BAR 3 not enabled.\n");
1961
1962mqiobase_exit:
706f457d 1963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1964 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1965 return (0);
1966
1967iospace_error_exit:
1968 return (-ENOMEM);
1969}
1970
1971
6246b8a1
GM		 1972static int
1973qla83xx_iospace_config(struct qla_hw_data *ha)
1974{
1975 uint16_t msix;
6246b8a1
GM		 1976
1977 if (pci_request_selected_regions(ha->pdev, ha->bars,
1978 QLA2XXX_DRIVER_NAME)) {
1979 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1980 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1981 pci_name(ha->pdev));
1982
1983 goto iospace_error_exit;
1984 }
1985
1986 /* Use MMIO operations for all accesses. */
1987 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1988 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1989 "Invalid pci I/O region size (%s).\n",
1990 pci_name(ha->pdev));
1991 goto iospace_error_exit;
1992 }
1993 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1994 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1995 "Invalid PCI mem region size (%s), aborting\n",
1996 pci_name(ha->pdev));
1997 goto iospace_error_exit;
1998 }
1999
2000 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2001 if (!ha->iobase) {
2002 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2003 "Cannot remap MMIO (%s), aborting.\n",
2004 pci_name(ha->pdev));
2005 goto iospace_error_exit;
2006 }
2007
2008 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2009 /* 83XX 26XX always use MQ type access for queues
2010 * - mbar 2, a.k.a region 4 */
2011 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2012 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2013 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2014 pci_resource_len(ha->pdev, 4));
2015
2016 if (!ha->mqiobase) {
2017 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2018 "BAR2/region4 not enabled\n");
2019 goto mqiobase_exit;
2020 }
2021
2022 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2023 pci_resource_len(ha->pdev, 2));
2024 if (ha->msixbase) {
2025 /* Read MSIX vector size of the board */
2026 pci_read_config_word(ha->pdev,
2027 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2028 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2029 /*
2030 * By default, driver uses at least two msix vectors
2031 * (default & rspq)
2032 */
d7459527
MH		 2033 if (ql2xmqsupport) {
2034 /* MB interrupt uses 1 vector */
2035 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2036
2037 /* ATIOQ needs 1 vector. That's 1 less QPair */
2038 if (QLA_TGT_MODE_ENABLED())
2039 ha->max_req_queues--;
2040
d0d2c68b
MH		 2041 ha->max_rsp_queues = ha->max_req_queues;
2042
d7459527
MH		 2043 /* Queue pairs is the max value minus
2044 * the base queue pair */
2045 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2046 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2047 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2048 }
2049 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2050 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2051 } else
2052 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2053 "BAR 1 not enabled.\n");
2054
2055mqiobase_exit:
6246b8a1 2056 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2057 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2058 return 0;
2059
2060iospace_error_exit:
2061 return -ENOMEM;
2062}
2063
fd34f556
AV		 2064static struct isp_operations qla2100_isp_ops = {
2065 .pci_config = qla2100_pci_config,
2066 .reset_chip = qla2x00_reset_chip,
2067 .chip_diag = qla2x00_chip_diag,
2068 .config_rings = qla2x00_config_rings,
2069 .reset_adapter = qla2x00_reset_adapter,
2070 .nvram_config = qla2x00_nvram_config,
2071 .update_fw_options = qla2x00_update_fw_options,
2072 .load_risc = qla2x00_load_risc,
2073 .pci_info_str = qla2x00_pci_info_str,
2074 .fw_version_str = qla2x00_fw_version_str,
2075 .intr_handler = qla2100_intr_handler,
2076 .enable_intrs = qla2x00_enable_intrs,
2077 .disable_intrs = qla2x00_disable_intrs,
2078 .abort_command = qla2x00_abort_command,
523ec773
AV		 2079 .target_reset = qla2x00_abort_target,
2080 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2081 .fabric_login = qla2x00_login_fabric,
2082 .fabric_logout = qla2x00_fabric_logout,
2083 .calc_req_entries = qla2x00_calc_iocbs_32,
2084 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2085 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2086 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2087 .read_nvram = qla2x00_read_nvram_data,
2088 .write_nvram = qla2x00_write_nvram_data,
2089 .fw_dump = qla2100_fw_dump,
2090 .beacon_on = NULL,
2091 .beacon_off = NULL,
2092 .beacon_blink = NULL,
2093 .read_optrom = qla2x00_read_optrom_data,
2094 .write_optrom = qla2x00_write_optrom_data,
2095 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2096 .start_scsi = qla2x00_start_scsi,
d7459527 2097 .start_scsi_mq = NULL,
a9083016 2098 .abort_isp = qla2x00_abort_isp,
706f457d 2099 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2100 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2101};
2102
2103static struct isp_operations qla2300_isp_ops = {
2104 .pci_config = qla2300_pci_config,
2105 .reset_chip = qla2x00_reset_chip,
2106 .chip_diag = qla2x00_chip_diag,
2107 .config_rings = qla2x00_config_rings,
2108 .reset_adapter = qla2x00_reset_adapter,
2109 .nvram_config = qla2x00_nvram_config,
2110 .update_fw_options = qla2x00_update_fw_options,
2111 .load_risc = qla2x00_load_risc,
2112 .pci_info_str = qla2x00_pci_info_str,
2113 .fw_version_str = qla2x00_fw_version_str,
2114 .intr_handler = qla2300_intr_handler,
2115 .enable_intrs = qla2x00_enable_intrs,
2116 .disable_intrs = qla2x00_disable_intrs,
2117 .abort_command = qla2x00_abort_command,
523ec773
AV		 2118 .target_reset = qla2x00_abort_target,
2119 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2120 .fabric_login = qla2x00_login_fabric,
2121 .fabric_logout = qla2x00_fabric_logout,
2122 .calc_req_entries = qla2x00_calc_iocbs_32,
2123 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2124 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2125 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2126 .read_nvram = qla2x00_read_nvram_data,
2127 .write_nvram = qla2x00_write_nvram_data,
2128 .fw_dump = qla2300_fw_dump,
2129 .beacon_on = qla2x00_beacon_on,
2130 .beacon_off = qla2x00_beacon_off,
2131 .beacon_blink = qla2x00_beacon_blink,
2132 .read_optrom = qla2x00_read_optrom_data,
2133 .write_optrom = qla2x00_write_optrom_data,
2134 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2135 .start_scsi = qla2x00_start_scsi,
d7459527 2136 .start_scsi_mq = NULL,
a9083016 2137 .abort_isp = qla2x00_abort_isp,
7ec0effd 2138 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2139 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2140};
2141
2142static struct isp_operations qla24xx_isp_ops = {
2143 .pci_config = qla24xx_pci_config,
2144 .reset_chip = qla24xx_reset_chip,
2145 .chip_diag = qla24xx_chip_diag,
2146 .config_rings = qla24xx_config_rings,
2147 .reset_adapter = qla24xx_reset_adapter,
2148 .nvram_config = qla24xx_nvram_config,
2149 .update_fw_options = qla24xx_update_fw_options,
2150 .load_risc = qla24xx_load_risc,
2151 .pci_info_str = qla24xx_pci_info_str,
2152 .fw_version_str = qla24xx_fw_version_str,
2153 .intr_handler = qla24xx_intr_handler,
2154 .enable_intrs = qla24xx_enable_intrs,
2155 .disable_intrs = qla24xx_disable_intrs,
2156 .abort_command = qla24xx_abort_command,
523ec773
AV		 2157 .target_reset = qla24xx_abort_target,
2158 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2159 .fabric_login = qla24xx_login_fabric,
2160 .fabric_logout = qla24xx_fabric_logout,
2161 .calc_req_entries = NULL,
2162 .build_iocbs = NULL,
2163 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2164 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2165 .read_nvram = qla24xx_read_nvram_data,
2166 .write_nvram = qla24xx_write_nvram_data,
2167 .fw_dump = qla24xx_fw_dump,
2168 .beacon_on = qla24xx_beacon_on,
2169 .beacon_off = qla24xx_beacon_off,
2170 .beacon_blink = qla24xx_beacon_blink,
2171 .read_optrom = qla24xx_read_optrom_data,
2172 .write_optrom = qla24xx_write_optrom_data,
2173 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2174 .start_scsi = qla24xx_start_scsi,
d7459527 2175 .start_scsi_mq = NULL,
a9083016 2176 .abort_isp = qla2x00_abort_isp,
7ec0effd 2177 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2178 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2179};
2180
c3a2f0df
AV		 2181static struct isp_operations qla25xx_isp_ops = {
2182 .pci_config = qla25xx_pci_config,
2183 .reset_chip = qla24xx_reset_chip,
2184 .chip_diag = qla24xx_chip_diag,
2185 .config_rings = qla24xx_config_rings,
2186 .reset_adapter = qla24xx_reset_adapter,
2187 .nvram_config = qla24xx_nvram_config,
2188 .update_fw_options = qla24xx_update_fw_options,
2189 .load_risc = qla24xx_load_risc,
2190 .pci_info_str = qla24xx_pci_info_str,
2191 .fw_version_str = qla24xx_fw_version_str,
2192 .intr_handler = qla24xx_intr_handler,
2193 .enable_intrs = qla24xx_enable_intrs,
2194 .disable_intrs = qla24xx_disable_intrs,
2195 .abort_command = qla24xx_abort_command,
523ec773
AV		 2196 .target_reset = qla24xx_abort_target,
2197 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2198 .fabric_login = qla24xx_login_fabric,
2199 .fabric_logout = qla24xx_fabric_logout,
2200 .calc_req_entries = NULL,
2201 .build_iocbs = NULL,
2202 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2203 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2204 .read_nvram = qla25xx_read_nvram_data,
2205 .write_nvram = qla25xx_write_nvram_data,
2206 .fw_dump = qla25xx_fw_dump,
2207 .beacon_on = qla24xx_beacon_on,
2208 .beacon_off = qla24xx_beacon_off,
2209 .beacon_blink = qla24xx_beacon_blink,
338c9161 2210 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2211 .write_optrom = qla24xx_write_optrom_data,
2212 .get_flash_version = qla24xx_get_flash_version,
bad75002 2213 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2214 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2215 .abort_isp = qla2x00_abort_isp,
7ec0effd 2216 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2217 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2218};
2219
3a03eb79
AV		 2220static struct isp_operations qla81xx_isp_ops = {
2221 .pci_config = qla25xx_pci_config,
2222 .reset_chip = qla24xx_reset_chip,
2223 .chip_diag = qla24xx_chip_diag,
2224 .config_rings = qla24xx_config_rings,
2225 .reset_adapter = qla24xx_reset_adapter,
2226 .nvram_config = qla81xx_nvram_config,
2227 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2228 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2229 .pci_info_str = qla24xx_pci_info_str,
2230 .fw_version_str = qla24xx_fw_version_str,
2231 .intr_handler = qla24xx_intr_handler,
2232 .enable_intrs = qla24xx_enable_intrs,
2233 .disable_intrs = qla24xx_disable_intrs,
2234 .abort_command = qla24xx_abort_command,
2235 .target_reset = qla24xx_abort_target,
2236 .lun_reset = qla24xx_lun_reset,
2237 .fabric_login = qla24xx_login_fabric,
2238 .fabric_logout = qla24xx_fabric_logout,
2239 .calc_req_entries = NULL,
2240 .build_iocbs = NULL,
2241 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2242 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2243 .read_nvram = NULL,
2244 .write_nvram = NULL,
3a03eb79
AV		 2245 .fw_dump = qla81xx_fw_dump,
2246 .beacon_on = qla24xx_beacon_on,
2247 .beacon_off = qla24xx_beacon_off,
6246b8a1 2248 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2249 .read_optrom = qla25xx_read_optrom_data,
2250 .write_optrom = qla24xx_write_optrom_data,
2251 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2252 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2253 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2254 .abort_isp = qla2x00_abort_isp,
7ec0effd 2255 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2256 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2257};
2258
2259static struct isp_operations qla82xx_isp_ops = {
2260 .pci_config = qla82xx_pci_config,
2261 .reset_chip = qla82xx_reset_chip,
2262 .chip_diag = qla24xx_chip_diag,
2263 .config_rings = qla82xx_config_rings,
2264 .reset_adapter = qla24xx_reset_adapter,
2265 .nvram_config = qla81xx_nvram_config,
2266 .update_fw_options = qla24xx_update_fw_options,
2267 .load_risc = qla82xx_load_risc,
9d55ca66 2268 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2269 .fw_version_str = qla24xx_fw_version_str,
2270 .intr_handler = qla82xx_intr_handler,
2271 .enable_intrs = qla82xx_enable_intrs,
2272 .disable_intrs = qla82xx_disable_intrs,
2273 .abort_command = qla24xx_abort_command,
2274 .target_reset = qla24xx_abort_target,
2275 .lun_reset = qla24xx_lun_reset,
2276 .fabric_login = qla24xx_login_fabric,
2277 .fabric_logout = qla24xx_fabric_logout,
2278 .calc_req_entries = NULL,
2279 .build_iocbs = NULL,
2280 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2281 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2282 .read_nvram = qla24xx_read_nvram_data,
2283 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2284 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2285 .beacon_on = qla82xx_beacon_on,
2286 .beacon_off = qla82xx_beacon_off,
2287 .beacon_blink = NULL,
a9083016
GM		 2288 .read_optrom = qla82xx_read_optrom_data,
2289 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2290 .get_flash_version = qla82xx_get_flash_version,
a9083016 2291 .start_scsi = qla82xx_start_scsi,
d7459527 2292 .start_scsi_mq = NULL,
a9083016 2293 .abort_isp = qla82xx_abort_isp,
706f457d 2294 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2295 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2296};
2297
7ec0effd
AD		 2298static struct isp_operations qla8044_isp_ops = {
2299 .pci_config = qla82xx_pci_config,
2300 .reset_chip = qla82xx_reset_chip,
2301 .chip_diag = qla24xx_chip_diag,
2302 .config_rings = qla82xx_config_rings,
2303 .reset_adapter = qla24xx_reset_adapter,
2304 .nvram_config = qla81xx_nvram_config,
2305 .update_fw_options = qla24xx_update_fw_options,
2306 .load_risc = qla82xx_load_risc,
2307 .pci_info_str = qla24xx_pci_info_str,
2308 .fw_version_str = qla24xx_fw_version_str,
2309 .intr_handler = qla8044_intr_handler,
2310 .enable_intrs = qla82xx_enable_intrs,
2311 .disable_intrs = qla82xx_disable_intrs,
2312 .abort_command = qla24xx_abort_command,
2313 .target_reset = qla24xx_abort_target,
2314 .lun_reset = qla24xx_lun_reset,
2315 .fabric_login = qla24xx_login_fabric,
2316 .fabric_logout = qla24xx_fabric_logout,
2317 .calc_req_entries = NULL,
2318 .build_iocbs = NULL,
2319 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2320 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2321 .read_nvram = NULL,
2322 .write_nvram = NULL,
a1b23c5a 2323 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2324 .beacon_on = qla82xx_beacon_on,
2325 .beacon_off = qla82xx_beacon_off,
2326 .beacon_blink = NULL,
888e639d 2327 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2328 .write_optrom = qla8044_write_optrom_data,
2329 .get_flash_version = qla82xx_get_flash_version,
2330 .start_scsi = qla82xx_start_scsi,
d7459527 2331 .start_scsi_mq = NULL,
7ec0effd
AD		 2332 .abort_isp = qla8044_abort_isp,
2333 .iospace_config = qla82xx_iospace_config,
2334 .initialize_adapter = qla2x00_initialize_adapter,
2335};
2336
6246b8a1
GM		 2337static struct isp_operations qla83xx_isp_ops = {
2338 .pci_config = qla25xx_pci_config,
2339 .reset_chip = qla24xx_reset_chip,
2340 .chip_diag = qla24xx_chip_diag,
2341 .config_rings = qla24xx_config_rings,
2342 .reset_adapter = qla24xx_reset_adapter,
2343 .nvram_config = qla81xx_nvram_config,
2344 .update_fw_options = qla81xx_update_fw_options,
2345 .load_risc = qla81xx_load_risc,
2346 .pci_info_str = qla24xx_pci_info_str,
2347 .fw_version_str = qla24xx_fw_version_str,
2348 .intr_handler = qla24xx_intr_handler,
2349 .enable_intrs = qla24xx_enable_intrs,
2350 .disable_intrs = qla24xx_disable_intrs,
2351 .abort_command = qla24xx_abort_command,
2352 .target_reset = qla24xx_abort_target,
2353 .lun_reset = qla24xx_lun_reset,
2354 .fabric_login = qla24xx_login_fabric,
2355 .fabric_logout = qla24xx_fabric_logout,
2356 .calc_req_entries = NULL,
2357 .build_iocbs = NULL,
2358 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2359 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2360 .read_nvram = NULL,
2361 .write_nvram = NULL,
2362 .fw_dump = qla83xx_fw_dump,
2363 .beacon_on = qla24xx_beacon_on,
2364 .beacon_off = qla24xx_beacon_off,
2365 .beacon_blink = qla83xx_beacon_blink,
2366 .read_optrom = qla25xx_read_optrom_data,
2367 .write_optrom = qla24xx_write_optrom_data,
2368 .get_flash_version = qla24xx_get_flash_version,
2369 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2370 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2371 .abort_isp = qla2x00_abort_isp,
2372 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2373 .initialize_adapter = qla2x00_initialize_adapter,
2374};
2375
2376static struct isp_operations qlafx00_isp_ops = {
2377 .pci_config = qlafx00_pci_config,
2378 .reset_chip = qlafx00_soft_reset,
2379 .chip_diag = qlafx00_chip_diag,
2380 .config_rings = qlafx00_config_rings,
2381 .reset_adapter = qlafx00_soft_reset,
2382 .nvram_config = NULL,
2383 .update_fw_options = NULL,
2384 .load_risc = NULL,
2385 .pci_info_str = qlafx00_pci_info_str,
2386 .fw_version_str = qlafx00_fw_version_str,
2387 .intr_handler = qlafx00_intr_handler,
2388 .enable_intrs = qlafx00_enable_intrs,
2389 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2390 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2391 .target_reset = qlafx00_abort_target,
2392 .lun_reset = qlafx00_lun_reset,
2393 .fabric_login = NULL,
2394 .fabric_logout = NULL,
2395 .calc_req_entries = NULL,
2396 .build_iocbs = NULL,
2397 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2398 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2399 .read_nvram = qla24xx_read_nvram_data,
2400 .write_nvram = qla24xx_write_nvram_data,
2401 .fw_dump = NULL,
2402 .beacon_on = qla24xx_beacon_on,
2403 .beacon_off = qla24xx_beacon_off,
2404 .beacon_blink = NULL,
2405 .read_optrom = qla24xx_read_optrom_data,
2406 .write_optrom = qla24xx_write_optrom_data,
2407 .get_flash_version = qla24xx_get_flash_version,
2408 .start_scsi = qlafx00_start_scsi,
d7459527 2409 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2410 .abort_isp = qlafx00_abort_isp,
2411 .iospace_config = qlafx00_iospace_config,
2412 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2413};
2414
f73cb695
CD		 2415static struct isp_operations qla27xx_isp_ops = {
2416 .pci_config = qla25xx_pci_config,
2417 .reset_chip = qla24xx_reset_chip,
2418 .chip_diag = qla24xx_chip_diag,
2419 .config_rings = qla24xx_config_rings,
2420 .reset_adapter = qla24xx_reset_adapter,
2421 .nvram_config = qla81xx_nvram_config,
2422 .update_fw_options = qla81xx_update_fw_options,
2423 .load_risc = qla81xx_load_risc,
2424 .pci_info_str = qla24xx_pci_info_str,
2425 .fw_version_str = qla24xx_fw_version_str,
2426 .intr_handler = qla24xx_intr_handler,
2427 .enable_intrs = qla24xx_enable_intrs,
2428 .disable_intrs = qla24xx_disable_intrs,
2429 .abort_command = qla24xx_abort_command,
2430 .target_reset = qla24xx_abort_target,
2431 .lun_reset = qla24xx_lun_reset,
2432 .fabric_login = qla24xx_login_fabric,
2433 .fabric_logout = qla24xx_fabric_logout,
2434 .calc_req_entries = NULL,
2435 .build_iocbs = NULL,
2436 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2437 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2438 .read_nvram = NULL,
2439 .write_nvram = NULL,
2440 .fw_dump = qla27xx_fwdump,
2441 .beacon_on = qla24xx_beacon_on,
2442 .beacon_off = qla24xx_beacon_off,
2443 .beacon_blink = qla83xx_beacon_blink,
2444 .read_optrom = qla25xx_read_optrom_data,
2445 .write_optrom = qla24xx_write_optrom_data,
2446 .get_flash_version = qla24xx_get_flash_version,
2447 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2448 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2449 .abort_isp = qla2x00_abort_isp,
2450 .iospace_config = qla83xx_iospace_config,
2451 .initialize_adapter = qla2x00_initialize_adapter,
2452};
2453
ea5b6382 2454static inline void
e315cd28 2455qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2456{
2457 ha->device_type = DT_EXTENDED_IDS;
2458 switch (ha->pdev->device) {
2459 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2460 ha->isp_type |= DT_ISP2100;
ea5b6382 2461 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2462 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2463 break;
2464 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2465 ha->isp_type |= DT_ISP2200;
ea5b6382 2466 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2467 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2468 break;
2469 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2470 ha->isp_type |= DT_ISP2300;
4a59f71d 2471 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2472 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2473 break;
2474 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2475 ha->isp_type |= DT_ISP2312;
4a59f71d 2476 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2477 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2478 break;
2479 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2480 ha->isp_type |= DT_ISP2322;
4a59f71d 2481 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2482 if (ha->pdev->subsystem_vendor == 0x1028 &&
2483 ha->pdev->subsystem_device == 0x0170)
2484 ha->device_type |= DT_OEM_001;
441d1072 2485 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2486 break;
2487 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2488 ha->isp_type |= DT_ISP6312;
441d1072 2489 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2490 break;
2491 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2492 ha->isp_type |= DT_ISP6322;
441d1072 2493 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2494 break;
2495 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2496 ha->isp_type |= DT_ISP2422;
4a59f71d 2497 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2498 ha->device_type |= DT_FWI2;
c76f2c01 2499 ha->device_type |= DT_IIDMA;
441d1072 2500 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2501 break;
2502 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2503 ha->isp_type |= DT_ISP2432;
4a59f71d 2504 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2505 ha->device_type |= DT_FWI2;
c76f2c01 2506 ha->device_type |= DT_IIDMA;
441d1072 2507 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2508 break;
4d4df193 2509 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2510 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2511 ha->device_type |= DT_ZIO_SUPPORTED;
2512 ha->device_type |= DT_FWI2;
2513 ha->device_type |= DT_IIDMA;
2514 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2515 break;
044cc6c8 2516 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2517 ha->isp_type |= DT_ISP5422;
e428924c 2518 ha->device_type |= DT_FWI2;
441d1072 2519 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2520 break;
044cc6c8 2521 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2522 ha->isp_type |= DT_ISP5432;
e428924c 2523 ha->device_type |= DT_FWI2;
441d1072 2524 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2525 break;
c3a2f0df 2526 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2527 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2528 ha->device_type |= DT_ZIO_SUPPORTED;
2529 ha->device_type |= DT_FWI2;
2530 ha->device_type |= DT_IIDMA;
441d1072 2531 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2532 break;
3a03eb79 2533 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2534 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2535 ha->device_type |= DT_ZIO_SUPPORTED;
2536 ha->device_type |= DT_FWI2;
2537 ha->device_type |= DT_IIDMA;
2538 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2539 break;
a9083016 2540 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2541 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2542 ha->device_type |= DT_ZIO_SUPPORTED;
2543 ha->device_type |= DT_FWI2;
2544 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2545 /* Initialize 82XX ISP flags */
2546 qla82xx_init_flags(ha);
2547 break;
7ec0effd 2548 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2549 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2550 ha->device_type |= DT_ZIO_SUPPORTED;
2551 ha->device_type |= DT_FWI2;
2552 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2553 /* Initialize 82XX ISP flags */
2554 qla82xx_init_flags(ha);
2555 break;
6246b8a1 2556 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2557 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2558 ha->device_type |= DT_ZIO_SUPPORTED;
2559 ha->device_type |= DT_FWI2;
2560 ha->device_type |= DT_IIDMA;
2561 ha->device_type |= DT_T10_PI;
2562 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2563 break;
2564 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2565 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2566 ha->device_type |= DT_ZIO_SUPPORTED;
2567 ha->device_type |= DT_FWI2;
2568 ha->device_type |= DT_IIDMA;
2569 ha->device_type |= DT_T10_PI;
2570 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2571 break;
8ae6d9c7 2572 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2573 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2574 break;
f73cb695 2575 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2576 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2577 ha->device_type |= DT_ZIO_SUPPORTED;
2578 ha->device_type |= DT_FWI2;
2579 ha->device_type |= DT_IIDMA;
8ce3f570 2580 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2581 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2582 break;
2c5bbbb2 2583 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2584 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2585 ha->device_type |= DT_ZIO_SUPPORTED;
2586 ha->device_type |= DT_FWI2;
2587 ha->device_type |= DT_IIDMA;
8ce3f570 2588 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2589 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2590 break;
2b48992f 2591 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2592 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2593 ha->device_type |= DT_ZIO_SUPPORTED;
2594 ha->device_type |= DT_FWI2;
2595 ha->device_type |= DT_IIDMA;
8ce3f570 2596 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2598 break;
ea5b6382 2599 }
e5b68a61 2600
a9083016 2601 if (IS_QLA82XX(ha))
43a9c38b 2602 ha->port_no = ha->portnum & 1;
f73cb695 2603 else {
a9083016
GM		 2604 /* Get adapter physical port no from interrupt pin register. */
2605 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2606 if (IS_QLA27XX(ha))
2607 ha->port_no--;
2608 else
2609 ha->port_no = !(ha->port_no & 1);
2610 }
a9083016 2611
7c3df132 2612 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2613 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2614 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2615}
2616
1e99e33a
AV		 2617static void
2618qla2xxx_scan_start(struct Scsi_Host *shost)
2619{
e315cd28 2620 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2621
cbc8eb67
AV		 2622 if (vha->hw->flags.running_gold_fw)
2623 return;
2624
e315cd28
AC		 2625 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2626 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2627 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2628 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2629}
2630
2631static int
2632qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2633{
e315cd28 2634 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2635
a5dd506e
BK		 2636 if (test_bit(UNLOADING, &vha->dpc_flags))
2637 return 1;
e315cd28 2638 if (!vha->host)
1e99e33a 2639 return 1;
e315cd28 2640 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2641 return 1;
2642
e315cd28 2643 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2644}
2645
ec7193e2
QT		 2646static void qla2x00_iocb_work_fn(struct work_struct *work)
2647{
2648 struct scsi_qla_host *vha = container_of(work,
2649 struct scsi_qla_host, iocb_work);
2650 int cnt = 0;
2651
2652 while (!list_empty(&vha->work_list)) {
2653 qla2x00_do_work(vha);
2654 cnt++;
2655 if (cnt > 10)
2656 break;
2657 }
2658}
2659
1da177e4
LT		 2660/*
2661 * PCI driver interface
2662 */
6f039790 2663static int
7ee61397 2664qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2665{
a1541d5a 2666 int ret = -ENODEV;
1da177e4 2667 struct Scsi_Host *host;
e315cd28
AC		 2668 scsi_qla_host_t *base_vha = NULL;
2669 struct qla_hw_data *ha;
29856e28 2670 char pci_info[30];
7d613ac6 2671 char fw_str[30], wq_name[30];
5433383e 2672 struct scsi_host_template *sht;
642ef983 2673 int bars, mem_only = 0;
e315cd28 2674 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2675 struct req_que *req = NULL;
2676 struct rsp_que *rsp = NULL;
5601236b 2677 int i;
d7459527 2678
285d0321 2679 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2680 sht = &qla2xxx_driver_template;
5433383e 2681 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2682 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2683 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2684 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2685 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2686 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2687 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2688 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2689 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2690 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2691 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2692 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2693 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2694 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2695 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2696 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2697 mem_only = 1;
7c3df132
SK		 2698 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2699 "Mem only adapter.\n");
285d0321 2700 }
7c3df132
SK		 2701 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2702 "Bars=%d.\n", bars);
285d0321 2703
09483916
BH		 2704 if (mem_only) {
2705 if (pci_enable_device_mem(pdev))
ddff7ed4 2706 return ret;
09483916
BH		 2707 } else {
2708 if (pci_enable_device(pdev))
ddff7ed4 2709 return ret;
09483916 2710 }
285d0321 2711
0927678f
JB		 2712 /* This may fail but that's ok */
2713 pci_enable_pcie_error_reporting(pdev);
285d0321 2714
e315cd28
AC		 2715 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2716 if (!ha) {
7c3df132
SK		 2717 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2718 "Unable to allocate memory for ha.\n");
ddff7ed4 2719 goto disable_device;
1da177e4 2720 }
7c3df132
SK		 2721 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2722 "Memory allocated for ha=%p.\n", ha);
e315cd28 2723 ha->pdev = pdev;
33e79977
QT		 2724 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2725 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2726 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2727 spin_lock_init(&ha->tgt.atio_lock);
2728
1da177e4
LT		 2729
2730 /* Clear our data area */
285d0321 2731 ha->bars = bars;
09483916 2732 ha->mem_only = mem_only;
df4bf0bb 2733 spin_lock_init(&ha->hardware_lock);
339aa70e 2734 spin_lock_init(&ha->vport_slock);
a9b6f722 2735 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2736 mutex_init(&ha->optrom_mutex);
1da177e4 2737
ea5b6382
AV		 2738 /* Set ISP-type information. */
2739 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2740
2741 /* Set EEH reset type to fundamental if required by hba */
95676112 2742 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2743 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2744 pdev->needs_freset = 1;
ca79cf66 2745
cba1e47f
CD		 2746 ha->prev_topology = 0;
2747 ha->init_cb_size = sizeof(init_cb_t);
2748 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2749 ha->optrom_size = OPTROM_SIZE_2300;
2750
abbd8870 2751 /* Assign ISP specific operations. */
1da177e4 2752 if (IS_QLA2100(ha)) {
642ef983 2753 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2754 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2755 req_length = REQUEST_ENTRY_CNT_2100;
2756 rsp_length = RESPONSE_ENTRY_CNT_2100;
2757 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2758 ha->gid_list_info_size = 4;
3a03eb79
AV		 2759 ha->flash_conf_off = ~0;
2760 ha->flash_data_off = ~0;
2761 ha->nvram_conf_off = ~0;
2762 ha->nvram_data_off = ~0;
fd34f556 2763 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2764 } else if (IS_QLA2200(ha)) {
642ef983 2765 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2766 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2767 req_length = REQUEST_ENTRY_CNT_2200;
2768 rsp_length = RESPONSE_ENTRY_CNT_2100;
2769 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2770 ha->gid_list_info_size = 4;
3a03eb79
AV		 2771 ha->flash_conf_off = ~0;
2772 ha->flash_data_off = ~0;
2773 ha->nvram_conf_off = ~0;
2774 ha->nvram_data_off = ~0;
fd34f556 2775 ha->isp_ops = &qla2100_isp_ops;
fca29703 2776 } else if (IS_QLA23XX(ha)) {
642ef983 2777 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2778 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2779 req_length = REQUEST_ENTRY_CNT_2200;
2780 rsp_length = RESPONSE_ENTRY_CNT_2300;
2781 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2782 ha->gid_list_info_size = 6;
854165f4
AV		 2783 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2784 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2785 ha->flash_conf_off = ~0;
2786 ha->flash_data_off = ~0;
2787 ha->nvram_conf_off = ~0;
2788 ha->nvram_data_off = ~0;
fd34f556 2789 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2790 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2791 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2792 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2793 req_length = REQUEST_ENTRY_CNT_24XX;
2794 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2795 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2796 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2797 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2798 ha->gid_list_info_size = 8;
854165f4 2799 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2800 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2801 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2802 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2803 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2804 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2805 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2806 } else if (IS_QLA25XX(ha)) {
642ef983 2807 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2808 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2809 req_length = REQUEST_ENTRY_CNT_24XX;
2810 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2811 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2812 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2813 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2814 ha->gid_list_info_size = 8;
2815 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2816 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2817 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2818 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2819 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2820 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2821 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2822 } else if (IS_QLA81XX(ha)) {
642ef983 2823 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2824 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2825 req_length = REQUEST_ENTRY_CNT_24XX;
2826 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2827 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2828 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2829 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2830 ha->gid_list_info_size = 8;
2831 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2832 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2833 ha->isp_ops = &qla81xx_isp_ops;
2834 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2835 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2836 ha->nvram_conf_off = ~0;
2837 ha->nvram_data_off = ~0;
a9083016 2838 } else if (IS_QLA82XX(ha)) {
642ef983 2839 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2840 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2841 req_length = REQUEST_ENTRY_CNT_82XX;
2842 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2843 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2844 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2845 ha->gid_list_info_size = 8;
2846 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2847 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2848 ha->isp_ops = &qla82xx_isp_ops;
2849 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2850 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2851 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2852 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2853 } else if (IS_QLA8044(ha)) {
2854 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2855 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2856 req_length = REQUEST_ENTRY_CNT_82XX;
2857 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2858 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2859 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2860 ha->gid_list_info_size = 8;
2861 ha->optrom_size = OPTROM_SIZE_83XX;
2862 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2863 ha->isp_ops = &qla8044_isp_ops;
2864 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2865 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2866 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2867 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2868 } else if (IS_QLA83XX(ha)) {
7d613ac6 2869 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2870 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2871 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2872 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2873 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2874 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2875 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2876 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2877 ha->gid_list_info_size = 8;
2878 ha->optrom_size = OPTROM_SIZE_83XX;
2879 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2880 ha->isp_ops = &qla83xx_isp_ops;
2881 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2882 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2883 ha->nvram_conf_off = ~0;
2884 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2885 } else if (IS_QLAFX00(ha)) {
2886 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2887 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2888 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2889 req_length = REQUEST_ENTRY_CNT_FX00;
2890 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2891 ha->isp_ops = &qlafx00_isp_ops;
2892 ha->port_down_retry_count = 30; /* default value */
2893 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2894 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2895 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2896 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2897 ha->mr.host_info_resend = false;
2898 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2899 } else if (IS_QLA27XX(ha)) {
2900 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2901 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2902 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2903 req_length = REQUEST_ENTRY_CNT_83XX;
2904 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2905 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2906 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2907 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2908 ha->gid_list_info_size = 8;
2909 ha->optrom_size = OPTROM_SIZE_83XX;
2910 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2911 ha->isp_ops = &qla27xx_isp_ops;
2912 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2913 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2914 ha->nvram_conf_off = ~0;
2915 ha->nvram_data_off = ~0;
1da177e4 2916 }
6246b8a1 2917
7c3df132
SK		 2918 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2919 "mbx_count=%d, req_length=%d, "
2920 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2921 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2922 "max_fibre_devices=%d.\n",
7c3df132
SK		 2923 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2924 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2925 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2926 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2927 "isp_ops=%p, flash_conf_off=%d, "
2928 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2929 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2930 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2931
2932 /* Configure PCI I/O space */
2933 ret = ha->isp_ops->iospace_config(ha);
2934 if (ret)
0a63ad12 2935 goto iospace_config_failed;
706f457d
GM		 2936
2937 ql_log_pci(ql_log_info, pdev, 0x001d,
2938 "Found an ISP%04X irq %d iobase 0x%p.\n",
2939 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2940 mutex_init(&ha->vport_lock);
d7459527 2941 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2942 init_completion(&ha->mbx_cmd_comp);
2943 complete(&ha->mbx_cmd_comp);
2944 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2945 init_completion(&ha->dcbx_comp);
f356bef1 2946 init_completion(&ha->lb_portup_comp);
1da177e4 2947
2c3dfe3f 2948 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2949
53303c42 2950 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2951 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2952 "64 Bit addressing is %s.\n",
2953 ha->flags.enable_64bit_addressing ? "enable" :
2954 "disable");
73208dfd 2955 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2956 if (ret) {
7c3df132
SK		 2957 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2958 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2959
e315cd28
AC		 2960 goto probe_hw_failed;
2961 }
2962
73208dfd 2963 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2964 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2965 req->max_q_depth = ql2xmaxqdepth;
2966
e315cd28
AC		 2967
2968 base_vha = qla2x00_create_host(sht, ha);
2969 if (!base_vha) {
a1541d5a 2970 ret = -ENOMEM;
6e9f21f3 2971 qla2x00_mem_free(ha);
2afa19a9
AC		 2972 qla2x00_free_req_que(ha, req);
2973 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2974 goto probe_hw_failed;
1da177e4
LT		 2975 }
2976
e315cd28 2977 pci_set_drvdata(pdev, base_vha);
6b383979 2978 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2979
e315cd28 2980 host = base_vha->host;
2afa19a9 2981 base_vha->req = req;
73208dfd 2982 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2983 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2984 else
e315cd28
AC		 2985 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2986 base_vha->vp_idx;
58548cb5 2987
8ae6d9c7
GM		 2988 /* Setup fcport template structure. */
2989 ha->mr.fcport.vha = base_vha;
2990 ha->mr.fcport.port_type = FCT_UNKNOWN;
2991 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2992 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2993 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2994 ha->mr.fcport.scan_state = 1;
2995
58548cb5
GM		 2996 /* Set the SG table size based on ISP type */
2997 if (!IS_FWI2_CAPABLE(ha)) {
2998 if (IS_QLA2100(ha))
2999 host->sg_tablesize = 32;
3000 } else {
3001 if (!IS_QLA82XX(ha))
3002 host->sg_tablesize = QLA_SG_ALL;
3003 }
642ef983 3004 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3005 host->cmd_per_lun = 3;
3006 host->unique_id = host->host_no;
e02587d7 3007 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3008 host->max_cmd_len = 32;
3009 else
3010 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3011 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3012 /* Older HBAs support only 16-bit LUNs */
3013 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3014 ql2xmaxlun > 0xffff)
3015 host->max_lun = 0xffff;
3016 else
3017 host->max_lun = ql2xmaxlun;
e315cd28 3018 host->transportt = qla2xxx_transport_template;
9a069e19 3019 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3020
7c3df132
SK		 3021 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3022 "max_id=%d this_id=%d "
3023 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3024 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3025 host->this_id, host->cmd_per_lun, host->unique_id,
3026 host->max_cmd_len, host->max_channel, host->max_lun,
3027 host->transportt, sht->vendor_id);
3028
d7459527
MH		 3029 /* Set up the irqs */
3030 ret = qla2x00_request_irqs(ha, rsp);
3031 if (ret)
3032 goto probe_init_failed;
3033
9a347ff4
CD		 3034 /* Alloc arrays of request and response ring ptrs */
3035 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3036 ql_log(ql_log_fatal, base_vha, 0x003d,
3037 "Failed to allocate memory for queue pointers..."
3038 "aborting.\n");
3039 goto probe_init_failed;
3040 }
3041
5601236b
MH		 3042 if (ha->mqenable && shost_use_blk_mq(host)) {
3043 /* number of hardware queues supported by blk/scsi-mq*/
3044 host->nr_hw_queues = ha->max_qpairs;
3045
3046 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3047 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3048 } else
3049 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3050 "blk/scsi-mq disabled.\n");
3051
2d70c103 3052 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3053
90a86fc0
JC		 3054 pci_save_state(pdev);
3055
9a347ff4 3056 /* Assign back pointers */
2afa19a9
AC		 3057 rsp->req = req;
3058 req->rsp = rsp;
9a347ff4 3059
8ae6d9c7
GM		 3060 if (IS_QLAFX00(ha)) {
3061 ha->rsp_q_map[0] = rsp;
3062 ha->req_q_map[0] = req;
3063 set_bit(0, ha->req_qid_map);
3064 set_bit(0, ha->rsp_qid_map);
3065 }
3066
08029990
AV		 3067 /* FWI2-capable only. */
3068 req->req_q_in = &ha->iobase->isp24.req_q_in;
3069 req->req_q_out = &ha->iobase->isp24.req_q_out;
3070 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3071 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3072 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3073 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3074 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3075 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3076 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3077 }
3078
8ae6d9c7
GM		 3079 if (IS_QLAFX00(ha)) {
3080 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3081 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3082 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3083 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3084 }
3085
7ec0effd 3086 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3087 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3088 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3089 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3090 }
3091
7c3df132
SK		 3092 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3093 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3094 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3095 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3096 "req->req_q_in=%p req->req_q_out=%p "
3097 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3098 req->req_q_in, req->req_q_out,
3099 rsp->rsp_q_in, rsp->rsp_q_out);
3100 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3101 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3102 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3103 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3104 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3105 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3106
8ae6d9c7 3107 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3108 ql_log(ql_log_fatal, base_vha, 0x00d6,
3109 "Failed to initialize adapter - Adapter flags %x.\n",
3110 base_vha->device_flags);
1da177e4 3111
a9083016
GM		 3112 if (IS_QLA82XX(ha)) {
3113 qla82xx_idc_lock(ha);
3114 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3115 QLA8XXX_DEV_FAILED);
a9083016 3116 qla82xx_idc_unlock(ha);
7c3df132
SK		 3117 ql_log(ql_log_fatal, base_vha, 0x00d7,
3118 "HW State: FAILED.\n");
7ec0effd
AD		 3119 } else if (IS_QLA8044(ha)) {
3120 qla8044_idc_lock(ha);
3121 qla8044_wr_direct(base_vha,
3122 QLA8044_CRB_DEV_STATE_INDEX,
3123 QLA8XXX_DEV_FAILED);
3124 qla8044_idc_unlock(ha);
3125 ql_log(ql_log_fatal, base_vha, 0x0150,
3126 "HW State: FAILED.\n");
a9083016
GM		 3127 }
3128
a1541d5a 3129 ret = -ENODEV;
1da177e4
LT		 3130 goto probe_failed;
3131 }
3132
3b1bef64
CD		 3133 if (IS_QLAFX00(ha))
3134 host->can_queue = QLAFX00_MAX_CANQUEUE;
3135 else
3136 host->can_queue = req->num_outstanding_cmds - 10;
3137
3138 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3139 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3140 host->can_queue, base_vha->req,
3141 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3142
e326d22a
QT		 3143 if (ha->mqenable) {
3144 bool mq = false;
3145 bool startit = false;
d7459527 3146 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
e326d22a
QT		 3147
3148 if (QLA_TGT_MODE_ENABLED()) {
3149 mq = true;
3150 startit = false;
3151 }
3152
3153 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3154 shost_use_blk_mq(host)) {
3155 mq = true;
3156 startit = true;
3157 }
3158
3159 if (mq) {
3160 /* Create start of day qpairs for Block MQ */
5601236b 3161 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3162 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3163 }
3164 }
68ca949c 3165
cbc8eb67
AV		 3166 if (ha->flags.running_gold_fw)
3167 goto skip_dpc;
3168
1da177e4
LT		 3169 /*
3170 * Startup the kernel thread for this host adapter
3171 */
39a11240 3172 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3173 "%s_dpc", base_vha->host_str);
39a11240 3174 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3175 ql_log(ql_log_fatal, base_vha, 0x00ed,
3176 "Failed to start DPC thread.\n");
39a11240 3177 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3178 goto probe_failed;
3179 }
7c3df132
SK		 3180 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3181 "DPC thread started successfully.\n");
1da177e4 3182
2d70c103
NB		 3183 /*
3184 * If we're not coming up in initiator mode, we might sit for
3185 * a while without waking up the dpc thread, which leads to a
3186 * stuck process warning. So just kick the dpc once here and
3187 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3188 */
3189 qla2xxx_wake_dpc(base_vha);
3190
ec7193e2 3191 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3192 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3193
81178772
SK		 3194 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3195 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3196 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3197 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3198
3199 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3200 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3201 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3202 INIT_WORK(&ha->idc_state_handler,
3203 qla83xx_idc_state_handler_work);
3204 INIT_WORK(&ha->nic_core_unrecoverable,
3205 qla83xx_nic_core_unrecoverable_work);
3206 }
3207
cbc8eb67 3208skip_dpc:
e315cd28
AC		 3209 list_add_tail(&base_vha->list, &ha->vp_list);
3210 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3211
3212 /* Initialized the timer */
e315cd28 3213 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3214 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3215 "Started qla2x00_timer with "
3216 "interval=%d.\n", WATCH_INTERVAL);
3217 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3218 "Detected hba at address=%p.\n",
3219 ha);
d19044c3 3220
e02587d7 3221 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3222 if (ha->fw_attributes & BIT_4) {
9e522cd8 3223 int prot = 0, guard;
bad75002 3224 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3225 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3226 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3227 if (ql2xenabledif == 1)
3228 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3229 scsi_host_set_prot(host,
8cb2049c 3230 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3231 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3232 | SHOST_DIF_TYPE3_PROTECTION
3233 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3234 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3235 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3236
3237 guard = SHOST_DIX_GUARD_CRC;
3238
3239 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3240 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3241 guard |= SHOST_DIX_GUARD_IP;
3242
3243 scsi_host_set_guard(host, guard);
bad75002
AE		 3244 } else
3245 base_vha->flags.difdix_supported = 0;
3246 }
3247
a9083016
GM		 3248 ha->isp_ops->enable_intrs(ha);
3249
1fe19ee4
AB		 3250 if (IS_QLAFX00(ha)) {
3251 ret = qlafx00_fx_disc(base_vha,
3252 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3253 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3254 QLA_SG_ALL : 128;
3255 }
3256
a1541d5a
AV		 3257 ret = scsi_add_host(host, &pdev->dev);
3258 if (ret)
3259 goto probe_failed;
3260
1486400f
MR		 3261 base_vha->flags.init_done = 1;
3262 base_vha->flags.online = 1;
edaa5c74 3263 ha->prev_minidump_failed = 0;
1486400f 3264
7c3df132
SK		 3265 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3266 "Init done and hba is online.\n");
3267
726b8548
QT		 3268 if (qla_ini_mode_enabled(base_vha) ||
3269 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3270 scsi_scan_host(host);
3271 else
3272 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3273 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3274
e315cd28 3275 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3276
8ae6d9c7 3277 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3278 ret = qlafx00_fx_disc(base_vha,
3279 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3280
3281 /* Register system information */
3282 ret = qlafx00_fx_disc(base_vha,
3283 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3284 }
3285
e315cd28 3286 qla2x00_init_host_attr(base_vha);
a1541d5a 3287
e315cd28 3288 qla2x00_dfs_setup(base_vha);
df613b96 3289
03eb912a
AB		 3290 ql_log(ql_log_info, base_vha, 0x00fb,
3291 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3292 ql_log(ql_log_info, base_vha, 0x00fc,
3293 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3294 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3295 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3296 base_vha->host_no,
df57caba 3297 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3298
2d70c103
NB		 3299 qlt_add_target(ha, base_vha);
3300
6b383979 3301 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3302
3303 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3304 return -ENODEV;
3305
1da177e4
LT		 3306 return 0;
3307
6e9f21f3 3308probe_init_failed:
2afa19a9 3309 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3310 ha->req_q_map[0] = NULL;
3311 clear_bit(0, ha->req_qid_map);
2afa19a9 3312 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3313 ha->rsp_q_map[0] = NULL;
3314 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3315 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3316
1da177e4 3317probe_failed:
b9978769
AV		 3318 if (base_vha->timer_active)
3319 qla2x00_stop_timer(base_vha);
3320 base_vha->flags.online = 0;
3321 if (ha->dpc_thread) {
3322 struct task_struct *t = ha->dpc_thread;
3323
3324 ha->dpc_thread = NULL;
3325 kthread_stop(t);
3326 }
3327
e315cd28 3328 qla2x00_free_device(base_vha);
1da177e4 3329
e315cd28 3330 scsi_host_put(base_vha->host);
1da177e4 3331
e315cd28 3332probe_hw_failed:
1a2fbf18
JL		 3333 qla2x00_clear_drv_active(ha);
3334
0a63ad12 3335iospace_config_failed:
7ec0effd 3336 if (IS_P3P_TYPE(ha)) {
0a63ad12 3337 if (!ha->nx_pcibase)
f73cb695 3338 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3339 if (!ql2xdbwr)
f73cb695 3340 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3341 } else {
3342 if (ha->iobase)
3343 iounmap(ha->iobase);
8ae6d9c7
GM		 3344 if (ha->cregbase)
3345 iounmap(ha->cregbase);
a9083016 3346 }
e315cd28
AC		 3347 pci_release_selected_regions(ha->pdev, ha->bars);
3348 kfree(ha);
1da177e4 3349
ddff7ed4 3350disable_device:
e315cd28 3351 pci_disable_device(pdev);
a1541d5a 3352 return ret;
1da177e4 3353}
1da177e4 3354
e30d1756
MI		 3355static void
3356qla2x00_shutdown(struct pci_dev *pdev)
3357{
3358 scsi_qla_host_t *vha;
3359 struct qla_hw_data *ha;
3360
552f3f9a
MI		 3361 if (!atomic_read(&pdev->enable_cnt))
3362 return;
3363
e30d1756
MI		 3364 vha = pci_get_drvdata(pdev);
3365 ha = vha->hw;
3366
42479343
AB		 3367 /* Notify ISPFX00 firmware */
3368 if (IS_QLAFX00(ha))
3369 qlafx00_driver_shutdown(vha, 20);
3370
e30d1756
MI		 3371 /* Turn-off FCE trace */
3372 if (ha->flags.fce_enabled) {
3373 qla2x00_disable_fce_trace(vha, NULL, NULL);
3374 ha->flags.fce_enabled = 0;
3375 }
3376
3377 /* Turn-off EFT trace */
3378 if (ha->eft)
3379 qla2x00_disable_eft_trace(vha);
3380
3381 /* Stop currently executing firmware. */
3382 qla2x00_try_to_stop_firmware(vha);
3383
3384 /* Turn adapter off line */
3385 vha->flags.online = 0;
3386
3387 /* turn-off interrupts on the card */
3388 if (ha->interrupts_on) {
3389 vha->flags.init_done = 0;
3390 ha->isp_ops->disable_intrs(ha);
3391 }
3392
3393 qla2x00_free_irqs(vha);
3394
3395 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3396
3397 pci_disable_pcie_error_reporting(pdev);
3398 pci_disable_device(pdev);
e30d1756
MI		 3399}
3400
fe1b806f 3401/* Deletes all the virtual ports for a given ha */
4c993f76 3402static void
fe1b806f 3403qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3404{
fe1b806f 3405 scsi_qla_host_t *vha;
feafb7b1 3406 unsigned long flags;
e315cd28 3407
43ebf16d
AE		 3408 mutex_lock(&ha->vport_lock);
3409 while (ha->cur_vport_count) {
43ebf16d 3410 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3411
43ebf16d
AE		 3412 BUG_ON(base_vha->list.next == &ha->vp_list);
3413 /* This assumes first entry in ha->vp_list is always base vha */
3414 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3415 scsi_host_get(vha->host);
feafb7b1 3416
43ebf16d
AE		 3417 spin_unlock_irqrestore(&ha->vport_slock, flags);
3418 mutex_unlock(&ha->vport_lock);
3419
3420 fc_vport_terminate(vha->fc_vport);
3421 scsi_host_put(vha->host);
feafb7b1 3422
43ebf16d 3423 mutex_lock(&ha->vport_lock);
e315cd28 3424 }
43ebf16d 3425 mutex_unlock(&ha->vport_lock);
fe1b806f 3426}
1da177e4 3427
fe1b806f
CD		 3428/* Stops all deferred work threads */
3429static void
3430qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3431{
7d613ac6
SV		 3432 /* Cancel all work and destroy DPC workqueues */
3433 if (ha->dpc_lp_wq) {
3434 cancel_work_sync(&ha->idc_aen);
3435 destroy_workqueue(ha->dpc_lp_wq);
3436 ha->dpc_lp_wq = NULL;
3437 }
3438
3439 if (ha->dpc_hp_wq) {
3440 cancel_work_sync(&ha->nic_core_reset);
3441 cancel_work_sync(&ha->idc_state_handler);
3442 cancel_work_sync(&ha->nic_core_unrecoverable);
3443 destroy_workqueue(ha->dpc_hp_wq);
3444 ha->dpc_hp_wq = NULL;
3445 }
3446
b9978769
AV		 3447 /* Kill the kernel thread for this host */
3448 if (ha->dpc_thread) {
3449 struct task_struct *t = ha->dpc_thread;
3450
3451 /*
3452 * qla2xxx_wake_dpc checks for ->dpc_thread
3453 * so we need to zero it out.
3454 */
3455 ha->dpc_thread = NULL;
3456 kthread_stop(t);
3457 }
fe1b806f 3458}
1da177e4 3459
fe1b806f
CD		 3460static void
3461qla2x00_unmap_iobases(struct qla_hw_data *ha)
3462{
a9083016 3463 if (IS_QLA82XX(ha)) {
b963752f 3464
f73cb695 3465 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3466 if (!ql2xdbwr)
f73cb695 3467 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3468 } else {
3469 if (ha->iobase)
3470 iounmap(ha->iobase);
1da177e4 3471
8ae6d9c7
GM		 3472 if (ha->cregbase)
3473 iounmap(ha->cregbase);
3474
a9083016
GM		 3475 if (ha->mqiobase)
3476 iounmap(ha->mqiobase);
6246b8a1 3477
f73cb695 3478 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3479 iounmap(ha->msixbase);
a9083016 3480 }
fe1b806f
CD		 3481}
3482
3483static void
db7157d4 3484qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3485{
fe1b806f
CD		 3486 if (IS_QLA8044(ha)) {
3487 qla8044_idc_lock(ha);
c41afc9a 3488 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3489 qla8044_idc_unlock(ha);
3490 } else if (IS_QLA82XX(ha)) {
3491 qla82xx_idc_lock(ha);
3492 qla82xx_clear_drv_active(ha);
3493 qla82xx_idc_unlock(ha);
3494 }
3495}
3496
3497static void
3498qla2x00_remove_one(struct pci_dev *pdev)
3499{
3500 scsi_qla_host_t *base_vha;
3501 struct qla_hw_data *ha;
3502
beb9e315
JL		 3503 base_vha = pci_get_drvdata(pdev);
3504 ha = base_vha->hw;
3505
3506 /* Indicate device removal to prevent future board_disable and wait
3507 * until any pending board_disable has completed. */
3508 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3509 cancel_work_sync(&ha->board_disable);
3510
fe1b806f 3511 /*
beb9e315
JL		 3512 * If the PCI device is disabled then there was a PCI-disconnect and
3513 * qla2x00_disable_board_on_pci_error has taken care of most of the
3514 * resources.
fe1b806f 3515 */
beb9e315 3516 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3517 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3518 base_vha->gnl.l, base_vha->gnl.ldma);
3519
beb9e315
JL		 3520 scsi_host_put(base_vha->host);
3521 kfree(ha);
3522 pci_set_drvdata(pdev, NULL);
fe1b806f 3523 return;
beb9e315 3524 }
638a1a01
SC		 3525 qla2x00_wait_for_hba_ready(base_vha);
3526
726b8548
QT		 3527 /*
3528 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3529 * where it was set first.
3530 */
3531 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3532 return;
3533
fe1b806f 3534 set_bit(UNLOADING, &base_vha->dpc_flags);
726b8548
QT		 3535 dma_free_coherent(&ha->pdev->dev,
3536 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3537
3538 if (IS_QLAFX00(ha))
3539 qlafx00_driver_shutdown(base_vha, 20);
3540
3541 qla2x00_delete_all_vps(ha, base_vha);
3542
3543 if (IS_QLA8031(ha)) {
3544 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3545 "Clearing fcoe driver presence.\n");
3546 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3547 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3548 "Error while clearing DRV-Presence.\n");
3549 }
3550
3551 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3552
3553 qla2x00_dfs_remove(base_vha);
3554
3555 qla84xx_put_chip(base_vha);
3556
2d5a4c34
HM		 3557 /* Laser should be disabled only for ISP2031 */
3558 if (IS_QLA2031(ha))
3559 qla83xx_disable_laser(base_vha);
3560
fe1b806f
CD		 3561 /* Disable timer */
3562 if (base_vha->timer_active)
3563 qla2x00_stop_timer(base_vha);
3564
3565 base_vha->flags.online = 0;
3566
b0d6cabd
HM		 3567 /* free DMA memory */
3568 if (ha->exlogin_buf)
3569 qla2x00_free_exlogin_buffer(ha);
3570
2f56a7f1
HM		 3571 /* free DMA memory */
3572 if (ha->exchoffld_buf)
3573 qla2x00_free_exchoffld_buffer(ha);
3574
fe1b806f
CD		 3575 qla2x00_destroy_deferred_work(ha);
3576
3577 qlt_remove_target(ha, base_vha);
3578
3579 qla2x00_free_sysfs_attr(base_vha, true);
3580
3581 fc_remove_host(base_vha->host);
482c9dc7 3582 qlt_remove_target_resources(ha);
fe1b806f
CD		 3583
3584 scsi_remove_host(base_vha->host);
3585
3586 qla2x00_free_device(base_vha);
3587
db7157d4 3588 qla2x00_clear_drv_active(ha);
fe1b806f 3589
d2749ffa
AE		 3590 scsi_host_put(base_vha->host);
3591
fe1b806f 3592 qla2x00_unmap_iobases(ha);
73208dfd 3593
e315cd28
AC		 3594 pci_release_selected_regions(ha->pdev, ha->bars);
3595 kfree(ha);
1da177e4 3596
90a86fc0
JC		 3597 pci_disable_pcie_error_reporting(pdev);
3598
665db93b 3599 pci_disable_device(pdev);
1da177e4 3600}
1da177e4
LT		 3601
3602static void
e315cd28 3603qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3604{
e315cd28 3605 struct qla_hw_data *ha = vha->hw;
1da177e4 3606
85880801
AV		 3607 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3608
3609 /* Disable timer */
3610 if (vha->timer_active)
3611 qla2x00_stop_timer(vha);
3612
2afa19a9 3613 qla25xx_delete_queues(vha);
fe1b806f 3614
df613b96 3615 if (ha->flags.fce_enabled)
e315cd28 3616 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3617
a7a167bf 3618 if (ha->eft)
e315cd28 3619 qla2x00_disable_eft_trace(vha);
a7a167bf 3620
f6ef3b18 3621 /* Stop currently executing firmware. */
e315cd28 3622 qla2x00_try_to_stop_firmware(vha);
1da177e4 3623
85880801
AV		 3624 vha->flags.online = 0;
3625
f6ef3b18 3626 /* turn-off interrupts on the card */
a9083016
GM		 3627 if (ha->interrupts_on) {
3628 vha->flags.init_done = 0;
fd34f556 3629 ha->isp_ops->disable_intrs(ha);
a9083016 3630 }
f6ef3b18 3631
093df737
QT		 3632 qla2x00_free_fcports(vha);
3633
e315cd28 3634 qla2x00_free_irqs(vha);
1da177e4 3635
093df737
QT		 3636 /* Flush the work queue and remove it */
3637 if (ha->wq) {
3638 flush_workqueue(ha->wq);
3639 destroy_workqueue(ha->wq);
3640 ha->wq = NULL;
3641 }
3642
8867048b 3643
e315cd28 3644 qla2x00_mem_free(ha);
73208dfd 3645
08de2844
GM		 3646 qla82xx_md_free(vha);
3647
73208dfd 3648 qla2x00_free_queues(ha);
1da177e4
LT		 3649}
3650
8867048b
CD		 3651void qla2x00_free_fcports(struct scsi_qla_host *vha)
3652{
3653 fc_port_t *fcport, *tfcport;
3654
3655 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3656 list_del(&fcport->list);
5f16b331 3657 qla2x00_clear_loop_id(fcport);
8867048b 3658 kfree(fcport);
8867048b
CD		 3659 }
3660}
3661
d97994dc 3662static inline void
e315cd28 3663qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3664 int defer)
3665{
d97994dc 3666 struct fc_rport *rport;
67becc00 3667 scsi_qla_host_t *base_vha;
044d78e1 3668 unsigned long flags;
d97994dc
AV		 3669
3670 if (!fcport->rport)
3671 return;
3672
3673 rport = fcport->rport;
3674 if (defer) {
67becc00 3675 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3676 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3677 fcport->drport = rport;
044d78e1 3678 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3679 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3680 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3681 qla2xxx_wake_dpc(base_vha);
2d70c103 3682 } else {
df673274 3683 int now;
726b8548 3684 if (rport) {
83548fe2
QT		 3685 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3686 "%s %8phN. rport %p roles %x\n",
3687 __func__, fcport->port_name, rport,
3688 rport->roles);
d20ed91b 3689 fc_remote_port_delete(rport);
726b8548 3690 }
df673274 3691 qlt_do_generation_tick(vha, &now);
2d70c103 3692 }
d97994dc
AV		 3693}
3694
1da177e4
LT		 3695/*
3696 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3697 *
3698 * Input: ha = adapter block pointer. fcport = port structure pointer.
3699 *
3700 * Return: None.
3701 *
3702 * Context:
3703 */
e315cd28 3704void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3705 int do_login, int defer)
1da177e4 3706{
8ae6d9c7
GM		 3707 if (IS_QLAFX00(vha->hw)) {
3708 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3709 qla2x00_schedule_rport_del(vha, fcport, defer);
3710 return;
3711 }
3712
2c3dfe3f 3713 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3714 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3715 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3716 qla2x00_schedule_rport_del(vha, fcport, defer);
3717 }
fa2a1ce5 3718 /*
1da177e4
LT		 3719 * We may need to retry the login, so don't change the state of the
3720 * port but do the retries.
3721 */
3722 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3723 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3724
3725 if (!do_login)
3726 return;
3727
a1d0285e
AE		 3728 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3729
1da177e4 3730 if (fcport->login_retry == 0) {
e315cd28 3731 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3732
83548fe2 3733 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3734 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3735 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3736 }
3737}
3738
3739/*
3740 * qla2x00_mark_all_devices_lost
3741 * Updates fcport state when device goes offline.
3742 *
3743 * Input:
3744 * ha = adapter block pointer.
3745 * fcport = port structure pointer.
3746 *
3747 * Return:
3748 * None.
3749 *
3750 * Context:
3751 */
3752void
e315cd28 3753qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3754{
3755 fc_port_t *fcport;
3756
83548fe2
QT		 3757 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3758 "Mark all dev lost\n");
726b8548 3759
e315cd28 3760 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3761 fcport->scan_state = 0;
3762 qlt_schedule_sess_for_deletion_lock(fcport);
3763
c6d39e23 3764 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3765 continue;
0d6e61bc 3766
1da177e4
LT		 3767 /*
3768 * No point in marking the device as lost, if the device is
3769 * already DEAD.
3770 */
3771 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3772 continue;
e315cd28 3773 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3774 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3775 if (defer)
3776 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3777 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3778 qla2x00_schedule_rport_del(vha, fcport, defer);
3779 }
1da177e4
LT		 3780 }
3781}
3782
3783/*
3784* qla2x00_mem_alloc
3785* Allocates adapter memory.
3786*
3787* Returns:
3788* 0 = success.
e8711085 3789* !0 = failure.
1da177e4 3790*/
e8711085 3791static int
73208dfd
AC		 3792qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3793 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3794{
3795 char name[16];
1da177e4 3796
e8711085 3797 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3798 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3799 if (!ha->init_cb)
e315cd28 3800 goto fail;
e8711085 3801
2d70c103
NB		 3802 if (qlt_mem_alloc(ha) < 0)
3803 goto fail_free_init_cb;
3804
642ef983
CD		 3805 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3806 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3807 if (!ha->gid_list)
2d70c103 3808 goto fail_free_tgt_mem;
1da177e4 3809
e8711085
AV		 3810 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3811 if (!ha->srb_mempool)
e315cd28 3812 goto fail_free_gid_list;
e8711085 3813
7ec0effd 3814 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3815 /* Allocate cache for CT6 Ctx. */
3816 if (!ctx_cachep) {
3817 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3818 sizeof(struct ct6_dsd), 0,
3819 SLAB_HWCACHE_ALIGN, NULL);
3820 if (!ctx_cachep)
fc1ffd6c 3821 goto fail_free_srb_mempool;
a9083016
GM		 3822 }
3823 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3824 ctx_cachep);
3825 if (!ha->ctx_mempool)
3826 goto fail_free_srb_mempool;
7c3df132
SK		 3827 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3828 "ctx_cachep=%p ctx_mempool=%p.\n",
3829 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3830 }
3831
e8711085
AV		 3832 /* Get memory for cached NVRAM */
3833 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3834 if (!ha->nvram)
a9083016 3835 goto fail_free_ctx_mempool;
e8711085 3836
e315cd28
AC		 3837 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3838 ha->pdev->device);
3839 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3840 DMA_POOL_SIZE, 8, 0);
3841 if (!ha->s_dma_pool)
3842 goto fail_free_nvram;
3843
7c3df132
SK		 3844 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3845 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3846 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3847
7ec0effd 3848 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3849 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3850 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3851 if (!ha->dl_dma_pool) {
7c3df132
SK		 3852 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3853 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3854 goto fail_s_dma_pool;
3855 }
3856
3857 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3858 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3859 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3860 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3861 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3862 goto fail_dl_dma_pool;
3863 }
7c3df132
SK		 3864 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3865 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3866 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3867 }
3868
e8711085
AV		 3869 /* Allocate memory for SNS commands */
3870 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3871 /* Get consistent memory allocated for SNS commands */
e8711085 3872 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3873 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3874 if (!ha->sns_cmd)
e315cd28 3875 goto fail_dma_pool;
7c3df132 3876 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3877 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3878 } else {
e315cd28 3879 /* Get consistent memory allocated for MS IOCB */
e8711085 3880 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3881 &ha->ms_iocb_dma);
e8711085 3882 if (!ha->ms_iocb)
e315cd28
AC		 3883 goto fail_dma_pool;
3884 /* Get consistent memory allocated for CT SNS commands */
e8711085 3885 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3886 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3887 if (!ha->ct_sns)
3888 goto fail_free_ms_iocb;
7c3df132
SK		 3889 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3890 "ms_iocb=%p ct_sns=%p.\n",
3891 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3892 }
3893
e315cd28 3894 /* Allocate memory for request ring */
73208dfd
AC		 3895 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3896 if (!*req) {
7c3df132
SK		 3897 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3898 "Failed to allocate memory for req.\n");
e315cd28
AC		 3899 goto fail_req;
3900 }
73208dfd
AC		 3901 (*req)->length = req_len;
3902 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3903 ((*req)->length + 1) * sizeof(request_t),
3904 &(*req)->dma, GFP_KERNEL);
3905 if (!(*req)->ring) {
7c3df132
SK		 3906 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3907 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3908 goto fail_req_ring;
3909 }
3910 /* Allocate memory for response ring */
73208dfd
AC		 3911 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3912 if (!*rsp) {
7c3df132
SK		 3913 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3914 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3915 goto fail_rsp;
3916 }
73208dfd
AC		 3917 (*rsp)->hw = ha;
3918 (*rsp)->length = rsp_len;
3919 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3920 ((*rsp)->length + 1) * sizeof(response_t),
3921 &(*rsp)->dma, GFP_KERNEL);
3922 if (!(*rsp)->ring) {
7c3df132
SK		 3923 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3924 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3925 goto fail_rsp_ring;
3926 }
73208dfd
AC		 3927 (*req)->rsp = *rsp;
3928 (*rsp)->req = *req;
7c3df132
SK		 3929 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3930 "req=%p req->length=%d req->ring=%p rsp=%p "
3931 "rsp->length=%d rsp->ring=%p.\n",
3932 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3933 (*rsp)->ring);
73208dfd
AC		 3934 /* Allocate memory for NVRAM data for vports */
3935 if (ha->nvram_npiv_size) {
3936 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3937 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3938 if (!ha->npiv_info) {
7c3df132
SK		 3939 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3940 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3941 goto fail_npiv_info;
3942 }
3943 } else
3944 ha->npiv_info = NULL;
e8711085 3945
b64b0e8f 3946 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3947 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3948 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3949 &ha->ex_init_cb_dma);
3950 if (!ha->ex_init_cb)
3951 goto fail_ex_init_cb;
7c3df132
SK		 3952 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3953 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3954 }
3955
a9083016
GM		 3956 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3957
5ff1d584
AV		 3958 /* Get consistent memory allocated for Async Port-Database. */
3959 if (!IS_FWI2_CAPABLE(ha)) {
3960 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3961 &ha->async_pd_dma);
3962 if (!ha->async_pd)
3963 goto fail_async_pd;
7c3df132
SK		 3964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3965 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3966 }
3967
e315cd28 3968 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3969
3970 /* Allocate memory for our loop_id bitmap */
3971 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3972 GFP_KERNEL);
3973 if (!ha->loop_id_map)
fc1ffd6c 3974 goto fail_loop_id_map;
5f16b331
CD		 3975 else {
3976 qla2x00_set_reserved_loop_ids(ha);
3977 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3978 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3979 }
3980
b2a72ec3 3981 return 0;
e315cd28 3982
fc1ffd6c
QT		 3983fail_loop_id_map:
3984 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3985fail_async_pd:
3986 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3987fail_ex_init_cb:
3988 kfree(ha->npiv_info);
73208dfd
AC		 3989fail_npiv_info:
3990 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3991 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3992 (*rsp)->ring = NULL;
3993 (*rsp)->dma = 0;
e315cd28 3994fail_rsp_ring:
73208dfd 3995 kfree(*rsp);
e315cd28 3996fail_rsp:
73208dfd
AC		 3997 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3998 sizeof(request_t), (*req)->ring, (*req)->dma);
3999 (*req)->ring = NULL;
4000 (*req)->dma = 0;
e315cd28 4001fail_req_ring:
73208dfd 4002 kfree(*req);
e315cd28
AC		 4003fail_req:
4004 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4005 ha->ct_sns, ha->ct_sns_dma);
4006 ha->ct_sns = NULL;
4007 ha->ct_sns_dma = 0;
e8711085
AV		 4008fail_free_ms_iocb:
4009 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4010 ha->ms_iocb = NULL;
4011 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4012
4013 if (ha->sns_cmd)
4014 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4015 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4016fail_dma_pool:
bad75002 4017 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4018 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4019 ha->fcp_cmnd_dma_pool = NULL;
4020 }
4021fail_dl_dma_pool:
bad75002 4022 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4023 dma_pool_destroy(ha->dl_dma_pool);
4024 ha->dl_dma_pool = NULL;
4025 }
4026fail_s_dma_pool:
e315cd28
AC		 4027 dma_pool_destroy(ha->s_dma_pool);
4028 ha->s_dma_pool = NULL;
e8711085
AV		 4029fail_free_nvram:
4030 kfree(ha->nvram);
4031 ha->nvram = NULL;
a9083016 4032fail_free_ctx_mempool:
fc1ffd6c
QT		 4033 if (ha->ctx_mempool)
4034 mempool_destroy(ha->ctx_mempool);
a9083016 4035 ha->ctx_mempool = NULL;
e8711085 4036fail_free_srb_mempool:
fc1ffd6c
QT		 4037 if (ha->srb_mempool)
4038 mempool_destroy(ha->srb_mempool);
e8711085 4039 ha->srb_mempool = NULL;
e8711085 4040fail_free_gid_list:
642ef983
CD		 4041 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4042 ha->gid_list,
e315cd28 4043 ha->gid_list_dma);
e8711085
AV		 4044 ha->gid_list = NULL;
4045 ha->gid_list_dma = 0;
2d70c103
NB		 4046fail_free_tgt_mem:
4047 qlt_mem_free(ha);
e315cd28
AC		 4048fail_free_init_cb:
4049 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4050 ha->init_cb_dma);
4051 ha->init_cb = NULL;
4052 ha->init_cb_dma = 0;
e8711085 4053fail:
7c3df132
SK		 4054 ql_log(ql_log_fatal, NULL, 0x0030,
4055 "Memory allocation failure.\n");
e8711085 4056 return -ENOMEM;
1da177e4
LT		 4057}
4058
b0d6cabd
HM		 4059int
4060qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4061{
4062 int rval;
4063 uint16_t size, max_cnt, temp;
4064 struct qla_hw_data *ha = vha->hw;
4065
4066 /* Return if we don't need to alloacate any extended logins */
4067 if (!ql2xexlogins)
4068 return QLA_SUCCESS;
4069
99e1b683
QT		 4070 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4071 return QLA_SUCCESS;
4072
b0d6cabd
HM		 4073 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4074 max_cnt = 0;
4075 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4076 if (rval != QLA_SUCCESS) {
4077 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4078 "Failed to get exlogin status.\n");
4079 return rval;
4080 }
4081
4082 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4083 temp *= size;
4084
4085 if (temp != ha->exlogin_size) {
4086 qla2x00_free_exlogin_buffer(ha);
4087 ha->exlogin_size = temp;
4088
4089 ql_log(ql_log_info, vha, 0xd024,
4090 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4091 max_cnt, size, temp);
4092
4093 ql_log(ql_log_info, vha, 0xd025,
4094 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4095
4096 /* Get consistent memory for extended logins */
4097 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4098 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4099 if (!ha->exlogin_buf) {
4100 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4101 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4102 return -ENOMEM;
4103 }
b0d6cabd
HM		 4104 }
4105
4106 /* Now configure the dma buffer */
4107 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4108 if (rval) {
83548fe2 4109 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4110 "Setup extended login buffer ****FAILED****.\n");
4111 qla2x00_free_exlogin_buffer(ha);
4112 }
4113
4114 return rval;
4115}
4116
4117/*
4118* qla2x00_free_exlogin_buffer
4119*
4120* Input:
4121* ha = adapter block pointer
4122*/
4123void
4124qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4125{
4126 if (ha->exlogin_buf) {
4127 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4128 ha->exlogin_buf, ha->exlogin_buf_dma);
4129 ha->exlogin_buf = NULL;
4130 ha->exlogin_size = 0;
4131 }
4132}
4133
99e1b683
QT		 4134static void
4135qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4136{
4137 u32 temp;
4138 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4139
4140 if (qla_ini_mode_enabled(vha)) {
4141 if (ql2xiniexchg > max_cnt)
4142 ql2xiniexchg = max_cnt;
4143
4144 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4145 *ret_cnt = ql2xiniexchg;
4146 } else if (qla_tgt_mode_enabled(vha)) {
4147 if (ql2xexchoffld > max_cnt)
4148 ql2xexchoffld = max_cnt;
4149
4150 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4151 *ret_cnt = ql2xexchoffld;
4152 } else if (qla_dual_mode_enabled(vha)) {
4153 temp = ql2xiniexchg + ql2xexchoffld;
4154 if (temp > max_cnt) {
4155 ql2xiniexchg -= (temp - max_cnt)/2;
4156 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4157 temp = max_cnt;
4158 }
4159
4160 if (temp > FW_DEF_EXCHANGES_CNT)
4161 *ret_cnt = temp;
4162 }
4163}
4164
2f56a7f1
HM		 4165int
4166qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4167{
4168 int rval;
99e1b683
QT		 4169 u16 size, max_cnt;
4170 u32 temp;
2f56a7f1
HM		 4171 struct qla_hw_data *ha = vha->hw;
4172
99e1b683
QT		 4173 if (!ha->flags.exchoffld_enabled)
4174 return QLA_SUCCESS;
4175
4176 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4177 return QLA_SUCCESS;
4178
2f56a7f1
HM		 4179 max_cnt = 0;
4180 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4181 if (rval != QLA_SUCCESS) {
4182 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4183 "Failed to get exlogin status.\n");
4184 return rval;
4185 }
4186
99e1b683
QT		 4187 qla2x00_number_of_exch(vha, &temp, max_cnt);
4188 temp *= size;
2f56a7f1 4189
99e1b683
QT		 4190 if (temp != ha->exchoffld_size) {
4191 qla2x00_free_exchoffld_buffer(ha);
4192 ha->exchoffld_size = temp;
4193
4194 ql_log(ql_log_info, vha, 0xd016,
4195 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4196 max_cnt, size, temp);
4197
4198 ql_log(ql_log_info, vha, 0xd017,
4199 "Exchange Buffers requested size = 0x%x\n",
4200 ha->exchoffld_size);
4201
4202 /* Get consistent memory for extended logins */
4203 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4204 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4205 if (!ha->exchoffld_buf) {
4206 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4207 "Failed to allocate memory for exchoffld_buf_dma.\n");
4208 return -ENOMEM;
4209 }
2f56a7f1
HM		 4210 }
4211
4212 /* Now configure the dma buffer */
99e1b683 4213 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4214 if (rval) {
4215 ql_log(ql_log_fatal, vha, 0xd02e,
4216 "Setup exchange offload buffer ****FAILED****.\n");
4217 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4218 } else {
4219 /* re-adjust number of target exchange */
4220 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4221
4222 if (qla_ini_mode_enabled(vha))
4223 icb->exchange_count = 0;
4224 else
4225 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4226 }
4227
4228 return rval;
4229}
4230
4231/*
4232* qla2x00_free_exchoffld_buffer
4233*
4234* Input:
4235* ha = adapter block pointer
4236*/
4237void
4238qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4239{
4240 if (ha->exchoffld_buf) {
4241 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4242 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4243 ha->exchoffld_buf = NULL;
4244 ha->exchoffld_size = 0;
4245 }
4246}
4247
1da177e4 4248/*
e30d1756
MI		 4249* qla2x00_free_fw_dump
4250* Frees fw dump stuff.
1da177e4
LT		 4251*
4252* Input:
7ec0effd 4253* ha = adapter block pointer
1da177e4 4254*/
a824ebb3 4255static void
e30d1756 4256qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4257{
df613b96 4258 if (ha->fce)
f73cb695
CD		 4259 dma_free_coherent(&ha->pdev->dev,
4260 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4261
f73cb695
CD		 4262 if (ha->eft)
4263 dma_free_coherent(&ha->pdev->dev,
4264 EFT_SIZE, ha->eft, ha->eft_dma);
4265
4266 if (ha->fw_dump)
a7a167bf 4267 vfree(ha->fw_dump);
f73cb695
CD		 4268 if (ha->fw_dump_template)
4269 vfree(ha->fw_dump_template);
4270
e30d1756
MI		 4271 ha->fce = NULL;
4272 ha->fce_dma = 0;
4273 ha->eft = NULL;
4274 ha->eft_dma = 0;
e30d1756 4275 ha->fw_dumped = 0;
61f098dd 4276 ha->fw_dump_cap_flags = 0;
e30d1756 4277 ha->fw_dump_reading = 0;
f73cb695
CD		 4278 ha->fw_dump = NULL;
4279 ha->fw_dump_len = 0;
4280 ha->fw_dump_template = NULL;
4281 ha->fw_dump_template_len = 0;
e30d1756
MI		 4282}
4283
4284/*
4285* qla2x00_mem_free
4286* Frees all adapter allocated memory.
4287*
4288* Input:
4289* ha = adapter block pointer.
4290*/
4291static void
4292qla2x00_mem_free(struct qla_hw_data *ha)
4293{
4294 qla2x00_free_fw_dump(ha);
4295
81178772
SK		 4296 if (ha->mctp_dump)
4297 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4298 ha->mctp_dump_dma);
4299
e30d1756
MI		 4300 if (ha->srb_mempool)
4301 mempool_destroy(ha->srb_mempool);
a7a167bf 4302
11bbc1d8
AV		 4303 if (ha->dcbx_tlv)
4304 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4305 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4306
ce0423f4
AV		 4307 if (ha->xgmac_data)
4308 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4309 ha->xgmac_data, ha->xgmac_data_dma);
4310
1da177e4
LT		 4311 if (ha->sns_cmd)
4312 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4313 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4314
4315 if (ha->ct_sns)
4316 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4317 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4318
88729e53
AV		 4319 if (ha->sfp_data)
4320 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4321
1da177e4
LT		 4322 if (ha->ms_iocb)
4323 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4324
b64b0e8f 4325 if (ha->ex_init_cb)
a9083016
GM		 4326 dma_pool_free(ha->s_dma_pool,
4327 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4328
5ff1d584
AV		 4329 if (ha->async_pd)
4330 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4331
1da177e4
LT		 4332 if (ha->s_dma_pool)
4333 dma_pool_destroy(ha->s_dma_pool);
4334
1da177e4 4335 if (ha->gid_list)
642ef983
CD		 4336 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4337 ha->gid_list, ha->gid_list_dma);
1da177e4 4338
a9083016
GM		 4339 if (IS_QLA82XX(ha)) {
4340 if (!list_empty(&ha->gbl_dsd_list)) {
4341 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4342
4343 /* clean up allocated prev pool */
4344 list_for_each_entry_safe(dsd_ptr,
4345 tdsd_ptr, &ha->gbl_dsd_list, list) {
4346 dma_pool_free(ha->dl_dma_pool,
4347 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4348 list_del(&dsd_ptr->list);
4349 kfree(dsd_ptr);
4350 }
4351 }
4352 }
4353
4354 if (ha->dl_dma_pool)
4355 dma_pool_destroy(ha->dl_dma_pool);
4356
4357 if (ha->fcp_cmnd_dma_pool)
4358 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4359
4360 if (ha->ctx_mempool)
4361 mempool_destroy(ha->ctx_mempool);
4362
2d70c103
NB		 4363 qlt_mem_free(ha);
4364
e315cd28
AC		 4365 if (ha->init_cb)
4366 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4367 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4368 vfree(ha->optrom_buffer);
4369 kfree(ha->nvram);
73208dfd 4370 kfree(ha->npiv_info);
7a67735b 4371 kfree(ha->swl);
5f16b331 4372 kfree(ha->loop_id_map);
1da177e4 4373
e8711085 4374 ha->srb_mempool = NULL;
a9083016 4375 ha->ctx_mempool = NULL;
1da177e4
LT		 4376 ha->sns_cmd = NULL;
4377 ha->sns_cmd_dma = 0;
4378 ha->ct_sns = NULL;
4379 ha->ct_sns_dma = 0;
4380 ha->ms_iocb = NULL;
4381 ha->ms_iocb_dma = 0;
1da177e4
LT		 4382 ha->init_cb = NULL;
4383 ha->init_cb_dma = 0;
b64b0e8f
AV		 4384 ha->ex_init_cb = NULL;
4385 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4386 ha->async_pd = NULL;
4387 ha->async_pd_dma = 0;
1da177e4
LT		 4388
4389 ha->s_dma_pool = NULL;
a9083016
GM		 4390 ha->dl_dma_pool = NULL;
4391 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4392
1da177e4
LT		 4393 ha->gid_list = NULL;
4394 ha->gid_list_dma = 0;
2d70c103
NB		 4395
4396 ha->tgt.atio_ring = NULL;
4397 ha->tgt.atio_dma = 0;
4398 ha->tgt.tgt_vp_map = NULL;
e315cd28 4399}
1da177e4 4400
e315cd28
AC		 4401struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4402 struct qla_hw_data *ha)
4403{
4404 struct Scsi_Host *host;
4405 struct scsi_qla_host *vha = NULL;
854165f4 4406
e315cd28 4407 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4408 if (!host) {
7c3df132
SK		 4409 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4410 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4411 return NULL;
e315cd28
AC		 4412 }
4413
4414 /* Clear our data area */
4415 vha = shost_priv(host);
4416 memset(vha, 0, sizeof(scsi_qla_host_t));
4417
4418 vha->host = host;
4419 vha->host_no = host->host_no;
4420 vha->hw = ha;
4421
4422 INIT_LIST_HEAD(&vha->vp_fcports);
4423 INIT_LIST_HEAD(&vha->work_list);
4424 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4425 INIT_LIST_HEAD(&vha->qla_cmd_list);
4426 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4427 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4428 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4429 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4430 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4431 INIT_LIST_HEAD(&vha->nvme_rport_list);
e315cd28 4432
f999f4c1 4433 spin_lock_init(&vha->work_lock);
8b2f5ff3 4434 spin_lock_init(&vha->cmd_list_lock);
726b8548 4435 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4436 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4437
2fdbc65e
BVA		 4438 vha->gnl.size = sizeof(struct get_name_list_extended) *
4439 (ha->max_loop_id + 1);
41dc529a
QT		 4440 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4441 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4442 if (!vha->gnl.l) {
83548fe2 4443 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4444 "Alloc failed for name list.\n");
4445 scsi_remove_host(vha->host);
4446 return NULL;
4447 }
f999f4c1 4448
e315cd28 4449 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4450 ql_dbg(ql_dbg_init, vha, 0x0041,
4451 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4452 vha->host, vha->hw, vha,
4453 dev_name(&(ha->pdev->dev)));
4454
e315cd28 4455 return vha;
1da177e4
LT		 4456}
4457
726b8548 4458struct qla_work_evt *
f999f4c1 4459qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4460{
4461 struct qla_work_evt *e;
feafb7b1
AE		 4462 uint8_t bail;
4463
4464 QLA_VHA_MARK_BUSY(vha, bail);
4465 if (bail)
4466 return NULL;
0971de7f 4467
f999f4c1 4468 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4469 if (!e) {
4470 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4471 return NULL;
feafb7b1 4472 }
0971de7f
AV		 4473
4474 INIT_LIST_HEAD(&e->list);
4475 e->type = type;
4476 e->flags = QLA_EVT_FLAG_FREE;
4477 return e;
4478}
4479
726b8548 4480int
f999f4c1 4481qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4482{
f999f4c1 4483 unsigned long flags;
0971de7f 4484
f999f4c1 4485 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4486 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4487 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4488
4489 if (QLA_EARLY_LINKUP(vha->hw))
4490 schedule_work(&vha->iocb_work);
4491 else
4492 qla2xxx_wake_dpc(vha);
f999f4c1 4493
0971de7f
AV		 4494 return QLA_SUCCESS;
4495}
4496
4497int
e315cd28 4498qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4499 u32 data)
4500{
4501 struct qla_work_evt *e;
4502
f999f4c1 4503 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4504 if (!e)
4505 return QLA_FUNCTION_FAILED;
4506
4507 e->u.aen.code = code;
4508 e->u.aen.data = data;
f999f4c1 4509 return qla2x00_post_work(vha, e);
0971de7f
AV		 4510}
4511
8a659571
AV		 4512int
4513qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4514{
4515 struct qla_work_evt *e;
4516
f999f4c1 4517 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4518 if (!e)
4519 return QLA_FUNCTION_FAILED;
4520
4521 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4522 return qla2x00_post_work(vha, e);
8a659571
AV		 4523}
4524
ac280b67
AV		 4525#define qla2x00_post_async_work(name, type) \
4526int qla2x00_post_async_##name##_work( \
4527 struct scsi_qla_host *vha, \
4528 fc_port_t *fcport, uint16_t *data) \
4529{ \
4530 struct qla_work_evt *e; \
4531 \
4532 e = qla2x00_alloc_work(vha, type); \
4533 if (!e) \
4534 return QLA_FUNCTION_FAILED; \
4535 \
4536 e->u.logio.fcport = fcport; \
4537 if (data) { \
4538 e->u.logio.data[0] = data[0]; \
4539 e->u.logio.data[1] = data[1]; \
4540 } \
4541 return qla2x00_post_work(vha, e); \
4542}
4543
4544qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4545qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4546qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4547qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4548qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4549
3420d36c
AV		 4550int
4551qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4552{
4553 struct qla_work_evt *e;
4554
4555 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4556 if (!e)
4557 return QLA_FUNCTION_FAILED;
4558
4559 e->u.uevent.code = code;
4560 return qla2x00_post_work(vha, e);
4561}
4562
4563static void
4564qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4565{
4566 char event_string[40];
4567 char *envp[] = { event_string, NULL };
4568
4569 switch (code) {
4570 case QLA_UEVENT_CODE_FW_DUMP:
4571 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4572 vha->host_no);
4573 break;
4574 default:
4575 /* do nothing */
4576 break;
4577 }
4578 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4579}
4580
8ae6d9c7
GM		 4581int
4582qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4583 uint32_t *data, int cnt)
4584{
4585 struct qla_work_evt *e;
4586
4587 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4588 if (!e)
4589 return QLA_FUNCTION_FAILED;
4590
4591 e->u.aenfx.evtcode = evtcode;
4592 e->u.aenfx.count = cnt;
4593 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4594 return qla2x00_post_work(vha, e);
4595}
4596
726b8548
QT		 4597int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4598{
4599 struct qla_work_evt *e;
4600
4601 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4602 if (!e)
4603 return QLA_FUNCTION_FAILED;
4604
4605 e->u.fcport.fcport = fcport;
4606 return qla2x00_post_work(vha, e);
4607}
4608
4609static
4610void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4611{
4612 unsigned long flags;
4613 fc_port_t *fcport = NULL;
4614 struct qlt_plogi_ack_t *pla =
4615 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4616
4617 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4618 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4619 if (fcport) {
4620 fcport->d_id = e->u.new_sess.id;
4621 if (pla) {
4622 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4623 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4624 /* we took an extra ref_count to prevent PLOGI ACK when
4625 * fcport/sess has not been created.
4626 */
4627 pla->ref_count--;
4628 }
4629 } else {
4630 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4631 if (fcport) {
4632 fcport->d_id = e->u.new_sess.id;
4633 fcport->scan_state = QLA_FCPORT_FOUND;
4634 fcport->flags |= FCF_FABRIC_DEVICE;
4635 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4636
4637 memcpy(fcport->port_name, e->u.new_sess.port_name,
4638 WWN_SIZE);
4639 list_add_tail(&fcport->list, &vha->vp_fcports);
4640
4641 if (pla) {
4642 qlt_plogi_ack_link(vha, pla, fcport,
4643 QLT_PLOGI_LINK_SAME_WWN);
4644 pla->ref_count--;
4645 }
4646 }
4647 }
4648 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4649
4650 if (fcport) {
4651 if (pla)
4652 qlt_plogi_ack_unref(vha, pla);
4653 else
4654 qla24xx_async_gnl(vha, fcport);
4655 }
4656}
4657
ac280b67 4658void
e315cd28 4659qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4660{
f999f4c1
AV		 4661 struct qla_work_evt *e, *tmp;
4662 unsigned long flags;
4663 LIST_HEAD(work);
0971de7f 4664
f999f4c1
AV		 4665 spin_lock_irqsave(&vha->work_lock, flags);
4666 list_splice_init(&vha->work_list, &work);
4667 spin_unlock_irqrestore(&vha->work_lock, flags);
4668
4669 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4670 list_del_init(&e->list);
0971de7f
AV		 4671
4672 switch (e->type) {
4673 case QLA_EVT_AEN:
e315cd28 4674 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4675 e->u.aen.code, e->u.aen.data);
4676 break;
8a659571
AV		 4677 case QLA_EVT_IDC_ACK:
4678 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4679 break;
ac280b67
AV		 4680 case QLA_EVT_ASYNC_LOGIN:
4681 qla2x00_async_login(vha, e->u.logio.fcport,
4682 e->u.logio.data);
4683 break;
ac280b67
AV		 4684 case QLA_EVT_ASYNC_LOGOUT:
4685 qla2x00_async_logout(vha, e->u.logio.fcport);
4686 break;
4687 case QLA_EVT_ASYNC_LOGOUT_DONE:
4688 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4689 e->u.logio.data);
4690 break;
5ff1d584
AV		 4691 case QLA_EVT_ASYNC_ADISC:
4692 qla2x00_async_adisc(vha, e->u.logio.fcport,
4693 e->u.logio.data);
4694 break;
4695 case QLA_EVT_ASYNC_ADISC_DONE:
4696 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4697 e->u.logio.data);
4698 break;
3420d36c
AV		 4699 case QLA_EVT_UEVENT:
4700 qla2x00_uevent_emit(vha, e->u.uevent.code);
4701 break;
8ae6d9c7
GM		 4702 case QLA_EVT_AENFX:
4703 qlafx00_process_aen(vha, e);
4704 break;
726b8548
QT		 4705 case QLA_EVT_GIDPN:
4706 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4707 break;
4708 case QLA_EVT_GPNID:
4709 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4710 break;
4711 case QLA_EVT_GPNID_DONE:
4712 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4713 break;
4714 case QLA_EVT_NEW_SESS:
4715 qla24xx_create_new_sess(vha, e);
4716 break;
4717 case QLA_EVT_GPDB:
4718 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4719 e->u.fcport.opt);
4720 break;
a5d42f4c
DG		 4721 case QLA_EVT_PRLI:
4722 qla24xx_async_prli(vha, e->u.fcport.fcport);
4723 break;
726b8548
QT		 4724 case QLA_EVT_GPSC:
4725 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4726 break;
4727 case QLA_EVT_UPD_FCPORT:
4728 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4729 break;
4730 case QLA_EVT_GNL:
4731 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4732 break;
4733 case QLA_EVT_NACK:
4734 qla24xx_do_nack_work(vha, e);
4735 break;
0971de7f
AV		 4736 }
4737 if (e->flags & QLA_EVT_FLAG_FREE)
4738 kfree(e);
feafb7b1
AE		 4739
4740 /* For each work completed decrement vha ref count */
4741 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4742 }
e315cd28 4743}
f999f4c1 4744
e315cd28
AC		 4745/* Relogins all the fcports of a vport
4746 * Context: dpc thread
4747 */
4748void qla2x00_relogin(struct scsi_qla_host *vha)
4749{
4750 fc_port_t *fcport;
c6b2fca8 4751 int status;
726b8548 4752 struct event_arg ea;
e315cd28
AC		 4753
4754 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4755 /*
4756 * If the port is not ONLINE then try to login
4757 * to it if we haven't run out of retries.
4758 */
5ff1d584
AV		 4759 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4760 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4761 fcport->login_retry--;
e315cd28 4762 if (fcport->flags & FCF_FABRIC_DEVICE) {
83548fe2 4763 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4764 "%s %8phC DS %d LS %d\n", __func__,
4765 fcport->port_name, fcport->disc_state,
4766 fcport->fw_login_state);
4767 memset(&ea, 0, sizeof(ea));
4768 ea.event = FCME_RELOGIN;
4769 ea.fcport = fcport;
4770 qla2x00_fcport_event_handler(vha, &ea);
4771 } else {
e315cd28
AC		 4772 status = qla2x00_local_device_login(vha,
4773 fcport);
726b8548
QT		 4774 if (status == QLA_SUCCESS) {
4775 fcport->old_loop_id = fcport->loop_id;
4776 ql_dbg(ql_dbg_disc, vha, 0x2003,
4777 "Port login OK: logged in ID 0x%x.\n",
4778 fcport->loop_id);
4779 qla2x00_update_fcport(vha, fcport);
4780 } else if (status == 1) {
4781 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4782 /* retry the login again */
4783 ql_dbg(ql_dbg_disc, vha, 0x2007,
4784 "Retrying %d login again loop_id 0x%x.\n",
4785 fcport->login_retry,
4786 fcport->loop_id);
4787 } else {
4788 fcport->login_retry = 0;
4789 }
e315cd28 4790
726b8548
QT		 4791 if (fcport->login_retry == 0 &&
4792 status != QLA_SUCCESS)
4793 qla2x00_clear_loop_id(fcport);
e315cd28 4794 }
e315cd28
AC		 4795 }
4796 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4797 break;
0971de7f 4798 }
0971de7f
AV		 4799}
4800
7d613ac6
SV		 4801/* Schedule work on any of the dpc-workqueues */
4802void
4803qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4804{
4805 struct qla_hw_data *ha = base_vha->hw;
4806
4807 switch (work_code) {
4808 case MBA_IDC_AEN: /* 0x8200 */
4809 if (ha->dpc_lp_wq)
4810 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4811 break;
4812
4813 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4814 if (!ha->flags.nic_core_reset_hdlr_active) {
4815 if (ha->dpc_hp_wq)
4816 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4817 } else
4818 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4819 "NIC Core reset is already active. Skip "
4820 "scheduling it again.\n");
4821 break;
4822 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4823 if (ha->dpc_hp_wq)
4824 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4825 break;
4826 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4827 if (ha->dpc_hp_wq)
4828 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4829 break;
4830 default:
4831 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4832 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4833 }
4834
4835 return;
4836}
4837
4838/* Work: Perform NIC Core Unrecoverable state handling */
4839void
4840qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4841{
4842 struct qla_hw_data *ha =
2ad1b67c 4843 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4844 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4845 uint32_t dev_state = 0;
4846
4847 qla83xx_idc_lock(base_vha, 0);
4848 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4849 qla83xx_reset_ownership(base_vha);
4850 if (ha->flags.nic_core_reset_owner) {
4851 ha->flags.nic_core_reset_owner = 0;
4852 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4853 QLA8XXX_DEV_FAILED);
4854 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4855 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4856 }
4857 qla83xx_idc_unlock(base_vha, 0);
4858}
4859
4860/* Work: Execute IDC state handler */
4861void
4862qla83xx_idc_state_handler_work(struct work_struct *work)
4863{
4864 struct qla_hw_data *ha =
2ad1b67c 4865 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4866 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4867 uint32_t dev_state = 0;
4868
4869 qla83xx_idc_lock(base_vha, 0);
4870 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4871 if (dev_state == QLA8XXX_DEV_FAILED ||
4872 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4873 qla83xx_idc_state_handler(base_vha);
4874 qla83xx_idc_unlock(base_vha, 0);
4875}
4876
fa492630 4877static int
7d613ac6
SV		 4878qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4879{
4880 int rval = QLA_SUCCESS;
4881 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4882 uint32_t heart_beat_counter1, heart_beat_counter2;
4883
4884 do {
4885 if (time_after(jiffies, heart_beat_wait)) {
4886 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4887 "Nic Core f/w is not alive.\n");
4888 rval = QLA_FUNCTION_FAILED;
4889 break;
4890 }
4891
4892 qla83xx_idc_lock(base_vha, 0);
4893 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4894 &heart_beat_counter1);
4895 qla83xx_idc_unlock(base_vha, 0);
4896 msleep(100);
4897 qla83xx_idc_lock(base_vha, 0);
4898 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4899 &heart_beat_counter2);
4900 qla83xx_idc_unlock(base_vha, 0);
4901 } while (heart_beat_counter1 == heart_beat_counter2);
4902
4903 return rval;
4904}
4905
4906/* Work: Perform NIC Core Reset handling */
4907void
4908qla83xx_nic_core_reset_work(struct work_struct *work)
4909{
4910 struct qla_hw_data *ha =
4911 container_of(work, struct qla_hw_data, nic_core_reset);
4912 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4913 uint32_t dev_state = 0;
4914
81178772
SK		 4915 if (IS_QLA2031(ha)) {
4916 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4917 ql_log(ql_log_warn, base_vha, 0xb081,
4918 "Failed to dump mctp\n");
4919 return;
4920 }
4921
7d613ac6
SV		 4922 if (!ha->flags.nic_core_reset_hdlr_active) {
4923 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4924 qla83xx_idc_lock(base_vha, 0);
4925 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4926 &dev_state);
4927 qla83xx_idc_unlock(base_vha, 0);
4928 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4929 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4930 "Nic Core f/w is alive.\n");
4931 return;
4932 }
4933 }
4934
4935 ha->flags.nic_core_reset_hdlr_active = 1;
4936 if (qla83xx_nic_core_reset(base_vha)) {
4937 /* NIC Core reset failed. */
4938 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4939 "NIC Core reset failed.\n");
4940 }
4941 ha->flags.nic_core_reset_hdlr_active = 0;
4942 }
4943}
4944
4945/* Work: Handle 8200 IDC aens */
4946void
4947qla83xx_service_idc_aen(struct work_struct *work)
4948{
4949 struct qla_hw_data *ha =
4950 container_of(work, struct qla_hw_data, idc_aen);
4951 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4952 uint32_t dev_state, idc_control;
4953
4954 qla83xx_idc_lock(base_vha, 0);
4955 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4956 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4957 qla83xx_idc_unlock(base_vha, 0);
4958 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4959 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4960 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4961 "Application requested NIC Core Reset.\n");
4962 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4963 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4964 QLA_SUCCESS) {
4965 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4966 "Other protocol driver requested NIC Core Reset.\n");
4967 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4968 }
4969 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4970 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4971 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4972 }
4973}
4974
4975static void
4976qla83xx_wait_logic(void)
4977{
4978 int i;
4979
4980 /* Yield CPU */
4981 if (!in_interrupt()) {
4982 /*
4983 * Wait about 200ms before retrying again.
4984 * This controls the number of retries for single
4985 * lock operation.
4986 */
4987 msleep(100);
4988 schedule();
4989 } else {
4990 for (i = 0; i < 20; i++)
4991 cpu_relax(); /* This a nop instr on i386 */
4992 }
4993}
4994
fa492630 4995static int
7d613ac6
SV		 4996qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4997{
4998 int rval;
4999 uint32_t data;
5000 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5001 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5002 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5003 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5004 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5005
5006 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5007 if (rval)
5008 return rval;
5009
5010 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5011 return QLA_SUCCESS;
5012 } else {
5013 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5014 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5015 data);
5016 if (rval)
5017 return rval;
5018
5019 msleep(200);
5020
5021 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5022 &data);
5023 if (rval)
5024 return rval;
5025
5026 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5027 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5028 ~(idc_lck_rcvry_stage_mask));
5029 rval = qla83xx_wr_reg(base_vha,
5030 QLA83XX_IDC_LOCK_RECOVERY, data);
5031 if (rval)
5032 return rval;
5033
5034 /* Forcefully perform IDC UnLock */
5035 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5036 &data);
5037 if (rval)
5038 return rval;
5039 /* Clear lock-id by setting 0xff */
5040 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5041 0xff);
5042 if (rval)
5043 return rval;
5044 /* Clear lock-recovery by setting 0x0 */
5045 rval = qla83xx_wr_reg(base_vha,
5046 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5047 if (rval)
5048 return rval;
5049 } else
5050 return QLA_SUCCESS;
5051 }
5052
5053 return rval;
5054}
5055
fa492630 5056static int
7d613ac6
SV		 5057qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5058{
5059 int rval = QLA_SUCCESS;
5060 uint32_t o_drv_lockid, n_drv_lockid;
5061 unsigned long lock_recovery_timeout;
5062
5063 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5064retry_lockid:
5065 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5066 if (rval)
5067 goto exit;
5068
5069 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5070 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5071 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5072 return QLA_SUCCESS;
5073 else
5074 return QLA_FUNCTION_FAILED;
5075 }
5076
5077 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5078 if (rval)
5079 goto exit;
5080
5081 if (o_drv_lockid == n_drv_lockid) {
5082 qla83xx_wait_logic();
5083 goto retry_lockid;
5084 } else
5085 return QLA_SUCCESS;
5086
5087exit:
5088 return rval;
5089}
5090
5091void
5092qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5093{
5094 uint16_t options = (requester_id << 15) | BIT_6;
5095 uint32_t data;
6c315553 5096 uint32_t lock_owner;
7d613ac6
SV		 5097 struct qla_hw_data *ha = base_vha->hw;
5098
5099 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5100retry_lock:
5101 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5102 == QLA_SUCCESS) {
5103 if (data) {
5104 /* Setting lock-id to our function-number */
5105 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5106 ha->portnum);
5107 } else {
6c315553
SK		 5108 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5109 &lock_owner);
7d613ac6 5110 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5111 "Failed to acquire IDC lock, acquired by %d, "
5112 "retrying...\n", lock_owner);
7d613ac6
SV		 5113
5114 /* Retry/Perform IDC-Lock recovery */
5115 if (qla83xx_idc_lock_recovery(base_vha)
5116 == QLA_SUCCESS) {
5117 qla83xx_wait_logic();
5118 goto retry_lock;
5119 } else
5120 ql_log(ql_log_warn, base_vha, 0xb075,
5121 "IDC Lock recovery FAILED.\n");
5122 }
5123
5124 }
5125
5126 return;
5127
5128 /* XXX: IDC-lock implementation using access-control mbx */
5129retry_lock2:
5130 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5131 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5132 "Failed to acquire IDC lock. retrying...\n");
5133 /* Retry/Perform IDC-Lock recovery */
5134 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5135 qla83xx_wait_logic();
5136 goto retry_lock2;
5137 } else
5138 ql_log(ql_log_warn, base_vha, 0xb076,
5139 "IDC Lock recovery FAILED.\n");
5140 }
5141
5142 return;
5143}
5144
5145void
5146qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5147{
5897cb2f
BVA		 5148#if 0
5149 uint16_t options = (requester_id << 15) | BIT_7;
5150#endif
5151 uint16_t retry;
7d613ac6
SV		 5152 uint32_t data;
5153 struct qla_hw_data *ha = base_vha->hw;
5154
5155 /* IDC-unlock implementation using driver-unlock/lock-id
5156 * remote registers
5157 */
5158 retry = 0;
5159retry_unlock:
5160 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5161 == QLA_SUCCESS) {
5162 if (data == ha->portnum) {
5163 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5164 /* Clearing lock-id by setting 0xff */
5165 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5166 } else if (retry < 10) {
5167 /* SV: XXX: IDC unlock retrying needed here? */
5168
5169 /* Retry for IDC-unlock */
5170 qla83xx_wait_logic();
5171 retry++;
5172 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5173 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5174 goto retry_unlock;
5175 }
5176 } else if (retry < 10) {
5177 /* Retry for IDC-unlock */
5178 qla83xx_wait_logic();
5179 retry++;
5180 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5181 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5182 goto retry_unlock;
5183 }
5184
5185 return;
5186
5897cb2f 5187#if 0
7d613ac6
SV		 5188 /* XXX: IDC-unlock implementation using access-control mbx */
5189 retry = 0;
5190retry_unlock2:
5191 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5192 if (retry < 10) {
5193 /* Retry for IDC-unlock */
5194 qla83xx_wait_logic();
5195 retry++;
5196 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5197 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5198 goto retry_unlock2;
5199 }
5200 }
5201
5202 return;
5897cb2f 5203#endif
7d613ac6
SV		 5204}
5205
5206int
5207__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5208{
5209 int rval = QLA_SUCCESS;
5210 struct qla_hw_data *ha = vha->hw;
5211 uint32_t drv_presence;
5212
5213 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5214 if (rval == QLA_SUCCESS) {
5215 drv_presence |= (1 << ha->portnum);
5216 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5217 drv_presence);
5218 }
5219
5220 return rval;
5221}
5222
5223int
5224qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5225{
5226 int rval = QLA_SUCCESS;
5227
5228 qla83xx_idc_lock(vha, 0);
5229 rval = __qla83xx_set_drv_presence(vha);
5230 qla83xx_idc_unlock(vha, 0);
5231
5232 return rval;
5233}
5234
5235int
5236__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5237{
5238 int rval = QLA_SUCCESS;
5239 struct qla_hw_data *ha = vha->hw;
5240 uint32_t drv_presence;
5241
5242 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5243 if (rval == QLA_SUCCESS) {
5244 drv_presence &= ~(1 << ha->portnum);
5245 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5246 drv_presence);
5247 }
5248
5249 return rval;
5250}
5251
5252int
5253qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5254{
5255 int rval = QLA_SUCCESS;
5256
5257 qla83xx_idc_lock(vha, 0);
5258 rval = __qla83xx_clear_drv_presence(vha);
5259 qla83xx_idc_unlock(vha, 0);
5260
5261 return rval;
5262}
5263
fa492630 5264static void
7d613ac6
SV		 5265qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5266{
5267 struct qla_hw_data *ha = vha->hw;
5268 uint32_t drv_ack, drv_presence;
5269 unsigned long ack_timeout;
5270
5271 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5272 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5273 while (1) {
5274 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5275 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5276 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5277 break;
5278
5279 if (time_after_eq(jiffies, ack_timeout)) {
5280 ql_log(ql_log_warn, vha, 0xb067,
5281 "RESET ACK TIMEOUT! drv_presence=0x%x "
5282 "drv_ack=0x%x\n", drv_presence, drv_ack);
5283 /*
5284 * The function(s) which did not ack in time are forced
5285 * to withdraw any further participation in the IDC
5286 * reset.
5287 */
5288 if (drv_ack != drv_presence)
5289 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5290 drv_ack);
5291 break;
5292 }
5293
5294 qla83xx_idc_unlock(vha, 0);
5295 msleep(1000);
5296 qla83xx_idc_lock(vha, 0);
5297 }
5298
5299 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5300 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5301}
5302
fa492630 5303static int
7d613ac6
SV		 5304qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5305{
5306 int rval = QLA_SUCCESS;
5307 uint32_t idc_control;
5308
5309 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5310 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5311
5312 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5313 __qla83xx_get_idc_control(vha, &idc_control);
5314 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5315 __qla83xx_set_idc_control(vha, 0);
5316
5317 qla83xx_idc_unlock(vha, 0);
5318 rval = qla83xx_restart_nic_firmware(vha);
5319 qla83xx_idc_lock(vha, 0);
5320
5321 if (rval != QLA_SUCCESS) {
5322 ql_log(ql_log_fatal, vha, 0xb06a,
5323 "Failed to restart NIC f/w.\n");
5324 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5325 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5326 } else {
5327 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5328 "Success in restarting nic f/w.\n");
5329 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5330 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5331 }
5332
5333 return rval;
5334}
5335
5336/* Assumes idc_lock always held on entry */
5337int
5338qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5339{
5340 struct qla_hw_data *ha = base_vha->hw;
5341 int rval = QLA_SUCCESS;
5342 unsigned long dev_init_timeout;
5343 uint32_t dev_state;
5344
5345 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5346 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5347
5348 while (1) {
5349
5350 if (time_after_eq(jiffies, dev_init_timeout)) {
5351 ql_log(ql_log_warn, base_vha, 0xb06e,
5352 "Initialization TIMEOUT!\n");
5353 /* Init timeout. Disable further NIC Core
5354 * communication.
5355 */
5356 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5357 QLA8XXX_DEV_FAILED);
5358 ql_log(ql_log_info, base_vha, 0xb06f,
5359 "HW State: FAILED.\n");
5360 }
5361
5362 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5363 switch (dev_state) {
5364 case QLA8XXX_DEV_READY:
5365 if (ha->flags.nic_core_reset_owner)
5366 qla83xx_idc_audit(base_vha,
5367 IDC_AUDIT_COMPLETION);
5368 ha->flags.nic_core_reset_owner = 0;
5369 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5370 "Reset_owner reset by 0x%x.\n",
5371 ha->portnum);
5372 goto exit;
5373 case QLA8XXX_DEV_COLD:
5374 if (ha->flags.nic_core_reset_owner)
5375 rval = qla83xx_device_bootstrap(base_vha);
5376 else {
5377 /* Wait for AEN to change device-state */
5378 qla83xx_idc_unlock(base_vha, 0);
5379 msleep(1000);
5380 qla83xx_idc_lock(base_vha, 0);
5381 }
5382 break;
5383 case QLA8XXX_DEV_INITIALIZING:
5384 /* Wait for AEN to change device-state */
5385 qla83xx_idc_unlock(base_vha, 0);
5386 msleep(1000);
5387 qla83xx_idc_lock(base_vha, 0);
5388 break;
5389 case QLA8XXX_DEV_NEED_RESET:
5390 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5391 qla83xx_need_reset_handler(base_vha);
5392 else {
5393 /* Wait for AEN to change device-state */
5394 qla83xx_idc_unlock(base_vha, 0);
5395 msleep(1000);
5396 qla83xx_idc_lock(base_vha, 0);
5397 }
5398 /* reset timeout value after need reset handler */
5399 dev_init_timeout = jiffies +
5400 (ha->fcoe_dev_init_timeout * HZ);
5401 break;
5402 case QLA8XXX_DEV_NEED_QUIESCENT:
5403 /* XXX: DEBUG for now */
5404 qla83xx_idc_unlock(base_vha, 0);
5405 msleep(1000);
5406 qla83xx_idc_lock(base_vha, 0);
5407 break;
5408 case QLA8XXX_DEV_QUIESCENT:
5409 /* XXX: DEBUG for now */
5410 if (ha->flags.quiesce_owner)
5411 goto exit;
5412
5413 qla83xx_idc_unlock(base_vha, 0);
5414 msleep(1000);
5415 qla83xx_idc_lock(base_vha, 0);
5416 dev_init_timeout = jiffies +
5417 (ha->fcoe_dev_init_timeout * HZ);
5418 break;
5419 case QLA8XXX_DEV_FAILED:
5420 if (ha->flags.nic_core_reset_owner)
5421 qla83xx_idc_audit(base_vha,
5422 IDC_AUDIT_COMPLETION);
5423 ha->flags.nic_core_reset_owner = 0;
5424 __qla83xx_clear_drv_presence(base_vha);
5425 qla83xx_idc_unlock(base_vha, 0);
5426 qla8xxx_dev_failed_handler(base_vha);
5427 rval = QLA_FUNCTION_FAILED;
5428 qla83xx_idc_lock(base_vha, 0);
5429 goto exit;
5430 case QLA8XXX_BAD_VALUE:
5431 qla83xx_idc_unlock(base_vha, 0);
5432 msleep(1000);
5433 qla83xx_idc_lock(base_vha, 0);
5434 break;
5435 default:
5436 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5437 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5438 qla83xx_idc_unlock(base_vha, 0);
5439 qla8xxx_dev_failed_handler(base_vha);
5440 rval = QLA_FUNCTION_FAILED;
5441 qla83xx_idc_lock(base_vha, 0);
5442 goto exit;
5443 }
5444 }
5445
5446exit:
5447 return rval;
5448}
5449
f3ddac19
CD		 5450void
5451qla2x00_disable_board_on_pci_error(struct work_struct *work)
5452{
5453 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5454 board_disable);
5455 struct pci_dev *pdev = ha->pdev;
5456 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5457
726b8548
QT		 5458 /*
5459 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5460 * where it was set first.
5461 */
5462 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5463 return;
5464
f3ddac19
CD		 5465 ql_log(ql_log_warn, base_vha, 0x015b,
5466 "Disabling adapter.\n");
5467
726b8548
QT		 5468 qla2x00_wait_for_sess_deletion(base_vha);
5469
f3ddac19
CD		 5470 set_bit(UNLOADING, &base_vha->dpc_flags);
5471
5472 qla2x00_delete_all_vps(ha, base_vha);
5473
5474 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5475
5476 qla2x00_dfs_remove(base_vha);
5477
5478 qla84xx_put_chip(base_vha);
5479
5480 if (base_vha->timer_active)
5481 qla2x00_stop_timer(base_vha);
5482
5483 base_vha->flags.online = 0;
5484
5485 qla2x00_destroy_deferred_work(ha);
5486
5487 /*
5488 * Do not try to stop beacon blink as it will issue a mailbox
5489 * command.
5490 */
5491 qla2x00_free_sysfs_attr(base_vha, false);
5492
5493 fc_remove_host(base_vha->host);
5494
5495 scsi_remove_host(base_vha->host);
5496
5497 base_vha->flags.init_done = 0;
5498 qla25xx_delete_queues(base_vha);
f3ddac19 5499 qla2x00_free_fcports(base_vha);
093df737 5500 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5501 qla2x00_mem_free(ha);
5502 qla82xx_md_free(base_vha);
5503 qla2x00_free_queues(ha);
5504
f3ddac19
CD		 5505 qla2x00_unmap_iobases(ha);
5506
5507 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5508 pci_disable_pcie_error_reporting(pdev);
5509 pci_disable_device(pdev);
f3ddac19 5510
beb9e315
JL		 5511 /*
5512 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5513 */
f3ddac19
CD		 5514}
5515
1da177e4
LT		 5516/**************************************************************************
5517* qla2x00_do_dpc
5518* This kernel thread is a task that is schedule by the interrupt handler
5519* to perform the background processing for interrupts.
5520*
5521* Notes:
5522* This task always run in the context of a kernel thread. It
5523* is kick-off by the driver's detect code and starts up
5524* up one per adapter. It immediately goes to sleep and waits for
5525* some fibre event. When either the interrupt handler or
5526* the timer routine detects a event it will one of the task
5527* bits then wake us up.
5528**************************************************************************/
5529static int
5530qla2x00_do_dpc(void *data)
5531{
e315cd28
AC		 5532 scsi_qla_host_t *base_vha;
5533 struct qla_hw_data *ha;
d7459527
MH		 5534 uint32_t online;
5535 struct qla_qpair *qpair;
1da177e4 5536
e315cd28
AC		 5537 ha = (struct qla_hw_data *)data;
5538 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5539
8698a745 5540 set_user_nice(current, MIN_NICE);
1da177e4 5541
563585ec 5542 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5543 while (!kthread_should_stop()) {
7c3df132
SK		 5544 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5545 "DPC handler sleeping.\n");
1da177e4 5546
39a11240 5547 schedule();
1da177e4 5548
c142caf0
AV		 5549 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5550 goto end_loop;
1da177e4 5551
85880801 5552 if (ha->flags.eeh_busy) {
7c3df132
SK		 5553 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5554 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5555 goto end_loop;
85880801
AV		 5556 }
5557
1da177e4
LT		 5558 ha->dpc_active = 1;
5559
5f28d2d7
SK		 5560 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5561 "DPC handler waking up, dpc_flags=0x%lx.\n",
5562 base_vha->dpc_flags);
1da177e4 5563
a29b3dd7
JC		 5564 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5565 break;
5566
e315cd28 5567 qla2x00_do_work(base_vha);
0971de7f 5568
7ec0effd
AD		 5569 if (IS_P3P_TYPE(ha)) {
5570 if (IS_QLA8044(ha)) {
5571 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5572 &base_vha->dpc_flags)) {
5573 qla8044_idc_lock(ha);
5574 qla8044_wr_direct(base_vha,
5575 QLA8044_CRB_DEV_STATE_INDEX,
5576 QLA8XXX_DEV_FAILED);
5577 qla8044_idc_unlock(ha);
5578 ql_log(ql_log_info, base_vha, 0x4004,
5579 "HW State: FAILED.\n");
5580 qla8044_device_state_handler(base_vha);
5581 continue;
5582 }
5583
5584 } else {
5585 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5586 &base_vha->dpc_flags)) {
5587 qla82xx_idc_lock(ha);
5588 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5589 QLA8XXX_DEV_FAILED);
5590 qla82xx_idc_unlock(ha);
5591 ql_log(ql_log_info, base_vha, 0x0151,
5592 "HW State: FAILED.\n");
5593 qla82xx_device_state_handler(base_vha);
5594 continue;
5595 }
a9083016
GM		 5596 }
5597
5598 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5599 &base_vha->dpc_flags)) {
5600
7c3df132
SK		 5601 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5602 "FCoE context reset scheduled.\n");
a9083016
GM		 5603 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5604 &base_vha->dpc_flags))) {
5605 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5606 /* FCoE-ctx reset failed.
5607 * Escalate to chip-reset
5608 */
5609 set_bit(ISP_ABORT_NEEDED,
5610 &base_vha->dpc_flags);
5611 }
5612 clear_bit(ABORT_ISP_ACTIVE,
5613 &base_vha->dpc_flags);
5614 }
5615
7c3df132
SK		 5616 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5617 "FCoE context reset end.\n");
a9083016 5618 }
8ae6d9c7
GM		 5619 } else if (IS_QLAFX00(ha)) {
5620 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5621 &base_vha->dpc_flags)) {
5622 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5623 "Firmware Reset Recovery\n");
5624 if (qlafx00_reset_initialize(base_vha)) {
5625 /* Failed. Abort isp later. */
5626 if (!test_bit(UNLOADING,
f92f82d6 5627 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5628 set_bit(ISP_UNRECOVERABLE,
5629 &base_vha->dpc_flags);
5630 ql_dbg(ql_dbg_dpc, base_vha,
5631 0x4021,
5632 "Reset Recovery Failed\n");
f92f82d6 5633 }
8ae6d9c7
GM		 5634 }
5635 }
5636
5637 if (test_and_clear_bit(FX00_TARGET_SCAN,
5638 &base_vha->dpc_flags)) {
5639 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5640 "ISPFx00 Target Scan scheduled\n");
5641 if (qlafx00_rescan_isp(base_vha)) {
5642 if (!test_bit(UNLOADING,
5643 &base_vha->dpc_flags))
5644 set_bit(ISP_UNRECOVERABLE,
5645 &base_vha->dpc_flags);
5646 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5647 "ISPFx00 Target Scan Failed\n");
5648 }
5649 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5650 "ISPFx00 Target Scan End\n");
5651 }
e8f5e95d
AB		 5652 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5653 &base_vha->dpc_flags)) {
5654 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5655 "ISPFx00 Host Info resend scheduled\n");
5656 qlafx00_fx_disc(base_vha,
5657 &base_vha->hw->mr.fcport,
5658 FXDISC_REG_HOST_INFO);
5659 }
a9083016
GM		 5660 }
5661
e315cd28
AC		 5662 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5663 &base_vha->dpc_flags)) {
1da177e4 5664
7c3df132
SK		 5665 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5666 "ISP abort scheduled.\n");
1da177e4 5667 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5668 &base_vha->dpc_flags))) {
1da177e4 5669
a9083016 5670 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5671 /* failed. retry later */
5672 set_bit(ISP_ABORT_NEEDED,
e315cd28 5673 &base_vha->dpc_flags);
99363ef8 5674 }
e315cd28
AC		 5675 clear_bit(ABORT_ISP_ACTIVE,
5676 &base_vha->dpc_flags);
99363ef8
SJ		 5677 }
5678
7c3df132
SK		 5679 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5680 "ISP abort end.\n");
1da177e4
LT		 5681 }
5682
a394aac8
DJ		 5683 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5684 &base_vha->dpc_flags)) {
e315cd28 5685 qla2x00_update_fcports(base_vha);
c9c5ced9 5686 }
d97994dc 5687
8ae6d9c7
GM		 5688 if (IS_QLAFX00(ha))
5689 goto loop_resync_check;
5690
579d12b5 5691 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5692 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5693 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5694 if (IS_P3P_TYPE(ha)) {
5695 if (IS_QLA82XX(ha))
5696 qla82xx_device_state_handler(base_vha);
5697 if (IS_QLA8044(ha))
5698 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5699 clear_bit(ISP_QUIESCE_NEEDED,
5700 &base_vha->dpc_flags);
5701 if (!ha->flags.quiesce_owner) {
5702 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5703 if (IS_QLA82XX(ha)) {
5704 qla82xx_idc_lock(ha);
5705 qla82xx_clear_qsnt_ready(
5706 base_vha);
5707 qla82xx_idc_unlock(ha);
5708 } else if (IS_QLA8044(ha)) {
5709 qla8044_idc_lock(ha);
5710 qla8044_clear_qsnt_ready(
5711 base_vha);
5712 qla8044_idc_unlock(ha);
5713 }
8fcd6b8b
CD		 5714 }
5715 } else {
5716 clear_bit(ISP_QUIESCE_NEEDED,
5717 &base_vha->dpc_flags);
5718 qla2x00_quiesce_io(base_vha);
579d12b5 5719 }
7c3df132
SK		 5720 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5721 "Quiescence mode end.\n");
579d12b5
SK		 5722 }
5723
e315cd28 5724 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5725 &base_vha->dpc_flags) &&
e315cd28 5726 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5727
7c3df132
SK		 5728 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5729 "Reset marker scheduled.\n");
e315cd28
AC		 5730 qla2x00_rst_aen(base_vha);
5731 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5732 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5733 "Reset marker end.\n");
1da177e4
LT		 5734 }
5735
5736 /* Retry each device up to login retry count */
e315cd28
AC		 5737 if ((test_and_clear_bit(RELOGIN_NEEDED,
5738 &base_vha->dpc_flags)) &&
5739 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5740 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5741
7c3df132
SK		 5742 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5743 "Relogin scheduled.\n");
e315cd28 5744 qla2x00_relogin(base_vha);
7c3df132
SK		 5745 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5746 "Relogin end.\n");
1da177e4 5747 }
8ae6d9c7 5748loop_resync_check:
e315cd28 5749 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5750 &base_vha->dpc_flags)) {
1da177e4 5751
7c3df132
SK		 5752 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5753 "Loop resync scheduled.\n");
1da177e4
LT		 5754
5755 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5756 &base_vha->dpc_flags))) {
1da177e4 5757
52c82823 5758 qla2x00_loop_resync(base_vha);
1da177e4 5759
e315cd28
AC		 5760 clear_bit(LOOP_RESYNC_ACTIVE,
5761 &base_vha->dpc_flags);
1da177e4
LT		 5762 }
5763
7c3df132
SK		 5764 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5765 "Loop resync end.\n");
1da177e4
LT		 5766 }
5767
8ae6d9c7
GM		 5768 if (IS_QLAFX00(ha))
5769 goto intr_on_check;
5770
e315cd28
AC		 5771 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5772 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5773 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5774 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5775 }
5776
8ae6d9c7 5777intr_on_check:
1da177e4 5778 if (!ha->interrupts_on)
fd34f556 5779 ha->isp_ops->enable_intrs(ha);
1da177e4 5780
e315cd28 5781 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5782 &base_vha->dpc_flags)) {
5783 if (ha->beacon_blink_led == 1)
5784 ha->isp_ops->beacon_blink(base_vha);
5785 }
f6df144c 5786
d7459527
MH		 5787 /* qpair online check */
5788 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5789 &base_vha->dpc_flags)) {
5790 if (ha->flags.eeh_busy ||
5791 ha->flags.pci_channel_io_perm_failure)
5792 online = 0;
5793 else
5794 online = 1;
5795
5796 mutex_lock(&ha->mq_lock);
5797 list_for_each_entry(qpair, &base_vha->qp_list,
5798 qp_list_elem)
5799 qpair->online = online;
5800 mutex_unlock(&ha->mq_lock);
5801 }
5802
8ae6d9c7
GM		 5803 if (!IS_QLAFX00(ha))
5804 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5805
1da177e4 5806 ha->dpc_active = 0;
c142caf0 5807end_loop:
563585ec 5808 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5809 } /* End of while(1) */
563585ec 5810 __set_current_state(TASK_RUNNING);
1da177e4 5811
7c3df132
SK		 5812 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5813 "DPC handler exiting.\n");
1da177e4
LT		 5814
5815 /*
5816 * Make sure that nobody tries to wake us up again.
5817 */
1da177e4
LT		 5818 ha->dpc_active = 0;
5819
ac280b67
AV		 5820 /* Cleanup any residual CTX SRBs. */
5821 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5822
39a11240
CH		 5823 return 0;
5824}
5825
5826void
e315cd28 5827qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5828{
e315cd28 5829 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5830 struct task_struct *t = ha->dpc_thread;
5831
e315cd28 5832 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5833 wake_up_process(t);
1da177e4
LT		 5834}
5835
1da177e4
LT		 5836/*
5837* qla2x00_rst_aen
5838* Processes asynchronous reset.
5839*
5840* Input:
5841* ha = adapter block pointer.
5842*/
5843static void
e315cd28 5844qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5845{
e315cd28
AC		 5846 if (vha->flags.online && !vha->flags.reset_active &&
5847 !atomic_read(&vha->loop_down_timer) &&
5848 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5849 do {
e315cd28 5850 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5851
5852 /*
5853 * Issue marker command only when we are going to start
5854 * the I/O.
5855 */
e315cd28
AC		 5856 vha->marker_needed = 1;
5857 } while (!atomic_read(&vha->loop_down_timer) &&
5858 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5859 }
5860}
5861
1da177e4
LT		 5862/**************************************************************************
5863* qla2x00_timer
5864*
5865* Description:
5866* One second timer
5867*
5868* Context: Interrupt
5869***************************************************************************/
2c3dfe3f 5870void
e315cd28 5871qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5872{
1da177e4 5873 unsigned long cpu_flags = 0;
1da177e4
LT		 5874 int start_dpc = 0;
5875 int index;
5876 srb_t *sp;
85880801 5877 uint16_t w;
e315cd28 5878 struct qla_hw_data *ha = vha->hw;
73208dfd 5879 struct req_que *req;
85880801 5880
a5b36321 5881 if (ha->flags.eeh_busy) {
7c3df132
SK		 5882 ql_dbg(ql_dbg_timer, vha, 0x6000,
5883 "EEH = %d, restarting timer.\n",
5884 ha->flags.eeh_busy);
a5b36321
LC		 5885 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5886 return;
5887 }
5888
f3ddac19
CD		 5889 /*
5890 * Hardware read to raise pending EEH errors during mailbox waits. If
5891 * the read returns -1 then disable the board.
5892 */
5893 if (!pci_channel_offline(ha->pdev)) {
85880801 5894 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5895 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5896 }
1da177e4 5897
cefcaba6 5898 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5899 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5900 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5901 start_dpc++;
7ec0effd
AD		 5902 if (IS_QLA82XX(ha))
5903 qla82xx_watchdog(vha);
5904 else if (IS_QLA8044(ha))
5905 qla8044_watchdog(vha);
579d12b5
SK		 5906 }
5907
8ae6d9c7
GM		 5908 if (!vha->vp_idx && IS_QLAFX00(ha))
5909 qlafx00_timer_routine(vha);
5910
1da177e4 5911 /* Loop down handler. */
e315cd28 5912 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5913 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5914 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5915 && vha->flags.online) {
1da177e4 5916
e315cd28
AC		 5917 if (atomic_read(&vha->loop_down_timer) ==
5918 vha->loop_down_abort_time) {
1da177e4 5919
7c3df132
SK		 5920 ql_log(ql_log_info, vha, 0x6008,
5921 "Loop down - aborting the queues before time expires.\n");
1da177e4 5922
e315cd28
AC		 5923 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5924 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5925
f08b7251
AV		 5926 /*
5927 * Schedule an ISP abort to return any FCP2-device
5928 * commands.
5929 */
2c3dfe3f 5930 /* NPIV - scan physical port only */
e315cd28 5931 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5932 spin_lock_irqsave(&ha->hardware_lock,
5933 cpu_flags);
73208dfd 5934 req = ha->req_q_map[0];
2c3dfe3f 5935 for (index = 1;
8d93f550 5936 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5937 index++) {
5938 fc_port_t *sfcp;
5939
e315cd28 5940 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5941 if (!sp)
5942 continue;
c5419e26
QT		 5943 if (sp->cmd_type != TYPE_SRB)
5944 continue;
9ba56b95 5945 if (sp->type != SRB_SCSI_CMD)
cf53b069 5946 continue;
2c3dfe3f 5947 sfcp = sp->fcport;
f08b7251 5948 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5949 continue;
bdf79621 5950
8f7daead
GM		 5951 if (IS_QLA82XX(ha))
5952 set_bit(FCOE_CTX_RESET_NEEDED,
5953 &vha->dpc_flags);
5954 else
5955 set_bit(ISP_ABORT_NEEDED,
e315cd28 5956 &vha->dpc_flags);
2c3dfe3f
SJ		 5957 break;
5958 }
5959 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5960 cpu_flags);
1da177e4 5961 }
1da177e4
LT		 5962 start_dpc++;
5963 }
5964
5965 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5966 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5967 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5968 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5969 "Loop down - aborting ISP.\n");
5970
8f7daead
GM		 5971 if (IS_QLA82XX(ha))
5972 set_bit(FCOE_CTX_RESET_NEEDED,
5973 &vha->dpc_flags);
5974 else
5975 set_bit(ISP_ABORT_NEEDED,
5976 &vha->dpc_flags);
1da177e4
LT		 5977 }
5978 }
7c3df132
SK		 5979 ql_dbg(ql_dbg_timer, vha, 0x600a,
5980 "Loop down - seconds remaining %d.\n",
5981 atomic_read(&vha->loop_down_timer));
1da177e4 5982 }
cefcaba6
SK		 5983 /* Check if beacon LED needs to be blinked for physical host only */
5984 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5985 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5986 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5987 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5988 start_dpc++;
5989 }
f6df144c
AV		 5990 }
5991
550bf57d 5992 /* Process any deferred work. */
e315cd28 5993 if (!list_empty(&vha->work_list))
550bf57d
AV		 5994 start_dpc++;
5995
1da177e4 5996 /* Schedule the DPC routine if needed */
e315cd28
AC		 5997 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5998 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5999 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6000 start_dpc ||
e315cd28
AC		 6001 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6002 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6003 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6004 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6005 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6006 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6007 ql_dbg(ql_dbg_timer, vha, 0x600b,
6008 "isp_abort_needed=%d loop_resync_needed=%d "
6009 "fcport_update_needed=%d start_dpc=%d "
6010 "reset_marker_needed=%d",
6011 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6012 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6013 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6014 start_dpc,
6015 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6016 ql_dbg(ql_dbg_timer, vha, 0x600c,
6017 "beacon_blink_needed=%d isp_unrecoverable=%d "
6018 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6019 "relogin_needed=%d.\n",
7c3df132
SK		 6020 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6021 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6022 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6023 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6024 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6025 qla2xxx_wake_dpc(vha);
7c3df132 6026 }
1da177e4 6027
e315cd28 6028 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6029}
6030
5433383e
AV		 6031/* Firmware interface routines. */
6032
f73cb695 6033#define FW_BLOBS 11
5433383e
AV		 6034#define FW_ISP21XX 0
6035#define FW_ISP22XX 1
6036#define FW_ISP2300 2
6037#define FW_ISP2322 3
48c02fde 6038#define FW_ISP24XX 4
c3a2f0df 6039#define FW_ISP25XX 5
3a03eb79 6040#define FW_ISP81XX 6
a9083016 6041#define FW_ISP82XX 7
6246b8a1
GM		 6042#define FW_ISP2031 8
6043#define FW_ISP8031 9
2c5bbbb2 6044#define FW_ISP27XX 10
5433383e 6045
bb8ee499
AV		 6046#define FW_FILE_ISP21XX "ql2100_fw.bin"
6047#define FW_FILE_ISP22XX "ql2200_fw.bin"
6048#define FW_FILE_ISP2300 "ql2300_fw.bin"
6049#define FW_FILE_ISP2322 "ql2322_fw.bin"
6050#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6051#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6052#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6053#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6054#define FW_FILE_ISP2031 "ql2600_fw.bin"
6055#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6056#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6057
bb8ee499 6058
e1e82b6f 6059static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6060
6061static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6062 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6063 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6064 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6065 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6066 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6067 { .name = FW_FILE_ISP25XX, },
3a03eb79 6068 { .name = FW_FILE_ISP81XX, },
a9083016 6069 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6070 { .name = FW_FILE_ISP2031, },
6071 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6072 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6073};
6074
6075struct fw_blob *
e315cd28 6076qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6077{
e315cd28 6078 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6079 struct fw_blob *blob;
6080
5433383e
AV		 6081 if (IS_QLA2100(ha)) {
6082 blob = &qla_fw_blobs[FW_ISP21XX];
6083 } else if (IS_QLA2200(ha)) {
6084 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6085 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6086 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6087 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6088 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6089 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6090 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6091 } else if (IS_QLA25XX(ha)) {
6092 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6093 } else if (IS_QLA81XX(ha)) {
6094 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6095 } else if (IS_QLA82XX(ha)) {
6096 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6097 } else if (IS_QLA2031(ha)) {
6098 blob = &qla_fw_blobs[FW_ISP2031];
6099 } else if (IS_QLA8031(ha)) {
6100 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6101 } else if (IS_QLA27XX(ha)) {
6102 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6103 } else {
6104 return NULL;
5433383e
AV		 6105 }
6106
e1e82b6f 6107 mutex_lock(&qla_fw_lock);
5433383e
AV		 6108 if (blob->fw)
6109 goto out;
6110
6111 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6112 ql_log(ql_log_warn, vha, 0x0063,
6113 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6114 blob->fw = NULL;
6115 blob = NULL;
6116 goto out;
6117 }
6118
6119out:
e1e82b6f 6120 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6121 return blob;
6122}
6123
6124static void
6125qla2x00_release_firmware(void)
6126{
6127 int idx;
6128
e1e82b6f 6129 mutex_lock(&qla_fw_lock);
5433383e 6130 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6131 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6132 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6133}
6134
14e660e6
SJ		 6135static pci_ers_result_t
6136qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6137{
85880801
AV		 6138 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6139 struct qla_hw_data *ha = vha->hw;
6140
7c3df132
SK		 6141 ql_dbg(ql_dbg_aer, vha, 0x9000,
6142 "PCI error detected, state %x.\n", state);
b9b12f73 6143
14e660e6
SJ		 6144 switch (state) {
6145 case pci_channel_io_normal:
85880801 6146 ha->flags.eeh_busy = 0;
d7459527
MH		 6147 if (ql2xmqsupport) {
6148 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6149 qla2xxx_wake_dpc(vha);
6150 }
14e660e6
SJ		 6151 return PCI_ERS_RESULT_CAN_RECOVER;
6152 case pci_channel_io_frozen:
85880801 6153 ha->flags.eeh_busy = 1;
a5b36321
LC		 6154 /* For ISP82XX complete any pending mailbox cmd */
6155 if (IS_QLA82XX(ha)) {
7190575f 6156 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6157 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6158 qla82xx_clear_pending_mbx(vha);
a5b36321 6159 }
90a86fc0 6160 qla2x00_free_irqs(vha);
14e660e6 6161 pci_disable_device(pdev);
bddd2d65
LC		 6162 /* Return back all IOs */
6163 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6164 if (ql2xmqsupport) {
6165 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6166 qla2xxx_wake_dpc(vha);
6167 }
14e660e6
SJ		 6168 return PCI_ERS_RESULT_NEED_RESET;
6169 case pci_channel_io_perm_failure:
85880801
AV		 6170 ha->flags.pci_channel_io_perm_failure = 1;
6171 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6172 if (ql2xmqsupport) {
6173 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6174 qla2xxx_wake_dpc(vha);
6175 }
14e660e6
SJ		 6176 return PCI_ERS_RESULT_DISCONNECT;
6177 }
6178 return PCI_ERS_RESULT_NEED_RESET;
6179}
6180
6181static pci_ers_result_t
6182qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6183{
6184 int risc_paused = 0;
6185 uint32_t stat;
6186 unsigned long flags;
e315cd28
AC		 6187 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6188 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6189 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6190 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6191
bcc5b6d3
SK		 6192 if (IS_QLA82XX(ha))
6193 return PCI_ERS_RESULT_RECOVERED;
6194
14e660e6
SJ		 6195 spin_lock_irqsave(&ha->hardware_lock, flags);
6196 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6197 stat = RD_REG_DWORD(&reg->hccr);
6198 if (stat & HCCR_RISC_PAUSE)
6199 risc_paused = 1;
6200 } else if (IS_QLA23XX(ha)) {
6201 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6202 if (stat & HSR_RISC_PAUSED)
6203 risc_paused = 1;
6204 } else if (IS_FWI2_CAPABLE(ha)) {
6205 stat = RD_REG_DWORD(&reg24->host_status);
6206 if (stat & HSRX_RISC_PAUSED)
6207 risc_paused = 1;
6208 }
6209 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6210
6211 if (risc_paused) {
7c3df132
SK		 6212 ql_log(ql_log_info, base_vha, 0x9003,
6213 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6214 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6215
6216 return PCI_ERS_RESULT_NEED_RESET;
6217 } else
6218 return PCI_ERS_RESULT_RECOVERED;
6219}
6220
fa492630
SK		 6221static uint32_t
6222qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6223{
6224 uint32_t rval = QLA_FUNCTION_FAILED;
6225 uint32_t drv_active = 0;
6226 struct qla_hw_data *ha = base_vha->hw;
6227 int fn;
6228 struct pci_dev *other_pdev = NULL;
6229
7c3df132
SK		 6230 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6231 "Entered %s.\n", __func__);
a5b36321
LC		 6232
6233 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6234
6235 if (base_vha->flags.online) {
6236 /* Abort all outstanding commands,
6237 * so as to be requeued later */
6238 qla2x00_abort_isp_cleanup(base_vha);
6239 }
6240
6241
6242 fn = PCI_FUNC(ha->pdev->devfn);
6243 while (fn > 0) {
6244 fn--;
7c3df132
SK		 6245 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6246 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6247 other_pdev =
6248 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6249 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6250 fn));
6251
6252 if (!other_pdev)
6253 continue;
6254 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6255 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6256 "Found PCI func available and enable at 0x%x.\n",
6257 fn);
a5b36321
LC		 6258 pci_dev_put(other_pdev);
6259 break;
6260 }
6261 pci_dev_put(other_pdev);
6262 }
6263
6264 if (!fn) {
6265 /* Reset owner */
7c3df132
SK		 6266 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6267 "This devfn is reset owner = 0x%x.\n",
6268 ha->pdev->devfn);
a5b36321
LC		 6269 qla82xx_idc_lock(ha);
6270
6271 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6272 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6273
6274 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6275 QLA82XX_IDC_VERSION);
6276
6277 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6278 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6279 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6280
6281 qla82xx_idc_unlock(ha);
6282 /* Reset if device is not already reset
6283 * drv_active would be 0 if a reset has already been done
6284 */
6285 if (drv_active)
6286 rval = qla82xx_start_firmware(base_vha);
6287 else
6288 rval = QLA_SUCCESS;
6289 qla82xx_idc_lock(ha);
6290
6291 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6292 ql_log(ql_log_info, base_vha, 0x900b,
6293 "HW State: FAILED.\n");
a5b36321
LC		 6294 qla82xx_clear_drv_active(ha);
6295 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6296 QLA8XXX_DEV_FAILED);
a5b36321 6297 } else {
7c3df132
SK		 6298 ql_log(ql_log_info, base_vha, 0x900c,
6299 "HW State: READY.\n");
a5b36321 6300 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6301 QLA8XXX_DEV_READY);
a5b36321 6302 qla82xx_idc_unlock(ha);
7190575f 6303 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6304 rval = qla82xx_restart_isp(base_vha);
6305 qla82xx_idc_lock(ha);
6306 /* Clear driver state register */
6307 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6308 qla82xx_set_drv_active(base_vha);
6309 }
6310 qla82xx_idc_unlock(ha);
6311 } else {
7c3df132
SK		 6312 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6313 "This devfn is not reset owner = 0x%x.\n",
6314 ha->pdev->devfn);
a5b36321 6315 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6316 QLA8XXX_DEV_READY)) {
7190575f 6317 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6318 rval = qla82xx_restart_isp(base_vha);
6319 qla82xx_idc_lock(ha);
6320 qla82xx_set_drv_active(base_vha);
6321 qla82xx_idc_unlock(ha);
6322 }
6323 }
6324 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6325
6326 return rval;
6327}
6328
14e660e6
SJ		 6329static pci_ers_result_t
6330qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6331{
6332 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6333 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6334 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6335 struct rsp_que *rsp;
6336 int rc, retries = 10;
09483916 6337
7c3df132
SK		 6338 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6339 "Slot Reset.\n");
85880801 6340
90a86fc0
JC		 6341 /* Workaround: qla2xxx driver which access hardware earlier
6342 * needs error state to be pci_channel_io_online.
6343 * Otherwise mailbox command timesout.
6344 */
6345 pdev->error_state = pci_channel_io_normal;
6346
6347 pci_restore_state(pdev);
6348
8c1496bd
RL		 6349 /* pci_restore_state() clears the saved_state flag of the device
6350 * save restored state which resets saved_state flag
6351 */
6352 pci_save_state(pdev);
6353
09483916
BH		 6354 if (ha->mem_only)
6355 rc = pci_enable_device_mem(pdev);
6356 else
6357 rc = pci_enable_device(pdev);
14e660e6 6358
09483916 6359 if (rc) {
7c3df132 6360 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6361 "Can't re-enable PCI device after reset.\n");
a5b36321 6362 goto exit_slot_reset;
14e660e6 6363 }
14e660e6 6364
90a86fc0
JC		 6365 rsp = ha->rsp_q_map[0];
6366 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6367 goto exit_slot_reset;
90a86fc0 6368
e315cd28 6369 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6370 goto exit_slot_reset;
6371
6372 if (IS_QLA82XX(ha)) {
6373 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6374 ret = PCI_ERS_RESULT_RECOVERED;
6375 goto exit_slot_reset;
6376 } else
6377 goto exit_slot_reset;
6378 }
14e660e6 6379
90a86fc0
JC		 6380 while (ha->flags.mbox_busy && retries--)
6381 msleep(1000);
85880801 6382
e315cd28 6383 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6384 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6385 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6386 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6387
90a86fc0 6388
a5b36321 6389exit_slot_reset:
7c3df132
SK		 6390 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6391 "slot_reset return %x.\n", ret);
85880801 6392
14e660e6
SJ		 6393 return ret;
6394}
6395
6396static void
6397qla2xxx_pci_resume(struct pci_dev *pdev)
6398{
e315cd28
AC		 6399 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6400 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6401 int ret;
6402
7c3df132
SK		 6403 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6404 "pci_resume.\n");
85880801 6405
e315cd28 6406 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6407 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6408 ql_log(ql_log_fatal, base_vha, 0x9002,
6409 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6410 }
85880801 6411
3e46f031
LC		 6412 pci_cleanup_aer_uncorrect_error_status(pdev);
6413
85880801 6414 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6415}
6416
2d5a4c34
HM		 6417static void
6418qla83xx_disable_laser(scsi_qla_host_t *vha)
6419{
6420 uint32_t reg, data, fn;
6421 struct qla_hw_data *ha = vha->hw;
6422 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6423
6424 /* pci func #/port # */
6425 ql_dbg(ql_dbg_init, vha, 0x004b,
6426 "Disabling Laser for hba: %p\n", vha);
6427
6428 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6429 (BIT_15|BIT_14|BIT_13|BIT_12));
6430
6431 fn = (fn >> 12);
6432
6433 if (fn & 1)
6434 reg = PORT_1_2031;
6435 else
6436 reg = PORT_0_2031;
6437
6438 data = LASER_OFF_2031;
6439
6440 qla83xx_wr_reg(vha, reg, data);
6441}
6442
5601236b
MH		 6443static int qla2xxx_map_queues(struct Scsi_Host *shost)
6444{
6445 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6446
6447 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6448}
6449
a55b2d21 6450static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6451 .error_detected = qla2xxx_pci_error_detected,
6452 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6453 .slot_reset = qla2xxx_pci_slot_reset,
6454 .resume = qla2xxx_pci_resume,
6455};
6456
5433383e 6457static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6458 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6459 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6460 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6461 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6462 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6463 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6464 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6465 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6466 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6467 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6468 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6469 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6470 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6471 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6472 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6473 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6474 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6475 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6476 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6477 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6478 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6479 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6480 { 0 },
6481};
6482MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6483
fca29703 6484static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6485 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6486 .driver = {
6487 .owner = THIS_MODULE,
6488 },
fca29703 6489 .id_table = qla2xxx_pci_tbl,
7ee61397 6490 .probe = qla2x00_probe_one,
4c993f76 6491 .remove = qla2x00_remove_one,
e30d1756 6492 .shutdown = qla2x00_shutdown,
14e660e6 6493 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6494};
6495
75ef9de1 6496static const struct file_operations apidev_fops = {
6a03b4cd 6497 .owner = THIS_MODULE,
6038f373 6498 .llseek = noop_llseek,
6a03b4cd
HZ		 6499};
6500
1da177e4
LT		 6501/**
6502 * qla2x00_module_init - Module initialization.
6503 **/
6504static int __init
6505qla2x00_module_init(void)
6506{
fca29703
AV		 6507 int ret = 0;
6508
1da177e4 6509 /* Allocate cache for SRBs. */
354d6b21 6510 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6511 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6512 if (srb_cachep == NULL) {
7c3df132
SK		 6513 ql_log(ql_log_fatal, NULL, 0x0001,
6514 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6515 return -ENOMEM;
6516 }
6517
2d70c103
NB		 6518 /* Initialize target kmem_cache and mem_pools */
6519 ret = qlt_init();
6520 if (ret < 0) {
6521 kmem_cache_destroy(srb_cachep);
6522 return ret;
6523 } else if (ret > 0) {
6524 /*
6525 * If initiator mode is explictly disabled by qlt_init(),
6526 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6527 * performing scsi_scan_target() during LOOP UP event.
6528 */
6529 qla2xxx_transport_functions.disable_target_scan = 1;
6530 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6531 }
6532
1da177e4
LT		 6533 /* Derive version string. */
6534 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6535 if (ql2xextended_error_logging)
0181944f
AV		 6536 strcat(qla2x00_version_str, "-debug");
6537
1c97a12a
AV		 6538 qla2xxx_transport_template =
6539 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6540 if (!qla2xxx_transport_template) {
6541 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6542 ql_log(ql_log_fatal, NULL, 0x0002,
6543 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6544 qlt_exit();
1da177e4 6545 return -ENODEV;
2c3dfe3f 6546 }
6a03b4cd
HZ		 6547
6548 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6549 if (apidev_major < 0) {
7c3df132
SK		 6550 ql_log(ql_log_fatal, NULL, 0x0003,
6551 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6552 }
6553
2c3dfe3f
SJ		 6554 qla2xxx_transport_vport_template =
6555 fc_attach_transport(&qla2xxx_transport_vport_functions);
6556 if (!qla2xxx_transport_vport_template) {
6557 kmem_cache_destroy(srb_cachep);
2d70c103 6558 qlt_exit();
2c3dfe3f 6559 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6560 ql_log(ql_log_fatal, NULL, 0x0004,
6561 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6562 return -ENODEV;
2c3dfe3f 6563 }
7c3df132
SK		 6564 ql_log(ql_log_info, NULL, 0x0005,
6565 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6566 qla2x00_version_str);
7ee61397 6567 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6568 if (ret) {
6569 kmem_cache_destroy(srb_cachep);
2d70c103 6570 qlt_exit();
fca29703 6571 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6572 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6573 ql_log(ql_log_fatal, NULL, 0x0006,
6574 "pci_register_driver failed...ret=%d Failing load!.\n",
6575 ret);
fca29703
AV		 6576 }
6577 return ret;
1da177e4
LT		 6578}
6579
6580/**
6581 * qla2x00_module_exit - Module cleanup.
6582 **/
6583static void __exit
6584qla2x00_module_exit(void)
6585{
6a03b4cd 6586 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6587 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6588 qla2x00_release_firmware();
354d6b21 6589 kmem_cache_destroy(srb_cachep);
2d70c103 6590 qlt_exit();
a9083016
GM		 6591 if (ctx_cachep)
6592 kmem_cache_destroy(ctx_cachep);
1da177e4 6593 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6594 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6595}
6596
6597module_init(qla2x00_module_init);
6598module_exit(qla2x00_module_exit);
6599
6600MODULE_AUTHOR("QLogic Corporation");
6601MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6602MODULE_LICENSE("GPL");
6603MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6604MODULE_FIRMWARE(FW_FILE_ISP21XX);
6605MODULE_FIRMWARE(FW_FILE_ISP22XX);
6606MODULE_FIRMWARE(FW_FILE_ISP2300);
6607MODULE_FIRMWARE(FW_FILE_ISP2322);
6608MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6609MODULE_FIRMWARE(FW_FILE_ISP25XX);
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