]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/scsi/qla2xxx/qla_os.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
scsi: qla2xxx: use shadow register for ISP27XX
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
99e1b683
QT		 227int ql2xexchoffld = 1024;
228module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 229MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 230 "Number of target exchanges.");
231
232int ql2xiniexchg = 1024;
233module_param(ql2xiniexchg, uint, 0644);
234MODULE_PARM_DESC(ql2xiniexchg,
235 "Number of initiator exchanges.");
2f56a7f1 236
f198cafa
HM		 237int ql2xfwholdabts = 0;
238module_param(ql2xfwholdabts, int, S_IRUGO);
239MODULE_PARM_DESC(ql2xfwholdabts,
240 "Allow FW to hold status IOCB until ABTS rsp received. "
241 "0 (Default) Do not set fw option. "
242 "1 - Set fw option to hold ABTS.");
243
41dc529a
QT		 244int ql2xmvasynctoatio = 1;
245module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
246MODULE_PARM_DESC(ql2xmvasynctoatio,
247 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
248 "0 (Default). Do not move IOCBs"
249 "1 - Move IOCBs.");
250
1da177e4 251/*
fa2a1ce5 252 * SCSI host template entry points
1da177e4
LT		 253 */
254static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 255static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 256static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
257static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 258static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 259static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 260static int qla2xxx_eh_abort(struct scsi_cmnd *);
261static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 262static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 263static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
264static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 265
1a2fbf18 266static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 267static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 268static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 269static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 270
a5326f86 271struct scsi_host_template qla2xxx_driver_template = {
1da177e4 272 .module = THIS_MODULE,
cb63067a 273 .name = QLA2XXX_DRIVER_NAME,
a5326f86 274 .queuecommand = qla2xxx_queuecommand,
fca29703 275
b6a05c82 276 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 277 .eh_abort_handler = qla2xxx_eh_abort,
278 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 279 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 280 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
281 .eh_host_reset_handler = qla2xxx_eh_host_reset,
282
283 .slave_configure = qla2xxx_slave_configure,
284
285 .slave_alloc = qla2xxx_slave_alloc,
286 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 287 .scan_finished = qla2xxx_scan_finished,
288 .scan_start = qla2xxx_scan_start,
db5ed4df 289 .change_queue_depth = scsi_change_queue_depth,
5601236b 290 .map_queues = qla2xxx_map_queues,
fca29703
AV		 291 .this_id = -1,
292 .cmd_per_lun = 3,
293 .use_clustering = ENABLE_CLUSTERING,
294 .sg_tablesize = SG_ALL,
295
296 .max_sectors = 0xFFFF,
afb046e2 297 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 298
299 .supported_mode = MODE_INITIATOR,
c40ecc12 300 .track_queue_depth = 1,
fca29703
AV		 301};
302
1da177e4 303static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 304struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 305
1da177e4
LT		 306/* TODO Convert to inlines
307 *
308 * Timer routines
309 */
1da177e4 310
2c3dfe3f 311__inline__ void
e315cd28 312qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 313{
e315cd28
AC		 314 init_timer(&vha->timer);
315 vha->timer.expires = jiffies + interval * HZ;
316 vha->timer.data = (unsigned long)vha;
317 vha->timer.function = (void (*)(unsigned long))func;
318 add_timer(&vha->timer);
319 vha->timer_active = 1;
1da177e4
LT		 320}
321
322static inline void
e315cd28 323qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 324{
a9083016 325 /* Currently used for 82XX only. */
7c3df132
SK		 326 if (vha->device_flags & DFLG_DEV_FAILED) {
327 ql_dbg(ql_dbg_timer, vha, 0x600d,
328 "Device in a failed state, returning.\n");
a9083016 329 return;
7c3df132 330 }
a9083016 331
e315cd28 332 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 333}
334
a824ebb3 335static __inline__ void
e315cd28 336qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 337{
e315cd28
AC		 338 del_timer_sync(&vha->timer);
339 vha->timer_active = 0;
1da177e4
LT		 340}
341
1da177e4
LT		 342static int qla2x00_do_dpc(void *data);
343
344static void qla2x00_rst_aen(scsi_qla_host_t *);
345
73208dfd
AC		 346static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
347 struct req_que **, struct rsp_que **);
e30d1756 348static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 349static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 350int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
351 struct qla_qpair *qpair);
1da177e4 352
1da177e4 353/* -------------------------------------------------------------------------- */
9a347ff4
CD		 354static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
355 struct rsp_que *rsp)
73208dfd 356{
7c3df132 357 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 358 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 359 GFP_KERNEL);
360 if (!ha->req_q_map) {
7c3df132
SK		 361 ql_log(ql_log_fatal, vha, 0x003b,
362 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 363 goto fail_req_map;
364 }
365
2afa19a9 366 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 367 GFP_KERNEL);
368 if (!ha->rsp_q_map) {
7c3df132
SK		 369 ql_log(ql_log_fatal, vha, 0x003c,
370 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 371 goto fail_rsp_map;
372 }
d7459527 373
e326d22a
QT		 374 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
375 if (ha->base_qpair == NULL) {
376 ql_log(ql_log_warn, vha, 0x00e0,
377 "Failed to allocate base queue pair memory.\n");
378 goto fail_base_qpair;
379 }
380
381 rsp->qpair = ha->base_qpair;
382 rsp->req = req;
383 ha->base_qpair->req = req;
384 ha->base_qpair->rsp = rsp;
385 ha->base_qpair->vha = vha;
386 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
af7bb382 387 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d65237c7 388 /* init qpair to this cpu. Will adjust at run time. */
e326d22a
QT		 389 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
390 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
7c3f8fd1 391 ha->base_qpair->enable_class_2 = ql2xenableclass2;
e326d22a
QT		 392 qla_cpu_update(rsp->qpair, smp_processor_id());
393
d7459527
MH		 394 if (ql2xmqsupport && ha->max_qpairs) {
395 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
396 GFP_KERNEL);
397 if (!ha->queue_pair_map) {
398 ql_log(ql_log_fatal, vha, 0x0180,
399 "Unable to allocate memory for queue pair ptrs.\n");
400 goto fail_qpair_map;
401 }
d7459527
MH		 402 }
403
9a347ff4
CD		 404 /*
405 * Make sure we record at least the request and response queue zero in
406 * case we need to free them if part of the probe fails.
407 */
408 ha->rsp_q_map[0] = rsp;
409 ha->req_q_map[0] = req;
73208dfd
AC		 410 set_bit(0, ha->rsp_qid_map);
411 set_bit(0, ha->req_qid_map);
412 return 1;
413
d7459527 414fail_qpair_map:
82de802a
QT		 415 kfree(ha->base_qpair);
416 ha->base_qpair = NULL;
417fail_base_qpair:
d7459527
MH		 418 kfree(ha->rsp_q_map);
419 ha->rsp_q_map = NULL;
73208dfd
AC		 420fail_rsp_map:
421 kfree(ha->req_q_map);
422 ha->req_q_map = NULL;
423fail_req_map:
424 return -ENOMEM;
425}
426
2afa19a9 427static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 428{
8ae6d9c7
GM		 429 if (IS_QLAFX00(ha)) {
430 if (req && req->ring_fx00)
431 dma_free_coherent(&ha->pdev->dev,
432 (req->length_fx00 + 1) * sizeof(request_t),
433 req->ring_fx00, req->dma_fx00);
434 } else if (req && req->ring)
73208dfd
AC		 435 dma_free_coherent(&ha->pdev->dev,
436 (req->length + 1) * sizeof(request_t),
437 req->ring, req->dma);
438
8d93f550
CD		 439 if (req)
440 kfree(req->outstanding_cmds);
441
73208dfd 442 kfree(req);
73208dfd
AC		 443}
444
2afa19a9
AC		 445static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
446{
8ae6d9c7
GM		 447 if (IS_QLAFX00(ha)) {
448 if (rsp && rsp->ring)
449 dma_free_coherent(&ha->pdev->dev,
450 (rsp->length_fx00 + 1) * sizeof(request_t),
451 rsp->ring_fx00, rsp->dma_fx00);
452 } else if (rsp && rsp->ring) {
2afa19a9
AC		 453 dma_free_coherent(&ha->pdev->dev,
454 (rsp->length + 1) * sizeof(response_t),
455 rsp->ring, rsp->dma);
8ae6d9c7 456 }
2afa19a9 457 kfree(rsp);
2afa19a9
AC		 458}
459
73208dfd
AC		 460static void qla2x00_free_queues(struct qla_hw_data *ha)
461{
462 struct req_que *req;
463 struct rsp_que *rsp;
464 int cnt;
093df737 465 unsigned long flags;
73208dfd 466
82de802a
QT		 467 if (ha->queue_pair_map) {
468 kfree(ha->queue_pair_map);
469 ha->queue_pair_map = NULL;
470 }
471 if (ha->base_qpair) {
472 kfree(ha->base_qpair);
473 ha->base_qpair = NULL;
474 }
475
093df737 476 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 477 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 478 if (!test_bit(cnt, ha->req_qid_map))
479 continue;
480
73208dfd 481 req = ha->req_q_map[cnt];
093df737
QT		 482 clear_bit(cnt, ha->req_qid_map);
483 ha->req_q_map[cnt] = NULL;
484
485 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 486 qla2x00_free_req_que(ha, req);
093df737 487 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 488 }
093df737
QT		 489 spin_unlock_irqrestore(&ha->hardware_lock, flags);
490
73208dfd
AC		 491 kfree(ha->req_q_map);
492 ha->req_q_map = NULL;
2afa19a9 493
093df737
QT		 494
495 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 496 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 497 if (!test_bit(cnt, ha->rsp_qid_map))
498 continue;
499
2afa19a9 500 rsp = ha->rsp_q_map[cnt];
c3c42394 501 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 502 ha->rsp_q_map[cnt] = NULL;
503 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 504 qla2x00_free_rsp_que(ha, rsp);
093df737 505 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 506 }
093df737
QT		 507 spin_unlock_irqrestore(&ha->hardware_lock, flags);
508
2afa19a9
AC		 509 kfree(ha->rsp_q_map);
510 ha->rsp_q_map = NULL;
73208dfd
AC		 511}
512
1da177e4 513static char *
e315cd28 514qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 515{
e315cd28 516 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 517 static char *pci_bus_modes[] = {
518 "33", "66", "100", "133",
519 };
520 uint16_t pci_bus;
521
522 strcpy(str, "PCI");
523 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
524 if (pci_bus) {
525 strcat(str, "-X (");
526 strcat(str, pci_bus_modes[pci_bus]);
527 } else {
528 pci_bus = (ha->pci_attr & BIT_8) >> 8;
529 strcat(str, " (");
530 strcat(str, pci_bus_modes[pci_bus]);
531 }
532 strcat(str, " MHz)");
533
534 return (str);
535}
536
fca29703 537static char *
e315cd28 538qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 539{
540 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 541 struct qla_hw_data *ha = vha->hw;
fca29703 542 uint32_t pci_bus;
fca29703 543
62a276f8 544 if (pci_is_pcie(ha->pdev)) {
fca29703 545 char lwstr[6];
62a276f8 546 uint32_t lstat, lspeed, lwidth;
fca29703 547
62a276f8
BH		 548 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
549 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
550 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 551
552 strcpy(str, "PCIe (");
49300af7
SK		 553 switch (lspeed) {
554 case 1:
c87a0d8c 555 strcat(str, "2.5GT/s ");
49300af7
SK		 556 break;
557 case 2:
c87a0d8c 558 strcat(str, "5.0GT/s ");
49300af7
SK		 559 break;
560 case 3:
561 strcat(str, "8.0GT/s ");
562 break;
563 default:
fca29703 564 strcat(str, "<unknown> ");
49300af7
SK		 565 break;
566 }
fca29703
AV		 567 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
568 strcat(str, lwstr);
569
570 return str;
571 }
572
573 strcpy(str, "PCI");
574 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
575 if (pci_bus == 0 || pci_bus == 8) {
576 strcat(str, " (");
577 strcat(str, pci_bus_modes[pci_bus >> 3]);
578 } else {
579 strcat(str, "-X ");
580 if (pci_bus & BIT_2)
581 strcat(str, "Mode 2");
582 else
583 strcat(str, "Mode 1");
584 strcat(str, " (");
585 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
586 }
587 strcat(str, " MHz)");
588
589 return str;
590}
591
e5f82ab8 592static char *
df57caba 593qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 594{
595 char un_str[10];
e315cd28 596 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 597
df57caba
HM		 598 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
599 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 600
601 if (ha->fw_attributes & BIT_9) {
602 strcat(str, "FLX");
603 return (str);
604 }
605
606 switch (ha->fw_attributes & 0xFF) {
607 case 0x7:
608 strcat(str, "EF");
609 break;
610 case 0x17:
611 strcat(str, "TP");
612 break;
613 case 0x37:
614 strcat(str, "IP");
615 break;
616 case 0x77:
617 strcat(str, "VI");
618 break;
619 default:
620 sprintf(un_str, "(%x)", ha->fw_attributes);
621 strcat(str, un_str);
622 break;
623 }
624 if (ha->fw_attributes & 0x100)
625 strcat(str, "X");
626
627 return (str);
628}
629
e5f82ab8 630static char *
df57caba 631qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 632{
e315cd28 633 struct qla_hw_data *ha = vha->hw;
f0883ac6 634
df57caba 635 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 636 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 637 return str;
fca29703
AV		 638}
639
9ba56b95 640void
25ff6af1 641qla2x00_sp_free_dma(void *ptr)
fca29703 642{
25ff6af1
JC		 643 srb_t *sp = ptr;
644 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 645 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 646 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 647
9ba56b95
GM		 648 if (sp->flags & SRB_DMA_VALID) {
649 scsi_dma_unmap(cmd);
650 sp->flags &= ~SRB_DMA_VALID;
7c3df132 651 }
fca29703 652
9ba56b95
GM		 653 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
654 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
655 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
656 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
657 }
658
d5ff0eed
JC		 659 if (!ctx)
660 goto end;
661
9ba56b95
GM		 662 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
663 /* List assured to be having elements */
d5ff0eed 664 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 665 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
666 }
667
668 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 669 struct crc_context *ctx0 = ctx;
670
671 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 672 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
673 }
674
675 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 676 struct ct6_dsd *ctx1 = ctx;
fca29703 677
9ba56b95 678 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 679 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 680 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
681 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
682 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
683 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 684 }
685
d5ff0eed 686end:
9ba56b95 687 CMD_SP(cmd) = NULL;
25ff6af1 688 qla2x00_rel_sp(sp);
9ba56b95
GM		 689}
690
d7459527 691void
25ff6af1 692qla2x00_sp_compl(void *ptr, int res)
9ba56b95 693{
25ff6af1 694 srb_t *sp = ptr;
9ba56b95
GM		 695 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
696
697 cmd->result = res;
698
699 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 700 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 701 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
702 sp, GET_CMD_SP(sp));
703 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 704 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 705 return;
706 }
707 if (!atomic_dec_and_test(&sp->ref_count))
708 return;
709
25ff6af1 710 qla2x00_sp_free_dma(sp);
9ba56b95 711 cmd->scsi_done(cmd);
fca29703
AV		 712}
713
d7459527 714void
25ff6af1 715qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 716{
717 srb_t *sp = (srb_t *)ptr;
718 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
719 struct qla_hw_data *ha = sp->fcport->vha->hw;
720 void *ctx = GET_CMD_CTX_SP(sp);
721
722 if (sp->flags & SRB_DMA_VALID) {
723 scsi_dma_unmap(cmd);
724 sp->flags &= ~SRB_DMA_VALID;
725 }
726
727 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
728 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
729 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
730 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
731 }
732
d5ff0eed
JC		 733 if (!ctx)
734 goto end;
735
d7459527
MH		 736 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
737 /* List assured to be having elements */
d5ff0eed 738 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 739 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
740 }
741
742 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 743 struct crc_context *ctx0 = ctx;
744
745 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 746 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
747 }
748
749 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 750 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 751 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
752 ctx1->fcp_cmnd_dma);
753 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
754 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
755 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
756 mempool_free(ctx1, ha->ctx_mempool);
757 }
d5ff0eed 758end:
d7459527
MH		 759 CMD_SP(cmd) = NULL;
760 qla2xxx_rel_qpair_sp(sp->qpair, sp);
761}
762
763void
25ff6af1 764qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 765{
25ff6af1 766 srb_t *sp = ptr;
d7459527
MH		 767 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
768
769 cmd->result = res;
770
771 if (atomic_read(&sp->ref_count) == 0) {
772 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
773 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
774 sp, GET_CMD_SP(sp));
775 if (ql2xextended_error_logging & ql_dbg_io)
776 WARN_ON(atomic_read(&sp->ref_count) == 0);
777 return;
778 }
779 if (!atomic_dec_and_test(&sp->ref_count))
780 return;
781
25ff6af1 782 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 783 cmd->scsi_done(cmd);
784}
785
8ae6d9c7
GM		 786/* If we are SP1 here, we need to still take and release the host_lock as SP1
787 * does not have the changes necessary to avoid taking host->host_lock.
788 */
1da177e4 789static int
f5e3e40b 790qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 791{
134ae078 792 scsi_qla_host_t *vha = shost_priv(host);
fca29703 793 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 794 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 795 struct qla_hw_data *ha = vha->hw;
796 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 797 srb_t *sp;
798 int rval;
5601236b
MH		 799 struct qla_qpair *qpair = NULL;
800 uint32_t tag;
801 uint16_t hwq;
fca29703 802
04dfaa53
MFO		 803 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
804 cmd->result = DID_NO_CONNECT << 16;
805 goto qc24_fail_command;
806 }
807
5601236b
MH		 808 if (ha->mqenable) {
809 if (shost_use_blk_mq(vha->host)) {
810 tag = blk_mq_unique_tag(cmd->request);
811 hwq = blk_mq_unique_tag_to_hwq(tag);
812 qpair = ha->queue_pair_map[hwq];
813 } else if (vha->vp_idx && vha->qpair) {
814 qpair = vha->qpair;
815 }
816
817 if (qpair)
818 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 819 }
820
85880801 821 if (ha->flags.eeh_busy) {
7c3df132 822 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 823 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 824 "PCI Channel IO permanent failure, exiting "
825 "cmd=%p.\n", cmd);
b9b12f73 826 cmd->result = DID_NO_CONNECT << 16;
7c3df132 827 } else {
5f28d2d7 828 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 829 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 830 cmd->result = DID_REQUEUE << 16;
7c3df132 831 }
14e660e6
SJ		 832 goto qc24_fail_command;
833 }
834
19a7b4ae
JSEC		 835 rval = fc_remote_port_chkready(rport);
836 if (rval) {
837 cmd->result = rval;
5f28d2d7 838 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 839 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
840 cmd, rval);
fca29703
AV		 841 goto qc24_fail_command;
842 }
843
bad75002
AE		 844 if (!vha->flags.difdix_supported &&
845 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 846 ql_dbg(ql_dbg_io, vha, 0x3004,
847 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
848 cmd);
bad75002
AE		 849 cmd->result = DID_NO_CONNECT << 16;
850 goto qc24_fail_command;
851 }
aa651be8
CD		 852
853 if (!fcport) {
854 cmd->result = DID_NO_CONNECT << 16;
855 goto qc24_fail_command;
856 }
857
fca29703
AV		 858 if (atomic_read(&fcport->state) != FCS_ONLINE) {
859 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 860 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 861 ql_dbg(ql_dbg_io, vha, 0x3005,
862 "Returning DNC, fcport_state=%d loop_state=%d.\n",
863 atomic_read(&fcport->state),
864 atomic_read(&base_vha->loop_state));
fca29703
AV		 865 cmd->result = DID_NO_CONNECT << 16;
866 goto qc24_fail_command;
867 }
7b594131 868 goto qc24_target_busy;
fca29703
AV		 869 }
870
e05fe292
CD		 871 /*
872 * Return target busy if we've received a non-zero retry_delay_timer
873 * in a FCP_RSP.
874 */
975f7d46
BP		 875 if (fcport->retry_delay_timestamp == 0) {
876 /* retry delay not set */
877 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 878 fcport->retry_delay_timestamp = 0;
879 else
880 goto qc24_target_busy;
881
b00ee7d7 882 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 883 if (!sp)
f5e3e40b 884 goto qc24_host_busy;
fca29703 885
9ba56b95
GM		 886 sp->u.scmd.cmd = cmd;
887 sp->type = SRB_SCSI_CMD;
888 atomic_set(&sp->ref_count, 1);
889 CMD_SP(cmd) = (void *)sp;
890 sp->free = qla2x00_sp_free_dma;
891 sp->done = qla2x00_sp_compl;
892
e315cd28 893 rval = ha->isp_ops->start_scsi(sp);
7c3df132 894 if (rval != QLA_SUCCESS) {
53016ed3 895 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 896 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 897 goto qc24_host_busy_free_sp;
7c3df132 898 }
fca29703 899
fca29703
AV		 900 return 0;
901
902qc24_host_busy_free_sp:
25ff6af1 903 qla2x00_sp_free_dma(sp);
fca29703 904
f5e3e40b 905qc24_host_busy:
fca29703
AV		 906 return SCSI_MLQUEUE_HOST_BUSY;
907
7b594131
MC		 908qc24_target_busy:
909 return SCSI_MLQUEUE_TARGET_BUSY;
910
fca29703 911qc24_fail_command:
f5e3e40b 912 cmd->scsi_done(cmd);
fca29703
AV		 913
914 return 0;
915}
916
d7459527
MH		 917/* For MQ supported I/O */
918int
919qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
920 struct qla_qpair *qpair)
921{
922 scsi_qla_host_t *vha = shost_priv(host);
923 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
924 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
925 struct qla_hw_data *ha = vha->hw;
926 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
927 srb_t *sp;
928 int rval;
929
930 rval = fc_remote_port_chkready(rport);
931 if (rval) {
932 cmd->result = rval;
933 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
934 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
935 cmd, rval);
936 goto qc24_fail_command;
937 }
938
939 if (!fcport) {
940 cmd->result = DID_NO_CONNECT << 16;
941 goto qc24_fail_command;
942 }
943
944 if (atomic_read(&fcport->state) != FCS_ONLINE) {
945 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
946 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
947 ql_dbg(ql_dbg_io, vha, 0x3077,
948 "Returning DNC, fcport_state=%d loop_state=%d.\n",
949 atomic_read(&fcport->state),
950 atomic_read(&base_vha->loop_state));
951 cmd->result = DID_NO_CONNECT << 16;
952 goto qc24_fail_command;
953 }
954 goto qc24_target_busy;
955 }
956
957 /*
958 * Return target busy if we've received a non-zero retry_delay_timer
959 * in a FCP_RSP.
960 */
961 if (fcport->retry_delay_timestamp == 0) {
962 /* retry delay not set */
963 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
964 fcport->retry_delay_timestamp = 0;
965 else
966 goto qc24_target_busy;
967
968 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
969 if (!sp)
970 goto qc24_host_busy;
971
972 sp->u.scmd.cmd = cmd;
973 sp->type = SRB_SCSI_CMD;
974 atomic_set(&sp->ref_count, 1);
975 CMD_SP(cmd) = (void *)sp;
976 sp->free = qla2xxx_qpair_sp_free_dma;
977 sp->done = qla2xxx_qpair_sp_compl;
978 sp->qpair = qpair;
979
980 rval = ha->isp_ops->start_scsi_mq(sp);
981 if (rval != QLA_SUCCESS) {
982 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
983 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
984 if (rval == QLA_INTERFACE_ERROR)
985 goto qc24_fail_command;
986 goto qc24_host_busy_free_sp;
987 }
988
989 return 0;
990
991qc24_host_busy_free_sp:
25ff6af1 992 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 993
994qc24_host_busy:
995 return SCSI_MLQUEUE_HOST_BUSY;
996
997qc24_target_busy:
998 return SCSI_MLQUEUE_TARGET_BUSY;
999
1000qc24_fail_command:
1001 cmd->scsi_done(cmd);
1002
1003 return 0;
1004}
1005
1da177e4
LT		 1006/*
1007 * qla2x00_eh_wait_on_command
1008 * Waits for the command to be returned by the Firmware for some
1009 * max time.
1010 *
1011 * Input:
1da177e4 1012 * cmd = Scsi Command to wait on.
1da177e4
LT		 1013 *
1014 * Return:
1015 * Not Found : 0
1016 * Found : 1
1017 */
1018static int
e315cd28 1019qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1020{
fe74c71f 1021#define ABORT_POLLING_PERIOD 1000
478c3b03 1022#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1023 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1024 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1025 struct qla_hw_data *ha = vha->hw;
f4f051eb 1026 int ret = QLA_SUCCESS;
1da177e4 1027
85880801 1028 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1029 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1030 "Return:eh_wait.\n");
85880801
AV		 1031 return ret;
1032 }
1033
d970432c 1034 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1035 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1036 }
1037 if (CMD_SP(cmd))
1038 ret = QLA_FUNCTION_FAILED;
1da177e4 1039
f4f051eb 1040 return ret;
1da177e4
LT		 1041}
1042
1043/*
1044 * qla2x00_wait_for_hba_online
fa2a1ce5 1045 * Wait till the HBA is online after going through
1da177e4
LT		 1046 * <= MAX_RETRIES_OF_ISP_ABORT or
1047 * finally HBA is disabled ie marked offline
1048 *
1049 * Input:
1050 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1051 *
1052 * Note:
1da177e4
LT		 1053 * Does context switching-Release SPIN_LOCK
1054 * (if any) before calling this routine.
1055 *
1056 * Return:
1057 * Success (Adapter is online) : 0
1058 * Failed (Adapter is offline/disabled) : 1
1059 */
854165f4 1060int
e315cd28 1061qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1062{
fca29703
AV		 1063 int return_status;
1064 unsigned long wait_online;
e315cd28
AC		 1065 struct qla_hw_data *ha = vha->hw;
1066 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1067
fa2a1ce5 1068 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1069 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1070 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1071 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1072 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1073
1074 msleep(1000);
1075 }
e315cd28 1076 if (base_vha->flags.online)
fa2a1ce5 1077 return_status = QLA_SUCCESS;
1da177e4
LT		 1078 else
1079 return_status = QLA_FUNCTION_FAILED;
1080
1da177e4
LT		 1081 return (return_status);
1082}
1083
726b8548
QT		 1084static inline int test_fcport_count(scsi_qla_host_t *vha)
1085{
1086 struct qla_hw_data *ha = vha->hw;
1087 unsigned long flags;
1088 int res;
1089
1090 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1091 ql_dbg(ql_dbg_init, vha, 0x00ec,
1092 "tgt %p, fcport_count=%d\n",
1093 vha, vha->fcport_count);
726b8548
QT		 1094 res = (vha->fcport_count == 0);
1095 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1096
1097 return res;
1098}
1099
1100/*
1101 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1102 * it has dependency on UNLOADING flag to stop device discovery
1103 */
1104static void
1105qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1106{
1107 qla2x00_mark_all_devices_lost(vha, 0);
1108
1109 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1110}
1111
86fbee86 1112/*
638a1a01
SC		 1113 * qla2x00_wait_for_hba_ready
1114 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1115 *
1116 * Input:
1117 * ha - pointer to host adapter structure
1118 *
1119 * Note:
1120 * Does context switching-Release SPIN_LOCK
1121 * (if any) before calling this routine.
1122 *
86fbee86 1123 */
638a1a01
SC		 1124static void
1125qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1126{
86fbee86 1127 struct qla_hw_data *ha = vha->hw;
783e0dc4 1128 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1129
1d483901
DC		 1130 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1131 ha->flags.mbox_busy) ||
1132 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1133 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1134 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1135 break;
86fbee86 1136 msleep(1000);
783e0dc4 1137 }
86fbee86
LC		 1138}
1139
2533cf67
LC		 1140int
1141qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1142{
1143 int return_status;
1144 unsigned long wait_reset;
1145 struct qla_hw_data *ha = vha->hw;
1146 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1147
1148 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1149 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1150 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1151 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1152 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1153
1154 msleep(1000);
1155
1156 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1157 ha->flags.chip_reset_done)
1158 break;
1159 }
1160 if (ha->flags.chip_reset_done)
1161 return_status = QLA_SUCCESS;
1162 else
1163 return_status = QLA_FUNCTION_FAILED;
1164
1165 return return_status;
1166}
1167
083a469d
GM		 1168static void
1169sp_get(struct srb *sp)
1170{
1171 atomic_inc(&sp->ref_count);
1172}
1173
a465537a
SC		 1174#define ISP_REG_DISCONNECT 0xffffffffU
1175/**************************************************************************
1176* qla2x00_isp_reg_stat
1177*
1178* Description:
1179* Read the host status register of ISP before aborting the command.
1180*
1181* Input:
1182* ha = pointer to host adapter structure.
1183*
1184*
1185* Returns:
1186* Either true or false.
1187*
1188* Note: Return true if there is register disconnect.
1189**************************************************************************/
1190static inline
1191uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1192{
1193 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1194 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1195
bf6061b1
SC		 1196 if (IS_P3P_TYPE(ha))
1197 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1198 else
1199 return ((RD_REG_DWORD(&reg->host_status)) ==
1200 ISP_REG_DISCONNECT);
a465537a
SC		 1201}
1202
1da177e4
LT		 1203/**************************************************************************
1204* qla2xxx_eh_abort
1205*
1206* Description:
1207* The abort function will abort the specified command.
1208*
1209* Input:
1210* cmd = Linux SCSI command packet to be aborted.
1211*
1212* Returns:
1213* Either SUCCESS or FAILED.
1214*
1215* Note:
2ea00202 1216* Only return FAILED if command not returned by firmware.
1da177e4 1217**************************************************************************/
e5f82ab8 1218static int
1da177e4
LT		 1219qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1220{
e315cd28 1221 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1222 srb_t *sp;
4e98d3b8 1223 int ret;
9cb78c16
HR		 1224 unsigned int id;
1225 uint64_t lun;
18e144d3 1226 unsigned long flags;
f934c9d0 1227 int rval, wait = 0;
e315cd28 1228 struct qla_hw_data *ha = vha->hw;
1da177e4 1229
a465537a
SC		 1230 if (qla2x00_isp_reg_stat(ha)) {
1231 ql_log(ql_log_info, vha, 0x8042,
1232 "PCI/Register disconnect, exiting.\n");
1233 return FAILED;
1234 }
f4f051eb 1235 if (!CMD_SP(cmd))
2ea00202 1236 return SUCCESS;
1da177e4 1237
4e98d3b8
AV		 1238 ret = fc_block_scsi_eh(cmd);
1239 if (ret != 0)
1240 return ret;
1241 ret = SUCCESS;
1242
f4f051eb
AV		 1243 id = cmd->device->id;
1244 lun = cmd->device->lun;
1da177e4 1245
e315cd28 1246 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1247 sp = (srb_t *) CMD_SP(cmd);
1248 if (!sp) {
1249 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1250 return SUCCESS;
1251 }
1da177e4 1252
7c3df132 1253 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1254 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1255 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1256
170babc3
MC		 1257 /* Get a reference to the sp and drop the lock.*/
1258 sp_get(sp);
083a469d 1259
e315cd28 1260 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1261 rval = ha->isp_ops->abort_command(sp);
1262 if (rval) {
96219424 1263 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1264 ret = SUCCESS;
96219424 1265 else
f934c9d0
CD		 1266 ret = FAILED;
1267
7c3df132 1268 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1269 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1270 } else {
7c3df132 1271 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1272 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1273 wait = 1;
1274 }
75942064
SK		 1275
1276 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1277 sp->done(sp, 0);
75942064 1278 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1279
bc91ade9
CD		 1280 /* Did the command return during mailbox execution? */
1281 if (ret == FAILED && !CMD_SP(cmd))
1282 ret = SUCCESS;
1283
f4f051eb 1284 /* Wait for the command to be returned. */
2ea00202 1285 if (wait) {
e315cd28 1286 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1287 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1288 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1289 ret = FAILED;
f4f051eb 1290 }
1da177e4 1291 }
1da177e4 1292
7c3df132 1293 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1294 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1295 vha->host_no, id, lun, wait, ret);
1da177e4 1296
f4f051eb
AV		 1297 return ret;
1298}
1da177e4 1299
4d78c973 1300int
e315cd28 1301qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1302 uint64_t l, enum nexus_wait_type type)
f4f051eb 1303{
17d98630 1304 int cnt, match, status;
18e144d3 1305 unsigned long flags;
e315cd28 1306 struct qla_hw_data *ha = vha->hw;
73208dfd 1307 struct req_que *req;
4d78c973 1308 srb_t *sp;
9ba56b95 1309 struct scsi_cmnd *cmd;
1da177e4 1310
523ec773 1311 status = QLA_SUCCESS;
17d98630 1312
e315cd28 1313 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1314 req = vha->req;
17d98630 1315 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1316 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1317 sp = req->outstanding_cmds[cnt];
1318 if (!sp)
523ec773 1319 continue;
9ba56b95 1320 if (sp->type != SRB_SCSI_CMD)
cf53b069 1321 continue;
25ff6af1 1322 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1323 continue;
1324 match = 0;
9ba56b95 1325 cmd = GET_CMD_SP(sp);
17d98630
AC		 1326 switch (type) {
1327 case WAIT_HOST:
1328 match = 1;
1329 break;
1330 case WAIT_TARGET:
9ba56b95 1331 match = cmd->device->id == t;
17d98630
AC		 1332 break;
1333 case WAIT_LUN:
9ba56b95
GM		 1334 match = (cmd->device->id == t &&
1335 cmd->device->lun == l);
17d98630 1336 break;
73208dfd 1337 }
17d98630
AC		 1338 if (!match)
1339 continue;
1340
1341 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1342 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1343 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1344 }
e315cd28 1345 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1346
1347 return status;
1da177e4
LT		 1348}
1349
523ec773
AV		 1350static char *reset_errors[] = {
1351 "HBA not online",
1352 "HBA not ready",
1353 "Task management failed",
1354 "Waiting for command completions",
1355};
1da177e4 1356
e5f82ab8 1357static int
523ec773 1358__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1359 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1360{
e315cd28 1361 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1362 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1363 int err;
1da177e4 1364
7c3df132 1365 if (!fcport) {
523ec773 1366 return FAILED;
7c3df132 1367 }
1da177e4 1368
4e98d3b8
AV		 1369 err = fc_block_scsi_eh(cmd);
1370 if (err != 0)
1371 return err;
1372
7c3df132 1373 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1374 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1375 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1376
523ec773 1377 err = 0;
7c3df132
SK		 1378 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1379 ql_log(ql_log_warn, vha, 0x800a,
1380 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1381 goto eh_reset_failed;
7c3df132 1382 }
523ec773 1383 err = 2;
2afa19a9 1384 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1385 != QLA_SUCCESS) {
1386 ql_log(ql_log_warn, vha, 0x800c,
1387 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1388 goto eh_reset_failed;
7c3df132 1389 }
523ec773 1390 err = 3;
e315cd28 1391 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1392 cmd->device->lun, type) != QLA_SUCCESS) {
1393 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1394 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1395 goto eh_reset_failed;
7c3df132 1396 }
523ec773 1397
7c3df132 1398 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1399 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1400 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1401
1402 return SUCCESS;
1403
4d78c973 1404eh_reset_failed:
7c3df132 1405 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1406 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1407 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1408 cmd);
523ec773
AV		 1409 return FAILED;
1410}
1da177e4 1411
523ec773
AV		 1412static int
1413qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1414{
e315cd28
AC		 1415 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1416 struct qla_hw_data *ha = vha->hw;
1da177e4 1417
a465537a
SC		 1418 if (qla2x00_isp_reg_stat(ha)) {
1419 ql_log(ql_log_info, vha, 0x803e,
1420 "PCI/Register disconnect, exiting.\n");
1421 return FAILED;
1422 }
1423
523ec773
AV		 1424 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1425 ha->isp_ops->lun_reset);
1da177e4
LT		 1426}
1427
1da177e4 1428static int
523ec773 1429qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1430{
e315cd28
AC		 1431 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1432 struct qla_hw_data *ha = vha->hw;
1da177e4 1433
a465537a
SC		 1434 if (qla2x00_isp_reg_stat(ha)) {
1435 ql_log(ql_log_info, vha, 0x803f,
1436 "PCI/Register disconnect, exiting.\n");
1437 return FAILED;
1438 }
1439
523ec773
AV		 1440 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1441 ha->isp_ops->target_reset);
1da177e4
LT		 1442}
1443
1da177e4
LT		 1444/**************************************************************************
1445* qla2xxx_eh_bus_reset
1446*
1447* Description:
1448* The bus reset function will reset the bus and abort any executing
1449* commands.
1450*
1451* Input:
1452* cmd = Linux SCSI command packet of the command that cause the
1453* bus reset.
1454*
1455* Returns:
1456* SUCCESS/FAILURE (defined as macro in scsi.h).
1457*
1458**************************************************************************/
e5f82ab8 1459static int
1da177e4
LT		 1460qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1461{
e315cd28 1462 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1463 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1464 int ret = FAILED;
9cb78c16
HR		 1465 unsigned int id;
1466 uint64_t lun;
a465537a
SC		 1467 struct qla_hw_data *ha = vha->hw;
1468
1469 if (qla2x00_isp_reg_stat(ha)) {
1470 ql_log(ql_log_info, vha, 0x8040,
1471 "PCI/Register disconnect, exiting.\n");
1472 return FAILED;
1473 }
f4f051eb 1474
f4f051eb
AV		 1475 id = cmd->device->id;
1476 lun = cmd->device->lun;
1da177e4 1477
7c3df132 1478 if (!fcport) {
f4f051eb 1479 return ret;
7c3df132 1480 }
1da177e4 1481
4e98d3b8
AV		 1482 ret = fc_block_scsi_eh(cmd);
1483 if (ret != 0)
1484 return ret;
1485 ret = FAILED;
1486
7c3df132 1487 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1488 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1489
e315cd28 1490 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1491 ql_log(ql_log_fatal, vha, 0x8013,
1492 "Wait for hba online failed board disabled.\n");
f4f051eb 1493 goto eh_bus_reset_done;
1da177e4
LT		 1494 }
1495
ad537689
SK		 1496 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1497 ret = SUCCESS;
1498
f4f051eb
AV		 1499 if (ret == FAILED)
1500 goto eh_bus_reset_done;
1da177e4 1501
9a41a62b 1502 /* Flush outstanding commands. */
4d78c973 1503 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1504 QLA_SUCCESS) {
1505 ql_log(ql_log_warn, vha, 0x8014,
1506 "Wait for pending commands failed.\n");
9a41a62b 1507 ret = FAILED;
7c3df132 1508 }
1da177e4 1509
f4f051eb 1510eh_bus_reset_done:
7c3df132 1511 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1512 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1513 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1514
f4f051eb 1515 return ret;
1da177e4
LT		 1516}
1517
1518/**************************************************************************
1519* qla2xxx_eh_host_reset
1520*
1521* Description:
1522* The reset function will reset the Adapter.
1523*
1524* Input:
1525* cmd = Linux SCSI command packet of the command that cause the
1526* adapter reset.
1527*
1528* Returns:
1529* Either SUCCESS or FAILED.
1530*
1531* Note:
1532**************************************************************************/
e5f82ab8 1533static int
1da177e4
LT		 1534qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1535{
e315cd28 1536 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1537 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1538 int ret = FAILED;
9cb78c16
HR		 1539 unsigned int id;
1540 uint64_t lun;
e315cd28 1541 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1542
a465537a
SC		 1543 if (qla2x00_isp_reg_stat(ha)) {
1544 ql_log(ql_log_info, vha, 0x8041,
1545 "PCI/Register disconnect, exiting.\n");
1546 schedule_work(&ha->board_disable);
1547 return SUCCESS;
1548 }
1549
f4f051eb
AV		 1550 id = cmd->device->id;
1551 lun = cmd->device->lun;
f4f051eb 1552
7c3df132 1553 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1554 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1555
63ee7072
CD		 1556 /*
1557 * No point in issuing another reset if one is active. Also do not
1558 * attempt a reset if we are updating flash.
1559 */
1560 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1561 goto eh_host_reset_lock;
1da177e4 1562
e315cd28
AC		 1563 if (vha != base_vha) {
1564 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1565 goto eh_host_reset_lock;
e315cd28 1566 } else {
7ec0effd 1567 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1568 if (!qla82xx_fcoe_ctx_reset(vha)) {
1569 /* Ctx reset success */
1570 ret = SUCCESS;
1571 goto eh_host_reset_lock;
1572 }
1573 /* fall thru if ctx reset failed */
1574 }
68ca949c
AC		 1575 if (ha->wq)
1576 flush_workqueue(ha->wq);
1577
e315cd28 1578 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1579 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1580 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1581 /* failed. schedule dpc to try */
1582 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1583
7c3df132
SK		 1584 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1585 ql_log(ql_log_warn, vha, 0x802a,
1586 "wait for hba online failed.\n");
e315cd28 1587 goto eh_host_reset_lock;
7c3df132 1588 }
e315cd28
AC		 1589 }
1590 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1591 }
1da177e4 1592
e315cd28 1593 /* Waiting for command to be returned to OS.*/
4d78c973 1594 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1595 QLA_SUCCESS)
f4f051eb 1596 ret = SUCCESS;
1da177e4 1597
f4f051eb 1598eh_host_reset_lock:
cfb0919c 1599 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1600 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1601 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1602
f4f051eb
AV		 1603 return ret;
1604}
1da177e4
LT		 1605
1606/*
1607* qla2x00_loop_reset
1608* Issue loop reset.
1609*
1610* Input:
1611* ha = adapter block pointer.
1612*
1613* Returns:
1614* 0 = success
1615*/
a4722cf2 1616int
e315cd28 1617qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1618{
0c8c39af 1619 int ret;
bdf79621 1620 struct fc_port *fcport;
e315cd28 1621 struct qla_hw_data *ha = vha->hw;
1da177e4 1622
5854771e
AB		 1623 if (IS_QLAFX00(ha)) {
1624 return qlafx00_loop_reset(vha);
1625 }
1626
f4c496c1 1627 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1628 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1629 if (fcport->port_type != FCT_TARGET)
1630 continue;
1631
1632 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1633 if (ret != QLA_SUCCESS) {
7c3df132 1634 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1635 "Bus Reset failed: Reset=%d "
7c3df132 1636 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1637 }
1638 }
1639 }
1640
8ae6d9c7 1641
6246b8a1 1642 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1643 atomic_set(&vha->loop_state, LOOP_DOWN);
1644 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1645 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1646 ret = qla2x00_full_login_lip(vha);
0c8c39af 1647 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1648 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1649 "full_login_lip=%d.\n", ret);
749af3d5 1650 }
0c8c39af
AV		 1651 }
1652
0d6e61bc 1653 if (ha->flags.enable_lip_reset) {
e315cd28 1654 ret = qla2x00_lip_reset(vha);
ad537689 1655 if (ret != QLA_SUCCESS)
7c3df132
SK		 1656 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1657 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1658 }
1659
1da177e4 1660 /* Issue marker command only when we are going to start the I/O */
e315cd28 1661 vha->marker_needed = 1;
1da177e4 1662
0c8c39af 1663 return QLA_SUCCESS;
1da177e4
LT		 1664}
1665
df4bf0bb 1666void
e315cd28 1667qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1668{
4cd3b6eb 1669 int que, cnt, status;
df4bf0bb
AV		 1670 unsigned long flags;
1671 srb_t *sp;
e315cd28 1672 struct qla_hw_data *ha = vha->hw;
73208dfd 1673 struct req_que *req;
c5419e26
QT		 1674 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1675 struct qla_tgt_cmd *cmd;
1676 uint8_t trace = 0;
c0cb4496 1677
df4bf0bb 1678 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1679 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1680 req = ha->req_q_map[que];
73208dfd
AC		 1681 if (!req)
1682 continue;
8d93f550
CD		 1683 if (!req->outstanding_cmds)
1684 continue;
1685 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1686 sp = req->outstanding_cmds[cnt];
e612d465 1687 if (sp) {
c5419e26
QT		 1688 req->outstanding_cmds[cnt] = NULL;
1689 if (sp->cmd_type == TYPE_SRB) {
1690 /*
1691 * Don't abort commands in adapter
1692 * during EEH recovery as it's not
1693 * accessible/responding.
c733ab35 1694 */
c5419e26
QT		 1695 if (GET_CMD_SP(sp) &&
1696 !ha->flags.eeh_busy &&
1697 (sp->type == SRB_SCSI_CMD)) {
1698 /*
1699 * Get a reference to the sp
1700 * and drop the lock. The
1701 * reference ensures this
1702 * sp->done() call and not the
1703 * call in qla2xxx_eh_abort()
1704 * ends the SCSI command (with
1705 * result 'res').
1706 */
1707 sp_get(sp);
1708 spin_unlock_irqrestore(
1709 &ha->hardware_lock, flags);
1710 status = qla2xxx_eh_abort(
1711 GET_CMD_SP(sp));
1712 spin_lock_irqsave(
1713 &ha->hardware_lock, flags);
1714 /*
1715 * Get rid of extra reference
1716 * if immediate exit from
1717 * ql2xxx_eh_abort
1718 */
1719 if (status == FAILED &&
1720 (qla2x00_isp_reg_stat(ha)))
1721 atomic_dec(
1722 &sp->ref_count);
1723 }
1724 sp->done(sp, res);
1725 } else {
1726 if (!vha->hw->tgt.tgt_ops || !tgt ||
1727 qla_ini_mode_enabled(vha)) {
1728 if (!trace)
1729 ql_dbg(ql_dbg_tgt_mgt,
1730 vha, 0xf003,
1731 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1732 vha->dpc_flags);
1733 continue;
1734 }
1735 cmd = (struct qla_tgt_cmd *)sp;
1736 qlt_abort_cmd_on_host_reset(cmd->vha,
1737 cmd);
c733ab35 1738 }
73208dfd 1739 }
df4bf0bb
AV		 1740 }
1741 }
1742 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1743}
1744
f4f051eb
AV		 1745static int
1746qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1747{
bdf79621 1748 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1749
19a7b4ae 1750 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1751 return -ENXIO;
bdf79621 1752
19a7b4ae 1753 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1754
f4f051eb
AV		 1755 return 0;
1756}
1da177e4 1757
f4f051eb
AV		 1758static int
1759qla2xxx_slave_configure(struct scsi_device *sdev)
1760{
e315cd28 1761 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1762 struct req_que *req = vha->req;
8482e118 1763
9e522cd8
AE		 1764 if (IS_T10_PI_CAPABLE(vha->hw))
1765 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1766
db5ed4df 1767 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1768 return 0;
1769}
1da177e4 1770
f4f051eb
AV		 1771static void
1772qla2xxx_slave_destroy(struct scsi_device *sdev)
1773{
1774 sdev->hostdata = NULL;
1da177e4
LT		 1775}
1776
1777/**
1778 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1779 * @ha: HA context
1780 *
1781 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1782 * supported addressing method.
1783 */
1784static void
53303c42 1785qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1786{
7524f9b9 1787 /* Assume a 32bit DMA mask. */
1da177e4 1788 ha->flags.enable_64bit_addressing = 0;
1da177e4 1789
6a35528a 1790 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1791 /* Any upper-dword bits set? */
1792 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1793 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1794 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1795 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1796 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1797 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1798 return;
1da177e4 1799 }
1da177e4 1800 }
7524f9b9 1801
284901a9
YH		 1802 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1803 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1804}
1805
fd34f556 1806static void
e315cd28 1807qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1808{
1809 unsigned long flags = 0;
1810 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1811
1812 spin_lock_irqsave(&ha->hardware_lock, flags);
1813 ha->interrupts_on = 1;
1814 /* enable risc and host interrupts */
1815 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1816 RD_REG_WORD(&reg->ictrl);
1817 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1818
1819}
1820
1821static void
e315cd28 1822qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1823{
1824 unsigned long flags = 0;
1825 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1826
1827 spin_lock_irqsave(&ha->hardware_lock, flags);
1828 ha->interrupts_on = 0;
1829 /* disable risc and host interrupts */
1830 WRT_REG_WORD(&reg->ictrl, 0);
1831 RD_REG_WORD(&reg->ictrl);
1832 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1833}
1834
1835static void
e315cd28 1836qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1837{
1838 unsigned long flags = 0;
1839 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1840
1841 spin_lock_irqsave(&ha->hardware_lock, flags);
1842 ha->interrupts_on = 1;
1843 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1844 RD_REG_DWORD(&reg->ictrl);
1845 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1846}
1847
1848static void
e315cd28 1849qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1850{
1851 unsigned long flags = 0;
1852 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1853
124f85e6
AV		 1854 if (IS_NOPOLLING_TYPE(ha))
1855 return;
fd34f556
AV		 1856 spin_lock_irqsave(&ha->hardware_lock, flags);
1857 ha->interrupts_on = 0;
1858 WRT_REG_DWORD(&reg->ictrl, 0);
1859 RD_REG_DWORD(&reg->ictrl);
1860 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1861}
1862
706f457d
GM		 1863static int
1864qla2x00_iospace_config(struct qla_hw_data *ha)
1865{
1866 resource_size_t pio;
1867 uint16_t msix;
706f457d 1868
706f457d
GM		 1869 if (pci_request_selected_regions(ha->pdev, ha->bars,
1870 QLA2XXX_DRIVER_NAME)) {
1871 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1872 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1873 pci_name(ha->pdev));
1874 goto iospace_error_exit;
1875 }
1876 if (!(ha->bars & 1))
1877 goto skip_pio;
1878
1879 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1880 pio = pci_resource_start(ha->pdev, 0);
1881 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1882 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1883 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1884 "Invalid pci I/O region size (%s).\n",
1885 pci_name(ha->pdev));
1886 pio = 0;
1887 }
1888 } else {
1889 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1890 "Region #0 no a PIO resource (%s).\n",
1891 pci_name(ha->pdev));
1892 pio = 0;
1893 }
1894 ha->pio_address = pio;
1895 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1896 "PIO address=%llu.\n",
1897 (unsigned long long)ha->pio_address);
1898
1899skip_pio:
1900 /* Use MMIO operations for all accesses. */
1901 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1902 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1903 "Region #1 not an MMIO resource (%s), aborting.\n",
1904 pci_name(ha->pdev));
1905 goto iospace_error_exit;
1906 }
1907 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1908 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1909 "Invalid PCI mem region size (%s), aborting.\n",
1910 pci_name(ha->pdev));
1911 goto iospace_error_exit;
1912 }
1913
1914 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1915 if (!ha->iobase) {
1916 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1917 "Cannot remap MMIO (%s), aborting.\n",
1918 pci_name(ha->pdev));
1919 goto iospace_error_exit;
1920 }
1921
1922 /* Determine queue resources */
1923 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1924 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1925 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1926 goto mqiobase_exit;
1927
1928 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1929 pci_resource_len(ha->pdev, 3));
1930 if (ha->mqiobase) {
1931 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1932 "MQIO Base=%p.\n", ha->mqiobase);
1933 /* Read MSIX vector size of the board */
1934 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1935 ha->msix_count = msix + 1;
706f457d 1936 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1937 /* MB interrupt uses 1 vector */
1938 ha->max_req_queues = ha->msix_count - 1;
1939 ha->max_rsp_queues = ha->max_req_queues;
1940 /* Queue pairs is the max value minus the base queue pair */
1941 ha->max_qpairs = ha->max_rsp_queues - 1;
1942 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1943 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1944
706f457d 1945 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1946 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1947 } else
1948 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1949 "BAR 3 not enabled.\n");
1950
1951mqiobase_exit:
706f457d 1952 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1953 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1954 return (0);
1955
1956iospace_error_exit:
1957 return (-ENOMEM);
1958}
1959
1960
6246b8a1
GM		 1961static int
1962qla83xx_iospace_config(struct qla_hw_data *ha)
1963{
1964 uint16_t msix;
6246b8a1
GM		 1965
1966 if (pci_request_selected_regions(ha->pdev, ha->bars,
1967 QLA2XXX_DRIVER_NAME)) {
1968 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1969 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1970 pci_name(ha->pdev));
1971
1972 goto iospace_error_exit;
1973 }
1974
1975 /* Use MMIO operations for all accesses. */
1976 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1977 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1978 "Invalid pci I/O region size (%s).\n",
1979 pci_name(ha->pdev));
1980 goto iospace_error_exit;
1981 }
1982 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1983 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1984 "Invalid PCI mem region size (%s), aborting\n",
1985 pci_name(ha->pdev));
1986 goto iospace_error_exit;
1987 }
1988
1989 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1990 if (!ha->iobase) {
1991 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1992 "Cannot remap MMIO (%s), aborting.\n",
1993 pci_name(ha->pdev));
1994 goto iospace_error_exit;
1995 }
1996
1997 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1998 /* 83XX 26XX always use MQ type access for queues
1999 * - mbar 2, a.k.a region 4 */
2000 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2001 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2002 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2003 pci_resource_len(ha->pdev, 4));
2004
2005 if (!ha->mqiobase) {
2006 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2007 "BAR2/region4 not enabled\n");
2008 goto mqiobase_exit;
2009 }
2010
2011 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2012 pci_resource_len(ha->pdev, 2));
2013 if (ha->msixbase) {
2014 /* Read MSIX vector size of the board */
2015 pci_read_config_word(ha->pdev,
2016 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2017 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2018 /*
2019 * By default, driver uses at least two msix vectors
2020 * (default & rspq)
2021 */
d7459527
MH		 2022 if (ql2xmqsupport) {
2023 /* MB interrupt uses 1 vector */
2024 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2025
2026 /* ATIOQ needs 1 vector. That's 1 less QPair */
2027 if (QLA_TGT_MODE_ENABLED())
2028 ha->max_req_queues--;
2029
d0d2c68b
MH		 2030 ha->max_rsp_queues = ha->max_req_queues;
2031
d7459527
MH		 2032 /* Queue pairs is the max value minus
2033 * the base queue pair */
2034 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2035 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2036 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2037 }
2038 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2039 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2040 } else
2041 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2042 "BAR 1 not enabled.\n");
2043
2044mqiobase_exit:
6246b8a1 2045 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2046 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2047 return 0;
2048
2049iospace_error_exit:
2050 return -ENOMEM;
2051}
2052
fd34f556
AV		 2053static struct isp_operations qla2100_isp_ops = {
2054 .pci_config = qla2100_pci_config,
2055 .reset_chip = qla2x00_reset_chip,
2056 .chip_diag = qla2x00_chip_diag,
2057 .config_rings = qla2x00_config_rings,
2058 .reset_adapter = qla2x00_reset_adapter,
2059 .nvram_config = qla2x00_nvram_config,
2060 .update_fw_options = qla2x00_update_fw_options,
2061 .load_risc = qla2x00_load_risc,
2062 .pci_info_str = qla2x00_pci_info_str,
2063 .fw_version_str = qla2x00_fw_version_str,
2064 .intr_handler = qla2100_intr_handler,
2065 .enable_intrs = qla2x00_enable_intrs,
2066 .disable_intrs = qla2x00_disable_intrs,
2067 .abort_command = qla2x00_abort_command,
523ec773
AV		 2068 .target_reset = qla2x00_abort_target,
2069 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2070 .fabric_login = qla2x00_login_fabric,
2071 .fabric_logout = qla2x00_fabric_logout,
2072 .calc_req_entries = qla2x00_calc_iocbs_32,
2073 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2074 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2075 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2076 .read_nvram = qla2x00_read_nvram_data,
2077 .write_nvram = qla2x00_write_nvram_data,
2078 .fw_dump = qla2100_fw_dump,
2079 .beacon_on = NULL,
2080 .beacon_off = NULL,
2081 .beacon_blink = NULL,
2082 .read_optrom = qla2x00_read_optrom_data,
2083 .write_optrom = qla2x00_write_optrom_data,
2084 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2085 .start_scsi = qla2x00_start_scsi,
d7459527 2086 .start_scsi_mq = NULL,
a9083016 2087 .abort_isp = qla2x00_abort_isp,
706f457d 2088 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2089 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2090};
2091
2092static struct isp_operations qla2300_isp_ops = {
2093 .pci_config = qla2300_pci_config,
2094 .reset_chip = qla2x00_reset_chip,
2095 .chip_diag = qla2x00_chip_diag,
2096 .config_rings = qla2x00_config_rings,
2097 .reset_adapter = qla2x00_reset_adapter,
2098 .nvram_config = qla2x00_nvram_config,
2099 .update_fw_options = qla2x00_update_fw_options,
2100 .load_risc = qla2x00_load_risc,
2101 .pci_info_str = qla2x00_pci_info_str,
2102 .fw_version_str = qla2x00_fw_version_str,
2103 .intr_handler = qla2300_intr_handler,
2104 .enable_intrs = qla2x00_enable_intrs,
2105 .disable_intrs = qla2x00_disable_intrs,
2106 .abort_command = qla2x00_abort_command,
523ec773
AV		 2107 .target_reset = qla2x00_abort_target,
2108 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2109 .fabric_login = qla2x00_login_fabric,
2110 .fabric_logout = qla2x00_fabric_logout,
2111 .calc_req_entries = qla2x00_calc_iocbs_32,
2112 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2113 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2114 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2115 .read_nvram = qla2x00_read_nvram_data,
2116 .write_nvram = qla2x00_write_nvram_data,
2117 .fw_dump = qla2300_fw_dump,
2118 .beacon_on = qla2x00_beacon_on,
2119 .beacon_off = qla2x00_beacon_off,
2120 .beacon_blink = qla2x00_beacon_blink,
2121 .read_optrom = qla2x00_read_optrom_data,
2122 .write_optrom = qla2x00_write_optrom_data,
2123 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2124 .start_scsi = qla2x00_start_scsi,
d7459527 2125 .start_scsi_mq = NULL,
a9083016 2126 .abort_isp = qla2x00_abort_isp,
7ec0effd 2127 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2128 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2129};
2130
2131static struct isp_operations qla24xx_isp_ops = {
2132 .pci_config = qla24xx_pci_config,
2133 .reset_chip = qla24xx_reset_chip,
2134 .chip_diag = qla24xx_chip_diag,
2135 .config_rings = qla24xx_config_rings,
2136 .reset_adapter = qla24xx_reset_adapter,
2137 .nvram_config = qla24xx_nvram_config,
2138 .update_fw_options = qla24xx_update_fw_options,
2139 .load_risc = qla24xx_load_risc,
2140 .pci_info_str = qla24xx_pci_info_str,
2141 .fw_version_str = qla24xx_fw_version_str,
2142 .intr_handler = qla24xx_intr_handler,
2143 .enable_intrs = qla24xx_enable_intrs,
2144 .disable_intrs = qla24xx_disable_intrs,
2145 .abort_command = qla24xx_abort_command,
523ec773
AV		 2146 .target_reset = qla24xx_abort_target,
2147 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2148 .fabric_login = qla24xx_login_fabric,
2149 .fabric_logout = qla24xx_fabric_logout,
2150 .calc_req_entries = NULL,
2151 .build_iocbs = NULL,
2152 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2153 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2154 .read_nvram = qla24xx_read_nvram_data,
2155 .write_nvram = qla24xx_write_nvram_data,
2156 .fw_dump = qla24xx_fw_dump,
2157 .beacon_on = qla24xx_beacon_on,
2158 .beacon_off = qla24xx_beacon_off,
2159 .beacon_blink = qla24xx_beacon_blink,
2160 .read_optrom = qla24xx_read_optrom_data,
2161 .write_optrom = qla24xx_write_optrom_data,
2162 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2163 .start_scsi = qla24xx_start_scsi,
d7459527 2164 .start_scsi_mq = NULL,
a9083016 2165 .abort_isp = qla2x00_abort_isp,
7ec0effd 2166 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2167 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2168};
2169
c3a2f0df
AV		 2170static struct isp_operations qla25xx_isp_ops = {
2171 .pci_config = qla25xx_pci_config,
2172 .reset_chip = qla24xx_reset_chip,
2173 .chip_diag = qla24xx_chip_diag,
2174 .config_rings = qla24xx_config_rings,
2175 .reset_adapter = qla24xx_reset_adapter,
2176 .nvram_config = qla24xx_nvram_config,
2177 .update_fw_options = qla24xx_update_fw_options,
2178 .load_risc = qla24xx_load_risc,
2179 .pci_info_str = qla24xx_pci_info_str,
2180 .fw_version_str = qla24xx_fw_version_str,
2181 .intr_handler = qla24xx_intr_handler,
2182 .enable_intrs = qla24xx_enable_intrs,
2183 .disable_intrs = qla24xx_disable_intrs,
2184 .abort_command = qla24xx_abort_command,
523ec773
AV		 2185 .target_reset = qla24xx_abort_target,
2186 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2187 .fabric_login = qla24xx_login_fabric,
2188 .fabric_logout = qla24xx_fabric_logout,
2189 .calc_req_entries = NULL,
2190 .build_iocbs = NULL,
2191 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2192 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2193 .read_nvram = qla25xx_read_nvram_data,
2194 .write_nvram = qla25xx_write_nvram_data,
2195 .fw_dump = qla25xx_fw_dump,
2196 .beacon_on = qla24xx_beacon_on,
2197 .beacon_off = qla24xx_beacon_off,
2198 .beacon_blink = qla24xx_beacon_blink,
338c9161 2199 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2200 .write_optrom = qla24xx_write_optrom_data,
2201 .get_flash_version = qla24xx_get_flash_version,
bad75002 2202 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2203 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2204 .abort_isp = qla2x00_abort_isp,
7ec0effd 2205 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2206 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2207};
2208
3a03eb79
AV		 2209static struct isp_operations qla81xx_isp_ops = {
2210 .pci_config = qla25xx_pci_config,
2211 .reset_chip = qla24xx_reset_chip,
2212 .chip_diag = qla24xx_chip_diag,
2213 .config_rings = qla24xx_config_rings,
2214 .reset_adapter = qla24xx_reset_adapter,
2215 .nvram_config = qla81xx_nvram_config,
2216 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2217 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2218 .pci_info_str = qla24xx_pci_info_str,
2219 .fw_version_str = qla24xx_fw_version_str,
2220 .intr_handler = qla24xx_intr_handler,
2221 .enable_intrs = qla24xx_enable_intrs,
2222 .disable_intrs = qla24xx_disable_intrs,
2223 .abort_command = qla24xx_abort_command,
2224 .target_reset = qla24xx_abort_target,
2225 .lun_reset = qla24xx_lun_reset,
2226 .fabric_login = qla24xx_login_fabric,
2227 .fabric_logout = qla24xx_fabric_logout,
2228 .calc_req_entries = NULL,
2229 .build_iocbs = NULL,
2230 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2231 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2232 .read_nvram = NULL,
2233 .write_nvram = NULL,
3a03eb79
AV		 2234 .fw_dump = qla81xx_fw_dump,
2235 .beacon_on = qla24xx_beacon_on,
2236 .beacon_off = qla24xx_beacon_off,
6246b8a1 2237 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2238 .read_optrom = qla25xx_read_optrom_data,
2239 .write_optrom = qla24xx_write_optrom_data,
2240 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2241 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2242 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2243 .abort_isp = qla2x00_abort_isp,
7ec0effd 2244 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2245 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2246};
2247
2248static struct isp_operations qla82xx_isp_ops = {
2249 .pci_config = qla82xx_pci_config,
2250 .reset_chip = qla82xx_reset_chip,
2251 .chip_diag = qla24xx_chip_diag,
2252 .config_rings = qla82xx_config_rings,
2253 .reset_adapter = qla24xx_reset_adapter,
2254 .nvram_config = qla81xx_nvram_config,
2255 .update_fw_options = qla24xx_update_fw_options,
2256 .load_risc = qla82xx_load_risc,
9d55ca66 2257 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2258 .fw_version_str = qla24xx_fw_version_str,
2259 .intr_handler = qla82xx_intr_handler,
2260 .enable_intrs = qla82xx_enable_intrs,
2261 .disable_intrs = qla82xx_disable_intrs,
2262 .abort_command = qla24xx_abort_command,
2263 .target_reset = qla24xx_abort_target,
2264 .lun_reset = qla24xx_lun_reset,
2265 .fabric_login = qla24xx_login_fabric,
2266 .fabric_logout = qla24xx_fabric_logout,
2267 .calc_req_entries = NULL,
2268 .build_iocbs = NULL,
2269 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2270 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2271 .read_nvram = qla24xx_read_nvram_data,
2272 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2273 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2274 .beacon_on = qla82xx_beacon_on,
2275 .beacon_off = qla82xx_beacon_off,
2276 .beacon_blink = NULL,
a9083016
GM		 2277 .read_optrom = qla82xx_read_optrom_data,
2278 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2279 .get_flash_version = qla82xx_get_flash_version,
a9083016 2280 .start_scsi = qla82xx_start_scsi,
d7459527 2281 .start_scsi_mq = NULL,
a9083016 2282 .abort_isp = qla82xx_abort_isp,
706f457d 2283 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2284 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2285};
2286
7ec0effd
AD		 2287static struct isp_operations qla8044_isp_ops = {
2288 .pci_config = qla82xx_pci_config,
2289 .reset_chip = qla82xx_reset_chip,
2290 .chip_diag = qla24xx_chip_diag,
2291 .config_rings = qla82xx_config_rings,
2292 .reset_adapter = qla24xx_reset_adapter,
2293 .nvram_config = qla81xx_nvram_config,
2294 .update_fw_options = qla24xx_update_fw_options,
2295 .load_risc = qla82xx_load_risc,
2296 .pci_info_str = qla24xx_pci_info_str,
2297 .fw_version_str = qla24xx_fw_version_str,
2298 .intr_handler = qla8044_intr_handler,
2299 .enable_intrs = qla82xx_enable_intrs,
2300 .disable_intrs = qla82xx_disable_intrs,
2301 .abort_command = qla24xx_abort_command,
2302 .target_reset = qla24xx_abort_target,
2303 .lun_reset = qla24xx_lun_reset,
2304 .fabric_login = qla24xx_login_fabric,
2305 .fabric_logout = qla24xx_fabric_logout,
2306 .calc_req_entries = NULL,
2307 .build_iocbs = NULL,
2308 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2309 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2310 .read_nvram = NULL,
2311 .write_nvram = NULL,
a1b23c5a 2312 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2313 .beacon_on = qla82xx_beacon_on,
2314 .beacon_off = qla82xx_beacon_off,
2315 .beacon_blink = NULL,
888e639d 2316 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2317 .write_optrom = qla8044_write_optrom_data,
2318 .get_flash_version = qla82xx_get_flash_version,
2319 .start_scsi = qla82xx_start_scsi,
d7459527 2320 .start_scsi_mq = NULL,
7ec0effd
AD		 2321 .abort_isp = qla8044_abort_isp,
2322 .iospace_config = qla82xx_iospace_config,
2323 .initialize_adapter = qla2x00_initialize_adapter,
2324};
2325
6246b8a1
GM		 2326static struct isp_operations qla83xx_isp_ops = {
2327 .pci_config = qla25xx_pci_config,
2328 .reset_chip = qla24xx_reset_chip,
2329 .chip_diag = qla24xx_chip_diag,
2330 .config_rings = qla24xx_config_rings,
2331 .reset_adapter = qla24xx_reset_adapter,
2332 .nvram_config = qla81xx_nvram_config,
2333 .update_fw_options = qla81xx_update_fw_options,
2334 .load_risc = qla81xx_load_risc,
2335 .pci_info_str = qla24xx_pci_info_str,
2336 .fw_version_str = qla24xx_fw_version_str,
2337 .intr_handler = qla24xx_intr_handler,
2338 .enable_intrs = qla24xx_enable_intrs,
2339 .disable_intrs = qla24xx_disable_intrs,
2340 .abort_command = qla24xx_abort_command,
2341 .target_reset = qla24xx_abort_target,
2342 .lun_reset = qla24xx_lun_reset,
2343 .fabric_login = qla24xx_login_fabric,
2344 .fabric_logout = qla24xx_fabric_logout,
2345 .calc_req_entries = NULL,
2346 .build_iocbs = NULL,
2347 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2348 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2349 .read_nvram = NULL,
2350 .write_nvram = NULL,
2351 .fw_dump = qla83xx_fw_dump,
2352 .beacon_on = qla24xx_beacon_on,
2353 .beacon_off = qla24xx_beacon_off,
2354 .beacon_blink = qla83xx_beacon_blink,
2355 .read_optrom = qla25xx_read_optrom_data,
2356 .write_optrom = qla24xx_write_optrom_data,
2357 .get_flash_version = qla24xx_get_flash_version,
2358 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2359 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2360 .abort_isp = qla2x00_abort_isp,
2361 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2362 .initialize_adapter = qla2x00_initialize_adapter,
2363};
2364
2365static struct isp_operations qlafx00_isp_ops = {
2366 .pci_config = qlafx00_pci_config,
2367 .reset_chip = qlafx00_soft_reset,
2368 .chip_diag = qlafx00_chip_diag,
2369 .config_rings = qlafx00_config_rings,
2370 .reset_adapter = qlafx00_soft_reset,
2371 .nvram_config = NULL,
2372 .update_fw_options = NULL,
2373 .load_risc = NULL,
2374 .pci_info_str = qlafx00_pci_info_str,
2375 .fw_version_str = qlafx00_fw_version_str,
2376 .intr_handler = qlafx00_intr_handler,
2377 .enable_intrs = qlafx00_enable_intrs,
2378 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2379 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2380 .target_reset = qlafx00_abort_target,
2381 .lun_reset = qlafx00_lun_reset,
2382 .fabric_login = NULL,
2383 .fabric_logout = NULL,
2384 .calc_req_entries = NULL,
2385 .build_iocbs = NULL,
2386 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2387 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2388 .read_nvram = qla24xx_read_nvram_data,
2389 .write_nvram = qla24xx_write_nvram_data,
2390 .fw_dump = NULL,
2391 .beacon_on = qla24xx_beacon_on,
2392 .beacon_off = qla24xx_beacon_off,
2393 .beacon_blink = NULL,
2394 .read_optrom = qla24xx_read_optrom_data,
2395 .write_optrom = qla24xx_write_optrom_data,
2396 .get_flash_version = qla24xx_get_flash_version,
2397 .start_scsi = qlafx00_start_scsi,
d7459527 2398 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2399 .abort_isp = qlafx00_abort_isp,
2400 .iospace_config = qlafx00_iospace_config,
2401 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2402};
2403
f73cb695
CD		 2404static struct isp_operations qla27xx_isp_ops = {
2405 .pci_config = qla25xx_pci_config,
2406 .reset_chip = qla24xx_reset_chip,
2407 .chip_diag = qla24xx_chip_diag,
2408 .config_rings = qla24xx_config_rings,
2409 .reset_adapter = qla24xx_reset_adapter,
2410 .nvram_config = qla81xx_nvram_config,
2411 .update_fw_options = qla81xx_update_fw_options,
2412 .load_risc = qla81xx_load_risc,
2413 .pci_info_str = qla24xx_pci_info_str,
2414 .fw_version_str = qla24xx_fw_version_str,
2415 .intr_handler = qla24xx_intr_handler,
2416 .enable_intrs = qla24xx_enable_intrs,
2417 .disable_intrs = qla24xx_disable_intrs,
2418 .abort_command = qla24xx_abort_command,
2419 .target_reset = qla24xx_abort_target,
2420 .lun_reset = qla24xx_lun_reset,
2421 .fabric_login = qla24xx_login_fabric,
2422 .fabric_logout = qla24xx_fabric_logout,
2423 .calc_req_entries = NULL,
2424 .build_iocbs = NULL,
2425 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2426 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2427 .read_nvram = NULL,
2428 .write_nvram = NULL,
2429 .fw_dump = qla27xx_fwdump,
2430 .beacon_on = qla24xx_beacon_on,
2431 .beacon_off = qla24xx_beacon_off,
2432 .beacon_blink = qla83xx_beacon_blink,
2433 .read_optrom = qla25xx_read_optrom_data,
2434 .write_optrom = qla24xx_write_optrom_data,
2435 .get_flash_version = qla24xx_get_flash_version,
2436 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2437 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2438 .abort_isp = qla2x00_abort_isp,
2439 .iospace_config = qla83xx_iospace_config,
2440 .initialize_adapter = qla2x00_initialize_adapter,
2441};
2442
ea5b6382 2443static inline void
e315cd28 2444qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2445{
2446 ha->device_type = DT_EXTENDED_IDS;
2447 switch (ha->pdev->device) {
2448 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2449 ha->isp_type |= DT_ISP2100;
ea5b6382 2450 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2451 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2452 break;
2453 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2454 ha->isp_type |= DT_ISP2200;
ea5b6382 2455 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2456 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2457 break;
2458 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2459 ha->isp_type |= DT_ISP2300;
4a59f71d 2460 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2461 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2462 break;
2463 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2464 ha->isp_type |= DT_ISP2312;
4a59f71d 2465 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2466 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2467 break;
2468 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2469 ha->isp_type |= DT_ISP2322;
4a59f71d 2470 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2471 if (ha->pdev->subsystem_vendor == 0x1028 &&
2472 ha->pdev->subsystem_device == 0x0170)
2473 ha->device_type |= DT_OEM_001;
441d1072 2474 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2475 break;
2476 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2477 ha->isp_type |= DT_ISP6312;
441d1072 2478 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2479 break;
2480 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2481 ha->isp_type |= DT_ISP6322;
441d1072 2482 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2483 break;
2484 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2485 ha->isp_type |= DT_ISP2422;
4a59f71d 2486 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2487 ha->device_type |= DT_FWI2;
c76f2c01 2488 ha->device_type |= DT_IIDMA;
441d1072 2489 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2490 break;
2491 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2492 ha->isp_type |= DT_ISP2432;
4a59f71d 2493 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2494 ha->device_type |= DT_FWI2;
c76f2c01 2495 ha->device_type |= DT_IIDMA;
441d1072 2496 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2497 break;
4d4df193 2498 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2499 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2500 ha->device_type |= DT_ZIO_SUPPORTED;
2501 ha->device_type |= DT_FWI2;
2502 ha->device_type |= DT_IIDMA;
2503 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2504 break;
044cc6c8 2505 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2506 ha->isp_type |= DT_ISP5422;
e428924c 2507 ha->device_type |= DT_FWI2;
441d1072 2508 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2509 break;
044cc6c8 2510 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2511 ha->isp_type |= DT_ISP5432;
e428924c 2512 ha->device_type |= DT_FWI2;
441d1072 2513 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2514 break;
c3a2f0df 2515 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2516 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2517 ha->device_type |= DT_ZIO_SUPPORTED;
2518 ha->device_type |= DT_FWI2;
2519 ha->device_type |= DT_IIDMA;
441d1072 2520 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2521 break;
3a03eb79 2522 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2523 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2524 ha->device_type |= DT_ZIO_SUPPORTED;
2525 ha->device_type |= DT_FWI2;
2526 ha->device_type |= DT_IIDMA;
2527 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2528 break;
a9083016 2529 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2530 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2531 ha->device_type |= DT_ZIO_SUPPORTED;
2532 ha->device_type |= DT_FWI2;
2533 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2534 /* Initialize 82XX ISP flags */
2535 qla82xx_init_flags(ha);
2536 break;
7ec0effd 2537 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2538 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2539 ha->device_type |= DT_ZIO_SUPPORTED;
2540 ha->device_type |= DT_FWI2;
2541 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2542 /* Initialize 82XX ISP flags */
2543 qla82xx_init_flags(ha);
2544 break;
6246b8a1 2545 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2546 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2547 ha->device_type |= DT_ZIO_SUPPORTED;
2548 ha->device_type |= DT_FWI2;
2549 ha->device_type |= DT_IIDMA;
2550 ha->device_type |= DT_T10_PI;
2551 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2552 break;
2553 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2554 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2555 ha->device_type |= DT_ZIO_SUPPORTED;
2556 ha->device_type |= DT_FWI2;
2557 ha->device_type |= DT_IIDMA;
2558 ha->device_type |= DT_T10_PI;
2559 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2560 break;
8ae6d9c7 2561 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2562 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2563 break;
f73cb695 2564 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2565 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2566 ha->device_type |= DT_ZIO_SUPPORTED;
2567 ha->device_type |= DT_FWI2;
2568 ha->device_type |= DT_IIDMA;
8ce3f570 2569 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2570 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2571 break;
2c5bbbb2 2572 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2573 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2574 ha->device_type |= DT_ZIO_SUPPORTED;
2575 ha->device_type |= DT_FWI2;
2576 ha->device_type |= DT_IIDMA;
8ce3f570 2577 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2579 break;
2b48992f 2580 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2581 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2582 ha->device_type |= DT_ZIO_SUPPORTED;
2583 ha->device_type |= DT_FWI2;
2584 ha->device_type |= DT_IIDMA;
8ce3f570 2585 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2586 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2587 break;
ea5b6382 2588 }
e5b68a61 2589
a9083016 2590 if (IS_QLA82XX(ha))
43a9c38b 2591 ha->port_no = ha->portnum & 1;
f73cb695 2592 else {
a9083016
GM		 2593 /* Get adapter physical port no from interrupt pin register. */
2594 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2595 if (IS_QLA27XX(ha))
2596 ha->port_no--;
2597 else
2598 ha->port_no = !(ha->port_no & 1);
2599 }
a9083016 2600
7c3df132 2601 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2602 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2603 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2604}
2605
1e99e33a
AV		 2606static void
2607qla2xxx_scan_start(struct Scsi_Host *shost)
2608{
e315cd28 2609 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2610
cbc8eb67
AV		 2611 if (vha->hw->flags.running_gold_fw)
2612 return;
2613
e315cd28
AC		 2614 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2615 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2616 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2617 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2618}
2619
2620static int
2621qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2622{
e315cd28 2623 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2624
a5dd506e
BK		 2625 if (test_bit(UNLOADING, &vha->dpc_flags))
2626 return 1;
e315cd28 2627 if (!vha->host)
1e99e33a 2628 return 1;
e315cd28 2629 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2630 return 1;
2631
e315cd28 2632 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2633}
2634
ec7193e2
QT		 2635static void qla2x00_iocb_work_fn(struct work_struct *work)
2636{
2637 struct scsi_qla_host *vha = container_of(work,
2638 struct scsi_qla_host, iocb_work);
2639 int cnt = 0;
2640
2641 while (!list_empty(&vha->work_list)) {
2642 qla2x00_do_work(vha);
2643 cnt++;
2644 if (cnt > 10)
2645 break;
2646 }
2647}
2648
1da177e4
LT		 2649/*
2650 * PCI driver interface
2651 */
6f039790 2652static int
7ee61397 2653qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2654{
a1541d5a 2655 int ret = -ENODEV;
1da177e4 2656 struct Scsi_Host *host;
e315cd28
AC		 2657 scsi_qla_host_t *base_vha = NULL;
2658 struct qla_hw_data *ha;
29856e28 2659 char pci_info[30];
7d613ac6 2660 char fw_str[30], wq_name[30];
5433383e 2661 struct scsi_host_template *sht;
642ef983 2662 int bars, mem_only = 0;
e315cd28 2663 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2664 struct req_que *req = NULL;
2665 struct rsp_que *rsp = NULL;
5601236b 2666 int i;
d7459527 2667
285d0321 2668 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2669 sht = &qla2xxx_driver_template;
5433383e 2670 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2671 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2672 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2673 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2674 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2675 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2676 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2677 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2678 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2679 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2680 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2681 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2682 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2683 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2684 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2685 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2686 mem_only = 1;
7c3df132
SK		 2687 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2688 "Mem only adapter.\n");
285d0321 2689 }
7c3df132
SK		 2690 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2691 "Bars=%d.\n", bars);
285d0321 2692
09483916
BH		 2693 if (mem_only) {
2694 if (pci_enable_device_mem(pdev))
ddff7ed4 2695 return ret;
09483916
BH		 2696 } else {
2697 if (pci_enable_device(pdev))
ddff7ed4 2698 return ret;
09483916 2699 }
285d0321 2700
0927678f
JB		 2701 /* This may fail but that's ok */
2702 pci_enable_pcie_error_reporting(pdev);
285d0321 2703
e315cd28
AC		 2704 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2705 if (!ha) {
7c3df132
SK		 2706 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2707 "Unable to allocate memory for ha.\n");
ddff7ed4 2708 goto disable_device;
1da177e4 2709 }
7c3df132
SK		 2710 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2711 "Memory allocated for ha=%p.\n", ha);
e315cd28 2712 ha->pdev = pdev;
33e79977
QT		 2713 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2714 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2715 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2716 spin_lock_init(&ha->tgt.atio_lock);
2717
1da177e4
LT		 2718
2719 /* Clear our data area */
285d0321 2720 ha->bars = bars;
09483916 2721 ha->mem_only = mem_only;
df4bf0bb 2722 spin_lock_init(&ha->hardware_lock);
339aa70e 2723 spin_lock_init(&ha->vport_slock);
a9b6f722 2724 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2725 mutex_init(&ha->optrom_mutex);
1da177e4 2726
ea5b6382
AV		 2727 /* Set ISP-type information. */
2728 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2729
2730 /* Set EEH reset type to fundamental if required by hba */
95676112 2731 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2732 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2733 pdev->needs_freset = 1;
ca79cf66 2734
cba1e47f
CD		 2735 ha->prev_topology = 0;
2736 ha->init_cb_size = sizeof(init_cb_t);
2737 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2738 ha->optrom_size = OPTROM_SIZE_2300;
2739
abbd8870 2740 /* Assign ISP specific operations. */
1da177e4 2741 if (IS_QLA2100(ha)) {
642ef983 2742 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2743 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2744 req_length = REQUEST_ENTRY_CNT_2100;
2745 rsp_length = RESPONSE_ENTRY_CNT_2100;
2746 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2747 ha->gid_list_info_size = 4;
3a03eb79
AV		 2748 ha->flash_conf_off = ~0;
2749 ha->flash_data_off = ~0;
2750 ha->nvram_conf_off = ~0;
2751 ha->nvram_data_off = ~0;
fd34f556 2752 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2753 } else if (IS_QLA2200(ha)) {
642ef983 2754 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2755 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2756 req_length = REQUEST_ENTRY_CNT_2200;
2757 rsp_length = RESPONSE_ENTRY_CNT_2100;
2758 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2759 ha->gid_list_info_size = 4;
3a03eb79
AV		 2760 ha->flash_conf_off = ~0;
2761 ha->flash_data_off = ~0;
2762 ha->nvram_conf_off = ~0;
2763 ha->nvram_data_off = ~0;
fd34f556 2764 ha->isp_ops = &qla2100_isp_ops;
fca29703 2765 } else if (IS_QLA23XX(ha)) {
642ef983 2766 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2767 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2768 req_length = REQUEST_ENTRY_CNT_2200;
2769 rsp_length = RESPONSE_ENTRY_CNT_2300;
2770 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2771 ha->gid_list_info_size = 6;
854165f4
AV		 2772 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2773 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2774 ha->flash_conf_off = ~0;
2775 ha->flash_data_off = ~0;
2776 ha->nvram_conf_off = ~0;
2777 ha->nvram_data_off = ~0;
fd34f556 2778 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2779 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2780 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2781 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2782 req_length = REQUEST_ENTRY_CNT_24XX;
2783 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2784 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2785 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2786 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2787 ha->gid_list_info_size = 8;
854165f4 2788 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2789 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2790 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2791 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2792 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2793 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2794 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2795 } else if (IS_QLA25XX(ha)) {
642ef983 2796 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2797 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2798 req_length = REQUEST_ENTRY_CNT_24XX;
2799 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2800 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2801 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2802 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2803 ha->gid_list_info_size = 8;
2804 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2805 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2806 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2807 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2808 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2809 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2810 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2811 } else if (IS_QLA81XX(ha)) {
642ef983 2812 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2813 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2814 req_length = REQUEST_ENTRY_CNT_24XX;
2815 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2816 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2817 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2818 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2819 ha->gid_list_info_size = 8;
2820 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2821 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2822 ha->isp_ops = &qla81xx_isp_ops;
2823 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2824 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2825 ha->nvram_conf_off = ~0;
2826 ha->nvram_data_off = ~0;
a9083016 2827 } else if (IS_QLA82XX(ha)) {
642ef983 2828 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2829 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2830 req_length = REQUEST_ENTRY_CNT_82XX;
2831 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2832 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2833 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2834 ha->gid_list_info_size = 8;
2835 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2836 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2837 ha->isp_ops = &qla82xx_isp_ops;
2838 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2839 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2840 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2841 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2842 } else if (IS_QLA8044(ha)) {
2843 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2844 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2845 req_length = REQUEST_ENTRY_CNT_82XX;
2846 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2847 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2848 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2849 ha->gid_list_info_size = 8;
2850 ha->optrom_size = OPTROM_SIZE_83XX;
2851 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2852 ha->isp_ops = &qla8044_isp_ops;
2853 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2854 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2855 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2856 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2857 } else if (IS_QLA83XX(ha)) {
7d613ac6 2858 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2859 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2860 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2861 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2862 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2863 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2864 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2865 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2866 ha->gid_list_info_size = 8;
2867 ha->optrom_size = OPTROM_SIZE_83XX;
2868 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2869 ha->isp_ops = &qla83xx_isp_ops;
2870 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2871 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2872 ha->nvram_conf_off = ~0;
2873 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2874 } else if (IS_QLAFX00(ha)) {
2875 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2876 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2877 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2878 req_length = REQUEST_ENTRY_CNT_FX00;
2879 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2880 ha->isp_ops = &qlafx00_isp_ops;
2881 ha->port_down_retry_count = 30; /* default value */
2882 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2883 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2884 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2885 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2886 ha->mr.host_info_resend = false;
2887 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2888 } else if (IS_QLA27XX(ha)) {
2889 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2890 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2891 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2892 req_length = REQUEST_ENTRY_CNT_83XX;
2893 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2894 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2895 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2896 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2897 ha->gid_list_info_size = 8;
2898 ha->optrom_size = OPTROM_SIZE_83XX;
2899 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2900 ha->isp_ops = &qla27xx_isp_ops;
2901 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2902 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2903 ha->nvram_conf_off = ~0;
2904 ha->nvram_data_off = ~0;
1da177e4 2905 }
6246b8a1 2906
7c3df132
SK		 2907 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2908 "mbx_count=%d, req_length=%d, "
2909 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2910 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2911 "max_fibre_devices=%d.\n",
7c3df132
SK		 2912 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2913 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2914 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2915 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2916 "isp_ops=%p, flash_conf_off=%d, "
2917 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2918 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2919 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2920
2921 /* Configure PCI I/O space */
2922 ret = ha->isp_ops->iospace_config(ha);
2923 if (ret)
0a63ad12 2924 goto iospace_config_failed;
706f457d
GM		 2925
2926 ql_log_pci(ql_log_info, pdev, 0x001d,
2927 "Found an ISP%04X irq %d iobase 0x%p.\n",
2928 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2929 mutex_init(&ha->vport_lock);
d7459527 2930 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2931 init_completion(&ha->mbx_cmd_comp);
2932 complete(&ha->mbx_cmd_comp);
2933 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2934 init_completion(&ha->dcbx_comp);
f356bef1 2935 init_completion(&ha->lb_portup_comp);
1da177e4 2936
2c3dfe3f 2937 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2938
53303c42 2939 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2940 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2941 "64 Bit addressing is %s.\n",
2942 ha->flags.enable_64bit_addressing ? "enable" :
2943 "disable");
73208dfd 2944 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2945 if (ret) {
7c3df132
SK		 2946 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2947 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2948
e315cd28
AC		 2949 goto probe_hw_failed;
2950 }
2951
73208dfd 2952 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2953 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2954 req->max_q_depth = ql2xmaxqdepth;
2955
e315cd28
AC		 2956
2957 base_vha = qla2x00_create_host(sht, ha);
2958 if (!base_vha) {
a1541d5a 2959 ret = -ENOMEM;
6e9f21f3 2960 qla2x00_mem_free(ha);
2afa19a9
AC		 2961 qla2x00_free_req_que(ha, req);
2962 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2963 goto probe_hw_failed;
1da177e4
LT		 2964 }
2965
e315cd28 2966 pci_set_drvdata(pdev, base_vha);
6b383979 2967 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2968
e315cd28 2969 host = base_vha->host;
2afa19a9 2970 base_vha->req = req;
73208dfd 2971 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2972 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2973 else
e315cd28
AC		 2974 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2975 base_vha->vp_idx;
58548cb5 2976
8ae6d9c7
GM		 2977 /* Setup fcport template structure. */
2978 ha->mr.fcport.vha = base_vha;
2979 ha->mr.fcport.port_type = FCT_UNKNOWN;
2980 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2981 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2982 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2983 ha->mr.fcport.scan_state = 1;
2984
58548cb5
GM		 2985 /* Set the SG table size based on ISP type */
2986 if (!IS_FWI2_CAPABLE(ha)) {
2987 if (IS_QLA2100(ha))
2988 host->sg_tablesize = 32;
2989 } else {
2990 if (!IS_QLA82XX(ha))
2991 host->sg_tablesize = QLA_SG_ALL;
2992 }
642ef983 2993 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2994 host->cmd_per_lun = 3;
2995 host->unique_id = host->host_no;
e02587d7 2996 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2997 host->max_cmd_len = 32;
2998 else
2999 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3000 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3001 /* Older HBAs support only 16-bit LUNs */
3002 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3003 ql2xmaxlun > 0xffff)
3004 host->max_lun = 0xffff;
3005 else
3006 host->max_lun = ql2xmaxlun;
e315cd28 3007 host->transportt = qla2xxx_transport_template;
9a069e19 3008 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3009
7c3df132
SK		 3010 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3011 "max_id=%d this_id=%d "
3012 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3013 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3014 host->this_id, host->cmd_per_lun, host->unique_id,
3015 host->max_cmd_len, host->max_channel, host->max_lun,
3016 host->transportt, sht->vendor_id);
3017
d7459527
MH		 3018 /* Set up the irqs */
3019 ret = qla2x00_request_irqs(ha, rsp);
3020 if (ret)
3021 goto probe_init_failed;
3022
9a347ff4
CD		 3023 /* Alloc arrays of request and response ring ptrs */
3024 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3025 ql_log(ql_log_fatal, base_vha, 0x003d,
3026 "Failed to allocate memory for queue pointers..."
3027 "aborting.\n");
3028 goto probe_init_failed;
3029 }
3030
5601236b
MH		 3031 if (ha->mqenable && shost_use_blk_mq(host)) {
3032 /* number of hardware queues supported by blk/scsi-mq*/
3033 host->nr_hw_queues = ha->max_qpairs;
3034
3035 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3036 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3037 } else
3038 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3039 "blk/scsi-mq disabled.\n");
3040
2d70c103 3041 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3042
90a86fc0
JC		 3043 pci_save_state(pdev);
3044
9a347ff4 3045 /* Assign back pointers */
2afa19a9
AC		 3046 rsp->req = req;
3047 req->rsp = rsp;
9a347ff4 3048
8ae6d9c7
GM		 3049 if (IS_QLAFX00(ha)) {
3050 ha->rsp_q_map[0] = rsp;
3051 ha->req_q_map[0] = req;
3052 set_bit(0, ha->req_qid_map);
3053 set_bit(0, ha->rsp_qid_map);
3054 }
3055
08029990
AV		 3056 /* FWI2-capable only. */
3057 req->req_q_in = &ha->iobase->isp24.req_q_in;
3058 req->req_q_out = &ha->iobase->isp24.req_q_out;
3059 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3060 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3061 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3062 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3063 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3064 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3065 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3066 }
3067
8ae6d9c7
GM		 3068 if (IS_QLAFX00(ha)) {
3069 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3070 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3071 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3072 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3073 }
3074
7ec0effd 3075 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3076 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3077 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3078 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3079 }
3080
7c3df132
SK		 3081 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3082 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3083 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3084 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3085 "req->req_q_in=%p req->req_q_out=%p "
3086 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3087 req->req_q_in, req->req_q_out,
3088 rsp->rsp_q_in, rsp->rsp_q_out);
3089 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3090 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3091 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3092 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3093 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3094 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3095
8ae6d9c7 3096 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3097 ql_log(ql_log_fatal, base_vha, 0x00d6,
3098 "Failed to initialize adapter - Adapter flags %x.\n",
3099 base_vha->device_flags);
1da177e4 3100
a9083016
GM		 3101 if (IS_QLA82XX(ha)) {
3102 qla82xx_idc_lock(ha);
3103 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3104 QLA8XXX_DEV_FAILED);
a9083016 3105 qla82xx_idc_unlock(ha);
7c3df132
SK		 3106 ql_log(ql_log_fatal, base_vha, 0x00d7,
3107 "HW State: FAILED.\n");
7ec0effd
AD		 3108 } else if (IS_QLA8044(ha)) {
3109 qla8044_idc_lock(ha);
3110 qla8044_wr_direct(base_vha,
3111 QLA8044_CRB_DEV_STATE_INDEX,
3112 QLA8XXX_DEV_FAILED);
3113 qla8044_idc_unlock(ha);
3114 ql_log(ql_log_fatal, base_vha, 0x0150,
3115 "HW State: FAILED.\n");
a9083016
GM		 3116 }
3117
a1541d5a 3118 ret = -ENODEV;
1da177e4
LT		 3119 goto probe_failed;
3120 }
3121
3b1bef64
CD		 3122 if (IS_QLAFX00(ha))
3123 host->can_queue = QLAFX00_MAX_CANQUEUE;
3124 else
3125 host->can_queue = req->num_outstanding_cmds - 10;
3126
3127 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3128 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3129 host->can_queue, base_vha->req,
3130 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3131
e326d22a
QT		 3132 if (ha->mqenable) {
3133 bool mq = false;
3134 bool startit = false;
d7459527 3135 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
e326d22a
QT		 3136
3137 if (QLA_TGT_MODE_ENABLED()) {
3138 mq = true;
3139 startit = false;
3140 }
3141
3142 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3143 shost_use_blk_mq(host)) {
3144 mq = true;
3145 startit = true;
3146 }
3147
3148 if (mq) {
3149 /* Create start of day qpairs for Block MQ */
5601236b 3150 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3151 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3152 }
3153 }
68ca949c 3154
cbc8eb67
AV		 3155 if (ha->flags.running_gold_fw)
3156 goto skip_dpc;
3157
1da177e4
LT		 3158 /*
3159 * Startup the kernel thread for this host adapter
3160 */
39a11240 3161 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3162 "%s_dpc", base_vha->host_str);
39a11240 3163 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3164 ql_log(ql_log_fatal, base_vha, 0x00ed,
3165 "Failed to start DPC thread.\n");
39a11240 3166 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3167 goto probe_failed;
3168 }
7c3df132
SK		 3169 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3170 "DPC thread started successfully.\n");
1da177e4 3171
2d70c103
NB		 3172 /*
3173 * If we're not coming up in initiator mode, we might sit for
3174 * a while without waking up the dpc thread, which leads to a
3175 * stuck process warning. So just kick the dpc once here and
3176 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3177 */
3178 qla2xxx_wake_dpc(base_vha);
3179
ec7193e2 3180 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3181 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3182
81178772
SK		 3183 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3184 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3185 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3186 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3187
3188 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3189 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3190 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3191 INIT_WORK(&ha->idc_state_handler,
3192 qla83xx_idc_state_handler_work);
3193 INIT_WORK(&ha->nic_core_unrecoverable,
3194 qla83xx_nic_core_unrecoverable_work);
3195 }
3196
cbc8eb67 3197skip_dpc:
e315cd28
AC		 3198 list_add_tail(&base_vha->list, &ha->vp_list);
3199 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3200
3201 /* Initialized the timer */
e315cd28 3202 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3203 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3204 "Started qla2x00_timer with "
3205 "interval=%d.\n", WATCH_INTERVAL);
3206 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3207 "Detected hba at address=%p.\n",
3208 ha);
d19044c3 3209
e02587d7 3210 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3211 if (ha->fw_attributes & BIT_4) {
9e522cd8 3212 int prot = 0, guard;
bad75002 3213 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3214 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3215 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3216 if (ql2xenabledif == 1)
3217 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3218 scsi_host_set_prot(host,
8cb2049c 3219 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3220 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3221 | SHOST_DIF_TYPE3_PROTECTION
3222 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3223 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3224 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3225
3226 guard = SHOST_DIX_GUARD_CRC;
3227
3228 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3229 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3230 guard |= SHOST_DIX_GUARD_IP;
3231
3232 scsi_host_set_guard(host, guard);
bad75002
AE		 3233 } else
3234 base_vha->flags.difdix_supported = 0;
3235 }
3236
a9083016
GM		 3237 ha->isp_ops->enable_intrs(ha);
3238
1fe19ee4
AB		 3239 if (IS_QLAFX00(ha)) {
3240 ret = qlafx00_fx_disc(base_vha,
3241 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3242 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3243 QLA_SG_ALL : 128;
3244 }
3245
a1541d5a
AV		 3246 ret = scsi_add_host(host, &pdev->dev);
3247 if (ret)
3248 goto probe_failed;
3249
1486400f
MR		 3250 base_vha->flags.init_done = 1;
3251 base_vha->flags.online = 1;
edaa5c74 3252 ha->prev_minidump_failed = 0;
1486400f 3253
7c3df132
SK		 3254 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3255 "Init done and hba is online.\n");
3256
726b8548
QT		 3257 if (qla_ini_mode_enabled(base_vha) ||
3258 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3259 scsi_scan_host(host);
3260 else
3261 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3262 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3263
e315cd28 3264 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3265
8ae6d9c7 3266 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3267 ret = qlafx00_fx_disc(base_vha,
3268 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3269
3270 /* Register system information */
3271 ret = qlafx00_fx_disc(base_vha,
3272 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3273 }
3274
e315cd28 3275 qla2x00_init_host_attr(base_vha);
a1541d5a 3276
e315cd28 3277 qla2x00_dfs_setup(base_vha);
df613b96 3278
03eb912a
AB		 3279 ql_log(ql_log_info, base_vha, 0x00fb,
3280 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3281 ql_log(ql_log_info, base_vha, 0x00fc,
3282 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3283 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3284 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3285 base_vha->host_no,
df57caba 3286 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3287
2d70c103
NB		 3288 qlt_add_target(ha, base_vha);
3289
6b383979 3290 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3291
3292 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3293 return -ENODEV;
3294
1da177e4
LT		 3295 return 0;
3296
6e9f21f3 3297probe_init_failed:
2afa19a9 3298 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3299 ha->req_q_map[0] = NULL;
3300 clear_bit(0, ha->req_qid_map);
2afa19a9 3301 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3302 ha->rsp_q_map[0] = NULL;
3303 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3304 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3305
1da177e4 3306probe_failed:
b9978769
AV		 3307 if (base_vha->timer_active)
3308 qla2x00_stop_timer(base_vha);
3309 base_vha->flags.online = 0;
3310 if (ha->dpc_thread) {
3311 struct task_struct *t = ha->dpc_thread;
3312
3313 ha->dpc_thread = NULL;
3314 kthread_stop(t);
3315 }
3316
e315cd28 3317 qla2x00_free_device(base_vha);
1da177e4 3318
e315cd28 3319 scsi_host_put(base_vha->host);
1da177e4 3320
e315cd28 3321probe_hw_failed:
1a2fbf18
JL		 3322 qla2x00_clear_drv_active(ha);
3323
0a63ad12 3324iospace_config_failed:
7ec0effd 3325 if (IS_P3P_TYPE(ha)) {
0a63ad12 3326 if (!ha->nx_pcibase)
f73cb695 3327 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3328 if (!ql2xdbwr)
f73cb695 3329 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3330 } else {
3331 if (ha->iobase)
3332 iounmap(ha->iobase);
8ae6d9c7
GM		 3333 if (ha->cregbase)
3334 iounmap(ha->cregbase);
a9083016 3335 }
e315cd28
AC		 3336 pci_release_selected_regions(ha->pdev, ha->bars);
3337 kfree(ha);
1da177e4 3338
ddff7ed4 3339disable_device:
e315cd28 3340 pci_disable_device(pdev);
a1541d5a 3341 return ret;
1da177e4 3342}
1da177e4 3343
e30d1756
MI		 3344static void
3345qla2x00_shutdown(struct pci_dev *pdev)
3346{
3347 scsi_qla_host_t *vha;
3348 struct qla_hw_data *ha;
3349
552f3f9a
MI		 3350 if (!atomic_read(&pdev->enable_cnt))
3351 return;
3352
e30d1756
MI		 3353 vha = pci_get_drvdata(pdev);
3354 ha = vha->hw;
3355
42479343
AB		 3356 /* Notify ISPFX00 firmware */
3357 if (IS_QLAFX00(ha))
3358 qlafx00_driver_shutdown(vha, 20);
3359
e30d1756
MI		 3360 /* Turn-off FCE trace */
3361 if (ha->flags.fce_enabled) {
3362 qla2x00_disable_fce_trace(vha, NULL, NULL);
3363 ha->flags.fce_enabled = 0;
3364 }
3365
3366 /* Turn-off EFT trace */
3367 if (ha->eft)
3368 qla2x00_disable_eft_trace(vha);
3369
3370 /* Stop currently executing firmware. */
3371 qla2x00_try_to_stop_firmware(vha);
3372
3373 /* Turn adapter off line */
3374 vha->flags.online = 0;
3375
3376 /* turn-off interrupts on the card */
3377 if (ha->interrupts_on) {
3378 vha->flags.init_done = 0;
3379 ha->isp_ops->disable_intrs(ha);
3380 }
3381
3382 qla2x00_free_irqs(vha);
3383
3384 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3385
3386 pci_disable_pcie_error_reporting(pdev);
3387 pci_disable_device(pdev);
e30d1756
MI		 3388}
3389
fe1b806f 3390/* Deletes all the virtual ports for a given ha */
4c993f76 3391static void
fe1b806f 3392qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3393{
fe1b806f 3394 scsi_qla_host_t *vha;
feafb7b1 3395 unsigned long flags;
e315cd28 3396
43ebf16d
AE		 3397 mutex_lock(&ha->vport_lock);
3398 while (ha->cur_vport_count) {
43ebf16d 3399 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3400
43ebf16d
AE		 3401 BUG_ON(base_vha->list.next == &ha->vp_list);
3402 /* This assumes first entry in ha->vp_list is always base vha */
3403 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3404 scsi_host_get(vha->host);
feafb7b1 3405
43ebf16d
AE		 3406 spin_unlock_irqrestore(&ha->vport_slock, flags);
3407 mutex_unlock(&ha->vport_lock);
3408
3409 fc_vport_terminate(vha->fc_vport);
3410 scsi_host_put(vha->host);
feafb7b1 3411
43ebf16d 3412 mutex_lock(&ha->vport_lock);
e315cd28 3413 }
43ebf16d 3414 mutex_unlock(&ha->vport_lock);
fe1b806f 3415}
1da177e4 3416
fe1b806f
CD		 3417/* Stops all deferred work threads */
3418static void
3419qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3420{
7d613ac6
SV		 3421 /* Cancel all work and destroy DPC workqueues */
3422 if (ha->dpc_lp_wq) {
3423 cancel_work_sync(&ha->idc_aen);
3424 destroy_workqueue(ha->dpc_lp_wq);
3425 ha->dpc_lp_wq = NULL;
3426 }
3427
3428 if (ha->dpc_hp_wq) {
3429 cancel_work_sync(&ha->nic_core_reset);
3430 cancel_work_sync(&ha->idc_state_handler);
3431 cancel_work_sync(&ha->nic_core_unrecoverable);
3432 destroy_workqueue(ha->dpc_hp_wq);
3433 ha->dpc_hp_wq = NULL;
3434 }
3435
b9978769
AV		 3436 /* Kill the kernel thread for this host */
3437 if (ha->dpc_thread) {
3438 struct task_struct *t = ha->dpc_thread;
3439
3440 /*
3441 * qla2xxx_wake_dpc checks for ->dpc_thread
3442 * so we need to zero it out.
3443 */
3444 ha->dpc_thread = NULL;
3445 kthread_stop(t);
3446 }
fe1b806f 3447}
1da177e4 3448
fe1b806f
CD		 3449static void
3450qla2x00_unmap_iobases(struct qla_hw_data *ha)
3451{
a9083016 3452 if (IS_QLA82XX(ha)) {
b963752f 3453
f73cb695 3454 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3455 if (!ql2xdbwr)
f73cb695 3456 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3457 } else {
3458 if (ha->iobase)
3459 iounmap(ha->iobase);
1da177e4 3460
8ae6d9c7
GM		 3461 if (ha->cregbase)
3462 iounmap(ha->cregbase);
3463
a9083016
GM		 3464 if (ha->mqiobase)
3465 iounmap(ha->mqiobase);
6246b8a1 3466
f73cb695 3467 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3468 iounmap(ha->msixbase);
a9083016 3469 }
fe1b806f
CD		 3470}
3471
3472static void
db7157d4 3473qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3474{
fe1b806f
CD		 3475 if (IS_QLA8044(ha)) {
3476 qla8044_idc_lock(ha);
c41afc9a 3477 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3478 qla8044_idc_unlock(ha);
3479 } else if (IS_QLA82XX(ha)) {
3480 qla82xx_idc_lock(ha);
3481 qla82xx_clear_drv_active(ha);
3482 qla82xx_idc_unlock(ha);
3483 }
3484}
3485
3486static void
3487qla2x00_remove_one(struct pci_dev *pdev)
3488{
3489 scsi_qla_host_t *base_vha;
3490 struct qla_hw_data *ha;
3491
beb9e315
JL		 3492 base_vha = pci_get_drvdata(pdev);
3493 ha = base_vha->hw;
3494
3495 /* Indicate device removal to prevent future board_disable and wait
3496 * until any pending board_disable has completed. */
3497 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3498 cancel_work_sync(&ha->board_disable);
3499
fe1b806f 3500 /*
beb9e315
JL		 3501 * If the PCI device is disabled then there was a PCI-disconnect and
3502 * qla2x00_disable_board_on_pci_error has taken care of most of the
3503 * resources.
fe1b806f 3504 */
beb9e315 3505 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3506 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3507 base_vha->gnl.l, base_vha->gnl.ldma);
3508
beb9e315
JL		 3509 scsi_host_put(base_vha->host);
3510 kfree(ha);
3511 pci_set_drvdata(pdev, NULL);
fe1b806f 3512 return;
beb9e315 3513 }
638a1a01
SC		 3514 qla2x00_wait_for_hba_ready(base_vha);
3515
726b8548
QT		 3516 /*
3517 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3518 * where it was set first.
3519 */
3520 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3521 return;
3522
fe1b806f 3523 set_bit(UNLOADING, &base_vha->dpc_flags);
726b8548
QT		 3524 dma_free_coherent(&ha->pdev->dev,
3525 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3526
3527 if (IS_QLAFX00(ha))
3528 qlafx00_driver_shutdown(base_vha, 20);
3529
3530 qla2x00_delete_all_vps(ha, base_vha);
3531
3532 if (IS_QLA8031(ha)) {
3533 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3534 "Clearing fcoe driver presence.\n");
3535 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3536 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3537 "Error while clearing DRV-Presence.\n");
3538 }
3539
3540 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3541
3542 qla2x00_dfs_remove(base_vha);
3543
3544 qla84xx_put_chip(base_vha);
3545
2d5a4c34
HM		 3546 /* Laser should be disabled only for ISP2031 */
3547 if (IS_QLA2031(ha))
3548 qla83xx_disable_laser(base_vha);
3549
fe1b806f
CD		 3550 /* Disable timer */
3551 if (base_vha->timer_active)
3552 qla2x00_stop_timer(base_vha);
3553
3554 base_vha->flags.online = 0;
3555
b0d6cabd
HM		 3556 /* free DMA memory */
3557 if (ha->exlogin_buf)
3558 qla2x00_free_exlogin_buffer(ha);
3559
2f56a7f1
HM		 3560 /* free DMA memory */
3561 if (ha->exchoffld_buf)
3562 qla2x00_free_exchoffld_buffer(ha);
3563
fe1b806f
CD		 3564 qla2x00_destroy_deferred_work(ha);
3565
3566 qlt_remove_target(ha, base_vha);
3567
3568 qla2x00_free_sysfs_attr(base_vha, true);
3569
3570 fc_remove_host(base_vha->host);
482c9dc7 3571 qlt_remove_target_resources(ha);
fe1b806f
CD		 3572
3573 scsi_remove_host(base_vha->host);
3574
3575 qla2x00_free_device(base_vha);
3576
db7157d4 3577 qla2x00_clear_drv_active(ha);
fe1b806f 3578
d2749ffa
AE		 3579 scsi_host_put(base_vha->host);
3580
fe1b806f 3581 qla2x00_unmap_iobases(ha);
73208dfd 3582
e315cd28
AC		 3583 pci_release_selected_regions(ha->pdev, ha->bars);
3584 kfree(ha);
1da177e4 3585
90a86fc0
JC		 3586 pci_disable_pcie_error_reporting(pdev);
3587
665db93b 3588 pci_disable_device(pdev);
1da177e4 3589}
1da177e4
LT		 3590
3591static void
e315cd28 3592qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3593{
e315cd28 3594 struct qla_hw_data *ha = vha->hw;
1da177e4 3595
85880801
AV		 3596 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3597
3598 /* Disable timer */
3599 if (vha->timer_active)
3600 qla2x00_stop_timer(vha);
3601
2afa19a9 3602 qla25xx_delete_queues(vha);
fe1b806f 3603
df613b96 3604 if (ha->flags.fce_enabled)
e315cd28 3605 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3606
a7a167bf 3607 if (ha->eft)
e315cd28 3608 qla2x00_disable_eft_trace(vha);
a7a167bf 3609
f6ef3b18 3610 /* Stop currently executing firmware. */
e315cd28 3611 qla2x00_try_to_stop_firmware(vha);
1da177e4 3612
85880801
AV		 3613 vha->flags.online = 0;
3614
f6ef3b18 3615 /* turn-off interrupts on the card */
a9083016
GM		 3616 if (ha->interrupts_on) {
3617 vha->flags.init_done = 0;
fd34f556 3618 ha->isp_ops->disable_intrs(ha);
a9083016 3619 }
f6ef3b18 3620
093df737
QT		 3621 qla2x00_free_fcports(vha);
3622
e315cd28 3623 qla2x00_free_irqs(vha);
1da177e4 3624
093df737
QT		 3625 /* Flush the work queue and remove it */
3626 if (ha->wq) {
3627 flush_workqueue(ha->wq);
3628 destroy_workqueue(ha->wq);
3629 ha->wq = NULL;
3630 }
3631
8867048b 3632
e315cd28 3633 qla2x00_mem_free(ha);
73208dfd 3634
08de2844
GM		 3635 qla82xx_md_free(vha);
3636
73208dfd 3637 qla2x00_free_queues(ha);
1da177e4
LT		 3638}
3639
8867048b
CD		 3640void qla2x00_free_fcports(struct scsi_qla_host *vha)
3641{
3642 fc_port_t *fcport, *tfcport;
3643
3644 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3645 list_del(&fcport->list);
5f16b331 3646 qla2x00_clear_loop_id(fcport);
8867048b 3647 kfree(fcport);
8867048b
CD		 3648 }
3649}
3650
d97994dc 3651static inline void
e315cd28 3652qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3653 int defer)
3654{
d97994dc 3655 struct fc_rport *rport;
67becc00 3656 scsi_qla_host_t *base_vha;
044d78e1 3657 unsigned long flags;
d97994dc
AV		 3658
3659 if (!fcport->rport)
3660 return;
3661
3662 rport = fcport->rport;
3663 if (defer) {
67becc00 3664 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3665 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3666 fcport->drport = rport;
044d78e1 3667 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3668 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3669 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3670 qla2xxx_wake_dpc(base_vha);
2d70c103 3671 } else {
df673274 3672 int now;
726b8548 3673 if (rport) {
83548fe2
QT		 3674 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3675 "%s %8phN. rport %p roles %x\n",
3676 __func__, fcport->port_name, rport,
3677 rport->roles);
d20ed91b 3678 fc_remote_port_delete(rport);
726b8548 3679 }
df673274 3680 qlt_do_generation_tick(vha, &now);
2d70c103 3681 }
d97994dc
AV		 3682}
3683
1da177e4
LT		 3684/*
3685 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3686 *
3687 * Input: ha = adapter block pointer. fcport = port structure pointer.
3688 *
3689 * Return: None.
3690 *
3691 * Context:
3692 */
e315cd28 3693void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3694 int do_login, int defer)
1da177e4 3695{
8ae6d9c7
GM		 3696 if (IS_QLAFX00(vha->hw)) {
3697 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3698 qla2x00_schedule_rport_del(vha, fcport, defer);
3699 return;
3700 }
3701
2c3dfe3f 3702 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3703 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3704 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3705 qla2x00_schedule_rport_del(vha, fcport, defer);
3706 }
fa2a1ce5 3707 /*
1da177e4
LT		 3708 * We may need to retry the login, so don't change the state of the
3709 * port but do the retries.
3710 */
3711 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3712 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3713
3714 if (!do_login)
3715 return;
3716
a1d0285e
AE		 3717 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3718
1da177e4 3719 if (fcport->login_retry == 0) {
e315cd28 3720 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3721
83548fe2 3722 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3723 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3724 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3725 }
3726}
3727
3728/*
3729 * qla2x00_mark_all_devices_lost
3730 * Updates fcport state when device goes offline.
3731 *
3732 * Input:
3733 * ha = adapter block pointer.
3734 * fcport = port structure pointer.
3735 *
3736 * Return:
3737 * None.
3738 *
3739 * Context:
3740 */
3741void
e315cd28 3742qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3743{
3744 fc_port_t *fcport;
3745
83548fe2
QT		 3746 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3747 "Mark all dev lost\n");
726b8548 3748
e315cd28 3749 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3750 fcport->scan_state = 0;
3751 qlt_schedule_sess_for_deletion_lock(fcport);
3752
c6d39e23 3753 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3754 continue;
0d6e61bc 3755
1da177e4
LT		 3756 /*
3757 * No point in marking the device as lost, if the device is
3758 * already DEAD.
3759 */
3760 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3761 continue;
e315cd28 3762 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3763 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3764 if (defer)
3765 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3766 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3767 qla2x00_schedule_rport_del(vha, fcport, defer);
3768 }
1da177e4
LT		 3769 }
3770}
3771
3772/*
3773* qla2x00_mem_alloc
3774* Allocates adapter memory.
3775*
3776* Returns:
3777* 0 = success.
e8711085 3778* !0 = failure.
1da177e4 3779*/
e8711085 3780static int
73208dfd
AC		 3781qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3782 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3783{
3784 char name[16];
1da177e4 3785
e8711085 3786 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3787 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3788 if (!ha->init_cb)
e315cd28 3789 goto fail;
e8711085 3790
2d70c103
NB		 3791 if (qlt_mem_alloc(ha) < 0)
3792 goto fail_free_init_cb;
3793
642ef983
CD		 3794 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3795 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3796 if (!ha->gid_list)
2d70c103 3797 goto fail_free_tgt_mem;
1da177e4 3798
e8711085
AV		 3799 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3800 if (!ha->srb_mempool)
e315cd28 3801 goto fail_free_gid_list;
e8711085 3802
7ec0effd 3803 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3804 /* Allocate cache for CT6 Ctx. */
3805 if (!ctx_cachep) {
3806 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3807 sizeof(struct ct6_dsd), 0,
3808 SLAB_HWCACHE_ALIGN, NULL);
3809 if (!ctx_cachep)
fc1ffd6c 3810 goto fail_free_srb_mempool;
a9083016
GM		 3811 }
3812 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3813 ctx_cachep);
3814 if (!ha->ctx_mempool)
3815 goto fail_free_srb_mempool;
7c3df132
SK		 3816 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3817 "ctx_cachep=%p ctx_mempool=%p.\n",
3818 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3819 }
3820
e8711085
AV		 3821 /* Get memory for cached NVRAM */
3822 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3823 if (!ha->nvram)
a9083016 3824 goto fail_free_ctx_mempool;
e8711085 3825
e315cd28
AC		 3826 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3827 ha->pdev->device);
3828 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3829 DMA_POOL_SIZE, 8, 0);
3830 if (!ha->s_dma_pool)
3831 goto fail_free_nvram;
3832
7c3df132
SK		 3833 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3834 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3835 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3836
7ec0effd 3837 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3838 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3839 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3840 if (!ha->dl_dma_pool) {
7c3df132
SK		 3841 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3842 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3843 goto fail_s_dma_pool;
3844 }
3845
3846 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3847 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3848 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3849 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3850 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3851 goto fail_dl_dma_pool;
3852 }
7c3df132
SK		 3853 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3854 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3855 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3856 }
3857
e8711085
AV		 3858 /* Allocate memory for SNS commands */
3859 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3860 /* Get consistent memory allocated for SNS commands */
e8711085 3861 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3862 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3863 if (!ha->sns_cmd)
e315cd28 3864 goto fail_dma_pool;
7c3df132 3865 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3866 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3867 } else {
e315cd28 3868 /* Get consistent memory allocated for MS IOCB */
e8711085 3869 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3870 &ha->ms_iocb_dma);
e8711085 3871 if (!ha->ms_iocb)
e315cd28
AC		 3872 goto fail_dma_pool;
3873 /* Get consistent memory allocated for CT SNS commands */
e8711085 3874 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3875 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3876 if (!ha->ct_sns)
3877 goto fail_free_ms_iocb;
7c3df132
SK		 3878 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3879 "ms_iocb=%p ct_sns=%p.\n",
3880 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3881 }
3882
e315cd28 3883 /* Allocate memory for request ring */
73208dfd
AC		 3884 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3885 if (!*req) {
7c3df132
SK		 3886 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3887 "Failed to allocate memory for req.\n");
e315cd28
AC		 3888 goto fail_req;
3889 }
73208dfd
AC		 3890 (*req)->length = req_len;
3891 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3892 ((*req)->length + 1) * sizeof(request_t),
3893 &(*req)->dma, GFP_KERNEL);
3894 if (!(*req)->ring) {
7c3df132
SK		 3895 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3896 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3897 goto fail_req_ring;
3898 }
3899 /* Allocate memory for response ring */
73208dfd
AC		 3900 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3901 if (!*rsp) {
7c3df132
SK		 3902 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3903 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3904 goto fail_rsp;
3905 }
73208dfd
AC		 3906 (*rsp)->hw = ha;
3907 (*rsp)->length = rsp_len;
3908 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3909 ((*rsp)->length + 1) * sizeof(response_t),
3910 &(*rsp)->dma, GFP_KERNEL);
3911 if (!(*rsp)->ring) {
7c3df132
SK		 3912 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3913 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3914 goto fail_rsp_ring;
3915 }
73208dfd
AC		 3916 (*req)->rsp = *rsp;
3917 (*rsp)->req = *req;
7c3df132
SK		 3918 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3919 "req=%p req->length=%d req->ring=%p rsp=%p "
3920 "rsp->length=%d rsp->ring=%p.\n",
3921 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3922 (*rsp)->ring);
73208dfd
AC		 3923 /* Allocate memory for NVRAM data for vports */
3924 if (ha->nvram_npiv_size) {
3925 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3926 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3927 if (!ha->npiv_info) {
7c3df132
SK		 3928 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3929 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3930 goto fail_npiv_info;
3931 }
3932 } else
3933 ha->npiv_info = NULL;
e8711085 3934
b64b0e8f 3935 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3936 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3937 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3938 &ha->ex_init_cb_dma);
3939 if (!ha->ex_init_cb)
3940 goto fail_ex_init_cb;
7c3df132
SK		 3941 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3942 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3943 }
3944
a9083016
GM		 3945 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3946
5ff1d584
AV		 3947 /* Get consistent memory allocated for Async Port-Database. */
3948 if (!IS_FWI2_CAPABLE(ha)) {
3949 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3950 &ha->async_pd_dma);
3951 if (!ha->async_pd)
3952 goto fail_async_pd;
7c3df132
SK		 3953 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3954 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3955 }
3956
e315cd28 3957 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3958
3959 /* Allocate memory for our loop_id bitmap */
3960 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3961 GFP_KERNEL);
3962 if (!ha->loop_id_map)
fc1ffd6c 3963 goto fail_loop_id_map;
5f16b331
CD		 3964 else {
3965 qla2x00_set_reserved_loop_ids(ha);
3966 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3967 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3968 }
3969
b2a72ec3 3970 return 0;
e315cd28 3971
fc1ffd6c
QT		 3972fail_loop_id_map:
3973 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3974fail_async_pd:
3975 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3976fail_ex_init_cb:
3977 kfree(ha->npiv_info);
73208dfd
AC		 3978fail_npiv_info:
3979 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3980 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3981 (*rsp)->ring = NULL;
3982 (*rsp)->dma = 0;
e315cd28 3983fail_rsp_ring:
73208dfd 3984 kfree(*rsp);
e315cd28 3985fail_rsp:
73208dfd
AC		 3986 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3987 sizeof(request_t), (*req)->ring, (*req)->dma);
3988 (*req)->ring = NULL;
3989 (*req)->dma = 0;
e315cd28 3990fail_req_ring:
73208dfd 3991 kfree(*req);
e315cd28
AC		 3992fail_req:
3993 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3994 ha->ct_sns, ha->ct_sns_dma);
3995 ha->ct_sns = NULL;
3996 ha->ct_sns_dma = 0;
e8711085
AV		 3997fail_free_ms_iocb:
3998 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3999 ha->ms_iocb = NULL;
4000 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4001
4002 if (ha->sns_cmd)
4003 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4004 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4005fail_dma_pool:
bad75002 4006 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4007 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4008 ha->fcp_cmnd_dma_pool = NULL;
4009 }
4010fail_dl_dma_pool:
bad75002 4011 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4012 dma_pool_destroy(ha->dl_dma_pool);
4013 ha->dl_dma_pool = NULL;
4014 }
4015fail_s_dma_pool:
e315cd28
AC		 4016 dma_pool_destroy(ha->s_dma_pool);
4017 ha->s_dma_pool = NULL;
e8711085
AV		 4018fail_free_nvram:
4019 kfree(ha->nvram);
4020 ha->nvram = NULL;
a9083016 4021fail_free_ctx_mempool:
fc1ffd6c
QT		 4022 if (ha->ctx_mempool)
4023 mempool_destroy(ha->ctx_mempool);
a9083016 4024 ha->ctx_mempool = NULL;
e8711085 4025fail_free_srb_mempool:
fc1ffd6c
QT		 4026 if (ha->srb_mempool)
4027 mempool_destroy(ha->srb_mempool);
e8711085 4028 ha->srb_mempool = NULL;
e8711085 4029fail_free_gid_list:
642ef983
CD		 4030 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4031 ha->gid_list,
e315cd28 4032 ha->gid_list_dma);
e8711085
AV		 4033 ha->gid_list = NULL;
4034 ha->gid_list_dma = 0;
2d70c103
NB		 4035fail_free_tgt_mem:
4036 qlt_mem_free(ha);
e315cd28
AC		 4037fail_free_init_cb:
4038 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4039 ha->init_cb_dma);
4040 ha->init_cb = NULL;
4041 ha->init_cb_dma = 0;
e8711085 4042fail:
7c3df132
SK		 4043 ql_log(ql_log_fatal, NULL, 0x0030,
4044 "Memory allocation failure.\n");
e8711085 4045 return -ENOMEM;
1da177e4
LT		 4046}
4047
b0d6cabd
HM		 4048int
4049qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4050{
4051 int rval;
4052 uint16_t size, max_cnt, temp;
4053 struct qla_hw_data *ha = vha->hw;
4054
4055 /* Return if we don't need to alloacate any extended logins */
4056 if (!ql2xexlogins)
4057 return QLA_SUCCESS;
4058
99e1b683
QT		 4059 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4060 return QLA_SUCCESS;
4061
b0d6cabd
HM		 4062 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4063 max_cnt = 0;
4064 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4065 if (rval != QLA_SUCCESS) {
4066 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4067 "Failed to get exlogin status.\n");
4068 return rval;
4069 }
4070
4071 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4072 temp *= size;
4073
4074 if (temp != ha->exlogin_size) {
4075 qla2x00_free_exlogin_buffer(ha);
4076 ha->exlogin_size = temp;
4077
4078 ql_log(ql_log_info, vha, 0xd024,
4079 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4080 max_cnt, size, temp);
4081
4082 ql_log(ql_log_info, vha, 0xd025,
4083 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4084
4085 /* Get consistent memory for extended logins */
4086 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4087 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4088 if (!ha->exlogin_buf) {
4089 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4090 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4091 return -ENOMEM;
4092 }
b0d6cabd
HM		 4093 }
4094
4095 /* Now configure the dma buffer */
4096 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4097 if (rval) {
83548fe2 4098 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4099 "Setup extended login buffer ****FAILED****.\n");
4100 qla2x00_free_exlogin_buffer(ha);
4101 }
4102
4103 return rval;
4104}
4105
4106/*
4107* qla2x00_free_exlogin_buffer
4108*
4109* Input:
4110* ha = adapter block pointer
4111*/
4112void
4113qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4114{
4115 if (ha->exlogin_buf) {
4116 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4117 ha->exlogin_buf, ha->exlogin_buf_dma);
4118 ha->exlogin_buf = NULL;
4119 ha->exlogin_size = 0;
4120 }
4121}
4122
99e1b683
QT		 4123static void
4124qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4125{
4126 u32 temp;
4127 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4128
4129 if (qla_ini_mode_enabled(vha)) {
4130 if (ql2xiniexchg > max_cnt)
4131 ql2xiniexchg = max_cnt;
4132
4133 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4134 *ret_cnt = ql2xiniexchg;
4135 } else if (qla_tgt_mode_enabled(vha)) {
4136 if (ql2xexchoffld > max_cnt)
4137 ql2xexchoffld = max_cnt;
4138
4139 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4140 *ret_cnt = ql2xexchoffld;
4141 } else if (qla_dual_mode_enabled(vha)) {
4142 temp = ql2xiniexchg + ql2xexchoffld;
4143 if (temp > max_cnt) {
4144 ql2xiniexchg -= (temp - max_cnt)/2;
4145 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4146 temp = max_cnt;
4147 }
4148
4149 if (temp > FW_DEF_EXCHANGES_CNT)
4150 *ret_cnt = temp;
4151 }
4152}
4153
2f56a7f1
HM		 4154int
4155qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4156{
4157 int rval;
99e1b683
QT		 4158 u16 size, max_cnt;
4159 u32 temp;
2f56a7f1
HM		 4160 struct qla_hw_data *ha = vha->hw;
4161
99e1b683
QT		 4162 if (!ha->flags.exchoffld_enabled)
4163 return QLA_SUCCESS;
4164
4165 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4166 return QLA_SUCCESS;
4167
4168 ql_log(ql_log_info, vha, 0xd014,
4169 "Exchange offload count: %d.\n", ql2xexlogins);
4170
4171 max_cnt = 0;
4172 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4173 if (rval != QLA_SUCCESS) {
4174 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4175 "Failed to get exlogin status.\n");
4176 return rval;
4177 }
4178
99e1b683
QT		 4179 qla2x00_number_of_exch(vha, &temp, max_cnt);
4180 temp *= size;
2f56a7f1 4181
99e1b683
QT		 4182 if (temp != ha->exchoffld_size) {
4183 qla2x00_free_exchoffld_buffer(ha);
4184 ha->exchoffld_size = temp;
4185
4186 ql_log(ql_log_info, vha, 0xd016,
4187 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4188 max_cnt, size, temp);
4189
4190 ql_log(ql_log_info, vha, 0xd017,
4191 "Exchange Buffers requested size = 0x%x\n",
4192 ha->exchoffld_size);
4193
4194 /* Get consistent memory for extended logins */
4195 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4196 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4197 if (!ha->exchoffld_buf) {
4198 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4199 "Failed to allocate memory for exchoffld_buf_dma.\n");
4200 return -ENOMEM;
4201 }
2f56a7f1
HM		 4202 }
4203
4204 /* Now configure the dma buffer */
99e1b683 4205 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4206 if (rval) {
4207 ql_log(ql_log_fatal, vha, 0xd02e,
4208 "Setup exchange offload buffer ****FAILED****.\n");
4209 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4210 } else {
4211 /* re-adjust number of target exchange */
4212 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4213
4214 if (qla_ini_mode_enabled(vha))
4215 icb->exchange_count = 0;
4216 else
4217 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4218 }
4219
4220 return rval;
4221}
4222
4223/*
4224* qla2x00_free_exchoffld_buffer
4225*
4226* Input:
4227* ha = adapter block pointer
4228*/
4229void
4230qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4231{
4232 if (ha->exchoffld_buf) {
4233 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4234 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4235 ha->exchoffld_buf = NULL;
4236 ha->exchoffld_size = 0;
4237 }
4238}
4239
1da177e4 4240/*
e30d1756
MI		 4241* qla2x00_free_fw_dump
4242* Frees fw dump stuff.
1da177e4
LT		 4243*
4244* Input:
7ec0effd 4245* ha = adapter block pointer
1da177e4 4246*/
a824ebb3 4247static void
e30d1756 4248qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4249{
df613b96 4250 if (ha->fce)
f73cb695
CD		 4251 dma_free_coherent(&ha->pdev->dev,
4252 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4253
f73cb695
CD		 4254 if (ha->eft)
4255 dma_free_coherent(&ha->pdev->dev,
4256 EFT_SIZE, ha->eft, ha->eft_dma);
4257
4258 if (ha->fw_dump)
a7a167bf 4259 vfree(ha->fw_dump);
f73cb695
CD		 4260 if (ha->fw_dump_template)
4261 vfree(ha->fw_dump_template);
4262
e30d1756
MI		 4263 ha->fce = NULL;
4264 ha->fce_dma = 0;
4265 ha->eft = NULL;
4266 ha->eft_dma = 0;
e30d1756 4267 ha->fw_dumped = 0;
61f098dd 4268 ha->fw_dump_cap_flags = 0;
e30d1756 4269 ha->fw_dump_reading = 0;
f73cb695
CD		 4270 ha->fw_dump = NULL;
4271 ha->fw_dump_len = 0;
4272 ha->fw_dump_template = NULL;
4273 ha->fw_dump_template_len = 0;
e30d1756
MI		 4274}
4275
4276/*
4277* qla2x00_mem_free
4278* Frees all adapter allocated memory.
4279*
4280* Input:
4281* ha = adapter block pointer.
4282*/
4283static void
4284qla2x00_mem_free(struct qla_hw_data *ha)
4285{
4286 qla2x00_free_fw_dump(ha);
4287
81178772
SK		 4288 if (ha->mctp_dump)
4289 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4290 ha->mctp_dump_dma);
4291
e30d1756
MI		 4292 if (ha->srb_mempool)
4293 mempool_destroy(ha->srb_mempool);
a7a167bf 4294
11bbc1d8
AV		 4295 if (ha->dcbx_tlv)
4296 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4297 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4298
ce0423f4
AV		 4299 if (ha->xgmac_data)
4300 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4301 ha->xgmac_data, ha->xgmac_data_dma);
4302
1da177e4
LT		 4303 if (ha->sns_cmd)
4304 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4305 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4306
4307 if (ha->ct_sns)
4308 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4309 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4310
88729e53
AV		 4311 if (ha->sfp_data)
4312 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4313
1da177e4
LT		 4314 if (ha->ms_iocb)
4315 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4316
b64b0e8f 4317 if (ha->ex_init_cb)
a9083016
GM		 4318 dma_pool_free(ha->s_dma_pool,
4319 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4320
5ff1d584
AV		 4321 if (ha->async_pd)
4322 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4323
1da177e4
LT		 4324 if (ha->s_dma_pool)
4325 dma_pool_destroy(ha->s_dma_pool);
4326
1da177e4 4327 if (ha->gid_list)
642ef983
CD		 4328 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4329 ha->gid_list, ha->gid_list_dma);
1da177e4 4330
a9083016
GM		 4331 if (IS_QLA82XX(ha)) {
4332 if (!list_empty(&ha->gbl_dsd_list)) {
4333 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4334
4335 /* clean up allocated prev pool */
4336 list_for_each_entry_safe(dsd_ptr,
4337 tdsd_ptr, &ha->gbl_dsd_list, list) {
4338 dma_pool_free(ha->dl_dma_pool,
4339 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4340 list_del(&dsd_ptr->list);
4341 kfree(dsd_ptr);
4342 }
4343 }
4344 }
4345
4346 if (ha->dl_dma_pool)
4347 dma_pool_destroy(ha->dl_dma_pool);
4348
4349 if (ha->fcp_cmnd_dma_pool)
4350 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4351
4352 if (ha->ctx_mempool)
4353 mempool_destroy(ha->ctx_mempool);
4354
2d70c103
NB		 4355 qlt_mem_free(ha);
4356
e315cd28
AC		 4357 if (ha->init_cb)
4358 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4359 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4360 vfree(ha->optrom_buffer);
4361 kfree(ha->nvram);
73208dfd 4362 kfree(ha->npiv_info);
7a67735b 4363 kfree(ha->swl);
5f16b331 4364 kfree(ha->loop_id_map);
1da177e4 4365
e8711085 4366 ha->srb_mempool = NULL;
a9083016 4367 ha->ctx_mempool = NULL;
1da177e4
LT		 4368 ha->sns_cmd = NULL;
4369 ha->sns_cmd_dma = 0;
4370 ha->ct_sns = NULL;
4371 ha->ct_sns_dma = 0;
4372 ha->ms_iocb = NULL;
4373 ha->ms_iocb_dma = 0;
1da177e4
LT		 4374 ha->init_cb = NULL;
4375 ha->init_cb_dma = 0;
b64b0e8f
AV		 4376 ha->ex_init_cb = NULL;
4377 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4378 ha->async_pd = NULL;
4379 ha->async_pd_dma = 0;
1da177e4
LT		 4380
4381 ha->s_dma_pool = NULL;
a9083016
GM		 4382 ha->dl_dma_pool = NULL;
4383 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4384
1da177e4
LT		 4385 ha->gid_list = NULL;
4386 ha->gid_list_dma = 0;
2d70c103
NB		 4387
4388 ha->tgt.atio_ring = NULL;
4389 ha->tgt.atio_dma = 0;
4390 ha->tgt.tgt_vp_map = NULL;
e315cd28 4391}
1da177e4 4392
e315cd28
AC		 4393struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4394 struct qla_hw_data *ha)
4395{
4396 struct Scsi_Host *host;
4397 struct scsi_qla_host *vha = NULL;
854165f4 4398
e315cd28 4399 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4400 if (!host) {
7c3df132
SK		 4401 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4402 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4403 return NULL;
e315cd28
AC		 4404 }
4405
4406 /* Clear our data area */
4407 vha = shost_priv(host);
4408 memset(vha, 0, sizeof(scsi_qla_host_t));
4409
4410 vha->host = host;
4411 vha->host_no = host->host_no;
4412 vha->hw = ha;
4413
4414 INIT_LIST_HEAD(&vha->vp_fcports);
4415 INIT_LIST_HEAD(&vha->work_list);
4416 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4417 INIT_LIST_HEAD(&vha->qla_cmd_list);
4418 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4419 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4420 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4421 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4422 INIT_LIST_HEAD(&vha->gnl.fcports);
e315cd28 4423
f999f4c1 4424 spin_lock_init(&vha->work_lock);
8b2f5ff3 4425 spin_lock_init(&vha->cmd_list_lock);
726b8548 4426 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4427 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4428
2fdbc65e
BVA		 4429 vha->gnl.size = sizeof(struct get_name_list_extended) *
4430 (ha->max_loop_id + 1);
41dc529a
QT		 4431 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4432 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4433 if (!vha->gnl.l) {
83548fe2 4434 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4435 "Alloc failed for name list.\n");
4436 scsi_remove_host(vha->host);
4437 return NULL;
4438 }
f999f4c1 4439
e315cd28 4440 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4441 ql_dbg(ql_dbg_init, vha, 0x0041,
4442 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4443 vha->host, vha->hw, vha,
4444 dev_name(&(ha->pdev->dev)));
4445
e315cd28 4446 return vha;
1da177e4
LT		 4447}
4448
726b8548 4449struct qla_work_evt *
f999f4c1 4450qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4451{
4452 struct qla_work_evt *e;
feafb7b1
AE		 4453 uint8_t bail;
4454
4455 QLA_VHA_MARK_BUSY(vha, bail);
4456 if (bail)
4457 return NULL;
0971de7f 4458
f999f4c1 4459 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4460 if (!e) {
4461 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4462 return NULL;
feafb7b1 4463 }
0971de7f
AV		 4464
4465 INIT_LIST_HEAD(&e->list);
4466 e->type = type;
4467 e->flags = QLA_EVT_FLAG_FREE;
4468 return e;
4469}
4470
726b8548 4471int
f999f4c1 4472qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4473{
f999f4c1 4474 unsigned long flags;
0971de7f 4475
f999f4c1 4476 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4477 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4478 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4479
4480 if (QLA_EARLY_LINKUP(vha->hw))
4481 schedule_work(&vha->iocb_work);
4482 else
4483 qla2xxx_wake_dpc(vha);
f999f4c1 4484
0971de7f
AV		 4485 return QLA_SUCCESS;
4486}
4487
4488int
e315cd28 4489qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4490 u32 data)
4491{
4492 struct qla_work_evt *e;
4493
f999f4c1 4494 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4495 if (!e)
4496 return QLA_FUNCTION_FAILED;
4497
4498 e->u.aen.code = code;
4499 e->u.aen.data = data;
f999f4c1 4500 return qla2x00_post_work(vha, e);
0971de7f
AV		 4501}
4502
8a659571
AV		 4503int
4504qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4505{
4506 struct qla_work_evt *e;
4507
f999f4c1 4508 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4509 if (!e)
4510 return QLA_FUNCTION_FAILED;
4511
4512 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4513 return qla2x00_post_work(vha, e);
8a659571
AV		 4514}
4515
ac280b67
AV		 4516#define qla2x00_post_async_work(name, type) \
4517int qla2x00_post_async_##name##_work( \
4518 struct scsi_qla_host *vha, \
4519 fc_port_t *fcport, uint16_t *data) \
4520{ \
4521 struct qla_work_evt *e; \
4522 \
4523 e = qla2x00_alloc_work(vha, type); \
4524 if (!e) \
4525 return QLA_FUNCTION_FAILED; \
4526 \
4527 e->u.logio.fcport = fcport; \
4528 if (data) { \
4529 e->u.logio.data[0] = data[0]; \
4530 e->u.logio.data[1] = data[1]; \
4531 } \
4532 return qla2x00_post_work(vha, e); \
4533}
4534
4535qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4536qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4537qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4538qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4539qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4540
3420d36c
AV		 4541int
4542qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4543{
4544 struct qla_work_evt *e;
4545
4546 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4547 if (!e)
4548 return QLA_FUNCTION_FAILED;
4549
4550 e->u.uevent.code = code;
4551 return qla2x00_post_work(vha, e);
4552}
4553
4554static void
4555qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4556{
4557 char event_string[40];
4558 char *envp[] = { event_string, NULL };
4559
4560 switch (code) {
4561 case QLA_UEVENT_CODE_FW_DUMP:
4562 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4563 vha->host_no);
4564 break;
4565 default:
4566 /* do nothing */
4567 break;
4568 }
4569 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4570}
4571
8ae6d9c7
GM		 4572int
4573qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4574 uint32_t *data, int cnt)
4575{
4576 struct qla_work_evt *e;
4577
4578 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4579 if (!e)
4580 return QLA_FUNCTION_FAILED;
4581
4582 e->u.aenfx.evtcode = evtcode;
4583 e->u.aenfx.count = cnt;
4584 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4585 return qla2x00_post_work(vha, e);
4586}
4587
726b8548
QT		 4588int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4589{
4590 struct qla_work_evt *e;
4591
4592 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4593 if (!e)
4594 return QLA_FUNCTION_FAILED;
4595
4596 e->u.fcport.fcport = fcport;
4597 return qla2x00_post_work(vha, e);
4598}
4599
4600static
4601void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4602{
4603 unsigned long flags;
4604 fc_port_t *fcport = NULL;
4605 struct qlt_plogi_ack_t *pla =
4606 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4607
4608 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4609 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4610 if (fcport) {
4611 fcport->d_id = e->u.new_sess.id;
4612 if (pla) {
4613 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4614 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4615 /* we took an extra ref_count to prevent PLOGI ACK when
4616 * fcport/sess has not been created.
4617 */
4618 pla->ref_count--;
4619 }
4620 } else {
4621 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4622 if (fcport) {
4623 fcport->d_id = e->u.new_sess.id;
4624 fcport->scan_state = QLA_FCPORT_FOUND;
4625 fcport->flags |= FCF_FABRIC_DEVICE;
4626 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4627
4628 memcpy(fcport->port_name, e->u.new_sess.port_name,
4629 WWN_SIZE);
4630 list_add_tail(&fcport->list, &vha->vp_fcports);
4631
4632 if (pla) {
4633 qlt_plogi_ack_link(vha, pla, fcport,
4634 QLT_PLOGI_LINK_SAME_WWN);
4635 pla->ref_count--;
4636 }
4637 }
4638 }
4639 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4640
4641 if (fcport) {
4642 if (pla)
4643 qlt_plogi_ack_unref(vha, pla);
4644 else
4645 qla24xx_async_gnl(vha, fcport);
4646 }
4647}
4648
ac280b67 4649void
e315cd28 4650qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4651{
f999f4c1
AV		 4652 struct qla_work_evt *e, *tmp;
4653 unsigned long flags;
4654 LIST_HEAD(work);
0971de7f 4655
f999f4c1
AV		 4656 spin_lock_irqsave(&vha->work_lock, flags);
4657 list_splice_init(&vha->work_list, &work);
4658 spin_unlock_irqrestore(&vha->work_lock, flags);
4659
4660 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4661 list_del_init(&e->list);
0971de7f
AV		 4662
4663 switch (e->type) {
4664 case QLA_EVT_AEN:
e315cd28 4665 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4666 e->u.aen.code, e->u.aen.data);
4667 break;
8a659571
AV		 4668 case QLA_EVT_IDC_ACK:
4669 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4670 break;
ac280b67
AV		 4671 case QLA_EVT_ASYNC_LOGIN:
4672 qla2x00_async_login(vha, e->u.logio.fcport,
4673 e->u.logio.data);
4674 break;
ac280b67
AV		 4675 case QLA_EVT_ASYNC_LOGOUT:
4676 qla2x00_async_logout(vha, e->u.logio.fcport);
4677 break;
4678 case QLA_EVT_ASYNC_LOGOUT_DONE:
4679 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4680 e->u.logio.data);
4681 break;
5ff1d584
AV		 4682 case QLA_EVT_ASYNC_ADISC:
4683 qla2x00_async_adisc(vha, e->u.logio.fcport,
4684 e->u.logio.data);
4685 break;
4686 case QLA_EVT_ASYNC_ADISC_DONE:
4687 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4688 e->u.logio.data);
4689 break;
3420d36c
AV		 4690 case QLA_EVT_UEVENT:
4691 qla2x00_uevent_emit(vha, e->u.uevent.code);
4692 break;
8ae6d9c7
GM		 4693 case QLA_EVT_AENFX:
4694 qlafx00_process_aen(vha, e);
4695 break;
726b8548
QT		 4696 case QLA_EVT_GIDPN:
4697 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4698 break;
4699 case QLA_EVT_GPNID:
4700 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4701 break;
4702 case QLA_EVT_GPNID_DONE:
4703 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4704 break;
4705 case QLA_EVT_NEW_SESS:
4706 qla24xx_create_new_sess(vha, e);
4707 break;
4708 case QLA_EVT_GPDB:
4709 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4710 e->u.fcport.opt);
4711 break;
4712 case QLA_EVT_GPSC:
4713 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4714 break;
4715 case QLA_EVT_UPD_FCPORT:
4716 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4717 break;
4718 case QLA_EVT_GNL:
4719 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4720 break;
4721 case QLA_EVT_NACK:
4722 qla24xx_do_nack_work(vha, e);
4723 break;
0971de7f
AV		 4724 }
4725 if (e->flags & QLA_EVT_FLAG_FREE)
4726 kfree(e);
feafb7b1
AE		 4727
4728 /* For each work completed decrement vha ref count */
4729 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4730 }
e315cd28 4731}
f999f4c1 4732
e315cd28
AC		 4733/* Relogins all the fcports of a vport
4734 * Context: dpc thread
4735 */
4736void qla2x00_relogin(struct scsi_qla_host *vha)
4737{
4738 fc_port_t *fcport;
c6b2fca8 4739 int status;
726b8548 4740 struct event_arg ea;
e315cd28
AC		 4741
4742 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4743 /*
4744 * If the port is not ONLINE then try to login
4745 * to it if we haven't run out of retries.
4746 */
5ff1d584
AV		 4747 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4748 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4749 fcport->login_retry--;
e315cd28 4750 if (fcport->flags & FCF_FABRIC_DEVICE) {
83548fe2 4751 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4752 "%s %8phC DS %d LS %d\n", __func__,
4753 fcport->port_name, fcport->disc_state,
4754 fcport->fw_login_state);
4755 memset(&ea, 0, sizeof(ea));
4756 ea.event = FCME_RELOGIN;
4757 ea.fcport = fcport;
4758 qla2x00_fcport_event_handler(vha, &ea);
4759 } else {
e315cd28
AC		 4760 status = qla2x00_local_device_login(vha,
4761 fcport);
726b8548
QT		 4762 if (status == QLA_SUCCESS) {
4763 fcport->old_loop_id = fcport->loop_id;
4764 ql_dbg(ql_dbg_disc, vha, 0x2003,
4765 "Port login OK: logged in ID 0x%x.\n",
4766 fcport->loop_id);
4767 qla2x00_update_fcport(vha, fcport);
4768 } else if (status == 1) {
4769 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4770 /* retry the login again */
4771 ql_dbg(ql_dbg_disc, vha, 0x2007,
4772 "Retrying %d login again loop_id 0x%x.\n",
4773 fcport->login_retry,
4774 fcport->loop_id);
4775 } else {
4776 fcport->login_retry = 0;
4777 }
e315cd28 4778
726b8548
QT		 4779 if (fcport->login_retry == 0 &&
4780 status != QLA_SUCCESS)
4781 qla2x00_clear_loop_id(fcport);
e315cd28 4782 }
e315cd28
AC		 4783 }
4784 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4785 break;
0971de7f 4786 }
0971de7f
AV		 4787}
4788
7d613ac6
SV		 4789/* Schedule work on any of the dpc-workqueues */
4790void
4791qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4792{
4793 struct qla_hw_data *ha = base_vha->hw;
4794
4795 switch (work_code) {
4796 case MBA_IDC_AEN: /* 0x8200 */
4797 if (ha->dpc_lp_wq)
4798 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4799 break;
4800
4801 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4802 if (!ha->flags.nic_core_reset_hdlr_active) {
4803 if (ha->dpc_hp_wq)
4804 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4805 } else
4806 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4807 "NIC Core reset is already active. Skip "
4808 "scheduling it again.\n");
4809 break;
4810 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4811 if (ha->dpc_hp_wq)
4812 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4813 break;
4814 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4815 if (ha->dpc_hp_wq)
4816 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4817 break;
4818 default:
4819 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4820 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4821 }
4822
4823 return;
4824}
4825
4826/* Work: Perform NIC Core Unrecoverable state handling */
4827void
4828qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4829{
4830 struct qla_hw_data *ha =
2ad1b67c 4831 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4832 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4833 uint32_t dev_state = 0;
4834
4835 qla83xx_idc_lock(base_vha, 0);
4836 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4837 qla83xx_reset_ownership(base_vha);
4838 if (ha->flags.nic_core_reset_owner) {
4839 ha->flags.nic_core_reset_owner = 0;
4840 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4841 QLA8XXX_DEV_FAILED);
4842 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4843 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4844 }
4845 qla83xx_idc_unlock(base_vha, 0);
4846}
4847
4848/* Work: Execute IDC state handler */
4849void
4850qla83xx_idc_state_handler_work(struct work_struct *work)
4851{
4852 struct qla_hw_data *ha =
2ad1b67c 4853 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4854 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4855 uint32_t dev_state = 0;
4856
4857 qla83xx_idc_lock(base_vha, 0);
4858 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4859 if (dev_state == QLA8XXX_DEV_FAILED ||
4860 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4861 qla83xx_idc_state_handler(base_vha);
4862 qla83xx_idc_unlock(base_vha, 0);
4863}
4864
fa492630 4865static int
7d613ac6
SV		 4866qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4867{
4868 int rval = QLA_SUCCESS;
4869 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4870 uint32_t heart_beat_counter1, heart_beat_counter2;
4871
4872 do {
4873 if (time_after(jiffies, heart_beat_wait)) {
4874 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4875 "Nic Core f/w is not alive.\n");
4876 rval = QLA_FUNCTION_FAILED;
4877 break;
4878 }
4879
4880 qla83xx_idc_lock(base_vha, 0);
4881 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4882 &heart_beat_counter1);
4883 qla83xx_idc_unlock(base_vha, 0);
4884 msleep(100);
4885 qla83xx_idc_lock(base_vha, 0);
4886 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4887 &heart_beat_counter2);
4888 qla83xx_idc_unlock(base_vha, 0);
4889 } while (heart_beat_counter1 == heart_beat_counter2);
4890
4891 return rval;
4892}
4893
4894/* Work: Perform NIC Core Reset handling */
4895void
4896qla83xx_nic_core_reset_work(struct work_struct *work)
4897{
4898 struct qla_hw_data *ha =
4899 container_of(work, struct qla_hw_data, nic_core_reset);
4900 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4901 uint32_t dev_state = 0;
4902
81178772
SK		 4903 if (IS_QLA2031(ha)) {
4904 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4905 ql_log(ql_log_warn, base_vha, 0xb081,
4906 "Failed to dump mctp\n");
4907 return;
4908 }
4909
7d613ac6
SV		 4910 if (!ha->flags.nic_core_reset_hdlr_active) {
4911 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4912 qla83xx_idc_lock(base_vha, 0);
4913 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4914 &dev_state);
4915 qla83xx_idc_unlock(base_vha, 0);
4916 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4917 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4918 "Nic Core f/w is alive.\n");
4919 return;
4920 }
4921 }
4922
4923 ha->flags.nic_core_reset_hdlr_active = 1;
4924 if (qla83xx_nic_core_reset(base_vha)) {
4925 /* NIC Core reset failed. */
4926 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4927 "NIC Core reset failed.\n");
4928 }
4929 ha->flags.nic_core_reset_hdlr_active = 0;
4930 }
4931}
4932
4933/* Work: Handle 8200 IDC aens */
4934void
4935qla83xx_service_idc_aen(struct work_struct *work)
4936{
4937 struct qla_hw_data *ha =
4938 container_of(work, struct qla_hw_data, idc_aen);
4939 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4940 uint32_t dev_state, idc_control;
4941
4942 qla83xx_idc_lock(base_vha, 0);
4943 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4944 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4945 qla83xx_idc_unlock(base_vha, 0);
4946 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4947 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4948 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4949 "Application requested NIC Core Reset.\n");
4950 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4951 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4952 QLA_SUCCESS) {
4953 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4954 "Other protocol driver requested NIC Core Reset.\n");
4955 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4956 }
4957 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4958 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4959 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4960 }
4961}
4962
4963static void
4964qla83xx_wait_logic(void)
4965{
4966 int i;
4967
4968 /* Yield CPU */
4969 if (!in_interrupt()) {
4970 /*
4971 * Wait about 200ms before retrying again.
4972 * This controls the number of retries for single
4973 * lock operation.
4974 */
4975 msleep(100);
4976 schedule();
4977 } else {
4978 for (i = 0; i < 20; i++)
4979 cpu_relax(); /* This a nop instr on i386 */
4980 }
4981}
4982
fa492630 4983static int
7d613ac6
SV		 4984qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4985{
4986 int rval;
4987 uint32_t data;
4988 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4989 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4990 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4991 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4992 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4993
4994 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4995 if (rval)
4996 return rval;
4997
4998 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4999 return QLA_SUCCESS;
5000 } else {
5001 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5002 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5003 data);
5004 if (rval)
5005 return rval;
5006
5007 msleep(200);
5008
5009 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5010 &data);
5011 if (rval)
5012 return rval;
5013
5014 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5015 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5016 ~(idc_lck_rcvry_stage_mask));
5017 rval = qla83xx_wr_reg(base_vha,
5018 QLA83XX_IDC_LOCK_RECOVERY, data);
5019 if (rval)
5020 return rval;
5021
5022 /* Forcefully perform IDC UnLock */
5023 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5024 &data);
5025 if (rval)
5026 return rval;
5027 /* Clear lock-id by setting 0xff */
5028 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5029 0xff);
5030 if (rval)
5031 return rval;
5032 /* Clear lock-recovery by setting 0x0 */
5033 rval = qla83xx_wr_reg(base_vha,
5034 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5035 if (rval)
5036 return rval;
5037 } else
5038 return QLA_SUCCESS;
5039 }
5040
5041 return rval;
5042}
5043
fa492630 5044static int
7d613ac6
SV		 5045qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5046{
5047 int rval = QLA_SUCCESS;
5048 uint32_t o_drv_lockid, n_drv_lockid;
5049 unsigned long lock_recovery_timeout;
5050
5051 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5052retry_lockid:
5053 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5054 if (rval)
5055 goto exit;
5056
5057 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5058 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5059 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5060 return QLA_SUCCESS;
5061 else
5062 return QLA_FUNCTION_FAILED;
5063 }
5064
5065 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5066 if (rval)
5067 goto exit;
5068
5069 if (o_drv_lockid == n_drv_lockid) {
5070 qla83xx_wait_logic();
5071 goto retry_lockid;
5072 } else
5073 return QLA_SUCCESS;
5074
5075exit:
5076 return rval;
5077}
5078
5079void
5080qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5081{
5082 uint16_t options = (requester_id << 15) | BIT_6;
5083 uint32_t data;
6c315553 5084 uint32_t lock_owner;
7d613ac6
SV		 5085 struct qla_hw_data *ha = base_vha->hw;
5086
5087 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5088retry_lock:
5089 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5090 == QLA_SUCCESS) {
5091 if (data) {
5092 /* Setting lock-id to our function-number */
5093 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5094 ha->portnum);
5095 } else {
6c315553
SK		 5096 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5097 &lock_owner);
7d613ac6 5098 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5099 "Failed to acquire IDC lock, acquired by %d, "
5100 "retrying...\n", lock_owner);
7d613ac6
SV		 5101
5102 /* Retry/Perform IDC-Lock recovery */
5103 if (qla83xx_idc_lock_recovery(base_vha)
5104 == QLA_SUCCESS) {
5105 qla83xx_wait_logic();
5106 goto retry_lock;
5107 } else
5108 ql_log(ql_log_warn, base_vha, 0xb075,
5109 "IDC Lock recovery FAILED.\n");
5110 }
5111
5112 }
5113
5114 return;
5115
5116 /* XXX: IDC-lock implementation using access-control mbx */
5117retry_lock2:
5118 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5119 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5120 "Failed to acquire IDC lock. retrying...\n");
5121 /* Retry/Perform IDC-Lock recovery */
5122 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5123 qla83xx_wait_logic();
5124 goto retry_lock2;
5125 } else
5126 ql_log(ql_log_warn, base_vha, 0xb076,
5127 "IDC Lock recovery FAILED.\n");
5128 }
5129
5130 return;
5131}
5132
5133void
5134qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5135{
5897cb2f
BVA		 5136#if 0
5137 uint16_t options = (requester_id << 15) | BIT_7;
5138#endif
5139 uint16_t retry;
7d613ac6
SV		 5140 uint32_t data;
5141 struct qla_hw_data *ha = base_vha->hw;
5142
5143 /* IDC-unlock implementation using driver-unlock/lock-id
5144 * remote registers
5145 */
5146 retry = 0;
5147retry_unlock:
5148 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5149 == QLA_SUCCESS) {
5150 if (data == ha->portnum) {
5151 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5152 /* Clearing lock-id by setting 0xff */
5153 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5154 } else if (retry < 10) {
5155 /* SV: XXX: IDC unlock retrying needed here? */
5156
5157 /* Retry for IDC-unlock */
5158 qla83xx_wait_logic();
5159 retry++;
5160 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5161 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5162 goto retry_unlock;
5163 }
5164 } else if (retry < 10) {
5165 /* Retry for IDC-unlock */
5166 qla83xx_wait_logic();
5167 retry++;
5168 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5169 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5170 goto retry_unlock;
5171 }
5172
5173 return;
5174
5897cb2f 5175#if 0
7d613ac6
SV		 5176 /* XXX: IDC-unlock implementation using access-control mbx */
5177 retry = 0;
5178retry_unlock2:
5179 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5180 if (retry < 10) {
5181 /* Retry for IDC-unlock */
5182 qla83xx_wait_logic();
5183 retry++;
5184 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5185 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5186 goto retry_unlock2;
5187 }
5188 }
5189
5190 return;
5897cb2f 5191#endif
7d613ac6
SV		 5192}
5193
5194int
5195__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5196{
5197 int rval = QLA_SUCCESS;
5198 struct qla_hw_data *ha = vha->hw;
5199 uint32_t drv_presence;
5200
5201 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5202 if (rval == QLA_SUCCESS) {
5203 drv_presence |= (1 << ha->portnum);
5204 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5205 drv_presence);
5206 }
5207
5208 return rval;
5209}
5210
5211int
5212qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5213{
5214 int rval = QLA_SUCCESS;
5215
5216 qla83xx_idc_lock(vha, 0);
5217 rval = __qla83xx_set_drv_presence(vha);
5218 qla83xx_idc_unlock(vha, 0);
5219
5220 return rval;
5221}
5222
5223int
5224__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5225{
5226 int rval = QLA_SUCCESS;
5227 struct qla_hw_data *ha = vha->hw;
5228 uint32_t drv_presence;
5229
5230 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5231 if (rval == QLA_SUCCESS) {
5232 drv_presence &= ~(1 << ha->portnum);
5233 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5234 drv_presence);
5235 }
5236
5237 return rval;
5238}
5239
5240int
5241qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5242{
5243 int rval = QLA_SUCCESS;
5244
5245 qla83xx_idc_lock(vha, 0);
5246 rval = __qla83xx_clear_drv_presence(vha);
5247 qla83xx_idc_unlock(vha, 0);
5248
5249 return rval;
5250}
5251
fa492630 5252static void
7d613ac6
SV		 5253qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5254{
5255 struct qla_hw_data *ha = vha->hw;
5256 uint32_t drv_ack, drv_presence;
5257 unsigned long ack_timeout;
5258
5259 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5260 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5261 while (1) {
5262 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5263 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5264 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5265 break;
5266
5267 if (time_after_eq(jiffies, ack_timeout)) {
5268 ql_log(ql_log_warn, vha, 0xb067,
5269 "RESET ACK TIMEOUT! drv_presence=0x%x "
5270 "drv_ack=0x%x\n", drv_presence, drv_ack);
5271 /*
5272 * The function(s) which did not ack in time are forced
5273 * to withdraw any further participation in the IDC
5274 * reset.
5275 */
5276 if (drv_ack != drv_presence)
5277 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5278 drv_ack);
5279 break;
5280 }
5281
5282 qla83xx_idc_unlock(vha, 0);
5283 msleep(1000);
5284 qla83xx_idc_lock(vha, 0);
5285 }
5286
5287 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5288 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5289}
5290
fa492630 5291static int
7d613ac6
SV		 5292qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5293{
5294 int rval = QLA_SUCCESS;
5295 uint32_t idc_control;
5296
5297 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5298 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5299
5300 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5301 __qla83xx_get_idc_control(vha, &idc_control);
5302 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5303 __qla83xx_set_idc_control(vha, 0);
5304
5305 qla83xx_idc_unlock(vha, 0);
5306 rval = qla83xx_restart_nic_firmware(vha);
5307 qla83xx_idc_lock(vha, 0);
5308
5309 if (rval != QLA_SUCCESS) {
5310 ql_log(ql_log_fatal, vha, 0xb06a,
5311 "Failed to restart NIC f/w.\n");
5312 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5313 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5314 } else {
5315 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5316 "Success in restarting nic f/w.\n");
5317 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5318 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5319 }
5320
5321 return rval;
5322}
5323
5324/* Assumes idc_lock always held on entry */
5325int
5326qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5327{
5328 struct qla_hw_data *ha = base_vha->hw;
5329 int rval = QLA_SUCCESS;
5330 unsigned long dev_init_timeout;
5331 uint32_t dev_state;
5332
5333 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5334 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5335
5336 while (1) {
5337
5338 if (time_after_eq(jiffies, dev_init_timeout)) {
5339 ql_log(ql_log_warn, base_vha, 0xb06e,
5340 "Initialization TIMEOUT!\n");
5341 /* Init timeout. Disable further NIC Core
5342 * communication.
5343 */
5344 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5345 QLA8XXX_DEV_FAILED);
5346 ql_log(ql_log_info, base_vha, 0xb06f,
5347 "HW State: FAILED.\n");
5348 }
5349
5350 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5351 switch (dev_state) {
5352 case QLA8XXX_DEV_READY:
5353 if (ha->flags.nic_core_reset_owner)
5354 qla83xx_idc_audit(base_vha,
5355 IDC_AUDIT_COMPLETION);
5356 ha->flags.nic_core_reset_owner = 0;
5357 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5358 "Reset_owner reset by 0x%x.\n",
5359 ha->portnum);
5360 goto exit;
5361 case QLA8XXX_DEV_COLD:
5362 if (ha->flags.nic_core_reset_owner)
5363 rval = qla83xx_device_bootstrap(base_vha);
5364 else {
5365 /* Wait for AEN to change device-state */
5366 qla83xx_idc_unlock(base_vha, 0);
5367 msleep(1000);
5368 qla83xx_idc_lock(base_vha, 0);
5369 }
5370 break;
5371 case QLA8XXX_DEV_INITIALIZING:
5372 /* Wait for AEN to change device-state */
5373 qla83xx_idc_unlock(base_vha, 0);
5374 msleep(1000);
5375 qla83xx_idc_lock(base_vha, 0);
5376 break;
5377 case QLA8XXX_DEV_NEED_RESET:
5378 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5379 qla83xx_need_reset_handler(base_vha);
5380 else {
5381 /* Wait for AEN to change device-state */
5382 qla83xx_idc_unlock(base_vha, 0);
5383 msleep(1000);
5384 qla83xx_idc_lock(base_vha, 0);
5385 }
5386 /* reset timeout value after need reset handler */
5387 dev_init_timeout = jiffies +
5388 (ha->fcoe_dev_init_timeout * HZ);
5389 break;
5390 case QLA8XXX_DEV_NEED_QUIESCENT:
5391 /* XXX: DEBUG for now */
5392 qla83xx_idc_unlock(base_vha, 0);
5393 msleep(1000);
5394 qla83xx_idc_lock(base_vha, 0);
5395 break;
5396 case QLA8XXX_DEV_QUIESCENT:
5397 /* XXX: DEBUG for now */
5398 if (ha->flags.quiesce_owner)
5399 goto exit;
5400
5401 qla83xx_idc_unlock(base_vha, 0);
5402 msleep(1000);
5403 qla83xx_idc_lock(base_vha, 0);
5404 dev_init_timeout = jiffies +
5405 (ha->fcoe_dev_init_timeout * HZ);
5406 break;
5407 case QLA8XXX_DEV_FAILED:
5408 if (ha->flags.nic_core_reset_owner)
5409 qla83xx_idc_audit(base_vha,
5410 IDC_AUDIT_COMPLETION);
5411 ha->flags.nic_core_reset_owner = 0;
5412 __qla83xx_clear_drv_presence(base_vha);
5413 qla83xx_idc_unlock(base_vha, 0);
5414 qla8xxx_dev_failed_handler(base_vha);
5415 rval = QLA_FUNCTION_FAILED;
5416 qla83xx_idc_lock(base_vha, 0);
5417 goto exit;
5418 case QLA8XXX_BAD_VALUE:
5419 qla83xx_idc_unlock(base_vha, 0);
5420 msleep(1000);
5421 qla83xx_idc_lock(base_vha, 0);
5422 break;
5423 default:
5424 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5425 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5426 qla83xx_idc_unlock(base_vha, 0);
5427 qla8xxx_dev_failed_handler(base_vha);
5428 rval = QLA_FUNCTION_FAILED;
5429 qla83xx_idc_lock(base_vha, 0);
5430 goto exit;
5431 }
5432 }
5433
5434exit:
5435 return rval;
5436}
5437
f3ddac19
CD		 5438void
5439qla2x00_disable_board_on_pci_error(struct work_struct *work)
5440{
5441 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5442 board_disable);
5443 struct pci_dev *pdev = ha->pdev;
5444 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5445
726b8548
QT		 5446 /*
5447 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5448 * where it was set first.
5449 */
5450 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5451 return;
5452
f3ddac19
CD		 5453 ql_log(ql_log_warn, base_vha, 0x015b,
5454 "Disabling adapter.\n");
5455
726b8548
QT		 5456 qla2x00_wait_for_sess_deletion(base_vha);
5457
f3ddac19
CD		 5458 set_bit(UNLOADING, &base_vha->dpc_flags);
5459
5460 qla2x00_delete_all_vps(ha, base_vha);
5461
5462 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5463
5464 qla2x00_dfs_remove(base_vha);
5465
5466 qla84xx_put_chip(base_vha);
5467
5468 if (base_vha->timer_active)
5469 qla2x00_stop_timer(base_vha);
5470
5471 base_vha->flags.online = 0;
5472
5473 qla2x00_destroy_deferred_work(ha);
5474
5475 /*
5476 * Do not try to stop beacon blink as it will issue a mailbox
5477 * command.
5478 */
5479 qla2x00_free_sysfs_attr(base_vha, false);
5480
5481 fc_remove_host(base_vha->host);
5482
5483 scsi_remove_host(base_vha->host);
5484
5485 base_vha->flags.init_done = 0;
5486 qla25xx_delete_queues(base_vha);
f3ddac19 5487 qla2x00_free_fcports(base_vha);
093df737 5488 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5489 qla2x00_mem_free(ha);
5490 qla82xx_md_free(base_vha);
5491 qla2x00_free_queues(ha);
5492
f3ddac19
CD		 5493 qla2x00_unmap_iobases(ha);
5494
5495 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5496 pci_disable_pcie_error_reporting(pdev);
5497 pci_disable_device(pdev);
f3ddac19 5498
beb9e315
JL		 5499 /*
5500 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5501 */
f3ddac19
CD		 5502}
5503
1da177e4
LT		 5504/**************************************************************************
5505* qla2x00_do_dpc
5506* This kernel thread is a task that is schedule by the interrupt handler
5507* to perform the background processing for interrupts.
5508*
5509* Notes:
5510* This task always run in the context of a kernel thread. It
5511* is kick-off by the driver's detect code and starts up
5512* up one per adapter. It immediately goes to sleep and waits for
5513* some fibre event. When either the interrupt handler or
5514* the timer routine detects a event it will one of the task
5515* bits then wake us up.
5516**************************************************************************/
5517static int
5518qla2x00_do_dpc(void *data)
5519{
e315cd28
AC		 5520 scsi_qla_host_t *base_vha;
5521 struct qla_hw_data *ha;
d7459527
MH		 5522 uint32_t online;
5523 struct qla_qpair *qpair;
1da177e4 5524
e315cd28
AC		 5525 ha = (struct qla_hw_data *)data;
5526 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5527
8698a745 5528 set_user_nice(current, MIN_NICE);
1da177e4 5529
563585ec 5530 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5531 while (!kthread_should_stop()) {
7c3df132
SK		 5532 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5533 "DPC handler sleeping.\n");
1da177e4 5534
39a11240 5535 schedule();
1da177e4 5536
c142caf0
AV		 5537 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5538 goto end_loop;
1da177e4 5539
85880801 5540 if (ha->flags.eeh_busy) {
7c3df132
SK		 5541 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5542 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5543 goto end_loop;
85880801
AV		 5544 }
5545
1da177e4
LT		 5546 ha->dpc_active = 1;
5547
5f28d2d7
SK		 5548 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5549 "DPC handler waking up, dpc_flags=0x%lx.\n",
5550 base_vha->dpc_flags);
1da177e4 5551
a29b3dd7
JC		 5552 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5553 break;
5554
e315cd28 5555 qla2x00_do_work(base_vha);
0971de7f 5556
7ec0effd
AD		 5557 if (IS_P3P_TYPE(ha)) {
5558 if (IS_QLA8044(ha)) {
5559 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5560 &base_vha->dpc_flags)) {
5561 qla8044_idc_lock(ha);
5562 qla8044_wr_direct(base_vha,
5563 QLA8044_CRB_DEV_STATE_INDEX,
5564 QLA8XXX_DEV_FAILED);
5565 qla8044_idc_unlock(ha);
5566 ql_log(ql_log_info, base_vha, 0x4004,
5567 "HW State: FAILED.\n");
5568 qla8044_device_state_handler(base_vha);
5569 continue;
5570 }
5571
5572 } else {
5573 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5574 &base_vha->dpc_flags)) {
5575 qla82xx_idc_lock(ha);
5576 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5577 QLA8XXX_DEV_FAILED);
5578 qla82xx_idc_unlock(ha);
5579 ql_log(ql_log_info, base_vha, 0x0151,
5580 "HW State: FAILED.\n");
5581 qla82xx_device_state_handler(base_vha);
5582 continue;
5583 }
a9083016
GM		 5584 }
5585
5586 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5587 &base_vha->dpc_flags)) {
5588
7c3df132
SK		 5589 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5590 "FCoE context reset scheduled.\n");
a9083016
GM		 5591 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5592 &base_vha->dpc_flags))) {
5593 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5594 /* FCoE-ctx reset failed.
5595 * Escalate to chip-reset
5596 */
5597 set_bit(ISP_ABORT_NEEDED,
5598 &base_vha->dpc_flags);
5599 }
5600 clear_bit(ABORT_ISP_ACTIVE,
5601 &base_vha->dpc_flags);
5602 }
5603
7c3df132
SK		 5604 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5605 "FCoE context reset end.\n");
a9083016 5606 }
8ae6d9c7
GM		 5607 } else if (IS_QLAFX00(ha)) {
5608 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5609 &base_vha->dpc_flags)) {
5610 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5611 "Firmware Reset Recovery\n");
5612 if (qlafx00_reset_initialize(base_vha)) {
5613 /* Failed. Abort isp later. */
5614 if (!test_bit(UNLOADING,
f92f82d6 5615 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5616 set_bit(ISP_UNRECOVERABLE,
5617 &base_vha->dpc_flags);
5618 ql_dbg(ql_dbg_dpc, base_vha,
5619 0x4021,
5620 "Reset Recovery Failed\n");
f92f82d6 5621 }
8ae6d9c7
GM		 5622 }
5623 }
5624
5625 if (test_and_clear_bit(FX00_TARGET_SCAN,
5626 &base_vha->dpc_flags)) {
5627 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5628 "ISPFx00 Target Scan scheduled\n");
5629 if (qlafx00_rescan_isp(base_vha)) {
5630 if (!test_bit(UNLOADING,
5631 &base_vha->dpc_flags))
5632 set_bit(ISP_UNRECOVERABLE,
5633 &base_vha->dpc_flags);
5634 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5635 "ISPFx00 Target Scan Failed\n");
5636 }
5637 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5638 "ISPFx00 Target Scan End\n");
5639 }
e8f5e95d
AB		 5640 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5641 &base_vha->dpc_flags)) {
5642 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5643 "ISPFx00 Host Info resend scheduled\n");
5644 qlafx00_fx_disc(base_vha,
5645 &base_vha->hw->mr.fcport,
5646 FXDISC_REG_HOST_INFO);
5647 }
a9083016
GM		 5648 }
5649
e315cd28
AC		 5650 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5651 &base_vha->dpc_flags)) {
1da177e4 5652
7c3df132
SK		 5653 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5654 "ISP abort scheduled.\n");
1da177e4 5655 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5656 &base_vha->dpc_flags))) {
1da177e4 5657
a9083016 5658 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5659 /* failed. retry later */
5660 set_bit(ISP_ABORT_NEEDED,
e315cd28 5661 &base_vha->dpc_flags);
99363ef8 5662 }
e315cd28
AC		 5663 clear_bit(ABORT_ISP_ACTIVE,
5664 &base_vha->dpc_flags);
99363ef8
SJ		 5665 }
5666
7c3df132
SK		 5667 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5668 "ISP abort end.\n");
1da177e4
LT		 5669 }
5670
a394aac8
DJ		 5671 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5672 &base_vha->dpc_flags)) {
e315cd28 5673 qla2x00_update_fcports(base_vha);
c9c5ced9 5674 }
d97994dc 5675
8ae6d9c7
GM		 5676 if (IS_QLAFX00(ha))
5677 goto loop_resync_check;
5678
579d12b5 5679 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5680 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5681 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5682 if (IS_P3P_TYPE(ha)) {
5683 if (IS_QLA82XX(ha))
5684 qla82xx_device_state_handler(base_vha);
5685 if (IS_QLA8044(ha))
5686 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5687 clear_bit(ISP_QUIESCE_NEEDED,
5688 &base_vha->dpc_flags);
5689 if (!ha->flags.quiesce_owner) {
5690 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5691 if (IS_QLA82XX(ha)) {
5692 qla82xx_idc_lock(ha);
5693 qla82xx_clear_qsnt_ready(
5694 base_vha);
5695 qla82xx_idc_unlock(ha);
5696 } else if (IS_QLA8044(ha)) {
5697 qla8044_idc_lock(ha);
5698 qla8044_clear_qsnt_ready(
5699 base_vha);
5700 qla8044_idc_unlock(ha);
5701 }
8fcd6b8b
CD		 5702 }
5703 } else {
5704 clear_bit(ISP_QUIESCE_NEEDED,
5705 &base_vha->dpc_flags);
5706 qla2x00_quiesce_io(base_vha);
579d12b5 5707 }
7c3df132
SK		 5708 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5709 "Quiescence mode end.\n");
579d12b5
SK		 5710 }
5711
e315cd28 5712 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5713 &base_vha->dpc_flags) &&
e315cd28 5714 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5715
7c3df132
SK		 5716 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5717 "Reset marker scheduled.\n");
e315cd28
AC		 5718 qla2x00_rst_aen(base_vha);
5719 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5720 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5721 "Reset marker end.\n");
1da177e4
LT		 5722 }
5723
5724 /* Retry each device up to login retry count */
e315cd28
AC		 5725 if ((test_and_clear_bit(RELOGIN_NEEDED,
5726 &base_vha->dpc_flags)) &&
5727 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5728 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5729
7c3df132
SK		 5730 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5731 "Relogin scheduled.\n");
e315cd28 5732 qla2x00_relogin(base_vha);
7c3df132
SK		 5733 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5734 "Relogin end.\n");
1da177e4 5735 }
8ae6d9c7 5736loop_resync_check:
e315cd28 5737 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5738 &base_vha->dpc_flags)) {
1da177e4 5739
7c3df132
SK		 5740 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5741 "Loop resync scheduled.\n");
1da177e4
LT		 5742
5743 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5744 &base_vha->dpc_flags))) {
1da177e4 5745
52c82823 5746 qla2x00_loop_resync(base_vha);
1da177e4 5747
e315cd28
AC		 5748 clear_bit(LOOP_RESYNC_ACTIVE,
5749 &base_vha->dpc_flags);
1da177e4
LT		 5750 }
5751
7c3df132
SK		 5752 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5753 "Loop resync end.\n");
1da177e4
LT		 5754 }
5755
8ae6d9c7
GM		 5756 if (IS_QLAFX00(ha))
5757 goto intr_on_check;
5758
e315cd28
AC		 5759 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5760 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5761 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5762 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5763 }
5764
8ae6d9c7 5765intr_on_check:
1da177e4 5766 if (!ha->interrupts_on)
fd34f556 5767 ha->isp_ops->enable_intrs(ha);
1da177e4 5768
e315cd28 5769 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5770 &base_vha->dpc_flags)) {
5771 if (ha->beacon_blink_led == 1)
5772 ha->isp_ops->beacon_blink(base_vha);
5773 }
f6df144c 5774
d7459527
MH		 5775 /* qpair online check */
5776 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5777 &base_vha->dpc_flags)) {
5778 if (ha->flags.eeh_busy ||
5779 ha->flags.pci_channel_io_perm_failure)
5780 online = 0;
5781 else
5782 online = 1;
5783
5784 mutex_lock(&ha->mq_lock);
5785 list_for_each_entry(qpair, &base_vha->qp_list,
5786 qp_list_elem)
5787 qpair->online = online;
5788 mutex_unlock(&ha->mq_lock);
5789 }
5790
8ae6d9c7
GM		 5791 if (!IS_QLAFX00(ha))
5792 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5793
1da177e4 5794 ha->dpc_active = 0;
c142caf0 5795end_loop:
563585ec 5796 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5797 } /* End of while(1) */
563585ec 5798 __set_current_state(TASK_RUNNING);
1da177e4 5799
7c3df132
SK		 5800 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5801 "DPC handler exiting.\n");
1da177e4
LT		 5802
5803 /*
5804 * Make sure that nobody tries to wake us up again.
5805 */
1da177e4
LT		 5806 ha->dpc_active = 0;
5807
ac280b67
AV		 5808 /* Cleanup any residual CTX SRBs. */
5809 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5810
39a11240
CH		 5811 return 0;
5812}
5813
5814void
e315cd28 5815qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5816{
e315cd28 5817 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5818 struct task_struct *t = ha->dpc_thread;
5819
e315cd28 5820 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5821 wake_up_process(t);
1da177e4
LT		 5822}
5823
1da177e4
LT		 5824/*
5825* qla2x00_rst_aen
5826* Processes asynchronous reset.
5827*
5828* Input:
5829* ha = adapter block pointer.
5830*/
5831static void
e315cd28 5832qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5833{
e315cd28
AC		 5834 if (vha->flags.online && !vha->flags.reset_active &&
5835 !atomic_read(&vha->loop_down_timer) &&
5836 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5837 do {
e315cd28 5838 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5839
5840 /*
5841 * Issue marker command only when we are going to start
5842 * the I/O.
5843 */
e315cd28
AC		 5844 vha->marker_needed = 1;
5845 } while (!atomic_read(&vha->loop_down_timer) &&
5846 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5847 }
5848}
5849
1da177e4
LT		 5850/**************************************************************************
5851* qla2x00_timer
5852*
5853* Description:
5854* One second timer
5855*
5856* Context: Interrupt
5857***************************************************************************/
2c3dfe3f 5858void
e315cd28 5859qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5860{
1da177e4 5861 unsigned long cpu_flags = 0;
1da177e4
LT		 5862 int start_dpc = 0;
5863 int index;
5864 srb_t *sp;
85880801 5865 uint16_t w;
e315cd28 5866 struct qla_hw_data *ha = vha->hw;
73208dfd 5867 struct req_que *req;
85880801 5868
a5b36321 5869 if (ha->flags.eeh_busy) {
7c3df132
SK		 5870 ql_dbg(ql_dbg_timer, vha, 0x6000,
5871 "EEH = %d, restarting timer.\n",
5872 ha->flags.eeh_busy);
a5b36321
LC		 5873 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5874 return;
5875 }
5876
f3ddac19
CD		 5877 /*
5878 * Hardware read to raise pending EEH errors during mailbox waits. If
5879 * the read returns -1 then disable the board.
5880 */
5881 if (!pci_channel_offline(ha->pdev)) {
85880801 5882 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5883 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5884 }
1da177e4 5885
cefcaba6 5886 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5887 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5888 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5889 start_dpc++;
7ec0effd
AD		 5890 if (IS_QLA82XX(ha))
5891 qla82xx_watchdog(vha);
5892 else if (IS_QLA8044(ha))
5893 qla8044_watchdog(vha);
579d12b5
SK		 5894 }
5895
8ae6d9c7
GM		 5896 if (!vha->vp_idx && IS_QLAFX00(ha))
5897 qlafx00_timer_routine(vha);
5898
1da177e4 5899 /* Loop down handler. */
e315cd28 5900 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5901 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5902 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5903 && vha->flags.online) {
1da177e4 5904
e315cd28
AC		 5905 if (atomic_read(&vha->loop_down_timer) ==
5906 vha->loop_down_abort_time) {
1da177e4 5907
7c3df132
SK		 5908 ql_log(ql_log_info, vha, 0x6008,
5909 "Loop down - aborting the queues before time expires.\n");
1da177e4 5910
e315cd28
AC		 5911 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5912 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5913
f08b7251
AV		 5914 /*
5915 * Schedule an ISP abort to return any FCP2-device
5916 * commands.
5917 */
2c3dfe3f 5918 /* NPIV - scan physical port only */
e315cd28 5919 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5920 spin_lock_irqsave(&ha->hardware_lock,
5921 cpu_flags);
73208dfd 5922 req = ha->req_q_map[0];
2c3dfe3f 5923 for (index = 1;
8d93f550 5924 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5925 index++) {
5926 fc_port_t *sfcp;
5927
e315cd28 5928 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5929 if (!sp)
5930 continue;
c5419e26
QT		 5931 if (sp->cmd_type != TYPE_SRB)
5932 continue;
9ba56b95 5933 if (sp->type != SRB_SCSI_CMD)
cf53b069 5934 continue;
2c3dfe3f 5935 sfcp = sp->fcport;
f08b7251 5936 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5937 continue;
bdf79621 5938
8f7daead
GM		 5939 if (IS_QLA82XX(ha))
5940 set_bit(FCOE_CTX_RESET_NEEDED,
5941 &vha->dpc_flags);
5942 else
5943 set_bit(ISP_ABORT_NEEDED,
e315cd28 5944 &vha->dpc_flags);
2c3dfe3f
SJ		 5945 break;
5946 }
5947 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5948 cpu_flags);
1da177e4 5949 }
1da177e4
LT		 5950 start_dpc++;
5951 }
5952
5953 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5954 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5955 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5956 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5957 "Loop down - aborting ISP.\n");
5958
8f7daead
GM		 5959 if (IS_QLA82XX(ha))
5960 set_bit(FCOE_CTX_RESET_NEEDED,
5961 &vha->dpc_flags);
5962 else
5963 set_bit(ISP_ABORT_NEEDED,
5964 &vha->dpc_flags);
1da177e4
LT		 5965 }
5966 }
7c3df132
SK		 5967 ql_dbg(ql_dbg_timer, vha, 0x600a,
5968 "Loop down - seconds remaining %d.\n",
5969 atomic_read(&vha->loop_down_timer));
1da177e4 5970 }
cefcaba6
SK		 5971 /* Check if beacon LED needs to be blinked for physical host only */
5972 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5973 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5974 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5975 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5976 start_dpc++;
5977 }
f6df144c
AV		 5978 }
5979
550bf57d 5980 /* Process any deferred work. */
e315cd28 5981 if (!list_empty(&vha->work_list))
550bf57d
AV		 5982 start_dpc++;
5983
1da177e4 5984 /* Schedule the DPC routine if needed */
e315cd28
AC		 5985 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5986 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5987 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5988 start_dpc ||
e315cd28
AC		 5989 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5990 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5991 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5992 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5993 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5994 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5995 ql_dbg(ql_dbg_timer, vha, 0x600b,
5996 "isp_abort_needed=%d loop_resync_needed=%d "
5997 "fcport_update_needed=%d start_dpc=%d "
5998 "reset_marker_needed=%d",
5999 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6000 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6001 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6002 start_dpc,
6003 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6004 ql_dbg(ql_dbg_timer, vha, 0x600c,
6005 "beacon_blink_needed=%d isp_unrecoverable=%d "
6006 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6007 "relogin_needed=%d.\n",
7c3df132
SK		 6008 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6009 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6010 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6011 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6012 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6013 qla2xxx_wake_dpc(vha);
7c3df132 6014 }
1da177e4 6015
e315cd28 6016 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6017}
6018
5433383e
AV		 6019/* Firmware interface routines. */
6020
f73cb695 6021#define FW_BLOBS 11
5433383e
AV		 6022#define FW_ISP21XX 0
6023#define FW_ISP22XX 1
6024#define FW_ISP2300 2
6025#define FW_ISP2322 3
48c02fde 6026#define FW_ISP24XX 4
c3a2f0df 6027#define FW_ISP25XX 5
3a03eb79 6028#define FW_ISP81XX 6
a9083016 6029#define FW_ISP82XX 7
6246b8a1
GM		 6030#define FW_ISP2031 8
6031#define FW_ISP8031 9
2c5bbbb2 6032#define FW_ISP27XX 10
5433383e 6033
bb8ee499
AV		 6034#define FW_FILE_ISP21XX "ql2100_fw.bin"
6035#define FW_FILE_ISP22XX "ql2200_fw.bin"
6036#define FW_FILE_ISP2300 "ql2300_fw.bin"
6037#define FW_FILE_ISP2322 "ql2322_fw.bin"
6038#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6039#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6040#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6041#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6042#define FW_FILE_ISP2031 "ql2600_fw.bin"
6043#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6044#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6045
bb8ee499 6046
e1e82b6f 6047static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6048
6049static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6050 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6051 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6052 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6053 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6054 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6055 { .name = FW_FILE_ISP25XX, },
3a03eb79 6056 { .name = FW_FILE_ISP81XX, },
a9083016 6057 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6058 { .name = FW_FILE_ISP2031, },
6059 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6060 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6061};
6062
6063struct fw_blob *
e315cd28 6064qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6065{
e315cd28 6066 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6067 struct fw_blob *blob;
6068
5433383e
AV		 6069 if (IS_QLA2100(ha)) {
6070 blob = &qla_fw_blobs[FW_ISP21XX];
6071 } else if (IS_QLA2200(ha)) {
6072 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6073 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6074 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6075 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6076 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6077 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6078 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6079 } else if (IS_QLA25XX(ha)) {
6080 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6081 } else if (IS_QLA81XX(ha)) {
6082 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6083 } else if (IS_QLA82XX(ha)) {
6084 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6085 } else if (IS_QLA2031(ha)) {
6086 blob = &qla_fw_blobs[FW_ISP2031];
6087 } else if (IS_QLA8031(ha)) {
6088 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6089 } else if (IS_QLA27XX(ha)) {
6090 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6091 } else {
6092 return NULL;
5433383e
AV		 6093 }
6094
e1e82b6f 6095 mutex_lock(&qla_fw_lock);
5433383e
AV		 6096 if (blob->fw)
6097 goto out;
6098
6099 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6100 ql_log(ql_log_warn, vha, 0x0063,
6101 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6102 blob->fw = NULL;
6103 blob = NULL;
6104 goto out;
6105 }
6106
6107out:
e1e82b6f 6108 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6109 return blob;
6110}
6111
6112static void
6113qla2x00_release_firmware(void)
6114{
6115 int idx;
6116
e1e82b6f 6117 mutex_lock(&qla_fw_lock);
5433383e 6118 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6119 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6120 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6121}
6122
14e660e6
SJ		 6123static pci_ers_result_t
6124qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6125{
85880801
AV		 6126 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6127 struct qla_hw_data *ha = vha->hw;
6128
7c3df132
SK		 6129 ql_dbg(ql_dbg_aer, vha, 0x9000,
6130 "PCI error detected, state %x.\n", state);
b9b12f73 6131
14e660e6
SJ		 6132 switch (state) {
6133 case pci_channel_io_normal:
85880801 6134 ha->flags.eeh_busy = 0;
d7459527
MH		 6135 if (ql2xmqsupport) {
6136 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6137 qla2xxx_wake_dpc(vha);
6138 }
14e660e6
SJ		 6139 return PCI_ERS_RESULT_CAN_RECOVER;
6140 case pci_channel_io_frozen:
85880801 6141 ha->flags.eeh_busy = 1;
a5b36321
LC		 6142 /* For ISP82XX complete any pending mailbox cmd */
6143 if (IS_QLA82XX(ha)) {
7190575f 6144 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6145 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6146 qla82xx_clear_pending_mbx(vha);
a5b36321 6147 }
90a86fc0 6148 qla2x00_free_irqs(vha);
14e660e6 6149 pci_disable_device(pdev);
bddd2d65
LC		 6150 /* Return back all IOs */
6151 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6152 if (ql2xmqsupport) {
6153 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6154 qla2xxx_wake_dpc(vha);
6155 }
14e660e6
SJ		 6156 return PCI_ERS_RESULT_NEED_RESET;
6157 case pci_channel_io_perm_failure:
85880801
AV		 6158 ha->flags.pci_channel_io_perm_failure = 1;
6159 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6160 if (ql2xmqsupport) {
6161 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6162 qla2xxx_wake_dpc(vha);
6163 }
14e660e6
SJ		 6164 return PCI_ERS_RESULT_DISCONNECT;
6165 }
6166 return PCI_ERS_RESULT_NEED_RESET;
6167}
6168
6169static pci_ers_result_t
6170qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6171{
6172 int risc_paused = 0;
6173 uint32_t stat;
6174 unsigned long flags;
e315cd28
AC		 6175 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6176 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6177 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6178 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6179
bcc5b6d3
SK		 6180 if (IS_QLA82XX(ha))
6181 return PCI_ERS_RESULT_RECOVERED;
6182
14e660e6
SJ		 6183 spin_lock_irqsave(&ha->hardware_lock, flags);
6184 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6185 stat = RD_REG_DWORD(&reg->hccr);
6186 if (stat & HCCR_RISC_PAUSE)
6187 risc_paused = 1;
6188 } else if (IS_QLA23XX(ha)) {
6189 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6190 if (stat & HSR_RISC_PAUSED)
6191 risc_paused = 1;
6192 } else if (IS_FWI2_CAPABLE(ha)) {
6193 stat = RD_REG_DWORD(&reg24->host_status);
6194 if (stat & HSRX_RISC_PAUSED)
6195 risc_paused = 1;
6196 }
6197 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6198
6199 if (risc_paused) {
7c3df132
SK		 6200 ql_log(ql_log_info, base_vha, 0x9003,
6201 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6202 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6203
6204 return PCI_ERS_RESULT_NEED_RESET;
6205 } else
6206 return PCI_ERS_RESULT_RECOVERED;
6207}
6208
fa492630
SK		 6209static uint32_t
6210qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6211{
6212 uint32_t rval = QLA_FUNCTION_FAILED;
6213 uint32_t drv_active = 0;
6214 struct qla_hw_data *ha = base_vha->hw;
6215 int fn;
6216 struct pci_dev *other_pdev = NULL;
6217
7c3df132
SK		 6218 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6219 "Entered %s.\n", __func__);
a5b36321
LC		 6220
6221 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6222
6223 if (base_vha->flags.online) {
6224 /* Abort all outstanding commands,
6225 * so as to be requeued later */
6226 qla2x00_abort_isp_cleanup(base_vha);
6227 }
6228
6229
6230 fn = PCI_FUNC(ha->pdev->devfn);
6231 while (fn > 0) {
6232 fn--;
7c3df132
SK		 6233 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6234 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6235 other_pdev =
6236 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6237 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6238 fn));
6239
6240 if (!other_pdev)
6241 continue;
6242 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6243 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6244 "Found PCI func available and enable at 0x%x.\n",
6245 fn);
a5b36321
LC		 6246 pci_dev_put(other_pdev);
6247 break;
6248 }
6249 pci_dev_put(other_pdev);
6250 }
6251
6252 if (!fn) {
6253 /* Reset owner */
7c3df132
SK		 6254 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6255 "This devfn is reset owner = 0x%x.\n",
6256 ha->pdev->devfn);
a5b36321
LC		 6257 qla82xx_idc_lock(ha);
6258
6259 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6260 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6261
6262 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6263 QLA82XX_IDC_VERSION);
6264
6265 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6266 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6267 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6268
6269 qla82xx_idc_unlock(ha);
6270 /* Reset if device is not already reset
6271 * drv_active would be 0 if a reset has already been done
6272 */
6273 if (drv_active)
6274 rval = qla82xx_start_firmware(base_vha);
6275 else
6276 rval = QLA_SUCCESS;
6277 qla82xx_idc_lock(ha);
6278
6279 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6280 ql_log(ql_log_info, base_vha, 0x900b,
6281 "HW State: FAILED.\n");
a5b36321
LC		 6282 qla82xx_clear_drv_active(ha);
6283 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6284 QLA8XXX_DEV_FAILED);
a5b36321 6285 } else {
7c3df132
SK		 6286 ql_log(ql_log_info, base_vha, 0x900c,
6287 "HW State: READY.\n");
a5b36321 6288 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6289 QLA8XXX_DEV_READY);
a5b36321 6290 qla82xx_idc_unlock(ha);
7190575f 6291 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6292 rval = qla82xx_restart_isp(base_vha);
6293 qla82xx_idc_lock(ha);
6294 /* Clear driver state register */
6295 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6296 qla82xx_set_drv_active(base_vha);
6297 }
6298 qla82xx_idc_unlock(ha);
6299 } else {
7c3df132
SK		 6300 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6301 "This devfn is not reset owner = 0x%x.\n",
6302 ha->pdev->devfn);
a5b36321 6303 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6304 QLA8XXX_DEV_READY)) {
7190575f 6305 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6306 rval = qla82xx_restart_isp(base_vha);
6307 qla82xx_idc_lock(ha);
6308 qla82xx_set_drv_active(base_vha);
6309 qla82xx_idc_unlock(ha);
6310 }
6311 }
6312 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6313
6314 return rval;
6315}
6316
14e660e6
SJ		 6317static pci_ers_result_t
6318qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6319{
6320 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6321 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6322 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6323 struct rsp_que *rsp;
6324 int rc, retries = 10;
09483916 6325
7c3df132
SK		 6326 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6327 "Slot Reset.\n");
85880801 6328
90a86fc0
JC		 6329 /* Workaround: qla2xxx driver which access hardware earlier
6330 * needs error state to be pci_channel_io_online.
6331 * Otherwise mailbox command timesout.
6332 */
6333 pdev->error_state = pci_channel_io_normal;
6334
6335 pci_restore_state(pdev);
6336
8c1496bd
RL		 6337 /* pci_restore_state() clears the saved_state flag of the device
6338 * save restored state which resets saved_state flag
6339 */
6340 pci_save_state(pdev);
6341
09483916
BH		 6342 if (ha->mem_only)
6343 rc = pci_enable_device_mem(pdev);
6344 else
6345 rc = pci_enable_device(pdev);
14e660e6 6346
09483916 6347 if (rc) {
7c3df132 6348 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6349 "Can't re-enable PCI device after reset.\n");
a5b36321 6350 goto exit_slot_reset;
14e660e6 6351 }
14e660e6 6352
90a86fc0
JC		 6353 rsp = ha->rsp_q_map[0];
6354 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6355 goto exit_slot_reset;
90a86fc0 6356
e315cd28 6357 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6358 goto exit_slot_reset;
6359
6360 if (IS_QLA82XX(ha)) {
6361 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6362 ret = PCI_ERS_RESULT_RECOVERED;
6363 goto exit_slot_reset;
6364 } else
6365 goto exit_slot_reset;
6366 }
14e660e6 6367
90a86fc0
JC		 6368 while (ha->flags.mbox_busy && retries--)
6369 msleep(1000);
85880801 6370
e315cd28 6371 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6372 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6373 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6374 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6375
90a86fc0 6376
a5b36321 6377exit_slot_reset:
7c3df132
SK		 6378 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6379 "slot_reset return %x.\n", ret);
85880801 6380
14e660e6
SJ		 6381 return ret;
6382}
6383
6384static void
6385qla2xxx_pci_resume(struct pci_dev *pdev)
6386{
e315cd28
AC		 6387 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6388 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6389 int ret;
6390
7c3df132
SK		 6391 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6392 "pci_resume.\n");
85880801 6393
e315cd28 6394 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6395 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6396 ql_log(ql_log_fatal, base_vha, 0x9002,
6397 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6398 }
85880801 6399
3e46f031
LC		 6400 pci_cleanup_aer_uncorrect_error_status(pdev);
6401
85880801 6402 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6403}
6404
2d5a4c34
HM		 6405static void
6406qla83xx_disable_laser(scsi_qla_host_t *vha)
6407{
6408 uint32_t reg, data, fn;
6409 struct qla_hw_data *ha = vha->hw;
6410 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6411
6412 /* pci func #/port # */
6413 ql_dbg(ql_dbg_init, vha, 0x004b,
6414 "Disabling Laser for hba: %p\n", vha);
6415
6416 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6417 (BIT_15|BIT_14|BIT_13|BIT_12));
6418
6419 fn = (fn >> 12);
6420
6421 if (fn & 1)
6422 reg = PORT_1_2031;
6423 else
6424 reg = PORT_0_2031;
6425
6426 data = LASER_OFF_2031;
6427
6428 qla83xx_wr_reg(vha, reg, data);
6429}
6430
5601236b
MH		 6431static int qla2xxx_map_queues(struct Scsi_Host *shost)
6432{
6433 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6434
6435 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6436}
6437
a55b2d21 6438static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6439 .error_detected = qla2xxx_pci_error_detected,
6440 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6441 .slot_reset = qla2xxx_pci_slot_reset,
6442 .resume = qla2xxx_pci_resume,
6443};
6444
5433383e 6445static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6446 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6447 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6448 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6449 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6450 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6451 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6452 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6453 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6454 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6455 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6456 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6457 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6458 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6459 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6460 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6461 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6462 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6463 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6464 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6465 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6466 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6467 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6468 { 0 },
6469};
6470MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6471
fca29703 6472static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6473 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6474 .driver = {
6475 .owner = THIS_MODULE,
6476 },
fca29703 6477 .id_table = qla2xxx_pci_tbl,
7ee61397 6478 .probe = qla2x00_probe_one,
4c993f76 6479 .remove = qla2x00_remove_one,
e30d1756 6480 .shutdown = qla2x00_shutdown,
14e660e6 6481 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6482};
6483
75ef9de1 6484static const struct file_operations apidev_fops = {
6a03b4cd 6485 .owner = THIS_MODULE,
6038f373 6486 .llseek = noop_llseek,
6a03b4cd
HZ		 6487};
6488
1da177e4
LT		 6489/**
6490 * qla2x00_module_init - Module initialization.
6491 **/
6492static int __init
6493qla2x00_module_init(void)
6494{
fca29703
AV		 6495 int ret = 0;
6496
1da177e4 6497 /* Allocate cache for SRBs. */
354d6b21 6498 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6499 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6500 if (srb_cachep == NULL) {
7c3df132
SK		 6501 ql_log(ql_log_fatal, NULL, 0x0001,
6502 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6503 return -ENOMEM;
6504 }
6505
2d70c103
NB		 6506 /* Initialize target kmem_cache and mem_pools */
6507 ret = qlt_init();
6508 if (ret < 0) {
6509 kmem_cache_destroy(srb_cachep);
6510 return ret;
6511 } else if (ret > 0) {
6512 /*
6513 * If initiator mode is explictly disabled by qlt_init(),
6514 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6515 * performing scsi_scan_target() during LOOP UP event.
6516 */
6517 qla2xxx_transport_functions.disable_target_scan = 1;
6518 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6519 }
6520
1da177e4
LT		 6521 /* Derive version string. */
6522 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6523 if (ql2xextended_error_logging)
0181944f
AV		 6524 strcat(qla2x00_version_str, "-debug");
6525
1c97a12a
AV		 6526 qla2xxx_transport_template =
6527 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6528 if (!qla2xxx_transport_template) {
6529 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6530 ql_log(ql_log_fatal, NULL, 0x0002,
6531 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6532 qlt_exit();
1da177e4 6533 return -ENODEV;
2c3dfe3f 6534 }
6a03b4cd
HZ		 6535
6536 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6537 if (apidev_major < 0) {
7c3df132
SK		 6538 ql_log(ql_log_fatal, NULL, 0x0003,
6539 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6540 }
6541
2c3dfe3f
SJ		 6542 qla2xxx_transport_vport_template =
6543 fc_attach_transport(&qla2xxx_transport_vport_functions);
6544 if (!qla2xxx_transport_vport_template) {
6545 kmem_cache_destroy(srb_cachep);
2d70c103 6546 qlt_exit();
2c3dfe3f 6547 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6548 ql_log(ql_log_fatal, NULL, 0x0004,
6549 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6550 return -ENODEV;
2c3dfe3f 6551 }
7c3df132
SK		 6552 ql_log(ql_log_info, NULL, 0x0005,
6553 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6554 qla2x00_version_str);
7ee61397 6555 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6556 if (ret) {
6557 kmem_cache_destroy(srb_cachep);
2d70c103 6558 qlt_exit();
fca29703 6559 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6560 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6561 ql_log(ql_log_fatal, NULL, 0x0006,
6562 "pci_register_driver failed...ret=%d Failing load!.\n",
6563 ret);
fca29703
AV		 6564 }
6565 return ret;
1da177e4
LT		 6566}
6567
6568/**
6569 * qla2x00_module_exit - Module cleanup.
6570 **/
6571static void __exit
6572qla2x00_module_exit(void)
6573{
6a03b4cd 6574 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6575 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6576 qla2x00_release_firmware();
354d6b21 6577 kmem_cache_destroy(srb_cachep);
2d70c103 6578 qlt_exit();
a9083016
GM		 6579 if (ctx_cachep)
6580 kmem_cache_destroy(ctx_cachep);
1da177e4 6581 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6582 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6583}
6584
6585module_init(qla2x00_module_init);
6586module_exit(qla2x00_module_exit);
6587
6588MODULE_AUTHOR("QLogic Corporation");
6589MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6590MODULE_LICENSE("GPL");
6591MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6592MODULE_FIRMWARE(FW_FILE_ISP21XX);
6593MODULE_FIRMWARE(FW_FILE_ISP22XX);
6594MODULE_FIRMWARE(FW_FILE_ISP2300);
6595MODULE_FIRMWARE(FW_FILE_ISP2322);
6596MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6597MODULE_FIRMWARE(FW_FILE_ISP25XX);
Ubuntu Jammy Linux kernel mirror