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[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
1da177e4 50int ql2xlogintimeout = 20;
f2019cb1 51module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 52MODULE_PARM_DESC(ql2xlogintimeout,
53 "Login timeout value in seconds.");
54
a7b61842 55int qlport_down_retry;
f2019cb1 56module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 57MODULE_PARM_DESC(qlport_down_retry,
900d9f98 58 "Maximum number of command retries to a port that returns "
1da177e4
LT		 59 "a PORT-DOWN status.");
60
1da177e4
LT		 61int ql2xplogiabsentdevice;
62module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
63MODULE_PARM_DESC(ql2xplogiabsentdevice,
64 "Option to enable PLOGI to devices that are not present after "
900d9f98 65 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 66 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
67
1da177e4 68int ql2xloginretrycount = 0;
f2019cb1 69module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 70MODULE_PARM_DESC(ql2xloginretrycount,
71 "Specify an alternate value for the NVRAM login retry count.");
72
a7a167bf 73int ql2xallocfwdump = 1;
f2019cb1 74module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 75MODULE_PARM_DESC(ql2xallocfwdump,
76 "Option to enable allocation of memory for a firmware dump "
77 "during HBA initialization. Memory allocation requirements "
78 "vary by ISP type. Default is 1 - allocate memory.");
79
11010fec 80int ql2xextended_error_logging;
27d94035 81module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 82MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 83 "Option to enable extended error logging,\n"
84 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
85 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
86 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
87 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
88 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
89 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
90 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
91 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 92 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
93 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 94 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 95 "\t\t0x1e400000 - Preferred value for capturing essential "
96 "debug information (equivalent to old "
97 "ql2xextended_error_logging=1).\n"
3ce8866c 98 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 99
a9083016 100int ql2xshiftctondsd = 6;
f2019cb1 101module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 102MODULE_PARM_DESC(ql2xshiftctondsd,
103 "Set to control shifting of command type processing "
104 "based on total number of SG elements.");
105
1da177e4
LT		 106static void qla2x00_free_device(scsi_qla_host_t *);
107
7e47e5ca 108int ql2xfdmienable=1;
f2019cb1 109module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 110MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 111 "Enables FDMI registrations. "
112 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 113
3c290d0b 114int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 115module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
116MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 117 "Maximum queue depth to set for each LUN. "
118 "Default is 32.");
df7baa50 119
9e522cd8
AE		 120int ql2xenabledif = 2;
121module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 122MODULE_PARM_DESC(ql2xenabledif,
123 " Enable T10-CRC-DIF "
8cb2049c
AE		 124 " Default is 0 - No DIF Support. 1 - Enable it"
125 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 126
8cb2049c 127int ql2xenablehba_err_chk = 2;
bad75002
AE		 128module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
129MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 130 " Enable T10-CRC-DIF Error isolation by HBA:\n"
131 " Default is 1.\n"
132 " 0 -- Error isolation disabled\n"
133 " 1 -- Error isolation enabled only for DIX Type 0\n"
134 " 2 -- Error isolation enabled for all Types\n");
bad75002 135
e5896bd5 136int ql2xiidmaenable=1;
f2019cb1 137module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 138MODULE_PARM_DESC(ql2xiidmaenable,
139 "Enables iIDMA settings "
140 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
141
73208dfd 142int ql2xmaxqueues = 1;
f2019cb1 143module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 144MODULE_PARM_DESC(ql2xmaxqueues,
145 "Enables MQ settings "
ae68230c
JP		 146 "Default is 1 for single queue. Set it to number "
147 "of queues in MQ mode.");
68ca949c
AC		 148
149int ql2xmultique_tag;
f2019cb1 150module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 151MODULE_PARM_DESC(ql2xmultique_tag,
152 "Enables CPU affinity settings for the driver "
153 "Default is 0 for no affinity of request and response IO. "
154 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 155
156int ql2xfwloadbin;
86e45bf6 157module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 158MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 159 "Option to specify location from which to load ISP firmware:.\n"
160 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 161 " interface.\n"
162 " 1 -- load firmware from flash.\n"
163 " 0 -- use default semantics.\n");
164
ae97c91e 165int ql2xetsenable;
f2019cb1 166module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 167MODULE_PARM_DESC(ql2xetsenable,
168 "Enables firmware ETS burst."
169 "Default is 0 - skip ETS enablement.");
170
6907869d 171int ql2xdbwr = 1;
86e45bf6 172module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 173MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 174 "Option to specify scheme for request queue posting.\n"
175 " 0 -- Regular doorbell.\n"
176 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 177
f4c496c1 178int ql2xtargetreset = 1;
f2019cb1 179module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 180MODULE_PARM_DESC(ql2xtargetreset,
181 "Enable target reset."
182 "Default is 1 - use hw defaults.");
183
4da26e16 184int ql2xgffidenable;
f2019cb1 185module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 186MODULE_PARM_DESC(ql2xgffidenable,
187 "Enables GFF_ID checks of port type. "
188 "Default is 0 - Do not use GFF_ID information.");
a9083016 189
3822263e 190int ql2xasynctmfenable;
f2019cb1 191module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 192MODULE_PARM_DESC(ql2xasynctmfenable,
193 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
194 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 195
196int ql2xdontresethba;
86e45bf6 197module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 198MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 199 "Option to specify reset behaviour.\n"
200 " 0 (Default) -- Reset on failure.\n"
201 " 1 -- Do not reset on failure.\n");
ed0de87c 202
82515920
AV		 203uint ql2xmaxlun = MAX_LUNS;
204module_param(ql2xmaxlun, uint, S_IRUGO);
205MODULE_PARM_DESC(ql2xmaxlun,
206 "Defines the maximum LU number to register with the SCSI "
207 "midlayer. Default is 65535.");
208
08de2844
GM		 209int ql2xmdcapmask = 0x1F;
210module_param(ql2xmdcapmask, int, S_IRUGO);
211MODULE_PARM_DESC(ql2xmdcapmask,
212 "Set the Minidump driver capture mask level. "
6e96fa7b 213 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 214
3aadff35 215int ql2xmdenable = 1;
08de2844
GM		 216module_param(ql2xmdenable, int, S_IRUGO);
217MODULE_PARM_DESC(ql2xmdenable,
218 "Enable/disable MiniDump. "
3aadff35
GM		 219 "0 - MiniDump disabled. "
220 "1 (Default) - MiniDump enabled.");
08de2844 221
1da177e4 222/*
fa2a1ce5 223 * SCSI host template entry points
1da177e4
LT		 224 */
225static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 226static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 227static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
228static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 229static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 230static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 231static int qla2xxx_eh_abort(struct scsi_cmnd *);
232static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 233static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 234static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
235static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 236
e881a172 237static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 238static int qla2x00_change_queue_type(struct scsi_device *, int);
239
a5326f86 240struct scsi_host_template qla2xxx_driver_template = {
1da177e4 241 .module = THIS_MODULE,
cb63067a 242 .name = QLA2XXX_DRIVER_NAME,
a5326f86 243 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 244
245 .eh_abort_handler = qla2xxx_eh_abort,
246 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 247 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 248 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
249 .eh_host_reset_handler = qla2xxx_eh_host_reset,
250
251 .slave_configure = qla2xxx_slave_configure,
252
253 .slave_alloc = qla2xxx_slave_alloc,
254 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 255 .scan_finished = qla2xxx_scan_finished,
256 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 257 .change_queue_depth = qla2x00_change_queue_depth,
258 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 259 .this_id = -1,
260 .cmd_per_lun = 3,
261 .use_clustering = ENABLE_CLUSTERING,
262 .sg_tablesize = SG_ALL,
263
264 .max_sectors = 0xFFFF,
afb046e2 265 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 266
267 .supported_mode = MODE_INITIATOR,
fca29703
AV		 268};
269
1da177e4 270static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 271struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 272
1da177e4
LT		 273/* TODO Convert to inlines
274 *
275 * Timer routines
276 */
1da177e4 277
2c3dfe3f 278__inline__ void
e315cd28 279qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 280{
e315cd28
AC		 281 init_timer(&vha->timer);
282 vha->timer.expires = jiffies + interval * HZ;
283 vha->timer.data = (unsigned long)vha;
284 vha->timer.function = (void (*)(unsigned long))func;
285 add_timer(&vha->timer);
286 vha->timer_active = 1;
1da177e4
LT		 287}
288
289static inline void
e315cd28 290qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 291{
a9083016 292 /* Currently used for 82XX only. */
7c3df132
SK		 293 if (vha->device_flags & DFLG_DEV_FAILED) {
294 ql_dbg(ql_dbg_timer, vha, 0x600d,
295 "Device in a failed state, returning.\n");
a9083016 296 return;
7c3df132 297 }
a9083016 298
e315cd28 299 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 300}
301
a824ebb3 302static __inline__ void
e315cd28 303qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 304{
e315cd28
AC		 305 del_timer_sync(&vha->timer);
306 vha->timer_active = 0;
1da177e4
LT		 307}
308
1da177e4
LT		 309static int qla2x00_do_dpc(void *data);
310
311static void qla2x00_rst_aen(scsi_qla_host_t *);
312
73208dfd
AC		 313static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
314 struct req_que **, struct rsp_que **);
e30d1756 315static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 316static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 317
1da177e4 318/* -------------------------------------------------------------------------- */
9a347ff4
CD		 319static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
320 struct rsp_que *rsp)
73208dfd 321{
7c3df132 322 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 323 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 324 GFP_KERNEL);
325 if (!ha->req_q_map) {
7c3df132
SK		 326 ql_log(ql_log_fatal, vha, 0x003b,
327 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 328 goto fail_req_map;
329 }
330
2afa19a9 331 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 332 GFP_KERNEL);
333 if (!ha->rsp_q_map) {
7c3df132
SK		 334 ql_log(ql_log_fatal, vha, 0x003c,
335 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 336 goto fail_rsp_map;
337 }
9a347ff4
CD		 338 /*
339 * Make sure we record at least the request and response queue zero in
340 * case we need to free them if part of the probe fails.
341 */
342 ha->rsp_q_map[0] = rsp;
343 ha->req_q_map[0] = req;
73208dfd
AC		 344 set_bit(0, ha->rsp_qid_map);
345 set_bit(0, ha->req_qid_map);
346 return 1;
347
348fail_rsp_map:
349 kfree(ha->req_q_map);
350 ha->req_q_map = NULL;
351fail_req_map:
352 return -ENOMEM;
353}
354
2afa19a9 355static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 356{
73208dfd
AC		 357 if (req && req->ring)
358 dma_free_coherent(&ha->pdev->dev,
359 (req->length + 1) * sizeof(request_t),
360 req->ring, req->dma);
361
8d93f550
CD		 362 if (req)
363 kfree(req->outstanding_cmds);
364
73208dfd
AC		 365 kfree(req);
366 req = NULL;
367}
368
2afa19a9
AC		 369static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
370{
371 if (rsp && rsp->ring)
372 dma_free_coherent(&ha->pdev->dev,
373 (rsp->length + 1) * sizeof(response_t),
374 rsp->ring, rsp->dma);
375
376 kfree(rsp);
377 rsp = NULL;
378}
379
73208dfd
AC		 380static void qla2x00_free_queues(struct qla_hw_data *ha)
381{
382 struct req_que *req;
383 struct rsp_que *rsp;
384 int cnt;
385
2afa19a9 386 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 387 req = ha->req_q_map[cnt];
2afa19a9 388 qla2x00_free_req_que(ha, req);
73208dfd 389 }
73208dfd
AC		 390 kfree(ha->req_q_map);
391 ha->req_q_map = NULL;
2afa19a9
AC		 392
393 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
394 rsp = ha->rsp_q_map[cnt];
395 qla2x00_free_rsp_que(ha, rsp);
396 }
397 kfree(ha->rsp_q_map);
398 ha->rsp_q_map = NULL;
73208dfd
AC		 399}
400
68ca949c
AC		 401static int qla25xx_setup_mode(struct scsi_qla_host *vha)
402{
403 uint16_t options = 0;
404 int ques, req, ret;
405 struct qla_hw_data *ha = vha->hw;
406
7163ea81 407 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 408 ql_log(ql_log_warn, vha, 0x00d8,
409 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 410 goto fail;
411 }
68ca949c 412 if (ql2xmultique_tag) {
68ca949c
AC		 413 /* create a request queue for IO */
414 options |= BIT_7;
415 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
416 QLA_DEFAULT_QUE_QOS);
417 if (!req) {
7c3df132
SK		 418 ql_log(ql_log_warn, vha, 0x00e0,
419 "Failed to create request queue.\n");
68ca949c
AC		 420 goto fail;
421 }
278274d5 422 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 423 vha->req = ha->req_q_map[req];
424 options |= BIT_1;
425 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
426 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
427 if (!ret) {
7c3df132
SK		 428 ql_log(ql_log_warn, vha, 0x00e8,
429 "Failed to create response queue.\n");
68ca949c
AC		 430 goto fail2;
431 }
432 }
7163ea81 433 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 434 ql_dbg(ql_dbg_multiq, vha, 0xc007,
435 "CPU affinity mode enalbed, "
436 "no. of response queues:%d no. of request queues:%d.\n",
437 ha->max_rsp_queues, ha->max_req_queues);
438 ql_dbg(ql_dbg_init, vha, 0x00e9,
439 "CPU affinity mode enalbed, "
440 "no. of response queues:%d no. of request queues:%d.\n",
441 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 442 }
443 return 0;
444fail2:
445 qla25xx_delete_queues(vha);
7163ea81
AC		 446 destroy_workqueue(ha->wq);
447 ha->wq = NULL;
0cd33fcf 448 vha->req = ha->req_q_map[0];
68ca949c
AC		 449fail:
450 ha->mqenable = 0;
7163ea81
AC		 451 kfree(ha->req_q_map);
452 kfree(ha->rsp_q_map);
453 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 454 return 1;
455}
456
1da177e4 457static char *
e315cd28 458qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 459{
e315cd28 460 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 461 static char *pci_bus_modes[] = {
462 "33", "66", "100", "133",
463 };
464 uint16_t pci_bus;
465
466 strcpy(str, "PCI");
467 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
468 if (pci_bus) {
469 strcat(str, "-X (");
470 strcat(str, pci_bus_modes[pci_bus]);
471 } else {
472 pci_bus = (ha->pci_attr & BIT_8) >> 8;
473 strcat(str, " (");
474 strcat(str, pci_bus_modes[pci_bus]);
475 }
476 strcat(str, " MHz)");
477
478 return (str);
479}
480
fca29703 481static char *
e315cd28 482qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 483{
484 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 485 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 486 uint32_t pci_bus;
487 int pcie_reg;
488
e67f1321 489 pcie_reg = pci_pcie_cap(ha->pdev);
fca29703
AV		 490 if (pcie_reg) {
491 char lwstr[6];
492 uint16_t pcie_lstat, lspeed, lwidth;
493
e67f1321 494 pcie_reg += PCI_EXP_LNKCAP;
fca29703
AV		 495 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
496 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
497 lwidth = (pcie_lstat &
498 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
499
500 strcpy(str, "PCIe (");
49300af7
SK		 501 switch (lspeed) {
502 case 1:
c87a0d8c 503 strcat(str, "2.5GT/s ");
49300af7
SK		 504 break;
505 case 2:
c87a0d8c 506 strcat(str, "5.0GT/s ");
49300af7
SK		 507 break;
508 case 3:
509 strcat(str, "8.0GT/s ");
510 break;
511 default:
fca29703 512 strcat(str, "<unknown> ");
49300af7
SK		 513 break;
514 }
fca29703
AV		 515 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
516 strcat(str, lwstr);
517
518 return str;
519 }
520
521 strcpy(str, "PCI");
522 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
523 if (pci_bus == 0 || pci_bus == 8) {
524 strcat(str, " (");
525 strcat(str, pci_bus_modes[pci_bus >> 3]);
526 } else {
527 strcat(str, "-X ");
528 if (pci_bus & BIT_2)
529 strcat(str, "Mode 2");
530 else
531 strcat(str, "Mode 1");
532 strcat(str, " (");
533 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
534 }
535 strcat(str, " MHz)");
536
537 return str;
538}
539
e5f82ab8 540static char *
e315cd28 541qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 542{
543 char un_str[10];
e315cd28 544 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 545
1da177e4
LT		 546 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
547 ha->fw_minor_version,
548 ha->fw_subminor_version);
549
550 if (ha->fw_attributes & BIT_9) {
551 strcat(str, "FLX");
552 return (str);
553 }
554
555 switch (ha->fw_attributes & 0xFF) {
556 case 0x7:
557 strcat(str, "EF");
558 break;
559 case 0x17:
560 strcat(str, "TP");
561 break;
562 case 0x37:
563 strcat(str, "IP");
564 break;
565 case 0x77:
566 strcat(str, "VI");
567 break;
568 default:
569 sprintf(un_str, "(%x)", ha->fw_attributes);
570 strcat(str, un_str);
571 break;
572 }
573 if (ha->fw_attributes & 0x100)
574 strcat(str, "X");
575
576 return (str);
577}
578
e5f82ab8 579static char *
e315cd28 580qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 581{
e315cd28 582 struct qla_hw_data *ha = vha->hw;
f0883ac6 583
3a03eb79
AV		 584 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
585 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 586 return str;
fca29703
AV		 587}
588
9ba56b95
GM		 589void
590qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 591{
9ba56b95
GM		 592 srb_t *sp = (srb_t *)ptr;
593 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
594 struct qla_hw_data *ha = sp->fcport->vha->hw;
595 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 596
9ba56b95
GM		 597 if (sp->flags & SRB_DMA_VALID) {
598 scsi_dma_unmap(cmd);
599 sp->flags &= ~SRB_DMA_VALID;
7c3df132 600 }
fca29703 601
9ba56b95
GM		 602 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
603 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
604 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
605 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
606 }
607
608 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
609 /* List assured to be having elements */
610 qla2x00_clean_dsd_pool(ha, sp);
611 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
612 }
613
614 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
615 dma_pool_free(ha->dl_dma_pool, ctx,
616 ((struct crc_context *)ctx)->crc_ctx_dma);
617 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
618 }
619
620 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
621 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 622
9ba56b95
GM		 623 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
624 ctx1->fcp_cmnd_dma);
625 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
626 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
627 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
628 mempool_free(ctx1, ha->ctx_mempool);
629 ctx1 = NULL;
630 }
631
632 CMD_SP(cmd) = NULL;
b00ee7d7 633 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 634}
635
636static void
637qla2x00_sp_compl(void *data, void *ptr, int res)
638{
639 struct qla_hw_data *ha = (struct qla_hw_data *)data;
640 srb_t *sp = (srb_t *)ptr;
641 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
642
643 cmd->result = res;
644
645 if (atomic_read(&sp->ref_count) == 0) {
646 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
647 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
648 sp, GET_CMD_SP(sp));
649 if (ql2xextended_error_logging & ql_dbg_io)
650 BUG();
651 return;
652 }
653 if (!atomic_dec_and_test(&sp->ref_count))
654 return;
655
656 qla2x00_sp_free_dma(ha, sp);
657 cmd->scsi_done(cmd);
fca29703
AV		 658}
659
1da177e4 660static int
f5e3e40b 661qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 662{
134ae078 663 scsi_qla_host_t *vha = shost_priv(host);
fca29703 664 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 665 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 666 struct qla_hw_data *ha = vha->hw;
667 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 668 srb_t *sp;
669 int rval;
670
85880801 671 if (ha->flags.eeh_busy) {
7c3df132 672 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 673 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 674 "PCI Channel IO permanent failure, exiting "
675 "cmd=%p.\n", cmd);
b9b12f73 676 cmd->result = DID_NO_CONNECT << 16;
7c3df132 677 } else {
5f28d2d7 678 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 679 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 680 cmd->result = DID_REQUEUE << 16;
7c3df132 681 }
14e660e6
SJ		 682 goto qc24_fail_command;
683 }
684
19a7b4ae
JSEC		 685 rval = fc_remote_port_chkready(rport);
686 if (rval) {
687 cmd->result = rval;
5f28d2d7 688 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 689 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
690 cmd, rval);
fca29703
AV		 691 goto qc24_fail_command;
692 }
693
bad75002
AE		 694 if (!vha->flags.difdix_supported &&
695 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 696 ql_dbg(ql_dbg_io, vha, 0x3004,
697 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
698 cmd);
bad75002
AE		 699 cmd->result = DID_NO_CONNECT << 16;
700 goto qc24_fail_command;
701 }
aa651be8
CD		 702
703 if (!fcport) {
704 cmd->result = DID_NO_CONNECT << 16;
705 goto qc24_fail_command;
706 }
707
fca29703
AV		 708 if (atomic_read(&fcport->state) != FCS_ONLINE) {
709 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 710 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 711 ql_dbg(ql_dbg_io, vha, 0x3005,
712 "Returning DNC, fcport_state=%d loop_state=%d.\n",
713 atomic_read(&fcport->state),
714 atomic_read(&base_vha->loop_state));
fca29703
AV		 715 cmd->result = DID_NO_CONNECT << 16;
716 goto qc24_fail_command;
717 }
7b594131 718 goto qc24_target_busy;
fca29703
AV		 719 }
720
b00ee7d7 721 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
3c290d0b
CD		 722 if (!sp) {
723 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
f5e3e40b 724 goto qc24_host_busy;
3c290d0b 725 }
fca29703 726
9ba56b95
GM		 727 sp->u.scmd.cmd = cmd;
728 sp->type = SRB_SCSI_CMD;
729 atomic_set(&sp->ref_count, 1);
730 CMD_SP(cmd) = (void *)sp;
731 sp->free = qla2x00_sp_free_dma;
732 sp->done = qla2x00_sp_compl;
733
e315cd28 734 rval = ha->isp_ops->start_scsi(sp);
7c3df132 735 if (rval != QLA_SUCCESS) {
53016ed3 736 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 737 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
3c290d0b 738 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
fca29703 739 goto qc24_host_busy_free_sp;
7c3df132 740 }
fca29703 741
fca29703
AV		 742 return 0;
743
744qc24_host_busy_free_sp:
9ba56b95 745 qla2x00_sp_free_dma(ha, sp);
fca29703 746
f5e3e40b 747qc24_host_busy:
fca29703
AV		 748 return SCSI_MLQUEUE_HOST_BUSY;
749
7b594131
MC		 750qc24_target_busy:
751 return SCSI_MLQUEUE_TARGET_BUSY;
752
fca29703 753qc24_fail_command:
f5e3e40b 754 cmd->scsi_done(cmd);
fca29703
AV		 755
756 return 0;
757}
758
1da177e4
LT		 759/*
760 * qla2x00_eh_wait_on_command
761 * Waits for the command to be returned by the Firmware for some
762 * max time.
763 *
764 * Input:
1da177e4 765 * cmd = Scsi Command to wait on.
1da177e4
LT		 766 *
767 * Return:
768 * Not Found : 0
769 * Found : 1
770 */
771static int
e315cd28 772qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 773{
fe74c71f
AV		 774#define ABORT_POLLING_PERIOD 1000
775#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 776 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 777 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
778 struct qla_hw_data *ha = vha->hw;
f4f051eb 779 int ret = QLA_SUCCESS;
1da177e4 780
85880801 781 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 782 ql_dbg(ql_dbg_taskm, vha, 0x8005,
783 "Return:eh_wait.\n");
85880801
AV		 784 return ret;
785 }
786
d970432c 787 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 788 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 789 }
790 if (CMD_SP(cmd))
791 ret = QLA_FUNCTION_FAILED;
1da177e4 792
f4f051eb 793 return ret;
1da177e4
LT		 794}
795
796/*
797 * qla2x00_wait_for_hba_online
fa2a1ce5 798 * Wait till the HBA is online after going through
1da177e4
LT		 799 * <= MAX_RETRIES_OF_ISP_ABORT or
800 * finally HBA is disabled ie marked offline
801 *
802 * Input:
803 * ha - pointer to host adapter structure
fa2a1ce5
AV		 804 *
805 * Note:
1da177e4
LT		 806 * Does context switching-Release SPIN_LOCK
807 * (if any) before calling this routine.
808 *
809 * Return:
810 * Success (Adapter is online) : 0
811 * Failed (Adapter is offline/disabled) : 1
812 */
854165f4 813int
e315cd28 814qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 815{
fca29703
AV		 816 int return_status;
817 unsigned long wait_online;
e315cd28
AC		 818 struct qla_hw_data *ha = vha->hw;
819 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 820
fa2a1ce5 821 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 822 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
823 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
824 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
825 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 826
827 msleep(1000);
828 }
e315cd28 829 if (base_vha->flags.online)
fa2a1ce5 830 return_status = QLA_SUCCESS;
1da177e4
LT		 831 else
832 return_status = QLA_FUNCTION_FAILED;
833
1da177e4
LT		 834 return (return_status);
835}
836
86fbee86
LC		 837/*
838 * qla2x00_wait_for_reset_ready
839 * Wait till the HBA is online after going through
840 * <= MAX_RETRIES_OF_ISP_ABORT or
841 * finally HBA is disabled ie marked offline or flash
842 * operations are in progress.
843 *
844 * Input:
845 * ha - pointer to host adapter structure
846 *
847 * Note:
848 * Does context switching-Release SPIN_LOCK
849 * (if any) before calling this routine.
850 *
851 * Return:
852 * Success (Adapter is online/no flash ops) : 0
853 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
854 */
3dbe756a 855static int
86fbee86
LC		 856qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
857{
858 int return_status;
859 unsigned long wait_online;
860 struct qla_hw_data *ha = vha->hw;
861 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
862
863 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
864 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
865 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
866 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
867 ha->optrom_state != QLA_SWAITING ||
868 ha->dpc_active) && time_before(jiffies, wait_online))
869 msleep(1000);
870
871 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
872 return_status = QLA_SUCCESS;
873 else
874 return_status = QLA_FUNCTION_FAILED;
875
7c3df132
SK		 876 ql_dbg(ql_dbg_taskm, vha, 0x8019,
877 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 878
879 return return_status;
880}
881
2533cf67
LC		 882int
883qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
884{
885 int return_status;
886 unsigned long wait_reset;
887 struct qla_hw_data *ha = vha->hw;
888 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
889
890 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
891 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
892 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
893 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
894 ha->dpc_active) && time_before(jiffies, wait_reset)) {
895
896 msleep(1000);
897
898 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
899 ha->flags.chip_reset_done)
900 break;
901 }
902 if (ha->flags.chip_reset_done)
903 return_status = QLA_SUCCESS;
904 else
905 return_status = QLA_FUNCTION_FAILED;
906
907 return return_status;
908}
909
083a469d
GM		 910static void
911sp_get(struct srb *sp)
912{
913 atomic_inc(&sp->ref_count);
914}
915
1da177e4
LT		 916/**************************************************************************
917* qla2xxx_eh_abort
918*
919* Description:
920* The abort function will abort the specified command.
921*
922* Input:
923* cmd = Linux SCSI command packet to be aborted.
924*
925* Returns:
926* Either SUCCESS or FAILED.
927*
928* Note:
2ea00202 929* Only return FAILED if command not returned by firmware.
1da177e4 930**************************************************************************/
e5f82ab8 931static int
1da177e4
LT		 932qla2xxx_eh_abort(struct scsi_cmnd *cmd)
933{
e315cd28 934 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 935 srb_t *sp;
4e98d3b8 936 int ret;
f4f051eb 937 unsigned int id, lun;
18e144d3 938 unsigned long flags;
2ea00202 939 int wait = 0;
e315cd28 940 struct qla_hw_data *ha = vha->hw;
1da177e4 941
f4f051eb 942 if (!CMD_SP(cmd))
2ea00202 943 return SUCCESS;
1da177e4 944
4e98d3b8
AV		 945 ret = fc_block_scsi_eh(cmd);
946 if (ret != 0)
947 return ret;
948 ret = SUCCESS;
949
f4f051eb
AV		 950 id = cmd->device->id;
951 lun = cmd->device->lun;
1da177e4 952
e315cd28 953 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 954 sp = (srb_t *) CMD_SP(cmd);
955 if (!sp) {
956 spin_unlock_irqrestore(&ha->hardware_lock, flags);
957 return SUCCESS;
958 }
1da177e4 959
7c3df132 960 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 961 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
962 vha->host_no, id, lun, sp, cmd);
17d98630 963
170babc3
MC		 964 /* Get a reference to the sp and drop the lock.*/
965 sp_get(sp);
083a469d 966
e315cd28 967 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 968 if (ha->isp_ops->abort_command(sp)) {
a55aac79 969 ret = FAILED;
7c3df132 970 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 971 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 972 } else {
7c3df132 973 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 974 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 975 wait = 1;
976 }
75942064
SK		 977
978 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 979 sp->done(ha, sp, 0);
75942064 980 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 981
bc91ade9
CD		 982 /* Did the command return during mailbox execution? */
983 if (ret == FAILED && !CMD_SP(cmd))
984 ret = SUCCESS;
985
f4f051eb 986 /* Wait for the command to be returned. */
2ea00202 987 if (wait) {
e315cd28 988 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 989 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 990 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 991 ret = FAILED;
f4f051eb 992 }
1da177e4 993 }
1da177e4 994
7c3df132 995 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 996 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
997 vha->host_no, id, lun, wait, ret);
1da177e4 998
f4f051eb
AV		 999 return ret;
1000}
1da177e4 1001
4d78c973 1002int
e315cd28 1003qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1004 unsigned int l, enum nexus_wait_type type)
f4f051eb 1005{
17d98630 1006 int cnt, match, status;
18e144d3 1007 unsigned long flags;
e315cd28 1008 struct qla_hw_data *ha = vha->hw;
73208dfd 1009 struct req_que *req;
4d78c973 1010 srb_t *sp;
9ba56b95 1011 struct scsi_cmnd *cmd;
1da177e4 1012
523ec773 1013 status = QLA_SUCCESS;
17d98630 1014
e315cd28 1015 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1016 req = vha->req;
17d98630 1017 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1018 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1019 sp = req->outstanding_cmds[cnt];
1020 if (!sp)
523ec773 1021 continue;
9ba56b95 1022 if (sp->type != SRB_SCSI_CMD)
cf53b069 1023 continue;
17d98630
AC		 1024 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1025 continue;
1026 match = 0;
9ba56b95 1027 cmd = GET_CMD_SP(sp);
17d98630
AC		 1028 switch (type) {
1029 case WAIT_HOST:
1030 match = 1;
1031 break;
1032 case WAIT_TARGET:
9ba56b95 1033 match = cmd->device->id == t;
17d98630
AC		 1034 break;
1035 case WAIT_LUN:
9ba56b95
GM		 1036 match = (cmd->device->id == t &&
1037 cmd->device->lun == l);
17d98630 1038 break;
73208dfd 1039 }
17d98630
AC		 1040 if (!match)
1041 continue;
1042
1043 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1044 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1045 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1046 }
e315cd28 1047 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1048
1049 return status;
1da177e4
LT		 1050}
1051
523ec773
AV		 1052static char *reset_errors[] = {
1053 "HBA not online",
1054 "HBA not ready",
1055 "Task management failed",
1056 "Waiting for command completions",
1057};
1da177e4 1058
e5f82ab8 1059static int
523ec773 1060__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1061 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1062{
e315cd28 1063 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1064 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1065 int err;
1da177e4 1066
7c3df132 1067 if (!fcport) {
523ec773 1068 return FAILED;
7c3df132 1069 }
1da177e4 1070
4e98d3b8
AV		 1071 err = fc_block_scsi_eh(cmd);
1072 if (err != 0)
1073 return err;
1074
7c3df132 1075 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1076 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1077 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1078
523ec773 1079 err = 0;
7c3df132
SK		 1080 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1081 ql_log(ql_log_warn, vha, 0x800a,
1082 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1083 goto eh_reset_failed;
7c3df132 1084 }
523ec773 1085 err = 2;
2afa19a9 1086 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1087 != QLA_SUCCESS) {
1088 ql_log(ql_log_warn, vha, 0x800c,
1089 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1090 goto eh_reset_failed;
7c3df132 1091 }
523ec773 1092 err = 3;
e315cd28 1093 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1094 cmd->device->lun, type) != QLA_SUCCESS) {
1095 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1096 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1097 goto eh_reset_failed;
7c3df132 1098 }
523ec773 1099
7c3df132 1100 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1101 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1102 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1103
1104 return SUCCESS;
1105
4d78c973 1106eh_reset_failed:
7c3df132 1107 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1108 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1109 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1110 cmd);
523ec773
AV		 1111 return FAILED;
1112}
1da177e4 1113
523ec773
AV		 1114static int
1115qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1116{
e315cd28
AC		 1117 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1118 struct qla_hw_data *ha = vha->hw;
1da177e4 1119
523ec773
AV		 1120 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1121 ha->isp_ops->lun_reset);
1da177e4
LT		 1122}
1123
1da177e4 1124static int
523ec773 1125qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1126{
e315cd28
AC		 1127 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1128 struct qla_hw_data *ha = vha->hw;
1da177e4 1129
523ec773
AV		 1130 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1131 ha->isp_ops->target_reset);
1da177e4
LT		 1132}
1133
1da177e4
LT		 1134/**************************************************************************
1135* qla2xxx_eh_bus_reset
1136*
1137* Description:
1138* The bus reset function will reset the bus and abort any executing
1139* commands.
1140*
1141* Input:
1142* cmd = Linux SCSI command packet of the command that cause the
1143* bus reset.
1144*
1145* Returns:
1146* SUCCESS/FAILURE (defined as macro in scsi.h).
1147*
1148**************************************************************************/
e5f82ab8 1149static int
1da177e4
LT		 1150qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1151{
e315cd28 1152 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1153 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1154 int ret = FAILED;
f4f051eb 1155 unsigned int id, lun;
f4f051eb 1156
f4f051eb
AV		 1157 id = cmd->device->id;
1158 lun = cmd->device->lun;
1da177e4 1159
7c3df132 1160 if (!fcport) {
f4f051eb 1161 return ret;
7c3df132 1162 }
1da177e4 1163
4e98d3b8
AV		 1164 ret = fc_block_scsi_eh(cmd);
1165 if (ret != 0)
1166 return ret;
1167 ret = FAILED;
1168
7c3df132 1169 ql_log(ql_log_info, vha, 0x8012,
46270afe 1170 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1171
e315cd28 1172 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1173 ql_log(ql_log_fatal, vha, 0x8013,
1174 "Wait for hba online failed board disabled.\n");
f4f051eb 1175 goto eh_bus_reset_done;
1da177e4
LT		 1176 }
1177
ad537689
SK		 1178 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1179 ret = SUCCESS;
1180
f4f051eb
AV		 1181 if (ret == FAILED)
1182 goto eh_bus_reset_done;
1da177e4 1183
9a41a62b 1184 /* Flush outstanding commands. */
4d78c973 1185 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1186 QLA_SUCCESS) {
1187 ql_log(ql_log_warn, vha, 0x8014,
1188 "Wait for pending commands failed.\n");
9a41a62b 1189 ret = FAILED;
7c3df132 1190 }
1da177e4 1191
f4f051eb 1192eh_bus_reset_done:
7c3df132 1193 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1194 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1195 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1196
f4f051eb 1197 return ret;
1da177e4
LT		 1198}
1199
1200/**************************************************************************
1201* qla2xxx_eh_host_reset
1202*
1203* Description:
1204* The reset function will reset the Adapter.
1205*
1206* Input:
1207* cmd = Linux SCSI command packet of the command that cause the
1208* adapter reset.
1209*
1210* Returns:
1211* Either SUCCESS or FAILED.
1212*
1213* Note:
1214**************************************************************************/
e5f82ab8 1215static int
1da177e4
LT		 1216qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1217{
e315cd28 1218 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1219 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1220 int ret = FAILED;
f4f051eb 1221 unsigned int id, lun;
e315cd28 1222 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1223
f4f051eb
AV		 1224 id = cmd->device->id;
1225 lun = cmd->device->lun;
f4f051eb 1226
7c3df132 1227 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1228 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1229
86fbee86 1230 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1231 goto eh_host_reset_lock;
1da177e4 1232
e315cd28
AC		 1233 if (vha != base_vha) {
1234 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1235 goto eh_host_reset_lock;
e315cd28 1236 } else {
a9083016
GM		 1237 if (IS_QLA82XX(vha->hw)) {
1238 if (!qla82xx_fcoe_ctx_reset(vha)) {
1239 /* Ctx reset success */
1240 ret = SUCCESS;
1241 goto eh_host_reset_lock;
1242 }
1243 /* fall thru if ctx reset failed */
1244 }
68ca949c
AC		 1245 if (ha->wq)
1246 flush_workqueue(ha->wq);
1247
e315cd28 1248 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1249 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1250 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1251 /* failed. schedule dpc to try */
1252 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1253
7c3df132
SK		 1254 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1255 ql_log(ql_log_warn, vha, 0x802a,
1256 "wait for hba online failed.\n");
e315cd28 1257 goto eh_host_reset_lock;
7c3df132 1258 }
e315cd28
AC		 1259 }
1260 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1261 }
1da177e4 1262
e315cd28 1263 /* Waiting for command to be returned to OS.*/
4d78c973 1264 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1265 QLA_SUCCESS)
f4f051eb 1266 ret = SUCCESS;
1da177e4 1267
f4f051eb 1268eh_host_reset_lock:
cfb0919c
CD		 1269 ql_log(ql_log_info, vha, 0x8017,
1270 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1271 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1272
f4f051eb
AV		 1273 return ret;
1274}
1da177e4
LT		 1275
1276/*
1277* qla2x00_loop_reset
1278* Issue loop reset.
1279*
1280* Input:
1281* ha = adapter block pointer.
1282*
1283* Returns:
1284* 0 = success
1285*/
a4722cf2 1286int
e315cd28 1287qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1288{
0c8c39af 1289 int ret;
bdf79621 1290 struct fc_port *fcport;
e315cd28 1291 struct qla_hw_data *ha = vha->hw;
1da177e4 1292
f4c496c1 1293 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1294 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1295 if (fcport->port_type != FCT_TARGET)
1296 continue;
1297
1298 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1299 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1300 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1301 "Bus Reset failed: Target Reset=%d "
1302 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1303 }
1304 }
1305 }
1306
6246b8a1 1307 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1308 atomic_set(&vha->loop_state, LOOP_DOWN);
1309 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1310 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1311 ret = qla2x00_full_login_lip(vha);
0c8c39af 1312 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1313 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1314 "full_login_lip=%d.\n", ret);
749af3d5 1315 }
0c8c39af
AV		 1316 }
1317
0d6e61bc 1318 if (ha->flags.enable_lip_reset) {
e315cd28 1319 ret = qla2x00_lip_reset(vha);
ad537689 1320 if (ret != QLA_SUCCESS)
7c3df132
SK		 1321 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1322 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1323 }
1324
1da177e4 1325 /* Issue marker command only when we are going to start the I/O */
e315cd28 1326 vha->marker_needed = 1;
1da177e4 1327
0c8c39af 1328 return QLA_SUCCESS;
1da177e4
LT		 1329}
1330
df4bf0bb 1331void
e315cd28 1332qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1333{
73208dfd 1334 int que, cnt;
df4bf0bb
AV		 1335 unsigned long flags;
1336 srb_t *sp;
e315cd28 1337 struct qla_hw_data *ha = vha->hw;
73208dfd 1338 struct req_que *req;
df4bf0bb
AV		 1339
1340 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1341 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1342 req = ha->req_q_map[que];
73208dfd
AC		 1343 if (!req)
1344 continue;
8d93f550
CD		 1345 if (!req->outstanding_cmds)
1346 continue;
1347 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1348 sp = req->outstanding_cmds[cnt];
e612d465 1349 if (sp) {
73208dfd 1350 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1351 sp->done(vha, sp, res);
73208dfd 1352 }
df4bf0bb
AV		 1353 }
1354 }
1355 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1356}
1357
f4f051eb
AV		 1358static int
1359qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1360{
bdf79621 1361 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1362
19a7b4ae 1363 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1364 return -ENXIO;
bdf79621 1365
19a7b4ae 1366 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1367
f4f051eb
AV		 1368 return 0;
1369}
1da177e4 1370
f4f051eb
AV		 1371static int
1372qla2xxx_slave_configure(struct scsi_device *sdev)
1373{
e315cd28 1374 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1375 struct req_que *req = vha->req;
8482e118 1376
9e522cd8
AE		 1377 if (IS_T10_PI_CAPABLE(vha->hw))
1378 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1379
f4f051eb 1380 if (sdev->tagged_supported)
73208dfd 1381 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1382 else
73208dfd 1383 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1384 return 0;
1385}
1da177e4 1386
f4f051eb
AV		 1387static void
1388qla2xxx_slave_destroy(struct scsi_device *sdev)
1389{
1390 sdev->hostdata = NULL;
1da177e4
LT		 1391}
1392
c45dd305
GM		 1393static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1394{
1395 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1396
1397 if (!scsi_track_queue_full(sdev, qdepth))
1398 return;
1399
7c3df132 1400 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1401 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1402 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1403}
1404
1405static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1406{
1407 fc_port_t *fcport = sdev->hostdata;
1408 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1409 struct req_que *req = NULL;
1410
1411 req = vha->req;
1412 if (!req)
1413 return;
1414
1415 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1416 return;
1417
1418 if (sdev->ordered_tags)
1419 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1420 else
1421 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1422
7c3df132 1423 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1424 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1425 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1426}
1427
ce7e4af7 1428static int
e881a172 1429qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1430{
c45dd305
GM		 1431 switch (reason) {
1432 case SCSI_QDEPTH_DEFAULT:
1433 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1434 break;
1435 case SCSI_QDEPTH_QFULL:
1436 qla2x00_handle_queue_full(sdev, qdepth);
1437 break;
1438 case SCSI_QDEPTH_RAMP_UP:
1439 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1440 break;
1441 default:
08002af2 1442 return -EOPNOTSUPP;
c45dd305 1443 }
e881a172 1444
ce7e4af7
AV		 1445 return sdev->queue_depth;
1446}
1447
1448static int
1449qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1450{
1451 if (sdev->tagged_supported) {
1452 scsi_set_tag_type(sdev, tag_type);
1453 if (tag_type)
1454 scsi_activate_tcq(sdev, sdev->queue_depth);
1455 else
1456 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1457 } else
1458 tag_type = 0;
1459
1460 return tag_type;
1461}
1462
3c290d0b
CD		 1463static void
1464qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1465{
1466 scsi_qla_host_t *vp;
1467 struct Scsi_Host *shost;
1468 struct scsi_device *sdev;
1469 struct qla_hw_data *ha = vha->hw;
1470 unsigned long flags;
1471
1472 ha->host_last_rampdown_time = jiffies;
1473
1474 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1475 return;
1476
1477 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1478 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1479 else
1480 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1481
1482 /*
1483 * Geometrically ramp down the queue depth for all devices on this
1484 * adapter
1485 */
1486 spin_lock_irqsave(&ha->vport_slock, flags);
1487 list_for_each_entry(vp, &ha->vp_list, list) {
1488 shost = vp->host;
1489 shost_for_each_device(sdev, shost) {
1490 if (sdev->queue_depth > shost->cmd_per_lun) {
1491 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1492 continue;
1493 ql_log(ql_log_warn, vp, 0x3031,
1494 "%ld:%d:%d: Ramping down queue depth to %d",
1495 vp->host_no, sdev->id, sdev->lun,
1496 ha->cfg_lun_q_depth);
1497 qla2x00_change_queue_depth(sdev,
1498 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1499 }
1500 }
1501 }
1502 spin_unlock_irqrestore(&ha->vport_slock, flags);
1503
1504 return;
1505}
1506
1507static void
1508qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1509{
1510 scsi_qla_host_t *vp;
1511 struct Scsi_Host *shost;
1512 struct scsi_device *sdev;
1513 struct qla_hw_data *ha = vha->hw;
1514 unsigned long flags;
1515
1516 ha->host_last_rampup_time = jiffies;
1517 ha->cfg_lun_q_depth++;
1518
1519 /*
1520 * Linearly ramp up the queue depth for all devices on this
1521 * adapter
1522 */
1523 spin_lock_irqsave(&ha->vport_slock, flags);
1524 list_for_each_entry(vp, &ha->vp_list, list) {
1525 shost = vp->host;
1526 shost_for_each_device(sdev, shost) {
1527 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1528 continue;
1529 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1530 SCSI_QDEPTH_RAMP_UP);
1531 }
1532 }
1533 spin_unlock_irqrestore(&ha->vport_slock, flags);
1534
1535 return;
1536}
1537
1da177e4
LT		 1538/**
1539 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1540 * @ha: HA context
1541 *
1542 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1543 * supported addressing method.
1544 */
1545static void
53303c42 1546qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1547{
7524f9b9 1548 /* Assume a 32bit DMA mask. */
1da177e4 1549 ha->flags.enable_64bit_addressing = 0;
1da177e4 1550
6a35528a 1551 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1552 /* Any upper-dword bits set? */
1553 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1554 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1555 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1556 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1557 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1558 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1559 return;
1da177e4 1560 }
1da177e4 1561 }
7524f9b9 1562
284901a9
YH		 1563 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1564 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1565}
1566
fd34f556 1567static void
e315cd28 1568qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1569{
1570 unsigned long flags = 0;
1571 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1572
1573 spin_lock_irqsave(&ha->hardware_lock, flags);
1574 ha->interrupts_on = 1;
1575 /* enable risc and host interrupts */
1576 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1577 RD_REG_WORD(&reg->ictrl);
1578 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1579
1580}
1581
1582static void
e315cd28 1583qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1584{
1585 unsigned long flags = 0;
1586 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1587
1588 spin_lock_irqsave(&ha->hardware_lock, flags);
1589 ha->interrupts_on = 0;
1590 /* disable risc and host interrupts */
1591 WRT_REG_WORD(&reg->ictrl, 0);
1592 RD_REG_WORD(&reg->ictrl);
1593 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1594}
1595
1596static void
e315cd28 1597qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1598{
1599 unsigned long flags = 0;
1600 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1601
1602 spin_lock_irqsave(&ha->hardware_lock, flags);
1603 ha->interrupts_on = 1;
1604 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1605 RD_REG_DWORD(&reg->ictrl);
1606 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1607}
1608
1609static void
e315cd28 1610qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1611{
1612 unsigned long flags = 0;
1613 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1614
124f85e6
AV		 1615 if (IS_NOPOLLING_TYPE(ha))
1616 return;
fd34f556
AV		 1617 spin_lock_irqsave(&ha->hardware_lock, flags);
1618 ha->interrupts_on = 0;
1619 WRT_REG_DWORD(&reg->ictrl, 0);
1620 RD_REG_DWORD(&reg->ictrl);
1621 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1622}
1623
706f457d
GM		 1624static int
1625qla2x00_iospace_config(struct qla_hw_data *ha)
1626{
1627 resource_size_t pio;
1628 uint16_t msix;
1629 int cpus;
1630
706f457d
GM		 1631 if (pci_request_selected_regions(ha->pdev, ha->bars,
1632 QLA2XXX_DRIVER_NAME)) {
1633 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1634 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1635 pci_name(ha->pdev));
1636 goto iospace_error_exit;
1637 }
1638 if (!(ha->bars & 1))
1639 goto skip_pio;
1640
1641 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1642 pio = pci_resource_start(ha->pdev, 0);
1643 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1644 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1645 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1646 "Invalid pci I/O region size (%s).\n",
1647 pci_name(ha->pdev));
1648 pio = 0;
1649 }
1650 } else {
1651 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1652 "Region #0 no a PIO resource (%s).\n",
1653 pci_name(ha->pdev));
1654 pio = 0;
1655 }
1656 ha->pio_address = pio;
1657 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1658 "PIO address=%llu.\n",
1659 (unsigned long long)ha->pio_address);
1660
1661skip_pio:
1662 /* Use MMIO operations for all accesses. */
1663 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1664 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1665 "Region #1 not an MMIO resource (%s), aborting.\n",
1666 pci_name(ha->pdev));
1667 goto iospace_error_exit;
1668 }
1669 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1670 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1671 "Invalid PCI mem region size (%s), aborting.\n",
1672 pci_name(ha->pdev));
1673 goto iospace_error_exit;
1674 }
1675
1676 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1677 if (!ha->iobase) {
1678 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1679 "Cannot remap MMIO (%s), aborting.\n",
1680 pci_name(ha->pdev));
1681 goto iospace_error_exit;
1682 }
1683
1684 /* Determine queue resources */
1685 ha->max_req_queues = ha->max_rsp_queues = 1;
1686 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1687 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1688 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1689 goto mqiobase_exit;
1690
1691 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1692 pci_resource_len(ha->pdev, 3));
1693 if (ha->mqiobase) {
1694 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1695 "MQIO Base=%p.\n", ha->mqiobase);
1696 /* Read MSIX vector size of the board */
1697 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1698 ha->msix_count = msix;
1699 /* Max queues are bounded by available msix vectors */
1700 /* queue 0 uses two msix vectors */
1701 if (ql2xmultique_tag) {
1702 cpus = num_online_cpus();
1703 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1704 (cpus + 1) : (ha->msix_count - 1);
1705 ha->max_req_queues = 2;
1706 } else if (ql2xmaxqueues > 1) {
1707 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1708 QLA_MQ_SIZE : ql2xmaxqueues;
1709 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1710 "QoS mode set, max no of request queues:%d.\n",
1711 ha->max_req_queues);
1712 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1713 "QoS mode set, max no of request queues:%d.\n",
1714 ha->max_req_queues);
1715 }
1716 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1717 "MSI-X vector count: %d.\n", msix);
1718 } else
1719 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1720 "BAR 3 not enabled.\n");
1721
1722mqiobase_exit:
1723 ha->msix_count = ha->max_rsp_queues + 1;
1724 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1725 "MSIX Count:%d.\n", ha->msix_count);
1726 return (0);
1727
1728iospace_error_exit:
1729 return (-ENOMEM);
1730}
1731
1732
6246b8a1
GM		 1733static int
1734qla83xx_iospace_config(struct qla_hw_data *ha)
1735{
1736 uint16_t msix;
1737 int cpus;
1738
1739 if (pci_request_selected_regions(ha->pdev, ha->bars,
1740 QLA2XXX_DRIVER_NAME)) {
1741 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1742 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1743 pci_name(ha->pdev));
1744
1745 goto iospace_error_exit;
1746 }
1747
1748 /* Use MMIO operations for all accesses. */
1749 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1750 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1751 "Invalid pci I/O region size (%s).\n",
1752 pci_name(ha->pdev));
1753 goto iospace_error_exit;
1754 }
1755 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1756 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1757 "Invalid PCI mem region size (%s), aborting\n",
1758 pci_name(ha->pdev));
1759 goto iospace_error_exit;
1760 }
1761
1762 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1763 if (!ha->iobase) {
1764 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1765 "Cannot remap MMIO (%s), aborting.\n",
1766 pci_name(ha->pdev));
1767 goto iospace_error_exit;
1768 }
1769
1770 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1771 /* 83XX 26XX always use MQ type access for queues
1772 * - mbar 2, a.k.a region 4 */
1773 ha->max_req_queues = ha->max_rsp_queues = 1;
1774 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1775 pci_resource_len(ha->pdev, 4));
1776
1777 if (!ha->mqiobase) {
1778 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1779 "BAR2/region4 not enabled\n");
1780 goto mqiobase_exit;
1781 }
1782
1783 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1784 pci_resource_len(ha->pdev, 2));
1785 if (ha->msixbase) {
1786 /* Read MSIX vector size of the board */
1787 pci_read_config_word(ha->pdev,
1788 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1789 ha->msix_count = msix;
1790 /* Max queues are bounded by available msix vectors */
1791 /* queue 0 uses two msix vectors */
1792 if (ql2xmultique_tag) {
1793 cpus = num_online_cpus();
1794 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1795 (cpus + 1) : (ha->msix_count - 1);
1796 ha->max_req_queues = 2;
1797 } else if (ql2xmaxqueues > 1) {
1798 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1799 QLA_MQ_SIZE : ql2xmaxqueues;
1800 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1801 "QoS mode set, max no of request queues:%d.\n",
1802 ha->max_req_queues);
1803 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1804 "QoS mode set, max no of request queues:%d.\n",
1805 ha->max_req_queues);
1806 }
1807 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1808 "MSI-X vector count: %d.\n", msix);
1809 } else
1810 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1811 "BAR 1 not enabled.\n");
1812
1813mqiobase_exit:
1814 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1815
1816 qlt_83xx_iospace_config(ha);
1817
6246b8a1
GM		 1818 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1819 "MSIX Count:%d.\n", ha->msix_count);
1820 return 0;
1821
1822iospace_error_exit:
1823 return -ENOMEM;
1824}
1825
fd34f556
AV		 1826static struct isp_operations qla2100_isp_ops = {
1827 .pci_config = qla2100_pci_config,
1828 .reset_chip = qla2x00_reset_chip,
1829 .chip_diag = qla2x00_chip_diag,
1830 .config_rings = qla2x00_config_rings,
1831 .reset_adapter = qla2x00_reset_adapter,
1832 .nvram_config = qla2x00_nvram_config,
1833 .update_fw_options = qla2x00_update_fw_options,
1834 .load_risc = qla2x00_load_risc,
1835 .pci_info_str = qla2x00_pci_info_str,
1836 .fw_version_str = qla2x00_fw_version_str,
1837 .intr_handler = qla2100_intr_handler,
1838 .enable_intrs = qla2x00_enable_intrs,
1839 .disable_intrs = qla2x00_disable_intrs,
1840 .abort_command = qla2x00_abort_command,
523ec773
AV		 1841 .target_reset = qla2x00_abort_target,
1842 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1843 .fabric_login = qla2x00_login_fabric,
1844 .fabric_logout = qla2x00_fabric_logout,
1845 .calc_req_entries = qla2x00_calc_iocbs_32,
1846 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1847 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1848 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1849 .read_nvram = qla2x00_read_nvram_data,
1850 .write_nvram = qla2x00_write_nvram_data,
1851 .fw_dump = qla2100_fw_dump,
1852 .beacon_on = NULL,
1853 .beacon_off = NULL,
1854 .beacon_blink = NULL,
1855 .read_optrom = qla2x00_read_optrom_data,
1856 .write_optrom = qla2x00_write_optrom_data,
1857 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1858 .start_scsi = qla2x00_start_scsi,
a9083016 1859 .abort_isp = qla2x00_abort_isp,
706f457d 1860 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1861};
1862
1863static struct isp_operations qla2300_isp_ops = {
1864 .pci_config = qla2300_pci_config,
1865 .reset_chip = qla2x00_reset_chip,
1866 .chip_diag = qla2x00_chip_diag,
1867 .config_rings = qla2x00_config_rings,
1868 .reset_adapter = qla2x00_reset_adapter,
1869 .nvram_config = qla2x00_nvram_config,
1870 .update_fw_options = qla2x00_update_fw_options,
1871 .load_risc = qla2x00_load_risc,
1872 .pci_info_str = qla2x00_pci_info_str,
1873 .fw_version_str = qla2x00_fw_version_str,
1874 .intr_handler = qla2300_intr_handler,
1875 .enable_intrs = qla2x00_enable_intrs,
1876 .disable_intrs = qla2x00_disable_intrs,
1877 .abort_command = qla2x00_abort_command,
523ec773
AV		 1878 .target_reset = qla2x00_abort_target,
1879 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1880 .fabric_login = qla2x00_login_fabric,
1881 .fabric_logout = qla2x00_fabric_logout,
1882 .calc_req_entries = qla2x00_calc_iocbs_32,
1883 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1884 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1885 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1886 .read_nvram = qla2x00_read_nvram_data,
1887 .write_nvram = qla2x00_write_nvram_data,
1888 .fw_dump = qla2300_fw_dump,
1889 .beacon_on = qla2x00_beacon_on,
1890 .beacon_off = qla2x00_beacon_off,
1891 .beacon_blink = qla2x00_beacon_blink,
1892 .read_optrom = qla2x00_read_optrom_data,
1893 .write_optrom = qla2x00_write_optrom_data,
1894 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1895 .start_scsi = qla2x00_start_scsi,
a9083016 1896 .abort_isp = qla2x00_abort_isp,
706f457d 1897 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1898};
1899
1900static struct isp_operations qla24xx_isp_ops = {
1901 .pci_config = qla24xx_pci_config,
1902 .reset_chip = qla24xx_reset_chip,
1903 .chip_diag = qla24xx_chip_diag,
1904 .config_rings = qla24xx_config_rings,
1905 .reset_adapter = qla24xx_reset_adapter,
1906 .nvram_config = qla24xx_nvram_config,
1907 .update_fw_options = qla24xx_update_fw_options,
1908 .load_risc = qla24xx_load_risc,
1909 .pci_info_str = qla24xx_pci_info_str,
1910 .fw_version_str = qla24xx_fw_version_str,
1911 .intr_handler = qla24xx_intr_handler,
1912 .enable_intrs = qla24xx_enable_intrs,
1913 .disable_intrs = qla24xx_disable_intrs,
1914 .abort_command = qla24xx_abort_command,
523ec773
AV		 1915 .target_reset = qla24xx_abort_target,
1916 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1917 .fabric_login = qla24xx_login_fabric,
1918 .fabric_logout = qla24xx_fabric_logout,
1919 .calc_req_entries = NULL,
1920 .build_iocbs = NULL,
1921 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1922 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1923 .read_nvram = qla24xx_read_nvram_data,
1924 .write_nvram = qla24xx_write_nvram_data,
1925 .fw_dump = qla24xx_fw_dump,
1926 .beacon_on = qla24xx_beacon_on,
1927 .beacon_off = qla24xx_beacon_off,
1928 .beacon_blink = qla24xx_beacon_blink,
1929 .read_optrom = qla24xx_read_optrom_data,
1930 .write_optrom = qla24xx_write_optrom_data,
1931 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1932 .start_scsi = qla24xx_start_scsi,
a9083016 1933 .abort_isp = qla2x00_abort_isp,
706f457d 1934 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1935};
1936
c3a2f0df
AV		 1937static struct isp_operations qla25xx_isp_ops = {
1938 .pci_config = qla25xx_pci_config,
1939 .reset_chip = qla24xx_reset_chip,
1940 .chip_diag = qla24xx_chip_diag,
1941 .config_rings = qla24xx_config_rings,
1942 .reset_adapter = qla24xx_reset_adapter,
1943 .nvram_config = qla24xx_nvram_config,
1944 .update_fw_options = qla24xx_update_fw_options,
1945 .load_risc = qla24xx_load_risc,
1946 .pci_info_str = qla24xx_pci_info_str,
1947 .fw_version_str = qla24xx_fw_version_str,
1948 .intr_handler = qla24xx_intr_handler,
1949 .enable_intrs = qla24xx_enable_intrs,
1950 .disable_intrs = qla24xx_disable_intrs,
1951 .abort_command = qla24xx_abort_command,
523ec773
AV		 1952 .target_reset = qla24xx_abort_target,
1953 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1954 .fabric_login = qla24xx_login_fabric,
1955 .fabric_logout = qla24xx_fabric_logout,
1956 .calc_req_entries = NULL,
1957 .build_iocbs = NULL,
1958 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1959 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1960 .read_nvram = qla25xx_read_nvram_data,
1961 .write_nvram = qla25xx_write_nvram_data,
1962 .fw_dump = qla25xx_fw_dump,
1963 .beacon_on = qla24xx_beacon_on,
1964 .beacon_off = qla24xx_beacon_off,
1965 .beacon_blink = qla24xx_beacon_blink,
338c9161 1966 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1967 .write_optrom = qla24xx_write_optrom_data,
1968 .get_flash_version = qla24xx_get_flash_version,
bad75002 1969 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1970 .abort_isp = qla2x00_abort_isp,
706f457d 1971 .iospace_config = qla2x00_iospace_config,
c3a2f0df
AV		 1972};
1973
3a03eb79
AV		 1974static struct isp_operations qla81xx_isp_ops = {
1975 .pci_config = qla25xx_pci_config,
1976 .reset_chip = qla24xx_reset_chip,
1977 .chip_diag = qla24xx_chip_diag,
1978 .config_rings = qla24xx_config_rings,
1979 .reset_adapter = qla24xx_reset_adapter,
1980 .nvram_config = qla81xx_nvram_config,
1981 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1982 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1983 .pci_info_str = qla24xx_pci_info_str,
1984 .fw_version_str = qla24xx_fw_version_str,
1985 .intr_handler = qla24xx_intr_handler,
1986 .enable_intrs = qla24xx_enable_intrs,
1987 .disable_intrs = qla24xx_disable_intrs,
1988 .abort_command = qla24xx_abort_command,
1989 .target_reset = qla24xx_abort_target,
1990 .lun_reset = qla24xx_lun_reset,
1991 .fabric_login = qla24xx_login_fabric,
1992 .fabric_logout = qla24xx_fabric_logout,
1993 .calc_req_entries = NULL,
1994 .build_iocbs = NULL,
1995 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1996 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1997 .read_nvram = NULL,
1998 .write_nvram = NULL,
3a03eb79
AV		 1999 .fw_dump = qla81xx_fw_dump,
2000 .beacon_on = qla24xx_beacon_on,
2001 .beacon_off = qla24xx_beacon_off,
6246b8a1 2002 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2003 .read_optrom = qla25xx_read_optrom_data,
2004 .write_optrom = qla24xx_write_optrom_data,
2005 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2006 .start_scsi = qla24xx_dif_start_scsi,
a9083016 2007 .abort_isp = qla2x00_abort_isp,
706f457d 2008 .iospace_config = qla2x00_iospace_config,
a9083016
GM		 2009};
2010
2011static struct isp_operations qla82xx_isp_ops = {
2012 .pci_config = qla82xx_pci_config,
2013 .reset_chip = qla82xx_reset_chip,
2014 .chip_diag = qla24xx_chip_diag,
2015 .config_rings = qla82xx_config_rings,
2016 .reset_adapter = qla24xx_reset_adapter,
2017 .nvram_config = qla81xx_nvram_config,
2018 .update_fw_options = qla24xx_update_fw_options,
2019 .load_risc = qla82xx_load_risc,
9d55ca66 2020 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2021 .fw_version_str = qla24xx_fw_version_str,
2022 .intr_handler = qla82xx_intr_handler,
2023 .enable_intrs = qla82xx_enable_intrs,
2024 .disable_intrs = qla82xx_disable_intrs,
2025 .abort_command = qla24xx_abort_command,
2026 .target_reset = qla24xx_abort_target,
2027 .lun_reset = qla24xx_lun_reset,
2028 .fabric_login = qla24xx_login_fabric,
2029 .fabric_logout = qla24xx_fabric_logout,
2030 .calc_req_entries = NULL,
2031 .build_iocbs = NULL,
2032 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2033 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2034 .read_nvram = qla24xx_read_nvram_data,
2035 .write_nvram = qla24xx_write_nvram_data,
2036 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 2037 .beacon_on = qla82xx_beacon_on,
2038 .beacon_off = qla82xx_beacon_off,
2039 .beacon_blink = NULL,
a9083016
GM		 2040 .read_optrom = qla82xx_read_optrom_data,
2041 .write_optrom = qla82xx_write_optrom_data,
2042 .get_flash_version = qla24xx_get_flash_version,
2043 .start_scsi = qla82xx_start_scsi,
2044 .abort_isp = qla82xx_abort_isp,
706f457d 2045 .iospace_config = qla82xx_iospace_config,
3a03eb79
AV		 2046};
2047
6246b8a1
GM		 2048static struct isp_operations qla83xx_isp_ops = {
2049 .pci_config = qla25xx_pci_config,
2050 .reset_chip = qla24xx_reset_chip,
2051 .chip_diag = qla24xx_chip_diag,
2052 .config_rings = qla24xx_config_rings,
2053 .reset_adapter = qla24xx_reset_adapter,
2054 .nvram_config = qla81xx_nvram_config,
2055 .update_fw_options = qla81xx_update_fw_options,
2056 .load_risc = qla81xx_load_risc,
2057 .pci_info_str = qla24xx_pci_info_str,
2058 .fw_version_str = qla24xx_fw_version_str,
2059 .intr_handler = qla24xx_intr_handler,
2060 .enable_intrs = qla24xx_enable_intrs,
2061 .disable_intrs = qla24xx_disable_intrs,
2062 .abort_command = qla24xx_abort_command,
2063 .target_reset = qla24xx_abort_target,
2064 .lun_reset = qla24xx_lun_reset,
2065 .fabric_login = qla24xx_login_fabric,
2066 .fabric_logout = qla24xx_fabric_logout,
2067 .calc_req_entries = NULL,
2068 .build_iocbs = NULL,
2069 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2070 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2071 .read_nvram = NULL,
2072 .write_nvram = NULL,
2073 .fw_dump = qla83xx_fw_dump,
2074 .beacon_on = qla24xx_beacon_on,
2075 .beacon_off = qla24xx_beacon_off,
2076 .beacon_blink = qla83xx_beacon_blink,
2077 .read_optrom = qla25xx_read_optrom_data,
2078 .write_optrom = qla24xx_write_optrom_data,
2079 .get_flash_version = qla24xx_get_flash_version,
2080 .start_scsi = qla24xx_dif_start_scsi,
2081 .abort_isp = qla2x00_abort_isp,
2082 .iospace_config = qla83xx_iospace_config,
2083};
2084
ea5b6382 2085static inline void
e315cd28 2086qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2087{
2088 ha->device_type = DT_EXTENDED_IDS;
2089 switch (ha->pdev->device) {
2090 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2091 ha->device_type |= DT_ISP2100;
2092 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2093 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2094 break;
2095 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2096 ha->device_type |= DT_ISP2200;
2097 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2098 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2099 break;
2100 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2101 ha->device_type |= DT_ISP2300;
4a59f71d 2102 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2103 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2104 break;
2105 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2106 ha->device_type |= DT_ISP2312;
4a59f71d 2107 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2108 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2109 break;
2110 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2111 ha->device_type |= DT_ISP2322;
4a59f71d 2112 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2113 if (ha->pdev->subsystem_vendor == 0x1028 &&
2114 ha->pdev->subsystem_device == 0x0170)
2115 ha->device_type |= DT_OEM_001;
441d1072 2116 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2117 break;
2118 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2119 ha->device_type |= DT_ISP6312;
441d1072 2120 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2121 break;
2122 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2123 ha->device_type |= DT_ISP6322;
441d1072 2124 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2125 break;
2126 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2127 ha->device_type |= DT_ISP2422;
4a59f71d 2128 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2129 ha->device_type |= DT_FWI2;
c76f2c01 2130 ha->device_type |= DT_IIDMA;
441d1072 2131 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2132 break;
2133 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2134 ha->device_type |= DT_ISP2432;
4a59f71d 2135 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2136 ha->device_type |= DT_FWI2;
c76f2c01 2137 ha->device_type |= DT_IIDMA;
441d1072 2138 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2139 break;
4d4df193
HK		 2140 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2141 ha->device_type |= DT_ISP8432;
2142 ha->device_type |= DT_ZIO_SUPPORTED;
2143 ha->device_type |= DT_FWI2;
2144 ha->device_type |= DT_IIDMA;
2145 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2146 break;
044cc6c8
AV		 2147 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2148 ha->device_type |= DT_ISP5422;
e428924c 2149 ha->device_type |= DT_FWI2;
441d1072 2150 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2151 break;
044cc6c8
AV		 2152 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2153 ha->device_type |= DT_ISP5432;
e428924c 2154 ha->device_type |= DT_FWI2;
441d1072 2155 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2156 break;
c3a2f0df
AV		 2157 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2158 ha->device_type |= DT_ISP2532;
2159 ha->device_type |= DT_ZIO_SUPPORTED;
2160 ha->device_type |= DT_FWI2;
2161 ha->device_type |= DT_IIDMA;
441d1072 2162 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2163 break;
3a03eb79
AV		 2164 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2165 ha->device_type |= DT_ISP8001;
2166 ha->device_type |= DT_ZIO_SUPPORTED;
2167 ha->device_type |= DT_FWI2;
2168 ha->device_type |= DT_IIDMA;
2169 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2170 break;
a9083016
GM		 2171 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2172 ha->device_type |= DT_ISP8021;
2173 ha->device_type |= DT_ZIO_SUPPORTED;
2174 ha->device_type |= DT_FWI2;
2175 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2176 /* Initialize 82XX ISP flags */
2177 qla82xx_init_flags(ha);
2178 break;
6246b8a1
GM		 2179 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2180 ha->device_type |= DT_ISP2031;
2181 ha->device_type |= DT_ZIO_SUPPORTED;
2182 ha->device_type |= DT_FWI2;
2183 ha->device_type |= DT_IIDMA;
2184 ha->device_type |= DT_T10_PI;
2185 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2186 break;
2187 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2188 ha->device_type |= DT_ISP8031;
2189 ha->device_type |= DT_ZIO_SUPPORTED;
2190 ha->device_type |= DT_FWI2;
2191 ha->device_type |= DT_IIDMA;
2192 ha->device_type |= DT_T10_PI;
2193 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2194 break;
ea5b6382 2195 }
e5b68a61 2196
a9083016
GM		 2197 if (IS_QLA82XX(ha))
2198 ha->port_no = !(ha->portnum & 1);
2199 else
2200 /* Get adapter physical port no from interrupt pin register. */
2201 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2202
e5b68a61
AC		 2203 if (ha->port_no & 1)
2204 ha->flags.port0 = 1;
2205 else
2206 ha->flags.port0 = 0;
7c3df132 2207 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2208 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2209 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 2210}
2211
1e99e33a
AV		 2212static void
2213qla2xxx_scan_start(struct Scsi_Host *shost)
2214{
e315cd28 2215 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2216
cbc8eb67
AV		 2217 if (vha->hw->flags.running_gold_fw)
2218 return;
2219
e315cd28
AC		 2220 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2221 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2222 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2223 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2224}
2225
2226static int
2227qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2228{
e315cd28 2229 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2230
e315cd28 2231 if (!vha->host)
1e99e33a 2232 return 1;
e315cd28 2233 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2234 return 1;
2235
e315cd28 2236 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2237}
2238
1da177e4
LT		 2239/*
2240 * PCI driver interface
2241 */
6f039790 2242static int
7ee61397 2243qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2244{
a1541d5a 2245 int ret = -ENODEV;
1da177e4 2246 struct Scsi_Host *host;
e315cd28
AC		 2247 scsi_qla_host_t *base_vha = NULL;
2248 struct qla_hw_data *ha;
29856e28 2249 char pci_info[30];
7d613ac6 2250 char fw_str[30], wq_name[30];
5433383e 2251 struct scsi_host_template *sht;
642ef983 2252 int bars, mem_only = 0;
e315cd28 2253 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2254 struct req_que *req = NULL;
2255 struct rsp_que *rsp = NULL;
1da177e4 2256
285d0321 2257 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2258 sht = &qla2xxx_driver_template;
5433383e 2259 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2260 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2261 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2262 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2263 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2264 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2265 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2266 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2267 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2268 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) {
285d0321 2269 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2270 mem_only = 1;
7c3df132
SK		 2271 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2272 "Mem only adapter.\n");
285d0321 2273 }
7c3df132
SK		 2274 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2275 "Bars=%d.\n", bars);
285d0321 2276
09483916
BH		 2277 if (mem_only) {
2278 if (pci_enable_device_mem(pdev))
2279 goto probe_out;
2280 } else {
2281 if (pci_enable_device(pdev))
2282 goto probe_out;
2283 }
285d0321 2284
0927678f
JB		 2285 /* This may fail but that's ok */
2286 pci_enable_pcie_error_reporting(pdev);
285d0321 2287
e315cd28
AC		 2288 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2289 if (!ha) {
7c3df132
SK		 2290 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2291 "Unable to allocate memory for ha.\n");
e315cd28 2292 goto probe_out;
1da177e4 2293 }
7c3df132
SK		 2294 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2295 "Memory allocated for ha=%p.\n", ha);
e315cd28 2296 ha->pdev = pdev;
2d70c103 2297 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2298
2299 /* Clear our data area */
285d0321 2300 ha->bars = bars;
09483916 2301 ha->mem_only = mem_only;
df4bf0bb 2302 spin_lock_init(&ha->hardware_lock);
339aa70e 2303 spin_lock_init(&ha->vport_slock);
a9b6f722 2304 mutex_init(&ha->selflogin_lock);
1da177e4 2305
ea5b6382
AV		 2306 /* Set ISP-type information. */
2307 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2308
2309 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2310 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2311 IS_QLA83XX(ha))
ca79cf66 2312 pdev->needs_freset = 1;
ca79cf66 2313
cba1e47f
CD		 2314 ha->prev_topology = 0;
2315 ha->init_cb_size = sizeof(init_cb_t);
2316 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2317 ha->optrom_size = OPTROM_SIZE_2300;
3c290d0b 2318 ha->cfg_lun_q_depth = ql2xmaxqdepth;
cba1e47f 2319
abbd8870 2320 /* Assign ISP specific operations. */
1da177e4 2321 if (IS_QLA2100(ha)) {
642ef983 2322 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2323 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2324 req_length = REQUEST_ENTRY_CNT_2100;
2325 rsp_length = RESPONSE_ENTRY_CNT_2100;
2326 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2327 ha->gid_list_info_size = 4;
3a03eb79
AV		 2328 ha->flash_conf_off = ~0;
2329 ha->flash_data_off = ~0;
2330 ha->nvram_conf_off = ~0;
2331 ha->nvram_data_off = ~0;
fd34f556 2332 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2333 } else if (IS_QLA2200(ha)) {
642ef983 2334 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2335 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2336 req_length = REQUEST_ENTRY_CNT_2200;
2337 rsp_length = RESPONSE_ENTRY_CNT_2100;
2338 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2339 ha->gid_list_info_size = 4;
3a03eb79
AV		 2340 ha->flash_conf_off = ~0;
2341 ha->flash_data_off = ~0;
2342 ha->nvram_conf_off = ~0;
2343 ha->nvram_data_off = ~0;
fd34f556 2344 ha->isp_ops = &qla2100_isp_ops;
fca29703 2345 } else if (IS_QLA23XX(ha)) {
642ef983 2346 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2347 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2348 req_length = REQUEST_ENTRY_CNT_2200;
2349 rsp_length = RESPONSE_ENTRY_CNT_2300;
2350 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2351 ha->gid_list_info_size = 6;
854165f4
AV		 2352 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2353 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2354 ha->flash_conf_off = ~0;
2355 ha->flash_data_off = ~0;
2356 ha->nvram_conf_off = ~0;
2357 ha->nvram_data_off = ~0;
fd34f556 2358 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2359 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2360 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2361 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2362 req_length = REQUEST_ENTRY_CNT_24XX;
2363 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2364 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2365 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2366 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2367 ha->gid_list_info_size = 8;
854165f4 2368 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2369 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2370 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2371 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2372 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2373 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2374 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2375 } else if (IS_QLA25XX(ha)) {
642ef983 2376 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2377 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2378 req_length = REQUEST_ENTRY_CNT_24XX;
2379 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2380 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2381 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2382 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2383 ha->gid_list_info_size = 8;
2384 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2385 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2386 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2387 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2388 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2389 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2390 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2391 } else if (IS_QLA81XX(ha)) {
642ef983 2392 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2393 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2394 req_length = REQUEST_ENTRY_CNT_24XX;
2395 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2396 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2397 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2398 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2399 ha->gid_list_info_size = 8;
2400 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2401 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2402 ha->isp_ops = &qla81xx_isp_ops;
2403 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2404 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2405 ha->nvram_conf_off = ~0;
2406 ha->nvram_data_off = ~0;
a9083016 2407 } else if (IS_QLA82XX(ha)) {
642ef983 2408 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2409 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2410 req_length = REQUEST_ENTRY_CNT_82XX;
2411 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2412 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2413 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2414 ha->gid_list_info_size = 8;
2415 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2416 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2417 ha->isp_ops = &qla82xx_isp_ops;
2418 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2419 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2420 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2421 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2422 } else if (IS_QLA83XX(ha)) {
7d613ac6 2423 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2424 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2425 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2426 req_length = REQUEST_ENTRY_CNT_24XX;
2427 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2428 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2429 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2430 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2431 ha->gid_list_info_size = 8;
2432 ha->optrom_size = OPTROM_SIZE_83XX;
2433 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2434 ha->isp_ops = &qla83xx_isp_ops;
2435 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2436 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2437 ha->nvram_conf_off = ~0;
2438 ha->nvram_data_off = ~0;
1da177e4 2439 }
6246b8a1 2440
7c3df132
SK		 2441 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2442 "mbx_count=%d, req_length=%d, "
2443 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2444 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2445 "max_fibre_devices=%d.\n",
7c3df132
SK		 2446 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2447 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2448 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2449 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2450 "isp_ops=%p, flash_conf_off=%d, "
2451 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2452 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2453 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2454
2455 /* Configure PCI I/O space */
2456 ret = ha->isp_ops->iospace_config(ha);
2457 if (ret)
0a63ad12 2458 goto iospace_config_failed;
706f457d
GM		 2459
2460 ql_log_pci(ql_log_info, pdev, 0x001d,
2461 "Found an ISP%04X irq %d iobase 0x%p.\n",
2462 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2463 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2464 init_completion(&ha->mbx_cmd_comp);
2465 complete(&ha->mbx_cmd_comp);
2466 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2467 init_completion(&ha->dcbx_comp);
f356bef1 2468 init_completion(&ha->lb_portup_comp);
1da177e4 2469
2c3dfe3f 2470 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2471
53303c42 2472 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2473 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2474 "64 Bit addressing is %s.\n",
2475 ha->flags.enable_64bit_addressing ? "enable" :
2476 "disable");
73208dfd 2477 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2478 if (!ret) {
7c3df132
SK		 2479 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2480 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2481
e315cd28
AC		 2482 goto probe_hw_failed;
2483 }
2484
73208dfd 2485 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2486 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2487 req->max_q_depth = ql2xmaxqdepth;
2488
e315cd28
AC		 2489
2490 base_vha = qla2x00_create_host(sht, ha);
2491 if (!base_vha) {
a1541d5a 2492 ret = -ENOMEM;
6e9f21f3 2493 qla2x00_mem_free(ha);
2afa19a9
AC		 2494 qla2x00_free_req_que(ha, req);
2495 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2496 goto probe_hw_failed;
1da177e4
LT		 2497 }
2498
e315cd28
AC		 2499 pci_set_drvdata(pdev, base_vha);
2500
e315cd28 2501 host = base_vha->host;
2afa19a9 2502 base_vha->req = req;
73208dfd
AC		 2503 host->can_queue = req->length + 128;
2504 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2505 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2506 else
e315cd28
AC		 2507 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2508 base_vha->vp_idx;
58548cb5
GM		 2509
2510 /* Set the SG table size based on ISP type */
2511 if (!IS_FWI2_CAPABLE(ha)) {
2512 if (IS_QLA2100(ha))
2513 host->sg_tablesize = 32;
2514 } else {
2515 if (!IS_QLA82XX(ha))
2516 host->sg_tablesize = QLA_SG_ALL;
2517 }
7c3df132
SK		 2518 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2519 "can_queue=%d, req=%p, "
2520 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2521 host->can_queue, base_vha->req,
2522 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2523 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2524 host->cmd_per_lun = 3;
2525 host->unique_id = host->host_no;
e02587d7 2526 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2527 host->max_cmd_len = 32;
2528 else
2529 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2530 host->max_channel = MAX_BUSES - 1;
82515920 2531 host->max_lun = ql2xmaxlun;
e315cd28 2532 host->transportt = qla2xxx_transport_template;
9a069e19 2533 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2534
7c3df132
SK		 2535 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2536 "max_id=%d this_id=%d "
2537 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2538 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2539 host->this_id, host->cmd_per_lun, host->unique_id,
2540 host->max_cmd_len, host->max_channel, host->max_lun,
2541 host->transportt, sht->vendor_id);
2542
9a347ff4
CD		 2543que_init:
2544 /* Alloc arrays of request and response ring ptrs */
2545 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2546 ql_log(ql_log_fatal, base_vha, 0x003d,
2547 "Failed to allocate memory for queue pointers..."
2548 "aborting.\n");
2549 goto probe_init_failed;
2550 }
2551
2d70c103 2552 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2553
73208dfd
AC		 2554 /* Set up the irqs */
2555 ret = qla2x00_request_irqs(ha, rsp);
2556 if (ret)
6e9f21f3 2557 goto probe_init_failed;
90a86fc0
JC		 2558
2559 pci_save_state(pdev);
2560
9a347ff4 2561 /* Assign back pointers */
2afa19a9
AC		 2562 rsp->req = req;
2563 req->rsp = rsp;
9a347ff4 2564
08029990
AV		 2565 /* FWI2-capable only. */
2566 req->req_q_in = &ha->iobase->isp24.req_q_in;
2567 req->req_q_out = &ha->iobase->isp24.req_q_out;
2568 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2569 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2570 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2571 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2572 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2573 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2574 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2575 }
2576
a9083016
GM		 2577 if (IS_QLA82XX(ha)) {
2578 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2579 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2580 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2581 }
2582
7c3df132
SK		 2583 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2584 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2585 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2586 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2587 "req->req_q_in=%p req->req_q_out=%p "
2588 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2589 req->req_q_in, req->req_q_out,
2590 rsp->rsp_q_in, rsp->rsp_q_out);
2591 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2592 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2593 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2594 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2595 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2596 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2597
7c3df132
SK		 2598 if (qla2x00_initialize_adapter(base_vha)) {
2599 ql_log(ql_log_fatal, base_vha, 0x00d6,
2600 "Failed to initialize adapter - Adapter flags %x.\n",
2601 base_vha->device_flags);
1da177e4 2602
a9083016
GM		 2603 if (IS_QLA82XX(ha)) {
2604 qla82xx_idc_lock(ha);
2605 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2606 QLA8XXX_DEV_FAILED);
a9083016 2607 qla82xx_idc_unlock(ha);
7c3df132
SK		 2608 ql_log(ql_log_fatal, base_vha, 0x00d7,
2609 "HW State: FAILED.\n");
a9083016
GM		 2610 }
2611
a1541d5a 2612 ret = -ENODEV;
1da177e4
LT		 2613 goto probe_failed;
2614 }
2615
7163ea81
AC		 2616 if (ha->mqenable) {
2617 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2618 ql_log(ql_log_warn, base_vha, 0x00ec,
2619 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2620 goto que_init;
2621 }
2622 }
68ca949c 2623
cbc8eb67
AV		 2624 if (ha->flags.running_gold_fw)
2625 goto skip_dpc;
2626
1da177e4
LT		 2627 /*
2628 * Startup the kernel thread for this host adapter
2629 */
39a11240 2630 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2631 "%s_dpc", base_vha->host_str);
39a11240 2632 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2633 ql_log(ql_log_fatal, base_vha, 0x00ed,
2634 "Failed to start DPC thread.\n");
39a11240 2635 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2636 goto probe_failed;
2637 }
7c3df132
SK		 2638 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2639 "DPC thread started successfully.\n");
1da177e4 2640
2d70c103
NB		 2641 /*
2642 * If we're not coming up in initiator mode, we might sit for
2643 * a while without waking up the dpc thread, which leads to a
2644 * stuck process warning. So just kick the dpc once here and
2645 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2646 */
2647 qla2xxx_wake_dpc(base_vha);
2648
81178772
SK		 2649 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2650 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2651 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2652 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2653
2654 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2655 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2656 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2657 INIT_WORK(&ha->idc_state_handler,
2658 qla83xx_idc_state_handler_work);
2659 INIT_WORK(&ha->nic_core_unrecoverable,
2660 qla83xx_nic_core_unrecoverable_work);
2661 }
2662
cbc8eb67 2663skip_dpc:
e315cd28
AC		 2664 list_add_tail(&base_vha->list, &ha->vp_list);
2665 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2666
2667 /* Initialized the timer */
e315cd28 2668 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2669 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2670 "Started qla2x00_timer with "
2671 "interval=%d.\n", WATCH_INTERVAL);
2672 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2673 "Detected hba at address=%p.\n",
2674 ha);
d19044c3 2675
e02587d7 2676 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2677 if (ha->fw_attributes & BIT_4) {
9e522cd8 2678 int prot = 0, guard;
bad75002 2679 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2680 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2681 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2682 if (ql2xenabledif == 1)
2683 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2684 scsi_host_set_prot(host,
8cb2049c 2685 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2686 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2687 | SHOST_DIF_TYPE3_PROTECTION
2688 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2689 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2690 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2691
2692 guard = SHOST_DIX_GUARD_CRC;
2693
2694 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2695 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2696 guard |= SHOST_DIX_GUARD_IP;
2697
2698 scsi_host_set_guard(host, guard);
bad75002
AE		 2699 } else
2700 base_vha->flags.difdix_supported = 0;
2701 }
2702
a9083016
GM		 2703 ha->isp_ops->enable_intrs(ha);
2704
a1541d5a
AV		 2705 ret = scsi_add_host(host, &pdev->dev);
2706 if (ret)
2707 goto probe_failed;
2708
1486400f
MR		 2709 base_vha->flags.init_done = 1;
2710 base_vha->flags.online = 1;
2711
7c3df132
SK		 2712 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2713 "Init done and hba is online.\n");
2714
2d70c103
NB		 2715 if (qla_ini_mode_enabled(base_vha))
2716 scsi_scan_host(host);
2717 else
2718 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2719 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2720
e315cd28 2721 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2722
e315cd28 2723 qla2x00_init_host_attr(base_vha);
a1541d5a 2724
e315cd28 2725 qla2x00_dfs_setup(base_vha);
df613b96 2726
7c3df132
SK		 2727 ql_log(ql_log_info, base_vha, 0x00fb,
2728 "QLogic %s - %s.\n",
2729 ha->model_number, ha->model_desc ? ha->model_desc : "");
2730 ql_log(ql_log_info, base_vha, 0x00fc,
2731 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2732 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2733 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2734 base_vha->host_no,
e315cd28 2735 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2736
2d70c103
NB		 2737 qlt_add_target(ha, base_vha);
2738
1da177e4
LT		 2739 return 0;
2740
6e9f21f3 2741probe_init_failed:
2afa19a9 2742 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2743 ha->req_q_map[0] = NULL;
2744 clear_bit(0, ha->req_qid_map);
2afa19a9 2745 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2746 ha->rsp_q_map[0] = NULL;
2747 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2748 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2749
1da177e4 2750probe_failed:
b9978769
AV		 2751 if (base_vha->timer_active)
2752 qla2x00_stop_timer(base_vha);
2753 base_vha->flags.online = 0;
2754 if (ha->dpc_thread) {
2755 struct task_struct *t = ha->dpc_thread;
2756
2757 ha->dpc_thread = NULL;
2758 kthread_stop(t);
2759 }
2760
e315cd28 2761 qla2x00_free_device(base_vha);
1da177e4 2762
e315cd28 2763 scsi_host_put(base_vha->host);
1da177e4 2764
e315cd28 2765probe_hw_failed:
a9083016
GM		 2766 if (IS_QLA82XX(ha)) {
2767 qla82xx_idc_lock(ha);
2768 qla82xx_clear_drv_active(ha);
2769 qla82xx_idc_unlock(ha);
0a63ad12
SK		 2770 }
2771iospace_config_failed:
2772 if (IS_QLA82XX(ha)) {
2773 if (!ha->nx_pcibase)
2774 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
a9083016
GM		 2775 if (!ql2xdbwr)
2776 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2777 } else {
2778 if (ha->iobase)
2779 iounmap(ha->iobase);
2780 }
e315cd28
AC		 2781 pci_release_selected_regions(ha->pdev, ha->bars);
2782 kfree(ha);
2783 ha = NULL;
1da177e4 2784
a1541d5a 2785probe_out:
e315cd28 2786 pci_disable_device(pdev);
a1541d5a 2787 return ret;
1da177e4 2788}
1da177e4 2789
2d70c103
NB		 2790static void
2791qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2792{
2793 struct qla_hw_data *ha = vha->hw;
2794 struct task_struct *t = ha->dpc_thread;
2795
2796 if (ha->dpc_thread == NULL)
2797 return;
2798 /*
2799 * qla2xxx_wake_dpc checks for ->dpc_thread
2800 * so we need to zero it out.
2801 */
2802 ha->dpc_thread = NULL;
2803 kthread_stop(t);
2804}
2805
e30d1756
MI		 2806static void
2807qla2x00_shutdown(struct pci_dev *pdev)
2808{
2809 scsi_qla_host_t *vha;
2810 struct qla_hw_data *ha;
2811
552f3f9a
MI		 2812 if (!atomic_read(&pdev->enable_cnt))
2813 return;
2814
e30d1756
MI		 2815 vha = pci_get_drvdata(pdev);
2816 ha = vha->hw;
2817
2818 /* Turn-off FCE trace */
2819 if (ha->flags.fce_enabled) {
2820 qla2x00_disable_fce_trace(vha, NULL, NULL);
2821 ha->flags.fce_enabled = 0;
2822 }
2823
2824 /* Turn-off EFT trace */
2825 if (ha->eft)
2826 qla2x00_disable_eft_trace(vha);
2827
2828 /* Stop currently executing firmware. */
2829 qla2x00_try_to_stop_firmware(vha);
2830
2831 /* Turn adapter off line */
2832 vha->flags.online = 0;
2833
2834 /* turn-off interrupts on the card */
2835 if (ha->interrupts_on) {
2836 vha->flags.init_done = 0;
2837 ha->isp_ops->disable_intrs(ha);
2838 }
2839
2840 qla2x00_free_irqs(vha);
2841
2842 qla2x00_free_fw_dump(ha);
2843}
2844
4c993f76 2845static void
7ee61397 2846qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2847{
feafb7b1 2848 scsi_qla_host_t *base_vha, *vha;
e315cd28 2849 struct qla_hw_data *ha;
feafb7b1 2850 unsigned long flags;
e315cd28 2851
9a347ff4
CD		 2852 /*
2853 * If the PCI device is disabled that means that probe failed and any
2854 * resources should be have cleaned up on probe exit.
2855 */
2856 if (!atomic_read(&pdev->enable_cnt))
2857 return;
2858
e315cd28
AC		 2859 base_vha = pci_get_drvdata(pdev);
2860 ha = base_vha->hw;
2861
2d70c103
NB		 2862 ha->flags.host_shutting_down = 1;
2863
220d36b4 2864 set_bit(UNLOADING, &base_vha->dpc_flags);
43ebf16d
AE		 2865 mutex_lock(&ha->vport_lock);
2866 while (ha->cur_vport_count) {
2867 struct Scsi_Host *scsi_host;
feafb7b1 2868
43ebf16d 2869 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2870
43ebf16d
AE		 2871 BUG_ON(base_vha->list.next == &ha->vp_list);
2872 /* This assumes first entry in ha->vp_list is always base vha */
2873 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2874 scsi_host = scsi_host_get(vha->host);
feafb7b1 2875
43ebf16d
AE		 2876 spin_unlock_irqrestore(&ha->vport_slock, flags);
2877 mutex_unlock(&ha->vport_lock);
2878
2879 fc_vport_terminate(vha->fc_vport);
2880 scsi_host_put(vha->host);
feafb7b1 2881
43ebf16d 2882 mutex_lock(&ha->vport_lock);
e315cd28 2883 }
43ebf16d 2884 mutex_unlock(&ha->vport_lock);
1da177e4 2885
7d613ac6
SV		 2886 if (IS_QLA8031(ha)) {
2887 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
2888 "Clearing fcoe driver presence.\n");
2889 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
2890 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
2891 "Error while clearing DRV-Presence.\n");
2892 }
2893
b9978769
AV		 2894 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2895
e315cd28 2896 qla2x00_dfs_remove(base_vha);
c795c1e4 2897
e315cd28 2898 qla84xx_put_chip(base_vha);
c795c1e4 2899
b9978769
AV		 2900 /* Disable timer */
2901 if (base_vha->timer_active)
2902 qla2x00_stop_timer(base_vha);
2903
2904 base_vha->flags.online = 0;
2905
68ca949c
AC		 2906 /* Flush the work queue and remove it */
2907 if (ha->wq) {
2908 flush_workqueue(ha->wq);
2909 destroy_workqueue(ha->wq);
2910 ha->wq = NULL;
2911 }
2912
7d613ac6
SV		 2913 /* Cancel all work and destroy DPC workqueues */
2914 if (ha->dpc_lp_wq) {
2915 cancel_work_sync(&ha->idc_aen);
2916 destroy_workqueue(ha->dpc_lp_wq);
2917 ha->dpc_lp_wq = NULL;
2918 }
2919
2920 if (ha->dpc_hp_wq) {
2921 cancel_work_sync(&ha->nic_core_reset);
2922 cancel_work_sync(&ha->idc_state_handler);
2923 cancel_work_sync(&ha->nic_core_unrecoverable);
2924 destroy_workqueue(ha->dpc_hp_wq);
2925 ha->dpc_hp_wq = NULL;
2926 }
2927
b9978769
AV		 2928 /* Kill the kernel thread for this host */
2929 if (ha->dpc_thread) {
2930 struct task_struct *t = ha->dpc_thread;
2931
2932 /*
2933 * qla2xxx_wake_dpc checks for ->dpc_thread
2934 * so we need to zero it out.
2935 */
2936 ha->dpc_thread = NULL;
2937 kthread_stop(t);
2938 }
2d70c103 2939 qlt_remove_target(ha, base_vha);
b9978769 2940
e315cd28 2941 qla2x00_free_sysfs_attr(base_vha);
df613b96 2942
e315cd28 2943 fc_remove_host(base_vha->host);
4d4df193 2944
e315cd28 2945 scsi_remove_host(base_vha->host);
1da177e4 2946
e315cd28 2947 qla2x00_free_device(base_vha);
bdf79621 2948
e315cd28 2949 scsi_host_put(base_vha->host);
1da177e4 2950
a9083016 2951 if (IS_QLA82XX(ha)) {
b963752f
GM		 2952 qla82xx_idc_lock(ha);
2953 qla82xx_clear_drv_active(ha);
2954 qla82xx_idc_unlock(ha);
2955
a9083016
GM		 2956 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2957 if (!ql2xdbwr)
2958 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2959 } else {
2960 if (ha->iobase)
2961 iounmap(ha->iobase);
1da177e4 2962
a9083016
GM		 2963 if (ha->mqiobase)
2964 iounmap(ha->mqiobase);
6246b8a1
GM		 2965
2966 if (IS_QLA83XX(ha) && ha->msixbase)
2967 iounmap(ha->msixbase);
a9083016 2968 }
73208dfd 2969
e315cd28
AC		 2970 pci_release_selected_regions(ha->pdev, ha->bars);
2971 kfree(ha);
2972 ha = NULL;
1da177e4 2973
90a86fc0
JC		 2974 pci_disable_pcie_error_reporting(pdev);
2975
665db93b 2976 pci_disable_device(pdev);
1da177e4
LT		 2977 pci_set_drvdata(pdev, NULL);
2978}
1da177e4
LT		 2979
2980static void
e315cd28 2981qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2982{
e315cd28 2983 struct qla_hw_data *ha = vha->hw;
1da177e4 2984
85880801
AV		 2985 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2986
2987 /* Disable timer */
2988 if (vha->timer_active)
2989 qla2x00_stop_timer(vha);
2990
2d70c103 2991 qla2x00_stop_dpc_thread(vha);
85880801 2992
2afa19a9 2993 qla25xx_delete_queues(vha);
df613b96 2994 if (ha->flags.fce_enabled)
e315cd28 2995 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2996
a7a167bf 2997 if (ha->eft)
e315cd28 2998 qla2x00_disable_eft_trace(vha);
a7a167bf 2999
f6ef3b18 3000 /* Stop currently executing firmware. */
e315cd28 3001 qla2x00_try_to_stop_firmware(vha);
1da177e4 3002
85880801
AV		 3003 vha->flags.online = 0;
3004
f6ef3b18 3005 /* turn-off interrupts on the card */
a9083016
GM		 3006 if (ha->interrupts_on) {
3007 vha->flags.init_done = 0;
fd34f556 3008 ha->isp_ops->disable_intrs(ha);
a9083016 3009 }
f6ef3b18 3010
e315cd28 3011 qla2x00_free_irqs(vha);
1da177e4 3012
8867048b
CD		 3013 qla2x00_free_fcports(vha);
3014
e315cd28 3015 qla2x00_mem_free(ha);
73208dfd 3016
08de2844
GM		 3017 qla82xx_md_free(vha);
3018
73208dfd 3019 qla2x00_free_queues(ha);
1da177e4
LT		 3020}
3021
8867048b
CD		 3022void qla2x00_free_fcports(struct scsi_qla_host *vha)
3023{
3024 fc_port_t *fcport, *tfcport;
3025
3026 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3027 list_del(&fcport->list);
5f16b331 3028 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3029 kfree(fcport);
3030 fcport = NULL;
3031 }
3032}
3033
d97994dc 3034static inline void
e315cd28 3035qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3036 int defer)
3037{
d97994dc 3038 struct fc_rport *rport;
67becc00 3039 scsi_qla_host_t *base_vha;
044d78e1 3040 unsigned long flags;
d97994dc
AV		 3041
3042 if (!fcport->rport)
3043 return;
3044
3045 rport = fcport->rport;
3046 if (defer) {
67becc00 3047 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3048 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3049 fcport->drport = rport;
044d78e1 3050 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3051 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3052 qla2xxx_wake_dpc(base_vha);
2d70c103 3053 } else {
d97994dc 3054 fc_remote_port_delete(rport);
2d70c103
NB		 3055 qlt_fc_port_deleted(vha, fcport);
3056 }
d97994dc
AV		 3057}
3058
1da177e4
LT		 3059/*
3060 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3061 *
3062 * Input: ha = adapter block pointer. fcport = port structure pointer.
3063 *
3064 * Return: None.
3065 *
3066 * Context:
3067 */
e315cd28 3068void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3069 int do_login, int defer)
1da177e4 3070{
2c3dfe3f 3071 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3072 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3073 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3074 qla2x00_schedule_rport_del(vha, fcport, defer);
3075 }
fa2a1ce5 3076 /*
1da177e4
LT		 3077 * We may need to retry the login, so don't change the state of the
3078 * port but do the retries.
3079 */
3080 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3081 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3082
3083 if (!do_login)
3084 return;
3085
3086 if (fcport->login_retry == 0) {
e315cd28
AC		 3087 fcport->login_retry = vha->hw->login_retry_count;
3088 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3089
7c3df132
SK		 3090 ql_dbg(ql_dbg_disc, vha, 0x2067,
3091 "Port login retry "
1da177e4 3092 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 3093 "id = 0x%04x retry cnt=%d.\n",
3094 fcport->port_name[0], fcport->port_name[1],
3095 fcport->port_name[2], fcport->port_name[3],
3096 fcport->port_name[4], fcport->port_name[5],
3097 fcport->port_name[6], fcport->port_name[7],
3098 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3099 }
3100}
3101
3102/*
3103 * qla2x00_mark_all_devices_lost
3104 * Updates fcport state when device goes offline.
3105 *
3106 * Input:
3107 * ha = adapter block pointer.
3108 * fcport = port structure pointer.
3109 *
3110 * Return:
3111 * None.
3112 *
3113 * Context:
3114 */
3115void
e315cd28 3116qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3117{
3118 fc_port_t *fcport;
3119
e315cd28 3120 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3121 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3122 continue;
0d6e61bc 3123
1da177e4
LT		 3124 /*
3125 * No point in marking the device as lost, if the device is
3126 * already DEAD.
3127 */
3128 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3129 continue;
e315cd28 3130 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3131 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3132 if (defer)
3133 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3134 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3135 qla2x00_schedule_rport_del(vha, fcport, defer);
3136 }
1da177e4
LT		 3137 }
3138}
3139
3140/*
3141* qla2x00_mem_alloc
3142* Allocates adapter memory.
3143*
3144* Returns:
3145* 0 = success.
e8711085 3146* !0 = failure.
1da177e4 3147*/
e8711085 3148static int
73208dfd
AC		 3149qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3150 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3151{
3152 char name[16];
1da177e4 3153
e8711085 3154 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3155 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3156 if (!ha->init_cb)
e315cd28 3157 goto fail;
e8711085 3158
2d70c103
NB		 3159 if (qlt_mem_alloc(ha) < 0)
3160 goto fail_free_init_cb;
3161
642ef983
CD		 3162 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3163 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3164 if (!ha->gid_list)
2d70c103 3165 goto fail_free_tgt_mem;
1da177e4 3166
e8711085
AV		 3167 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3168 if (!ha->srb_mempool)
e315cd28 3169 goto fail_free_gid_list;
e8711085 3170
a9083016
GM		 3171 if (IS_QLA82XX(ha)) {
3172 /* Allocate cache for CT6 Ctx. */
3173 if (!ctx_cachep) {
3174 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3175 sizeof(struct ct6_dsd), 0,
3176 SLAB_HWCACHE_ALIGN, NULL);
3177 if (!ctx_cachep)
3178 goto fail_free_gid_list;
3179 }
3180 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3181 ctx_cachep);
3182 if (!ha->ctx_mempool)
3183 goto fail_free_srb_mempool;
7c3df132
SK		 3184 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3185 "ctx_cachep=%p ctx_mempool=%p.\n",
3186 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3187 }
3188
e8711085
AV		 3189 /* Get memory for cached NVRAM */
3190 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3191 if (!ha->nvram)
a9083016 3192 goto fail_free_ctx_mempool;
e8711085 3193
e315cd28
AC		 3194 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3195 ha->pdev->device);
3196 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3197 DMA_POOL_SIZE, 8, 0);
3198 if (!ha->s_dma_pool)
3199 goto fail_free_nvram;
3200
7c3df132
SK		 3201 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3202 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3203 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3204
bad75002 3205 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3206 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3207 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3208 if (!ha->dl_dma_pool) {
7c3df132
SK		 3209 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3210 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3211 goto fail_s_dma_pool;
3212 }
3213
3214 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3215 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3216 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3217 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3218 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3219 goto fail_dl_dma_pool;
3220 }
7c3df132
SK		 3221 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3222 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3223 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3224 }
3225
e8711085
AV		 3226 /* Allocate memory for SNS commands */
3227 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3228 /* Get consistent memory allocated for SNS commands */
e8711085 3229 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3230 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3231 if (!ha->sns_cmd)
e315cd28 3232 goto fail_dma_pool;
7c3df132 3233 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3234 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3235 } else {
e315cd28 3236 /* Get consistent memory allocated for MS IOCB */
e8711085 3237 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3238 &ha->ms_iocb_dma);
e8711085 3239 if (!ha->ms_iocb)
e315cd28
AC		 3240 goto fail_dma_pool;
3241 /* Get consistent memory allocated for CT SNS commands */
e8711085 3242 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3243 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3244 if (!ha->ct_sns)
3245 goto fail_free_ms_iocb;
7c3df132
SK		 3246 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3247 "ms_iocb=%p ct_sns=%p.\n",
3248 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3249 }
3250
e315cd28 3251 /* Allocate memory for request ring */
73208dfd
AC		 3252 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3253 if (!*req) {
7c3df132
SK		 3254 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3255 "Failed to allocate memory for req.\n");
e315cd28
AC		 3256 goto fail_req;
3257 }
73208dfd
AC		 3258 (*req)->length = req_len;
3259 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3260 ((*req)->length + 1) * sizeof(request_t),
3261 &(*req)->dma, GFP_KERNEL);
3262 if (!(*req)->ring) {
7c3df132
SK		 3263 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3264 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3265 goto fail_req_ring;
3266 }
3267 /* Allocate memory for response ring */
73208dfd
AC		 3268 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3269 if (!*rsp) {
7c3df132
SK		 3270 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3271 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3272 goto fail_rsp;
3273 }
73208dfd
AC		 3274 (*rsp)->hw = ha;
3275 (*rsp)->length = rsp_len;
3276 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3277 ((*rsp)->length + 1) * sizeof(response_t),
3278 &(*rsp)->dma, GFP_KERNEL);
3279 if (!(*rsp)->ring) {
7c3df132
SK		 3280 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3281 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3282 goto fail_rsp_ring;
3283 }
73208dfd
AC		 3284 (*req)->rsp = *rsp;
3285 (*rsp)->req = *req;
7c3df132
SK		 3286 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3287 "req=%p req->length=%d req->ring=%p rsp=%p "
3288 "rsp->length=%d rsp->ring=%p.\n",
3289 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3290 (*rsp)->ring);
73208dfd
AC		 3291 /* Allocate memory for NVRAM data for vports */
3292 if (ha->nvram_npiv_size) {
3293 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3294 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3295 if (!ha->npiv_info) {
7c3df132
SK		 3296 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3297 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3298 goto fail_npiv_info;
3299 }
3300 } else
3301 ha->npiv_info = NULL;
e8711085 3302
b64b0e8f 3303 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3304 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3305 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3306 &ha->ex_init_cb_dma);
3307 if (!ha->ex_init_cb)
3308 goto fail_ex_init_cb;
7c3df132
SK		 3309 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3310 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3311 }
3312
a9083016
GM		 3313 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3314
5ff1d584
AV		 3315 /* Get consistent memory allocated for Async Port-Database. */
3316 if (!IS_FWI2_CAPABLE(ha)) {
3317 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3318 &ha->async_pd_dma);
3319 if (!ha->async_pd)
3320 goto fail_async_pd;
7c3df132
SK		 3321 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3322 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3323 }
3324
e315cd28 3325 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3326
3327 /* Allocate memory for our loop_id bitmap */
3328 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3329 GFP_KERNEL);
3330 if (!ha->loop_id_map)
3331 goto fail_async_pd;
3332 else {
3333 qla2x00_set_reserved_loop_ids(ha);
3334 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3335 "loop_id_map=%p. \n", ha->loop_id_map);
3336 }
3337
e315cd28
AC		 3338 return 1;
3339
5ff1d584
AV		 3340fail_async_pd:
3341 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3342fail_ex_init_cb:
3343 kfree(ha->npiv_info);
73208dfd
AC		 3344fail_npiv_info:
3345 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3346 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3347 (*rsp)->ring = NULL;
3348 (*rsp)->dma = 0;
e315cd28 3349fail_rsp_ring:
73208dfd 3350 kfree(*rsp);
e315cd28 3351fail_rsp:
73208dfd
AC		 3352 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3353 sizeof(request_t), (*req)->ring, (*req)->dma);
3354 (*req)->ring = NULL;
3355 (*req)->dma = 0;
e315cd28 3356fail_req_ring:
73208dfd 3357 kfree(*req);
e315cd28
AC		 3358fail_req:
3359 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3360 ha->ct_sns, ha->ct_sns_dma);
3361 ha->ct_sns = NULL;
3362 ha->ct_sns_dma = 0;
e8711085
AV		 3363fail_free_ms_iocb:
3364 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3365 ha->ms_iocb = NULL;
3366 ha->ms_iocb_dma = 0;
e315cd28 3367fail_dma_pool:
bad75002 3368 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3369 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3370 ha->fcp_cmnd_dma_pool = NULL;
3371 }
3372fail_dl_dma_pool:
bad75002 3373 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3374 dma_pool_destroy(ha->dl_dma_pool);
3375 ha->dl_dma_pool = NULL;
3376 }
3377fail_s_dma_pool:
e315cd28
AC		 3378 dma_pool_destroy(ha->s_dma_pool);
3379 ha->s_dma_pool = NULL;
e8711085
AV		 3380fail_free_nvram:
3381 kfree(ha->nvram);
3382 ha->nvram = NULL;
a9083016
GM		 3383fail_free_ctx_mempool:
3384 mempool_destroy(ha->ctx_mempool);
3385 ha->ctx_mempool = NULL;
e8711085
AV		 3386fail_free_srb_mempool:
3387 mempool_destroy(ha->srb_mempool);
3388 ha->srb_mempool = NULL;
e8711085 3389fail_free_gid_list:
642ef983
CD		 3390 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3391 ha->gid_list,
e315cd28 3392 ha->gid_list_dma);
e8711085
AV		 3393 ha->gid_list = NULL;
3394 ha->gid_list_dma = 0;
2d70c103
NB		 3395fail_free_tgt_mem:
3396 qlt_mem_free(ha);
e315cd28
AC		 3397fail_free_init_cb:
3398 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3399 ha->init_cb_dma);
3400 ha->init_cb = NULL;
3401 ha->init_cb_dma = 0;
e8711085 3402fail:
7c3df132
SK		 3403 ql_log(ql_log_fatal, NULL, 0x0030,
3404 "Memory allocation failure.\n");
e8711085 3405 return -ENOMEM;
1da177e4
LT		 3406}
3407
3408/*
e30d1756
MI		 3409* qla2x00_free_fw_dump
3410* Frees fw dump stuff.
1da177e4
LT		 3411*
3412* Input:
e30d1756 3413* ha = adapter block pointer.
1da177e4 3414*/
a824ebb3 3415static void
e30d1756 3416qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3417{
df613b96
AV		 3418 if (ha->fce)
3419 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3420 ha->fce_dma);
df613b96 3421
a7a167bf
AV		 3422 if (ha->fw_dump) {
3423 if (ha->eft)
3424 dma_free_coherent(&ha->pdev->dev,
e30d1756 3425 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3426 vfree(ha->fw_dump);
3427 }
e30d1756
MI		 3428 ha->fce = NULL;
3429 ha->fce_dma = 0;
3430 ha->eft = NULL;
3431 ha->eft_dma = 0;
3432 ha->fw_dump = NULL;
3433 ha->fw_dumped = 0;
3434 ha->fw_dump_reading = 0;
3435}
3436
3437/*
3438* qla2x00_mem_free
3439* Frees all adapter allocated memory.
3440*
3441* Input:
3442* ha = adapter block pointer.
3443*/
3444static void
3445qla2x00_mem_free(struct qla_hw_data *ha)
3446{
3447 qla2x00_free_fw_dump(ha);
3448
81178772
SK		 3449 if (ha->mctp_dump)
3450 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3451 ha->mctp_dump_dma);
3452
e30d1756
MI		 3453 if (ha->srb_mempool)
3454 mempool_destroy(ha->srb_mempool);
a7a167bf 3455
11bbc1d8
AV		 3456 if (ha->dcbx_tlv)
3457 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3458 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3459
ce0423f4
AV		 3460 if (ha->xgmac_data)
3461 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3462 ha->xgmac_data, ha->xgmac_data_dma);
3463
1da177e4
LT		 3464 if (ha->sns_cmd)
3465 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3466 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3467
3468 if (ha->ct_sns)
3469 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3470 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3471
88729e53
AV		 3472 if (ha->sfp_data)
3473 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3474
1da177e4
LT		 3475 if (ha->ms_iocb)
3476 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3477
b64b0e8f 3478 if (ha->ex_init_cb)
a9083016
GM		 3479 dma_pool_free(ha->s_dma_pool,
3480 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3481
5ff1d584
AV		 3482 if (ha->async_pd)
3483 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3484
1da177e4
LT		 3485 if (ha->s_dma_pool)
3486 dma_pool_destroy(ha->s_dma_pool);
3487
1da177e4 3488 if (ha->gid_list)
642ef983
CD		 3489 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3490 ha->gid_list, ha->gid_list_dma);
1da177e4 3491
a9083016
GM		 3492 if (IS_QLA82XX(ha)) {
3493 if (!list_empty(&ha->gbl_dsd_list)) {
3494 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3495
3496 /* clean up allocated prev pool */
3497 list_for_each_entry_safe(dsd_ptr,
3498 tdsd_ptr, &ha->gbl_dsd_list, list) {
3499 dma_pool_free(ha->dl_dma_pool,
3500 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3501 list_del(&dsd_ptr->list);
3502 kfree(dsd_ptr);
3503 }
3504 }
3505 }
3506
3507 if (ha->dl_dma_pool)
3508 dma_pool_destroy(ha->dl_dma_pool);
3509
3510 if (ha->fcp_cmnd_dma_pool)
3511 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3512
3513 if (ha->ctx_mempool)
3514 mempool_destroy(ha->ctx_mempool);
3515
2d70c103
NB		 3516 qlt_mem_free(ha);
3517
e315cd28
AC		 3518 if (ha->init_cb)
3519 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3520 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3521 vfree(ha->optrom_buffer);
3522 kfree(ha->nvram);
73208dfd 3523 kfree(ha->npiv_info);
7a67735b 3524 kfree(ha->swl);
5f16b331 3525 kfree(ha->loop_id_map);
1da177e4 3526
e8711085 3527 ha->srb_mempool = NULL;
a9083016 3528 ha->ctx_mempool = NULL;
1da177e4
LT		 3529 ha->sns_cmd = NULL;
3530 ha->sns_cmd_dma = 0;
3531 ha->ct_sns = NULL;
3532 ha->ct_sns_dma = 0;
3533 ha->ms_iocb = NULL;
3534 ha->ms_iocb_dma = 0;
1da177e4
LT		 3535 ha->init_cb = NULL;
3536 ha->init_cb_dma = 0;
b64b0e8f
AV		 3537 ha->ex_init_cb = NULL;
3538 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3539 ha->async_pd = NULL;
3540 ha->async_pd_dma = 0;
1da177e4
LT		 3541
3542 ha->s_dma_pool = NULL;
a9083016
GM		 3543 ha->dl_dma_pool = NULL;
3544 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3545
1da177e4
LT		 3546 ha->gid_list = NULL;
3547 ha->gid_list_dma = 0;
2d70c103
NB		 3548
3549 ha->tgt.atio_ring = NULL;
3550 ha->tgt.atio_dma = 0;
3551 ha->tgt.tgt_vp_map = NULL;
e315cd28 3552}
1da177e4 3553
e315cd28
AC		 3554struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3555 struct qla_hw_data *ha)
3556{
3557 struct Scsi_Host *host;
3558 struct scsi_qla_host *vha = NULL;
854165f4 3559
e315cd28
AC		 3560 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3561 if (host == NULL) {
7c3df132
SK		 3562 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3563 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3564 goto fail;
3565 }
3566
3567 /* Clear our data area */
3568 vha = shost_priv(host);
3569 memset(vha, 0, sizeof(scsi_qla_host_t));
3570
3571 vha->host = host;
3572 vha->host_no = host->host_no;
3573 vha->hw = ha;
3574
3575 INIT_LIST_HEAD(&vha->vp_fcports);
3576 INIT_LIST_HEAD(&vha->work_list);
3577 INIT_LIST_HEAD(&vha->list);
3578
f999f4c1
AV		 3579 spin_lock_init(&vha->work_lock);
3580
e315cd28 3581 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3582 ql_dbg(ql_dbg_init, vha, 0x0041,
3583 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3584 vha->host, vha->hw, vha,
3585 dev_name(&(ha->pdev->dev)));
3586
e315cd28
AC		 3587 return vha;
3588
3589fail:
3590 return vha;
1da177e4
LT		 3591}
3592
01ef66bb 3593static struct qla_work_evt *
f999f4c1 3594qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3595{
3596 struct qla_work_evt *e;
feafb7b1
AE		 3597 uint8_t bail;
3598
3599 QLA_VHA_MARK_BUSY(vha, bail);
3600 if (bail)
3601 return NULL;
0971de7f 3602
f999f4c1 3603 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3604 if (!e) {
3605 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3606 return NULL;
feafb7b1 3607 }
0971de7f
AV		 3608
3609 INIT_LIST_HEAD(&e->list);
3610 e->type = type;
3611 e->flags = QLA_EVT_FLAG_FREE;
3612 return e;
3613}
3614
01ef66bb 3615static int
f999f4c1 3616qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3617{
f999f4c1 3618 unsigned long flags;
0971de7f 3619
f999f4c1 3620 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3621 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3622 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3623 qla2xxx_wake_dpc(vha);
f999f4c1 3624
0971de7f
AV		 3625 return QLA_SUCCESS;
3626}
3627
3628int
e315cd28 3629qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3630 u32 data)
3631{
3632 struct qla_work_evt *e;
3633
f999f4c1 3634 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3635 if (!e)
3636 return QLA_FUNCTION_FAILED;
3637
3638 e->u.aen.code = code;
3639 e->u.aen.data = data;
f999f4c1 3640 return qla2x00_post_work(vha, e);
0971de7f
AV		 3641}
3642
8a659571
AV		 3643int
3644qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3645{
3646 struct qla_work_evt *e;
3647
f999f4c1 3648 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3649 if (!e)
3650 return QLA_FUNCTION_FAILED;
3651
3652 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3653 return qla2x00_post_work(vha, e);
8a659571
AV		 3654}
3655
ac280b67
AV		 3656#define qla2x00_post_async_work(name, type) \
3657int qla2x00_post_async_##name##_work( \
3658 struct scsi_qla_host *vha, \
3659 fc_port_t *fcport, uint16_t *data) \
3660{ \
3661 struct qla_work_evt *e; \
3662 \
3663 e = qla2x00_alloc_work(vha, type); \
3664 if (!e) \
3665 return QLA_FUNCTION_FAILED; \
3666 \
3667 e->u.logio.fcport = fcport; \
3668 if (data) { \
3669 e->u.logio.data[0] = data[0]; \
3670 e->u.logio.data[1] = data[1]; \
3671 } \
3672 return qla2x00_post_work(vha, e); \
3673}
3674
3675qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3676qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3677qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3678qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3679qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3680qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3681
3420d36c
AV		 3682int
3683qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3684{
3685 struct qla_work_evt *e;
3686
3687 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3688 if (!e)
3689 return QLA_FUNCTION_FAILED;
3690
3691 e->u.uevent.code = code;
3692 return qla2x00_post_work(vha, e);
3693}
3694
3695static void
3696qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3697{
3698 char event_string[40];
3699 char *envp[] = { event_string, NULL };
3700
3701 switch (code) {
3702 case QLA_UEVENT_CODE_FW_DUMP:
3703 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3704 vha->host_no);
3705 break;
3706 default:
3707 /* do nothing */
3708 break;
3709 }
3710 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3711}
3712
ac280b67 3713void
e315cd28 3714qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3715{
f999f4c1
AV		 3716 struct qla_work_evt *e, *tmp;
3717 unsigned long flags;
3718 LIST_HEAD(work);
0971de7f 3719
f999f4c1
AV		 3720 spin_lock_irqsave(&vha->work_lock, flags);
3721 list_splice_init(&vha->work_list, &work);
3722 spin_unlock_irqrestore(&vha->work_lock, flags);
3723
3724 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3725 list_del_init(&e->list);
0971de7f
AV		 3726
3727 switch (e->type) {
3728 case QLA_EVT_AEN:
e315cd28 3729 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3730 e->u.aen.code, e->u.aen.data);
3731 break;
8a659571
AV		 3732 case QLA_EVT_IDC_ACK:
3733 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3734 break;
ac280b67
AV		 3735 case QLA_EVT_ASYNC_LOGIN:
3736 qla2x00_async_login(vha, e->u.logio.fcport,
3737 e->u.logio.data);
3738 break;
3739 case QLA_EVT_ASYNC_LOGIN_DONE:
3740 qla2x00_async_login_done(vha, e->u.logio.fcport,
3741 e->u.logio.data);
3742 break;
3743 case QLA_EVT_ASYNC_LOGOUT:
3744 qla2x00_async_logout(vha, e->u.logio.fcport);
3745 break;
3746 case QLA_EVT_ASYNC_LOGOUT_DONE:
3747 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3748 e->u.logio.data);
3749 break;
5ff1d584
AV		 3750 case QLA_EVT_ASYNC_ADISC:
3751 qla2x00_async_adisc(vha, e->u.logio.fcport,
3752 e->u.logio.data);
3753 break;
3754 case QLA_EVT_ASYNC_ADISC_DONE:
3755 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3756 e->u.logio.data);
3757 break;
3420d36c
AV		 3758 case QLA_EVT_UEVENT:
3759 qla2x00_uevent_emit(vha, e->u.uevent.code);
3760 break;
0971de7f
AV		 3761 }
3762 if (e->flags & QLA_EVT_FLAG_FREE)
3763 kfree(e);
feafb7b1
AE		 3764
3765 /* For each work completed decrement vha ref count */
3766 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3767 }
e315cd28 3768}
f999f4c1 3769
e315cd28
AC		 3770/* Relogins all the fcports of a vport
3771 * Context: dpc thread
3772 */
3773void qla2x00_relogin(struct scsi_qla_host *vha)
3774{
3775 fc_port_t *fcport;
c6b2fca8 3776 int status;
e315cd28
AC		 3777 uint16_t next_loopid = 0;
3778 struct qla_hw_data *ha = vha->hw;
ac280b67 3779 uint16_t data[2];
e315cd28
AC		 3780
3781 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3782 /*
3783 * If the port is not ONLINE then try to login
3784 * to it if we haven't run out of retries.
3785 */
5ff1d584
AV		 3786 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3787 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3788 fcport->login_retry--;
e315cd28 3789 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3790 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3791 ha->isp_ops->fabric_logout(vha,
3792 fcport->loop_id,
3793 fcport->d_id.b.domain,
3794 fcport->d_id.b.area,
3795 fcport->d_id.b.al_pa);
3796
03bcfb57
JC		 3797 if (fcport->loop_id == FC_NO_LOOP_ID) {
3798 fcport->loop_id = next_loopid =
3799 ha->min_external_loopid;
3800 status = qla2x00_find_new_loop_id(
3801 vha, fcport);
3802 if (status != QLA_SUCCESS) {
3803 /* Ran out of IDs to use */
3804 break;
3805 }
3806 }
3807
ac280b67 3808 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3809 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3810 data[0] = 0;
3811 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3812 status = qla2x00_post_async_login_work(
3813 vha, fcport, data);
3814 if (status == QLA_SUCCESS)
3815 continue;
3816 /* Attempt a retry. */
3817 status = 1;
aaf4d3e2 3818 } else {
ac280b67
AV		 3819 status = qla2x00_fabric_login(vha,
3820 fcport, &next_loopid);
aaf4d3e2
SK		 3821 if (status == QLA_SUCCESS) {
3822 int status2;
3823 uint8_t opts;
3824
3825 opts = 0;
3826 if (fcport->flags &
3827 FCF_FCP2_DEVICE)
3828 opts |= BIT_1;
03003960
SK		 3829 status2 =
3830 qla2x00_get_port_database(
3831 vha, fcport, opts);
aaf4d3e2
SK		 3832 if (status2 != QLA_SUCCESS)
3833 status = 1;
3834 }
3835 }
e315cd28
AC		 3836 } else
3837 status = qla2x00_local_device_login(vha,
3838 fcport);
3839
e315cd28
AC		 3840 if (status == QLA_SUCCESS) {
3841 fcport->old_loop_id = fcport->loop_id;
3842
7c3df132
SK		 3843 ql_dbg(ql_dbg_disc, vha, 0x2003,
3844 "Port login OK: logged in ID 0x%x.\n",
3845 fcport->loop_id);
e315cd28
AC		 3846
3847 qla2x00_update_fcport(vha, fcport);
3848
3849 } else if (status == 1) {
3850 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3851 /* retry the login again */
7c3df132
SK		 3852 ql_dbg(ql_dbg_disc, vha, 0x2007,
3853 "Retrying %d login again loop_id 0x%x.\n",
3854 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3855 } else {
3856 fcport->login_retry = 0;
3857 }
3858
3859 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 3860 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 3861 }
3862 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3863 break;
0971de7f 3864 }
0971de7f
AV		 3865}
3866
7d613ac6
SV		 3867/* Schedule work on any of the dpc-workqueues */
3868void
3869qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
3870{
3871 struct qla_hw_data *ha = base_vha->hw;
3872
3873 switch (work_code) {
3874 case MBA_IDC_AEN: /* 0x8200 */
3875 if (ha->dpc_lp_wq)
3876 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
3877 break;
3878
3879 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
3880 if (!ha->flags.nic_core_reset_hdlr_active) {
3881 if (ha->dpc_hp_wq)
3882 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
3883 } else
3884 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
3885 "NIC Core reset is already active. Skip "
3886 "scheduling it again.\n");
3887 break;
3888 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
3889 if (ha->dpc_hp_wq)
3890 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
3891 break;
3892 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
3893 if (ha->dpc_hp_wq)
3894 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
3895 break;
3896 default:
3897 ql_log(ql_log_warn, base_vha, 0xb05f,
3898 "Unknow work-code=0x%x.\n", work_code);
3899 }
3900
3901 return;
3902}
3903
3904/* Work: Perform NIC Core Unrecoverable state handling */
3905void
3906qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
3907{
3908 struct qla_hw_data *ha =
2ad1b67c 3909 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 3910 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3911 uint32_t dev_state = 0;
3912
3913 qla83xx_idc_lock(base_vha, 0);
3914 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3915 qla83xx_reset_ownership(base_vha);
3916 if (ha->flags.nic_core_reset_owner) {
3917 ha->flags.nic_core_reset_owner = 0;
3918 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3919 QLA8XXX_DEV_FAILED);
3920 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
3921 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
3922 }
3923 qla83xx_idc_unlock(base_vha, 0);
3924}
3925
3926/* Work: Execute IDC state handler */
3927void
3928qla83xx_idc_state_handler_work(struct work_struct *work)
3929{
3930 struct qla_hw_data *ha =
2ad1b67c 3931 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 3932 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3933 uint32_t dev_state = 0;
3934
3935 qla83xx_idc_lock(base_vha, 0);
3936 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3937 if (dev_state == QLA8XXX_DEV_FAILED ||
3938 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
3939 qla83xx_idc_state_handler(base_vha);
3940 qla83xx_idc_unlock(base_vha, 0);
3941}
3942
fa492630 3943static int
7d613ac6
SV		 3944qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
3945{
3946 int rval = QLA_SUCCESS;
3947 unsigned long heart_beat_wait = jiffies + (1 * HZ);
3948 uint32_t heart_beat_counter1, heart_beat_counter2;
3949
3950 do {
3951 if (time_after(jiffies, heart_beat_wait)) {
3952 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
3953 "Nic Core f/w is not alive.\n");
3954 rval = QLA_FUNCTION_FAILED;
3955 break;
3956 }
3957
3958 qla83xx_idc_lock(base_vha, 0);
3959 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3960 &heart_beat_counter1);
3961 qla83xx_idc_unlock(base_vha, 0);
3962 msleep(100);
3963 qla83xx_idc_lock(base_vha, 0);
3964 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3965 &heart_beat_counter2);
3966 qla83xx_idc_unlock(base_vha, 0);
3967 } while (heart_beat_counter1 == heart_beat_counter2);
3968
3969 return rval;
3970}
3971
3972/* Work: Perform NIC Core Reset handling */
3973void
3974qla83xx_nic_core_reset_work(struct work_struct *work)
3975{
3976 struct qla_hw_data *ha =
3977 container_of(work, struct qla_hw_data, nic_core_reset);
3978 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3979 uint32_t dev_state = 0;
3980
81178772
SK		 3981 if (IS_QLA2031(ha)) {
3982 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
3983 ql_log(ql_log_warn, base_vha, 0xb081,
3984 "Failed to dump mctp\n");
3985 return;
3986 }
3987
7d613ac6
SV		 3988 if (!ha->flags.nic_core_reset_hdlr_active) {
3989 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
3990 qla83xx_idc_lock(base_vha, 0);
3991 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3992 &dev_state);
3993 qla83xx_idc_unlock(base_vha, 0);
3994 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
3995 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
3996 "Nic Core f/w is alive.\n");
3997 return;
3998 }
3999 }
4000
4001 ha->flags.nic_core_reset_hdlr_active = 1;
4002 if (qla83xx_nic_core_reset(base_vha)) {
4003 /* NIC Core reset failed. */
4004 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4005 "NIC Core reset failed.\n");
4006 }
4007 ha->flags.nic_core_reset_hdlr_active = 0;
4008 }
4009}
4010
4011/* Work: Handle 8200 IDC aens */
4012void
4013qla83xx_service_idc_aen(struct work_struct *work)
4014{
4015 struct qla_hw_data *ha =
4016 container_of(work, struct qla_hw_data, idc_aen);
4017 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4018 uint32_t dev_state, idc_control;
4019
4020 qla83xx_idc_lock(base_vha, 0);
4021 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4022 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4023 qla83xx_idc_unlock(base_vha, 0);
4024 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4025 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4026 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4027 "Application requested NIC Core Reset.\n");
4028 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4029 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4030 QLA_SUCCESS) {
4031 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4032 "Other protocol driver requested NIC Core Reset.\n");
4033 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4034 }
4035 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4036 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4037 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4038 }
4039}
4040
4041static void
4042qla83xx_wait_logic(void)
4043{
4044 int i;
4045
4046 /* Yield CPU */
4047 if (!in_interrupt()) {
4048 /*
4049 * Wait about 200ms before retrying again.
4050 * This controls the number of retries for single
4051 * lock operation.
4052 */
4053 msleep(100);
4054 schedule();
4055 } else {
4056 for (i = 0; i < 20; i++)
4057 cpu_relax(); /* This a nop instr on i386 */
4058 }
4059}
4060
fa492630 4061static int
7d613ac6
SV		 4062qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4063{
4064 int rval;
4065 uint32_t data;
4066 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4067 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4068 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4069 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4070 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4071
4072 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4073 if (rval)
4074 return rval;
4075
4076 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4077 return QLA_SUCCESS;
4078 } else {
4079 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4080 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4081 data);
4082 if (rval)
4083 return rval;
4084
4085 msleep(200);
4086
4087 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4088 &data);
4089 if (rval)
4090 return rval;
4091
4092 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4093 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4094 ~(idc_lck_rcvry_stage_mask));
4095 rval = qla83xx_wr_reg(base_vha,
4096 QLA83XX_IDC_LOCK_RECOVERY, data);
4097 if (rval)
4098 return rval;
4099
4100 /* Forcefully perform IDC UnLock */
4101 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4102 &data);
4103 if (rval)
4104 return rval;
4105 /* Clear lock-id by setting 0xff */
4106 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4107 0xff);
4108 if (rval)
4109 return rval;
4110 /* Clear lock-recovery by setting 0x0 */
4111 rval = qla83xx_wr_reg(base_vha,
4112 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4113 if (rval)
4114 return rval;
4115 } else
4116 return QLA_SUCCESS;
4117 }
4118
4119 return rval;
4120}
4121
fa492630 4122static int
7d613ac6
SV		 4123qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4124{
4125 int rval = QLA_SUCCESS;
4126 uint32_t o_drv_lockid, n_drv_lockid;
4127 unsigned long lock_recovery_timeout;
4128
4129 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4130retry_lockid:
4131 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4132 if (rval)
4133 goto exit;
4134
4135 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4136 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4137 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4138 return QLA_SUCCESS;
4139 else
4140 return QLA_FUNCTION_FAILED;
4141 }
4142
4143 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4144 if (rval)
4145 goto exit;
4146
4147 if (o_drv_lockid == n_drv_lockid) {
4148 qla83xx_wait_logic();
4149 goto retry_lockid;
4150 } else
4151 return QLA_SUCCESS;
4152
4153exit:
4154 return rval;
4155}
4156
4157void
4158qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4159{
4160 uint16_t options = (requester_id << 15) | BIT_6;
4161 uint32_t data;
6c315553 4162 uint32_t lock_owner;
7d613ac6
SV		 4163 struct qla_hw_data *ha = base_vha->hw;
4164
4165 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4166retry_lock:
4167 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4168 == QLA_SUCCESS) {
4169 if (data) {
4170 /* Setting lock-id to our function-number */
4171 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4172 ha->portnum);
4173 } else {
6c315553
SK		 4174 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4175 &lock_owner);
7d613ac6 4176 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4177 "Failed to acquire IDC lock, acquired by %d, "
4178 "retrying...\n", lock_owner);
7d613ac6
SV		 4179
4180 /* Retry/Perform IDC-Lock recovery */
4181 if (qla83xx_idc_lock_recovery(base_vha)
4182 == QLA_SUCCESS) {
4183 qla83xx_wait_logic();
4184 goto retry_lock;
4185 } else
4186 ql_log(ql_log_warn, base_vha, 0xb075,
4187 "IDC Lock recovery FAILED.\n");
4188 }
4189
4190 }
4191
4192 return;
4193
4194 /* XXX: IDC-lock implementation using access-control mbx */
4195retry_lock2:
4196 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4197 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4198 "Failed to acquire IDC lock. retrying...\n");
4199 /* Retry/Perform IDC-Lock recovery */
4200 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4201 qla83xx_wait_logic();
4202 goto retry_lock2;
4203 } else
4204 ql_log(ql_log_warn, base_vha, 0xb076,
4205 "IDC Lock recovery FAILED.\n");
4206 }
4207
4208 return;
4209}
4210
4211void
4212qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4213{
4214 uint16_t options = (requester_id << 15) | BIT_7, retry;
4215 uint32_t data;
4216 struct qla_hw_data *ha = base_vha->hw;
4217
4218 /* IDC-unlock implementation using driver-unlock/lock-id
4219 * remote registers
4220 */
4221 retry = 0;
4222retry_unlock:
4223 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4224 == QLA_SUCCESS) {
4225 if (data == ha->portnum) {
4226 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4227 /* Clearing lock-id by setting 0xff */
4228 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4229 } else if (retry < 10) {
4230 /* SV: XXX: IDC unlock retrying needed here? */
4231
4232 /* Retry for IDC-unlock */
4233 qla83xx_wait_logic();
4234 retry++;
4235 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4236 "Failed to release IDC lock, retyring=%d\n", retry);
4237 goto retry_unlock;
4238 }
4239 } else if (retry < 10) {
4240 /* Retry for IDC-unlock */
4241 qla83xx_wait_logic();
4242 retry++;
4243 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4244 "Failed to read drv-lockid, retyring=%d\n", retry);
4245 goto retry_unlock;
4246 }
4247
4248 return;
4249
4250 /* XXX: IDC-unlock implementation using access-control mbx */
4251 retry = 0;
4252retry_unlock2:
4253 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4254 if (retry < 10) {
4255 /* Retry for IDC-unlock */
4256 qla83xx_wait_logic();
4257 retry++;
4258 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4259 "Failed to release IDC lock, retyring=%d\n", retry);
4260 goto retry_unlock2;
4261 }
4262 }
4263
4264 return;
4265}
4266
4267int
4268__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4269{
4270 int rval = QLA_SUCCESS;
4271 struct qla_hw_data *ha = vha->hw;
4272 uint32_t drv_presence;
4273
4274 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4275 if (rval == QLA_SUCCESS) {
4276 drv_presence |= (1 << ha->portnum);
4277 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4278 drv_presence);
4279 }
4280
4281 return rval;
4282}
4283
4284int
4285qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4286{
4287 int rval = QLA_SUCCESS;
4288
4289 qla83xx_idc_lock(vha, 0);
4290 rval = __qla83xx_set_drv_presence(vha);
4291 qla83xx_idc_unlock(vha, 0);
4292
4293 return rval;
4294}
4295
4296int
4297__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4298{
4299 int rval = QLA_SUCCESS;
4300 struct qla_hw_data *ha = vha->hw;
4301 uint32_t drv_presence;
4302
4303 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4304 if (rval == QLA_SUCCESS) {
4305 drv_presence &= ~(1 << ha->portnum);
4306 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4307 drv_presence);
4308 }
4309
4310 return rval;
4311}
4312
4313int
4314qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4315{
4316 int rval = QLA_SUCCESS;
4317
4318 qla83xx_idc_lock(vha, 0);
4319 rval = __qla83xx_clear_drv_presence(vha);
4320 qla83xx_idc_unlock(vha, 0);
4321
4322 return rval;
4323}
4324
fa492630 4325static void
7d613ac6
SV		 4326qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4327{
4328 struct qla_hw_data *ha = vha->hw;
4329 uint32_t drv_ack, drv_presence;
4330 unsigned long ack_timeout;
4331
4332 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4333 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4334 while (1) {
4335 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4336 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4337 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4338 break;
4339
4340 if (time_after_eq(jiffies, ack_timeout)) {
4341 ql_log(ql_log_warn, vha, 0xb067,
4342 "RESET ACK TIMEOUT! drv_presence=0x%x "
4343 "drv_ack=0x%x\n", drv_presence, drv_ack);
4344 /*
4345 * The function(s) which did not ack in time are forced
4346 * to withdraw any further participation in the IDC
4347 * reset.
4348 */
4349 if (drv_ack != drv_presence)
4350 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4351 drv_ack);
4352 break;
4353 }
4354
4355 qla83xx_idc_unlock(vha, 0);
4356 msleep(1000);
4357 qla83xx_idc_lock(vha, 0);
4358 }
4359
4360 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4361 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4362}
4363
fa492630 4364static int
7d613ac6
SV		 4365qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4366{
4367 int rval = QLA_SUCCESS;
4368 uint32_t idc_control;
4369
4370 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4371 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4372
4373 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4374 __qla83xx_get_idc_control(vha, &idc_control);
4375 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4376 __qla83xx_set_idc_control(vha, 0);
4377
4378 qla83xx_idc_unlock(vha, 0);
4379 rval = qla83xx_restart_nic_firmware(vha);
4380 qla83xx_idc_lock(vha, 0);
4381
4382 if (rval != QLA_SUCCESS) {
4383 ql_log(ql_log_fatal, vha, 0xb06a,
4384 "Failed to restart NIC f/w.\n");
4385 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4386 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4387 } else {
4388 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4389 "Success in restarting nic f/w.\n");
4390 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4391 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4392 }
4393
4394 return rval;
4395}
4396
4397/* Assumes idc_lock always held on entry */
4398int
4399qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4400{
4401 struct qla_hw_data *ha = base_vha->hw;
4402 int rval = QLA_SUCCESS;
4403 unsigned long dev_init_timeout;
4404 uint32_t dev_state;
4405
4406 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4407 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4408
4409 while (1) {
4410
4411 if (time_after_eq(jiffies, dev_init_timeout)) {
4412 ql_log(ql_log_warn, base_vha, 0xb06e,
4413 "Initialization TIMEOUT!\n");
4414 /* Init timeout. Disable further NIC Core
4415 * communication.
4416 */
4417 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4418 QLA8XXX_DEV_FAILED);
4419 ql_log(ql_log_info, base_vha, 0xb06f,
4420 "HW State: FAILED.\n");
4421 }
4422
4423 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4424 switch (dev_state) {
4425 case QLA8XXX_DEV_READY:
4426 if (ha->flags.nic_core_reset_owner)
4427 qla83xx_idc_audit(base_vha,
4428 IDC_AUDIT_COMPLETION);
4429 ha->flags.nic_core_reset_owner = 0;
4430 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4431 "Reset_owner reset by 0x%x.\n",
4432 ha->portnum);
4433 goto exit;
4434 case QLA8XXX_DEV_COLD:
4435 if (ha->flags.nic_core_reset_owner)
4436 rval = qla83xx_device_bootstrap(base_vha);
4437 else {
4438 /* Wait for AEN to change device-state */
4439 qla83xx_idc_unlock(base_vha, 0);
4440 msleep(1000);
4441 qla83xx_idc_lock(base_vha, 0);
4442 }
4443 break;
4444 case QLA8XXX_DEV_INITIALIZING:
4445 /* Wait for AEN to change device-state */
4446 qla83xx_idc_unlock(base_vha, 0);
4447 msleep(1000);
4448 qla83xx_idc_lock(base_vha, 0);
4449 break;
4450 case QLA8XXX_DEV_NEED_RESET:
4451 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4452 qla83xx_need_reset_handler(base_vha);
4453 else {
4454 /* Wait for AEN to change device-state */
4455 qla83xx_idc_unlock(base_vha, 0);
4456 msleep(1000);
4457 qla83xx_idc_lock(base_vha, 0);
4458 }
4459 /* reset timeout value after need reset handler */
4460 dev_init_timeout = jiffies +
4461 (ha->fcoe_dev_init_timeout * HZ);
4462 break;
4463 case QLA8XXX_DEV_NEED_QUIESCENT:
4464 /* XXX: DEBUG for now */
4465 qla83xx_idc_unlock(base_vha, 0);
4466 msleep(1000);
4467 qla83xx_idc_lock(base_vha, 0);
4468 break;
4469 case QLA8XXX_DEV_QUIESCENT:
4470 /* XXX: DEBUG for now */
4471 if (ha->flags.quiesce_owner)
4472 goto exit;
4473
4474 qla83xx_idc_unlock(base_vha, 0);
4475 msleep(1000);
4476 qla83xx_idc_lock(base_vha, 0);
4477 dev_init_timeout = jiffies +
4478 (ha->fcoe_dev_init_timeout * HZ);
4479 break;
4480 case QLA8XXX_DEV_FAILED:
4481 if (ha->flags.nic_core_reset_owner)
4482 qla83xx_idc_audit(base_vha,
4483 IDC_AUDIT_COMPLETION);
4484 ha->flags.nic_core_reset_owner = 0;
4485 __qla83xx_clear_drv_presence(base_vha);
4486 qla83xx_idc_unlock(base_vha, 0);
4487 qla8xxx_dev_failed_handler(base_vha);
4488 rval = QLA_FUNCTION_FAILED;
4489 qla83xx_idc_lock(base_vha, 0);
4490 goto exit;
4491 case QLA8XXX_BAD_VALUE:
4492 qla83xx_idc_unlock(base_vha, 0);
4493 msleep(1000);
4494 qla83xx_idc_lock(base_vha, 0);
4495 break;
4496 default:
4497 ql_log(ql_log_warn, base_vha, 0xb071,
4498 "Unknow Device State: %x.\n", dev_state);
4499 qla83xx_idc_unlock(base_vha, 0);
4500 qla8xxx_dev_failed_handler(base_vha);
4501 rval = QLA_FUNCTION_FAILED;
4502 qla83xx_idc_lock(base_vha, 0);
4503 goto exit;
4504 }
4505 }
4506
4507exit:
4508 return rval;
4509}
4510
1da177e4
LT		 4511/**************************************************************************
4512* qla2x00_do_dpc
4513* This kernel thread is a task that is schedule by the interrupt handler
4514* to perform the background processing for interrupts.
4515*
4516* Notes:
4517* This task always run in the context of a kernel thread. It
4518* is kick-off by the driver's detect code and starts up
4519* up one per adapter. It immediately goes to sleep and waits for
4520* some fibre event. When either the interrupt handler or
4521* the timer routine detects a event it will one of the task
4522* bits then wake us up.
4523**************************************************************************/
4524static int
4525qla2x00_do_dpc(void *data)
4526{
2c3dfe3f 4527 int rval;
e315cd28
AC		 4528 scsi_qla_host_t *base_vha;
4529 struct qla_hw_data *ha;
1da177e4 4530
e315cd28
AC		 4531 ha = (struct qla_hw_data *)data;
4532 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4533
1da177e4
LT		 4534 set_user_nice(current, -20);
4535
563585ec 4536 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4537 while (!kthread_should_stop()) {
7c3df132
SK		 4538 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4539 "DPC handler sleeping.\n");
1da177e4 4540
39a11240
CH		 4541 schedule();
4542 __set_current_state(TASK_RUNNING);
1da177e4 4543
c142caf0
AV		 4544 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4545 goto end_loop;
1da177e4 4546
85880801 4547 if (ha->flags.eeh_busy) {
7c3df132
SK		 4548 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4549 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4550 goto end_loop;
85880801
AV		 4551 }
4552
1da177e4
LT		 4553 ha->dpc_active = 1;
4554
5f28d2d7
SK		 4555 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4556 "DPC handler waking up, dpc_flags=0x%lx.\n",
4557 base_vha->dpc_flags);
1da177e4 4558
e315cd28 4559 qla2x00_do_work(base_vha);
0971de7f 4560
a9083016
GM		 4561 if (IS_QLA82XX(ha)) {
4562 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4563 &base_vha->dpc_flags)) {
4564 qla82xx_idc_lock(ha);
4565 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 4566 QLA8XXX_DEV_FAILED);
a9083016 4567 qla82xx_idc_unlock(ha);
7c3df132
SK		 4568 ql_log(ql_log_info, base_vha, 0x4004,
4569 "HW State: FAILED.\n");
a9083016
GM		 4570 qla82xx_device_state_handler(base_vha);
4571 continue;
4572 }
4573
4574 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4575 &base_vha->dpc_flags)) {
4576
7c3df132
SK		 4577 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4578 "FCoE context reset scheduled.\n");
a9083016
GM		 4579 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4580 &base_vha->dpc_flags))) {
4581 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4582 /* FCoE-ctx reset failed.
4583 * Escalate to chip-reset
4584 */
4585 set_bit(ISP_ABORT_NEEDED,
4586 &base_vha->dpc_flags);
4587 }
4588 clear_bit(ABORT_ISP_ACTIVE,
4589 &base_vha->dpc_flags);
4590 }
4591
7c3df132
SK		 4592 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4593 "FCoE context reset end.\n");
a9083016
GM		 4594 }
4595 }
4596
e315cd28
AC		 4597 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4598 &base_vha->dpc_flags)) {
1da177e4 4599
7c3df132
SK		 4600 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4601 "ISP abort scheduled.\n");
1da177e4 4602 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4603 &base_vha->dpc_flags))) {
1da177e4 4604
a9083016 4605 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4606 /* failed. retry later */
4607 set_bit(ISP_ABORT_NEEDED,
e315cd28 4608 &base_vha->dpc_flags);
99363ef8 4609 }
e315cd28
AC		 4610 clear_bit(ABORT_ISP_ACTIVE,
4611 &base_vha->dpc_flags);
99363ef8
SJ		 4612 }
4613
7c3df132
SK		 4614 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4615 "ISP abort end.\n");
1da177e4
LT		 4616 }
4617
a394aac8
DJ		 4618 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4619 &base_vha->dpc_flags)) {
e315cd28 4620 qla2x00_update_fcports(base_vha);
c9c5ced9 4621 }
d97994dc 4622
2d70c103
NB		 4623 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4624 int ret;
4625 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4626 if (ret != QLA_SUCCESS)
4627 ql_log(ql_log_warn, base_vha, 0x121,
4628 "Failed to enable receiving of RSCN "
4629 "requests: 0x%x.\n", ret);
4630 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4631 }
4632
579d12b5 4633 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4634 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4635 "Quiescence mode scheduled.\n");
8fcd6b8b
CD		 4636 if (IS_QLA82XX(ha)) {
4637 qla82xx_device_state_handler(base_vha);
4638 clear_bit(ISP_QUIESCE_NEEDED,
4639 &base_vha->dpc_flags);
4640 if (!ha->flags.quiesce_owner) {
4641 qla2x00_perform_loop_resync(base_vha);
4642
4643 qla82xx_idc_lock(ha);
4644 qla82xx_clear_qsnt_ready(base_vha);
4645 qla82xx_idc_unlock(ha);
4646 }
4647 } else {
4648 clear_bit(ISP_QUIESCE_NEEDED,
4649 &base_vha->dpc_flags);
4650 qla2x00_quiesce_io(base_vha);
579d12b5 4651 }
7c3df132
SK		 4652 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4653 "Quiescence mode end.\n");
579d12b5
SK		 4654 }
4655
e315cd28
AC		 4656 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4657 &base_vha->dpc_flags) &&
4658 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4659
7c3df132
SK		 4660 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4661 "Reset marker scheduled.\n");
e315cd28
AC		 4662 qla2x00_rst_aen(base_vha);
4663 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4664 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4665 "Reset marker end.\n");
1da177e4
LT		 4666 }
4667
4668 /* Retry each device up to login retry count */
e315cd28
AC		 4669 if ((test_and_clear_bit(RELOGIN_NEEDED,
4670 &base_vha->dpc_flags)) &&
4671 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4672 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4673
7c3df132
SK		 4674 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4675 "Relogin scheduled.\n");
e315cd28 4676 qla2x00_relogin(base_vha);
7c3df132
SK		 4677 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4678 "Relogin end.\n");
1da177e4
LT		 4679 }
4680
e315cd28
AC		 4681 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
4682 &base_vha->dpc_flags)) {
1da177e4 4683
7c3df132
SK		 4684 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4685 "Loop resync scheduled.\n");
1da177e4
LT		 4686
4687 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4688 &base_vha->dpc_flags))) {
1da177e4 4689
e315cd28 4690 rval = qla2x00_loop_resync(base_vha);
1da177e4 4691
e315cd28
AC		 4692 clear_bit(LOOP_RESYNC_ACTIVE,
4693 &base_vha->dpc_flags);
1da177e4
LT		 4694 }
4695
7c3df132
SK		 4696 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4697 "Loop resync end.\n");
1da177e4
LT		 4698 }
4699
e315cd28
AC		 4700 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4701 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4702 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4703 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4704 }
4705
3c290d0b
CD		 4706 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4707 &base_vha->dpc_flags)) {
4708 /* Prevents simultaneous ramp up and down */
4709 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4710 &base_vha->dpc_flags);
4711 qla2x00_host_ramp_down_queuedepth(base_vha);
4712 }
4713
4714 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4715 &base_vha->dpc_flags))
4716 qla2x00_host_ramp_up_queuedepth(base_vha);
4717
1da177e4 4718 if (!ha->interrupts_on)
fd34f556 4719 ha->isp_ops->enable_intrs(ha);
1da177e4 4720
e315cd28
AC		 4721 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
4722 &base_vha->dpc_flags))
4723 ha->isp_ops->beacon_blink(base_vha);
f6df144c 4724
e315cd28 4725 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 4726
1da177e4 4727 ha->dpc_active = 0;
c142caf0 4728end_loop:
563585ec 4729 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 4730 } /* End of while(1) */
563585ec 4731 __set_current_state(TASK_RUNNING);
1da177e4 4732
7c3df132
SK		 4733 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
4734 "DPC handler exiting.\n");
1da177e4
LT		 4735
4736 /*
4737 * Make sure that nobody tries to wake us up again.
4738 */
1da177e4
LT		 4739 ha->dpc_active = 0;
4740
ac280b67
AV		 4741 /* Cleanup any residual CTX SRBs. */
4742 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4743
39a11240
CH		 4744 return 0;
4745}
4746
4747void
e315cd28 4748qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 4749{
e315cd28 4750 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 4751 struct task_struct *t = ha->dpc_thread;
4752
e315cd28 4753 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 4754 wake_up_process(t);
1da177e4
LT		 4755}
4756
1da177e4
LT		 4757/*
4758* qla2x00_rst_aen
4759* Processes asynchronous reset.
4760*
4761* Input:
4762* ha = adapter block pointer.
4763*/
4764static void
e315cd28 4765qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 4766{
e315cd28
AC		 4767 if (vha->flags.online && !vha->flags.reset_active &&
4768 !atomic_read(&vha->loop_down_timer) &&
4769 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 4770 do {
e315cd28 4771 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4772
4773 /*
4774 * Issue marker command only when we are going to start
4775 * the I/O.
4776 */
e315cd28
AC		 4777 vha->marker_needed = 1;
4778 } while (!atomic_read(&vha->loop_down_timer) &&
4779 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 4780 }
4781}
4782
1da177e4
LT		 4783/**************************************************************************
4784* qla2x00_timer
4785*
4786* Description:
4787* One second timer
4788*
4789* Context: Interrupt
4790***************************************************************************/
2c3dfe3f 4791void
e315cd28 4792qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 4793{
1da177e4 4794 unsigned long cpu_flags = 0;
1da177e4
LT		 4795 int start_dpc = 0;
4796 int index;
4797 srb_t *sp;
85880801 4798 uint16_t w;
e315cd28 4799 struct qla_hw_data *ha = vha->hw;
73208dfd 4800 struct req_que *req;
85880801 4801
a5b36321 4802 if (ha->flags.eeh_busy) {
7c3df132
SK		 4803 ql_dbg(ql_dbg_timer, vha, 0x6000,
4804 "EEH = %d, restarting timer.\n",
4805 ha->flags.eeh_busy);
a5b36321
LC		 4806 qla2x00_restart_timer(vha, WATCH_INTERVAL);
4807 return;
4808 }
4809
85880801
AV		 4810 /* Hardware read to raise pending EEH errors during mailbox waits. */
4811 if (!pci_channel_offline(ha->pdev))
4812 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 4813
cefcaba6
SK		 4814 /* Make sure qla82xx_watchdog is run only for physical port */
4815 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 4816 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
4817 start_dpc++;
4818 qla82xx_watchdog(vha);
4819 }
4820
1da177e4 4821 /* Loop down handler. */
e315cd28 4822 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 4823 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
4824 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 4825 && vha->flags.online) {
1da177e4 4826
e315cd28
AC		 4827 if (atomic_read(&vha->loop_down_timer) ==
4828 vha->loop_down_abort_time) {
1da177e4 4829
7c3df132
SK		 4830 ql_log(ql_log_info, vha, 0x6008,
4831 "Loop down - aborting the queues before time expires.\n");
1da177e4 4832
e315cd28
AC		 4833 if (!IS_QLA2100(ha) && vha->link_down_timeout)
4834 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 4835
f08b7251
AV		 4836 /*
4837 * Schedule an ISP abort to return any FCP2-device
4838 * commands.
4839 */
2c3dfe3f 4840 /* NPIV - scan physical port only */
e315cd28 4841 if (!vha->vp_idx) {
2c3dfe3f
SJ		 4842 spin_lock_irqsave(&ha->hardware_lock,
4843 cpu_flags);
73208dfd 4844 req = ha->req_q_map[0];
2c3dfe3f 4845 for (index = 1;
8d93f550 4846 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 4847 index++) {
4848 fc_port_t *sfcp;
4849
e315cd28 4850 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 4851 if (!sp)
4852 continue;
9ba56b95 4853 if (sp->type != SRB_SCSI_CMD)
cf53b069 4854 continue;
2c3dfe3f 4855 sfcp = sp->fcport;
f08b7251 4856 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 4857 continue;
bdf79621 4858
8f7daead
GM		 4859 if (IS_QLA82XX(ha))
4860 set_bit(FCOE_CTX_RESET_NEEDED,
4861 &vha->dpc_flags);
4862 else
4863 set_bit(ISP_ABORT_NEEDED,
e315cd28 4864 &vha->dpc_flags);
2c3dfe3f
SJ		 4865 break;
4866 }
4867 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 4868 cpu_flags);
1da177e4 4869 }
1da177e4
LT		 4870 start_dpc++;
4871 }
4872
4873 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 4874 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 4875 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 4876 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 4877 "Loop down - aborting ISP.\n");
4878
8f7daead
GM		 4879 if (IS_QLA82XX(ha))
4880 set_bit(FCOE_CTX_RESET_NEEDED,
4881 &vha->dpc_flags);
4882 else
4883 set_bit(ISP_ABORT_NEEDED,
4884 &vha->dpc_flags);
1da177e4
LT		 4885 }
4886 }
7c3df132
SK		 4887 ql_dbg(ql_dbg_timer, vha, 0x600a,
4888 "Loop down - seconds remaining %d.\n",
4889 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 4890 }
4891
cefcaba6
SK		 4892 /* Check if beacon LED needs to be blinked for physical host only */
4893 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 4894 /* There is no beacon_blink function for ISP82xx */
4895 if (!IS_QLA82XX(ha)) {
4896 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
4897 start_dpc++;
4898 }
f6df144c
AV		 4899 }
4900
550bf57d 4901 /* Process any deferred work. */
e315cd28 4902 if (!list_empty(&vha->work_list))
550bf57d
AV		 4903 start_dpc++;
4904
1da177e4 4905 /* Schedule the DPC routine if needed */
e315cd28
AC		 4906 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
4907 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
4908 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 4909 start_dpc ||
e315cd28
AC		 4910 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
4911 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 4912 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
4913 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 4914 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
3c290d0b
CD		 4915 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
4916 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
4917 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
7c3df132
SK		 4918 ql_dbg(ql_dbg_timer, vha, 0x600b,
4919 "isp_abort_needed=%d loop_resync_needed=%d "
4920 "fcport_update_needed=%d start_dpc=%d "
4921 "reset_marker_needed=%d",
4922 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
4923 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
4924 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
4925 start_dpc,
4926 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
4927 ql_dbg(ql_dbg_timer, vha, 0x600c,
4928 "beacon_blink_needed=%d isp_unrecoverable=%d "
4929 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3c290d0b
CD		 4930 "relogin_needed=%d, host_ramp_down_needed=%d "
4931 "host_ramp_up_needed=%d.\n",
7c3df132
SK		 4932 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
4933 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
4934 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
4935 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3c290d0b
CD		 4936 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
4937 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
4938 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
e315cd28 4939 qla2xxx_wake_dpc(vha);
7c3df132 4940 }
1da177e4 4941
e315cd28 4942 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 4943}
4944
5433383e
AV		 4945/* Firmware interface routines. */
4946
6246b8a1 4947#define FW_BLOBS 10
5433383e
AV		 4948#define FW_ISP21XX 0
4949#define FW_ISP22XX 1
4950#define FW_ISP2300 2
4951#define FW_ISP2322 3
48c02fde 4952#define FW_ISP24XX 4
c3a2f0df 4953#define FW_ISP25XX 5
3a03eb79 4954#define FW_ISP81XX 6
a9083016 4955#define FW_ISP82XX 7
6246b8a1
GM		 4956#define FW_ISP2031 8
4957#define FW_ISP8031 9
5433383e 4958
bb8ee499
AV		 4959#define FW_FILE_ISP21XX "ql2100_fw.bin"
4960#define FW_FILE_ISP22XX "ql2200_fw.bin"
4961#define FW_FILE_ISP2300 "ql2300_fw.bin"
4962#define FW_FILE_ISP2322 "ql2322_fw.bin"
4963#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 4964#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 4965#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 4966#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 4967#define FW_FILE_ISP2031 "ql2600_fw.bin"
4968#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 4969
e1e82b6f 4970static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 4971
4972static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 4973 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
4974 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
4975 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
4976 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
4977 { .name = FW_FILE_ISP24XX, },
c3a2f0df 4978 { .name = FW_FILE_ISP25XX, },
3a03eb79 4979 { .name = FW_FILE_ISP81XX, },
a9083016 4980 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 4981 { .name = FW_FILE_ISP2031, },
4982 { .name = FW_FILE_ISP8031, },
5433383e
AV		 4983};
4984
4985struct fw_blob *
e315cd28 4986qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4987{
e315cd28 4988 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4989 struct fw_blob *blob;
4990
5433383e
AV		 4991 if (IS_QLA2100(ha)) {
4992 blob = &qla_fw_blobs[FW_ISP21XX];
4993 } else if (IS_QLA2200(ha)) {
4994 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4995 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4996 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4997 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4998 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4999 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5000 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5001 } else if (IS_QLA25XX(ha)) {
5002 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5003 } else if (IS_QLA81XX(ha)) {
5004 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5005 } else if (IS_QLA82XX(ha)) {
5006 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5007 } else if (IS_QLA2031(ha)) {
5008 blob = &qla_fw_blobs[FW_ISP2031];
5009 } else if (IS_QLA8031(ha)) {
5010 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 5011 } else {
5012 return NULL;
5433383e
AV		 5013 }
5014
e1e82b6f 5015 mutex_lock(&qla_fw_lock);
5433383e
AV		 5016 if (blob->fw)
5017 goto out;
5018
5019 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5020 ql_log(ql_log_warn, vha, 0x0063,
5021 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5022 blob->fw = NULL;
5023 blob = NULL;
5024 goto out;
5025 }
5026
5027out:
e1e82b6f 5028 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5029 return blob;
5030}
5031
5032static void
5033qla2x00_release_firmware(void)
5034{
5035 int idx;
5036
e1e82b6f 5037 mutex_lock(&qla_fw_lock);
5433383e 5038 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5039 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5040 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5041}
5042
14e660e6
SJ		 5043static pci_ers_result_t
5044qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5045{
85880801
AV		 5046 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5047 struct qla_hw_data *ha = vha->hw;
5048
7c3df132
SK		 5049 ql_dbg(ql_dbg_aer, vha, 0x9000,
5050 "PCI error detected, state %x.\n", state);
b9b12f73 5051
14e660e6
SJ		 5052 switch (state) {
5053 case pci_channel_io_normal:
85880801 5054 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5055 return PCI_ERS_RESULT_CAN_RECOVER;
5056 case pci_channel_io_frozen:
85880801 5057 ha->flags.eeh_busy = 1;
a5b36321
LC		 5058 /* For ISP82XX complete any pending mailbox cmd */
5059 if (IS_QLA82XX(ha)) {
7190575f 5060 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5061 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5062 qla82xx_clear_pending_mbx(vha);
a5b36321 5063 }
90a86fc0 5064 qla2x00_free_irqs(vha);
14e660e6 5065 pci_disable_device(pdev);
bddd2d65
LC		 5066 /* Return back all IOs */
5067 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5068 return PCI_ERS_RESULT_NEED_RESET;
5069 case pci_channel_io_perm_failure:
85880801
AV		 5070 ha->flags.pci_channel_io_perm_failure = 1;
5071 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5072 return PCI_ERS_RESULT_DISCONNECT;
5073 }
5074 return PCI_ERS_RESULT_NEED_RESET;
5075}
5076
5077static pci_ers_result_t
5078qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5079{
5080 int risc_paused = 0;
5081 uint32_t stat;
5082 unsigned long flags;
e315cd28
AC		 5083 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5084 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5085 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5086 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5087
bcc5b6d3
SK		 5088 if (IS_QLA82XX(ha))
5089 return PCI_ERS_RESULT_RECOVERED;
5090
14e660e6
SJ		 5091 spin_lock_irqsave(&ha->hardware_lock, flags);
5092 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5093 stat = RD_REG_DWORD(&reg->hccr);
5094 if (stat & HCCR_RISC_PAUSE)
5095 risc_paused = 1;
5096 } else if (IS_QLA23XX(ha)) {
5097 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5098 if (stat & HSR_RISC_PAUSED)
5099 risc_paused = 1;
5100 } else if (IS_FWI2_CAPABLE(ha)) {
5101 stat = RD_REG_DWORD(&reg24->host_status);
5102 if (stat & HSRX_RISC_PAUSED)
5103 risc_paused = 1;
5104 }
5105 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5106
5107 if (risc_paused) {
7c3df132
SK		 5108 ql_log(ql_log_info, base_vha, 0x9003,
5109 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5110 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5111
5112 return PCI_ERS_RESULT_NEED_RESET;
5113 } else
5114 return PCI_ERS_RESULT_RECOVERED;
5115}
5116
fa492630
SK		 5117static uint32_t
5118qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5119{
5120 uint32_t rval = QLA_FUNCTION_FAILED;
5121 uint32_t drv_active = 0;
5122 struct qla_hw_data *ha = base_vha->hw;
5123 int fn;
5124 struct pci_dev *other_pdev = NULL;
5125
7c3df132
SK		 5126 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5127 "Entered %s.\n", __func__);
a5b36321
LC		 5128
5129 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5130
5131 if (base_vha->flags.online) {
5132 /* Abort all outstanding commands,
5133 * so as to be requeued later */
5134 qla2x00_abort_isp_cleanup(base_vha);
5135 }
5136
5137
5138 fn = PCI_FUNC(ha->pdev->devfn);
5139 while (fn > 0) {
5140 fn--;
7c3df132
SK		 5141 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5142 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5143 other_pdev =
5144 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5145 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5146 fn));
5147
5148 if (!other_pdev)
5149 continue;
5150 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5151 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5152 "Found PCI func available and enable at 0x%x.\n",
5153 fn);
a5b36321
LC		 5154 pci_dev_put(other_pdev);
5155 break;
5156 }
5157 pci_dev_put(other_pdev);
5158 }
5159
5160 if (!fn) {
5161 /* Reset owner */
7c3df132
SK		 5162 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5163 "This devfn is reset owner = 0x%x.\n",
5164 ha->pdev->devfn);
a5b36321
LC		 5165 qla82xx_idc_lock(ha);
5166
5167 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5168 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5169
5170 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5171 QLA82XX_IDC_VERSION);
5172
5173 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5174 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5175 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5176
5177 qla82xx_idc_unlock(ha);
5178 /* Reset if device is not already reset
5179 * drv_active would be 0 if a reset has already been done
5180 */
5181 if (drv_active)
5182 rval = qla82xx_start_firmware(base_vha);
5183 else
5184 rval = QLA_SUCCESS;
5185 qla82xx_idc_lock(ha);
5186
5187 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5188 ql_log(ql_log_info, base_vha, 0x900b,
5189 "HW State: FAILED.\n");
a5b36321
LC		 5190 qla82xx_clear_drv_active(ha);
5191 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5192 QLA8XXX_DEV_FAILED);
a5b36321 5193 } else {
7c3df132
SK		 5194 ql_log(ql_log_info, base_vha, 0x900c,
5195 "HW State: READY.\n");
a5b36321 5196 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5197 QLA8XXX_DEV_READY);
a5b36321 5198 qla82xx_idc_unlock(ha);
7190575f 5199 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5200 rval = qla82xx_restart_isp(base_vha);
5201 qla82xx_idc_lock(ha);
5202 /* Clear driver state register */
5203 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5204 qla82xx_set_drv_active(base_vha);
5205 }
5206 qla82xx_idc_unlock(ha);
5207 } else {
7c3df132
SK		 5208 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5209 "This devfn is not reset owner = 0x%x.\n",
5210 ha->pdev->devfn);
a5b36321 5211 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5212 QLA8XXX_DEV_READY)) {
7190575f 5213 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5214 rval = qla82xx_restart_isp(base_vha);
5215 qla82xx_idc_lock(ha);
5216 qla82xx_set_drv_active(base_vha);
5217 qla82xx_idc_unlock(ha);
5218 }
5219 }
5220 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5221
5222 return rval;
5223}
5224
14e660e6
SJ		 5225static pci_ers_result_t
5226qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5227{
5228 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5229 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5230 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5231 struct rsp_que *rsp;
5232 int rc, retries = 10;
09483916 5233
7c3df132
SK		 5234 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5235 "Slot Reset.\n");
85880801 5236
90a86fc0
JC		 5237 /* Workaround: qla2xxx driver which access hardware earlier
5238 * needs error state to be pci_channel_io_online.
5239 * Otherwise mailbox command timesout.
5240 */
5241 pdev->error_state = pci_channel_io_normal;
5242
5243 pci_restore_state(pdev);
5244
8c1496bd
RL		 5245 /* pci_restore_state() clears the saved_state flag of the device
5246 * save restored state which resets saved_state flag
5247 */
5248 pci_save_state(pdev);
5249
09483916
BH		 5250 if (ha->mem_only)
5251 rc = pci_enable_device_mem(pdev);
5252 else
5253 rc = pci_enable_device(pdev);
14e660e6 5254
09483916 5255 if (rc) {
7c3df132 5256 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5257 "Can't re-enable PCI device after reset.\n");
a5b36321 5258 goto exit_slot_reset;
14e660e6 5259 }
14e660e6 5260
90a86fc0
JC		 5261 rsp = ha->rsp_q_map[0];
5262 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5263 goto exit_slot_reset;
90a86fc0 5264
e315cd28 5265 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5266 goto exit_slot_reset;
5267
5268 if (IS_QLA82XX(ha)) {
5269 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5270 ret = PCI_ERS_RESULT_RECOVERED;
5271 goto exit_slot_reset;
5272 } else
5273 goto exit_slot_reset;
5274 }
14e660e6 5275
90a86fc0
JC		 5276 while (ha->flags.mbox_busy && retries--)
5277 msleep(1000);
85880801 5278
e315cd28 5279 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5280 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5281 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5282 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5283
90a86fc0 5284
a5b36321 5285exit_slot_reset:
7c3df132
SK		 5286 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5287 "slot_reset return %x.\n", ret);
85880801 5288
14e660e6
SJ		 5289 return ret;
5290}
5291
5292static void
5293qla2xxx_pci_resume(struct pci_dev *pdev)
5294{
e315cd28
AC		 5295 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5296 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5297 int ret;
5298
7c3df132
SK		 5299 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5300 "pci_resume.\n");
85880801 5301
e315cd28 5302 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5303 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5304 ql_log(ql_log_fatal, base_vha, 0x9002,
5305 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5306 }
85880801 5307
3e46f031
LC		 5308 pci_cleanup_aer_uncorrect_error_status(pdev);
5309
85880801 5310 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5311}
5312
a55b2d21 5313static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5314 .error_detected = qla2xxx_pci_error_detected,
5315 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5316 .slot_reset = qla2xxx_pci_slot_reset,
5317 .resume = qla2xxx_pci_resume,
5318};
5319
5433383e 5320static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5332 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5333 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5334 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5335 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5336 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5337 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5433383e
AV		 5338 { 0 },
5339};
5340MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5341
fca29703 5342static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5343 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5344 .driver = {
5345 .owner = THIS_MODULE,
5346 },
fca29703 5347 .id_table = qla2xxx_pci_tbl,
7ee61397 5348 .probe = qla2x00_probe_one,
4c993f76 5349 .remove = qla2x00_remove_one,
e30d1756 5350 .shutdown = qla2x00_shutdown,
14e660e6 5351 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5352};
5353
6a03b4cd
HZ		 5354static struct file_operations apidev_fops = {
5355 .owner = THIS_MODULE,
6038f373 5356 .llseek = noop_llseek,
6a03b4cd
HZ		 5357};
5358
1da177e4
LT		 5359/**
5360 * qla2x00_module_init - Module initialization.
5361 **/
5362static int __init
5363qla2x00_module_init(void)
5364{
fca29703
AV		 5365 int ret = 0;
5366
1da177e4 5367 /* Allocate cache for SRBs. */
354d6b21 5368 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5369 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5370 if (srb_cachep == NULL) {
7c3df132
SK		 5371 ql_log(ql_log_fatal, NULL, 0x0001,
5372 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5373 return -ENOMEM;
5374 }
5375
2d70c103
NB		 5376 /* Initialize target kmem_cache and mem_pools */
5377 ret = qlt_init();
5378 if (ret < 0) {
5379 kmem_cache_destroy(srb_cachep);
5380 return ret;
5381 } else if (ret > 0) {
5382 /*
5383 * If initiator mode is explictly disabled by qlt_init(),
5384 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5385 * performing scsi_scan_target() during LOOP UP event.
5386 */
5387 qla2xxx_transport_functions.disable_target_scan = 1;
5388 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5389 }
5390
1da177e4
LT		 5391 /* Derive version string. */
5392 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5393 if (ql2xextended_error_logging)
0181944f
AV		 5394 strcat(qla2x00_version_str, "-debug");
5395
1c97a12a
AV		 5396 qla2xxx_transport_template =
5397 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5398 if (!qla2xxx_transport_template) {
5399 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5400 ql_log(ql_log_fatal, NULL, 0x0002,
5401 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5402 qlt_exit();
1da177e4 5403 return -ENODEV;
2c3dfe3f 5404 }
6a03b4cd
HZ		 5405
5406 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5407 if (apidev_major < 0) {
7c3df132
SK		 5408 ql_log(ql_log_fatal, NULL, 0x0003,
5409 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5410 }
5411
2c3dfe3f
SJ		 5412 qla2xxx_transport_vport_template =
5413 fc_attach_transport(&qla2xxx_transport_vport_functions);
5414 if (!qla2xxx_transport_vport_template) {
5415 kmem_cache_destroy(srb_cachep);
2d70c103 5416 qlt_exit();
2c3dfe3f 5417 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5418 ql_log(ql_log_fatal, NULL, 0x0004,
5419 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5420 return -ENODEV;
2c3dfe3f 5421 }
7c3df132
SK		 5422 ql_log(ql_log_info, NULL, 0x0005,
5423 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5424 qla2x00_version_str);
7ee61397 5425 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5426 if (ret) {
5427 kmem_cache_destroy(srb_cachep);
2d70c103 5428 qlt_exit();
fca29703 5429 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5430 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5431 ql_log(ql_log_fatal, NULL, 0x0006,
5432 "pci_register_driver failed...ret=%d Failing load!.\n",
5433 ret);
fca29703
AV		 5434 }
5435 return ret;
1da177e4
LT		 5436}
5437
5438/**
5439 * qla2x00_module_exit - Module cleanup.
5440 **/
5441static void __exit
5442qla2x00_module_exit(void)
5443{
6a03b4cd 5444 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5445 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5446 qla2x00_release_firmware();
354d6b21 5447 kmem_cache_destroy(srb_cachep);
2d70c103 5448 qlt_exit();
a9083016
GM		 5449 if (ctx_cachep)
5450 kmem_cache_destroy(ctx_cachep);
1da177e4 5451 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5452 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5453}
5454
5455module_init(qla2x00_module_init);
5456module_exit(qla2x00_module_exit);
5457
5458MODULE_AUTHOR("QLogic Corporation");
5459MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5460MODULE_LICENSE("GPL");
5461MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5462MODULE_FIRMWARE(FW_FILE_ISP21XX);
5463MODULE_FIRMWARE(FW_FILE_ISP22XX);
5464MODULE_FIRMWARE(FW_FILE_ISP2300);
5465MODULE_FIRMWARE(FW_FILE_ISP2322);
5466MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5467MODULE_FIRMWARE(FW_FILE_ISP25XX);
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