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Commit | Line | Data |
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1da177e4 | 1 | /* |
fa90c54f | 2 | * QLogic Fibre Channel HBA Driver |
bd21eaf9 | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
1da177e4 | 4 | * |
fa90c54f | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
1da177e4 LT |
6 | */ |
7 | #include "qla_def.h" | |
8 | ||
9 | #include <linux/moduleparam.h> | |
10 | #include <linux/vmalloc.h> | |
1da177e4 | 11 | #include <linux/delay.h> |
39a11240 | 12 | #include <linux/kthread.h> |
e1e82b6f | 13 | #include <linux/mutex.h> |
3420d36c | 14 | #include <linux/kobject.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
1da177e4 LT |
16 | #include <scsi/scsi_tcq.h> |
17 | #include <scsi/scsicam.h> | |
18 | #include <scsi/scsi_transport.h> | |
19 | #include <scsi/scsi_transport_fc.h> | |
20 | ||
2d70c103 NB |
21 | #include "qla_target.h" |
22 | ||
1da177e4 LT |
23 | /* |
24 | * Driver version | |
25 | */ | |
26 | char qla2x00_version_str[40]; | |
27 | ||
6a03b4cd HZ |
28 | static int apidev_major; |
29 | ||
1da177e4 LT |
30 | /* |
31 | * SRB allocation cache | |
32 | */ | |
e18b890b | 33 | static struct kmem_cache *srb_cachep; |
1da177e4 | 34 | |
a9083016 GM |
35 | /* |
36 | * CT6 CTX allocation cache | |
37 | */ | |
38 | static struct kmem_cache *ctx_cachep; | |
3ce8866c SK |
39 | /* |
40 | * error level for logging | |
41 | */ | |
42 | int ql_errlev = ql_log_all; | |
a9083016 | 43 | |
fa492630 | 44 | static int ql2xenableclass2; |
2d70c103 NB |
45 | module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); |
46 | MODULE_PARM_DESC(ql2xenableclass2, | |
47 | "Specify if Class 2 operations are supported from the very " | |
48 | "beginning. Default is 0 - class 2 not supported."); | |
49 | ||
8ae6d9c7 | 50 | |
1da177e4 | 51 | int ql2xlogintimeout = 20; |
f2019cb1 | 52 | module_param(ql2xlogintimeout, int, S_IRUGO); |
1da177e4 LT |
53 | MODULE_PARM_DESC(ql2xlogintimeout, |
54 | "Login timeout value in seconds."); | |
55 | ||
a7b61842 | 56 | int qlport_down_retry; |
f2019cb1 | 57 | module_param(qlport_down_retry, int, S_IRUGO); |
1da177e4 | 58 | MODULE_PARM_DESC(qlport_down_retry, |
900d9f98 | 59 | "Maximum number of command retries to a port that returns " |
1da177e4 LT |
60 | "a PORT-DOWN status."); |
61 | ||
1da177e4 LT |
62 | int ql2xplogiabsentdevice; |
63 | module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); | |
64 | MODULE_PARM_DESC(ql2xplogiabsentdevice, | |
65 | "Option to enable PLOGI to devices that are not present after " | |
900d9f98 | 66 | "a Fabric scan. This is needed for several broken switches. " |
1da177e4 LT |
67 | "Default is 0 - no PLOGI. 1 - perfom PLOGI."); |
68 | ||
1da177e4 | 69 | int ql2xloginretrycount = 0; |
f2019cb1 | 70 | module_param(ql2xloginretrycount, int, S_IRUGO); |
1da177e4 LT |
71 | MODULE_PARM_DESC(ql2xloginretrycount, |
72 | "Specify an alternate value for the NVRAM login retry count."); | |
73 | ||
a7a167bf | 74 | int ql2xallocfwdump = 1; |
f2019cb1 | 75 | module_param(ql2xallocfwdump, int, S_IRUGO); |
a7a167bf AV |
76 | MODULE_PARM_DESC(ql2xallocfwdump, |
77 | "Option to enable allocation of memory for a firmware dump " | |
78 | "during HBA initialization. Memory allocation requirements " | |
79 | "vary by ISP type. Default is 1 - allocate memory."); | |
80 | ||
11010fec | 81 | int ql2xextended_error_logging; |
27d94035 | 82 | module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); |
11010fec | 83 | MODULE_PARM_DESC(ql2xextended_error_logging, |
3ce8866c SK |
84 | "Option to enable extended error logging,\n" |
85 | "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" | |
86 | "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" | |
87 | "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" | |
88 | "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" | |
89 | "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" | |
90 | "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" | |
91 | "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" | |
92 | "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" | |
29f9f90c CD |
93 | "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" |
94 | "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" | |
3ce8866c | 95 | "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" |
cfb0919c CD |
96 | "\t\t0x1e400000 - Preferred value for capturing essential " |
97 | "debug information (equivalent to old " | |
98 | "ql2xextended_error_logging=1).\n" | |
3ce8866c | 99 | "\t\tDo LOGICAL OR of the value to enable more than one level"); |
0181944f | 100 | |
a9083016 | 101 | int ql2xshiftctondsd = 6; |
f2019cb1 | 102 | module_param(ql2xshiftctondsd, int, S_IRUGO); |
a9083016 GM |
103 | MODULE_PARM_DESC(ql2xshiftctondsd, |
104 | "Set to control shifting of command type processing " | |
105 | "based on total number of SG elements."); | |
106 | ||
7e47e5ca | 107 | int ql2xfdmienable=1; |
de187df8 | 108 | module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); |
cca5335c | 109 | MODULE_PARM_DESC(ql2xfdmienable, |
7794a5af FW |
110 | "Enables FDMI registrations. " |
111 | "0 - no FDMI. Default is 1 - perform FDMI."); | |
cca5335c | 112 | |
50280c01 CD |
113 | #define MAX_Q_DEPTH 32 |
114 | static int ql2xmaxqdepth = MAX_Q_DEPTH; | |
df7baa50 AV |
115 | module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); |
116 | MODULE_PARM_DESC(ql2xmaxqdepth, | |
e92e4a8f CD |
117 | "Maximum queue depth to set for each LUN. " |
118 | "Default is 32."); | |
df7baa50 | 119 | |
9e522cd8 AE |
120 | int ql2xenabledif = 2; |
121 | module_param(ql2xenabledif, int, S_IRUGO); | |
bad75002 | 122 | MODULE_PARM_DESC(ql2xenabledif, |
b97f5d0b SM |
123 | " Enable T10-CRC-DIF:\n" |
124 | " Default is 2.\n" | |
125 | " 0 -- No DIF Support\n" | |
126 | " 1 -- Enable DIF for all types\n" | |
127 | " 2 -- Enable DIF for all types, except Type 0.\n"); | |
bad75002 | 128 | |
8cb2049c | 129 | int ql2xenablehba_err_chk = 2; |
bad75002 AE |
130 | module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); |
131 | MODULE_PARM_DESC(ql2xenablehba_err_chk, | |
8cb2049c | 132 | " Enable T10-CRC-DIF Error isolation by HBA:\n" |
b97f5d0b | 133 | " Default is 2.\n" |
8cb2049c AE |
134 | " 0 -- Error isolation disabled\n" |
135 | " 1 -- Error isolation enabled only for DIX Type 0\n" | |
136 | " 2 -- Error isolation enabled for all Types\n"); | |
bad75002 | 137 | |
e5896bd5 | 138 | int ql2xiidmaenable=1; |
f2019cb1 | 139 | module_param(ql2xiidmaenable, int, S_IRUGO); |
e5896bd5 AV |
140 | MODULE_PARM_DESC(ql2xiidmaenable, |
141 | "Enables iIDMA settings " | |
142 | "Default is 1 - perform iIDMA. 0 - no iIDMA."); | |
143 | ||
73208dfd | 144 | int ql2xmaxqueues = 1; |
f2019cb1 | 145 | module_param(ql2xmaxqueues, int, S_IRUGO); |
73208dfd AC |
146 | MODULE_PARM_DESC(ql2xmaxqueues, |
147 | "Enables MQ settings " | |
ae68230c JP |
148 | "Default is 1 for single queue. Set it to number " |
149 | "of queues in MQ mode."); | |
68ca949c AC |
150 | |
151 | int ql2xmultique_tag; | |
f2019cb1 | 152 | module_param(ql2xmultique_tag, int, S_IRUGO); |
68ca949c AC |
153 | MODULE_PARM_DESC(ql2xmultique_tag, |
154 | "Enables CPU affinity settings for the driver " | |
155 | "Default is 0 for no affinity of request and response IO. " | |
156 | "Set it to 1 to turn on the cpu affinity."); | |
e337d907 AV |
157 | |
158 | int ql2xfwloadbin; | |
86e45bf6 | 159 | module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); |
e337d907 | 160 | MODULE_PARM_DESC(ql2xfwloadbin, |
7c3df132 SK |
161 | "Option to specify location from which to load ISP firmware:.\n" |
162 | " 2 -- load firmware via the request_firmware() (hotplug).\n" | |
e337d907 AV |
163 | " interface.\n" |
164 | " 1 -- load firmware from flash.\n" | |
165 | " 0 -- use default semantics.\n"); | |
166 | ||
ae97c91e | 167 | int ql2xetsenable; |
f2019cb1 | 168 | module_param(ql2xetsenable, int, S_IRUGO); |
ae97c91e AV |
169 | MODULE_PARM_DESC(ql2xetsenable, |
170 | "Enables firmware ETS burst." | |
171 | "Default is 0 - skip ETS enablement."); | |
172 | ||
6907869d | 173 | int ql2xdbwr = 1; |
86e45bf6 | 174 | module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); |
a9083016 | 175 | MODULE_PARM_DESC(ql2xdbwr, |
08de2844 GM |
176 | "Option to specify scheme for request queue posting.\n" |
177 | " 0 -- Regular doorbell.\n" | |
178 | " 1 -- CAMRAM doorbell (faster).\n"); | |
a9083016 | 179 | |
f4c496c1 | 180 | int ql2xtargetreset = 1; |
f2019cb1 | 181 | module_param(ql2xtargetreset, int, S_IRUGO); |
f4c496c1 GM |
182 | MODULE_PARM_DESC(ql2xtargetreset, |
183 | "Enable target reset." | |
184 | "Default is 1 - use hw defaults."); | |
185 | ||
4da26e16 | 186 | int ql2xgffidenable; |
f2019cb1 | 187 | module_param(ql2xgffidenable, int, S_IRUGO); |
4da26e16 CD |
188 | MODULE_PARM_DESC(ql2xgffidenable, |
189 | "Enables GFF_ID checks of port type. " | |
190 | "Default is 0 - Do not use GFF_ID information."); | |
a9083016 | 191 | |
3822263e | 192 | int ql2xasynctmfenable; |
f2019cb1 | 193 | module_param(ql2xasynctmfenable, int, S_IRUGO); |
3822263e MI |
194 | MODULE_PARM_DESC(ql2xasynctmfenable, |
195 | "Enables issue of TM IOCBs asynchronously via IOCB mechanism" | |
196 | "Default is 0 - Issue TM IOCBs via mailbox mechanism."); | |
ed0de87c GM |
197 | |
198 | int ql2xdontresethba; | |
86e45bf6 | 199 | module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); |
ed0de87c | 200 | MODULE_PARM_DESC(ql2xdontresethba, |
08de2844 GM |
201 | "Option to specify reset behaviour.\n" |
202 | " 0 (Default) -- Reset on failure.\n" | |
203 | " 1 -- Do not reset on failure.\n"); | |
ed0de87c | 204 | |
1abf635d HR |
205 | uint64_t ql2xmaxlun = MAX_LUNS; |
206 | module_param(ql2xmaxlun, ullong, S_IRUGO); | |
82515920 AV |
207 | MODULE_PARM_DESC(ql2xmaxlun, |
208 | "Defines the maximum LU number to register with the SCSI " | |
209 | "midlayer. Default is 65535."); | |
210 | ||
08de2844 GM |
211 | int ql2xmdcapmask = 0x1F; |
212 | module_param(ql2xmdcapmask, int, S_IRUGO); | |
213 | MODULE_PARM_DESC(ql2xmdcapmask, | |
214 | "Set the Minidump driver capture mask level. " | |
6e96fa7b | 215 | "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); |
08de2844 | 216 | |
3aadff35 | 217 | int ql2xmdenable = 1; |
08de2844 GM |
218 | module_param(ql2xmdenable, int, S_IRUGO); |
219 | MODULE_PARM_DESC(ql2xmdenable, | |
220 | "Enable/disable MiniDump. " | |
3aadff35 GM |
221 | "0 - MiniDump disabled. " |
222 | "1 (Default) - MiniDump enabled."); | |
08de2844 | 223 | |
1da177e4 | 224 | /* |
fa2a1ce5 | 225 | * SCSI host template entry points |
1da177e4 LT |
226 | */ |
227 | static int qla2xxx_slave_configure(struct scsi_device * device); | |
f4f051eb | 228 | static int qla2xxx_slave_alloc(struct scsi_device *); |
1e99e33a AV |
229 | static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time); |
230 | static void qla2xxx_scan_start(struct Scsi_Host *); | |
f4f051eb | 231 | static void qla2xxx_slave_destroy(struct scsi_device *); |
f281233d | 232 | static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
1da177e4 LT |
233 | static int qla2xxx_eh_abort(struct scsi_cmnd *); |
234 | static int qla2xxx_eh_device_reset(struct scsi_cmnd *); | |
523ec773 | 235 | static int qla2xxx_eh_target_reset(struct scsi_cmnd *); |
1da177e4 LT |
236 | static int qla2xxx_eh_bus_reset(struct scsi_cmnd *); |
237 | static int qla2xxx_eh_host_reset(struct scsi_cmnd *); | |
1da177e4 | 238 | |
1a2fbf18 | 239 | static void qla2x00_clear_drv_active(struct qla_hw_data *); |
3491255e | 240 | static void qla2x00_free_device(scsi_qla_host_t *); |
2d5a4c34 | 241 | static void qla83xx_disable_laser(scsi_qla_host_t *vha); |
ce7e4af7 | 242 | |
a5326f86 | 243 | struct scsi_host_template qla2xxx_driver_template = { |
1da177e4 | 244 | .module = THIS_MODULE, |
cb63067a | 245 | .name = QLA2XXX_DRIVER_NAME, |
a5326f86 | 246 | .queuecommand = qla2xxx_queuecommand, |
fca29703 AV |
247 | |
248 | .eh_abort_handler = qla2xxx_eh_abort, | |
249 | .eh_device_reset_handler = qla2xxx_eh_device_reset, | |
523ec773 | 250 | .eh_target_reset_handler = qla2xxx_eh_target_reset, |
fca29703 AV |
251 | .eh_bus_reset_handler = qla2xxx_eh_bus_reset, |
252 | .eh_host_reset_handler = qla2xxx_eh_host_reset, | |
253 | ||
254 | .slave_configure = qla2xxx_slave_configure, | |
255 | ||
256 | .slave_alloc = qla2xxx_slave_alloc, | |
257 | .slave_destroy = qla2xxx_slave_destroy, | |
ed677086 AV |
258 | .scan_finished = qla2xxx_scan_finished, |
259 | .scan_start = qla2xxx_scan_start, | |
db5ed4df | 260 | .change_queue_depth = scsi_change_queue_depth, |
fca29703 AV |
261 | .this_id = -1, |
262 | .cmd_per_lun = 3, | |
263 | .use_clustering = ENABLE_CLUSTERING, | |
264 | .sg_tablesize = SG_ALL, | |
265 | ||
266 | .max_sectors = 0xFFFF, | |
afb046e2 | 267 | .shost_attrs = qla2x00_host_attrs, |
2d70c103 NB |
268 | |
269 | .supported_mode = MODE_INITIATOR, | |
2ecb204d | 270 | .use_blk_tags = 1, |
c40ecc12 | 271 | .track_queue_depth = 1, |
fca29703 AV |
272 | }; |
273 | ||
1da177e4 | 274 | static struct scsi_transport_template *qla2xxx_transport_template = NULL; |
2c3dfe3f | 275 | struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; |
1da177e4 | 276 | |
1da177e4 LT |
277 | /* TODO Convert to inlines |
278 | * | |
279 | * Timer routines | |
280 | */ | |
1da177e4 | 281 | |
2c3dfe3f | 282 | __inline__ void |
e315cd28 | 283 | qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) |
1da177e4 | 284 | { |
e315cd28 AC |
285 | init_timer(&vha->timer); |
286 | vha->timer.expires = jiffies + interval * HZ; | |
287 | vha->timer.data = (unsigned long)vha; | |
288 | vha->timer.function = (void (*)(unsigned long))func; | |
289 | add_timer(&vha->timer); | |
290 | vha->timer_active = 1; | |
1da177e4 LT |
291 | } |
292 | ||
293 | static inline void | |
e315cd28 | 294 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) |
1da177e4 | 295 | { |
a9083016 | 296 | /* Currently used for 82XX only. */ |
7c3df132 SK |
297 | if (vha->device_flags & DFLG_DEV_FAILED) { |
298 | ql_dbg(ql_dbg_timer, vha, 0x600d, | |
299 | "Device in a failed state, returning.\n"); | |
a9083016 | 300 | return; |
7c3df132 | 301 | } |
a9083016 | 302 | |
e315cd28 | 303 | mod_timer(&vha->timer, jiffies + interval * HZ); |
1da177e4 LT |
304 | } |
305 | ||
a824ebb3 | 306 | static __inline__ void |
e315cd28 | 307 | qla2x00_stop_timer(scsi_qla_host_t *vha) |
1da177e4 | 308 | { |
e315cd28 AC |
309 | del_timer_sync(&vha->timer); |
310 | vha->timer_active = 0; | |
1da177e4 LT |
311 | } |
312 | ||
1da177e4 LT |
313 | static int qla2x00_do_dpc(void *data); |
314 | ||
315 | static void qla2x00_rst_aen(scsi_qla_host_t *); | |
316 | ||
73208dfd AC |
317 | static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, |
318 | struct req_que **, struct rsp_que **); | |
e30d1756 | 319 | static void qla2x00_free_fw_dump(struct qla_hw_data *); |
e315cd28 | 320 | static void qla2x00_mem_free(struct qla_hw_data *); |
1da177e4 | 321 | |
1da177e4 | 322 | /* -------------------------------------------------------------------------- */ |
9a347ff4 CD |
323 | static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, |
324 | struct rsp_que *rsp) | |
73208dfd | 325 | { |
7c3df132 | 326 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); |
2afa19a9 | 327 | ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues, |
73208dfd AC |
328 | GFP_KERNEL); |
329 | if (!ha->req_q_map) { | |
7c3df132 SK |
330 | ql_log(ql_log_fatal, vha, 0x003b, |
331 | "Unable to allocate memory for request queue ptrs.\n"); | |
73208dfd AC |
332 | goto fail_req_map; |
333 | } | |
334 | ||
2afa19a9 | 335 | ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues, |
73208dfd AC |
336 | GFP_KERNEL); |
337 | if (!ha->rsp_q_map) { | |
7c3df132 SK |
338 | ql_log(ql_log_fatal, vha, 0x003c, |
339 | "Unable to allocate memory for response queue ptrs.\n"); | |
73208dfd AC |
340 | goto fail_rsp_map; |
341 | } | |
9a347ff4 CD |
342 | /* |
343 | * Make sure we record at least the request and response queue zero in | |
344 | * case we need to free them if part of the probe fails. | |
345 | */ | |
346 | ha->rsp_q_map[0] = rsp; | |
347 | ha->req_q_map[0] = req; | |
73208dfd AC |
348 | set_bit(0, ha->rsp_qid_map); |
349 | set_bit(0, ha->req_qid_map); | |
350 | return 1; | |
351 | ||
352 | fail_rsp_map: | |
353 | kfree(ha->req_q_map); | |
354 | ha->req_q_map = NULL; | |
355 | fail_req_map: | |
356 | return -ENOMEM; | |
357 | } | |
358 | ||
2afa19a9 | 359 | static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) |
73208dfd | 360 | { |
8ae6d9c7 GM |
361 | if (IS_QLAFX00(ha)) { |
362 | if (req && req->ring_fx00) | |
363 | dma_free_coherent(&ha->pdev->dev, | |
364 | (req->length_fx00 + 1) * sizeof(request_t), | |
365 | req->ring_fx00, req->dma_fx00); | |
366 | } else if (req && req->ring) | |
73208dfd AC |
367 | dma_free_coherent(&ha->pdev->dev, |
368 | (req->length + 1) * sizeof(request_t), | |
369 | req->ring, req->dma); | |
370 | ||
8d93f550 CD |
371 | if (req) |
372 | kfree(req->outstanding_cmds); | |
373 | ||
73208dfd AC |
374 | kfree(req); |
375 | req = NULL; | |
376 | } | |
377 | ||
2afa19a9 AC |
378 | static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) |
379 | { | |
8ae6d9c7 GM |
380 | if (IS_QLAFX00(ha)) { |
381 | if (rsp && rsp->ring) | |
382 | dma_free_coherent(&ha->pdev->dev, | |
383 | (rsp->length_fx00 + 1) * sizeof(request_t), | |
384 | rsp->ring_fx00, rsp->dma_fx00); | |
385 | } else if (rsp && rsp->ring) { | |
2afa19a9 AC |
386 | dma_free_coherent(&ha->pdev->dev, |
387 | (rsp->length + 1) * sizeof(response_t), | |
388 | rsp->ring, rsp->dma); | |
8ae6d9c7 | 389 | } |
2afa19a9 AC |
390 | kfree(rsp); |
391 | rsp = NULL; | |
392 | } | |
393 | ||
73208dfd AC |
394 | static void qla2x00_free_queues(struct qla_hw_data *ha) |
395 | { | |
396 | struct req_que *req; | |
397 | struct rsp_que *rsp; | |
398 | int cnt; | |
399 | ||
2afa19a9 | 400 | for (cnt = 0; cnt < ha->max_req_queues; cnt++) { |
73208dfd | 401 | req = ha->req_q_map[cnt]; |
2afa19a9 | 402 | qla2x00_free_req_que(ha, req); |
73208dfd | 403 | } |
73208dfd AC |
404 | kfree(ha->req_q_map); |
405 | ha->req_q_map = NULL; | |
2afa19a9 AC |
406 | |
407 | for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { | |
408 | rsp = ha->rsp_q_map[cnt]; | |
409 | qla2x00_free_rsp_que(ha, rsp); | |
410 | } | |
411 | kfree(ha->rsp_q_map); | |
412 | ha->rsp_q_map = NULL; | |
73208dfd AC |
413 | } |
414 | ||
68ca949c AC |
415 | static int qla25xx_setup_mode(struct scsi_qla_host *vha) |
416 | { | |
417 | uint16_t options = 0; | |
418 | int ques, req, ret; | |
419 | struct qla_hw_data *ha = vha->hw; | |
420 | ||
7163ea81 | 421 | if (!(ha->fw_attributes & BIT_6)) { |
7c3df132 SK |
422 | ql_log(ql_log_warn, vha, 0x00d8, |
423 | "Firmware is not multi-queue capable.\n"); | |
7163ea81 AC |
424 | goto fail; |
425 | } | |
68ca949c | 426 | if (ql2xmultique_tag) { |
68ca949c AC |
427 | /* create a request queue for IO */ |
428 | options |= BIT_7; | |
429 | req = qla25xx_create_req_que(ha, options, 0, 0, -1, | |
430 | QLA_DEFAULT_QUE_QOS); | |
431 | if (!req) { | |
7c3df132 SK |
432 | ql_log(ql_log_warn, vha, 0x00e0, |
433 | "Failed to create request queue.\n"); | |
68ca949c AC |
434 | goto fail; |
435 | } | |
278274d5 | 436 | ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1); |
68ca949c AC |
437 | vha->req = ha->req_q_map[req]; |
438 | options |= BIT_1; | |
439 | for (ques = 1; ques < ha->max_rsp_queues; ques++) { | |
440 | ret = qla25xx_create_rsp_que(ha, options, 0, 0, req); | |
441 | if (!ret) { | |
7c3df132 SK |
442 | ql_log(ql_log_warn, vha, 0x00e8, |
443 | "Failed to create response queue.\n"); | |
68ca949c AC |
444 | goto fail2; |
445 | } | |
446 | } | |
7163ea81 | 447 | ha->flags.cpu_affinity_enabled = 1; |
7c3df132 | 448 | ql_dbg(ql_dbg_multiq, vha, 0xc007, |
6ef68da7 | 449 | "CPU affinity mode enabled, " |
7c3df132 SK |
450 | "no. of response queues:%d no. of request queues:%d.\n", |
451 | ha->max_rsp_queues, ha->max_req_queues); | |
452 | ql_dbg(ql_dbg_init, vha, 0x00e9, | |
6ef68da7 | 453 | "CPU affinity mode enabled, " |
7c3df132 SK |
454 | "no. of response queues:%d no. of request queues:%d.\n", |
455 | ha->max_rsp_queues, ha->max_req_queues); | |
68ca949c AC |
456 | } |
457 | return 0; | |
458 | fail2: | |
459 | qla25xx_delete_queues(vha); | |
7163ea81 AC |
460 | destroy_workqueue(ha->wq); |
461 | ha->wq = NULL; | |
0cd33fcf | 462 | vha->req = ha->req_q_map[0]; |
68ca949c AC |
463 | fail: |
464 | ha->mqenable = 0; | |
7163ea81 AC |
465 | kfree(ha->req_q_map); |
466 | kfree(ha->rsp_q_map); | |
467 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
68ca949c AC |
468 | return 1; |
469 | } | |
470 | ||
1da177e4 | 471 | static char * |
e315cd28 | 472 | qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str) |
1da177e4 | 473 | { |
e315cd28 | 474 | struct qla_hw_data *ha = vha->hw; |
1da177e4 LT |
475 | static char *pci_bus_modes[] = { |
476 | "33", "66", "100", "133", | |
477 | }; | |
478 | uint16_t pci_bus; | |
479 | ||
480 | strcpy(str, "PCI"); | |
481 | pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; | |
482 | if (pci_bus) { | |
483 | strcat(str, "-X ("); | |
484 | strcat(str, pci_bus_modes[pci_bus]); | |
485 | } else { | |
486 | pci_bus = (ha->pci_attr & BIT_8) >> 8; | |
487 | strcat(str, " ("); | |
488 | strcat(str, pci_bus_modes[pci_bus]); | |
489 | } | |
490 | strcat(str, " MHz)"); | |
491 | ||
492 | return (str); | |
493 | } | |
494 | ||
fca29703 | 495 | static char * |
e315cd28 | 496 | qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str) |
fca29703 AV |
497 | { |
498 | static char *pci_bus_modes[] = { "33", "66", "100", "133", }; | |
e315cd28 | 499 | struct qla_hw_data *ha = vha->hw; |
fca29703 | 500 | uint32_t pci_bus; |
fca29703 | 501 | |
62a276f8 | 502 | if (pci_is_pcie(ha->pdev)) { |
fca29703 | 503 | char lwstr[6]; |
62a276f8 | 504 | uint32_t lstat, lspeed, lwidth; |
fca29703 | 505 | |
62a276f8 BH |
506 | pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); |
507 | lspeed = lstat & PCI_EXP_LNKCAP_SLS; | |
508 | lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4; | |
fca29703 AV |
509 | |
510 | strcpy(str, "PCIe ("); | |
49300af7 SK |
511 | switch (lspeed) { |
512 | case 1: | |
c87a0d8c | 513 | strcat(str, "2.5GT/s "); |
49300af7 SK |
514 | break; |
515 | case 2: | |
c87a0d8c | 516 | strcat(str, "5.0GT/s "); |
49300af7 SK |
517 | break; |
518 | case 3: | |
519 | strcat(str, "8.0GT/s "); | |
520 | break; | |
521 | default: | |
fca29703 | 522 | strcat(str, "<unknown> "); |
49300af7 SK |
523 | break; |
524 | } | |
fca29703 AV |
525 | snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth); |
526 | strcat(str, lwstr); | |
527 | ||
528 | return str; | |
529 | } | |
530 | ||
531 | strcpy(str, "PCI"); | |
532 | pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; | |
533 | if (pci_bus == 0 || pci_bus == 8) { | |
534 | strcat(str, " ("); | |
535 | strcat(str, pci_bus_modes[pci_bus >> 3]); | |
536 | } else { | |
537 | strcat(str, "-X "); | |
538 | if (pci_bus & BIT_2) | |
539 | strcat(str, "Mode 2"); | |
540 | else | |
541 | strcat(str, "Mode 1"); | |
542 | strcat(str, " ("); | |
543 | strcat(str, pci_bus_modes[pci_bus & ~BIT_2]); | |
544 | } | |
545 | strcat(str, " MHz)"); | |
546 | ||
547 | return str; | |
548 | } | |
549 | ||
e5f82ab8 | 550 | static char * |
df57caba | 551 | qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) |
1da177e4 LT |
552 | { |
553 | char un_str[10]; | |
e315cd28 | 554 | struct qla_hw_data *ha = vha->hw; |
fa2a1ce5 | 555 | |
df57caba HM |
556 | snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, |
557 | ha->fw_minor_version, ha->fw_subminor_version); | |
1da177e4 LT |
558 | |
559 | if (ha->fw_attributes & BIT_9) { | |
560 | strcat(str, "FLX"); | |
561 | return (str); | |
562 | } | |
563 | ||
564 | switch (ha->fw_attributes & 0xFF) { | |
565 | case 0x7: | |
566 | strcat(str, "EF"); | |
567 | break; | |
568 | case 0x17: | |
569 | strcat(str, "TP"); | |
570 | break; | |
571 | case 0x37: | |
572 | strcat(str, "IP"); | |
573 | break; | |
574 | case 0x77: | |
575 | strcat(str, "VI"); | |
576 | break; | |
577 | default: | |
578 | sprintf(un_str, "(%x)", ha->fw_attributes); | |
579 | strcat(str, un_str); | |
580 | break; | |
581 | } | |
582 | if (ha->fw_attributes & 0x100) | |
583 | strcat(str, "X"); | |
584 | ||
585 | return (str); | |
586 | } | |
587 | ||
e5f82ab8 | 588 | static char * |
df57caba | 589 | qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) |
fca29703 | 590 | { |
e315cd28 | 591 | struct qla_hw_data *ha = vha->hw; |
f0883ac6 | 592 | |
df57caba | 593 | snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, |
3a03eb79 | 594 | ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); |
fca29703 | 595 | return str; |
fca29703 AV |
596 | } |
597 | ||
9ba56b95 GM |
598 | void |
599 | qla2x00_sp_free_dma(void *vha, void *ptr) | |
fca29703 | 600 | { |
9ba56b95 GM |
601 | srb_t *sp = (srb_t *)ptr; |
602 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
603 | struct qla_hw_data *ha = sp->fcport->vha->hw; | |
604 | void *ctx = GET_CMD_CTX_SP(sp); | |
fca29703 | 605 | |
9ba56b95 GM |
606 | if (sp->flags & SRB_DMA_VALID) { |
607 | scsi_dma_unmap(cmd); | |
608 | sp->flags &= ~SRB_DMA_VALID; | |
7c3df132 | 609 | } |
fca29703 | 610 | |
9ba56b95 GM |
611 | if (sp->flags & SRB_CRC_PROT_DMA_VALID) { |
612 | dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), | |
613 | scsi_prot_sg_count(cmd), cmd->sc_data_direction); | |
614 | sp->flags &= ~SRB_CRC_PROT_DMA_VALID; | |
615 | } | |
616 | ||
617 | if (sp->flags & SRB_CRC_CTX_DSD_VALID) { | |
618 | /* List assured to be having elements */ | |
f83adb61 | 619 | qla2x00_clean_dsd_pool(ha, sp, NULL); |
9ba56b95 GM |
620 | sp->flags &= ~SRB_CRC_CTX_DSD_VALID; |
621 | } | |
622 | ||
623 | if (sp->flags & SRB_CRC_CTX_DMA_VALID) { | |
624 | dma_pool_free(ha->dl_dma_pool, ctx, | |
625 | ((struct crc_context *)ctx)->crc_ctx_dma); | |
626 | sp->flags &= ~SRB_CRC_CTX_DMA_VALID; | |
627 | } | |
628 | ||
629 | if (sp->flags & SRB_FCP_CMND_DMA_VALID) { | |
630 | struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx; | |
fca29703 | 631 | |
9ba56b95 GM |
632 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, |
633 | ctx1->fcp_cmnd_dma); | |
634 | list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list); | |
635 | ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt; | |
636 | ha->gbl_dsd_avail += ctx1->dsd_use_cnt; | |
637 | mempool_free(ctx1, ha->ctx_mempool); | |
638 | ctx1 = NULL; | |
639 | } | |
640 | ||
641 | CMD_SP(cmd) = NULL; | |
b00ee7d7 | 642 | qla2x00_rel_sp(sp->fcport->vha, sp); |
9ba56b95 GM |
643 | } |
644 | ||
14b06808 | 645 | static void |
9ba56b95 GM |
646 | qla2x00_sp_compl(void *data, void *ptr, int res) |
647 | { | |
648 | struct qla_hw_data *ha = (struct qla_hw_data *)data; | |
649 | srb_t *sp = (srb_t *)ptr; | |
650 | struct scsi_cmnd *cmd = GET_CMD_SP(sp); | |
651 | ||
652 | cmd->result = res; | |
653 | ||
654 | if (atomic_read(&sp->ref_count) == 0) { | |
655 | ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015, | |
656 | "SP reference-count to ZERO -- sp=%p cmd=%p.\n", | |
657 | sp, GET_CMD_SP(sp)); | |
658 | if (ql2xextended_error_logging & ql_dbg_io) | |
659 | BUG(); | |
660 | return; | |
661 | } | |
662 | if (!atomic_dec_and_test(&sp->ref_count)) | |
663 | return; | |
664 | ||
665 | qla2x00_sp_free_dma(ha, sp); | |
666 | cmd->scsi_done(cmd); | |
fca29703 AV |
667 | } |
668 | ||
8ae6d9c7 GM |
669 | /* If we are SP1 here, we need to still take and release the host_lock as SP1 |
670 | * does not have the changes necessary to avoid taking host->host_lock. | |
671 | */ | |
1da177e4 | 672 | static int |
f5e3e40b | 673 | qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) |
fca29703 | 674 | { |
134ae078 | 675 | scsi_qla_host_t *vha = shost_priv(host); |
fca29703 | 676 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
19a7b4ae | 677 | struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); |
e315cd28 AC |
678 | struct qla_hw_data *ha = vha->hw; |
679 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | |
fca29703 AV |
680 | srb_t *sp; |
681 | int rval; | |
682 | ||
85880801 | 683 | if (ha->flags.eeh_busy) { |
7c3df132 | 684 | if (ha->flags.pci_channel_io_perm_failure) { |
5f28d2d7 | 685 | ql_dbg(ql_dbg_aer, vha, 0x9010, |
7c3df132 SK |
686 | "PCI Channel IO permanent failure, exiting " |
687 | "cmd=%p.\n", cmd); | |
b9b12f73 | 688 | cmd->result = DID_NO_CONNECT << 16; |
7c3df132 | 689 | } else { |
5f28d2d7 | 690 | ql_dbg(ql_dbg_aer, vha, 0x9011, |
7c3df132 | 691 | "EEH_Busy, Requeuing the cmd=%p.\n", cmd); |
85880801 | 692 | cmd->result = DID_REQUEUE << 16; |
7c3df132 | 693 | } |
14e660e6 SJ |
694 | goto qc24_fail_command; |
695 | } | |
696 | ||
19a7b4ae JSEC |
697 | rval = fc_remote_port_chkready(rport); |
698 | if (rval) { | |
699 | cmd->result = rval; | |
5f28d2d7 | 700 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, |
7c3df132 SK |
701 | "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", |
702 | cmd, rval); | |
fca29703 AV |
703 | goto qc24_fail_command; |
704 | } | |
705 | ||
bad75002 AE |
706 | if (!vha->flags.difdix_supported && |
707 | scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { | |
7c3df132 SK |
708 | ql_dbg(ql_dbg_io, vha, 0x3004, |
709 | "DIF Cap not reg, fail DIF capable cmd's:%p.\n", | |
710 | cmd); | |
bad75002 AE |
711 | cmd->result = DID_NO_CONNECT << 16; |
712 | goto qc24_fail_command; | |
713 | } | |
aa651be8 CD |
714 | |
715 | if (!fcport) { | |
716 | cmd->result = DID_NO_CONNECT << 16; | |
717 | goto qc24_fail_command; | |
718 | } | |
719 | ||
fca29703 AV |
720 | if (atomic_read(&fcport->state) != FCS_ONLINE) { |
721 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || | |
38170fa8 | 722 | atomic_read(&base_vha->loop_state) == LOOP_DEAD) { |
7c3df132 SK |
723 | ql_dbg(ql_dbg_io, vha, 0x3005, |
724 | "Returning DNC, fcport_state=%d loop_state=%d.\n", | |
725 | atomic_read(&fcport->state), | |
726 | atomic_read(&base_vha->loop_state)); | |
fca29703 AV |
727 | cmd->result = DID_NO_CONNECT << 16; |
728 | goto qc24_fail_command; | |
729 | } | |
7b594131 | 730 | goto qc24_target_busy; |
fca29703 AV |
731 | } |
732 | ||
e05fe292 CD |
733 | /* |
734 | * Return target busy if we've received a non-zero retry_delay_timer | |
735 | * in a FCP_RSP. | |
736 | */ | |
975f7d46 BP |
737 | if (fcport->retry_delay_timestamp == 0) { |
738 | /* retry delay not set */ | |
739 | } else if (time_after(jiffies, fcport->retry_delay_timestamp)) | |
e05fe292 CD |
740 | fcport->retry_delay_timestamp = 0; |
741 | else | |
742 | goto qc24_target_busy; | |
743 | ||
b00ee7d7 | 744 | sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC); |
50280c01 | 745 | if (!sp) |
f5e3e40b | 746 | goto qc24_host_busy; |
fca29703 | 747 | |
9ba56b95 GM |
748 | sp->u.scmd.cmd = cmd; |
749 | sp->type = SRB_SCSI_CMD; | |
750 | atomic_set(&sp->ref_count, 1); | |
751 | CMD_SP(cmd) = (void *)sp; | |
752 | sp->free = qla2x00_sp_free_dma; | |
753 | sp->done = qla2x00_sp_compl; | |
754 | ||
e315cd28 | 755 | rval = ha->isp_ops->start_scsi(sp); |
7c3df132 | 756 | if (rval != QLA_SUCCESS) { |
53016ed3 | 757 | ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, |
7c3df132 | 758 | "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); |
fca29703 | 759 | goto qc24_host_busy_free_sp; |
7c3df132 | 760 | } |
fca29703 | 761 | |
fca29703 AV |
762 | return 0; |
763 | ||
764 | qc24_host_busy_free_sp: | |
9ba56b95 | 765 | qla2x00_sp_free_dma(ha, sp); |
fca29703 | 766 | |
f5e3e40b | 767 | qc24_host_busy: |
fca29703 AV |
768 | return SCSI_MLQUEUE_HOST_BUSY; |
769 | ||
7b594131 MC |
770 | qc24_target_busy: |
771 | return SCSI_MLQUEUE_TARGET_BUSY; | |
772 | ||
fca29703 | 773 | qc24_fail_command: |
f5e3e40b | 774 | cmd->scsi_done(cmd); |
fca29703 AV |
775 | |
776 | return 0; | |
777 | } | |
778 | ||
1da177e4 LT |
779 | /* |
780 | * qla2x00_eh_wait_on_command | |
781 | * Waits for the command to be returned by the Firmware for some | |
782 | * max time. | |
783 | * | |
784 | * Input: | |
1da177e4 | 785 | * cmd = Scsi Command to wait on. |
1da177e4 LT |
786 | * |
787 | * Return: | |
788 | * Not Found : 0 | |
789 | * Found : 1 | |
790 | */ | |
791 | static int | |
e315cd28 | 792 | qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd) |
1da177e4 | 793 | { |
fe74c71f | 794 | #define ABORT_POLLING_PERIOD 1000 |
478c3b03 | 795 | #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) |
f4f051eb | 796 | unsigned long wait_iter = ABORT_WAIT_ITER; |
85880801 AV |
797 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
798 | struct qla_hw_data *ha = vha->hw; | |
f4f051eb | 799 | int ret = QLA_SUCCESS; |
1da177e4 | 800 | |
85880801 | 801 | if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) { |
7c3df132 SK |
802 | ql_dbg(ql_dbg_taskm, vha, 0x8005, |
803 | "Return:eh_wait.\n"); | |
85880801 AV |
804 | return ret; |
805 | } | |
806 | ||
d970432c | 807 | while (CMD_SP(cmd) && wait_iter--) { |
fe74c71f | 808 | msleep(ABORT_POLLING_PERIOD); |
f4f051eb AV |
809 | } |
810 | if (CMD_SP(cmd)) | |
811 | ret = QLA_FUNCTION_FAILED; | |
1da177e4 | 812 | |
f4f051eb | 813 | return ret; |
1da177e4 LT |
814 | } |
815 | ||
816 | /* | |
817 | * qla2x00_wait_for_hba_online | |
fa2a1ce5 | 818 | * Wait till the HBA is online after going through |
1da177e4 LT |
819 | * <= MAX_RETRIES_OF_ISP_ABORT or |
820 | * finally HBA is disabled ie marked offline | |
821 | * | |
822 | * Input: | |
823 | * ha - pointer to host adapter structure | |
fa2a1ce5 AV |
824 | * |
825 | * Note: | |
1da177e4 LT |
826 | * Does context switching-Release SPIN_LOCK |
827 | * (if any) before calling this routine. | |
828 | * | |
829 | * Return: | |
830 | * Success (Adapter is online) : 0 | |
831 | * Failed (Adapter is offline/disabled) : 1 | |
832 | */ | |
854165f4 | 833 | int |
e315cd28 | 834 | qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) |
1da177e4 | 835 | { |
fca29703 AV |
836 | int return_status; |
837 | unsigned long wait_online; | |
e315cd28 AC |
838 | struct qla_hw_data *ha = vha->hw; |
839 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 840 | |
fa2a1ce5 | 841 | wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); |
e315cd28 AC |
842 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || |
843 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
844 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
845 | ha->dpc_active) && time_before(jiffies, wait_online)) { | |
1da177e4 LT |
846 | |
847 | msleep(1000); | |
848 | } | |
e315cd28 | 849 | if (base_vha->flags.online) |
fa2a1ce5 | 850 | return_status = QLA_SUCCESS; |
1da177e4 LT |
851 | else |
852 | return_status = QLA_FUNCTION_FAILED; | |
853 | ||
1da177e4 LT |
854 | return (return_status); |
855 | } | |
856 | ||
86fbee86 | 857 | /* |
638a1a01 SC |
858 | * qla2x00_wait_for_hba_ready |
859 | * Wait till the HBA is ready before doing driver unload | |
86fbee86 LC |
860 | * |
861 | * Input: | |
862 | * ha - pointer to host adapter structure | |
863 | * | |
864 | * Note: | |
865 | * Does context switching-Release SPIN_LOCK | |
866 | * (if any) before calling this routine. | |
867 | * | |
86fbee86 | 868 | */ |
638a1a01 SC |
869 | static void |
870 | qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) | |
86fbee86 | 871 | { |
86fbee86 | 872 | struct qla_hw_data *ha = vha->hw; |
86fbee86 | 873 | |
9d35894d SC |
874 | while (((qla2x00_reset_active(vha)) || ha->dpc_active || |
875 | ha->flags.mbox_busy) || | |
876 | test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || | |
877 | test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) | |
86fbee86 | 878 | msleep(1000); |
86fbee86 LC |
879 | } |
880 | ||
2533cf67 LC |
881 | int |
882 | qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) | |
883 | { | |
884 | int return_status; | |
885 | unsigned long wait_reset; | |
886 | struct qla_hw_data *ha = vha->hw; | |
887 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
888 | ||
889 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | |
890 | while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || | |
891 | test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || | |
892 | test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || | |
893 | ha->dpc_active) && time_before(jiffies, wait_reset)) { | |
894 | ||
895 | msleep(1000); | |
896 | ||
897 | if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && | |
898 | ha->flags.chip_reset_done) | |
899 | break; | |
900 | } | |
901 | if (ha->flags.chip_reset_done) | |
902 | return_status = QLA_SUCCESS; | |
903 | else | |
904 | return_status = QLA_FUNCTION_FAILED; | |
905 | ||
906 | return return_status; | |
907 | } | |
908 | ||
083a469d GM |
909 | static void |
910 | sp_get(struct srb *sp) | |
911 | { | |
912 | atomic_inc(&sp->ref_count); | |
913 | } | |
914 | ||
1da177e4 LT |
915 | /************************************************************************** |
916 | * qla2xxx_eh_abort | |
917 | * | |
918 | * Description: | |
919 | * The abort function will abort the specified command. | |
920 | * | |
921 | * Input: | |
922 | * cmd = Linux SCSI command packet to be aborted. | |
923 | * | |
924 | * Returns: | |
925 | * Either SUCCESS or FAILED. | |
926 | * | |
927 | * Note: | |
2ea00202 | 928 | * Only return FAILED if command not returned by firmware. |
1da177e4 | 929 | **************************************************************************/ |
e5f82ab8 | 930 | static int |
1da177e4 LT |
931 | qla2xxx_eh_abort(struct scsi_cmnd *cmd) |
932 | { | |
e315cd28 | 933 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
f4f051eb | 934 | srb_t *sp; |
4e98d3b8 | 935 | int ret; |
9cb78c16 HR |
936 | unsigned int id; |
937 | uint64_t lun; | |
18e144d3 | 938 | unsigned long flags; |
f934c9d0 | 939 | int rval, wait = 0; |
e315cd28 | 940 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 941 | |
f4f051eb | 942 | if (!CMD_SP(cmd)) |
2ea00202 | 943 | return SUCCESS; |
1da177e4 | 944 | |
4e98d3b8 AV |
945 | ret = fc_block_scsi_eh(cmd); |
946 | if (ret != 0) | |
947 | return ret; | |
948 | ret = SUCCESS; | |
949 | ||
f4f051eb AV |
950 | id = cmd->device->id; |
951 | lun = cmd->device->lun; | |
1da177e4 | 952 | |
e315cd28 | 953 | spin_lock_irqsave(&ha->hardware_lock, flags); |
170babc3 MC |
954 | sp = (srb_t *) CMD_SP(cmd); |
955 | if (!sp) { | |
956 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
957 | return SUCCESS; | |
958 | } | |
1da177e4 | 959 | |
7c3df132 | 960 | ql_dbg(ql_dbg_taskm, vha, 0x8002, |
9cb78c16 | 961 | "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p\n", |
cfb0919c | 962 | vha->host_no, id, lun, sp, cmd); |
17d98630 | 963 | |
170babc3 MC |
964 | /* Get a reference to the sp and drop the lock.*/ |
965 | sp_get(sp); | |
083a469d | 966 | |
e315cd28 | 967 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
f934c9d0 CD |
968 | rval = ha->isp_ops->abort_command(sp); |
969 | if (rval) { | |
970 | if (rval == QLA_FUNCTION_PARAMETER_ERROR) { | |
971 | /* | |
972 | * Decrement the ref_count since we can't find the | |
973 | * command | |
974 | */ | |
975 | atomic_dec(&sp->ref_count); | |
976 | ret = SUCCESS; | |
977 | } else | |
978 | ret = FAILED; | |
979 | ||
7c3df132 | 980 | ql_dbg(ql_dbg_taskm, vha, 0x8003, |
f934c9d0 | 981 | "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval); |
170babc3 | 982 | } else { |
7c3df132 | 983 | ql_dbg(ql_dbg_taskm, vha, 0x8004, |
cfb0919c | 984 | "Abort command mbx success cmd=%p.\n", cmd); |
170babc3 MC |
985 | wait = 1; |
986 | } | |
75942064 SK |
987 | |
988 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
f934c9d0 CD |
989 | /* |
990 | * Clear the slot in the oustanding_cmds array if we can't find the | |
991 | * command to reclaim the resources. | |
992 | */ | |
993 | if (rval == QLA_FUNCTION_PARAMETER_ERROR) | |
994 | vha->req->outstanding_cmds[sp->handle] = NULL; | |
9ba56b95 | 995 | sp->done(ha, sp, 0); |
75942064 | 996 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
1da177e4 | 997 | |
bc91ade9 CD |
998 | /* Did the command return during mailbox execution? */ |
999 | if (ret == FAILED && !CMD_SP(cmd)) | |
1000 | ret = SUCCESS; | |
1001 | ||
f4f051eb | 1002 | /* Wait for the command to be returned. */ |
2ea00202 | 1003 | if (wait) { |
e315cd28 | 1004 | if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) { |
7c3df132 | 1005 | ql_log(ql_log_warn, vha, 0x8006, |
cfb0919c | 1006 | "Abort handler timed out cmd=%p.\n", cmd); |
2ea00202 | 1007 | ret = FAILED; |
f4f051eb | 1008 | } |
1da177e4 | 1009 | } |
1da177e4 | 1010 | |
7c3df132 | 1011 | ql_log(ql_log_info, vha, 0x801c, |
9cb78c16 | 1012 | "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n", |
cfb0919c | 1013 | vha->host_no, id, lun, wait, ret); |
1da177e4 | 1014 | |
f4f051eb AV |
1015 | return ret; |
1016 | } | |
1da177e4 | 1017 | |
4d78c973 | 1018 | int |
e315cd28 | 1019 | qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, |
9cb78c16 | 1020 | uint64_t l, enum nexus_wait_type type) |
f4f051eb | 1021 | { |
17d98630 | 1022 | int cnt, match, status; |
18e144d3 | 1023 | unsigned long flags; |
e315cd28 | 1024 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1025 | struct req_que *req; |
4d78c973 | 1026 | srb_t *sp; |
9ba56b95 | 1027 | struct scsi_cmnd *cmd; |
1da177e4 | 1028 | |
523ec773 | 1029 | status = QLA_SUCCESS; |
17d98630 | 1030 | |
e315cd28 | 1031 | spin_lock_irqsave(&ha->hardware_lock, flags); |
67c2e93a | 1032 | req = vha->req; |
17d98630 | 1033 | for (cnt = 1; status == QLA_SUCCESS && |
8d93f550 | 1034 | cnt < req->num_outstanding_cmds; cnt++) { |
17d98630 AC |
1035 | sp = req->outstanding_cmds[cnt]; |
1036 | if (!sp) | |
523ec773 | 1037 | continue; |
9ba56b95 | 1038 | if (sp->type != SRB_SCSI_CMD) |
cf53b069 | 1039 | continue; |
17d98630 AC |
1040 | if (vha->vp_idx != sp->fcport->vha->vp_idx) |
1041 | continue; | |
1042 | match = 0; | |
9ba56b95 | 1043 | cmd = GET_CMD_SP(sp); |
17d98630 AC |
1044 | switch (type) { |
1045 | case WAIT_HOST: | |
1046 | match = 1; | |
1047 | break; | |
1048 | case WAIT_TARGET: | |
9ba56b95 | 1049 | match = cmd->device->id == t; |
17d98630 AC |
1050 | break; |
1051 | case WAIT_LUN: | |
9ba56b95 GM |
1052 | match = (cmd->device->id == t && |
1053 | cmd->device->lun == l); | |
17d98630 | 1054 | break; |
73208dfd | 1055 | } |
17d98630 AC |
1056 | if (!match) |
1057 | continue; | |
1058 | ||
1059 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
9ba56b95 | 1060 | status = qla2x00_eh_wait_on_command(cmd); |
17d98630 | 1061 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1da177e4 | 1062 | } |
e315cd28 | 1063 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
523ec773 AV |
1064 | |
1065 | return status; | |
1da177e4 LT |
1066 | } |
1067 | ||
523ec773 AV |
1068 | static char *reset_errors[] = { |
1069 | "HBA not online", | |
1070 | "HBA not ready", | |
1071 | "Task management failed", | |
1072 | "Waiting for command completions", | |
1073 | }; | |
1da177e4 | 1074 | |
e5f82ab8 | 1075 | static int |
523ec773 | 1076 | __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type, |
9cb78c16 | 1077 | struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int)) |
1da177e4 | 1078 | { |
e315cd28 | 1079 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1080 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
523ec773 | 1081 | int err; |
1da177e4 | 1082 | |
7c3df132 | 1083 | if (!fcport) { |
523ec773 | 1084 | return FAILED; |
7c3df132 | 1085 | } |
1da177e4 | 1086 | |
4e98d3b8 AV |
1087 | err = fc_block_scsi_eh(cmd); |
1088 | if (err != 0) | |
1089 | return err; | |
1090 | ||
7c3df132 | 1091 | ql_log(ql_log_info, vha, 0x8009, |
9cb78c16 | 1092 | "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no, |
7c3df132 | 1093 | cmd->device->id, cmd->device->lun, cmd); |
1da177e4 | 1094 | |
523ec773 | 1095 | err = 0; |
7c3df132 SK |
1096 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
1097 | ql_log(ql_log_warn, vha, 0x800a, | |
1098 | "Wait for hba online failed for cmd=%p.\n", cmd); | |
523ec773 | 1099 | goto eh_reset_failed; |
7c3df132 | 1100 | } |
523ec773 | 1101 | err = 2; |
2afa19a9 | 1102 | if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1) |
7c3df132 SK |
1103 | != QLA_SUCCESS) { |
1104 | ql_log(ql_log_warn, vha, 0x800c, | |
1105 | "do_reset failed for cmd=%p.\n", cmd); | |
523ec773 | 1106 | goto eh_reset_failed; |
7c3df132 | 1107 | } |
523ec773 | 1108 | err = 3; |
e315cd28 | 1109 | if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id, |
7c3df132 SK |
1110 | cmd->device->lun, type) != QLA_SUCCESS) { |
1111 | ql_log(ql_log_warn, vha, 0x800d, | |
d6a03581 | 1112 | "wait for pending cmds failed for cmd=%p.\n", cmd); |
523ec773 | 1113 | goto eh_reset_failed; |
7c3df132 | 1114 | } |
523ec773 | 1115 | |
7c3df132 | 1116 | ql_log(ql_log_info, vha, 0x800e, |
9cb78c16 | 1117 | "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name, |
cfb0919c | 1118 | vha->host_no, cmd->device->id, cmd->device->lun, cmd); |
523ec773 AV |
1119 | |
1120 | return SUCCESS; | |
1121 | ||
4d78c973 | 1122 | eh_reset_failed: |
7c3df132 | 1123 | ql_log(ql_log_info, vha, 0x800f, |
9cb78c16 | 1124 | "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name, |
cfb0919c CD |
1125 | reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, |
1126 | cmd); | |
523ec773 AV |
1127 | return FAILED; |
1128 | } | |
1da177e4 | 1129 | |
523ec773 AV |
1130 | static int |
1131 | qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) | |
1132 | { | |
e315cd28 AC |
1133 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1134 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1135 | |
523ec773 AV |
1136 | return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd, |
1137 | ha->isp_ops->lun_reset); | |
1da177e4 LT |
1138 | } |
1139 | ||
1da177e4 | 1140 | static int |
523ec773 | 1141 | qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) |
1da177e4 | 1142 | { |
e315cd28 AC |
1143 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
1144 | struct qla_hw_data *ha = vha->hw; | |
1da177e4 | 1145 | |
523ec773 AV |
1146 | return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd, |
1147 | ha->isp_ops->target_reset); | |
1da177e4 LT |
1148 | } |
1149 | ||
1da177e4 LT |
1150 | /************************************************************************** |
1151 | * qla2xxx_eh_bus_reset | |
1152 | * | |
1153 | * Description: | |
1154 | * The bus reset function will reset the bus and abort any executing | |
1155 | * commands. | |
1156 | * | |
1157 | * Input: | |
1158 | * cmd = Linux SCSI command packet of the command that cause the | |
1159 | * bus reset. | |
1160 | * | |
1161 | * Returns: | |
1162 | * SUCCESS/FAILURE (defined as macro in scsi.h). | |
1163 | * | |
1164 | **************************************************************************/ | |
e5f82ab8 | 1165 | static int |
1da177e4 LT |
1166 | qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) |
1167 | { | |
e315cd28 | 1168 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
bdf79621 | 1169 | fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; |
2c3dfe3f | 1170 | int ret = FAILED; |
9cb78c16 HR |
1171 | unsigned int id; |
1172 | uint64_t lun; | |
f4f051eb | 1173 | |
f4f051eb AV |
1174 | id = cmd->device->id; |
1175 | lun = cmd->device->lun; | |
1da177e4 | 1176 | |
7c3df132 | 1177 | if (!fcport) { |
f4f051eb | 1178 | return ret; |
7c3df132 | 1179 | } |
1da177e4 | 1180 | |
4e98d3b8 AV |
1181 | ret = fc_block_scsi_eh(cmd); |
1182 | if (ret != 0) | |
1183 | return ret; | |
1184 | ret = FAILED; | |
1185 | ||
7c3df132 | 1186 | ql_log(ql_log_info, vha, 0x8012, |
9cb78c16 | 1187 | "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); |
1da177e4 | 1188 | |
e315cd28 | 1189 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
7c3df132 SK |
1190 | ql_log(ql_log_fatal, vha, 0x8013, |
1191 | "Wait for hba online failed board disabled.\n"); | |
f4f051eb | 1192 | goto eh_bus_reset_done; |
1da177e4 LT |
1193 | } |
1194 | ||
ad537689 SK |
1195 | if (qla2x00_loop_reset(vha) == QLA_SUCCESS) |
1196 | ret = SUCCESS; | |
1197 | ||
f4f051eb AV |
1198 | if (ret == FAILED) |
1199 | goto eh_bus_reset_done; | |
1da177e4 | 1200 | |
9a41a62b | 1201 | /* Flush outstanding commands. */ |
4d78c973 | 1202 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != |
7c3df132 SK |
1203 | QLA_SUCCESS) { |
1204 | ql_log(ql_log_warn, vha, 0x8014, | |
1205 | "Wait for pending commands failed.\n"); | |
9a41a62b | 1206 | ret = FAILED; |
7c3df132 | 1207 | } |
1da177e4 | 1208 | |
f4f051eb | 1209 | eh_bus_reset_done: |
7c3df132 | 1210 | ql_log(ql_log_warn, vha, 0x802b, |
9cb78c16 | 1211 | "BUS RESET %s nexus=%ld:%d:%llu.\n", |
d6a03581 | 1212 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); |
1da177e4 | 1213 | |
f4f051eb | 1214 | return ret; |
1da177e4 LT |
1215 | } |
1216 | ||
1217 | /************************************************************************** | |
1218 | * qla2xxx_eh_host_reset | |
1219 | * | |
1220 | * Description: | |
1221 | * The reset function will reset the Adapter. | |
1222 | * | |
1223 | * Input: | |
1224 | * cmd = Linux SCSI command packet of the command that cause the | |
1225 | * adapter reset. | |
1226 | * | |
1227 | * Returns: | |
1228 | * Either SUCCESS or FAILED. | |
1229 | * | |
1230 | * Note: | |
1231 | **************************************************************************/ | |
e5f82ab8 | 1232 | static int |
1da177e4 LT |
1233 | qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) |
1234 | { | |
e315cd28 | 1235 | scsi_qla_host_t *vha = shost_priv(cmd->device->host); |
e315cd28 | 1236 | struct qla_hw_data *ha = vha->hw; |
2c3dfe3f | 1237 | int ret = FAILED; |
9cb78c16 HR |
1238 | unsigned int id; |
1239 | uint64_t lun; | |
e315cd28 | 1240 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
1da177e4 | 1241 | |
f4f051eb AV |
1242 | id = cmd->device->id; |
1243 | lun = cmd->device->lun; | |
f4f051eb | 1244 | |
7c3df132 | 1245 | ql_log(ql_log_info, vha, 0x8018, |
9cb78c16 | 1246 | "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); |
1da177e4 | 1247 | |
63ee7072 CD |
1248 | /* |
1249 | * No point in issuing another reset if one is active. Also do not | |
1250 | * attempt a reset if we are updating flash. | |
1251 | */ | |
1252 | if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) | |
f4f051eb | 1253 | goto eh_host_reset_lock; |
1da177e4 | 1254 | |
e315cd28 AC |
1255 | if (vha != base_vha) { |
1256 | if (qla2x00_vp_abort_isp(vha)) | |
f4f051eb | 1257 | goto eh_host_reset_lock; |
e315cd28 | 1258 | } else { |
7ec0effd | 1259 | if (IS_P3P_TYPE(vha->hw)) { |
a9083016 GM |
1260 | if (!qla82xx_fcoe_ctx_reset(vha)) { |
1261 | /* Ctx reset success */ | |
1262 | ret = SUCCESS; | |
1263 | goto eh_host_reset_lock; | |
1264 | } | |
1265 | /* fall thru if ctx reset failed */ | |
1266 | } | |
68ca949c AC |
1267 | if (ha->wq) |
1268 | flush_workqueue(ha->wq); | |
1269 | ||
e315cd28 | 1270 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 1271 | if (ha->isp_ops->abort_isp(base_vha)) { |
e315cd28 AC |
1272 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
1273 | /* failed. schedule dpc to try */ | |
1274 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | |
1275 | ||
7c3df132 SK |
1276 | if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { |
1277 | ql_log(ql_log_warn, vha, 0x802a, | |
1278 | "wait for hba online failed.\n"); | |
e315cd28 | 1279 | goto eh_host_reset_lock; |
7c3df132 | 1280 | } |
e315cd28 AC |
1281 | } |
1282 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
fa2a1ce5 | 1283 | } |
1da177e4 | 1284 | |
e315cd28 | 1285 | /* Waiting for command to be returned to OS.*/ |
4d78c973 | 1286 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == |
e315cd28 | 1287 | QLA_SUCCESS) |
f4f051eb | 1288 | ret = SUCCESS; |
1da177e4 | 1289 | |
f4f051eb | 1290 | eh_host_reset_lock: |
cfb0919c | 1291 | ql_log(ql_log_info, vha, 0x8017, |
9cb78c16 | 1292 | "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", |
cfb0919c | 1293 | (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); |
1da177e4 | 1294 | |
f4f051eb AV |
1295 | return ret; |
1296 | } | |
1da177e4 LT |
1297 | |
1298 | /* | |
1299 | * qla2x00_loop_reset | |
1300 | * Issue loop reset. | |
1301 | * | |
1302 | * Input: | |
1303 | * ha = adapter block pointer. | |
1304 | * | |
1305 | * Returns: | |
1306 | * 0 = success | |
1307 | */ | |
a4722cf2 | 1308 | int |
e315cd28 | 1309 | qla2x00_loop_reset(scsi_qla_host_t *vha) |
1da177e4 | 1310 | { |
0c8c39af | 1311 | int ret; |
bdf79621 | 1312 | struct fc_port *fcport; |
e315cd28 | 1313 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 1314 | |
5854771e AB |
1315 | if (IS_QLAFX00(ha)) { |
1316 | return qlafx00_loop_reset(vha); | |
1317 | } | |
1318 | ||
f4c496c1 | 1319 | if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) { |
55e5ed27 AV |
1320 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
1321 | if (fcport->port_type != FCT_TARGET) | |
1322 | continue; | |
1323 | ||
1324 | ret = ha->isp_ops->target_reset(fcport, 0, 0); | |
1325 | if (ret != QLA_SUCCESS) { | |
7c3df132 | 1326 | ql_dbg(ql_dbg_taskm, vha, 0x802c, |
5854771e | 1327 | "Bus Reset failed: Reset=%d " |
7c3df132 | 1328 | "d_id=%x.\n", ret, fcport->d_id.b24); |
55e5ed27 AV |
1329 | } |
1330 | } | |
1331 | } | |
1332 | ||
8ae6d9c7 | 1333 | |
6246b8a1 | 1334 | if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { |
0b7e7c53 AV |
1335 | atomic_set(&vha->loop_state, LOOP_DOWN); |
1336 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | |
1337 | qla2x00_mark_all_devices_lost(vha, 0); | |
e315cd28 | 1338 | ret = qla2x00_full_login_lip(vha); |
0c8c39af | 1339 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
1340 | ql_dbg(ql_dbg_taskm, vha, 0x802d, |
1341 | "full_login_lip=%d.\n", ret); | |
749af3d5 | 1342 | } |
0c8c39af AV |
1343 | } |
1344 | ||
0d6e61bc | 1345 | if (ha->flags.enable_lip_reset) { |
e315cd28 | 1346 | ret = qla2x00_lip_reset(vha); |
ad537689 | 1347 | if (ret != QLA_SUCCESS) |
7c3df132 SK |
1348 | ql_dbg(ql_dbg_taskm, vha, 0x802e, |
1349 | "lip_reset failed (%d).\n", ret); | |
1da177e4 LT |
1350 | } |
1351 | ||
1da177e4 | 1352 | /* Issue marker command only when we are going to start the I/O */ |
e315cd28 | 1353 | vha->marker_needed = 1; |
1da177e4 | 1354 | |
0c8c39af | 1355 | return QLA_SUCCESS; |
1da177e4 LT |
1356 | } |
1357 | ||
df4bf0bb | 1358 | void |
e315cd28 | 1359 | qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) |
df4bf0bb | 1360 | { |
73208dfd | 1361 | int que, cnt; |
df4bf0bb AV |
1362 | unsigned long flags; |
1363 | srb_t *sp; | |
e315cd28 | 1364 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 1365 | struct req_que *req; |
df4bf0bb | 1366 | |
c0cb4496 AE |
1367 | qlt_host_reset_handler(ha); |
1368 | ||
df4bf0bb | 1369 | spin_lock_irqsave(&ha->hardware_lock, flags); |
2afa19a9 | 1370 | for (que = 0; que < ha->max_req_queues; que++) { |
29bdccbe | 1371 | req = ha->req_q_map[que]; |
73208dfd AC |
1372 | if (!req) |
1373 | continue; | |
8d93f550 CD |
1374 | if (!req->outstanding_cmds) |
1375 | continue; | |
1376 | for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { | |
73208dfd | 1377 | sp = req->outstanding_cmds[cnt]; |
e612d465 | 1378 | if (sp) { |
73208dfd | 1379 | req->outstanding_cmds[cnt] = NULL; |
9ba56b95 | 1380 | sp->done(vha, sp, res); |
73208dfd | 1381 | } |
df4bf0bb AV |
1382 | } |
1383 | } | |
1384 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1385 | } | |
1386 | ||
f4f051eb AV |
1387 | static int |
1388 | qla2xxx_slave_alloc(struct scsi_device *sdev) | |
1da177e4 | 1389 | { |
bdf79621 | 1390 | struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); |
1da177e4 | 1391 | |
19a7b4ae | 1392 | if (!rport || fc_remote_port_chkready(rport)) |
f4f051eb | 1393 | return -ENXIO; |
bdf79621 | 1394 | |
19a7b4ae | 1395 | sdev->hostdata = *(fc_port_t **)rport->dd_data; |
1da177e4 | 1396 | |
f4f051eb AV |
1397 | return 0; |
1398 | } | |
1da177e4 | 1399 | |
f4f051eb AV |
1400 | static int |
1401 | qla2xxx_slave_configure(struct scsi_device *sdev) | |
1402 | { | |
e315cd28 | 1403 | scsi_qla_host_t *vha = shost_priv(sdev->host); |
2afa19a9 | 1404 | struct req_que *req = vha->req; |
8482e118 | 1405 | |
9e522cd8 AE |
1406 | if (IS_T10_PI_CAPABLE(vha->hw)) |
1407 | blk_queue_update_dma_alignment(sdev->request_queue, 0x7); | |
1408 | ||
db5ed4df | 1409 | scsi_change_queue_depth(sdev, req->max_q_depth); |
f4f051eb AV |
1410 | return 0; |
1411 | } | |
1da177e4 | 1412 | |
f4f051eb AV |
1413 | static void |
1414 | qla2xxx_slave_destroy(struct scsi_device *sdev) | |
1415 | { | |
1416 | sdev->hostdata = NULL; | |
1da177e4 LT |
1417 | } |
1418 | ||
1419 | /** | |
1420 | * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. | |
1421 | * @ha: HA context | |
1422 | * | |
1423 | * At exit, the @ha's flags.enable_64bit_addressing set to indicated | |
1424 | * supported addressing method. | |
1425 | */ | |
1426 | static void | |
53303c42 | 1427 | qla2x00_config_dma_addressing(struct qla_hw_data *ha) |
1da177e4 | 1428 | { |
7524f9b9 | 1429 | /* Assume a 32bit DMA mask. */ |
1da177e4 | 1430 | ha->flags.enable_64bit_addressing = 0; |
1da177e4 | 1431 | |
6a35528a | 1432 | if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { |
7524f9b9 AV |
1433 | /* Any upper-dword bits set? */ |
1434 | if (MSD(dma_get_required_mask(&ha->pdev->dev)) && | |
6a35528a | 1435 | !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) { |
7524f9b9 | 1436 | /* Ok, a 64bit DMA mask is applicable. */ |
1da177e4 | 1437 | ha->flags.enable_64bit_addressing = 1; |
fd34f556 AV |
1438 | ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; |
1439 | ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; | |
7524f9b9 | 1440 | return; |
1da177e4 | 1441 | } |
1da177e4 | 1442 | } |
7524f9b9 | 1443 | |
284901a9 YH |
1444 | dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); |
1445 | pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32)); | |
1da177e4 LT |
1446 | } |
1447 | ||
fd34f556 | 1448 | static void |
e315cd28 | 1449 | qla2x00_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1450 | { |
1451 | unsigned long flags = 0; | |
1452 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1453 | ||
1454 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1455 | ha->interrupts_on = 1; | |
1456 | /* enable risc and host interrupts */ | |
1457 | WRT_REG_WORD(®->ictrl, ICR_EN_INT | ICR_EN_RISC); | |
1458 | RD_REG_WORD(®->ictrl); | |
1459 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1460 | ||
1461 | } | |
1462 | ||
1463 | static void | |
e315cd28 | 1464 | qla2x00_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1465 | { |
1466 | unsigned long flags = 0; | |
1467 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | |
1468 | ||
1469 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1470 | ha->interrupts_on = 0; | |
1471 | /* disable risc and host interrupts */ | |
1472 | WRT_REG_WORD(®->ictrl, 0); | |
1473 | RD_REG_WORD(®->ictrl); | |
1474 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1475 | } | |
1476 | ||
1477 | static void | |
e315cd28 | 1478 | qla24xx_enable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1479 | { |
1480 | unsigned long flags = 0; | |
1481 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1482 | ||
1483 | spin_lock_irqsave(&ha->hardware_lock, flags); | |
1484 | ha->interrupts_on = 1; | |
1485 | WRT_REG_DWORD(®->ictrl, ICRX_EN_RISC_INT); | |
1486 | RD_REG_DWORD(®->ictrl); | |
1487 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1488 | } | |
1489 | ||
1490 | static void | |
e315cd28 | 1491 | qla24xx_disable_intrs(struct qla_hw_data *ha) |
fd34f556 AV |
1492 | { |
1493 | unsigned long flags = 0; | |
1494 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | |
1495 | ||
124f85e6 AV |
1496 | if (IS_NOPOLLING_TYPE(ha)) |
1497 | return; | |
fd34f556 AV |
1498 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1499 | ha->interrupts_on = 0; | |
1500 | WRT_REG_DWORD(®->ictrl, 0); | |
1501 | RD_REG_DWORD(®->ictrl); | |
1502 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
1503 | } | |
1504 | ||
706f457d GM |
1505 | static int |
1506 | qla2x00_iospace_config(struct qla_hw_data *ha) | |
1507 | { | |
1508 | resource_size_t pio; | |
1509 | uint16_t msix; | |
1510 | int cpus; | |
1511 | ||
706f457d GM |
1512 | if (pci_request_selected_regions(ha->pdev, ha->bars, |
1513 | QLA2XXX_DRIVER_NAME)) { | |
1514 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, | |
1515 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1516 | pci_name(ha->pdev)); | |
1517 | goto iospace_error_exit; | |
1518 | } | |
1519 | if (!(ha->bars & 1)) | |
1520 | goto skip_pio; | |
1521 | ||
1522 | /* We only need PIO for Flash operations on ISP2312 v2 chips. */ | |
1523 | pio = pci_resource_start(ha->pdev, 0); | |
1524 | if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { | |
1525 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1526 | ql_log_pci(ql_log_warn, ha->pdev, 0x0012, | |
1527 | "Invalid pci I/O region size (%s).\n", | |
1528 | pci_name(ha->pdev)); | |
1529 | pio = 0; | |
1530 | } | |
1531 | } else { | |
1532 | ql_log_pci(ql_log_warn, ha->pdev, 0x0013, | |
1533 | "Region #0 no a PIO resource (%s).\n", | |
1534 | pci_name(ha->pdev)); | |
1535 | pio = 0; | |
1536 | } | |
1537 | ha->pio_address = pio; | |
1538 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, | |
1539 | "PIO address=%llu.\n", | |
1540 | (unsigned long long)ha->pio_address); | |
1541 | ||
1542 | skip_pio: | |
1543 | /* Use MMIO operations for all accesses. */ | |
1544 | if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { | |
1545 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, | |
1546 | "Region #1 not an MMIO resource (%s), aborting.\n", | |
1547 | pci_name(ha->pdev)); | |
1548 | goto iospace_error_exit; | |
1549 | } | |
1550 | if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { | |
1551 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, | |
1552 | "Invalid PCI mem region size (%s), aborting.\n", | |
1553 | pci_name(ha->pdev)); | |
1554 | goto iospace_error_exit; | |
1555 | } | |
1556 | ||
1557 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); | |
1558 | if (!ha->iobase) { | |
1559 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, | |
1560 | "Cannot remap MMIO (%s), aborting.\n", | |
1561 | pci_name(ha->pdev)); | |
1562 | goto iospace_error_exit; | |
1563 | } | |
1564 | ||
1565 | /* Determine queue resources */ | |
1566 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1567 | if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) || | |
1568 | (ql2xmaxqueues > 1 && ql2xmultique_tag) || | |
1569 | (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) | |
1570 | goto mqiobase_exit; | |
1571 | ||
1572 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), | |
1573 | pci_resource_len(ha->pdev, 3)); | |
1574 | if (ha->mqiobase) { | |
1575 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, | |
1576 | "MQIO Base=%p.\n", ha->mqiobase); | |
1577 | /* Read MSIX vector size of the board */ | |
1578 | pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); | |
1579 | ha->msix_count = msix; | |
1580 | /* Max queues are bounded by available msix vectors */ | |
1581 | /* queue 0 uses two msix vectors */ | |
1582 | if (ql2xmultique_tag) { | |
1583 | cpus = num_online_cpus(); | |
1584 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1585 | (cpus + 1) : (ha->msix_count - 1); | |
1586 | ha->max_req_queues = 2; | |
1587 | } else if (ql2xmaxqueues > 1) { | |
1588 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1589 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1590 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008, | |
1591 | "QoS mode set, max no of request queues:%d.\n", | |
1592 | ha->max_req_queues); | |
1593 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019, | |
1594 | "QoS mode set, max no of request queues:%d.\n", | |
1595 | ha->max_req_queues); | |
1596 | } | |
1597 | ql_log_pci(ql_log_info, ha->pdev, 0x001a, | |
1598 | "MSI-X vector count: %d.\n", msix); | |
1599 | } else | |
1600 | ql_log_pci(ql_log_info, ha->pdev, 0x001b, | |
1601 | "BAR 3 not enabled.\n"); | |
1602 | ||
1603 | mqiobase_exit: | |
1604 | ha->msix_count = ha->max_rsp_queues + 1; | |
1605 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, | |
1606 | "MSIX Count:%d.\n", ha->msix_count); | |
1607 | return (0); | |
1608 | ||
1609 | iospace_error_exit: | |
1610 | return (-ENOMEM); | |
1611 | } | |
1612 | ||
1613 | ||
6246b8a1 GM |
1614 | static int |
1615 | qla83xx_iospace_config(struct qla_hw_data *ha) | |
1616 | { | |
1617 | uint16_t msix; | |
1618 | int cpus; | |
1619 | ||
1620 | if (pci_request_selected_regions(ha->pdev, ha->bars, | |
1621 | QLA2XXX_DRIVER_NAME)) { | |
1622 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, | |
1623 | "Failed to reserve PIO/MMIO regions (%s), aborting.\n", | |
1624 | pci_name(ha->pdev)); | |
1625 | ||
1626 | goto iospace_error_exit; | |
1627 | } | |
1628 | ||
1629 | /* Use MMIO operations for all accesses. */ | |
1630 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | |
1631 | ql_log_pci(ql_log_warn, ha->pdev, 0x0118, | |
1632 | "Invalid pci I/O region size (%s).\n", | |
1633 | pci_name(ha->pdev)); | |
1634 | goto iospace_error_exit; | |
1635 | } | |
1636 | if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { | |
1637 | ql_log_pci(ql_log_warn, ha->pdev, 0x0119, | |
1638 | "Invalid PCI mem region size (%s), aborting\n", | |
1639 | pci_name(ha->pdev)); | |
1640 | goto iospace_error_exit; | |
1641 | } | |
1642 | ||
1643 | ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); | |
1644 | if (!ha->iobase) { | |
1645 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, | |
1646 | "Cannot remap MMIO (%s), aborting.\n", | |
1647 | pci_name(ha->pdev)); | |
1648 | goto iospace_error_exit; | |
1649 | } | |
1650 | ||
1651 | /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ | |
1652 | /* 83XX 26XX always use MQ type access for queues | |
1653 | * - mbar 2, a.k.a region 4 */ | |
1654 | ha->max_req_queues = ha->max_rsp_queues = 1; | |
1655 | ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), | |
1656 | pci_resource_len(ha->pdev, 4)); | |
1657 | ||
1658 | if (!ha->mqiobase) { | |
1659 | ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, | |
1660 | "BAR2/region4 not enabled\n"); | |
1661 | goto mqiobase_exit; | |
1662 | } | |
1663 | ||
1664 | ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), | |
1665 | pci_resource_len(ha->pdev, 2)); | |
1666 | if (ha->msixbase) { | |
1667 | /* Read MSIX vector size of the board */ | |
1668 | pci_read_config_word(ha->pdev, | |
1669 | QLA_83XX_PCI_MSIX_CONTROL, &msix); | |
1670 | ha->msix_count = msix; | |
1671 | /* Max queues are bounded by available msix vectors */ | |
1672 | /* queue 0 uses two msix vectors */ | |
1673 | if (ql2xmultique_tag) { | |
1674 | cpus = num_online_cpus(); | |
1675 | ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ? | |
1676 | (cpus + 1) : (ha->msix_count - 1); | |
1677 | ha->max_req_queues = 2; | |
1678 | } else if (ql2xmaxqueues > 1) { | |
1679 | ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ? | |
1680 | QLA_MQ_SIZE : ql2xmaxqueues; | |
1681 | ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c, | |
1682 | "QoS mode set, max no of request queues:%d.\n", | |
1683 | ha->max_req_queues); | |
1684 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, | |
1685 | "QoS mode set, max no of request queues:%d.\n", | |
1686 | ha->max_req_queues); | |
1687 | } | |
1688 | ql_log_pci(ql_log_info, ha->pdev, 0x011c, | |
1689 | "MSI-X vector count: %d.\n", msix); | |
1690 | } else | |
1691 | ql_log_pci(ql_log_info, ha->pdev, 0x011e, | |
1692 | "BAR 1 not enabled.\n"); | |
1693 | ||
1694 | mqiobase_exit: | |
1695 | ha->msix_count = ha->max_rsp_queues + 1; | |
aa230bc5 AE |
1696 | |
1697 | qlt_83xx_iospace_config(ha); | |
1698 | ||
6246b8a1 GM |
1699 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, |
1700 | "MSIX Count:%d.\n", ha->msix_count); | |
1701 | return 0; | |
1702 | ||
1703 | iospace_error_exit: | |
1704 | return -ENOMEM; | |
1705 | } | |
1706 | ||
fd34f556 AV |
1707 | static struct isp_operations qla2100_isp_ops = { |
1708 | .pci_config = qla2100_pci_config, | |
1709 | .reset_chip = qla2x00_reset_chip, | |
1710 | .chip_diag = qla2x00_chip_diag, | |
1711 | .config_rings = qla2x00_config_rings, | |
1712 | .reset_adapter = qla2x00_reset_adapter, | |
1713 | .nvram_config = qla2x00_nvram_config, | |
1714 | .update_fw_options = qla2x00_update_fw_options, | |
1715 | .load_risc = qla2x00_load_risc, | |
1716 | .pci_info_str = qla2x00_pci_info_str, | |
1717 | .fw_version_str = qla2x00_fw_version_str, | |
1718 | .intr_handler = qla2100_intr_handler, | |
1719 | .enable_intrs = qla2x00_enable_intrs, | |
1720 | .disable_intrs = qla2x00_disable_intrs, | |
1721 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1722 | .target_reset = qla2x00_abort_target, |
1723 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1724 | .fabric_login = qla2x00_login_fabric, |
1725 | .fabric_logout = qla2x00_fabric_logout, | |
1726 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1727 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1728 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1729 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1730 | .read_nvram = qla2x00_read_nvram_data, | |
1731 | .write_nvram = qla2x00_write_nvram_data, | |
1732 | .fw_dump = qla2100_fw_dump, | |
1733 | .beacon_on = NULL, | |
1734 | .beacon_off = NULL, | |
1735 | .beacon_blink = NULL, | |
1736 | .read_optrom = qla2x00_read_optrom_data, | |
1737 | .write_optrom = qla2x00_write_optrom_data, | |
1738 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1739 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1740 | .abort_isp = qla2x00_abort_isp, |
706f457d | 1741 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1742 | .initialize_adapter = qla2x00_initialize_adapter, |
fd34f556 AV |
1743 | }; |
1744 | ||
1745 | static struct isp_operations qla2300_isp_ops = { | |
1746 | .pci_config = qla2300_pci_config, | |
1747 | .reset_chip = qla2x00_reset_chip, | |
1748 | .chip_diag = qla2x00_chip_diag, | |
1749 | .config_rings = qla2x00_config_rings, | |
1750 | .reset_adapter = qla2x00_reset_adapter, | |
1751 | .nvram_config = qla2x00_nvram_config, | |
1752 | .update_fw_options = qla2x00_update_fw_options, | |
1753 | .load_risc = qla2x00_load_risc, | |
1754 | .pci_info_str = qla2x00_pci_info_str, | |
1755 | .fw_version_str = qla2x00_fw_version_str, | |
1756 | .intr_handler = qla2300_intr_handler, | |
1757 | .enable_intrs = qla2x00_enable_intrs, | |
1758 | .disable_intrs = qla2x00_disable_intrs, | |
1759 | .abort_command = qla2x00_abort_command, | |
523ec773 AV |
1760 | .target_reset = qla2x00_abort_target, |
1761 | .lun_reset = qla2x00_lun_reset, | |
fd34f556 AV |
1762 | .fabric_login = qla2x00_login_fabric, |
1763 | .fabric_logout = qla2x00_fabric_logout, | |
1764 | .calc_req_entries = qla2x00_calc_iocbs_32, | |
1765 | .build_iocbs = qla2x00_build_scsi_iocbs_32, | |
1766 | .prep_ms_iocb = qla2x00_prep_ms_iocb, | |
1767 | .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, | |
1768 | .read_nvram = qla2x00_read_nvram_data, | |
1769 | .write_nvram = qla2x00_write_nvram_data, | |
1770 | .fw_dump = qla2300_fw_dump, | |
1771 | .beacon_on = qla2x00_beacon_on, | |
1772 | .beacon_off = qla2x00_beacon_off, | |
1773 | .beacon_blink = qla2x00_beacon_blink, | |
1774 | .read_optrom = qla2x00_read_optrom_data, | |
1775 | .write_optrom = qla2x00_write_optrom_data, | |
1776 | .get_flash_version = qla2x00_get_flash_version, | |
e315cd28 | 1777 | .start_scsi = qla2x00_start_scsi, |
a9083016 | 1778 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1779 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1780 | .initialize_adapter = qla2x00_initialize_adapter, |
fd34f556 AV |
1781 | }; |
1782 | ||
1783 | static struct isp_operations qla24xx_isp_ops = { | |
1784 | .pci_config = qla24xx_pci_config, | |
1785 | .reset_chip = qla24xx_reset_chip, | |
1786 | .chip_diag = qla24xx_chip_diag, | |
1787 | .config_rings = qla24xx_config_rings, | |
1788 | .reset_adapter = qla24xx_reset_adapter, | |
1789 | .nvram_config = qla24xx_nvram_config, | |
1790 | .update_fw_options = qla24xx_update_fw_options, | |
1791 | .load_risc = qla24xx_load_risc, | |
1792 | .pci_info_str = qla24xx_pci_info_str, | |
1793 | .fw_version_str = qla24xx_fw_version_str, | |
1794 | .intr_handler = qla24xx_intr_handler, | |
1795 | .enable_intrs = qla24xx_enable_intrs, | |
1796 | .disable_intrs = qla24xx_disable_intrs, | |
1797 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1798 | .target_reset = qla24xx_abort_target, |
1799 | .lun_reset = qla24xx_lun_reset, | |
fd34f556 AV |
1800 | .fabric_login = qla24xx_login_fabric, |
1801 | .fabric_logout = qla24xx_fabric_logout, | |
1802 | .calc_req_entries = NULL, | |
1803 | .build_iocbs = NULL, | |
1804 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1805 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1806 | .read_nvram = qla24xx_read_nvram_data, | |
1807 | .write_nvram = qla24xx_write_nvram_data, | |
1808 | .fw_dump = qla24xx_fw_dump, | |
1809 | .beacon_on = qla24xx_beacon_on, | |
1810 | .beacon_off = qla24xx_beacon_off, | |
1811 | .beacon_blink = qla24xx_beacon_blink, | |
1812 | .read_optrom = qla24xx_read_optrom_data, | |
1813 | .write_optrom = qla24xx_write_optrom_data, | |
1814 | .get_flash_version = qla24xx_get_flash_version, | |
e315cd28 | 1815 | .start_scsi = qla24xx_start_scsi, |
a9083016 | 1816 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1817 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1818 | .initialize_adapter = qla2x00_initialize_adapter, |
fd34f556 AV |
1819 | }; |
1820 | ||
c3a2f0df AV |
1821 | static struct isp_operations qla25xx_isp_ops = { |
1822 | .pci_config = qla25xx_pci_config, | |
1823 | .reset_chip = qla24xx_reset_chip, | |
1824 | .chip_diag = qla24xx_chip_diag, | |
1825 | .config_rings = qla24xx_config_rings, | |
1826 | .reset_adapter = qla24xx_reset_adapter, | |
1827 | .nvram_config = qla24xx_nvram_config, | |
1828 | .update_fw_options = qla24xx_update_fw_options, | |
1829 | .load_risc = qla24xx_load_risc, | |
1830 | .pci_info_str = qla24xx_pci_info_str, | |
1831 | .fw_version_str = qla24xx_fw_version_str, | |
1832 | .intr_handler = qla24xx_intr_handler, | |
1833 | .enable_intrs = qla24xx_enable_intrs, | |
1834 | .disable_intrs = qla24xx_disable_intrs, | |
1835 | .abort_command = qla24xx_abort_command, | |
523ec773 AV |
1836 | .target_reset = qla24xx_abort_target, |
1837 | .lun_reset = qla24xx_lun_reset, | |
c3a2f0df AV |
1838 | .fabric_login = qla24xx_login_fabric, |
1839 | .fabric_logout = qla24xx_fabric_logout, | |
1840 | .calc_req_entries = NULL, | |
1841 | .build_iocbs = NULL, | |
1842 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1843 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1844 | .read_nvram = qla25xx_read_nvram_data, | |
1845 | .write_nvram = qla25xx_write_nvram_data, | |
1846 | .fw_dump = qla25xx_fw_dump, | |
1847 | .beacon_on = qla24xx_beacon_on, | |
1848 | .beacon_off = qla24xx_beacon_off, | |
1849 | .beacon_blink = qla24xx_beacon_blink, | |
338c9161 | 1850 | .read_optrom = qla25xx_read_optrom_data, |
c3a2f0df AV |
1851 | .write_optrom = qla24xx_write_optrom_data, |
1852 | .get_flash_version = qla24xx_get_flash_version, | |
bad75002 | 1853 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 | 1854 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1855 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1856 | .initialize_adapter = qla2x00_initialize_adapter, |
c3a2f0df AV |
1857 | }; |
1858 | ||
3a03eb79 AV |
1859 | static struct isp_operations qla81xx_isp_ops = { |
1860 | .pci_config = qla25xx_pci_config, | |
1861 | .reset_chip = qla24xx_reset_chip, | |
1862 | .chip_diag = qla24xx_chip_diag, | |
1863 | .config_rings = qla24xx_config_rings, | |
1864 | .reset_adapter = qla24xx_reset_adapter, | |
1865 | .nvram_config = qla81xx_nvram_config, | |
1866 | .update_fw_options = qla81xx_update_fw_options, | |
eaac30be | 1867 | .load_risc = qla81xx_load_risc, |
3a03eb79 AV |
1868 | .pci_info_str = qla24xx_pci_info_str, |
1869 | .fw_version_str = qla24xx_fw_version_str, | |
1870 | .intr_handler = qla24xx_intr_handler, | |
1871 | .enable_intrs = qla24xx_enable_intrs, | |
1872 | .disable_intrs = qla24xx_disable_intrs, | |
1873 | .abort_command = qla24xx_abort_command, | |
1874 | .target_reset = qla24xx_abort_target, | |
1875 | .lun_reset = qla24xx_lun_reset, | |
1876 | .fabric_login = qla24xx_login_fabric, | |
1877 | .fabric_logout = qla24xx_fabric_logout, | |
1878 | .calc_req_entries = NULL, | |
1879 | .build_iocbs = NULL, | |
1880 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1881 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
3d79038f AV |
1882 | .read_nvram = NULL, |
1883 | .write_nvram = NULL, | |
3a03eb79 AV |
1884 | .fw_dump = qla81xx_fw_dump, |
1885 | .beacon_on = qla24xx_beacon_on, | |
1886 | .beacon_off = qla24xx_beacon_off, | |
6246b8a1 | 1887 | .beacon_blink = qla83xx_beacon_blink, |
3a03eb79 AV |
1888 | .read_optrom = qla25xx_read_optrom_data, |
1889 | .write_optrom = qla24xx_write_optrom_data, | |
1890 | .get_flash_version = qla24xx_get_flash_version, | |
ba77ef53 | 1891 | .start_scsi = qla24xx_dif_start_scsi, |
a9083016 | 1892 | .abort_isp = qla2x00_abort_isp, |
7ec0effd | 1893 | .iospace_config = qla2x00_iospace_config, |
8ae6d9c7 | 1894 | .initialize_adapter = qla2x00_initialize_adapter, |
a9083016 GM |
1895 | }; |
1896 | ||
1897 | static struct isp_operations qla82xx_isp_ops = { | |
1898 | .pci_config = qla82xx_pci_config, | |
1899 | .reset_chip = qla82xx_reset_chip, | |
1900 | .chip_diag = qla24xx_chip_diag, | |
1901 | .config_rings = qla82xx_config_rings, | |
1902 | .reset_adapter = qla24xx_reset_adapter, | |
1903 | .nvram_config = qla81xx_nvram_config, | |
1904 | .update_fw_options = qla24xx_update_fw_options, | |
1905 | .load_risc = qla82xx_load_risc, | |
9d55ca66 | 1906 | .pci_info_str = qla24xx_pci_info_str, |
a9083016 GM |
1907 | .fw_version_str = qla24xx_fw_version_str, |
1908 | .intr_handler = qla82xx_intr_handler, | |
1909 | .enable_intrs = qla82xx_enable_intrs, | |
1910 | .disable_intrs = qla82xx_disable_intrs, | |
1911 | .abort_command = qla24xx_abort_command, | |
1912 | .target_reset = qla24xx_abort_target, | |
1913 | .lun_reset = qla24xx_lun_reset, | |
1914 | .fabric_login = qla24xx_login_fabric, | |
1915 | .fabric_logout = qla24xx_fabric_logout, | |
1916 | .calc_req_entries = NULL, | |
1917 | .build_iocbs = NULL, | |
1918 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1919 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1920 | .read_nvram = qla24xx_read_nvram_data, | |
1921 | .write_nvram = qla24xx_write_nvram_data, | |
a1b23c5a | 1922 | .fw_dump = qla82xx_fw_dump, |
999916dc SK |
1923 | .beacon_on = qla82xx_beacon_on, |
1924 | .beacon_off = qla82xx_beacon_off, | |
1925 | .beacon_blink = NULL, | |
a9083016 GM |
1926 | .read_optrom = qla82xx_read_optrom_data, |
1927 | .write_optrom = qla82xx_write_optrom_data, | |
7ec0effd | 1928 | .get_flash_version = qla82xx_get_flash_version, |
a9083016 GM |
1929 | .start_scsi = qla82xx_start_scsi, |
1930 | .abort_isp = qla82xx_abort_isp, | |
706f457d | 1931 | .iospace_config = qla82xx_iospace_config, |
8ae6d9c7 | 1932 | .initialize_adapter = qla2x00_initialize_adapter, |
3a03eb79 AV |
1933 | }; |
1934 | ||
7ec0effd AD |
1935 | static struct isp_operations qla8044_isp_ops = { |
1936 | .pci_config = qla82xx_pci_config, | |
1937 | .reset_chip = qla82xx_reset_chip, | |
1938 | .chip_diag = qla24xx_chip_diag, | |
1939 | .config_rings = qla82xx_config_rings, | |
1940 | .reset_adapter = qla24xx_reset_adapter, | |
1941 | .nvram_config = qla81xx_nvram_config, | |
1942 | .update_fw_options = qla24xx_update_fw_options, | |
1943 | .load_risc = qla82xx_load_risc, | |
1944 | .pci_info_str = qla24xx_pci_info_str, | |
1945 | .fw_version_str = qla24xx_fw_version_str, | |
1946 | .intr_handler = qla8044_intr_handler, | |
1947 | .enable_intrs = qla82xx_enable_intrs, | |
1948 | .disable_intrs = qla82xx_disable_intrs, | |
1949 | .abort_command = qla24xx_abort_command, | |
1950 | .target_reset = qla24xx_abort_target, | |
1951 | .lun_reset = qla24xx_lun_reset, | |
1952 | .fabric_login = qla24xx_login_fabric, | |
1953 | .fabric_logout = qla24xx_fabric_logout, | |
1954 | .calc_req_entries = NULL, | |
1955 | .build_iocbs = NULL, | |
1956 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1957 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1958 | .read_nvram = NULL, | |
1959 | .write_nvram = NULL, | |
a1b23c5a | 1960 | .fw_dump = qla8044_fw_dump, |
7ec0effd AD |
1961 | .beacon_on = qla82xx_beacon_on, |
1962 | .beacon_off = qla82xx_beacon_off, | |
1963 | .beacon_blink = NULL, | |
888e639d | 1964 | .read_optrom = qla8044_read_optrom_data, |
7ec0effd AD |
1965 | .write_optrom = qla8044_write_optrom_data, |
1966 | .get_flash_version = qla82xx_get_flash_version, | |
1967 | .start_scsi = qla82xx_start_scsi, | |
1968 | .abort_isp = qla8044_abort_isp, | |
1969 | .iospace_config = qla82xx_iospace_config, | |
1970 | .initialize_adapter = qla2x00_initialize_adapter, | |
1971 | }; | |
1972 | ||
6246b8a1 GM |
1973 | static struct isp_operations qla83xx_isp_ops = { |
1974 | .pci_config = qla25xx_pci_config, | |
1975 | .reset_chip = qla24xx_reset_chip, | |
1976 | .chip_diag = qla24xx_chip_diag, | |
1977 | .config_rings = qla24xx_config_rings, | |
1978 | .reset_adapter = qla24xx_reset_adapter, | |
1979 | .nvram_config = qla81xx_nvram_config, | |
1980 | .update_fw_options = qla81xx_update_fw_options, | |
1981 | .load_risc = qla81xx_load_risc, | |
1982 | .pci_info_str = qla24xx_pci_info_str, | |
1983 | .fw_version_str = qla24xx_fw_version_str, | |
1984 | .intr_handler = qla24xx_intr_handler, | |
1985 | .enable_intrs = qla24xx_enable_intrs, | |
1986 | .disable_intrs = qla24xx_disable_intrs, | |
1987 | .abort_command = qla24xx_abort_command, | |
1988 | .target_reset = qla24xx_abort_target, | |
1989 | .lun_reset = qla24xx_lun_reset, | |
1990 | .fabric_login = qla24xx_login_fabric, | |
1991 | .fabric_logout = qla24xx_fabric_logout, | |
1992 | .calc_req_entries = NULL, | |
1993 | .build_iocbs = NULL, | |
1994 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
1995 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
1996 | .read_nvram = NULL, | |
1997 | .write_nvram = NULL, | |
1998 | .fw_dump = qla83xx_fw_dump, | |
1999 | .beacon_on = qla24xx_beacon_on, | |
2000 | .beacon_off = qla24xx_beacon_off, | |
2001 | .beacon_blink = qla83xx_beacon_blink, | |
2002 | .read_optrom = qla25xx_read_optrom_data, | |
2003 | .write_optrom = qla24xx_write_optrom_data, | |
2004 | .get_flash_version = qla24xx_get_flash_version, | |
2005 | .start_scsi = qla24xx_dif_start_scsi, | |
2006 | .abort_isp = qla2x00_abort_isp, | |
2007 | .iospace_config = qla83xx_iospace_config, | |
8ae6d9c7 GM |
2008 | .initialize_adapter = qla2x00_initialize_adapter, |
2009 | }; | |
2010 | ||
2011 | static struct isp_operations qlafx00_isp_ops = { | |
2012 | .pci_config = qlafx00_pci_config, | |
2013 | .reset_chip = qlafx00_soft_reset, | |
2014 | .chip_diag = qlafx00_chip_diag, | |
2015 | .config_rings = qlafx00_config_rings, | |
2016 | .reset_adapter = qlafx00_soft_reset, | |
2017 | .nvram_config = NULL, | |
2018 | .update_fw_options = NULL, | |
2019 | .load_risc = NULL, | |
2020 | .pci_info_str = qlafx00_pci_info_str, | |
2021 | .fw_version_str = qlafx00_fw_version_str, | |
2022 | .intr_handler = qlafx00_intr_handler, | |
2023 | .enable_intrs = qlafx00_enable_intrs, | |
2024 | .disable_intrs = qlafx00_disable_intrs, | |
4440e46d | 2025 | .abort_command = qla24xx_async_abort_command, |
8ae6d9c7 GM |
2026 | .target_reset = qlafx00_abort_target, |
2027 | .lun_reset = qlafx00_lun_reset, | |
2028 | .fabric_login = NULL, | |
2029 | .fabric_logout = NULL, | |
2030 | .calc_req_entries = NULL, | |
2031 | .build_iocbs = NULL, | |
2032 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2033 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2034 | .read_nvram = qla24xx_read_nvram_data, | |
2035 | .write_nvram = qla24xx_write_nvram_data, | |
2036 | .fw_dump = NULL, | |
2037 | .beacon_on = qla24xx_beacon_on, | |
2038 | .beacon_off = qla24xx_beacon_off, | |
2039 | .beacon_blink = NULL, | |
2040 | .read_optrom = qla24xx_read_optrom_data, | |
2041 | .write_optrom = qla24xx_write_optrom_data, | |
2042 | .get_flash_version = qla24xx_get_flash_version, | |
2043 | .start_scsi = qlafx00_start_scsi, | |
2044 | .abort_isp = qlafx00_abort_isp, | |
2045 | .iospace_config = qlafx00_iospace_config, | |
2046 | .initialize_adapter = qlafx00_initialize_adapter, | |
6246b8a1 GM |
2047 | }; |
2048 | ||
f73cb695 CD |
2049 | static struct isp_operations qla27xx_isp_ops = { |
2050 | .pci_config = qla25xx_pci_config, | |
2051 | .reset_chip = qla24xx_reset_chip, | |
2052 | .chip_diag = qla24xx_chip_diag, | |
2053 | .config_rings = qla24xx_config_rings, | |
2054 | .reset_adapter = qla24xx_reset_adapter, | |
2055 | .nvram_config = qla81xx_nvram_config, | |
2056 | .update_fw_options = qla81xx_update_fw_options, | |
2057 | .load_risc = qla81xx_load_risc, | |
2058 | .pci_info_str = qla24xx_pci_info_str, | |
2059 | .fw_version_str = qla24xx_fw_version_str, | |
2060 | .intr_handler = qla24xx_intr_handler, | |
2061 | .enable_intrs = qla24xx_enable_intrs, | |
2062 | .disable_intrs = qla24xx_disable_intrs, | |
2063 | .abort_command = qla24xx_abort_command, | |
2064 | .target_reset = qla24xx_abort_target, | |
2065 | .lun_reset = qla24xx_lun_reset, | |
2066 | .fabric_login = qla24xx_login_fabric, | |
2067 | .fabric_logout = qla24xx_fabric_logout, | |
2068 | .calc_req_entries = NULL, | |
2069 | .build_iocbs = NULL, | |
2070 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | |
2071 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | |
2072 | .read_nvram = NULL, | |
2073 | .write_nvram = NULL, | |
2074 | .fw_dump = qla27xx_fwdump, | |
2075 | .beacon_on = qla24xx_beacon_on, | |
2076 | .beacon_off = qla24xx_beacon_off, | |
2077 | .beacon_blink = qla83xx_beacon_blink, | |
2078 | .read_optrom = qla25xx_read_optrom_data, | |
2079 | .write_optrom = qla24xx_write_optrom_data, | |
2080 | .get_flash_version = qla24xx_get_flash_version, | |
2081 | .start_scsi = qla24xx_dif_start_scsi, | |
2082 | .abort_isp = qla2x00_abort_isp, | |
2083 | .iospace_config = qla83xx_iospace_config, | |
2084 | .initialize_adapter = qla2x00_initialize_adapter, | |
2085 | }; | |
2086 | ||
ea5b6382 | 2087 | static inline void |
e315cd28 | 2088 | qla2x00_set_isp_flags(struct qla_hw_data *ha) |
ea5b6382 AV |
2089 | { |
2090 | ha->device_type = DT_EXTENDED_IDS; | |
2091 | switch (ha->pdev->device) { | |
2092 | case PCI_DEVICE_ID_QLOGIC_ISP2100: | |
2093 | ha->device_type |= DT_ISP2100; | |
2094 | ha->device_type &= ~DT_EXTENDED_IDS; | |
441d1072 | 2095 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 AV |
2096 | break; |
2097 | case PCI_DEVICE_ID_QLOGIC_ISP2200: | |
2098 | ha->device_type |= DT_ISP2200; | |
2099 | ha->device_type &= ~DT_EXTENDED_IDS; | |
441d1072 | 2100 | ha->fw_srisc_address = RISC_START_ADDRESS_2100; |
ea5b6382 AV |
2101 | break; |
2102 | case PCI_DEVICE_ID_QLOGIC_ISP2300: | |
2103 | ha->device_type |= DT_ISP2300; | |
4a59f71d | 2104 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 2105 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
2106 | break; |
2107 | case PCI_DEVICE_ID_QLOGIC_ISP2312: | |
2108 | ha->device_type |= DT_ISP2312; | |
4a59f71d | 2109 | ha->device_type |= DT_ZIO_SUPPORTED; |
441d1072 | 2110 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
2111 | break; |
2112 | case PCI_DEVICE_ID_QLOGIC_ISP2322: | |
2113 | ha->device_type |= DT_ISP2322; | |
4a59f71d | 2114 | ha->device_type |= DT_ZIO_SUPPORTED; |
ea5b6382 AV |
2115 | if (ha->pdev->subsystem_vendor == 0x1028 && |
2116 | ha->pdev->subsystem_device == 0x0170) | |
2117 | ha->device_type |= DT_OEM_001; | |
441d1072 | 2118 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
2119 | break; |
2120 | case PCI_DEVICE_ID_QLOGIC_ISP6312: | |
2121 | ha->device_type |= DT_ISP6312; | |
441d1072 | 2122 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
2123 | break; |
2124 | case PCI_DEVICE_ID_QLOGIC_ISP6322: | |
2125 | ha->device_type |= DT_ISP6322; | |
441d1072 | 2126 | ha->fw_srisc_address = RISC_START_ADDRESS_2300; |
ea5b6382 AV |
2127 | break; |
2128 | case PCI_DEVICE_ID_QLOGIC_ISP2422: | |
2129 | ha->device_type |= DT_ISP2422; | |
4a59f71d | 2130 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 2131 | ha->device_type |= DT_FWI2; |
c76f2c01 | 2132 | ha->device_type |= DT_IIDMA; |
441d1072 | 2133 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 AV |
2134 | break; |
2135 | case PCI_DEVICE_ID_QLOGIC_ISP2432: | |
2136 | ha->device_type |= DT_ISP2432; | |
4a59f71d | 2137 | ha->device_type |= DT_ZIO_SUPPORTED; |
e428924c | 2138 | ha->device_type |= DT_FWI2; |
c76f2c01 | 2139 | ha->device_type |= DT_IIDMA; |
441d1072 | 2140 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2141 | break; |
4d4df193 HK |
2142 | case PCI_DEVICE_ID_QLOGIC_ISP8432: |
2143 | ha->device_type |= DT_ISP8432; | |
2144 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2145 | ha->device_type |= DT_FWI2; | |
2146 | ha->device_type |= DT_IIDMA; | |
2147 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2148 | break; | |
044cc6c8 AV |
2149 | case PCI_DEVICE_ID_QLOGIC_ISP5422: |
2150 | ha->device_type |= DT_ISP5422; | |
e428924c | 2151 | ha->device_type |= DT_FWI2; |
441d1072 | 2152 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2153 | break; |
044cc6c8 AV |
2154 | case PCI_DEVICE_ID_QLOGIC_ISP5432: |
2155 | ha->device_type |= DT_ISP5432; | |
e428924c | 2156 | ha->device_type |= DT_FWI2; |
441d1072 | 2157 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2158 | break; |
c3a2f0df AV |
2159 | case PCI_DEVICE_ID_QLOGIC_ISP2532: |
2160 | ha->device_type |= DT_ISP2532; | |
2161 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2162 | ha->device_type |= DT_FWI2; | |
2163 | ha->device_type |= DT_IIDMA; | |
441d1072 | 2164 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
ea5b6382 | 2165 | break; |
3a03eb79 AV |
2166 | case PCI_DEVICE_ID_QLOGIC_ISP8001: |
2167 | ha->device_type |= DT_ISP8001; | |
2168 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2169 | ha->device_type |= DT_FWI2; | |
2170 | ha->device_type |= DT_IIDMA; | |
2171 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2172 | break; | |
a9083016 GM |
2173 | case PCI_DEVICE_ID_QLOGIC_ISP8021: |
2174 | ha->device_type |= DT_ISP8021; | |
2175 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2176 | ha->device_type |= DT_FWI2; | |
2177 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2178 | /* Initialize 82XX ISP flags */ | |
2179 | qla82xx_init_flags(ha); | |
2180 | break; | |
7ec0effd AD |
2181 | case PCI_DEVICE_ID_QLOGIC_ISP8044: |
2182 | ha->device_type |= DT_ISP8044; | |
2183 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2184 | ha->device_type |= DT_FWI2; | |
2185 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2186 | /* Initialize 82XX ISP flags */ | |
2187 | qla82xx_init_flags(ha); | |
2188 | break; | |
6246b8a1 GM |
2189 | case PCI_DEVICE_ID_QLOGIC_ISP2031: |
2190 | ha->device_type |= DT_ISP2031; | |
2191 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2192 | ha->device_type |= DT_FWI2; | |
2193 | ha->device_type |= DT_IIDMA; | |
2194 | ha->device_type |= DT_T10_PI; | |
2195 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2196 | break; | |
2197 | case PCI_DEVICE_ID_QLOGIC_ISP8031: | |
2198 | ha->device_type |= DT_ISP8031; | |
2199 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2200 | ha->device_type |= DT_FWI2; | |
2201 | ha->device_type |= DT_IIDMA; | |
2202 | ha->device_type |= DT_T10_PI; | |
2203 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2204 | break; | |
8ae6d9c7 GM |
2205 | case PCI_DEVICE_ID_QLOGIC_ISPF001: |
2206 | ha->device_type |= DT_ISPFX00; | |
2207 | break; | |
f73cb695 CD |
2208 | case PCI_DEVICE_ID_QLOGIC_ISP2071: |
2209 | ha->device_type |= DT_ISP2071; | |
2210 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2211 | ha->device_type |= DT_FWI2; | |
2212 | ha->device_type |= DT_IIDMA; | |
2213 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2214 | break; | |
2c5bbbb2 JC |
2215 | case PCI_DEVICE_ID_QLOGIC_ISP2271: |
2216 | ha->device_type |= DT_ISP2271; | |
2217 | ha->device_type |= DT_ZIO_SUPPORTED; | |
2218 | ha->device_type |= DT_FWI2; | |
2219 | ha->device_type |= DT_IIDMA; | |
2220 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | |
2221 | break; | |
ea5b6382 | 2222 | } |
e5b68a61 | 2223 | |
a9083016 | 2224 | if (IS_QLA82XX(ha)) |
43a9c38b | 2225 | ha->port_no = ha->portnum & 1; |
f73cb695 | 2226 | else { |
a9083016 GM |
2227 | /* Get adapter physical port no from interrupt pin register. */ |
2228 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); | |
f73cb695 CD |
2229 | if (IS_QLA27XX(ha)) |
2230 | ha->port_no--; | |
2231 | else | |
2232 | ha->port_no = !(ha->port_no & 1); | |
2233 | } | |
a9083016 | 2234 | |
7c3df132 | 2235 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, |
d8424f68 | 2236 | "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", |
f73cb695 | 2237 | ha->device_type, ha->port_no, ha->fw_srisc_address); |
ea5b6382 AV |
2238 | } |
2239 | ||
1e99e33a AV |
2240 | static void |
2241 | qla2xxx_scan_start(struct Scsi_Host *shost) | |
2242 | { | |
e315cd28 | 2243 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 2244 | |
cbc8eb67 AV |
2245 | if (vha->hw->flags.running_gold_fw) |
2246 | return; | |
2247 | ||
e315cd28 AC |
2248 | set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); |
2249 | set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); | |
2250 | set_bit(RSCN_UPDATE, &vha->dpc_flags); | |
2251 | set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); | |
1e99e33a AV |
2252 | } |
2253 | ||
2254 | static int | |
2255 | qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) | |
2256 | { | |
e315cd28 | 2257 | scsi_qla_host_t *vha = shost_priv(shost); |
1e99e33a | 2258 | |
e315cd28 | 2259 | if (!vha->host) |
1e99e33a | 2260 | return 1; |
e315cd28 | 2261 | if (time > vha->hw->loop_reset_delay * HZ) |
1e99e33a AV |
2262 | return 1; |
2263 | ||
e315cd28 | 2264 | return atomic_read(&vha->loop_state) == LOOP_READY; |
1e99e33a AV |
2265 | } |
2266 | ||
1da177e4 LT |
2267 | /* |
2268 | * PCI driver interface | |
2269 | */ | |
6f039790 | 2270 | static int |
7ee61397 | 2271 | qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) |
1da177e4 | 2272 | { |
a1541d5a | 2273 | int ret = -ENODEV; |
1da177e4 | 2274 | struct Scsi_Host *host; |
e315cd28 AC |
2275 | scsi_qla_host_t *base_vha = NULL; |
2276 | struct qla_hw_data *ha; | |
29856e28 | 2277 | char pci_info[30]; |
7d613ac6 | 2278 | char fw_str[30], wq_name[30]; |
5433383e | 2279 | struct scsi_host_template *sht; |
642ef983 | 2280 | int bars, mem_only = 0; |
e315cd28 | 2281 | uint16_t req_length = 0, rsp_length = 0; |
73208dfd AC |
2282 | struct req_que *req = NULL; |
2283 | struct rsp_que *rsp = NULL; | |
285d0321 | 2284 | bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); |
a5326f86 | 2285 | sht = &qla2xxx_driver_template; |
5433383e | 2286 | if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || |
8bc69e7d | 2287 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || |
4d4df193 | 2288 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || |
8bc69e7d | 2289 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || |
c3a2f0df | 2290 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || |
3a03eb79 | 2291 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || |
a9083016 | 2292 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || |
6246b8a1 GM |
2293 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || |
2294 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || | |
8ae6d9c7 | 2295 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || |
7ec0effd | 2296 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || |
f73cb695 | 2297 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || |
2c5bbbb2 JC |
2298 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || |
2299 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271) { | |
285d0321 | 2300 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
09483916 | 2301 | mem_only = 1; |
7c3df132 SK |
2302 | ql_dbg_pci(ql_dbg_init, pdev, 0x0007, |
2303 | "Mem only adapter.\n"); | |
285d0321 | 2304 | } |
7c3df132 SK |
2305 | ql_dbg_pci(ql_dbg_init, pdev, 0x0008, |
2306 | "Bars=%d.\n", bars); | |
285d0321 | 2307 | |
09483916 BH |
2308 | if (mem_only) { |
2309 | if (pci_enable_device_mem(pdev)) | |
2310 | goto probe_out; | |
2311 | } else { | |
2312 | if (pci_enable_device(pdev)) | |
2313 | goto probe_out; | |
2314 | } | |
285d0321 | 2315 | |
0927678f JB |
2316 | /* This may fail but that's ok */ |
2317 | pci_enable_pcie_error_reporting(pdev); | |
285d0321 | 2318 | |
e315cd28 AC |
2319 | ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); |
2320 | if (!ha) { | |
7c3df132 SK |
2321 | ql_log_pci(ql_log_fatal, pdev, 0x0009, |
2322 | "Unable to allocate memory for ha.\n"); | |
e315cd28 | 2323 | goto probe_out; |
1da177e4 | 2324 | } |
7c3df132 SK |
2325 | ql_dbg_pci(ql_dbg_init, pdev, 0x000a, |
2326 | "Memory allocated for ha=%p.\n", ha); | |
e315cd28 | 2327 | ha->pdev = pdev; |
2d70c103 | 2328 | ha->tgt.enable_class_2 = ql2xenableclass2; |
33e79977 QT |
2329 | INIT_LIST_HEAD(&ha->tgt.q_full_list); |
2330 | spin_lock_init(&ha->tgt.q_full_lock); | |
1da177e4 LT |
2331 | |
2332 | /* Clear our data area */ | |
285d0321 | 2333 | ha->bars = bars; |
09483916 | 2334 | ha->mem_only = mem_only; |
df4bf0bb | 2335 | spin_lock_init(&ha->hardware_lock); |
339aa70e | 2336 | spin_lock_init(&ha->vport_slock); |
a9b6f722 | 2337 | mutex_init(&ha->selflogin_lock); |
7a8ab9c8 | 2338 | mutex_init(&ha->optrom_mutex); |
1da177e4 | 2339 | |
ea5b6382 AV |
2340 | /* Set ISP-type information. */ |
2341 | qla2x00_set_isp_flags(ha); | |
ca79cf66 DG |
2342 | |
2343 | /* Set EEH reset type to fundamental if required by hba */ | |
95676112 | 2344 | if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || |
f73cb695 | 2345 | IS_QLA83XX(ha) || IS_QLA27XX(ha)) |
ca79cf66 | 2346 | pdev->needs_freset = 1; |
ca79cf66 | 2347 | |
cba1e47f CD |
2348 | ha->prev_topology = 0; |
2349 | ha->init_cb_size = sizeof(init_cb_t); | |
2350 | ha->link_data_rate = PORT_SPEED_UNKNOWN; | |
2351 | ha->optrom_size = OPTROM_SIZE_2300; | |
2352 | ||
abbd8870 | 2353 | /* Assign ISP specific operations. */ |
1da177e4 | 2354 | if (IS_QLA2100(ha)) { |
642ef983 | 2355 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
1da177e4 | 2356 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; |
e315cd28 AC |
2357 | req_length = REQUEST_ENTRY_CNT_2100; |
2358 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2359 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2360 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2361 | ha->flash_conf_off = ~0; |
2362 | ha->flash_data_off = ~0; | |
2363 | ha->nvram_conf_off = ~0; | |
2364 | ha->nvram_data_off = ~0; | |
fd34f556 | 2365 | ha->isp_ops = &qla2100_isp_ops; |
1da177e4 | 2366 | } else if (IS_QLA2200(ha)) { |
642ef983 | 2367 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
67ddda35 | 2368 | ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; |
e315cd28 AC |
2369 | req_length = REQUEST_ENTRY_CNT_2200; |
2370 | rsp_length = RESPONSE_ENTRY_CNT_2100; | |
2371 | ha->max_loop_id = SNS_LAST_LOOP_ID_2100; | |
abbd8870 | 2372 | ha->gid_list_info_size = 4; |
3a03eb79 AV |
2373 | ha->flash_conf_off = ~0; |
2374 | ha->flash_data_off = ~0; | |
2375 | ha->nvram_conf_off = ~0; | |
2376 | ha->nvram_data_off = ~0; | |
fd34f556 | 2377 | ha->isp_ops = &qla2100_isp_ops; |
fca29703 | 2378 | } else if (IS_QLA23XX(ha)) { |
642ef983 | 2379 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; |
1da177e4 | 2380 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2381 | req_length = REQUEST_ENTRY_CNT_2200; |
2382 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2383 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
abbd8870 | 2384 | ha->gid_list_info_size = 6; |
854165f4 AV |
2385 | if (IS_QLA2322(ha) || IS_QLA6322(ha)) |
2386 | ha->optrom_size = OPTROM_SIZE_2322; | |
3a03eb79 AV |
2387 | ha->flash_conf_off = ~0; |
2388 | ha->flash_data_off = ~0; | |
2389 | ha->nvram_conf_off = ~0; | |
2390 | ha->nvram_data_off = ~0; | |
fd34f556 | 2391 | ha->isp_ops = &qla2300_isp_ops; |
4d4df193 | 2392 | } else if (IS_QLA24XX_TYPE(ha)) { |
642ef983 | 2393 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
fca29703 | 2394 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2395 | req_length = REQUEST_ENTRY_CNT_24XX; |
2396 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2d70c103 | 2397 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
e315cd28 | 2398 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2c3dfe3f | 2399 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
fca29703 | 2400 | ha->gid_list_info_size = 8; |
854165f4 | 2401 | ha->optrom_size = OPTROM_SIZE_24XX; |
73208dfd | 2402 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; |
fd34f556 | 2403 | ha->isp_ops = &qla24xx_isp_ops; |
3a03eb79 AV |
2404 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2405 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2406 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2407 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
c3a2f0df | 2408 | } else if (IS_QLA25XX(ha)) { |
642ef983 | 2409 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
c3a2f0df | 2410 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
e315cd28 AC |
2411 | req_length = REQUEST_ENTRY_CNT_24XX; |
2412 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
2d70c103 | 2413 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
e315cd28 | 2414 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
c3a2f0df | 2415 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); |
c3a2f0df AV |
2416 | ha->gid_list_info_size = 8; |
2417 | ha->optrom_size = OPTROM_SIZE_25XX; | |
73208dfd | 2418 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
c3a2f0df | 2419 | ha->isp_ops = &qla25xx_isp_ops; |
3a03eb79 AV |
2420 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; |
2421 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2422 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2423 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
2424 | } else if (IS_QLA81XX(ha)) { | |
642ef983 | 2425 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
3a03eb79 AV |
2426 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
2427 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2428 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
aa230bc5 | 2429 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
3a03eb79 AV |
2430 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2431 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2432 | ha->gid_list_info_size = 8; | |
2433 | ha->optrom_size = OPTROM_SIZE_81XX; | |
40859ae5 | 2434 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
3a03eb79 AV |
2435 | ha->isp_ops = &qla81xx_isp_ops; |
2436 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2437 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2438 | ha->nvram_conf_off = ~0; | |
2439 | ha->nvram_data_off = ~0; | |
a9083016 | 2440 | } else if (IS_QLA82XX(ha)) { |
642ef983 | 2441 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
a9083016 GM |
2442 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
2443 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2444 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2445 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2446 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2447 | ha->gid_list_info_size = 8; | |
2448 | ha->optrom_size = OPTROM_SIZE_82XX; | |
087c621e | 2449 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; |
a9083016 GM |
2450 | ha->isp_ops = &qla82xx_isp_ops; |
2451 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2452 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2453 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2454 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
7ec0effd AD |
2455 | } else if (IS_QLA8044(ha)) { |
2456 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2457 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2458 | req_length = REQUEST_ENTRY_CNT_82XX; | |
2459 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | |
2460 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | |
2461 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2462 | ha->gid_list_info_size = 8; | |
2463 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2464 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2465 | ha->isp_ops = &qla8044_isp_ops; | |
2466 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | |
2467 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | |
2468 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | |
2469 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | |
6246b8a1 | 2470 | } else if (IS_QLA83XX(ha)) { |
7d613ac6 | 2471 | ha->portnum = PCI_FUNC(ha->pdev->devfn); |
642ef983 | 2472 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; |
6246b8a1 | 2473 | ha->mbx_count = MAILBOX_REGISTER_COUNT; |
f2ea653f | 2474 | req_length = REQUEST_ENTRY_CNT_83XX; |
6246b8a1 | 2475 | rsp_length = RESPONSE_ENTRY_CNT_2300; |
b8aa4bdf | 2476 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
6246b8a1 GM |
2477 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2478 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2479 | ha->gid_list_info_size = 8; | |
2480 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2481 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2482 | ha->isp_ops = &qla83xx_isp_ops; | |
2483 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2484 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2485 | ha->nvram_conf_off = ~0; | |
2486 | ha->nvram_data_off = ~0; | |
8ae6d9c7 GM |
2487 | } else if (IS_QLAFX00(ha)) { |
2488 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; | |
2489 | ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; | |
2490 | ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; | |
2491 | req_length = REQUEST_ENTRY_CNT_FX00; | |
2492 | rsp_length = RESPONSE_ENTRY_CNT_FX00; | |
8ae6d9c7 GM |
2493 | ha->isp_ops = &qlafx00_isp_ops; |
2494 | ha->port_down_retry_count = 30; /* default value */ | |
2495 | ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; | |
2496 | ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; | |
71e56003 | 2497 | ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; |
8ae6d9c7 | 2498 | ha->mr.fw_hbt_en = 1; |
e8f5e95d AB |
2499 | ha->mr.host_info_resend = false; |
2500 | ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; | |
f73cb695 CD |
2501 | } else if (IS_QLA27XX(ha)) { |
2502 | ha->portnum = PCI_FUNC(ha->pdev->devfn); | |
2503 | ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; | |
2504 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | |
2505 | req_length = REQUEST_ENTRY_CNT_24XX; | |
2506 | rsp_length = RESPONSE_ENTRY_CNT_2300; | |
b20f02e1 | 2507 | ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; |
f73cb695 CD |
2508 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; |
2509 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | |
2510 | ha->gid_list_info_size = 8; | |
2511 | ha->optrom_size = OPTROM_SIZE_83XX; | |
2512 | ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; | |
2513 | ha->isp_ops = &qla27xx_isp_ops; | |
2514 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; | |
2515 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | |
2516 | ha->nvram_conf_off = ~0; | |
2517 | ha->nvram_data_off = ~0; | |
1da177e4 | 2518 | } |
6246b8a1 | 2519 | |
7c3df132 SK |
2520 | ql_dbg_pci(ql_dbg_init, pdev, 0x001e, |
2521 | "mbx_count=%d, req_length=%d, " | |
2522 | "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " | |
642ef983 CD |
2523 | "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " |
2524 | "max_fibre_devices=%d.\n", | |
7c3df132 SK |
2525 | ha->mbx_count, req_length, rsp_length, ha->max_loop_id, |
2526 | ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, | |
642ef983 | 2527 | ha->nvram_npiv_size, ha->max_fibre_devices); |
7c3df132 SK |
2528 | ql_dbg_pci(ql_dbg_init, pdev, 0x001f, |
2529 | "isp_ops=%p, flash_conf_off=%d, " | |
2530 | "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", | |
2531 | ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, | |
2532 | ha->nvram_conf_off, ha->nvram_data_off); | |
706f457d GM |
2533 | |
2534 | /* Configure PCI I/O space */ | |
2535 | ret = ha->isp_ops->iospace_config(ha); | |
2536 | if (ret) | |
0a63ad12 | 2537 | goto iospace_config_failed; |
706f457d GM |
2538 | |
2539 | ql_log_pci(ql_log_info, pdev, 0x001d, | |
2540 | "Found an ISP%04X irq %d iobase 0x%p.\n", | |
2541 | pdev->device, pdev->irq, ha->iobase); | |
6c2f527c | 2542 | mutex_init(&ha->vport_lock); |
0b05a1f0 MB |
2543 | init_completion(&ha->mbx_cmd_comp); |
2544 | complete(&ha->mbx_cmd_comp); | |
2545 | init_completion(&ha->mbx_intr_comp); | |
23f2ebd1 | 2546 | init_completion(&ha->dcbx_comp); |
f356bef1 | 2547 | init_completion(&ha->lb_portup_comp); |
1da177e4 | 2548 | |
2c3dfe3f | 2549 | set_bit(0, (unsigned long *) ha->vp_idx_map); |
1da177e4 | 2550 | |
53303c42 | 2551 | qla2x00_config_dma_addressing(ha); |
7c3df132 SK |
2552 | ql_dbg_pci(ql_dbg_init, pdev, 0x0020, |
2553 | "64 Bit addressing is %s.\n", | |
2554 | ha->flags.enable_64bit_addressing ? "enable" : | |
2555 | "disable"); | |
73208dfd | 2556 | ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); |
b2a72ec3 | 2557 | if (ret) { |
7c3df132 SK |
2558 | ql_log_pci(ql_log_fatal, pdev, 0x0031, |
2559 | "Failed to allocate memory for adapter, aborting.\n"); | |
1da177e4 | 2560 | |
e315cd28 AC |
2561 | goto probe_hw_failed; |
2562 | } | |
2563 | ||
73208dfd | 2564 | req->max_q_depth = MAX_Q_DEPTH; |
e315cd28 | 2565 | if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) |
73208dfd AC |
2566 | req->max_q_depth = ql2xmaxqdepth; |
2567 | ||
e315cd28 AC |
2568 | |
2569 | base_vha = qla2x00_create_host(sht, ha); | |
2570 | if (!base_vha) { | |
a1541d5a | 2571 | ret = -ENOMEM; |
6e9f21f3 | 2572 | qla2x00_mem_free(ha); |
2afa19a9 AC |
2573 | qla2x00_free_req_que(ha, req); |
2574 | qla2x00_free_rsp_que(ha, rsp); | |
e315cd28 | 2575 | goto probe_hw_failed; |
1da177e4 LT |
2576 | } |
2577 | ||
e315cd28 | 2578 | pci_set_drvdata(pdev, base_vha); |
6b383979 | 2579 | set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); |
e315cd28 | 2580 | |
e315cd28 | 2581 | host = base_vha->host; |
2afa19a9 | 2582 | base_vha->req = req; |
73208dfd | 2583 | if (IS_QLA2XXX_MIDTYPE(ha)) |
e315cd28 | 2584 | base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx; |
73208dfd | 2585 | else |
e315cd28 AC |
2586 | base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + |
2587 | base_vha->vp_idx; | |
58548cb5 | 2588 | |
8ae6d9c7 GM |
2589 | /* Setup fcport template structure. */ |
2590 | ha->mr.fcport.vha = base_vha; | |
2591 | ha->mr.fcport.port_type = FCT_UNKNOWN; | |
2592 | ha->mr.fcport.loop_id = FC_NO_LOOP_ID; | |
2593 | qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); | |
2594 | ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; | |
2595 | ha->mr.fcport.scan_state = 1; | |
2596 | ||
58548cb5 GM |
2597 | /* Set the SG table size based on ISP type */ |
2598 | if (!IS_FWI2_CAPABLE(ha)) { | |
2599 | if (IS_QLA2100(ha)) | |
2600 | host->sg_tablesize = 32; | |
2601 | } else { | |
2602 | if (!IS_QLA82XX(ha)) | |
2603 | host->sg_tablesize = QLA_SG_ALL; | |
2604 | } | |
642ef983 | 2605 | host->max_id = ha->max_fibre_devices; |
e315cd28 AC |
2606 | host->cmd_per_lun = 3; |
2607 | host->unique_id = host->host_no; | |
e02587d7 | 2608 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) |
0c470874 AE |
2609 | host->max_cmd_len = 32; |
2610 | else | |
2611 | host->max_cmd_len = MAX_CMDSZ; | |
e315cd28 | 2612 | host->max_channel = MAX_BUSES - 1; |
755f516b HR |
2613 | /* Older HBAs support only 16-bit LUNs */ |
2614 | if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && | |
2615 | ql2xmaxlun > 0xffff) | |
2616 | host->max_lun = 0xffff; | |
2617 | else | |
2618 | host->max_lun = ql2xmaxlun; | |
e315cd28 | 2619 | host->transportt = qla2xxx_transport_template; |
9a069e19 | 2620 | sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); |
e315cd28 | 2621 | |
7c3df132 SK |
2622 | ql_dbg(ql_dbg_init, base_vha, 0x0033, |
2623 | "max_id=%d this_id=%d " | |
2624 | "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " | |
1abf635d | 2625 | "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, |
7c3df132 SK |
2626 | host->this_id, host->cmd_per_lun, host->unique_id, |
2627 | host->max_cmd_len, host->max_channel, host->max_lun, | |
2628 | host->transportt, sht->vendor_id); | |
2629 | ||
9a347ff4 CD |
2630 | que_init: |
2631 | /* Alloc arrays of request and response ring ptrs */ | |
2632 | if (!qla2x00_alloc_queues(ha, req, rsp)) { | |
2633 | ql_log(ql_log_fatal, base_vha, 0x003d, | |
2634 | "Failed to allocate memory for queue pointers..." | |
2635 | "aborting.\n"); | |
2636 | goto probe_init_failed; | |
2637 | } | |
2638 | ||
2d70c103 | 2639 | qlt_probe_one_stage1(base_vha, ha); |
9a347ff4 | 2640 | |
73208dfd AC |
2641 | /* Set up the irqs */ |
2642 | ret = qla2x00_request_irqs(ha, rsp); | |
2643 | if (ret) | |
6e9f21f3 | 2644 | goto probe_init_failed; |
90a86fc0 JC |
2645 | |
2646 | pci_save_state(pdev); | |
2647 | ||
9a347ff4 | 2648 | /* Assign back pointers */ |
2afa19a9 AC |
2649 | rsp->req = req; |
2650 | req->rsp = rsp; | |
9a347ff4 | 2651 | |
8ae6d9c7 GM |
2652 | if (IS_QLAFX00(ha)) { |
2653 | ha->rsp_q_map[0] = rsp; | |
2654 | ha->req_q_map[0] = req; | |
2655 | set_bit(0, ha->req_qid_map); | |
2656 | set_bit(0, ha->rsp_qid_map); | |
2657 | } | |
2658 | ||
08029990 AV |
2659 | /* FWI2-capable only. */ |
2660 | req->req_q_in = &ha->iobase->isp24.req_q_in; | |
2661 | req->req_q_out = &ha->iobase->isp24.req_q_out; | |
2662 | rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; | |
2663 | rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; | |
f73cb695 | 2664 | if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) { |
08029990 AV |
2665 | req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; |
2666 | req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; | |
2667 | rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; | |
2668 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; | |
17d98630 AC |
2669 | } |
2670 | ||
8ae6d9c7 GM |
2671 | if (IS_QLAFX00(ha)) { |
2672 | req->req_q_in = &ha->iobase->ispfx00.req_q_in; | |
2673 | req->req_q_out = &ha->iobase->ispfx00.req_q_out; | |
2674 | rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; | |
2675 | rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; | |
2676 | } | |
2677 | ||
7ec0effd | 2678 | if (IS_P3P_TYPE(ha)) { |
a9083016 GM |
2679 | req->req_q_out = &ha->iobase->isp82.req_q_out[0]; |
2680 | rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; | |
2681 | rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; | |
2682 | } | |
2683 | ||
7c3df132 SK |
2684 | ql_dbg(ql_dbg_multiq, base_vha, 0xc009, |
2685 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2686 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2687 | ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, | |
2688 | "req->req_q_in=%p req->req_q_out=%p " | |
2689 | "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2690 | req->req_q_in, req->req_q_out, | |
2691 | rsp->rsp_q_in, rsp->rsp_q_out); | |
2692 | ql_dbg(ql_dbg_init, base_vha, 0x003e, | |
2693 | "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", | |
2694 | ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); | |
2695 | ql_dbg(ql_dbg_init, base_vha, 0x003f, | |
2696 | "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", | |
2697 | req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); | |
1da177e4 | 2698 | |
8ae6d9c7 | 2699 | if (ha->isp_ops->initialize_adapter(base_vha)) { |
7c3df132 SK |
2700 | ql_log(ql_log_fatal, base_vha, 0x00d6, |
2701 | "Failed to initialize adapter - Adapter flags %x.\n", | |
2702 | base_vha->device_flags); | |
1da177e4 | 2703 | |
a9083016 GM |
2704 | if (IS_QLA82XX(ha)) { |
2705 | qla82xx_idc_lock(ha); | |
2706 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
7d613ac6 | 2707 | QLA8XXX_DEV_FAILED); |
a9083016 | 2708 | qla82xx_idc_unlock(ha); |
7c3df132 SK |
2709 | ql_log(ql_log_fatal, base_vha, 0x00d7, |
2710 | "HW State: FAILED.\n"); | |
7ec0effd AD |
2711 | } else if (IS_QLA8044(ha)) { |
2712 | qla8044_idc_lock(ha); | |
2713 | qla8044_wr_direct(base_vha, | |
2714 | QLA8044_CRB_DEV_STATE_INDEX, | |
2715 | QLA8XXX_DEV_FAILED); | |
2716 | qla8044_idc_unlock(ha); | |
2717 | ql_log(ql_log_fatal, base_vha, 0x0150, | |
2718 | "HW State: FAILED.\n"); | |
a9083016 GM |
2719 | } |
2720 | ||
a1541d5a | 2721 | ret = -ENODEV; |
1da177e4 LT |
2722 | goto probe_failed; |
2723 | } | |
2724 | ||
3b1bef64 CD |
2725 | if (IS_QLAFX00(ha)) |
2726 | host->can_queue = QLAFX00_MAX_CANQUEUE; | |
2727 | else | |
2728 | host->can_queue = req->num_outstanding_cmds - 10; | |
2729 | ||
2730 | ql_dbg(ql_dbg_init, base_vha, 0x0032, | |
2731 | "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", | |
2732 | host->can_queue, base_vha->req, | |
2733 | base_vha->mgmt_svr_loop_id, host->sg_tablesize); | |
2734 | ||
7163ea81 AC |
2735 | if (ha->mqenable) { |
2736 | if (qla25xx_setup_mode(base_vha)) { | |
7c3df132 SK |
2737 | ql_log(ql_log_warn, base_vha, 0x00ec, |
2738 | "Failed to create queues, falling back to single queue mode.\n"); | |
7163ea81 AC |
2739 | goto que_init; |
2740 | } | |
2741 | } | |
68ca949c | 2742 | |
cbc8eb67 AV |
2743 | if (ha->flags.running_gold_fw) |
2744 | goto skip_dpc; | |
2745 | ||
1da177e4 LT |
2746 | /* |
2747 | * Startup the kernel thread for this host adapter | |
2748 | */ | |
39a11240 | 2749 | ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, |
7c3df132 | 2750 | "%s_dpc", base_vha->host_str); |
39a11240 | 2751 | if (IS_ERR(ha->dpc_thread)) { |
7c3df132 SK |
2752 | ql_log(ql_log_fatal, base_vha, 0x00ed, |
2753 | "Failed to start DPC thread.\n"); | |
39a11240 | 2754 | ret = PTR_ERR(ha->dpc_thread); |
1da177e4 LT |
2755 | goto probe_failed; |
2756 | } | |
7c3df132 SK |
2757 | ql_dbg(ql_dbg_init, base_vha, 0x00ee, |
2758 | "DPC thread started successfully.\n"); | |
1da177e4 | 2759 | |
2d70c103 NB |
2760 | /* |
2761 | * If we're not coming up in initiator mode, we might sit for | |
2762 | * a while without waking up the dpc thread, which leads to a | |
2763 | * stuck process warning. So just kick the dpc once here and | |
2764 | * let the kthread start (and go back to sleep in qla2x00_do_dpc). | |
2765 | */ | |
2766 | qla2xxx_wake_dpc(base_vha); | |
2767 | ||
f3ddac19 CD |
2768 | INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); |
2769 | ||
81178772 SK |
2770 | if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { |
2771 | sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); | |
2772 | ha->dpc_lp_wq = create_singlethread_workqueue(wq_name); | |
2773 | INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); | |
2774 | ||
2775 | sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); | |
2776 | ha->dpc_hp_wq = create_singlethread_workqueue(wq_name); | |
2777 | INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); | |
2778 | INIT_WORK(&ha->idc_state_handler, | |
2779 | qla83xx_idc_state_handler_work); | |
2780 | INIT_WORK(&ha->nic_core_unrecoverable, | |
2781 | qla83xx_nic_core_unrecoverable_work); | |
2782 | } | |
2783 | ||
cbc8eb67 | 2784 | skip_dpc: |
e315cd28 AC |
2785 | list_add_tail(&base_vha->list, &ha->vp_list); |
2786 | base_vha->host->irq = ha->pdev->irq; | |
1da177e4 LT |
2787 | |
2788 | /* Initialized the timer */ | |
e315cd28 | 2789 | qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL); |
7c3df132 SK |
2790 | ql_dbg(ql_dbg_init, base_vha, 0x00ef, |
2791 | "Started qla2x00_timer with " | |
2792 | "interval=%d.\n", WATCH_INTERVAL); | |
2793 | ql_dbg(ql_dbg_init, base_vha, 0x00f0, | |
2794 | "Detected hba at address=%p.\n", | |
2795 | ha); | |
d19044c3 | 2796 | |
e02587d7 | 2797 | if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { |
bad75002 | 2798 | if (ha->fw_attributes & BIT_4) { |
9e522cd8 | 2799 | int prot = 0, guard; |
bad75002 | 2800 | base_vha->flags.difdix_supported = 1; |
7c3df132 SK |
2801 | ql_dbg(ql_dbg_init, base_vha, 0x00f1, |
2802 | "Registering for DIF/DIX type 1 and 3 protection.\n"); | |
8cb2049c AE |
2803 | if (ql2xenabledif == 1) |
2804 | prot = SHOST_DIX_TYPE0_PROTECTION; | |
bad75002 | 2805 | scsi_host_set_prot(host, |
8cb2049c | 2806 | prot | SHOST_DIF_TYPE1_PROTECTION |
0c470874 | 2807 | | SHOST_DIF_TYPE2_PROTECTION |
bad75002 AE |
2808 | | SHOST_DIF_TYPE3_PROTECTION |
2809 | | SHOST_DIX_TYPE1_PROTECTION | |
0c470874 | 2810 | | SHOST_DIX_TYPE2_PROTECTION |
bad75002 | 2811 | | SHOST_DIX_TYPE3_PROTECTION); |
9e522cd8 AE |
2812 | |
2813 | guard = SHOST_DIX_GUARD_CRC; | |
2814 | ||
2815 | if (IS_PI_IPGUARD_CAPABLE(ha) && | |
2816 | (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) | |
2817 | guard |= SHOST_DIX_GUARD_IP; | |
2818 | ||
2819 | scsi_host_set_guard(host, guard); | |
bad75002 AE |
2820 | } else |
2821 | base_vha->flags.difdix_supported = 0; | |
2822 | } | |
2823 | ||
a9083016 GM |
2824 | ha->isp_ops->enable_intrs(ha); |
2825 | ||
1fe19ee4 AB |
2826 | if (IS_QLAFX00(ha)) { |
2827 | ret = qlafx00_fx_disc(base_vha, | |
2828 | &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); | |
2829 | host->sg_tablesize = (ha->mr.extended_io_enabled) ? | |
2830 | QLA_SG_ALL : 128; | |
2831 | } | |
2832 | ||
a1541d5a AV |
2833 | ret = scsi_add_host(host, &pdev->dev); |
2834 | if (ret) | |
2835 | goto probe_failed; | |
2836 | ||
1486400f MR |
2837 | base_vha->flags.init_done = 1; |
2838 | base_vha->flags.online = 1; | |
edaa5c74 | 2839 | ha->prev_minidump_failed = 0; |
1486400f | 2840 | |
7c3df132 SK |
2841 | ql_dbg(ql_dbg_init, base_vha, 0x00f2, |
2842 | "Init done and hba is online.\n"); | |
2843 | ||
2d70c103 NB |
2844 | if (qla_ini_mode_enabled(base_vha)) |
2845 | scsi_scan_host(host); | |
2846 | else | |
2847 | ql_dbg(ql_dbg_init, base_vha, 0x0122, | |
2848 | "skipping scsi_scan_host() for non-initiator port\n"); | |
1e99e33a | 2849 | |
e315cd28 | 2850 | qla2x00_alloc_sysfs_attr(base_vha); |
a1541d5a | 2851 | |
8ae6d9c7 | 2852 | if (IS_QLAFX00(ha)) { |
8ae6d9c7 GM |
2853 | ret = qlafx00_fx_disc(base_vha, |
2854 | &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); | |
2855 | ||
2856 | /* Register system information */ | |
2857 | ret = qlafx00_fx_disc(base_vha, | |
2858 | &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); | |
2859 | } | |
2860 | ||
e315cd28 | 2861 | qla2x00_init_host_attr(base_vha); |
a1541d5a | 2862 | |
e315cd28 | 2863 | qla2x00_dfs_setup(base_vha); |
df613b96 | 2864 | |
03eb912a AB |
2865 | ql_log(ql_log_info, base_vha, 0x00fb, |
2866 | "QLogic %s - %s.\n", ha->model_number, ha->model_desc); | |
7c3df132 SK |
2867 | ql_log(ql_log_info, base_vha, 0x00fc, |
2868 | "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", | |
2869 | pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info), | |
2870 | pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', | |
2871 | base_vha->host_no, | |
df57caba | 2872 | ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); |
1da177e4 | 2873 | |
2d70c103 NB |
2874 | qlt_add_target(ha, base_vha); |
2875 | ||
6b383979 | 2876 | clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); |
1da177e4 LT |
2877 | return 0; |
2878 | ||
6e9f21f3 | 2879 | probe_init_failed: |
2afa19a9 | 2880 | qla2x00_free_req_que(ha, req); |
9a347ff4 CD |
2881 | ha->req_q_map[0] = NULL; |
2882 | clear_bit(0, ha->req_qid_map); | |
2afa19a9 | 2883 | qla2x00_free_rsp_que(ha, rsp); |
9a347ff4 CD |
2884 | ha->rsp_q_map[0] = NULL; |
2885 | clear_bit(0, ha->rsp_qid_map); | |
2afa19a9 | 2886 | ha->max_req_queues = ha->max_rsp_queues = 0; |
6e9f21f3 | 2887 | |
1da177e4 | 2888 | probe_failed: |
b9978769 AV |
2889 | if (base_vha->timer_active) |
2890 | qla2x00_stop_timer(base_vha); | |
2891 | base_vha->flags.online = 0; | |
2892 | if (ha->dpc_thread) { | |
2893 | struct task_struct *t = ha->dpc_thread; | |
2894 | ||
2895 | ha->dpc_thread = NULL; | |
2896 | kthread_stop(t); | |
2897 | } | |
2898 | ||
e315cd28 | 2899 | qla2x00_free_device(base_vha); |
1da177e4 | 2900 | |
e315cd28 | 2901 | scsi_host_put(base_vha->host); |
1da177e4 | 2902 | |
e315cd28 | 2903 | probe_hw_failed: |
1a2fbf18 JL |
2904 | qla2x00_clear_drv_active(ha); |
2905 | ||
0a63ad12 | 2906 | iospace_config_failed: |
7ec0effd | 2907 | if (IS_P3P_TYPE(ha)) { |
0a63ad12 | 2908 | if (!ha->nx_pcibase) |
f73cb695 | 2909 | iounmap((device_reg_t *)ha->nx_pcibase); |
a9083016 | 2910 | if (!ql2xdbwr) |
f73cb695 | 2911 | iounmap((device_reg_t *)ha->nxdb_wr_ptr); |
a9083016 GM |
2912 | } else { |
2913 | if (ha->iobase) | |
2914 | iounmap(ha->iobase); | |
8ae6d9c7 GM |
2915 | if (ha->cregbase) |
2916 | iounmap(ha->cregbase); | |
a9083016 | 2917 | } |
e315cd28 AC |
2918 | pci_release_selected_regions(ha->pdev, ha->bars); |
2919 | kfree(ha); | |
2920 | ha = NULL; | |
1da177e4 | 2921 | |
a1541d5a | 2922 | probe_out: |
e315cd28 | 2923 | pci_disable_device(pdev); |
a1541d5a | 2924 | return ret; |
1da177e4 | 2925 | } |
1da177e4 | 2926 | |
e30d1756 MI |
2927 | static void |
2928 | qla2x00_shutdown(struct pci_dev *pdev) | |
2929 | { | |
2930 | scsi_qla_host_t *vha; | |
2931 | struct qla_hw_data *ha; | |
2932 | ||
552f3f9a MI |
2933 | if (!atomic_read(&pdev->enable_cnt)) |
2934 | return; | |
2935 | ||
e30d1756 MI |
2936 | vha = pci_get_drvdata(pdev); |
2937 | ha = vha->hw; | |
2938 | ||
42479343 AB |
2939 | /* Notify ISPFX00 firmware */ |
2940 | if (IS_QLAFX00(ha)) | |
2941 | qlafx00_driver_shutdown(vha, 20); | |
2942 | ||
e30d1756 MI |
2943 | /* Turn-off FCE trace */ |
2944 | if (ha->flags.fce_enabled) { | |
2945 | qla2x00_disable_fce_trace(vha, NULL, NULL); | |
2946 | ha->flags.fce_enabled = 0; | |
2947 | } | |
2948 | ||
2949 | /* Turn-off EFT trace */ | |
2950 | if (ha->eft) | |
2951 | qla2x00_disable_eft_trace(vha); | |
2952 | ||
2953 | /* Stop currently executing firmware. */ | |
2954 | qla2x00_try_to_stop_firmware(vha); | |
2955 | ||
2956 | /* Turn adapter off line */ | |
2957 | vha->flags.online = 0; | |
2958 | ||
2959 | /* turn-off interrupts on the card */ | |
2960 | if (ha->interrupts_on) { | |
2961 | vha->flags.init_done = 0; | |
2962 | ha->isp_ops->disable_intrs(ha); | |
2963 | } | |
2964 | ||
2965 | qla2x00_free_irqs(vha); | |
2966 | ||
2967 | qla2x00_free_fw_dump(ha); | |
61d41f61 CD |
2968 | |
2969 | pci_disable_pcie_error_reporting(pdev); | |
2970 | pci_disable_device(pdev); | |
e30d1756 MI |
2971 | } |
2972 | ||
fe1b806f | 2973 | /* Deletes all the virtual ports for a given ha */ |
4c993f76 | 2974 | static void |
fe1b806f | 2975 | qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) |
1da177e4 | 2976 | { |
fe1b806f CD |
2977 | struct Scsi_Host *scsi_host; |
2978 | scsi_qla_host_t *vha; | |
feafb7b1 | 2979 | unsigned long flags; |
e315cd28 | 2980 | |
43ebf16d AE |
2981 | mutex_lock(&ha->vport_lock); |
2982 | while (ha->cur_vport_count) { | |
43ebf16d | 2983 | spin_lock_irqsave(&ha->vport_slock, flags); |
feafb7b1 | 2984 | |
43ebf16d AE |
2985 | BUG_ON(base_vha->list.next == &ha->vp_list); |
2986 | /* This assumes first entry in ha->vp_list is always base vha */ | |
2987 | vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); | |
fe1b806f | 2988 | scsi_host = scsi_host_get(vha->host); |
feafb7b1 | 2989 | |
43ebf16d AE |
2990 | spin_unlock_irqrestore(&ha->vport_slock, flags); |
2991 | mutex_unlock(&ha->vport_lock); | |
2992 | ||
2993 | fc_vport_terminate(vha->fc_vport); | |
2994 | scsi_host_put(vha->host); | |
feafb7b1 | 2995 | |
43ebf16d | 2996 | mutex_lock(&ha->vport_lock); |
e315cd28 | 2997 | } |
43ebf16d | 2998 | mutex_unlock(&ha->vport_lock); |
fe1b806f | 2999 | } |
1da177e4 | 3000 | |
fe1b806f CD |
3001 | /* Stops all deferred work threads */ |
3002 | static void | |
3003 | qla2x00_destroy_deferred_work(struct qla_hw_data *ha) | |
3004 | { | |
68ca949c AC |
3005 | /* Flush the work queue and remove it */ |
3006 | if (ha->wq) { | |
3007 | flush_workqueue(ha->wq); | |
3008 | destroy_workqueue(ha->wq); | |
3009 | ha->wq = NULL; | |
3010 | } | |
3011 | ||
7d613ac6 SV |
3012 | /* Cancel all work and destroy DPC workqueues */ |
3013 | if (ha->dpc_lp_wq) { | |
3014 | cancel_work_sync(&ha->idc_aen); | |
3015 | destroy_workqueue(ha->dpc_lp_wq); | |
3016 | ha->dpc_lp_wq = NULL; | |
3017 | } | |
3018 | ||
3019 | if (ha->dpc_hp_wq) { | |
3020 | cancel_work_sync(&ha->nic_core_reset); | |
3021 | cancel_work_sync(&ha->idc_state_handler); | |
3022 | cancel_work_sync(&ha->nic_core_unrecoverable); | |
3023 | destroy_workqueue(ha->dpc_hp_wq); | |
3024 | ha->dpc_hp_wq = NULL; | |
3025 | } | |
3026 | ||
b9978769 AV |
3027 | /* Kill the kernel thread for this host */ |
3028 | if (ha->dpc_thread) { | |
3029 | struct task_struct *t = ha->dpc_thread; | |
3030 | ||
3031 | /* | |
3032 | * qla2xxx_wake_dpc checks for ->dpc_thread | |
3033 | * so we need to zero it out. | |
3034 | */ | |
3035 | ha->dpc_thread = NULL; | |
3036 | kthread_stop(t); | |
3037 | } | |
fe1b806f | 3038 | } |
1da177e4 | 3039 | |
fe1b806f CD |
3040 | static void |
3041 | qla2x00_unmap_iobases(struct qla_hw_data *ha) | |
3042 | { | |
a9083016 | 3043 | if (IS_QLA82XX(ha)) { |
b963752f | 3044 | |
f73cb695 | 3045 | iounmap((device_reg_t *)ha->nx_pcibase); |
a9083016 | 3046 | if (!ql2xdbwr) |
f73cb695 | 3047 | iounmap((device_reg_t *)ha->nxdb_wr_ptr); |
a9083016 GM |
3048 | } else { |
3049 | if (ha->iobase) | |
3050 | iounmap(ha->iobase); | |
1da177e4 | 3051 | |
8ae6d9c7 GM |
3052 | if (ha->cregbase) |
3053 | iounmap(ha->cregbase); | |
3054 | ||
a9083016 GM |
3055 | if (ha->mqiobase) |
3056 | iounmap(ha->mqiobase); | |
6246b8a1 | 3057 | |
f73cb695 | 3058 | if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase) |
6246b8a1 | 3059 | iounmap(ha->msixbase); |
a9083016 | 3060 | } |
fe1b806f CD |
3061 | } |
3062 | ||
3063 | static void | |
db7157d4 | 3064 | qla2x00_clear_drv_active(struct qla_hw_data *ha) |
fe1b806f | 3065 | { |
fe1b806f CD |
3066 | if (IS_QLA8044(ha)) { |
3067 | qla8044_idc_lock(ha); | |
c41afc9a | 3068 | qla8044_clear_drv_active(ha); |
fe1b806f CD |
3069 | qla8044_idc_unlock(ha); |
3070 | } else if (IS_QLA82XX(ha)) { | |
3071 | qla82xx_idc_lock(ha); | |
3072 | qla82xx_clear_drv_active(ha); | |
3073 | qla82xx_idc_unlock(ha); | |
3074 | } | |
3075 | } | |
3076 | ||
3077 | static void | |
3078 | qla2x00_remove_one(struct pci_dev *pdev) | |
3079 | { | |
3080 | scsi_qla_host_t *base_vha; | |
3081 | struct qla_hw_data *ha; | |
3082 | ||
beb9e315 JL |
3083 | base_vha = pci_get_drvdata(pdev); |
3084 | ha = base_vha->hw; | |
3085 | ||
3086 | /* Indicate device removal to prevent future board_disable and wait | |
3087 | * until any pending board_disable has completed. */ | |
3088 | set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); | |
3089 | cancel_work_sync(&ha->board_disable); | |
3090 | ||
fe1b806f | 3091 | /* |
beb9e315 JL |
3092 | * If the PCI device is disabled then there was a PCI-disconnect and |
3093 | * qla2x00_disable_board_on_pci_error has taken care of most of the | |
3094 | * resources. | |
fe1b806f | 3095 | */ |
beb9e315 JL |
3096 | if (!atomic_read(&pdev->enable_cnt)) { |
3097 | scsi_host_put(base_vha->host); | |
3098 | kfree(ha); | |
3099 | pci_set_drvdata(pdev, NULL); | |
fe1b806f | 3100 | return; |
beb9e315 | 3101 | } |
fe1b806f | 3102 | |
638a1a01 SC |
3103 | qla2x00_wait_for_hba_ready(base_vha); |
3104 | ||
fe1b806f CD |
3105 | set_bit(UNLOADING, &base_vha->dpc_flags); |
3106 | ||
3107 | if (IS_QLAFX00(ha)) | |
3108 | qlafx00_driver_shutdown(base_vha, 20); | |
3109 | ||
3110 | qla2x00_delete_all_vps(ha, base_vha); | |
3111 | ||
3112 | if (IS_QLA8031(ha)) { | |
3113 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, | |
3114 | "Clearing fcoe driver presence.\n"); | |
3115 | if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) | |
3116 | ql_dbg(ql_dbg_p3p, base_vha, 0xb079, | |
3117 | "Error while clearing DRV-Presence.\n"); | |
3118 | } | |
3119 | ||
3120 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
3121 | ||
3122 | qla2x00_dfs_remove(base_vha); | |
3123 | ||
3124 | qla84xx_put_chip(base_vha); | |
3125 | ||
2d5a4c34 HM |
3126 | /* Laser should be disabled only for ISP2031 */ |
3127 | if (IS_QLA2031(ha)) | |
3128 | qla83xx_disable_laser(base_vha); | |
3129 | ||
fe1b806f CD |
3130 | /* Disable timer */ |
3131 | if (base_vha->timer_active) | |
3132 | qla2x00_stop_timer(base_vha); | |
3133 | ||
3134 | base_vha->flags.online = 0; | |
3135 | ||
3136 | qla2x00_destroy_deferred_work(ha); | |
3137 | ||
3138 | qlt_remove_target(ha, base_vha); | |
3139 | ||
3140 | qla2x00_free_sysfs_attr(base_vha, true); | |
3141 | ||
3142 | fc_remove_host(base_vha->host); | |
3143 | ||
3144 | scsi_remove_host(base_vha->host); | |
3145 | ||
3146 | qla2x00_free_device(base_vha); | |
3147 | ||
db7157d4 | 3148 | qla2x00_clear_drv_active(ha); |
fe1b806f | 3149 | |
d2749ffa AE |
3150 | scsi_host_put(base_vha->host); |
3151 | ||
fe1b806f | 3152 | qla2x00_unmap_iobases(ha); |
73208dfd | 3153 | |
e315cd28 AC |
3154 | pci_release_selected_regions(ha->pdev, ha->bars); |
3155 | kfree(ha); | |
3156 | ha = NULL; | |
1da177e4 | 3157 | |
90a86fc0 JC |
3158 | pci_disable_pcie_error_reporting(pdev); |
3159 | ||
665db93b | 3160 | pci_disable_device(pdev); |
1da177e4 | 3161 | } |
1da177e4 LT |
3162 | |
3163 | static void | |
e315cd28 | 3164 | qla2x00_free_device(scsi_qla_host_t *vha) |
1da177e4 | 3165 | { |
e315cd28 | 3166 | struct qla_hw_data *ha = vha->hw; |
1da177e4 | 3167 | |
85880801 AV |
3168 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); |
3169 | ||
3170 | /* Disable timer */ | |
3171 | if (vha->timer_active) | |
3172 | qla2x00_stop_timer(vha); | |
3173 | ||
2afa19a9 | 3174 | qla25xx_delete_queues(vha); |
fe1b806f | 3175 | |
df613b96 | 3176 | if (ha->flags.fce_enabled) |
e315cd28 | 3177 | qla2x00_disable_fce_trace(vha, NULL, NULL); |
df613b96 | 3178 | |
a7a167bf | 3179 | if (ha->eft) |
e315cd28 | 3180 | qla2x00_disable_eft_trace(vha); |
a7a167bf | 3181 | |
f6ef3b18 | 3182 | /* Stop currently executing firmware. */ |
e315cd28 | 3183 | qla2x00_try_to_stop_firmware(vha); |
1da177e4 | 3184 | |
85880801 AV |
3185 | vha->flags.online = 0; |
3186 | ||
f6ef3b18 | 3187 | /* turn-off interrupts on the card */ |
a9083016 GM |
3188 | if (ha->interrupts_on) { |
3189 | vha->flags.init_done = 0; | |
fd34f556 | 3190 | ha->isp_ops->disable_intrs(ha); |
a9083016 | 3191 | } |
f6ef3b18 | 3192 | |
e315cd28 | 3193 | qla2x00_free_irqs(vha); |
1da177e4 | 3194 | |
8867048b CD |
3195 | qla2x00_free_fcports(vha); |
3196 | ||
e315cd28 | 3197 | qla2x00_mem_free(ha); |
73208dfd | 3198 | |
08de2844 GM |
3199 | qla82xx_md_free(vha); |
3200 | ||
73208dfd | 3201 | qla2x00_free_queues(ha); |
1da177e4 LT |
3202 | } |
3203 | ||
8867048b CD |
3204 | void qla2x00_free_fcports(struct scsi_qla_host *vha) |
3205 | { | |
3206 | fc_port_t *fcport, *tfcport; | |
3207 | ||
3208 | list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) { | |
3209 | list_del(&fcport->list); | |
5f16b331 | 3210 | qla2x00_clear_loop_id(fcport); |
8867048b CD |
3211 | kfree(fcport); |
3212 | fcport = NULL; | |
3213 | } | |
3214 | } | |
3215 | ||
d97994dc | 3216 | static inline void |
e315cd28 | 3217 | qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport, |
d97994dc AV |
3218 | int defer) |
3219 | { | |
d97994dc | 3220 | struct fc_rport *rport; |
67becc00 | 3221 | scsi_qla_host_t *base_vha; |
044d78e1 | 3222 | unsigned long flags; |
d97994dc AV |
3223 | |
3224 | if (!fcport->rport) | |
3225 | return; | |
3226 | ||
3227 | rport = fcport->rport; | |
3228 | if (defer) { | |
67becc00 | 3229 | base_vha = pci_get_drvdata(vha->hw->pdev); |
044d78e1 | 3230 | spin_lock_irqsave(vha->host->host_lock, flags); |
d97994dc | 3231 | fcport->drport = rport; |
044d78e1 | 3232 | spin_unlock_irqrestore(vha->host->host_lock, flags); |
df673274 | 3233 | qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen); |
67becc00 AV |
3234 | set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags); |
3235 | qla2xxx_wake_dpc(base_vha); | |
2d70c103 | 3236 | } else { |
df673274 | 3237 | int now; |
d20ed91b AP |
3238 | if (rport) |
3239 | fc_remote_port_delete(rport); | |
df673274 AP |
3240 | qlt_do_generation_tick(vha, &now); |
3241 | qlt_fc_port_deleted(vha, fcport, now); | |
2d70c103 | 3242 | } |
d97994dc AV |
3243 | } |
3244 | ||
1da177e4 LT |
3245 | /* |
3246 | * qla2x00_mark_device_lost Updates fcport state when device goes offline. | |
3247 | * | |
3248 | * Input: ha = adapter block pointer. fcport = port structure pointer. | |
3249 | * | |
3250 | * Return: None. | |
3251 | * | |
3252 | * Context: | |
3253 | */ | |
e315cd28 | 3254 | void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, |
d97994dc | 3255 | int do_login, int defer) |
1da177e4 | 3256 | { |
8ae6d9c7 GM |
3257 | if (IS_QLAFX00(vha->hw)) { |
3258 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); | |
3259 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
3260 | return; | |
3261 | } | |
3262 | ||
2c3dfe3f | 3263 | if (atomic_read(&fcport->state) == FCS_ONLINE && |
c6d39e23 | 3264 | vha->vp_idx == fcport->vha->vp_idx) { |
ec426e10 | 3265 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
e315cd28 AC |
3266 | qla2x00_schedule_rport_del(vha, fcport, defer); |
3267 | } | |
fa2a1ce5 | 3268 | /* |
1da177e4 LT |
3269 | * We may need to retry the login, so don't change the state of the |
3270 | * port but do the retries. | |
3271 | */ | |
3272 | if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) | |
ec426e10 | 3273 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
1da177e4 LT |
3274 | |
3275 | if (!do_login) | |
3276 | return; | |
3277 | ||
3278 | if (fcport->login_retry == 0) { | |
e315cd28 AC |
3279 | fcport->login_retry = vha->hw->login_retry_count; |
3280 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
1da177e4 | 3281 | |
7c3df132 | 3282 | ql_dbg(ql_dbg_disc, vha, 0x2067, |
7b833558 OK |
3283 | "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n", |
3284 | fcport->port_name, fcport->loop_id, fcport->login_retry); | |
1da177e4 LT |
3285 | } |
3286 | } | |
3287 | ||
3288 | /* | |
3289 | * qla2x00_mark_all_devices_lost | |
3290 | * Updates fcport state when device goes offline. | |
3291 | * | |
3292 | * Input: | |
3293 | * ha = adapter block pointer. | |
3294 | * fcport = port structure pointer. | |
3295 | * | |
3296 | * Return: | |
3297 | * None. | |
3298 | * | |
3299 | * Context: | |
3300 | */ | |
3301 | void | |
e315cd28 | 3302 | qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer) |
1da177e4 LT |
3303 | { |
3304 | fc_port_t *fcport; | |
3305 | ||
e315cd28 | 3306 | list_for_each_entry(fcport, &vha->vp_fcports, list) { |
c6d39e23 | 3307 | if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx) |
1da177e4 | 3308 | continue; |
0d6e61bc | 3309 | |
1da177e4 LT |
3310 | /* |
3311 | * No point in marking the device as lost, if the device is | |
3312 | * already DEAD. | |
3313 | */ | |
3314 | if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD) | |
3315 | continue; | |
e315cd28 | 3316 | if (atomic_read(&fcport->state) == FCS_ONLINE) { |
ec426e10 | 3317 | qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); |
0d6e61bc AV |
3318 | if (defer) |
3319 | qla2x00_schedule_rport_del(vha, fcport, defer); | |
c6d39e23 | 3320 | else if (vha->vp_idx == fcport->vha->vp_idx) |
0d6e61bc AV |
3321 | qla2x00_schedule_rport_del(vha, fcport, defer); |
3322 | } | |
1da177e4 LT |
3323 | } |
3324 | } | |
3325 | ||
3326 | /* | |
3327 | * qla2x00_mem_alloc | |
3328 | * Allocates adapter memory. | |
3329 | * | |
3330 | * Returns: | |
3331 | * 0 = success. | |
e8711085 | 3332 | * !0 = failure. |
1da177e4 | 3333 | */ |
e8711085 | 3334 | static int |
73208dfd AC |
3335 | qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, |
3336 | struct req_que **req, struct rsp_que **rsp) | |
1da177e4 LT |
3337 | { |
3338 | char name[16]; | |
1da177e4 | 3339 | |
e8711085 | 3340 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, |
e315cd28 | 3341 | &ha->init_cb_dma, GFP_KERNEL); |
e8711085 | 3342 | if (!ha->init_cb) |
e315cd28 | 3343 | goto fail; |
e8711085 | 3344 | |
2d70c103 NB |
3345 | if (qlt_mem_alloc(ha) < 0) |
3346 | goto fail_free_init_cb; | |
3347 | ||
642ef983 CD |
3348 | ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, |
3349 | qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); | |
e315cd28 | 3350 | if (!ha->gid_list) |
2d70c103 | 3351 | goto fail_free_tgt_mem; |
1da177e4 | 3352 | |
e8711085 AV |
3353 | ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); |
3354 | if (!ha->srb_mempool) | |
e315cd28 | 3355 | goto fail_free_gid_list; |
e8711085 | 3356 | |
7ec0effd | 3357 | if (IS_P3P_TYPE(ha)) { |
a9083016 GM |
3358 | /* Allocate cache for CT6 Ctx. */ |
3359 | if (!ctx_cachep) { | |
3360 | ctx_cachep = kmem_cache_create("qla2xxx_ctx", | |
3361 | sizeof(struct ct6_dsd), 0, | |
3362 | SLAB_HWCACHE_ALIGN, NULL); | |
3363 | if (!ctx_cachep) | |
3364 | goto fail_free_gid_list; | |
3365 | } | |
3366 | ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, | |
3367 | ctx_cachep); | |
3368 | if (!ha->ctx_mempool) | |
3369 | goto fail_free_srb_mempool; | |
7c3df132 SK |
3370 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, |
3371 | "ctx_cachep=%p ctx_mempool=%p.\n", | |
3372 | ctx_cachep, ha->ctx_mempool); | |
a9083016 GM |
3373 | } |
3374 | ||
e8711085 AV |
3375 | /* Get memory for cached NVRAM */ |
3376 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); | |
3377 | if (!ha->nvram) | |
a9083016 | 3378 | goto fail_free_ctx_mempool; |
e8711085 | 3379 | |
e315cd28 AC |
3380 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, |
3381 | ha->pdev->device); | |
3382 | ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3383 | DMA_POOL_SIZE, 8, 0); | |
3384 | if (!ha->s_dma_pool) | |
3385 | goto fail_free_nvram; | |
3386 | ||
7c3df132 SK |
3387 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, |
3388 | "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", | |
3389 | ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); | |
3390 | ||
7ec0effd | 3391 | if (IS_P3P_TYPE(ha) || ql2xenabledif) { |
a9083016 GM |
3392 | ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, |
3393 | DSD_LIST_DMA_POOL_SIZE, 8, 0); | |
3394 | if (!ha->dl_dma_pool) { | |
7c3df132 SK |
3395 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, |
3396 | "Failed to allocate memory for dl_dma_pool.\n"); | |
a9083016 GM |
3397 | goto fail_s_dma_pool; |
3398 | } | |
3399 | ||
3400 | ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, | |
3401 | FCP_CMND_DMA_POOL_SIZE, 8, 0); | |
3402 | if (!ha->fcp_cmnd_dma_pool) { | |
7c3df132 SK |
3403 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, |
3404 | "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); | |
a9083016 GM |
3405 | goto fail_dl_dma_pool; |
3406 | } | |
7c3df132 SK |
3407 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, |
3408 | "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n", | |
3409 | ha->dl_dma_pool, ha->fcp_cmnd_dma_pool); | |
a9083016 GM |
3410 | } |
3411 | ||
e8711085 AV |
3412 | /* Allocate memory for SNS commands */ |
3413 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | |
e315cd28 | 3414 | /* Get consistent memory allocated for SNS commands */ |
e8711085 | 3415 | ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 3416 | sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); |
e8711085 | 3417 | if (!ha->sns_cmd) |
e315cd28 | 3418 | goto fail_dma_pool; |
7c3df132 | 3419 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, |
d8424f68 | 3420 | "sns_cmd: %p.\n", ha->sns_cmd); |
e8711085 | 3421 | } else { |
e315cd28 | 3422 | /* Get consistent memory allocated for MS IOCB */ |
e8711085 | 3423 | ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
e315cd28 | 3424 | &ha->ms_iocb_dma); |
e8711085 | 3425 | if (!ha->ms_iocb) |
e315cd28 AC |
3426 | goto fail_dma_pool; |
3427 | /* Get consistent memory allocated for CT SNS commands */ | |
e8711085 | 3428 | ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, |
e315cd28 | 3429 | sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); |
e8711085 AV |
3430 | if (!ha->ct_sns) |
3431 | goto fail_free_ms_iocb; | |
7c3df132 SK |
3432 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, |
3433 | "ms_iocb=%p ct_sns=%p.\n", | |
3434 | ha->ms_iocb, ha->ct_sns); | |
1da177e4 LT |
3435 | } |
3436 | ||
e315cd28 | 3437 | /* Allocate memory for request ring */ |
73208dfd AC |
3438 | *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); |
3439 | if (!*req) { | |
7c3df132 SK |
3440 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, |
3441 | "Failed to allocate memory for req.\n"); | |
e315cd28 AC |
3442 | goto fail_req; |
3443 | } | |
73208dfd AC |
3444 | (*req)->length = req_len; |
3445 | (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3446 | ((*req)->length + 1) * sizeof(request_t), | |
3447 | &(*req)->dma, GFP_KERNEL); | |
3448 | if (!(*req)->ring) { | |
7c3df132 SK |
3449 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, |
3450 | "Failed to allocate memory for req_ring.\n"); | |
e315cd28 AC |
3451 | goto fail_req_ring; |
3452 | } | |
3453 | /* Allocate memory for response ring */ | |
73208dfd AC |
3454 | *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); |
3455 | if (!*rsp) { | |
7c3df132 SK |
3456 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, |
3457 | "Failed to allocate memory for rsp.\n"); | |
e315cd28 AC |
3458 | goto fail_rsp; |
3459 | } | |
73208dfd AC |
3460 | (*rsp)->hw = ha; |
3461 | (*rsp)->length = rsp_len; | |
3462 | (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, | |
3463 | ((*rsp)->length + 1) * sizeof(response_t), | |
3464 | &(*rsp)->dma, GFP_KERNEL); | |
3465 | if (!(*rsp)->ring) { | |
7c3df132 SK |
3466 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, |
3467 | "Failed to allocate memory for rsp_ring.\n"); | |
e315cd28 AC |
3468 | goto fail_rsp_ring; |
3469 | } | |
73208dfd AC |
3470 | (*req)->rsp = *rsp; |
3471 | (*rsp)->req = *req; | |
7c3df132 SK |
3472 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, |
3473 | "req=%p req->length=%d req->ring=%p rsp=%p " | |
3474 | "rsp->length=%d rsp->ring=%p.\n", | |
3475 | *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, | |
3476 | (*rsp)->ring); | |
73208dfd AC |
3477 | /* Allocate memory for NVRAM data for vports */ |
3478 | if (ha->nvram_npiv_size) { | |
3479 | ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) * | |
7c3df132 | 3480 | ha->nvram_npiv_size, GFP_KERNEL); |
73208dfd | 3481 | if (!ha->npiv_info) { |
7c3df132 SK |
3482 | ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, |
3483 | "Failed to allocate memory for npiv_info.\n"); | |
73208dfd AC |
3484 | goto fail_npiv_info; |
3485 | } | |
3486 | } else | |
3487 | ha->npiv_info = NULL; | |
e8711085 | 3488 | |
b64b0e8f | 3489 | /* Get consistent memory allocated for EX-INIT-CB. */ |
f73cb695 | 3490 | if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) { |
b64b0e8f AV |
3491 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
3492 | &ha->ex_init_cb_dma); | |
3493 | if (!ha->ex_init_cb) | |
3494 | goto fail_ex_init_cb; | |
7c3df132 SK |
3495 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, |
3496 | "ex_init_cb=%p.\n", ha->ex_init_cb); | |
b64b0e8f AV |
3497 | } |
3498 | ||
a9083016 GM |
3499 | INIT_LIST_HEAD(&ha->gbl_dsd_list); |
3500 | ||
5ff1d584 AV |
3501 | /* Get consistent memory allocated for Async Port-Database. */ |
3502 | if (!IS_FWI2_CAPABLE(ha)) { | |
3503 | ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | |
3504 | &ha->async_pd_dma); | |
3505 | if (!ha->async_pd) | |
3506 | goto fail_async_pd; | |
7c3df132 SK |
3507 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, |
3508 | "async_pd=%p.\n", ha->async_pd); | |
5ff1d584 AV |
3509 | } |
3510 | ||
e315cd28 | 3511 | INIT_LIST_HEAD(&ha->vp_list); |
5f16b331 CD |
3512 | |
3513 | /* Allocate memory for our loop_id bitmap */ | |
3514 | ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long), | |
3515 | GFP_KERNEL); | |
3516 | if (!ha->loop_id_map) | |
3517 | goto fail_async_pd; | |
3518 | else { | |
3519 | qla2x00_set_reserved_loop_ids(ha); | |
3520 | ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, | |
b2a72ec3 | 3521 | "loop_id_map=%p.\n", ha->loop_id_map); |
5f16b331 CD |
3522 | } |
3523 | ||
b2a72ec3 | 3524 | return 0; |
e315cd28 | 3525 | |
5ff1d584 AV |
3526 | fail_async_pd: |
3527 | dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f AV |
3528 | fail_ex_init_cb: |
3529 | kfree(ha->npiv_info); | |
73208dfd AC |
3530 | fail_npiv_info: |
3531 | dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * | |
3532 | sizeof(response_t), (*rsp)->ring, (*rsp)->dma); | |
3533 | (*rsp)->ring = NULL; | |
3534 | (*rsp)->dma = 0; | |
e315cd28 | 3535 | fail_rsp_ring: |
73208dfd | 3536 | kfree(*rsp); |
e315cd28 | 3537 | fail_rsp: |
73208dfd AC |
3538 | dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * |
3539 | sizeof(request_t), (*req)->ring, (*req)->dma); | |
3540 | (*req)->ring = NULL; | |
3541 | (*req)->dma = 0; | |
e315cd28 | 3542 | fail_req_ring: |
73208dfd | 3543 | kfree(*req); |
e315cd28 AC |
3544 | fail_req: |
3545 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
3546 | ha->ct_sns, ha->ct_sns_dma); | |
3547 | ha->ct_sns = NULL; | |
3548 | ha->ct_sns_dma = 0; | |
e8711085 AV |
3549 | fail_free_ms_iocb: |
3550 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3551 | ha->ms_iocb = NULL; | |
3552 | ha->ms_iocb_dma = 0; | |
e315cd28 | 3553 | fail_dma_pool: |
bad75002 | 3554 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
3555 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); |
3556 | ha->fcp_cmnd_dma_pool = NULL; | |
3557 | } | |
3558 | fail_dl_dma_pool: | |
bad75002 | 3559 | if (IS_QLA82XX(ha) || ql2xenabledif) { |
a9083016 GM |
3560 | dma_pool_destroy(ha->dl_dma_pool); |
3561 | ha->dl_dma_pool = NULL; | |
3562 | } | |
3563 | fail_s_dma_pool: | |
e315cd28 AC |
3564 | dma_pool_destroy(ha->s_dma_pool); |
3565 | ha->s_dma_pool = NULL; | |
e8711085 AV |
3566 | fail_free_nvram: |
3567 | kfree(ha->nvram); | |
3568 | ha->nvram = NULL; | |
a9083016 GM |
3569 | fail_free_ctx_mempool: |
3570 | mempool_destroy(ha->ctx_mempool); | |
3571 | ha->ctx_mempool = NULL; | |
e8711085 AV |
3572 | fail_free_srb_mempool: |
3573 | mempool_destroy(ha->srb_mempool); | |
3574 | ha->srb_mempool = NULL; | |
e8711085 | 3575 | fail_free_gid_list: |
642ef983 CD |
3576 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
3577 | ha->gid_list, | |
e315cd28 | 3578 | ha->gid_list_dma); |
e8711085 AV |
3579 | ha->gid_list = NULL; |
3580 | ha->gid_list_dma = 0; | |
2d70c103 NB |
3581 | fail_free_tgt_mem: |
3582 | qlt_mem_free(ha); | |
e315cd28 AC |
3583 | fail_free_init_cb: |
3584 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, | |
3585 | ha->init_cb_dma); | |
3586 | ha->init_cb = NULL; | |
3587 | ha->init_cb_dma = 0; | |
e8711085 | 3588 | fail: |
7c3df132 SK |
3589 | ql_log(ql_log_fatal, NULL, 0x0030, |
3590 | "Memory allocation failure.\n"); | |
e8711085 | 3591 | return -ENOMEM; |
1da177e4 LT |
3592 | } |
3593 | ||
3594 | /* | |
e30d1756 MI |
3595 | * qla2x00_free_fw_dump |
3596 | * Frees fw dump stuff. | |
1da177e4 LT |
3597 | * |
3598 | * Input: | |
7ec0effd | 3599 | * ha = adapter block pointer |
1da177e4 | 3600 | */ |
a824ebb3 | 3601 | static void |
e30d1756 | 3602 | qla2x00_free_fw_dump(struct qla_hw_data *ha) |
1da177e4 | 3603 | { |
df613b96 | 3604 | if (ha->fce) |
f73cb695 CD |
3605 | dma_free_coherent(&ha->pdev->dev, |
3606 | FCE_SIZE, ha->fce, ha->fce_dma); | |
df613b96 | 3607 | |
f73cb695 CD |
3608 | if (ha->eft) |
3609 | dma_free_coherent(&ha->pdev->dev, | |
3610 | EFT_SIZE, ha->eft, ha->eft_dma); | |
3611 | ||
3612 | if (ha->fw_dump) | |
a7a167bf | 3613 | vfree(ha->fw_dump); |
f73cb695 CD |
3614 | if (ha->fw_dump_template) |
3615 | vfree(ha->fw_dump_template); | |
3616 | ||
e30d1756 MI |
3617 | ha->fce = NULL; |
3618 | ha->fce_dma = 0; | |
3619 | ha->eft = NULL; | |
3620 | ha->eft_dma = 0; | |
e30d1756 | 3621 | ha->fw_dumped = 0; |
61f098dd | 3622 | ha->fw_dump_cap_flags = 0; |
e30d1756 | 3623 | ha->fw_dump_reading = 0; |
f73cb695 CD |
3624 | ha->fw_dump = NULL; |
3625 | ha->fw_dump_len = 0; | |
3626 | ha->fw_dump_template = NULL; | |
3627 | ha->fw_dump_template_len = 0; | |
e30d1756 MI |
3628 | } |
3629 | ||
3630 | /* | |
3631 | * qla2x00_mem_free | |
3632 | * Frees all adapter allocated memory. | |
3633 | * | |
3634 | * Input: | |
3635 | * ha = adapter block pointer. | |
3636 | */ | |
3637 | static void | |
3638 | qla2x00_mem_free(struct qla_hw_data *ha) | |
3639 | { | |
3640 | qla2x00_free_fw_dump(ha); | |
3641 | ||
81178772 SK |
3642 | if (ha->mctp_dump) |
3643 | dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, | |
3644 | ha->mctp_dump_dma); | |
3645 | ||
e30d1756 MI |
3646 | if (ha->srb_mempool) |
3647 | mempool_destroy(ha->srb_mempool); | |
a7a167bf | 3648 | |
11bbc1d8 AV |
3649 | if (ha->dcbx_tlv) |
3650 | dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, | |
3651 | ha->dcbx_tlv, ha->dcbx_tlv_dma); | |
3652 | ||
ce0423f4 AV |
3653 | if (ha->xgmac_data) |
3654 | dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, | |
3655 | ha->xgmac_data, ha->xgmac_data_dma); | |
3656 | ||
1da177e4 LT |
3657 | if (ha->sns_cmd) |
3658 | dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), | |
e315cd28 | 3659 | ha->sns_cmd, ha->sns_cmd_dma); |
1da177e4 LT |
3660 | |
3661 | if (ha->ct_sns) | |
3662 | dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), | |
e315cd28 | 3663 | ha->ct_sns, ha->ct_sns_dma); |
1da177e4 | 3664 | |
88729e53 AV |
3665 | if (ha->sfp_data) |
3666 | dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma); | |
3667 | ||
1da177e4 LT |
3668 | if (ha->ms_iocb) |
3669 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | |
3670 | ||
b64b0e8f | 3671 | if (ha->ex_init_cb) |
a9083016 GM |
3672 | dma_pool_free(ha->s_dma_pool, |
3673 | ha->ex_init_cb, ha->ex_init_cb_dma); | |
b64b0e8f | 3674 | |
5ff1d584 AV |
3675 | if (ha->async_pd) |
3676 | dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); | |
3677 | ||
1da177e4 LT |
3678 | if (ha->s_dma_pool) |
3679 | dma_pool_destroy(ha->s_dma_pool); | |
3680 | ||
1da177e4 | 3681 | if (ha->gid_list) |
642ef983 CD |
3682 | dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), |
3683 | ha->gid_list, ha->gid_list_dma); | |
1da177e4 | 3684 | |
a9083016 GM |
3685 | if (IS_QLA82XX(ha)) { |
3686 | if (!list_empty(&ha->gbl_dsd_list)) { | |
3687 | struct dsd_dma *dsd_ptr, *tdsd_ptr; | |
3688 | ||
3689 | /* clean up allocated prev pool */ | |
3690 | list_for_each_entry_safe(dsd_ptr, | |
3691 | tdsd_ptr, &ha->gbl_dsd_list, list) { | |
3692 | dma_pool_free(ha->dl_dma_pool, | |
3693 | dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); | |
3694 | list_del(&dsd_ptr->list); | |
3695 | kfree(dsd_ptr); | |
3696 | } | |
3697 | } | |
3698 | } | |
3699 | ||
3700 | if (ha->dl_dma_pool) | |
3701 | dma_pool_destroy(ha->dl_dma_pool); | |
3702 | ||
3703 | if (ha->fcp_cmnd_dma_pool) | |
3704 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | |
3705 | ||
3706 | if (ha->ctx_mempool) | |
3707 | mempool_destroy(ha->ctx_mempool); | |
3708 | ||
2d70c103 NB |
3709 | qlt_mem_free(ha); |
3710 | ||
e315cd28 AC |
3711 | if (ha->init_cb) |
3712 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, | |
a9083016 | 3713 | ha->init_cb, ha->init_cb_dma); |
e315cd28 AC |
3714 | vfree(ha->optrom_buffer); |
3715 | kfree(ha->nvram); | |
73208dfd | 3716 | kfree(ha->npiv_info); |
7a67735b | 3717 | kfree(ha->swl); |
5f16b331 | 3718 | kfree(ha->loop_id_map); |
1da177e4 | 3719 | |
e8711085 | 3720 | ha->srb_mempool = NULL; |
a9083016 | 3721 | ha->ctx_mempool = NULL; |
1da177e4 LT |
3722 | ha->sns_cmd = NULL; |
3723 | ha->sns_cmd_dma = 0; | |
3724 | ha->ct_sns = NULL; | |
3725 | ha->ct_sns_dma = 0; | |
3726 | ha->ms_iocb = NULL; | |
3727 | ha->ms_iocb_dma = 0; | |
1da177e4 LT |
3728 | ha->init_cb = NULL; |
3729 | ha->init_cb_dma = 0; | |
b64b0e8f AV |
3730 | ha->ex_init_cb = NULL; |
3731 | ha->ex_init_cb_dma = 0; | |
5ff1d584 AV |
3732 | ha->async_pd = NULL; |
3733 | ha->async_pd_dma = 0; | |
1da177e4 LT |
3734 | |
3735 | ha->s_dma_pool = NULL; | |
a9083016 GM |
3736 | ha->dl_dma_pool = NULL; |
3737 | ha->fcp_cmnd_dma_pool = NULL; | |
1da177e4 | 3738 | |
1da177e4 LT |
3739 | ha->gid_list = NULL; |
3740 | ha->gid_list_dma = 0; | |
2d70c103 NB |
3741 | |
3742 | ha->tgt.atio_ring = NULL; | |
3743 | ha->tgt.atio_dma = 0; | |
3744 | ha->tgt.tgt_vp_map = NULL; | |
e315cd28 | 3745 | } |
1da177e4 | 3746 | |
e315cd28 AC |
3747 | struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, |
3748 | struct qla_hw_data *ha) | |
3749 | { | |
3750 | struct Scsi_Host *host; | |
3751 | struct scsi_qla_host *vha = NULL; | |
854165f4 | 3752 | |
e315cd28 AC |
3753 | host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); |
3754 | if (host == NULL) { | |
7c3df132 SK |
3755 | ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, |
3756 | "Failed to allocate host from the scsi layer, aborting.\n"); | |
e315cd28 AC |
3757 | goto fail; |
3758 | } | |
3759 | ||
3760 | /* Clear our data area */ | |
3761 | vha = shost_priv(host); | |
3762 | memset(vha, 0, sizeof(scsi_qla_host_t)); | |
3763 | ||
3764 | vha->host = host; | |
3765 | vha->host_no = host->host_no; | |
3766 | vha->hw = ha; | |
3767 | ||
3768 | INIT_LIST_HEAD(&vha->vp_fcports); | |
3769 | INIT_LIST_HEAD(&vha->work_list); | |
3770 | INIT_LIST_HEAD(&vha->list); | |
8b2f5ff3 SN |
3771 | INIT_LIST_HEAD(&vha->qla_cmd_list); |
3772 | INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list); | |
e315cd28 | 3773 | |
f999f4c1 | 3774 | spin_lock_init(&vha->work_lock); |
8b2f5ff3 | 3775 | spin_lock_init(&vha->cmd_list_lock); |
f999f4c1 | 3776 | |
e315cd28 | 3777 | sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); |
7c3df132 SK |
3778 | ql_dbg(ql_dbg_init, vha, 0x0041, |
3779 | "Allocated the host=%p hw=%p vha=%p dev_name=%s", | |
3780 | vha->host, vha->hw, vha, | |
3781 | dev_name(&(ha->pdev->dev))); | |
3782 | ||
e315cd28 AC |
3783 | return vha; |
3784 | ||
3785 | fail: | |
3786 | return vha; | |
1da177e4 LT |
3787 | } |
3788 | ||
01ef66bb | 3789 | static struct qla_work_evt * |
f999f4c1 | 3790 | qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) |
0971de7f AV |
3791 | { |
3792 | struct qla_work_evt *e; | |
feafb7b1 AE |
3793 | uint8_t bail; |
3794 | ||
3795 | QLA_VHA_MARK_BUSY(vha, bail); | |
3796 | if (bail) | |
3797 | return NULL; | |
0971de7f | 3798 | |
f999f4c1 | 3799 | e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); |
feafb7b1 AE |
3800 | if (!e) { |
3801 | QLA_VHA_MARK_NOT_BUSY(vha); | |
0971de7f | 3802 | return NULL; |
feafb7b1 | 3803 | } |
0971de7f AV |
3804 | |
3805 | INIT_LIST_HEAD(&e->list); | |
3806 | e->type = type; | |
3807 | e->flags = QLA_EVT_FLAG_FREE; | |
3808 | return e; | |
3809 | } | |
3810 | ||
01ef66bb | 3811 | static int |
f999f4c1 | 3812 | qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) |
0971de7f | 3813 | { |
f999f4c1 | 3814 | unsigned long flags; |
0971de7f | 3815 | |
f999f4c1 | 3816 | spin_lock_irqsave(&vha->work_lock, flags); |
e315cd28 | 3817 | list_add_tail(&e->list, &vha->work_list); |
f999f4c1 | 3818 | spin_unlock_irqrestore(&vha->work_lock, flags); |
e315cd28 | 3819 | qla2xxx_wake_dpc(vha); |
f999f4c1 | 3820 | |
0971de7f AV |
3821 | return QLA_SUCCESS; |
3822 | } | |
3823 | ||
3824 | int | |
e315cd28 | 3825 | qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, |
0971de7f AV |
3826 | u32 data) |
3827 | { | |
3828 | struct qla_work_evt *e; | |
3829 | ||
f999f4c1 | 3830 | e = qla2x00_alloc_work(vha, QLA_EVT_AEN); |
0971de7f AV |
3831 | if (!e) |
3832 | return QLA_FUNCTION_FAILED; | |
3833 | ||
3834 | e->u.aen.code = code; | |
3835 | e->u.aen.data = data; | |
f999f4c1 | 3836 | return qla2x00_post_work(vha, e); |
0971de7f AV |
3837 | } |
3838 | ||
8a659571 AV |
3839 | int |
3840 | qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) | |
3841 | { | |
3842 | struct qla_work_evt *e; | |
3843 | ||
f999f4c1 | 3844 | e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); |
8a659571 AV |
3845 | if (!e) |
3846 | return QLA_FUNCTION_FAILED; | |
3847 | ||
3848 | memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); | |
f999f4c1 | 3849 | return qla2x00_post_work(vha, e); |
8a659571 AV |
3850 | } |
3851 | ||
ac280b67 AV |
3852 | #define qla2x00_post_async_work(name, type) \ |
3853 | int qla2x00_post_async_##name##_work( \ | |
3854 | struct scsi_qla_host *vha, \ | |
3855 | fc_port_t *fcport, uint16_t *data) \ | |
3856 | { \ | |
3857 | struct qla_work_evt *e; \ | |
3858 | \ | |
3859 | e = qla2x00_alloc_work(vha, type); \ | |
3860 | if (!e) \ | |
3861 | return QLA_FUNCTION_FAILED; \ | |
3862 | \ | |
3863 | e->u.logio.fcport = fcport; \ | |
3864 | if (data) { \ | |
3865 | e->u.logio.data[0] = data[0]; \ | |
3866 | e->u.logio.data[1] = data[1]; \ | |
3867 | } \ | |
3868 | return qla2x00_post_work(vha, e); \ | |
3869 | } | |
3870 | ||
3871 | qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); | |
3872 | qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE); | |
3873 | qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); | |
3874 | qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE); | |
5ff1d584 AV |
3875 | qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); |
3876 | qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE); | |
ac280b67 | 3877 | |
3420d36c AV |
3878 | int |
3879 | qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) | |
3880 | { | |
3881 | struct qla_work_evt *e; | |
3882 | ||
3883 | e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); | |
3884 | if (!e) | |
3885 | return QLA_FUNCTION_FAILED; | |
3886 | ||
3887 | e->u.uevent.code = code; | |
3888 | return qla2x00_post_work(vha, e); | |
3889 | } | |
3890 | ||
3891 | static void | |
3892 | qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) | |
3893 | { | |
3894 | char event_string[40]; | |
3895 | char *envp[] = { event_string, NULL }; | |
3896 | ||
3897 | switch (code) { | |
3898 | case QLA_UEVENT_CODE_FW_DUMP: | |
3899 | snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", | |
3900 | vha->host_no); | |
3901 | break; | |
3902 | default: | |
3903 | /* do nothing */ | |
3904 | break; | |
3905 | } | |
3906 | kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); | |
3907 | } | |
3908 | ||
8ae6d9c7 GM |
3909 | int |
3910 | qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, | |
3911 | uint32_t *data, int cnt) | |
3912 | { | |
3913 | struct qla_work_evt *e; | |
3914 | ||
3915 | e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); | |
3916 | if (!e) | |
3917 | return QLA_FUNCTION_FAILED; | |
3918 | ||
3919 | e->u.aenfx.evtcode = evtcode; | |
3920 | e->u.aenfx.count = cnt; | |
3921 | memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); | |
3922 | return qla2x00_post_work(vha, e); | |
3923 | } | |
3924 | ||
ac280b67 | 3925 | void |
e315cd28 | 3926 | qla2x00_do_work(struct scsi_qla_host *vha) |
0971de7f | 3927 | { |
f999f4c1 AV |
3928 | struct qla_work_evt *e, *tmp; |
3929 | unsigned long flags; | |
3930 | LIST_HEAD(work); | |
0971de7f | 3931 | |
f999f4c1 AV |
3932 | spin_lock_irqsave(&vha->work_lock, flags); |
3933 | list_splice_init(&vha->work_list, &work); | |
3934 | spin_unlock_irqrestore(&vha->work_lock, flags); | |
3935 | ||
3936 | list_for_each_entry_safe(e, tmp, &work, list) { | |
0971de7f | 3937 | list_del_init(&e->list); |
0971de7f AV |
3938 | |
3939 | switch (e->type) { | |
3940 | case QLA_EVT_AEN: | |
e315cd28 | 3941 | fc_host_post_event(vha->host, fc_get_event_number(), |
0971de7f AV |
3942 | e->u.aen.code, e->u.aen.data); |
3943 | break; | |
8a659571 AV |
3944 | case QLA_EVT_IDC_ACK: |
3945 | qla81xx_idc_ack(vha, e->u.idc_ack.mb); | |
3946 | break; | |
ac280b67 AV |
3947 | case QLA_EVT_ASYNC_LOGIN: |
3948 | qla2x00_async_login(vha, e->u.logio.fcport, | |
3949 | e->u.logio.data); | |
3950 | break; | |
3951 | case QLA_EVT_ASYNC_LOGIN_DONE: | |
3952 | qla2x00_async_login_done(vha, e->u.logio.fcport, | |
3953 | e->u.logio.data); | |
3954 | break; | |
3955 | case QLA_EVT_ASYNC_LOGOUT: | |
3956 | qla2x00_async_logout(vha, e->u.logio.fcport); | |
3957 | break; | |
3958 | case QLA_EVT_ASYNC_LOGOUT_DONE: | |
3959 | qla2x00_async_logout_done(vha, e->u.logio.fcport, | |
3960 | e->u.logio.data); | |
3961 | break; | |
5ff1d584 AV |
3962 | case QLA_EVT_ASYNC_ADISC: |
3963 | qla2x00_async_adisc(vha, e->u.logio.fcport, | |
3964 | e->u.logio.data); | |
3965 | break; | |
3966 | case QLA_EVT_ASYNC_ADISC_DONE: | |
3967 | qla2x00_async_adisc_done(vha, e->u.logio.fcport, | |
3968 | e->u.logio.data); | |
3969 | break; | |
3420d36c AV |
3970 | case QLA_EVT_UEVENT: |
3971 | qla2x00_uevent_emit(vha, e->u.uevent.code); | |
3972 | break; | |
8ae6d9c7 GM |
3973 | case QLA_EVT_AENFX: |
3974 | qlafx00_process_aen(vha, e); | |
3975 | break; | |
0971de7f AV |
3976 | } |
3977 | if (e->flags & QLA_EVT_FLAG_FREE) | |
3978 | kfree(e); | |
feafb7b1 AE |
3979 | |
3980 | /* For each work completed decrement vha ref count */ | |
3981 | QLA_VHA_MARK_NOT_BUSY(vha); | |
e315cd28 | 3982 | } |
e315cd28 | 3983 | } |
f999f4c1 | 3984 | |
e315cd28 AC |
3985 | /* Relogins all the fcports of a vport |
3986 | * Context: dpc thread | |
3987 | */ | |
3988 | void qla2x00_relogin(struct scsi_qla_host *vha) | |
3989 | { | |
3990 | fc_port_t *fcport; | |
c6b2fca8 | 3991 | int status; |
e315cd28 AC |
3992 | uint16_t next_loopid = 0; |
3993 | struct qla_hw_data *ha = vha->hw; | |
ac280b67 | 3994 | uint16_t data[2]; |
e315cd28 AC |
3995 | |
3996 | list_for_each_entry(fcport, &vha->vp_fcports, list) { | |
3997 | /* | |
3998 | * If the port is not ONLINE then try to login | |
3999 | * to it if we haven't run out of retries. | |
4000 | */ | |
5ff1d584 AV |
4001 | if (atomic_read(&fcport->state) != FCS_ONLINE && |
4002 | fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) { | |
ac280b67 | 4003 | fcport->login_retry--; |
e315cd28 | 4004 | if (fcport->flags & FCF_FABRIC_DEVICE) { |
f08b7251 | 4005 | if (fcport->flags & FCF_FCP2_DEVICE) |
e315cd28 AC |
4006 | ha->isp_ops->fabric_logout(vha, |
4007 | fcport->loop_id, | |
4008 | fcport->d_id.b.domain, | |
4009 | fcport->d_id.b.area, | |
4010 | fcport->d_id.b.al_pa); | |
4011 | ||
03bcfb57 JC |
4012 | if (fcport->loop_id == FC_NO_LOOP_ID) { |
4013 | fcport->loop_id = next_loopid = | |
4014 | ha->min_external_loopid; | |
4015 | status = qla2x00_find_new_loop_id( | |
4016 | vha, fcport); | |
4017 | if (status != QLA_SUCCESS) { | |
4018 | /* Ran out of IDs to use */ | |
4019 | break; | |
4020 | } | |
4021 | } | |
4022 | ||
ac280b67 | 4023 | if (IS_ALOGIO_CAPABLE(ha)) { |
5ff1d584 | 4024 | fcport->flags |= FCF_ASYNC_SENT; |
ac280b67 AV |
4025 | data[0] = 0; |
4026 | data[1] = QLA_LOGIO_LOGIN_RETRIED; | |
4027 | status = qla2x00_post_async_login_work( | |
4028 | vha, fcport, data); | |
4029 | if (status == QLA_SUCCESS) | |
4030 | continue; | |
4031 | /* Attempt a retry. */ | |
4032 | status = 1; | |
aaf4d3e2 | 4033 | } else { |
ac280b67 AV |
4034 | status = qla2x00_fabric_login(vha, |
4035 | fcport, &next_loopid); | |
aaf4d3e2 SK |
4036 | if (status == QLA_SUCCESS) { |
4037 | int status2; | |
4038 | uint8_t opts; | |
4039 | ||
4040 | opts = 0; | |
4041 | if (fcport->flags & | |
4042 | FCF_FCP2_DEVICE) | |
4043 | opts |= BIT_1; | |
03003960 SK |
4044 | status2 = |
4045 | qla2x00_get_port_database( | |
4046 | vha, fcport, opts); | |
aaf4d3e2 SK |
4047 | if (status2 != QLA_SUCCESS) |
4048 | status = 1; | |
4049 | } | |
4050 | } | |
e315cd28 AC |
4051 | } else |
4052 | status = qla2x00_local_device_login(vha, | |
4053 | fcport); | |
4054 | ||
e315cd28 AC |
4055 | if (status == QLA_SUCCESS) { |
4056 | fcport->old_loop_id = fcport->loop_id; | |
4057 | ||
7c3df132 SK |
4058 | ql_dbg(ql_dbg_disc, vha, 0x2003, |
4059 | "Port login OK: logged in ID 0x%x.\n", | |
4060 | fcport->loop_id); | |
e315cd28 AC |
4061 | |
4062 | qla2x00_update_fcport(vha, fcport); | |
4063 | ||
4064 | } else if (status == 1) { | |
4065 | set_bit(RELOGIN_NEEDED, &vha->dpc_flags); | |
4066 | /* retry the login again */ | |
7c3df132 SK |
4067 | ql_dbg(ql_dbg_disc, vha, 0x2007, |
4068 | "Retrying %d login again loop_id 0x%x.\n", | |
4069 | fcport->login_retry, fcport->loop_id); | |
e315cd28 AC |
4070 | } else { |
4071 | fcport->login_retry = 0; | |
4072 | } | |
4073 | ||
4074 | if (fcport->login_retry == 0 && status != QLA_SUCCESS) | |
5f16b331 | 4075 | qla2x00_clear_loop_id(fcport); |
e315cd28 AC |
4076 | } |
4077 | if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) | |
4078 | break; | |
0971de7f | 4079 | } |
0971de7f AV |
4080 | } |
4081 | ||
7d613ac6 SV |
4082 | /* Schedule work on any of the dpc-workqueues */ |
4083 | void | |
4084 | qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) | |
4085 | { | |
4086 | struct qla_hw_data *ha = base_vha->hw; | |
4087 | ||
4088 | switch (work_code) { | |
4089 | case MBA_IDC_AEN: /* 0x8200 */ | |
4090 | if (ha->dpc_lp_wq) | |
4091 | queue_work(ha->dpc_lp_wq, &ha->idc_aen); | |
4092 | break; | |
4093 | ||
4094 | case QLA83XX_NIC_CORE_RESET: /* 0x1 */ | |
4095 | if (!ha->flags.nic_core_reset_hdlr_active) { | |
4096 | if (ha->dpc_hp_wq) | |
4097 | queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); | |
4098 | } else | |
4099 | ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, | |
4100 | "NIC Core reset is already active. Skip " | |
4101 | "scheduling it again.\n"); | |
4102 | break; | |
4103 | case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ | |
4104 | if (ha->dpc_hp_wq) | |
4105 | queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); | |
4106 | break; | |
4107 | case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ | |
4108 | if (ha->dpc_hp_wq) | |
4109 | queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); | |
4110 | break; | |
4111 | default: | |
4112 | ql_log(ql_log_warn, base_vha, 0xb05f, | |
d939be3a | 4113 | "Unknown work-code=0x%x.\n", work_code); |
7d613ac6 SV |
4114 | } |
4115 | ||
4116 | return; | |
4117 | } | |
4118 | ||
4119 | /* Work: Perform NIC Core Unrecoverable state handling */ | |
4120 | void | |
4121 | qla83xx_nic_core_unrecoverable_work(struct work_struct *work) | |
4122 | { | |
4123 | struct qla_hw_data *ha = | |
2ad1b67c | 4124 | container_of(work, struct qla_hw_data, nic_core_unrecoverable); |
7d613ac6 SV |
4125 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
4126 | uint32_t dev_state = 0; | |
4127 | ||
4128 | qla83xx_idc_lock(base_vha, 0); | |
4129 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4130 | qla83xx_reset_ownership(base_vha); | |
4131 | if (ha->flags.nic_core_reset_owner) { | |
4132 | ha->flags.nic_core_reset_owner = 0; | |
4133 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4134 | QLA8XXX_DEV_FAILED); | |
4135 | ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); | |
4136 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); | |
4137 | } | |
4138 | qla83xx_idc_unlock(base_vha, 0); | |
4139 | } | |
4140 | ||
4141 | /* Work: Execute IDC state handler */ | |
4142 | void | |
4143 | qla83xx_idc_state_handler_work(struct work_struct *work) | |
4144 | { | |
4145 | struct qla_hw_data *ha = | |
2ad1b67c | 4146 | container_of(work, struct qla_hw_data, idc_state_handler); |
7d613ac6 SV |
4147 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); |
4148 | uint32_t dev_state = 0; | |
4149 | ||
4150 | qla83xx_idc_lock(base_vha, 0); | |
4151 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4152 | if (dev_state == QLA8XXX_DEV_FAILED || | |
4153 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) | |
4154 | qla83xx_idc_state_handler(base_vha); | |
4155 | qla83xx_idc_unlock(base_vha, 0); | |
4156 | } | |
4157 | ||
fa492630 | 4158 | static int |
7d613ac6 SV |
4159 | qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) |
4160 | { | |
4161 | int rval = QLA_SUCCESS; | |
4162 | unsigned long heart_beat_wait = jiffies + (1 * HZ); | |
4163 | uint32_t heart_beat_counter1, heart_beat_counter2; | |
4164 | ||
4165 | do { | |
4166 | if (time_after(jiffies, heart_beat_wait)) { | |
4167 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, | |
4168 | "Nic Core f/w is not alive.\n"); | |
4169 | rval = QLA_FUNCTION_FAILED; | |
4170 | break; | |
4171 | } | |
4172 | ||
4173 | qla83xx_idc_lock(base_vha, 0); | |
4174 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, | |
4175 | &heart_beat_counter1); | |
4176 | qla83xx_idc_unlock(base_vha, 0); | |
4177 | msleep(100); | |
4178 | qla83xx_idc_lock(base_vha, 0); | |
4179 | qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, | |
4180 | &heart_beat_counter2); | |
4181 | qla83xx_idc_unlock(base_vha, 0); | |
4182 | } while (heart_beat_counter1 == heart_beat_counter2); | |
4183 | ||
4184 | return rval; | |
4185 | } | |
4186 | ||
4187 | /* Work: Perform NIC Core Reset handling */ | |
4188 | void | |
4189 | qla83xx_nic_core_reset_work(struct work_struct *work) | |
4190 | { | |
4191 | struct qla_hw_data *ha = | |
4192 | container_of(work, struct qla_hw_data, nic_core_reset); | |
4193 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4194 | uint32_t dev_state = 0; | |
4195 | ||
81178772 SK |
4196 | if (IS_QLA2031(ha)) { |
4197 | if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) | |
4198 | ql_log(ql_log_warn, base_vha, 0xb081, | |
4199 | "Failed to dump mctp\n"); | |
4200 | return; | |
4201 | } | |
4202 | ||
7d613ac6 SV |
4203 | if (!ha->flags.nic_core_reset_hdlr_active) { |
4204 | if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { | |
4205 | qla83xx_idc_lock(base_vha, 0); | |
4206 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4207 | &dev_state); | |
4208 | qla83xx_idc_unlock(base_vha, 0); | |
4209 | if (dev_state != QLA8XXX_DEV_NEED_RESET) { | |
4210 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, | |
4211 | "Nic Core f/w is alive.\n"); | |
4212 | return; | |
4213 | } | |
4214 | } | |
4215 | ||
4216 | ha->flags.nic_core_reset_hdlr_active = 1; | |
4217 | if (qla83xx_nic_core_reset(base_vha)) { | |
4218 | /* NIC Core reset failed. */ | |
4219 | ql_dbg(ql_dbg_p3p, base_vha, 0xb061, | |
4220 | "NIC Core reset failed.\n"); | |
4221 | } | |
4222 | ha->flags.nic_core_reset_hdlr_active = 0; | |
4223 | } | |
4224 | } | |
4225 | ||
4226 | /* Work: Handle 8200 IDC aens */ | |
4227 | void | |
4228 | qla83xx_service_idc_aen(struct work_struct *work) | |
4229 | { | |
4230 | struct qla_hw_data *ha = | |
4231 | container_of(work, struct qla_hw_data, idc_aen); | |
4232 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4233 | uint32_t dev_state, idc_control; | |
4234 | ||
4235 | qla83xx_idc_lock(base_vha, 0); | |
4236 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4237 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); | |
4238 | qla83xx_idc_unlock(base_vha, 0); | |
4239 | if (dev_state == QLA8XXX_DEV_NEED_RESET) { | |
4240 | if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { | |
4241 | ql_dbg(ql_dbg_p3p, base_vha, 0xb062, | |
4242 | "Application requested NIC Core Reset.\n"); | |
4243 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); | |
4244 | } else if (qla83xx_check_nic_core_fw_alive(base_vha) == | |
4245 | QLA_SUCCESS) { | |
4246 | ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, | |
4247 | "Other protocol driver requested NIC Core Reset.\n"); | |
4248 | qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); | |
4249 | } | |
4250 | } else if (dev_state == QLA8XXX_DEV_FAILED || | |
4251 | dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { | |
4252 | qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); | |
4253 | } | |
4254 | } | |
4255 | ||
4256 | static void | |
4257 | qla83xx_wait_logic(void) | |
4258 | { | |
4259 | int i; | |
4260 | ||
4261 | /* Yield CPU */ | |
4262 | if (!in_interrupt()) { | |
4263 | /* | |
4264 | * Wait about 200ms before retrying again. | |
4265 | * This controls the number of retries for single | |
4266 | * lock operation. | |
4267 | */ | |
4268 | msleep(100); | |
4269 | schedule(); | |
4270 | } else { | |
4271 | for (i = 0; i < 20; i++) | |
4272 | cpu_relax(); /* This a nop instr on i386 */ | |
4273 | } | |
4274 | } | |
4275 | ||
fa492630 | 4276 | static int |
7d613ac6 SV |
4277 | qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) |
4278 | { | |
4279 | int rval; | |
4280 | uint32_t data; | |
4281 | uint32_t idc_lck_rcvry_stage_mask = 0x3; | |
4282 | uint32_t idc_lck_rcvry_owner_mask = 0x3c; | |
4283 | struct qla_hw_data *ha = base_vha->hw; | |
6c315553 SK |
4284 | ql_dbg(ql_dbg_p3p, base_vha, 0xb086, |
4285 | "Trying force recovery of the IDC lock.\n"); | |
7d613ac6 SV |
4286 | |
4287 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); | |
4288 | if (rval) | |
4289 | return rval; | |
4290 | ||
4291 | if ((data & idc_lck_rcvry_stage_mask) > 0) { | |
4292 | return QLA_SUCCESS; | |
4293 | } else { | |
4294 | data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); | |
4295 | rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, | |
4296 | data); | |
4297 | if (rval) | |
4298 | return rval; | |
4299 | ||
4300 | msleep(200); | |
4301 | ||
4302 | rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, | |
4303 | &data); | |
4304 | if (rval) | |
4305 | return rval; | |
4306 | ||
4307 | if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { | |
4308 | data &= (IDC_LOCK_RECOVERY_STAGE2 | | |
4309 | ~(idc_lck_rcvry_stage_mask)); | |
4310 | rval = qla83xx_wr_reg(base_vha, | |
4311 | QLA83XX_IDC_LOCK_RECOVERY, data); | |
4312 | if (rval) | |
4313 | return rval; | |
4314 | ||
4315 | /* Forcefully perform IDC UnLock */ | |
4316 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, | |
4317 | &data); | |
4318 | if (rval) | |
4319 | return rval; | |
4320 | /* Clear lock-id by setting 0xff */ | |
4321 | rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, | |
4322 | 0xff); | |
4323 | if (rval) | |
4324 | return rval; | |
4325 | /* Clear lock-recovery by setting 0x0 */ | |
4326 | rval = qla83xx_wr_reg(base_vha, | |
4327 | QLA83XX_IDC_LOCK_RECOVERY, 0x0); | |
4328 | if (rval) | |
4329 | return rval; | |
4330 | } else | |
4331 | return QLA_SUCCESS; | |
4332 | } | |
4333 | ||
4334 | return rval; | |
4335 | } | |
4336 | ||
fa492630 | 4337 | static int |
7d613ac6 SV |
4338 | qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) |
4339 | { | |
4340 | int rval = QLA_SUCCESS; | |
4341 | uint32_t o_drv_lockid, n_drv_lockid; | |
4342 | unsigned long lock_recovery_timeout; | |
4343 | ||
4344 | lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; | |
4345 | retry_lockid: | |
4346 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); | |
4347 | if (rval) | |
4348 | goto exit; | |
4349 | ||
4350 | /* MAX wait time before forcing IDC Lock recovery = 2 secs */ | |
4351 | if (time_after_eq(jiffies, lock_recovery_timeout)) { | |
4352 | if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) | |
4353 | return QLA_SUCCESS; | |
4354 | else | |
4355 | return QLA_FUNCTION_FAILED; | |
4356 | } | |
4357 | ||
4358 | rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); | |
4359 | if (rval) | |
4360 | goto exit; | |
4361 | ||
4362 | if (o_drv_lockid == n_drv_lockid) { | |
4363 | qla83xx_wait_logic(); | |
4364 | goto retry_lockid; | |
4365 | } else | |
4366 | return QLA_SUCCESS; | |
4367 | ||
4368 | exit: | |
4369 | return rval; | |
4370 | } | |
4371 | ||
4372 | void | |
4373 | qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) | |
4374 | { | |
4375 | uint16_t options = (requester_id << 15) | BIT_6; | |
4376 | uint32_t data; | |
6c315553 | 4377 | uint32_t lock_owner; |
7d613ac6 SV |
4378 | struct qla_hw_data *ha = base_vha->hw; |
4379 | ||
4380 | /* IDC-lock implementation using driver-lock/lock-id remote registers */ | |
4381 | retry_lock: | |
4382 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) | |
4383 | == QLA_SUCCESS) { | |
4384 | if (data) { | |
4385 | /* Setting lock-id to our function-number */ | |
4386 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, | |
4387 | ha->portnum); | |
4388 | } else { | |
6c315553 SK |
4389 | qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, |
4390 | &lock_owner); | |
7d613ac6 | 4391 | ql_dbg(ql_dbg_p3p, base_vha, 0xb063, |
6c315553 SK |
4392 | "Failed to acquire IDC lock, acquired by %d, " |
4393 | "retrying...\n", lock_owner); | |
7d613ac6 SV |
4394 | |
4395 | /* Retry/Perform IDC-Lock recovery */ | |
4396 | if (qla83xx_idc_lock_recovery(base_vha) | |
4397 | == QLA_SUCCESS) { | |
4398 | qla83xx_wait_logic(); | |
4399 | goto retry_lock; | |
4400 | } else | |
4401 | ql_log(ql_log_warn, base_vha, 0xb075, | |
4402 | "IDC Lock recovery FAILED.\n"); | |
4403 | } | |
4404 | ||
4405 | } | |
4406 | ||
4407 | return; | |
4408 | ||
4409 | /* XXX: IDC-lock implementation using access-control mbx */ | |
4410 | retry_lock2: | |
4411 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { | |
4412 | ql_dbg(ql_dbg_p3p, base_vha, 0xb072, | |
4413 | "Failed to acquire IDC lock. retrying...\n"); | |
4414 | /* Retry/Perform IDC-Lock recovery */ | |
4415 | if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) { | |
4416 | qla83xx_wait_logic(); | |
4417 | goto retry_lock2; | |
4418 | } else | |
4419 | ql_log(ql_log_warn, base_vha, 0xb076, | |
4420 | "IDC Lock recovery FAILED.\n"); | |
4421 | } | |
4422 | ||
4423 | return; | |
4424 | } | |
4425 | ||
4426 | void | |
4427 | qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) | |
4428 | { | |
5897cb2f BVA |
4429 | #if 0 |
4430 | uint16_t options = (requester_id << 15) | BIT_7; | |
4431 | #endif | |
4432 | uint16_t retry; | |
7d613ac6 SV |
4433 | uint32_t data; |
4434 | struct qla_hw_data *ha = base_vha->hw; | |
4435 | ||
4436 | /* IDC-unlock implementation using driver-unlock/lock-id | |
4437 | * remote registers | |
4438 | */ | |
4439 | retry = 0; | |
4440 | retry_unlock: | |
4441 | if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) | |
4442 | == QLA_SUCCESS) { | |
4443 | if (data == ha->portnum) { | |
4444 | qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); | |
4445 | /* Clearing lock-id by setting 0xff */ | |
4446 | qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); | |
4447 | } else if (retry < 10) { | |
4448 | /* SV: XXX: IDC unlock retrying needed here? */ | |
4449 | ||
4450 | /* Retry for IDC-unlock */ | |
4451 | qla83xx_wait_logic(); | |
4452 | retry++; | |
4453 | ql_dbg(ql_dbg_p3p, base_vha, 0xb064, | |
4454 | "Failed to release IDC lock, retyring=%d\n", retry); | |
4455 | goto retry_unlock; | |
4456 | } | |
4457 | } else if (retry < 10) { | |
4458 | /* Retry for IDC-unlock */ | |
4459 | qla83xx_wait_logic(); | |
4460 | retry++; | |
4461 | ql_dbg(ql_dbg_p3p, base_vha, 0xb065, | |
4462 | "Failed to read drv-lockid, retyring=%d\n", retry); | |
4463 | goto retry_unlock; | |
4464 | } | |
4465 | ||
4466 | return; | |
4467 | ||
5897cb2f | 4468 | #if 0 |
7d613ac6 SV |
4469 | /* XXX: IDC-unlock implementation using access-control mbx */ |
4470 | retry = 0; | |
4471 | retry_unlock2: | |
4472 | if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { | |
4473 | if (retry < 10) { | |
4474 | /* Retry for IDC-unlock */ | |
4475 | qla83xx_wait_logic(); | |
4476 | retry++; | |
4477 | ql_dbg(ql_dbg_p3p, base_vha, 0xb066, | |
4478 | "Failed to release IDC lock, retyring=%d\n", retry); | |
4479 | goto retry_unlock2; | |
4480 | } | |
4481 | } | |
4482 | ||
4483 | return; | |
5897cb2f | 4484 | #endif |
7d613ac6 SV |
4485 | } |
4486 | ||
4487 | int | |
4488 | __qla83xx_set_drv_presence(scsi_qla_host_t *vha) | |
4489 | { | |
4490 | int rval = QLA_SUCCESS; | |
4491 | struct qla_hw_data *ha = vha->hw; | |
4492 | uint32_t drv_presence; | |
4493 | ||
4494 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4495 | if (rval == QLA_SUCCESS) { | |
4496 | drv_presence |= (1 << ha->portnum); | |
4497 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4498 | drv_presence); | |
4499 | } | |
4500 | ||
4501 | return rval; | |
4502 | } | |
4503 | ||
4504 | int | |
4505 | qla83xx_set_drv_presence(scsi_qla_host_t *vha) | |
4506 | { | |
4507 | int rval = QLA_SUCCESS; | |
4508 | ||
4509 | qla83xx_idc_lock(vha, 0); | |
4510 | rval = __qla83xx_set_drv_presence(vha); | |
4511 | qla83xx_idc_unlock(vha, 0); | |
4512 | ||
4513 | return rval; | |
4514 | } | |
4515 | ||
4516 | int | |
4517 | __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) | |
4518 | { | |
4519 | int rval = QLA_SUCCESS; | |
4520 | struct qla_hw_data *ha = vha->hw; | |
4521 | uint32_t drv_presence; | |
4522 | ||
4523 | rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
4524 | if (rval == QLA_SUCCESS) { | |
4525 | drv_presence &= ~(1 << ha->portnum); | |
4526 | rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4527 | drv_presence); | |
4528 | } | |
4529 | ||
4530 | return rval; | |
4531 | } | |
4532 | ||
4533 | int | |
4534 | qla83xx_clear_drv_presence(scsi_qla_host_t *vha) | |
4535 | { | |
4536 | int rval = QLA_SUCCESS; | |
4537 | ||
4538 | qla83xx_idc_lock(vha, 0); | |
4539 | rval = __qla83xx_clear_drv_presence(vha); | |
4540 | qla83xx_idc_unlock(vha, 0); | |
4541 | ||
4542 | return rval; | |
4543 | } | |
4544 | ||
fa492630 | 4545 | static void |
7d613ac6 SV |
4546 | qla83xx_need_reset_handler(scsi_qla_host_t *vha) |
4547 | { | |
4548 | struct qla_hw_data *ha = vha->hw; | |
4549 | uint32_t drv_ack, drv_presence; | |
4550 | unsigned long ack_timeout; | |
4551 | ||
4552 | /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ | |
4553 | ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); | |
4554 | while (1) { | |
4555 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); | |
4556 | qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); | |
807fb6d8 | 4557 | if ((drv_ack & drv_presence) == drv_presence) |
7d613ac6 SV |
4558 | break; |
4559 | ||
4560 | if (time_after_eq(jiffies, ack_timeout)) { | |
4561 | ql_log(ql_log_warn, vha, 0xb067, | |
4562 | "RESET ACK TIMEOUT! drv_presence=0x%x " | |
4563 | "drv_ack=0x%x\n", drv_presence, drv_ack); | |
4564 | /* | |
4565 | * The function(s) which did not ack in time are forced | |
4566 | * to withdraw any further participation in the IDC | |
4567 | * reset. | |
4568 | */ | |
4569 | if (drv_ack != drv_presence) | |
4570 | qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, | |
4571 | drv_ack); | |
4572 | break; | |
4573 | } | |
4574 | ||
4575 | qla83xx_idc_unlock(vha, 0); | |
4576 | msleep(1000); | |
4577 | qla83xx_idc_lock(vha, 0); | |
4578 | } | |
4579 | ||
4580 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); | |
4581 | ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); | |
4582 | } | |
4583 | ||
fa492630 | 4584 | static int |
7d613ac6 SV |
4585 | qla83xx_device_bootstrap(scsi_qla_host_t *vha) |
4586 | { | |
4587 | int rval = QLA_SUCCESS; | |
4588 | uint32_t idc_control; | |
4589 | ||
4590 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); | |
4591 | ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); | |
4592 | ||
4593 | /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ | |
4594 | __qla83xx_get_idc_control(vha, &idc_control); | |
4595 | idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; | |
4596 | __qla83xx_set_idc_control(vha, 0); | |
4597 | ||
4598 | qla83xx_idc_unlock(vha, 0); | |
4599 | rval = qla83xx_restart_nic_firmware(vha); | |
4600 | qla83xx_idc_lock(vha, 0); | |
4601 | ||
4602 | if (rval != QLA_SUCCESS) { | |
4603 | ql_log(ql_log_fatal, vha, 0xb06a, | |
4604 | "Failed to restart NIC f/w.\n"); | |
4605 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); | |
4606 | ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); | |
4607 | } else { | |
4608 | ql_dbg(ql_dbg_p3p, vha, 0xb06c, | |
4609 | "Success in restarting nic f/w.\n"); | |
4610 | qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); | |
4611 | ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); | |
4612 | } | |
4613 | ||
4614 | return rval; | |
4615 | } | |
4616 | ||
4617 | /* Assumes idc_lock always held on entry */ | |
4618 | int | |
4619 | qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) | |
4620 | { | |
4621 | struct qla_hw_data *ha = base_vha->hw; | |
4622 | int rval = QLA_SUCCESS; | |
4623 | unsigned long dev_init_timeout; | |
4624 | uint32_t dev_state; | |
4625 | ||
4626 | /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ | |
4627 | dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); | |
4628 | ||
4629 | while (1) { | |
4630 | ||
4631 | if (time_after_eq(jiffies, dev_init_timeout)) { | |
4632 | ql_log(ql_log_warn, base_vha, 0xb06e, | |
4633 | "Initialization TIMEOUT!\n"); | |
4634 | /* Init timeout. Disable further NIC Core | |
4635 | * communication. | |
4636 | */ | |
4637 | qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, | |
4638 | QLA8XXX_DEV_FAILED); | |
4639 | ql_log(ql_log_info, base_vha, 0xb06f, | |
4640 | "HW State: FAILED.\n"); | |
4641 | } | |
4642 | ||
4643 | qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); | |
4644 | switch (dev_state) { | |
4645 | case QLA8XXX_DEV_READY: | |
4646 | if (ha->flags.nic_core_reset_owner) | |
4647 | qla83xx_idc_audit(base_vha, | |
4648 | IDC_AUDIT_COMPLETION); | |
4649 | ha->flags.nic_core_reset_owner = 0; | |
4650 | ql_dbg(ql_dbg_p3p, base_vha, 0xb070, | |
4651 | "Reset_owner reset by 0x%x.\n", | |
4652 | ha->portnum); | |
4653 | goto exit; | |
4654 | case QLA8XXX_DEV_COLD: | |
4655 | if (ha->flags.nic_core_reset_owner) | |
4656 | rval = qla83xx_device_bootstrap(base_vha); | |
4657 | else { | |
4658 | /* Wait for AEN to change device-state */ | |
4659 | qla83xx_idc_unlock(base_vha, 0); | |
4660 | msleep(1000); | |
4661 | qla83xx_idc_lock(base_vha, 0); | |
4662 | } | |
4663 | break; | |
4664 | case QLA8XXX_DEV_INITIALIZING: | |
4665 | /* Wait for AEN to change device-state */ | |
4666 | qla83xx_idc_unlock(base_vha, 0); | |
4667 | msleep(1000); | |
4668 | qla83xx_idc_lock(base_vha, 0); | |
4669 | break; | |
4670 | case QLA8XXX_DEV_NEED_RESET: | |
4671 | if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) | |
4672 | qla83xx_need_reset_handler(base_vha); | |
4673 | else { | |
4674 | /* Wait for AEN to change device-state */ | |
4675 | qla83xx_idc_unlock(base_vha, 0); | |
4676 | msleep(1000); | |
4677 | qla83xx_idc_lock(base_vha, 0); | |
4678 | } | |
4679 | /* reset timeout value after need reset handler */ | |
4680 | dev_init_timeout = jiffies + | |
4681 | (ha->fcoe_dev_init_timeout * HZ); | |
4682 | break; | |
4683 | case QLA8XXX_DEV_NEED_QUIESCENT: | |
4684 | /* XXX: DEBUG for now */ | |
4685 | qla83xx_idc_unlock(base_vha, 0); | |
4686 | msleep(1000); | |
4687 | qla83xx_idc_lock(base_vha, 0); | |
4688 | break; | |
4689 | case QLA8XXX_DEV_QUIESCENT: | |
4690 | /* XXX: DEBUG for now */ | |
4691 | if (ha->flags.quiesce_owner) | |
4692 | goto exit; | |
4693 | ||
4694 | qla83xx_idc_unlock(base_vha, 0); | |
4695 | msleep(1000); | |
4696 | qla83xx_idc_lock(base_vha, 0); | |
4697 | dev_init_timeout = jiffies + | |
4698 | (ha->fcoe_dev_init_timeout * HZ); | |
4699 | break; | |
4700 | case QLA8XXX_DEV_FAILED: | |
4701 | if (ha->flags.nic_core_reset_owner) | |
4702 | qla83xx_idc_audit(base_vha, | |
4703 | IDC_AUDIT_COMPLETION); | |
4704 | ha->flags.nic_core_reset_owner = 0; | |
4705 | __qla83xx_clear_drv_presence(base_vha); | |
4706 | qla83xx_idc_unlock(base_vha, 0); | |
4707 | qla8xxx_dev_failed_handler(base_vha); | |
4708 | rval = QLA_FUNCTION_FAILED; | |
4709 | qla83xx_idc_lock(base_vha, 0); | |
4710 | goto exit; | |
4711 | case QLA8XXX_BAD_VALUE: | |
4712 | qla83xx_idc_unlock(base_vha, 0); | |
4713 | msleep(1000); | |
4714 | qla83xx_idc_lock(base_vha, 0); | |
4715 | break; | |
4716 | default: | |
4717 | ql_log(ql_log_warn, base_vha, 0xb071, | |
d939be3a | 4718 | "Unknown Device State: %x.\n", dev_state); |
7d613ac6 SV |
4719 | qla83xx_idc_unlock(base_vha, 0); |
4720 | qla8xxx_dev_failed_handler(base_vha); | |
4721 | rval = QLA_FUNCTION_FAILED; | |
4722 | qla83xx_idc_lock(base_vha, 0); | |
4723 | goto exit; | |
4724 | } | |
4725 | } | |
4726 | ||
4727 | exit: | |
4728 | return rval; | |
4729 | } | |
4730 | ||
f3ddac19 CD |
4731 | void |
4732 | qla2x00_disable_board_on_pci_error(struct work_struct *work) | |
4733 | { | |
4734 | struct qla_hw_data *ha = container_of(work, struct qla_hw_data, | |
4735 | board_disable); | |
4736 | struct pci_dev *pdev = ha->pdev; | |
4737 | scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); | |
4738 | ||
4739 | ql_log(ql_log_warn, base_vha, 0x015b, | |
4740 | "Disabling adapter.\n"); | |
4741 | ||
4742 | set_bit(UNLOADING, &base_vha->dpc_flags); | |
4743 | ||
4744 | qla2x00_delete_all_vps(ha, base_vha); | |
4745 | ||
4746 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
4747 | ||
4748 | qla2x00_dfs_remove(base_vha); | |
4749 | ||
4750 | qla84xx_put_chip(base_vha); | |
4751 | ||
4752 | if (base_vha->timer_active) | |
4753 | qla2x00_stop_timer(base_vha); | |
4754 | ||
4755 | base_vha->flags.online = 0; | |
4756 | ||
4757 | qla2x00_destroy_deferred_work(ha); | |
4758 | ||
4759 | /* | |
4760 | * Do not try to stop beacon blink as it will issue a mailbox | |
4761 | * command. | |
4762 | */ | |
4763 | qla2x00_free_sysfs_attr(base_vha, false); | |
4764 | ||
4765 | fc_remove_host(base_vha->host); | |
4766 | ||
4767 | scsi_remove_host(base_vha->host); | |
4768 | ||
4769 | base_vha->flags.init_done = 0; | |
4770 | qla25xx_delete_queues(base_vha); | |
4771 | qla2x00_free_irqs(base_vha); | |
4772 | qla2x00_free_fcports(base_vha); | |
4773 | qla2x00_mem_free(ha); | |
4774 | qla82xx_md_free(base_vha); | |
4775 | qla2x00_free_queues(ha); | |
4776 | ||
f3ddac19 CD |
4777 | qla2x00_unmap_iobases(ha); |
4778 | ||
4779 | pci_release_selected_regions(ha->pdev, ha->bars); | |
f3ddac19 CD |
4780 | pci_disable_pcie_error_reporting(pdev); |
4781 | pci_disable_device(pdev); | |
f3ddac19 | 4782 | |
beb9e315 JL |
4783 | /* |
4784 | * Let qla2x00_remove_one cleanup qla_hw_data on device removal. | |
4785 | */ | |
f3ddac19 CD |
4786 | } |
4787 | ||
1da177e4 LT |
4788 | /************************************************************************** |
4789 | * qla2x00_do_dpc | |
4790 | * This kernel thread is a task that is schedule by the interrupt handler | |
4791 | * to perform the background processing for interrupts. | |
4792 | * | |
4793 | * Notes: | |
4794 | * This task always run in the context of a kernel thread. It | |
4795 | * is kick-off by the driver's detect code and starts up | |
4796 | * up one per adapter. It immediately goes to sleep and waits for | |
4797 | * some fibre event. When either the interrupt handler or | |
4798 | * the timer routine detects a event it will one of the task | |
4799 | * bits then wake us up. | |
4800 | **************************************************************************/ | |
4801 | static int | |
4802 | qla2x00_do_dpc(void *data) | |
4803 | { | |
2c3dfe3f | 4804 | int rval; |
e315cd28 AC |
4805 | scsi_qla_host_t *base_vha; |
4806 | struct qla_hw_data *ha; | |
1da177e4 | 4807 | |
e315cd28 AC |
4808 | ha = (struct qla_hw_data *)data; |
4809 | base_vha = pci_get_drvdata(ha->pdev); | |
1da177e4 | 4810 | |
8698a745 | 4811 | set_user_nice(current, MIN_NICE); |
1da177e4 | 4812 | |
563585ec | 4813 | set_current_state(TASK_INTERRUPTIBLE); |
39a11240 | 4814 | while (!kthread_should_stop()) { |
7c3df132 SK |
4815 | ql_dbg(ql_dbg_dpc, base_vha, 0x4000, |
4816 | "DPC handler sleeping.\n"); | |
1da177e4 | 4817 | |
39a11240 | 4818 | schedule(); |
1da177e4 | 4819 | |
c142caf0 AV |
4820 | if (!base_vha->flags.init_done || ha->flags.mbox_busy) |
4821 | goto end_loop; | |
1da177e4 | 4822 | |
85880801 | 4823 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
4824 | ql_dbg(ql_dbg_dpc, base_vha, 0x4003, |
4825 | "eeh_busy=%d.\n", ha->flags.eeh_busy); | |
c142caf0 | 4826 | goto end_loop; |
85880801 AV |
4827 | } |
4828 | ||
1da177e4 LT |
4829 | ha->dpc_active = 1; |
4830 | ||
5f28d2d7 SK |
4831 | ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, |
4832 | "DPC handler waking up, dpc_flags=0x%lx.\n", | |
4833 | base_vha->dpc_flags); | |
1da177e4 | 4834 | |
e315cd28 | 4835 | qla2x00_do_work(base_vha); |
0971de7f | 4836 | |
7ec0effd AD |
4837 | if (IS_P3P_TYPE(ha)) { |
4838 | if (IS_QLA8044(ha)) { | |
4839 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
4840 | &base_vha->dpc_flags)) { | |
4841 | qla8044_idc_lock(ha); | |
4842 | qla8044_wr_direct(base_vha, | |
4843 | QLA8044_CRB_DEV_STATE_INDEX, | |
4844 | QLA8XXX_DEV_FAILED); | |
4845 | qla8044_idc_unlock(ha); | |
4846 | ql_log(ql_log_info, base_vha, 0x4004, | |
4847 | "HW State: FAILED.\n"); | |
4848 | qla8044_device_state_handler(base_vha); | |
4849 | continue; | |
4850 | } | |
4851 | ||
4852 | } else { | |
4853 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
4854 | &base_vha->dpc_flags)) { | |
4855 | qla82xx_idc_lock(ha); | |
4856 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
4857 | QLA8XXX_DEV_FAILED); | |
4858 | qla82xx_idc_unlock(ha); | |
4859 | ql_log(ql_log_info, base_vha, 0x0151, | |
4860 | "HW State: FAILED.\n"); | |
4861 | qla82xx_device_state_handler(base_vha); | |
4862 | continue; | |
4863 | } | |
a9083016 GM |
4864 | } |
4865 | ||
4866 | if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, | |
4867 | &base_vha->dpc_flags)) { | |
4868 | ||
7c3df132 SK |
4869 | ql_dbg(ql_dbg_dpc, base_vha, 0x4005, |
4870 | "FCoE context reset scheduled.\n"); | |
a9083016 GM |
4871 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
4872 | &base_vha->dpc_flags))) { | |
4873 | if (qla82xx_fcoe_ctx_reset(base_vha)) { | |
4874 | /* FCoE-ctx reset failed. | |
4875 | * Escalate to chip-reset | |
4876 | */ | |
4877 | set_bit(ISP_ABORT_NEEDED, | |
4878 | &base_vha->dpc_flags); | |
4879 | } | |
4880 | clear_bit(ABORT_ISP_ACTIVE, | |
4881 | &base_vha->dpc_flags); | |
4882 | } | |
4883 | ||
7c3df132 SK |
4884 | ql_dbg(ql_dbg_dpc, base_vha, 0x4006, |
4885 | "FCoE context reset end.\n"); | |
a9083016 | 4886 | } |
8ae6d9c7 GM |
4887 | } else if (IS_QLAFX00(ha)) { |
4888 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | |
4889 | &base_vha->dpc_flags)) { | |
4890 | ql_dbg(ql_dbg_dpc, base_vha, 0x4020, | |
4891 | "Firmware Reset Recovery\n"); | |
4892 | if (qlafx00_reset_initialize(base_vha)) { | |
4893 | /* Failed. Abort isp later. */ | |
4894 | if (!test_bit(UNLOADING, | |
f92f82d6 | 4895 | &base_vha->dpc_flags)) { |
8ae6d9c7 GM |
4896 | set_bit(ISP_UNRECOVERABLE, |
4897 | &base_vha->dpc_flags); | |
4898 | ql_dbg(ql_dbg_dpc, base_vha, | |
4899 | 0x4021, | |
4900 | "Reset Recovery Failed\n"); | |
f92f82d6 | 4901 | } |
8ae6d9c7 GM |
4902 | } |
4903 | } | |
4904 | ||
4905 | if (test_and_clear_bit(FX00_TARGET_SCAN, | |
4906 | &base_vha->dpc_flags)) { | |
4907 | ql_dbg(ql_dbg_dpc, base_vha, 0x4022, | |
4908 | "ISPFx00 Target Scan scheduled\n"); | |
4909 | if (qlafx00_rescan_isp(base_vha)) { | |
4910 | if (!test_bit(UNLOADING, | |
4911 | &base_vha->dpc_flags)) | |
4912 | set_bit(ISP_UNRECOVERABLE, | |
4913 | &base_vha->dpc_flags); | |
4914 | ql_dbg(ql_dbg_dpc, base_vha, 0x401e, | |
4915 | "ISPFx00 Target Scan Failed\n"); | |
4916 | } | |
4917 | ql_dbg(ql_dbg_dpc, base_vha, 0x401f, | |
4918 | "ISPFx00 Target Scan End\n"); | |
4919 | } | |
e8f5e95d AB |
4920 | if (test_and_clear_bit(FX00_HOST_INFO_RESEND, |
4921 | &base_vha->dpc_flags)) { | |
4922 | ql_dbg(ql_dbg_dpc, base_vha, 0x4023, | |
4923 | "ISPFx00 Host Info resend scheduled\n"); | |
4924 | qlafx00_fx_disc(base_vha, | |
4925 | &base_vha->hw->mr.fcport, | |
4926 | FXDISC_REG_HOST_INFO); | |
4927 | } | |
a9083016 GM |
4928 | } |
4929 | ||
e315cd28 AC |
4930 | if (test_and_clear_bit(ISP_ABORT_NEEDED, |
4931 | &base_vha->dpc_flags)) { | |
1da177e4 | 4932 | |
7c3df132 SK |
4933 | ql_dbg(ql_dbg_dpc, base_vha, 0x4007, |
4934 | "ISP abort scheduled.\n"); | |
1da177e4 | 4935 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
e315cd28 | 4936 | &base_vha->dpc_flags))) { |
1da177e4 | 4937 | |
a9083016 | 4938 | if (ha->isp_ops->abort_isp(base_vha)) { |
1da177e4 LT |
4939 | /* failed. retry later */ |
4940 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 4941 | &base_vha->dpc_flags); |
99363ef8 | 4942 | } |
e315cd28 AC |
4943 | clear_bit(ABORT_ISP_ACTIVE, |
4944 | &base_vha->dpc_flags); | |
99363ef8 SJ |
4945 | } |
4946 | ||
7c3df132 SK |
4947 | ql_dbg(ql_dbg_dpc, base_vha, 0x4008, |
4948 | "ISP abort end.\n"); | |
1da177e4 LT |
4949 | } |
4950 | ||
a394aac8 DJ |
4951 | if (test_and_clear_bit(FCPORT_UPDATE_NEEDED, |
4952 | &base_vha->dpc_flags)) { | |
e315cd28 | 4953 | qla2x00_update_fcports(base_vha); |
c9c5ced9 | 4954 | } |
d97994dc | 4955 | |
2d70c103 NB |
4956 | if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) { |
4957 | int ret; | |
4958 | ret = qla2x00_send_change_request(base_vha, 0x3, 0); | |
4959 | if (ret != QLA_SUCCESS) | |
4960 | ql_log(ql_log_warn, base_vha, 0x121, | |
4961 | "Failed to enable receiving of RSCN " | |
4962 | "requests: 0x%x.\n", ret); | |
4963 | clear_bit(SCR_PENDING, &base_vha->dpc_flags); | |
4964 | } | |
4965 | ||
8ae6d9c7 GM |
4966 | if (IS_QLAFX00(ha)) |
4967 | goto loop_resync_check; | |
4968 | ||
579d12b5 | 4969 | if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { |
7c3df132 SK |
4970 | ql_dbg(ql_dbg_dpc, base_vha, 0x4009, |
4971 | "Quiescence mode scheduled.\n"); | |
7ec0effd AD |
4972 | if (IS_P3P_TYPE(ha)) { |
4973 | if (IS_QLA82XX(ha)) | |
4974 | qla82xx_device_state_handler(base_vha); | |
4975 | if (IS_QLA8044(ha)) | |
4976 | qla8044_device_state_handler(base_vha); | |
8fcd6b8b CD |
4977 | clear_bit(ISP_QUIESCE_NEEDED, |
4978 | &base_vha->dpc_flags); | |
4979 | if (!ha->flags.quiesce_owner) { | |
4980 | qla2x00_perform_loop_resync(base_vha); | |
7ec0effd AD |
4981 | if (IS_QLA82XX(ha)) { |
4982 | qla82xx_idc_lock(ha); | |
4983 | qla82xx_clear_qsnt_ready( | |
4984 | base_vha); | |
4985 | qla82xx_idc_unlock(ha); | |
4986 | } else if (IS_QLA8044(ha)) { | |
4987 | qla8044_idc_lock(ha); | |
4988 | qla8044_clear_qsnt_ready( | |
4989 | base_vha); | |
4990 | qla8044_idc_unlock(ha); | |
4991 | } | |
8fcd6b8b CD |
4992 | } |
4993 | } else { | |
4994 | clear_bit(ISP_QUIESCE_NEEDED, | |
4995 | &base_vha->dpc_flags); | |
4996 | qla2x00_quiesce_io(base_vha); | |
579d12b5 | 4997 | } |
7c3df132 SK |
4998 | ql_dbg(ql_dbg_dpc, base_vha, 0x400a, |
4999 | "Quiescence mode end.\n"); | |
579d12b5 SK |
5000 | } |
5001 | ||
e315cd28 | 5002 | if (test_and_clear_bit(RESET_MARKER_NEEDED, |
8ae6d9c7 | 5003 | &base_vha->dpc_flags) && |
e315cd28 | 5004 | (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { |
1da177e4 | 5005 | |
7c3df132 SK |
5006 | ql_dbg(ql_dbg_dpc, base_vha, 0x400b, |
5007 | "Reset marker scheduled.\n"); | |
e315cd28 AC |
5008 | qla2x00_rst_aen(base_vha); |
5009 | clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); | |
7c3df132 SK |
5010 | ql_dbg(ql_dbg_dpc, base_vha, 0x400c, |
5011 | "Reset marker end.\n"); | |
1da177e4 LT |
5012 | } |
5013 | ||
5014 | /* Retry each device up to login retry count */ | |
e315cd28 AC |
5015 | if ((test_and_clear_bit(RELOGIN_NEEDED, |
5016 | &base_vha->dpc_flags)) && | |
5017 | !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && | |
5018 | atomic_read(&base_vha->loop_state) != LOOP_DOWN) { | |
1da177e4 | 5019 | |
7c3df132 SK |
5020 | ql_dbg(ql_dbg_dpc, base_vha, 0x400d, |
5021 | "Relogin scheduled.\n"); | |
e315cd28 | 5022 | qla2x00_relogin(base_vha); |
7c3df132 SK |
5023 | ql_dbg(ql_dbg_dpc, base_vha, 0x400e, |
5024 | "Relogin end.\n"); | |
1da177e4 | 5025 | } |
8ae6d9c7 | 5026 | loop_resync_check: |
e315cd28 | 5027 | if (test_and_clear_bit(LOOP_RESYNC_NEEDED, |
8ae6d9c7 | 5028 | &base_vha->dpc_flags)) { |
1da177e4 | 5029 | |
7c3df132 SK |
5030 | ql_dbg(ql_dbg_dpc, base_vha, 0x400f, |
5031 | "Loop resync scheduled.\n"); | |
1da177e4 LT |
5032 | |
5033 | if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, | |
e315cd28 | 5034 | &base_vha->dpc_flags))) { |
1da177e4 | 5035 | |
e315cd28 | 5036 | rval = qla2x00_loop_resync(base_vha); |
1da177e4 | 5037 | |
e315cd28 AC |
5038 | clear_bit(LOOP_RESYNC_ACTIVE, |
5039 | &base_vha->dpc_flags); | |
1da177e4 LT |
5040 | } |
5041 | ||
7c3df132 SK |
5042 | ql_dbg(ql_dbg_dpc, base_vha, 0x4010, |
5043 | "Loop resync end.\n"); | |
1da177e4 LT |
5044 | } |
5045 | ||
8ae6d9c7 GM |
5046 | if (IS_QLAFX00(ha)) |
5047 | goto intr_on_check; | |
5048 | ||
e315cd28 AC |
5049 | if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && |
5050 | atomic_read(&base_vha->loop_state) == LOOP_READY) { | |
5051 | clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); | |
5052 | qla2xxx_flash_npiv_conf(base_vha); | |
272976ca AV |
5053 | } |
5054 | ||
8ae6d9c7 | 5055 | intr_on_check: |
1da177e4 | 5056 | if (!ha->interrupts_on) |
fd34f556 | 5057 | ha->isp_ops->enable_intrs(ha); |
1da177e4 | 5058 | |
e315cd28 | 5059 | if (test_and_clear_bit(BEACON_BLINK_NEEDED, |
90b604f2 HM |
5060 | &base_vha->dpc_flags)) { |
5061 | if (ha->beacon_blink_led == 1) | |
5062 | ha->isp_ops->beacon_blink(base_vha); | |
5063 | } | |
f6df144c | 5064 | |
8ae6d9c7 GM |
5065 | if (!IS_QLAFX00(ha)) |
5066 | qla2x00_do_dpc_all_vps(base_vha); | |
2c3dfe3f | 5067 | |
1da177e4 | 5068 | ha->dpc_active = 0; |
c142caf0 | 5069 | end_loop: |
563585ec | 5070 | set_current_state(TASK_INTERRUPTIBLE); |
1da177e4 | 5071 | } /* End of while(1) */ |
563585ec | 5072 | __set_current_state(TASK_RUNNING); |
1da177e4 | 5073 | |
7c3df132 SK |
5074 | ql_dbg(ql_dbg_dpc, base_vha, 0x4011, |
5075 | "DPC handler exiting.\n"); | |
1da177e4 LT |
5076 | |
5077 | /* | |
5078 | * Make sure that nobody tries to wake us up again. | |
5079 | */ | |
1da177e4 LT |
5080 | ha->dpc_active = 0; |
5081 | ||
ac280b67 AV |
5082 | /* Cleanup any residual CTX SRBs. */ |
5083 | qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); | |
5084 | ||
39a11240 CH |
5085 | return 0; |
5086 | } | |
5087 | ||
5088 | void | |
e315cd28 | 5089 | qla2xxx_wake_dpc(struct scsi_qla_host *vha) |
39a11240 | 5090 | { |
e315cd28 | 5091 | struct qla_hw_data *ha = vha->hw; |
c795c1e4 AV |
5092 | struct task_struct *t = ha->dpc_thread; |
5093 | ||
e315cd28 | 5094 | if (!test_bit(UNLOADING, &vha->dpc_flags) && t) |
c795c1e4 | 5095 | wake_up_process(t); |
1da177e4 LT |
5096 | } |
5097 | ||
1da177e4 LT |
5098 | /* |
5099 | * qla2x00_rst_aen | |
5100 | * Processes asynchronous reset. | |
5101 | * | |
5102 | * Input: | |
5103 | * ha = adapter block pointer. | |
5104 | */ | |
5105 | static void | |
e315cd28 | 5106 | qla2x00_rst_aen(scsi_qla_host_t *vha) |
1da177e4 | 5107 | { |
e315cd28 AC |
5108 | if (vha->flags.online && !vha->flags.reset_active && |
5109 | !atomic_read(&vha->loop_down_timer) && | |
5110 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { | |
1da177e4 | 5111 | do { |
e315cd28 | 5112 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); |
1da177e4 LT |
5113 | |
5114 | /* | |
5115 | * Issue marker command only when we are going to start | |
5116 | * the I/O. | |
5117 | */ | |
e315cd28 AC |
5118 | vha->marker_needed = 1; |
5119 | } while (!atomic_read(&vha->loop_down_timer) && | |
5120 | (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); | |
1da177e4 LT |
5121 | } |
5122 | } | |
5123 | ||
1da177e4 LT |
5124 | /************************************************************************** |
5125 | * qla2x00_timer | |
5126 | * | |
5127 | * Description: | |
5128 | * One second timer | |
5129 | * | |
5130 | * Context: Interrupt | |
5131 | ***************************************************************************/ | |
2c3dfe3f | 5132 | void |
e315cd28 | 5133 | qla2x00_timer(scsi_qla_host_t *vha) |
1da177e4 | 5134 | { |
1da177e4 | 5135 | unsigned long cpu_flags = 0; |
1da177e4 LT |
5136 | int start_dpc = 0; |
5137 | int index; | |
5138 | srb_t *sp; | |
85880801 | 5139 | uint16_t w; |
e315cd28 | 5140 | struct qla_hw_data *ha = vha->hw; |
73208dfd | 5141 | struct req_que *req; |
85880801 | 5142 | |
a5b36321 | 5143 | if (ha->flags.eeh_busy) { |
7c3df132 SK |
5144 | ql_dbg(ql_dbg_timer, vha, 0x6000, |
5145 | "EEH = %d, restarting timer.\n", | |
5146 | ha->flags.eeh_busy); | |
a5b36321 LC |
5147 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
5148 | return; | |
5149 | } | |
5150 | ||
f3ddac19 CD |
5151 | /* |
5152 | * Hardware read to raise pending EEH errors during mailbox waits. If | |
5153 | * the read returns -1 then disable the board. | |
5154 | */ | |
5155 | if (!pci_channel_offline(ha->pdev)) { | |
85880801 | 5156 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); |
c821e0d5 | 5157 | qla2x00_check_reg16_for_disconnect(vha, w); |
f3ddac19 | 5158 | } |
1da177e4 | 5159 | |
cefcaba6 | 5160 | /* Make sure qla82xx_watchdog is run only for physical port */ |
7ec0effd | 5161 | if (!vha->vp_idx && IS_P3P_TYPE(ha)) { |
579d12b5 SK |
5162 | if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) |
5163 | start_dpc++; | |
7ec0effd AD |
5164 | if (IS_QLA82XX(ha)) |
5165 | qla82xx_watchdog(vha); | |
5166 | else if (IS_QLA8044(ha)) | |
5167 | qla8044_watchdog(vha); | |
579d12b5 SK |
5168 | } |
5169 | ||
8ae6d9c7 GM |
5170 | if (!vha->vp_idx && IS_QLAFX00(ha)) |
5171 | qlafx00_timer_routine(vha); | |
5172 | ||
1da177e4 | 5173 | /* Loop down handler. */ |
e315cd28 | 5174 | if (atomic_read(&vha->loop_down_timer) > 0 && |
8f7daead GM |
5175 | !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && |
5176 | !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) | |
e315cd28 | 5177 | && vha->flags.online) { |
1da177e4 | 5178 | |
e315cd28 AC |
5179 | if (atomic_read(&vha->loop_down_timer) == |
5180 | vha->loop_down_abort_time) { | |
1da177e4 | 5181 | |
7c3df132 SK |
5182 | ql_log(ql_log_info, vha, 0x6008, |
5183 | "Loop down - aborting the queues before time expires.\n"); | |
1da177e4 | 5184 | |
e315cd28 AC |
5185 | if (!IS_QLA2100(ha) && vha->link_down_timeout) |
5186 | atomic_set(&vha->loop_state, LOOP_DEAD); | |
1da177e4 | 5187 | |
f08b7251 AV |
5188 | /* |
5189 | * Schedule an ISP abort to return any FCP2-device | |
5190 | * commands. | |
5191 | */ | |
2c3dfe3f | 5192 | /* NPIV - scan physical port only */ |
e315cd28 | 5193 | if (!vha->vp_idx) { |
2c3dfe3f SJ |
5194 | spin_lock_irqsave(&ha->hardware_lock, |
5195 | cpu_flags); | |
73208dfd | 5196 | req = ha->req_q_map[0]; |
2c3dfe3f | 5197 | for (index = 1; |
8d93f550 | 5198 | index < req->num_outstanding_cmds; |
2c3dfe3f SJ |
5199 | index++) { |
5200 | fc_port_t *sfcp; | |
5201 | ||
e315cd28 | 5202 | sp = req->outstanding_cmds[index]; |
2c3dfe3f SJ |
5203 | if (!sp) |
5204 | continue; | |
9ba56b95 | 5205 | if (sp->type != SRB_SCSI_CMD) |
cf53b069 | 5206 | continue; |
2c3dfe3f | 5207 | sfcp = sp->fcport; |
f08b7251 | 5208 | if (!(sfcp->flags & FCF_FCP2_DEVICE)) |
2c3dfe3f | 5209 | continue; |
bdf79621 | 5210 | |
8f7daead GM |
5211 | if (IS_QLA82XX(ha)) |
5212 | set_bit(FCOE_CTX_RESET_NEEDED, | |
5213 | &vha->dpc_flags); | |
5214 | else | |
5215 | set_bit(ISP_ABORT_NEEDED, | |
e315cd28 | 5216 | &vha->dpc_flags); |
2c3dfe3f SJ |
5217 | break; |
5218 | } | |
5219 | spin_unlock_irqrestore(&ha->hardware_lock, | |
e315cd28 | 5220 | cpu_flags); |
1da177e4 | 5221 | } |
1da177e4 LT |
5222 | start_dpc++; |
5223 | } | |
5224 | ||
5225 | /* if the loop has been down for 4 minutes, reinit adapter */ | |
e315cd28 | 5226 | if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { |
0d6e61bc | 5227 | if (!(vha->device_flags & DFLG_NO_CABLE)) { |
7c3df132 | 5228 | ql_log(ql_log_warn, vha, 0x6009, |
1da177e4 LT |
5229 | "Loop down - aborting ISP.\n"); |
5230 | ||
8f7daead GM |
5231 | if (IS_QLA82XX(ha)) |
5232 | set_bit(FCOE_CTX_RESET_NEEDED, | |
5233 | &vha->dpc_flags); | |
5234 | else | |
5235 | set_bit(ISP_ABORT_NEEDED, | |
5236 | &vha->dpc_flags); | |
1da177e4 LT |
5237 | } |
5238 | } | |
7c3df132 SK |
5239 | ql_dbg(ql_dbg_timer, vha, 0x600a, |
5240 | "Loop down - seconds remaining %d.\n", | |
5241 | atomic_read(&vha->loop_down_timer)); | |
1da177e4 | 5242 | } |
cefcaba6 SK |
5243 | /* Check if beacon LED needs to be blinked for physical host only */ |
5244 | if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { | |
999916dc | 5245 | /* There is no beacon_blink function for ISP82xx */ |
7ec0effd | 5246 | if (!IS_P3P_TYPE(ha)) { |
999916dc SK |
5247 | set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); |
5248 | start_dpc++; | |
5249 | } | |
f6df144c AV |
5250 | } |
5251 | ||
550bf57d | 5252 | /* Process any deferred work. */ |
e315cd28 | 5253 | if (!list_empty(&vha->work_list)) |
550bf57d AV |
5254 | start_dpc++; |
5255 | ||
1da177e4 | 5256 | /* Schedule the DPC routine if needed */ |
e315cd28 AC |
5257 | if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || |
5258 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || | |
5259 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) || | |
1da177e4 | 5260 | start_dpc || |
e315cd28 AC |
5261 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || |
5262 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || | |
a9083016 GM |
5263 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || |
5264 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | |
e315cd28 | 5265 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || |
50280c01 | 5266 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) { |
7c3df132 SK |
5267 | ql_dbg(ql_dbg_timer, vha, 0x600b, |
5268 | "isp_abort_needed=%d loop_resync_needed=%d " | |
5269 | "fcport_update_needed=%d start_dpc=%d " | |
5270 | "reset_marker_needed=%d", | |
5271 | test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), | |
5272 | test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), | |
5273 | test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags), | |
5274 | start_dpc, | |
5275 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); | |
5276 | ql_dbg(ql_dbg_timer, vha, 0x600c, | |
5277 | "beacon_blink_needed=%d isp_unrecoverable=%d " | |
5278 | "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " | |
50280c01 | 5279 | "relogin_needed=%d.\n", |
7c3df132 SK |
5280 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), |
5281 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), | |
5282 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), | |
5283 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags), | |
50280c01 | 5284 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags)); |
e315cd28 | 5285 | qla2xxx_wake_dpc(vha); |
7c3df132 | 5286 | } |
1da177e4 | 5287 | |
e315cd28 | 5288 | qla2x00_restart_timer(vha, WATCH_INTERVAL); |
1da177e4 LT |
5289 | } |
5290 | ||
5433383e AV |
5291 | /* Firmware interface routines. */ |
5292 | ||
f73cb695 | 5293 | #define FW_BLOBS 11 |
5433383e AV |
5294 | #define FW_ISP21XX 0 |
5295 | #define FW_ISP22XX 1 | |
5296 | #define FW_ISP2300 2 | |
5297 | #define FW_ISP2322 3 | |
48c02fde | 5298 | #define FW_ISP24XX 4 |
c3a2f0df | 5299 | #define FW_ISP25XX 5 |
3a03eb79 | 5300 | #define FW_ISP81XX 6 |
a9083016 | 5301 | #define FW_ISP82XX 7 |
6246b8a1 GM |
5302 | #define FW_ISP2031 8 |
5303 | #define FW_ISP8031 9 | |
2c5bbbb2 | 5304 | #define FW_ISP27XX 10 |
5433383e | 5305 | |
bb8ee499 AV |
5306 | #define FW_FILE_ISP21XX "ql2100_fw.bin" |
5307 | #define FW_FILE_ISP22XX "ql2200_fw.bin" | |
5308 | #define FW_FILE_ISP2300 "ql2300_fw.bin" | |
5309 | #define FW_FILE_ISP2322 "ql2322_fw.bin" | |
5310 | #define FW_FILE_ISP24XX "ql2400_fw.bin" | |
c3a2f0df | 5311 | #define FW_FILE_ISP25XX "ql2500_fw.bin" |
3a03eb79 | 5312 | #define FW_FILE_ISP81XX "ql8100_fw.bin" |
a9083016 | 5313 | #define FW_FILE_ISP82XX "ql8200_fw.bin" |
6246b8a1 GM |
5314 | #define FW_FILE_ISP2031 "ql2600_fw.bin" |
5315 | #define FW_FILE_ISP8031 "ql8300_fw.bin" | |
2c5bbbb2 | 5316 | #define FW_FILE_ISP27XX "ql2700_fw.bin" |
f73cb695 | 5317 | |
bb8ee499 | 5318 | |
e1e82b6f | 5319 | static DEFINE_MUTEX(qla_fw_lock); |
5433383e AV |
5320 | |
5321 | static struct fw_blob qla_fw_blobs[FW_BLOBS] = { | |
bb8ee499 AV |
5322 | { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, |
5323 | { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, | |
5324 | { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, | |
5325 | { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, | |
5326 | { .name = FW_FILE_ISP24XX, }, | |
c3a2f0df | 5327 | { .name = FW_FILE_ISP25XX, }, |
3a03eb79 | 5328 | { .name = FW_FILE_ISP81XX, }, |
a9083016 | 5329 | { .name = FW_FILE_ISP82XX, }, |
6246b8a1 GM |
5330 | { .name = FW_FILE_ISP2031, }, |
5331 | { .name = FW_FILE_ISP8031, }, | |
2c5bbbb2 | 5332 | { .name = FW_FILE_ISP27XX, }, |
5433383e AV |
5333 | }; |
5334 | ||
5335 | struct fw_blob * | |
e315cd28 | 5336 | qla2x00_request_firmware(scsi_qla_host_t *vha) |
5433383e | 5337 | { |
e315cd28 | 5338 | struct qla_hw_data *ha = vha->hw; |
5433383e AV |
5339 | struct fw_blob *blob; |
5340 | ||
5433383e AV |
5341 | if (IS_QLA2100(ha)) { |
5342 | blob = &qla_fw_blobs[FW_ISP21XX]; | |
5343 | } else if (IS_QLA2200(ha)) { | |
5344 | blob = &qla_fw_blobs[FW_ISP22XX]; | |
48c02fde | 5345 | } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { |
5433383e | 5346 | blob = &qla_fw_blobs[FW_ISP2300]; |
48c02fde | 5347 | } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { |
5433383e | 5348 | blob = &qla_fw_blobs[FW_ISP2322]; |
4d4df193 | 5349 | } else if (IS_QLA24XX_TYPE(ha)) { |
5433383e | 5350 | blob = &qla_fw_blobs[FW_ISP24XX]; |
c3a2f0df AV |
5351 | } else if (IS_QLA25XX(ha)) { |
5352 | blob = &qla_fw_blobs[FW_ISP25XX]; | |
3a03eb79 AV |
5353 | } else if (IS_QLA81XX(ha)) { |
5354 | blob = &qla_fw_blobs[FW_ISP81XX]; | |
a9083016 GM |
5355 | } else if (IS_QLA82XX(ha)) { |
5356 | blob = &qla_fw_blobs[FW_ISP82XX]; | |
6246b8a1 GM |
5357 | } else if (IS_QLA2031(ha)) { |
5358 | blob = &qla_fw_blobs[FW_ISP2031]; | |
5359 | } else if (IS_QLA8031(ha)) { | |
5360 | blob = &qla_fw_blobs[FW_ISP8031]; | |
2c5bbbb2 JC |
5361 | } else if (IS_QLA27XX(ha)) { |
5362 | blob = &qla_fw_blobs[FW_ISP27XX]; | |
8a655229 DC |
5363 | } else { |
5364 | return NULL; | |
5433383e AV |
5365 | } |
5366 | ||
e1e82b6f | 5367 | mutex_lock(&qla_fw_lock); |
5433383e AV |
5368 | if (blob->fw) |
5369 | goto out; | |
5370 | ||
5371 | if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { | |
7c3df132 SK |
5372 | ql_log(ql_log_warn, vha, 0x0063, |
5373 | "Failed to load firmware image (%s).\n", blob->name); | |
5433383e AV |
5374 | blob->fw = NULL; |
5375 | blob = NULL; | |
5376 | goto out; | |
5377 | } | |
5378 | ||
5379 | out: | |
e1e82b6f | 5380 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
5381 | return blob; |
5382 | } | |
5383 | ||
5384 | static void | |
5385 | qla2x00_release_firmware(void) | |
5386 | { | |
5387 | int idx; | |
5388 | ||
e1e82b6f | 5389 | mutex_lock(&qla_fw_lock); |
5433383e | 5390 | for (idx = 0; idx < FW_BLOBS; idx++) |
cf92549f | 5391 | release_firmware(qla_fw_blobs[idx].fw); |
e1e82b6f | 5392 | mutex_unlock(&qla_fw_lock); |
5433383e AV |
5393 | } |
5394 | ||
14e660e6 SJ |
5395 | static pci_ers_result_t |
5396 | qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) | |
5397 | { | |
85880801 AV |
5398 | scsi_qla_host_t *vha = pci_get_drvdata(pdev); |
5399 | struct qla_hw_data *ha = vha->hw; | |
5400 | ||
7c3df132 SK |
5401 | ql_dbg(ql_dbg_aer, vha, 0x9000, |
5402 | "PCI error detected, state %x.\n", state); | |
b9b12f73 | 5403 | |
14e660e6 SJ |
5404 | switch (state) { |
5405 | case pci_channel_io_normal: | |
85880801 | 5406 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
5407 | return PCI_ERS_RESULT_CAN_RECOVER; |
5408 | case pci_channel_io_frozen: | |
85880801 | 5409 | ha->flags.eeh_busy = 1; |
a5b36321 LC |
5410 | /* For ISP82XX complete any pending mailbox cmd */ |
5411 | if (IS_QLA82XX(ha)) { | |
7190575f | 5412 | ha->flags.isp82xx_fw_hung = 1; |
c8f6544e CD |
5413 | ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n"); |
5414 | qla82xx_clear_pending_mbx(vha); | |
a5b36321 | 5415 | } |
90a86fc0 | 5416 | qla2x00_free_irqs(vha); |
14e660e6 | 5417 | pci_disable_device(pdev); |
bddd2d65 LC |
5418 | /* Return back all IOs */ |
5419 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | |
14e660e6 SJ |
5420 | return PCI_ERS_RESULT_NEED_RESET; |
5421 | case pci_channel_io_perm_failure: | |
85880801 AV |
5422 | ha->flags.pci_channel_io_perm_failure = 1; |
5423 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | |
14e660e6 SJ |
5424 | return PCI_ERS_RESULT_DISCONNECT; |
5425 | } | |
5426 | return PCI_ERS_RESULT_NEED_RESET; | |
5427 | } | |
5428 | ||
5429 | static pci_ers_result_t | |
5430 | qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) | |
5431 | { | |
5432 | int risc_paused = 0; | |
5433 | uint32_t stat; | |
5434 | unsigned long flags; | |
e315cd28 AC |
5435 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
5436 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
5437 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
5438 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; | |
5439 | ||
bcc5b6d3 SK |
5440 | if (IS_QLA82XX(ha)) |
5441 | return PCI_ERS_RESULT_RECOVERED; | |
5442 | ||
14e660e6 SJ |
5443 | spin_lock_irqsave(&ha->hardware_lock, flags); |
5444 | if (IS_QLA2100(ha) || IS_QLA2200(ha)){ | |
5445 | stat = RD_REG_DWORD(®->hccr); | |
5446 | if (stat & HCCR_RISC_PAUSE) | |
5447 | risc_paused = 1; | |
5448 | } else if (IS_QLA23XX(ha)) { | |
5449 | stat = RD_REG_DWORD(®->u.isp2300.host_status); | |
5450 | if (stat & HSR_RISC_PAUSED) | |
5451 | risc_paused = 1; | |
5452 | } else if (IS_FWI2_CAPABLE(ha)) { | |
5453 | stat = RD_REG_DWORD(®24->host_status); | |
5454 | if (stat & HSRX_RISC_PAUSED) | |
5455 | risc_paused = 1; | |
5456 | } | |
5457 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | |
5458 | ||
5459 | if (risc_paused) { | |
7c3df132 SK |
5460 | ql_log(ql_log_info, base_vha, 0x9003, |
5461 | "RISC paused -- mmio_enabled, Dumping firmware.\n"); | |
e315cd28 | 5462 | ha->isp_ops->fw_dump(base_vha, 0); |
14e660e6 SJ |
5463 | |
5464 | return PCI_ERS_RESULT_NEED_RESET; | |
5465 | } else | |
5466 | return PCI_ERS_RESULT_RECOVERED; | |
5467 | } | |
5468 | ||
fa492630 SK |
5469 | static uint32_t |
5470 | qla82xx_error_recovery(scsi_qla_host_t *base_vha) | |
a5b36321 LC |
5471 | { |
5472 | uint32_t rval = QLA_FUNCTION_FAILED; | |
5473 | uint32_t drv_active = 0; | |
5474 | struct qla_hw_data *ha = base_vha->hw; | |
5475 | int fn; | |
5476 | struct pci_dev *other_pdev = NULL; | |
5477 | ||
7c3df132 SK |
5478 | ql_dbg(ql_dbg_aer, base_vha, 0x9006, |
5479 | "Entered %s.\n", __func__); | |
a5b36321 LC |
5480 | |
5481 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5482 | ||
5483 | if (base_vha->flags.online) { | |
5484 | /* Abort all outstanding commands, | |
5485 | * so as to be requeued later */ | |
5486 | qla2x00_abort_isp_cleanup(base_vha); | |
5487 | } | |
5488 | ||
5489 | ||
5490 | fn = PCI_FUNC(ha->pdev->devfn); | |
5491 | while (fn > 0) { | |
5492 | fn--; | |
7c3df132 SK |
5493 | ql_dbg(ql_dbg_aer, base_vha, 0x9007, |
5494 | "Finding pci device at function = 0x%x.\n", fn); | |
a5b36321 LC |
5495 | other_pdev = |
5496 | pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus), | |
5497 | ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn), | |
5498 | fn)); | |
5499 | ||
5500 | if (!other_pdev) | |
5501 | continue; | |
5502 | if (atomic_read(&other_pdev->enable_cnt)) { | |
7c3df132 SK |
5503 | ql_dbg(ql_dbg_aer, base_vha, 0x9008, |
5504 | "Found PCI func available and enable at 0x%x.\n", | |
5505 | fn); | |
a5b36321 LC |
5506 | pci_dev_put(other_pdev); |
5507 | break; | |
5508 | } | |
5509 | pci_dev_put(other_pdev); | |
5510 | } | |
5511 | ||
5512 | if (!fn) { | |
5513 | /* Reset owner */ | |
7c3df132 SK |
5514 | ql_dbg(ql_dbg_aer, base_vha, 0x9009, |
5515 | "This devfn is reset owner = 0x%x.\n", | |
5516 | ha->pdev->devfn); | |
a5b36321 LC |
5517 | qla82xx_idc_lock(ha); |
5518 | ||
5519 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
7d613ac6 | 5520 | QLA8XXX_DEV_INITIALIZING); |
a5b36321 LC |
5521 | |
5522 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, | |
5523 | QLA82XX_IDC_VERSION); | |
5524 | ||
5525 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | |
7c3df132 SK |
5526 | ql_dbg(ql_dbg_aer, base_vha, 0x900a, |
5527 | "drv_active = 0x%x.\n", drv_active); | |
a5b36321 LC |
5528 | |
5529 | qla82xx_idc_unlock(ha); | |
5530 | /* Reset if device is not already reset | |
5531 | * drv_active would be 0 if a reset has already been done | |
5532 | */ | |
5533 | if (drv_active) | |
5534 | rval = qla82xx_start_firmware(base_vha); | |
5535 | else | |
5536 | rval = QLA_SUCCESS; | |
5537 | qla82xx_idc_lock(ha); | |
5538 | ||
5539 | if (rval != QLA_SUCCESS) { | |
7c3df132 SK |
5540 | ql_log(ql_log_info, base_vha, 0x900b, |
5541 | "HW State: FAILED.\n"); | |
a5b36321 LC |
5542 | qla82xx_clear_drv_active(ha); |
5543 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | |
7d613ac6 | 5544 | QLA8XXX_DEV_FAILED); |
a5b36321 | 5545 | } else { |
7c3df132 SK |
5546 | ql_log(ql_log_info, base_vha, 0x900c, |
5547 | "HW State: READY.\n"); | |
a5b36321 | 5548 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, |
7d613ac6 | 5549 | QLA8XXX_DEV_READY); |
a5b36321 | 5550 | qla82xx_idc_unlock(ha); |
7190575f | 5551 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
5552 | rval = qla82xx_restart_isp(base_vha); |
5553 | qla82xx_idc_lock(ha); | |
5554 | /* Clear driver state register */ | |
5555 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | |
5556 | qla82xx_set_drv_active(base_vha); | |
5557 | } | |
5558 | qla82xx_idc_unlock(ha); | |
5559 | } else { | |
7c3df132 SK |
5560 | ql_dbg(ql_dbg_aer, base_vha, 0x900d, |
5561 | "This devfn is not reset owner = 0x%x.\n", | |
5562 | ha->pdev->devfn); | |
a5b36321 | 5563 | if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) == |
7d613ac6 | 5564 | QLA8XXX_DEV_READY)) { |
7190575f | 5565 | ha->flags.isp82xx_fw_hung = 0; |
a5b36321 LC |
5566 | rval = qla82xx_restart_isp(base_vha); |
5567 | qla82xx_idc_lock(ha); | |
5568 | qla82xx_set_drv_active(base_vha); | |
5569 | qla82xx_idc_unlock(ha); | |
5570 | } | |
5571 | } | |
5572 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | |
5573 | ||
5574 | return rval; | |
5575 | } | |
5576 | ||
14e660e6 SJ |
5577 | static pci_ers_result_t |
5578 | qla2xxx_pci_slot_reset(struct pci_dev *pdev) | |
5579 | { | |
5580 | pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; | |
e315cd28 AC |
5581 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
5582 | struct qla_hw_data *ha = base_vha->hw; | |
90a86fc0 JC |
5583 | struct rsp_que *rsp; |
5584 | int rc, retries = 10; | |
09483916 | 5585 | |
7c3df132 SK |
5586 | ql_dbg(ql_dbg_aer, base_vha, 0x9004, |
5587 | "Slot Reset.\n"); | |
85880801 | 5588 | |
90a86fc0 JC |
5589 | /* Workaround: qla2xxx driver which access hardware earlier |
5590 | * needs error state to be pci_channel_io_online. | |
5591 | * Otherwise mailbox command timesout. | |
5592 | */ | |
5593 | pdev->error_state = pci_channel_io_normal; | |
5594 | ||
5595 | pci_restore_state(pdev); | |
5596 | ||
8c1496bd RL |
5597 | /* pci_restore_state() clears the saved_state flag of the device |
5598 | * save restored state which resets saved_state flag | |
5599 | */ | |
5600 | pci_save_state(pdev); | |
5601 | ||
09483916 BH |
5602 | if (ha->mem_only) |
5603 | rc = pci_enable_device_mem(pdev); | |
5604 | else | |
5605 | rc = pci_enable_device(pdev); | |
14e660e6 | 5606 | |
09483916 | 5607 | if (rc) { |
7c3df132 | 5608 | ql_log(ql_log_warn, base_vha, 0x9005, |
14e660e6 | 5609 | "Can't re-enable PCI device after reset.\n"); |
a5b36321 | 5610 | goto exit_slot_reset; |
14e660e6 | 5611 | } |
14e660e6 | 5612 | |
90a86fc0 JC |
5613 | rsp = ha->rsp_q_map[0]; |
5614 | if (qla2x00_request_irqs(ha, rsp)) | |
a5b36321 | 5615 | goto exit_slot_reset; |
90a86fc0 | 5616 | |
e315cd28 | 5617 | if (ha->isp_ops->pci_config(base_vha)) |
a5b36321 LC |
5618 | goto exit_slot_reset; |
5619 | ||
5620 | if (IS_QLA82XX(ha)) { | |
5621 | if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) { | |
5622 | ret = PCI_ERS_RESULT_RECOVERED; | |
5623 | goto exit_slot_reset; | |
5624 | } else | |
5625 | goto exit_slot_reset; | |
5626 | } | |
14e660e6 | 5627 | |
90a86fc0 JC |
5628 | while (ha->flags.mbox_busy && retries--) |
5629 | msleep(1000); | |
85880801 | 5630 | |
e315cd28 | 5631 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
a9083016 | 5632 | if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) |
14e660e6 | 5633 | ret = PCI_ERS_RESULT_RECOVERED; |
e315cd28 | 5634 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
14e660e6 | 5635 | |
90a86fc0 | 5636 | |
a5b36321 | 5637 | exit_slot_reset: |
7c3df132 SK |
5638 | ql_dbg(ql_dbg_aer, base_vha, 0x900e, |
5639 | "slot_reset return %x.\n", ret); | |
85880801 | 5640 | |
14e660e6 SJ |
5641 | return ret; |
5642 | } | |
5643 | ||
5644 | static void | |
5645 | qla2xxx_pci_resume(struct pci_dev *pdev) | |
5646 | { | |
e315cd28 AC |
5647 | scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); |
5648 | struct qla_hw_data *ha = base_vha->hw; | |
14e660e6 SJ |
5649 | int ret; |
5650 | ||
7c3df132 SK |
5651 | ql_dbg(ql_dbg_aer, base_vha, 0x900f, |
5652 | "pci_resume.\n"); | |
85880801 | 5653 | |
e315cd28 | 5654 | ret = qla2x00_wait_for_hba_online(base_vha); |
14e660e6 | 5655 | if (ret != QLA_SUCCESS) { |
7c3df132 SK |
5656 | ql_log(ql_log_fatal, base_vha, 0x9002, |
5657 | "The device failed to resume I/O from slot/link_reset.\n"); | |
14e660e6 | 5658 | } |
85880801 | 5659 | |
3e46f031 LC |
5660 | pci_cleanup_aer_uncorrect_error_status(pdev); |
5661 | ||
85880801 | 5662 | ha->flags.eeh_busy = 0; |
14e660e6 SJ |
5663 | } |
5664 | ||
2d5a4c34 HM |
5665 | static void |
5666 | qla83xx_disable_laser(scsi_qla_host_t *vha) | |
5667 | { | |
5668 | uint32_t reg, data, fn; | |
5669 | struct qla_hw_data *ha = vha->hw; | |
5670 | struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24; | |
5671 | ||
5672 | /* pci func #/port # */ | |
5673 | ql_dbg(ql_dbg_init, vha, 0x004b, | |
5674 | "Disabling Laser for hba: %p\n", vha); | |
5675 | ||
5676 | fn = (RD_REG_DWORD(&isp_reg->ctrl_status) & | |
5677 | (BIT_15|BIT_14|BIT_13|BIT_12)); | |
5678 | ||
5679 | fn = (fn >> 12); | |
5680 | ||
5681 | if (fn & 1) | |
5682 | reg = PORT_1_2031; | |
5683 | else | |
5684 | reg = PORT_0_2031; | |
5685 | ||
5686 | data = LASER_OFF_2031; | |
5687 | ||
5688 | qla83xx_wr_reg(vha, reg, data); | |
5689 | } | |
5690 | ||
a55b2d21 | 5691 | static const struct pci_error_handlers qla2xxx_err_handler = { |
14e660e6 SJ |
5692 | .error_detected = qla2xxx_pci_error_detected, |
5693 | .mmio_enabled = qla2xxx_pci_mmio_enabled, | |
5694 | .slot_reset = qla2xxx_pci_slot_reset, | |
5695 | .resume = qla2xxx_pci_resume, | |
5696 | }; | |
5697 | ||
5433383e | 5698 | static struct pci_device_id qla2xxx_pci_tbl[] = { |
47f5e069 AV |
5699 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, |
5700 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, | |
5701 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, | |
5702 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, | |
5703 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, | |
5704 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, | |
5705 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, | |
5706 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, | |
5707 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, | |
4d4df193 | 5708 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, |
47f5e069 AV |
5709 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, |
5710 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, | |
c3a2f0df | 5711 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, |
6246b8a1 | 5712 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, |
3a03eb79 | 5713 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, |
a9083016 | 5714 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, |
650f528f | 5715 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, |
8ae6d9c7 | 5716 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, |
7ec0effd | 5717 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, |
f73cb695 | 5718 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, |
2c5bbbb2 | 5719 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, |
5433383e AV |
5720 | { 0 }, |
5721 | }; | |
5722 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); | |
5723 | ||
fca29703 | 5724 | static struct pci_driver qla2xxx_pci_driver = { |
cb63067a | 5725 | .name = QLA2XXX_DRIVER_NAME, |
0a21ef1e JB |
5726 | .driver = { |
5727 | .owner = THIS_MODULE, | |
5728 | }, | |
fca29703 | 5729 | .id_table = qla2xxx_pci_tbl, |
7ee61397 | 5730 | .probe = qla2x00_probe_one, |
4c993f76 | 5731 | .remove = qla2x00_remove_one, |
e30d1756 | 5732 | .shutdown = qla2x00_shutdown, |
14e660e6 | 5733 | .err_handler = &qla2xxx_err_handler, |
fca29703 AV |
5734 | }; |
5735 | ||
75ef9de1 | 5736 | static const struct file_operations apidev_fops = { |
6a03b4cd | 5737 | .owner = THIS_MODULE, |
6038f373 | 5738 | .llseek = noop_llseek, |
6a03b4cd HZ |
5739 | }; |
5740 | ||
1da177e4 LT |
5741 | /** |
5742 | * qla2x00_module_init - Module initialization. | |
5743 | **/ | |
5744 | static int __init | |
5745 | qla2x00_module_init(void) | |
5746 | { | |
fca29703 AV |
5747 | int ret = 0; |
5748 | ||
1da177e4 | 5749 | /* Allocate cache for SRBs. */ |
354d6b21 | 5750 | srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, |
20c2df83 | 5751 | SLAB_HWCACHE_ALIGN, NULL); |
1da177e4 | 5752 | if (srb_cachep == NULL) { |
7c3df132 SK |
5753 | ql_log(ql_log_fatal, NULL, 0x0001, |
5754 | "Unable to allocate SRB cache...Failing load!.\n"); | |
1da177e4 LT |
5755 | return -ENOMEM; |
5756 | } | |
5757 | ||
2d70c103 NB |
5758 | /* Initialize target kmem_cache and mem_pools */ |
5759 | ret = qlt_init(); | |
5760 | if (ret < 0) { | |
5761 | kmem_cache_destroy(srb_cachep); | |
5762 | return ret; | |
5763 | } else if (ret > 0) { | |
5764 | /* | |
5765 | * If initiator mode is explictly disabled by qlt_init(), | |
5766 | * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from | |
5767 | * performing scsi_scan_target() during LOOP UP event. | |
5768 | */ | |
5769 | qla2xxx_transport_functions.disable_target_scan = 1; | |
5770 | qla2xxx_transport_vport_functions.disable_target_scan = 1; | |
5771 | } | |
5772 | ||
1da177e4 LT |
5773 | /* Derive version string. */ |
5774 | strcpy(qla2x00_version_str, QLA2XXX_VERSION); | |
11010fec | 5775 | if (ql2xextended_error_logging) |
0181944f AV |
5776 | strcat(qla2x00_version_str, "-debug"); |
5777 | ||
1c97a12a AV |
5778 | qla2xxx_transport_template = |
5779 | fc_attach_transport(&qla2xxx_transport_functions); | |
2c3dfe3f SJ |
5780 | if (!qla2xxx_transport_template) { |
5781 | kmem_cache_destroy(srb_cachep); | |
7c3df132 SK |
5782 | ql_log(ql_log_fatal, NULL, 0x0002, |
5783 | "fc_attach_transport failed...Failing load!.\n"); | |
2d70c103 | 5784 | qlt_exit(); |
1da177e4 | 5785 | return -ENODEV; |
2c3dfe3f | 5786 | } |
6a03b4cd HZ |
5787 | |
5788 | apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); | |
5789 | if (apidev_major < 0) { | |
7c3df132 SK |
5790 | ql_log(ql_log_fatal, NULL, 0x0003, |
5791 | "Unable to register char device %s.\n", QLA2XXX_APIDEV); | |
6a03b4cd HZ |
5792 | } |
5793 | ||
2c3dfe3f SJ |
5794 | qla2xxx_transport_vport_template = |
5795 | fc_attach_transport(&qla2xxx_transport_vport_functions); | |
5796 | if (!qla2xxx_transport_vport_template) { | |
5797 | kmem_cache_destroy(srb_cachep); | |
2d70c103 | 5798 | qlt_exit(); |
2c3dfe3f | 5799 | fc_release_transport(qla2xxx_transport_template); |
7c3df132 SK |
5800 | ql_log(ql_log_fatal, NULL, 0x0004, |
5801 | "fc_attach_transport vport failed...Failing load!.\n"); | |
1da177e4 | 5802 | return -ENODEV; |
2c3dfe3f | 5803 | } |
7c3df132 SK |
5804 | ql_log(ql_log_info, NULL, 0x0005, |
5805 | "QLogic Fibre Channel HBA Driver: %s.\n", | |
fd9a29f0 | 5806 | qla2x00_version_str); |
7ee61397 | 5807 | ret = pci_register_driver(&qla2xxx_pci_driver); |
fca29703 AV |
5808 | if (ret) { |
5809 | kmem_cache_destroy(srb_cachep); | |
2d70c103 | 5810 | qlt_exit(); |
fca29703 | 5811 | fc_release_transport(qla2xxx_transport_template); |
2c3dfe3f | 5812 | fc_release_transport(qla2xxx_transport_vport_template); |
7c3df132 SK |
5813 | ql_log(ql_log_fatal, NULL, 0x0006, |
5814 | "pci_register_driver failed...ret=%d Failing load!.\n", | |
5815 | ret); | |
fca29703 AV |
5816 | } |
5817 | return ret; | |
1da177e4 LT |
5818 | } |
5819 | ||
5820 | /** | |
5821 | * qla2x00_module_exit - Module cleanup. | |
5822 | **/ | |
5823 | static void __exit | |
5824 | qla2x00_module_exit(void) | |
5825 | { | |
6a03b4cd | 5826 | unregister_chrdev(apidev_major, QLA2XXX_APIDEV); |
7ee61397 | 5827 | pci_unregister_driver(&qla2xxx_pci_driver); |
5433383e | 5828 | qla2x00_release_firmware(); |
354d6b21 | 5829 | kmem_cache_destroy(srb_cachep); |
2d70c103 | 5830 | qlt_exit(); |
a9083016 GM |
5831 | if (ctx_cachep) |
5832 | kmem_cache_destroy(ctx_cachep); | |
1da177e4 | 5833 | fc_release_transport(qla2xxx_transport_template); |
2c3dfe3f | 5834 | fc_release_transport(qla2xxx_transport_vport_template); |
1da177e4 LT |
5835 | } |
5836 | ||
5837 | module_init(qla2x00_module_init); | |
5838 | module_exit(qla2x00_module_exit); | |
5839 | ||
5840 | MODULE_AUTHOR("QLogic Corporation"); | |
5841 | MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); | |
5842 | MODULE_LICENSE("GPL"); | |
5843 | MODULE_VERSION(QLA2XXX_VERSION); | |
bb8ee499 AV |
5844 | MODULE_FIRMWARE(FW_FILE_ISP21XX); |
5845 | MODULE_FIRMWARE(FW_FILE_ISP22XX); | |
5846 | MODULE_FIRMWARE(FW_FILE_ISP2300); | |
5847 | MODULE_FIRMWARE(FW_FILE_ISP2322); | |
5848 | MODULE_FIRMWARE(FW_FILE_ISP24XX); | |
61623fc3 | 5849 | MODULE_FIRMWARE(FW_FILE_ISP25XX); |
f1458cda SC |
5850 | MODULE_FIRMWARE(FW_FILE_ISP2031); |
5851 | MODULE_FIRMWARE(FW_FILE_ISP8031); | |
5852 | MODULE_FIRMWARE(FW_FILE_ISP27XX); |