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[SCSI] qla2xxx: Parameterize the link speed of hba rather than fcport.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
46152ceb 3 * Copyright (c) 2003-2012 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
1da177e4 50int ql2xlogintimeout = 20;
f2019cb1 51module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 52MODULE_PARM_DESC(ql2xlogintimeout,
53 "Login timeout value in seconds.");
54
a7b61842 55int qlport_down_retry;
f2019cb1 56module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 57MODULE_PARM_DESC(qlport_down_retry,
900d9f98 58 "Maximum number of command retries to a port that returns "
1da177e4
LT		 59 "a PORT-DOWN status.");
60
1da177e4
LT		 61int ql2xplogiabsentdevice;
62module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
63MODULE_PARM_DESC(ql2xplogiabsentdevice,
64 "Option to enable PLOGI to devices that are not present after "
900d9f98 65 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 66 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
67
1da177e4 68int ql2xloginretrycount = 0;
f2019cb1 69module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 70MODULE_PARM_DESC(ql2xloginretrycount,
71 "Specify an alternate value for the NVRAM login retry count.");
72
a7a167bf 73int ql2xallocfwdump = 1;
f2019cb1 74module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 75MODULE_PARM_DESC(ql2xallocfwdump,
76 "Option to enable allocation of memory for a firmware dump "
77 "during HBA initialization. Memory allocation requirements "
78 "vary by ISP type. Default is 1 - allocate memory.");
79
11010fec 80int ql2xextended_error_logging;
27d94035 81module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 82MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 83 "Option to enable extended error logging,\n"
84 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
85 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
86 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
87 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
88 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
89 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
90 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
91 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
92 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 93 "\t\t0x1e400000 - Preferred value for capturing essential "
94 "debug information (equivalent to old "
95 "ql2xextended_error_logging=1).\n"
3ce8866c 96 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 97
a9083016 98int ql2xshiftctondsd = 6;
f2019cb1 99module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 100MODULE_PARM_DESC(ql2xshiftctondsd,
101 "Set to control shifting of command type processing "
102 "based on total number of SG elements.");
103
1da177e4
LT		 104static void qla2x00_free_device(scsi_qla_host_t *);
105
7e47e5ca 106int ql2xfdmienable=1;
f2019cb1 107module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 108MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 109 "Enables FDMI registrations. "
110 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 111
df7baa50
AV		 112#define MAX_Q_DEPTH 32
113static int ql2xmaxqdepth = MAX_Q_DEPTH;
114module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 116 "Maximum queue depth to set for each LUN. "
117 "Default is 32.");
df7baa50 118
9e522cd8
AE		 119int ql2xenabledif = 2;
120module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 121MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
8cb2049c
AE		 123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 125
8cb2049c 126int ql2xenablehba_err_chk = 2;
bad75002
AE		 127module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
130 " Default is 1.\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
bad75002 134
e5896bd5 135int ql2xiidmaenable=1;
f2019cb1 136module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 137MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
140
73208dfd 141int ql2xmaxqueues = 1;
f2019cb1 142module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 143MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
ae68230c
JP		 145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
68ca949c
AC		 147
148int ql2xmultique_tag;
f2019cb1 149module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 150MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 154
155int ql2xfwloadbin;
86e45bf6 156module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
82515920
AV		 202uint ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, uint, S_IRUGO);
204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
1da177e4 221/*
fa2a1ce5 222 * SCSI host template entry points
1da177e4
LT		 223 */
224static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 225static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 226static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 228static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 229static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 230static int qla2xxx_eh_abort(struct scsi_cmnd *);
231static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 232static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 233static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 235
e881a172 236static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7
AV		 237static int qla2x00_change_queue_type(struct scsi_device *, int);
238
a5326f86 239struct scsi_host_template qla2xxx_driver_template = {
1da177e4 240 .module = THIS_MODULE,
cb63067a 241 .name = QLA2XXX_DRIVER_NAME,
a5326f86 242 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 243
244 .eh_abort_handler = qla2xxx_eh_abort,
245 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 246 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 247 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
248 .eh_host_reset_handler = qla2xxx_eh_host_reset,
249
250 .slave_configure = qla2xxx_slave_configure,
251
252 .slave_alloc = qla2xxx_slave_alloc,
253 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 254 .scan_finished = qla2xxx_scan_finished,
255 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 256 .change_queue_depth = qla2x00_change_queue_depth,
257 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 258 .this_id = -1,
259 .cmd_per_lun = 3,
260 .use_clustering = ENABLE_CLUSTERING,
261 .sg_tablesize = SG_ALL,
262
263 .max_sectors = 0xFFFF,
afb046e2 264 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 265
266 .supported_mode = MODE_INITIATOR,
fca29703
AV		 267};
268
1da177e4 269static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 270struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 271
1da177e4
LT		 272/* TODO Convert to inlines
273 *
274 * Timer routines
275 */
1da177e4 276
2c3dfe3f 277__inline__ void
e315cd28 278qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 279{
e315cd28
AC		 280 init_timer(&vha->timer);
281 vha->timer.expires = jiffies + interval * HZ;
282 vha->timer.data = (unsigned long)vha;
283 vha->timer.function = (void (*)(unsigned long))func;
284 add_timer(&vha->timer);
285 vha->timer_active = 1;
1da177e4
LT		 286}
287
288static inline void
e315cd28 289qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 290{
a9083016 291 /* Currently used for 82XX only. */
7c3df132
SK		 292 if (vha->device_flags & DFLG_DEV_FAILED) {
293 ql_dbg(ql_dbg_timer, vha, 0x600d,
294 "Device in a failed state, returning.\n");
a9083016 295 return;
7c3df132 296 }
a9083016 297
e315cd28 298 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 299}
300
a824ebb3 301static __inline__ void
e315cd28 302qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 303{
e315cd28
AC		 304 del_timer_sync(&vha->timer);
305 vha->timer_active = 0;
1da177e4
LT		 306}
307
1da177e4
LT		 308static int qla2x00_do_dpc(void *data);
309
310static void qla2x00_rst_aen(scsi_qla_host_t *);
311
73208dfd
AC		 312static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
313 struct req_que **, struct rsp_que **);
e30d1756 314static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 315static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 316
1da177e4 317/* -------------------------------------------------------------------------- */
9a347ff4
CD		 318static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
319 struct rsp_que *rsp)
73208dfd 320{
7c3df132 321 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 322 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 323 GFP_KERNEL);
324 if (!ha->req_q_map) {
7c3df132
SK		 325 ql_log(ql_log_fatal, vha, 0x003b,
326 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 327 goto fail_req_map;
328 }
329
2afa19a9 330 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 331 GFP_KERNEL);
332 if (!ha->rsp_q_map) {
7c3df132
SK		 333 ql_log(ql_log_fatal, vha, 0x003c,
334 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 335 goto fail_rsp_map;
336 }
9a347ff4
CD		 337 /*
338 * Make sure we record at least the request and response queue zero in
339 * case we need to free them if part of the probe fails.
340 */
341 ha->rsp_q_map[0] = rsp;
342 ha->req_q_map[0] = req;
73208dfd
AC		 343 set_bit(0, ha->rsp_qid_map);
344 set_bit(0, ha->req_qid_map);
345 return 1;
346
347fail_rsp_map:
348 kfree(ha->req_q_map);
349 ha->req_q_map = NULL;
350fail_req_map:
351 return -ENOMEM;
352}
353
2afa19a9 354static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 355{
73208dfd
AC		 356 if (req && req->ring)
357 dma_free_coherent(&ha->pdev->dev,
358 (req->length + 1) * sizeof(request_t),
359 req->ring, req->dma);
360
361 kfree(req);
362 req = NULL;
363}
364
2afa19a9
AC		 365static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
366{
367 if (rsp && rsp->ring)
368 dma_free_coherent(&ha->pdev->dev,
369 (rsp->length + 1) * sizeof(response_t),
370 rsp->ring, rsp->dma);
371
372 kfree(rsp);
373 rsp = NULL;
374}
375
73208dfd
AC		 376static void qla2x00_free_queues(struct qla_hw_data *ha)
377{
378 struct req_que *req;
379 struct rsp_que *rsp;
380 int cnt;
381
2afa19a9 382 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 383 req = ha->req_q_map[cnt];
2afa19a9 384 qla2x00_free_req_que(ha, req);
73208dfd 385 }
73208dfd
AC		 386 kfree(ha->req_q_map);
387 ha->req_q_map = NULL;
2afa19a9
AC		 388
389 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
390 rsp = ha->rsp_q_map[cnt];
391 qla2x00_free_rsp_que(ha, rsp);
392 }
393 kfree(ha->rsp_q_map);
394 ha->rsp_q_map = NULL;
73208dfd
AC		 395}
396
68ca949c
AC		 397static int qla25xx_setup_mode(struct scsi_qla_host *vha)
398{
399 uint16_t options = 0;
400 int ques, req, ret;
401 struct qla_hw_data *ha = vha->hw;
402
7163ea81 403 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 404 ql_log(ql_log_warn, vha, 0x00d8,
405 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 406 goto fail;
407 }
68ca949c 408 if (ql2xmultique_tag) {
68ca949c
AC		 409 /* create a request queue for IO */
410 options |= BIT_7;
411 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
412 QLA_DEFAULT_QUE_QOS);
413 if (!req) {
7c3df132
SK		 414 ql_log(ql_log_warn, vha, 0x00e0,
415 "Failed to create request queue.\n");
68ca949c
AC		 416 goto fail;
417 }
278274d5 418 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 419 vha->req = ha->req_q_map[req];
420 options |= BIT_1;
421 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
422 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
423 if (!ret) {
7c3df132
SK		 424 ql_log(ql_log_warn, vha, 0x00e8,
425 "Failed to create response queue.\n");
68ca949c
AC		 426 goto fail2;
427 }
428 }
7163ea81 429 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 430 ql_dbg(ql_dbg_multiq, vha, 0xc007,
431 "CPU affinity mode enalbed, "
432 "no. of response queues:%d no. of request queues:%d.\n",
433 ha->max_rsp_queues, ha->max_req_queues);
434 ql_dbg(ql_dbg_init, vha, 0x00e9,
435 "CPU affinity mode enalbed, "
436 "no. of response queues:%d no. of request queues:%d.\n",
437 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 438 }
439 return 0;
440fail2:
441 qla25xx_delete_queues(vha);
7163ea81
AC		 442 destroy_workqueue(ha->wq);
443 ha->wq = NULL;
0cd33fcf 444 vha->req = ha->req_q_map[0];
68ca949c
AC		 445fail:
446 ha->mqenable = 0;
7163ea81
AC		 447 kfree(ha->req_q_map);
448 kfree(ha->rsp_q_map);
449 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 450 return 1;
451}
452
1da177e4 453static char *
e315cd28 454qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 455{
e315cd28 456 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 457 static char *pci_bus_modes[] = {
458 "33", "66", "100", "133",
459 };
460 uint16_t pci_bus;
461
462 strcpy(str, "PCI");
463 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
464 if (pci_bus) {
465 strcat(str, "-X (");
466 strcat(str, pci_bus_modes[pci_bus]);
467 } else {
468 pci_bus = (ha->pci_attr & BIT_8) >> 8;
469 strcat(str, " (");
470 strcat(str, pci_bus_modes[pci_bus]);
471 }
472 strcat(str, " MHz)");
473
474 return (str);
475}
476
fca29703 477static char *
e315cd28 478qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 479{
480 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 481 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 482 uint32_t pci_bus;
483 int pcie_reg;
484
e67f1321 485 pcie_reg = pci_pcie_cap(ha->pdev);
fca29703
AV		 486 if (pcie_reg) {
487 char lwstr[6];
488 uint16_t pcie_lstat, lspeed, lwidth;
489
e67f1321 490 pcie_reg += PCI_EXP_LNKCAP;
fca29703
AV		 491 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
492 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
493 lwidth = (pcie_lstat &
494 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
495
496 strcpy(str, "PCIe (");
49300af7
SK		 497 switch (lspeed) {
498 case 1:
c87a0d8c 499 strcat(str, "2.5GT/s ");
49300af7
SK		 500 break;
501 case 2:
c87a0d8c 502 strcat(str, "5.0GT/s ");
49300af7
SK		 503 break;
504 case 3:
505 strcat(str, "8.0GT/s ");
506 break;
507 default:
fca29703 508 strcat(str, "<unknown> ");
49300af7
SK		 509 break;
510 }
fca29703
AV		 511 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
512 strcat(str, lwstr);
513
514 return str;
515 }
516
517 strcpy(str, "PCI");
518 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
519 if (pci_bus == 0 || pci_bus == 8) {
520 strcat(str, " (");
521 strcat(str, pci_bus_modes[pci_bus >> 3]);
522 } else {
523 strcat(str, "-X ");
524 if (pci_bus & BIT_2)
525 strcat(str, "Mode 2");
526 else
527 strcat(str, "Mode 1");
528 strcat(str, " (");
529 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
530 }
531 strcat(str, " MHz)");
532
533 return str;
534}
535
e5f82ab8 536static char *
e315cd28 537qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 538{
539 char un_str[10];
e315cd28 540 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 541
1da177e4
LT		 542 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
543 ha->fw_minor_version,
544 ha->fw_subminor_version);
545
546 if (ha->fw_attributes & BIT_9) {
547 strcat(str, "FLX");
548 return (str);
549 }
550
551 switch (ha->fw_attributes & 0xFF) {
552 case 0x7:
553 strcat(str, "EF");
554 break;
555 case 0x17:
556 strcat(str, "TP");
557 break;
558 case 0x37:
559 strcat(str, "IP");
560 break;
561 case 0x77:
562 strcat(str, "VI");
563 break;
564 default:
565 sprintf(un_str, "(%x)", ha->fw_attributes);
566 strcat(str, un_str);
567 break;
568 }
569 if (ha->fw_attributes & 0x100)
570 strcat(str, "X");
571
572 return (str);
573}
574
e5f82ab8 575static char *
e315cd28 576qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 577{
e315cd28 578 struct qla_hw_data *ha = vha->hw;
f0883ac6 579
3a03eb79
AV		 580 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
581 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 582 return str;
fca29703
AV		 583}
584
9ba56b95
GM		 585void
586qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 587{
9ba56b95
GM		 588 srb_t *sp = (srb_t *)ptr;
589 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
590 struct qla_hw_data *ha = sp->fcport->vha->hw;
591 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 592
9ba56b95
GM		 593 if (sp->flags & SRB_DMA_VALID) {
594 scsi_dma_unmap(cmd);
595 sp->flags &= ~SRB_DMA_VALID;
7c3df132 596 }
fca29703 597
9ba56b95
GM		 598 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
599 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
600 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
601 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
602 }
603
604 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
605 /* List assured to be having elements */
606 qla2x00_clean_dsd_pool(ha, sp);
607 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
608 }
609
610 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
611 dma_pool_free(ha->dl_dma_pool, ctx,
612 ((struct crc_context *)ctx)->crc_ctx_dma);
613 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
614 }
615
616 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
617 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 618
9ba56b95
GM		 619 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
620 ctx1->fcp_cmnd_dma);
621 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
622 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
623 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
624 mempool_free(ctx1, ha->ctx_mempool);
625 ctx1 = NULL;
626 }
627
628 CMD_SP(cmd) = NULL;
629 mempool_free(sp, ha->srb_mempool);
630}
631
632static void
633qla2x00_sp_compl(void *data, void *ptr, int res)
634{
635 struct qla_hw_data *ha = (struct qla_hw_data *)data;
636 srb_t *sp = (srb_t *)ptr;
637 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
638
639 cmd->result = res;
640
641 if (atomic_read(&sp->ref_count) == 0) {
642 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
643 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
644 sp, GET_CMD_SP(sp));
645 if (ql2xextended_error_logging & ql_dbg_io)
646 BUG();
647 return;
648 }
649 if (!atomic_dec_and_test(&sp->ref_count))
650 return;
651
652 qla2x00_sp_free_dma(ha, sp);
653 cmd->scsi_done(cmd);
fca29703
AV		 654}
655
1da177e4 656static int
f5e3e40b 657qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 658{
134ae078 659 scsi_qla_host_t *vha = shost_priv(host);
fca29703 660 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 661 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 662 struct qla_hw_data *ha = vha->hw;
663 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 664 srb_t *sp;
665 int rval;
666
85880801 667 if (ha->flags.eeh_busy) {
7c3df132 668 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 669 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 670 "PCI Channel IO permanent failure, exiting "
671 "cmd=%p.\n", cmd);
b9b12f73 672 cmd->result = DID_NO_CONNECT << 16;
7c3df132 673 } else {
5f28d2d7 674 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 675 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 676 cmd->result = DID_REQUEUE << 16;
7c3df132 677 }
14e660e6
SJ		 678 goto qc24_fail_command;
679 }
680
19a7b4ae
JSEC		 681 rval = fc_remote_port_chkready(rport);
682 if (rval) {
683 cmd->result = rval;
5f28d2d7 684 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 685 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
686 cmd, rval);
fca29703
AV		 687 goto qc24_fail_command;
688 }
689
bad75002
AE		 690 if (!vha->flags.difdix_supported &&
691 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 692 ql_dbg(ql_dbg_io, vha, 0x3004,
693 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
694 cmd);
bad75002
AE		 695 cmd->result = DID_NO_CONNECT << 16;
696 goto qc24_fail_command;
697 }
aa651be8
CD		 698
699 if (!fcport) {
700 cmd->result = DID_NO_CONNECT << 16;
701 goto qc24_fail_command;
702 }
703
fca29703
AV		 704 if (atomic_read(&fcport->state) != FCS_ONLINE) {
705 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 706 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 707 ql_dbg(ql_dbg_io, vha, 0x3005,
708 "Returning DNC, fcport_state=%d loop_state=%d.\n",
709 atomic_read(&fcport->state),
710 atomic_read(&base_vha->loop_state));
fca29703
AV		 711 cmd->result = DID_NO_CONNECT << 16;
712 goto qc24_fail_command;
713 }
7b594131 714 goto qc24_target_busy;
fca29703
AV		 715 }
716
9ba56b95 717 sp = qla2x00_get_sp(base_vha, fcport, GFP_ATOMIC);
fca29703 718 if (!sp)
f5e3e40b 719 goto qc24_host_busy;
fca29703 720
9ba56b95
GM		 721 sp->u.scmd.cmd = cmd;
722 sp->type = SRB_SCSI_CMD;
723 atomic_set(&sp->ref_count, 1);
724 CMD_SP(cmd) = (void *)sp;
725 sp->free = qla2x00_sp_free_dma;
726 sp->done = qla2x00_sp_compl;
727
e315cd28 728 rval = ha->isp_ops->start_scsi(sp);
7c3df132 729 if (rval != QLA_SUCCESS) {
53016ed3 730 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 731 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 732 goto qc24_host_busy_free_sp;
7c3df132 733 }
fca29703 734
fca29703
AV		 735 return 0;
736
737qc24_host_busy_free_sp:
9ba56b95 738 qla2x00_sp_free_dma(ha, sp);
fca29703 739
f5e3e40b 740qc24_host_busy:
fca29703
AV		 741 return SCSI_MLQUEUE_HOST_BUSY;
742
7b594131
MC		 743qc24_target_busy:
744 return SCSI_MLQUEUE_TARGET_BUSY;
745
fca29703 746qc24_fail_command:
f5e3e40b 747 cmd->scsi_done(cmd);
fca29703
AV		 748
749 return 0;
750}
751
1da177e4
LT		 752/*
753 * qla2x00_eh_wait_on_command
754 * Waits for the command to be returned by the Firmware for some
755 * max time.
756 *
757 * Input:
1da177e4 758 * cmd = Scsi Command to wait on.
1da177e4
LT		 759 *
760 * Return:
761 * Not Found : 0
762 * Found : 1
763 */
764static int
e315cd28 765qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 766{
fe74c71f
AV		 767#define ABORT_POLLING_PERIOD 1000
768#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 769 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 770 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
771 struct qla_hw_data *ha = vha->hw;
f4f051eb 772 int ret = QLA_SUCCESS;
1da177e4 773
85880801 774 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 775 ql_dbg(ql_dbg_taskm, vha, 0x8005,
776 "Return:eh_wait.\n");
85880801
AV		 777 return ret;
778 }
779
d970432c 780 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 781 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 782 }
783 if (CMD_SP(cmd))
784 ret = QLA_FUNCTION_FAILED;
1da177e4 785
f4f051eb 786 return ret;
1da177e4
LT		 787}
788
789/*
790 * qla2x00_wait_for_hba_online
fa2a1ce5 791 * Wait till the HBA is online after going through
1da177e4
LT		 792 * <= MAX_RETRIES_OF_ISP_ABORT or
793 * finally HBA is disabled ie marked offline
794 *
795 * Input:
796 * ha - pointer to host adapter structure
fa2a1ce5
AV		 797 *
798 * Note:
1da177e4
LT		 799 * Does context switching-Release SPIN_LOCK
800 * (if any) before calling this routine.
801 *
802 * Return:
803 * Success (Adapter is online) : 0
804 * Failed (Adapter is offline/disabled) : 1
805 */
854165f4 806int
e315cd28 807qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 808{
fca29703
AV		 809 int return_status;
810 unsigned long wait_online;
e315cd28
AC		 811 struct qla_hw_data *ha = vha->hw;
812 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 813
fa2a1ce5 814 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 815 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
816 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
817 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
818 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 819
820 msleep(1000);
821 }
e315cd28 822 if (base_vha->flags.online)
fa2a1ce5 823 return_status = QLA_SUCCESS;
1da177e4
LT		 824 else
825 return_status = QLA_FUNCTION_FAILED;
826
1da177e4
LT		 827 return (return_status);
828}
829
86fbee86
LC		 830/*
831 * qla2x00_wait_for_reset_ready
832 * Wait till the HBA is online after going through
833 * <= MAX_RETRIES_OF_ISP_ABORT or
834 * finally HBA is disabled ie marked offline or flash
835 * operations are in progress.
836 *
837 * Input:
838 * ha - pointer to host adapter structure
839 *
840 * Note:
841 * Does context switching-Release SPIN_LOCK
842 * (if any) before calling this routine.
843 *
844 * Return:
845 * Success (Adapter is online/no flash ops) : 0
846 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
847 */
3dbe756a 848static int
86fbee86
LC		 849qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
850{
851 int return_status;
852 unsigned long wait_online;
853 struct qla_hw_data *ha = vha->hw;
854 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
855
856 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
857 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
858 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
859 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
860 ha->optrom_state != QLA_SWAITING ||
861 ha->dpc_active) && time_before(jiffies, wait_online))
862 msleep(1000);
863
864 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
865 return_status = QLA_SUCCESS;
866 else
867 return_status = QLA_FUNCTION_FAILED;
868
7c3df132
SK		 869 ql_dbg(ql_dbg_taskm, vha, 0x8019,
870 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 871
872 return return_status;
873}
874
2533cf67
LC		 875int
876qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
877{
878 int return_status;
879 unsigned long wait_reset;
880 struct qla_hw_data *ha = vha->hw;
881 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
882
883 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
884 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
885 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
886 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
887 ha->dpc_active) && time_before(jiffies, wait_reset)) {
888
889 msleep(1000);
890
891 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
892 ha->flags.chip_reset_done)
893 break;
894 }
895 if (ha->flags.chip_reset_done)
896 return_status = QLA_SUCCESS;
897 else
898 return_status = QLA_FUNCTION_FAILED;
899
900 return return_status;
901}
902
083a469d
GM		 903static void
904sp_get(struct srb *sp)
905{
906 atomic_inc(&sp->ref_count);
907}
908
1da177e4
LT		 909/**************************************************************************
910* qla2xxx_eh_abort
911*
912* Description:
913* The abort function will abort the specified command.
914*
915* Input:
916* cmd = Linux SCSI command packet to be aborted.
917*
918* Returns:
919* Either SUCCESS or FAILED.
920*
921* Note:
2ea00202 922* Only return FAILED if command not returned by firmware.
1da177e4 923**************************************************************************/
e5f82ab8 924static int
1da177e4
LT		 925qla2xxx_eh_abort(struct scsi_cmnd *cmd)
926{
e315cd28 927 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 928 srb_t *sp;
4e98d3b8 929 int ret;
f4f051eb 930 unsigned int id, lun;
18e144d3 931 unsigned long flags;
2ea00202 932 int wait = 0;
e315cd28 933 struct qla_hw_data *ha = vha->hw;
1da177e4 934
f4f051eb 935 if (!CMD_SP(cmd))
2ea00202 936 return SUCCESS;
1da177e4 937
4e98d3b8
AV		 938 ret = fc_block_scsi_eh(cmd);
939 if (ret != 0)
940 return ret;
941 ret = SUCCESS;
942
f4f051eb
AV		 943 id = cmd->device->id;
944 lun = cmd->device->lun;
1da177e4 945
e315cd28 946 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 947 sp = (srb_t *) CMD_SP(cmd);
948 if (!sp) {
949 spin_unlock_irqrestore(&ha->hardware_lock, flags);
950 return SUCCESS;
951 }
1da177e4 952
7c3df132 953 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 954 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
955 vha->host_no, id, lun, sp, cmd);
17d98630 956
170babc3
MC		 957 /* Get a reference to the sp and drop the lock.*/
958 sp_get(sp);
083a469d 959
e315cd28 960 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 961 if (ha->isp_ops->abort_command(sp)) {
a55aac79 962 ret = FAILED;
7c3df132 963 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 964 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 965 } else {
7c3df132 966 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 967 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 968 wait = 1;
969 }
75942064
SK		 970
971 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 972 sp->done(ha, sp, 0);
75942064 973 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 974
bc91ade9
CD		 975 /* Did the command return during mailbox execution? */
976 if (ret == FAILED && !CMD_SP(cmd))
977 ret = SUCCESS;
978
f4f051eb 979 /* Wait for the command to be returned. */
2ea00202 980 if (wait) {
e315cd28 981 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 982 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 983 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 984 ret = FAILED;
f4f051eb 985 }
1da177e4 986 }
1da177e4 987
7c3df132 988 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 989 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
990 vha->host_no, id, lun, wait, ret);
1da177e4 991
f4f051eb
AV		 992 return ret;
993}
1da177e4 994
4d78c973 995int
e315cd28 996qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 997 unsigned int l, enum nexus_wait_type type)
f4f051eb 998{
17d98630 999 int cnt, match, status;
18e144d3 1000 unsigned long flags;
e315cd28 1001 struct qla_hw_data *ha = vha->hw;
73208dfd 1002 struct req_que *req;
4d78c973 1003 srb_t *sp;
9ba56b95 1004 struct scsi_cmnd *cmd;
1da177e4 1005
523ec773 1006 status = QLA_SUCCESS;
17d98630 1007
e315cd28 1008 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1009 req = vha->req;
17d98630
AC		 1010 for (cnt = 1; status == QLA_SUCCESS &&
1011 cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1012 sp = req->outstanding_cmds[cnt];
1013 if (!sp)
523ec773 1014 continue;
9ba56b95 1015 if (sp->type != SRB_SCSI_CMD)
cf53b069 1016 continue;
17d98630
AC		 1017 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1018 continue;
1019 match = 0;
9ba56b95 1020 cmd = GET_CMD_SP(sp);
17d98630
AC		 1021 switch (type) {
1022 case WAIT_HOST:
1023 match = 1;
1024 break;
1025 case WAIT_TARGET:
9ba56b95 1026 match = cmd->device->id == t;
17d98630
AC		 1027 break;
1028 case WAIT_LUN:
9ba56b95
GM		 1029 match = (cmd->device->id == t &&
1030 cmd->device->lun == l);
17d98630 1031 break;
73208dfd 1032 }
17d98630
AC		 1033 if (!match)
1034 continue;
1035
1036 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1037 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1038 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1039 }
e315cd28 1040 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1041
1042 return status;
1da177e4
LT		 1043}
1044
523ec773
AV		 1045static char *reset_errors[] = {
1046 "HBA not online",
1047 "HBA not ready",
1048 "Task management failed",
1049 "Waiting for command completions",
1050};
1da177e4 1051
e5f82ab8 1052static int
523ec773 1053__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1054 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1055{
e315cd28 1056 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1057 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1058 int err;
1da177e4 1059
7c3df132 1060 if (!fcport) {
523ec773 1061 return FAILED;
7c3df132 1062 }
1da177e4 1063
4e98d3b8
AV		 1064 err = fc_block_scsi_eh(cmd);
1065 if (err != 0)
1066 return err;
1067
7c3df132 1068 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1069 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1070 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1071
523ec773 1072 err = 0;
7c3df132
SK		 1073 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1074 ql_log(ql_log_warn, vha, 0x800a,
1075 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1076 goto eh_reset_failed;
7c3df132 1077 }
523ec773 1078 err = 2;
2afa19a9 1079 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1080 != QLA_SUCCESS) {
1081 ql_log(ql_log_warn, vha, 0x800c,
1082 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1083 goto eh_reset_failed;
7c3df132 1084 }
523ec773 1085 err = 3;
e315cd28 1086 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1087 cmd->device->lun, type) != QLA_SUCCESS) {
1088 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1089 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1090 goto eh_reset_failed;
7c3df132 1091 }
523ec773 1092
7c3df132 1093 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1094 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1095 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1096
1097 return SUCCESS;
1098
4d78c973 1099eh_reset_failed:
7c3df132 1100 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1101 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1102 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1103 cmd);
523ec773
AV		 1104 return FAILED;
1105}
1da177e4 1106
523ec773
AV		 1107static int
1108qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1109{
e315cd28
AC		 1110 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1111 struct qla_hw_data *ha = vha->hw;
1da177e4 1112
523ec773
AV		 1113 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1114 ha->isp_ops->lun_reset);
1da177e4
LT		 1115}
1116
1da177e4 1117static int
523ec773 1118qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1119{
e315cd28
AC		 1120 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1121 struct qla_hw_data *ha = vha->hw;
1da177e4 1122
523ec773
AV		 1123 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1124 ha->isp_ops->target_reset);
1da177e4
LT		 1125}
1126
1da177e4
LT		 1127/**************************************************************************
1128* qla2xxx_eh_bus_reset
1129*
1130* Description:
1131* The bus reset function will reset the bus and abort any executing
1132* commands.
1133*
1134* Input:
1135* cmd = Linux SCSI command packet of the command that cause the
1136* bus reset.
1137*
1138* Returns:
1139* SUCCESS/FAILURE (defined as macro in scsi.h).
1140*
1141**************************************************************************/
e5f82ab8 1142static int
1da177e4
LT		 1143qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1144{
e315cd28 1145 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1146 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1147 int ret = FAILED;
f4f051eb 1148 unsigned int id, lun;
f4f051eb 1149
f4f051eb
AV		 1150 id = cmd->device->id;
1151 lun = cmd->device->lun;
1da177e4 1152
7c3df132 1153 if (!fcport) {
f4f051eb 1154 return ret;
7c3df132 1155 }
1da177e4 1156
4e98d3b8
AV		 1157 ret = fc_block_scsi_eh(cmd);
1158 if (ret != 0)
1159 return ret;
1160 ret = FAILED;
1161
7c3df132 1162 ql_log(ql_log_info, vha, 0x8012,
46270afe 1163 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1164
e315cd28 1165 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1166 ql_log(ql_log_fatal, vha, 0x8013,
1167 "Wait for hba online failed board disabled.\n");
f4f051eb 1168 goto eh_bus_reset_done;
1da177e4
LT		 1169 }
1170
ad537689
SK		 1171 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1172 ret = SUCCESS;
1173
f4f051eb
AV		 1174 if (ret == FAILED)
1175 goto eh_bus_reset_done;
1da177e4 1176
9a41a62b 1177 /* Flush outstanding commands. */
4d78c973 1178 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1179 QLA_SUCCESS) {
1180 ql_log(ql_log_warn, vha, 0x8014,
1181 "Wait for pending commands failed.\n");
9a41a62b 1182 ret = FAILED;
7c3df132 1183 }
1da177e4 1184
f4f051eb 1185eh_bus_reset_done:
7c3df132 1186 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1187 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1188 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1189
f4f051eb 1190 return ret;
1da177e4
LT		 1191}
1192
1193/**************************************************************************
1194* qla2xxx_eh_host_reset
1195*
1196* Description:
1197* The reset function will reset the Adapter.
1198*
1199* Input:
1200* cmd = Linux SCSI command packet of the command that cause the
1201* adapter reset.
1202*
1203* Returns:
1204* Either SUCCESS or FAILED.
1205*
1206* Note:
1207**************************************************************************/
e5f82ab8 1208static int
1da177e4
LT		 1209qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1210{
e315cd28 1211 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1212 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1213 int ret = FAILED;
f4f051eb 1214 unsigned int id, lun;
e315cd28 1215 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1216
f4f051eb
AV		 1217 id = cmd->device->id;
1218 lun = cmd->device->lun;
f4f051eb 1219
7c3df132 1220 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1221 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1222
86fbee86 1223 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1224 goto eh_host_reset_lock;
1da177e4 1225
e315cd28
AC		 1226 if (vha != base_vha) {
1227 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1228 goto eh_host_reset_lock;
e315cd28 1229 } else {
a9083016
GM		 1230 if (IS_QLA82XX(vha->hw)) {
1231 if (!qla82xx_fcoe_ctx_reset(vha)) {
1232 /* Ctx reset success */
1233 ret = SUCCESS;
1234 goto eh_host_reset_lock;
1235 }
1236 /* fall thru if ctx reset failed */
1237 }
68ca949c
AC		 1238 if (ha->wq)
1239 flush_workqueue(ha->wq);
1240
e315cd28 1241 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1242 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1243 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1244 /* failed. schedule dpc to try */
1245 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1246
7c3df132
SK		 1247 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1248 ql_log(ql_log_warn, vha, 0x802a,
1249 "wait for hba online failed.\n");
e315cd28 1250 goto eh_host_reset_lock;
7c3df132 1251 }
e315cd28
AC		 1252 }
1253 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1254 }
1da177e4 1255
e315cd28 1256 /* Waiting for command to be returned to OS.*/
4d78c973 1257 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1258 QLA_SUCCESS)
f4f051eb 1259 ret = SUCCESS;
1da177e4 1260
f4f051eb 1261eh_host_reset_lock:
cfb0919c
CD		 1262 ql_log(ql_log_info, vha, 0x8017,
1263 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1264 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1265
f4f051eb
AV		 1266 return ret;
1267}
1da177e4
LT		 1268
1269/*
1270* qla2x00_loop_reset
1271* Issue loop reset.
1272*
1273* Input:
1274* ha = adapter block pointer.
1275*
1276* Returns:
1277* 0 = success
1278*/
a4722cf2 1279int
e315cd28 1280qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1281{
0c8c39af 1282 int ret;
bdf79621 1283 struct fc_port *fcport;
e315cd28 1284 struct qla_hw_data *ha = vha->hw;
1da177e4 1285
f4c496c1 1286 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1287 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1288 if (fcport->port_type != FCT_TARGET)
1289 continue;
1290
1291 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1292 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1293 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1294 "Bus Reset failed: Target Reset=%d "
1295 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1296 }
1297 }
1298 }
1299
6246b8a1 1300 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
e315cd28 1301 ret = qla2x00_full_login_lip(vha);
0c8c39af 1302 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1303 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1304 "full_login_lip=%d.\n", ret);
749af3d5
AC		 1305 }
1306 atomic_set(&vha->loop_state, LOOP_DOWN);
1307 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1308 qla2x00_mark_all_devices_lost(vha, 0);
0c8c39af
AV		 1309 }
1310
0d6e61bc 1311 if (ha->flags.enable_lip_reset) {
e315cd28 1312 ret = qla2x00_lip_reset(vha);
ad537689 1313 if (ret != QLA_SUCCESS)
7c3df132
SK		 1314 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1315 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1316 }
1317
1da177e4 1318 /* Issue marker command only when we are going to start the I/O */
e315cd28 1319 vha->marker_needed = 1;
1da177e4 1320
0c8c39af 1321 return QLA_SUCCESS;
1da177e4
LT		 1322}
1323
df4bf0bb 1324void
e315cd28 1325qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1326{
73208dfd 1327 int que, cnt;
df4bf0bb
AV		 1328 unsigned long flags;
1329 srb_t *sp;
e315cd28 1330 struct qla_hw_data *ha = vha->hw;
73208dfd 1331 struct req_que *req;
df4bf0bb
AV		 1332
1333 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1334 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1335 req = ha->req_q_map[que];
73208dfd
AC		 1336 if (!req)
1337 continue;
1338 for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) {
1339 sp = req->outstanding_cmds[cnt];
e612d465 1340 if (sp) {
73208dfd 1341 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1342 sp->done(vha, sp, res);
73208dfd 1343 }
df4bf0bb
AV		 1344 }
1345 }
1346 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1347}
1348
f4f051eb
AV		 1349static int
1350qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1351{
bdf79621 1352 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1353
19a7b4ae 1354 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1355 return -ENXIO;
bdf79621 1356
19a7b4ae 1357 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1358
f4f051eb
AV		 1359 return 0;
1360}
1da177e4 1361
f4f051eb
AV		 1362static int
1363qla2xxx_slave_configure(struct scsi_device *sdev)
1364{
e315cd28 1365 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1366 struct req_que *req = vha->req;
8482e118 1367
9e522cd8
AE		 1368 if (IS_T10_PI_CAPABLE(vha->hw))
1369 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1370
f4f051eb 1371 if (sdev->tagged_supported)
73208dfd 1372 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1373 else
73208dfd 1374 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1375 return 0;
1376}
1da177e4 1377
f4f051eb
AV		 1378static void
1379qla2xxx_slave_destroy(struct scsi_device *sdev)
1380{
1381 sdev->hostdata = NULL;
1da177e4
LT		 1382}
1383
c45dd305
GM		 1384static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1385{
1386 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1387
1388 if (!scsi_track_queue_full(sdev, qdepth))
1389 return;
1390
7c3df132 1391 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1392 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1393 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1394}
1395
1396static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1397{
1398 fc_port_t *fcport = sdev->hostdata;
1399 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1400 struct req_que *req = NULL;
1401
1402 req = vha->req;
1403 if (!req)
1404 return;
1405
1406 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1407 return;
1408
1409 if (sdev->ordered_tags)
1410 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1411 else
1412 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1413
7c3df132 1414 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1415 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1416 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1417}
1418
ce7e4af7 1419static int
e881a172 1420qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1421{
c45dd305
GM		 1422 switch (reason) {
1423 case SCSI_QDEPTH_DEFAULT:
1424 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1425 break;
1426 case SCSI_QDEPTH_QFULL:
1427 qla2x00_handle_queue_full(sdev, qdepth);
1428 break;
1429 case SCSI_QDEPTH_RAMP_UP:
1430 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1431 break;
1432 default:
08002af2 1433 return -EOPNOTSUPP;
c45dd305 1434 }
e881a172 1435
ce7e4af7
AV		 1436 return sdev->queue_depth;
1437}
1438
1439static int
1440qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1441{
1442 if (sdev->tagged_supported) {
1443 scsi_set_tag_type(sdev, tag_type);
1444 if (tag_type)
1445 scsi_activate_tcq(sdev, sdev->queue_depth);
1446 else
1447 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1448 } else
1449 tag_type = 0;
1450
1451 return tag_type;
1452}
1453
1da177e4
LT		 1454/**
1455 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1456 * @ha: HA context
1457 *
1458 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1459 * supported addressing method.
1460 */
1461static void
53303c42 1462qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1463{
7524f9b9 1464 /* Assume a 32bit DMA mask. */
1da177e4 1465 ha->flags.enable_64bit_addressing = 0;
1da177e4 1466
6a35528a 1467 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1468 /* Any upper-dword bits set? */
1469 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1470 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1471 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1472 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1473 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1474 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1475 return;
1da177e4 1476 }
1da177e4 1477 }
7524f9b9 1478
284901a9
YH		 1479 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1480 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1481}
1482
fd34f556 1483static void
e315cd28 1484qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1485{
1486 unsigned long flags = 0;
1487 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1488
1489 spin_lock_irqsave(&ha->hardware_lock, flags);
1490 ha->interrupts_on = 1;
1491 /* enable risc and host interrupts */
1492 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1493 RD_REG_WORD(&reg->ictrl);
1494 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1495
1496}
1497
1498static void
e315cd28 1499qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1500{
1501 unsigned long flags = 0;
1502 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1503
1504 spin_lock_irqsave(&ha->hardware_lock, flags);
1505 ha->interrupts_on = 0;
1506 /* disable risc and host interrupts */
1507 WRT_REG_WORD(&reg->ictrl, 0);
1508 RD_REG_WORD(&reg->ictrl);
1509 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1510}
1511
1512static void
e315cd28 1513qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1514{
1515 unsigned long flags = 0;
1516 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1517
1518 spin_lock_irqsave(&ha->hardware_lock, flags);
1519 ha->interrupts_on = 1;
1520 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1521 RD_REG_DWORD(&reg->ictrl);
1522 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1523}
1524
1525static void
e315cd28 1526qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1527{
1528 unsigned long flags = 0;
1529 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1530
124f85e6
AV		 1531 if (IS_NOPOLLING_TYPE(ha))
1532 return;
fd34f556
AV		 1533 spin_lock_irqsave(&ha->hardware_lock, flags);
1534 ha->interrupts_on = 0;
1535 WRT_REG_DWORD(&reg->ictrl, 0);
1536 RD_REG_DWORD(&reg->ictrl);
1537 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1538}
1539
706f457d
GM		 1540static int
1541qla2x00_iospace_config(struct qla_hw_data *ha)
1542{
1543 resource_size_t pio;
1544 uint16_t msix;
1545 int cpus;
1546
706f457d
GM		 1547 if (pci_request_selected_regions(ha->pdev, ha->bars,
1548 QLA2XXX_DRIVER_NAME)) {
1549 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1550 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1551 pci_name(ha->pdev));
1552 goto iospace_error_exit;
1553 }
1554 if (!(ha->bars & 1))
1555 goto skip_pio;
1556
1557 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1558 pio = pci_resource_start(ha->pdev, 0);
1559 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1560 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1561 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1562 "Invalid pci I/O region size (%s).\n",
1563 pci_name(ha->pdev));
1564 pio = 0;
1565 }
1566 } else {
1567 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1568 "Region #0 no a PIO resource (%s).\n",
1569 pci_name(ha->pdev));
1570 pio = 0;
1571 }
1572 ha->pio_address = pio;
1573 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1574 "PIO address=%llu.\n",
1575 (unsigned long long)ha->pio_address);
1576
1577skip_pio:
1578 /* Use MMIO operations for all accesses. */
1579 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1580 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1581 "Region #1 not an MMIO resource (%s), aborting.\n",
1582 pci_name(ha->pdev));
1583 goto iospace_error_exit;
1584 }
1585 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1586 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1587 "Invalid PCI mem region size (%s), aborting.\n",
1588 pci_name(ha->pdev));
1589 goto iospace_error_exit;
1590 }
1591
1592 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1593 if (!ha->iobase) {
1594 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1595 "Cannot remap MMIO (%s), aborting.\n",
1596 pci_name(ha->pdev));
1597 goto iospace_error_exit;
1598 }
1599
1600 /* Determine queue resources */
1601 ha->max_req_queues = ha->max_rsp_queues = 1;
1602 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1603 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1604 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1605 goto mqiobase_exit;
1606
1607 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1608 pci_resource_len(ha->pdev, 3));
1609 if (ha->mqiobase) {
1610 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1611 "MQIO Base=%p.\n", ha->mqiobase);
1612 /* Read MSIX vector size of the board */
1613 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1614 ha->msix_count = msix;
1615 /* Max queues are bounded by available msix vectors */
1616 /* queue 0 uses two msix vectors */
1617 if (ql2xmultique_tag) {
1618 cpus = num_online_cpus();
1619 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1620 (cpus + 1) : (ha->msix_count - 1);
1621 ha->max_req_queues = 2;
1622 } else if (ql2xmaxqueues > 1) {
1623 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1624 QLA_MQ_SIZE : ql2xmaxqueues;
1625 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1626 "QoS mode set, max no of request queues:%d.\n",
1627 ha->max_req_queues);
1628 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1629 "QoS mode set, max no of request queues:%d.\n",
1630 ha->max_req_queues);
1631 }
1632 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1633 "MSI-X vector count: %d.\n", msix);
1634 } else
1635 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1636 "BAR 3 not enabled.\n");
1637
1638mqiobase_exit:
1639 ha->msix_count = ha->max_rsp_queues + 1;
1640 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1641 "MSIX Count:%d.\n", ha->msix_count);
1642 return (0);
1643
1644iospace_error_exit:
1645 return (-ENOMEM);
1646}
1647
1648
6246b8a1
GM		 1649static int
1650qla83xx_iospace_config(struct qla_hw_data *ha)
1651{
1652 uint16_t msix;
1653 int cpus;
1654
1655 if (pci_request_selected_regions(ha->pdev, ha->bars,
1656 QLA2XXX_DRIVER_NAME)) {
1657 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1658 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1659 pci_name(ha->pdev));
1660
1661 goto iospace_error_exit;
1662 }
1663
1664 /* Use MMIO operations for all accesses. */
1665 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1666 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1667 "Invalid pci I/O region size (%s).\n",
1668 pci_name(ha->pdev));
1669 goto iospace_error_exit;
1670 }
1671 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1672 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1673 "Invalid PCI mem region size (%s), aborting\n",
1674 pci_name(ha->pdev));
1675 goto iospace_error_exit;
1676 }
1677
1678 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1679 if (!ha->iobase) {
1680 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1681 "Cannot remap MMIO (%s), aborting.\n",
1682 pci_name(ha->pdev));
1683 goto iospace_error_exit;
1684 }
1685
1686 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1687 /* 83XX 26XX always use MQ type access for queues
1688 * - mbar 2, a.k.a region 4 */
1689 ha->max_req_queues = ha->max_rsp_queues = 1;
1690 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1691 pci_resource_len(ha->pdev, 4));
1692
1693 if (!ha->mqiobase) {
1694 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1695 "BAR2/region4 not enabled\n");
1696 goto mqiobase_exit;
1697 }
1698
1699 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1700 pci_resource_len(ha->pdev, 2));
1701 if (ha->msixbase) {
1702 /* Read MSIX vector size of the board */
1703 pci_read_config_word(ha->pdev,
1704 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1705 ha->msix_count = msix;
1706 /* Max queues are bounded by available msix vectors */
1707 /* queue 0 uses two msix vectors */
1708 if (ql2xmultique_tag) {
1709 cpus = num_online_cpus();
1710 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1711 (cpus + 1) : (ha->msix_count - 1);
1712 ha->max_req_queues = 2;
1713 } else if (ql2xmaxqueues > 1) {
1714 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1715 QLA_MQ_SIZE : ql2xmaxqueues;
1716 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1717 "QoS mode set, max no of request queues:%d.\n",
1718 ha->max_req_queues);
1719 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1720 "QoS mode set, max no of request queues:%d.\n",
1721 ha->max_req_queues);
1722 }
1723 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1724 "MSI-X vector count: %d.\n", msix);
1725 } else
1726 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1727 "BAR 1 not enabled.\n");
1728
1729mqiobase_exit:
1730 ha->msix_count = ha->max_rsp_queues + 1;
1731 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1732 "MSIX Count:%d.\n", ha->msix_count);
1733 return 0;
1734
1735iospace_error_exit:
1736 return -ENOMEM;
1737}
1738
fd34f556
AV		 1739static struct isp_operations qla2100_isp_ops = {
1740 .pci_config = qla2100_pci_config,
1741 .reset_chip = qla2x00_reset_chip,
1742 .chip_diag = qla2x00_chip_diag,
1743 .config_rings = qla2x00_config_rings,
1744 .reset_adapter = qla2x00_reset_adapter,
1745 .nvram_config = qla2x00_nvram_config,
1746 .update_fw_options = qla2x00_update_fw_options,
1747 .load_risc = qla2x00_load_risc,
1748 .pci_info_str = qla2x00_pci_info_str,
1749 .fw_version_str = qla2x00_fw_version_str,
1750 .intr_handler = qla2100_intr_handler,
1751 .enable_intrs = qla2x00_enable_intrs,
1752 .disable_intrs = qla2x00_disable_intrs,
1753 .abort_command = qla2x00_abort_command,
523ec773
AV		 1754 .target_reset = qla2x00_abort_target,
1755 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1756 .fabric_login = qla2x00_login_fabric,
1757 .fabric_logout = qla2x00_fabric_logout,
1758 .calc_req_entries = qla2x00_calc_iocbs_32,
1759 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1760 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1761 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1762 .read_nvram = qla2x00_read_nvram_data,
1763 .write_nvram = qla2x00_write_nvram_data,
1764 .fw_dump = qla2100_fw_dump,
1765 .beacon_on = NULL,
1766 .beacon_off = NULL,
1767 .beacon_blink = NULL,
1768 .read_optrom = qla2x00_read_optrom_data,
1769 .write_optrom = qla2x00_write_optrom_data,
1770 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1771 .start_scsi = qla2x00_start_scsi,
a9083016 1772 .abort_isp = qla2x00_abort_isp,
706f457d 1773 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1774};
1775
1776static struct isp_operations qla2300_isp_ops = {
1777 .pci_config = qla2300_pci_config,
1778 .reset_chip = qla2x00_reset_chip,
1779 .chip_diag = qla2x00_chip_diag,
1780 .config_rings = qla2x00_config_rings,
1781 .reset_adapter = qla2x00_reset_adapter,
1782 .nvram_config = qla2x00_nvram_config,
1783 .update_fw_options = qla2x00_update_fw_options,
1784 .load_risc = qla2x00_load_risc,
1785 .pci_info_str = qla2x00_pci_info_str,
1786 .fw_version_str = qla2x00_fw_version_str,
1787 .intr_handler = qla2300_intr_handler,
1788 .enable_intrs = qla2x00_enable_intrs,
1789 .disable_intrs = qla2x00_disable_intrs,
1790 .abort_command = qla2x00_abort_command,
523ec773
AV		 1791 .target_reset = qla2x00_abort_target,
1792 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1793 .fabric_login = qla2x00_login_fabric,
1794 .fabric_logout = qla2x00_fabric_logout,
1795 .calc_req_entries = qla2x00_calc_iocbs_32,
1796 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1797 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1798 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1799 .read_nvram = qla2x00_read_nvram_data,
1800 .write_nvram = qla2x00_write_nvram_data,
1801 .fw_dump = qla2300_fw_dump,
1802 .beacon_on = qla2x00_beacon_on,
1803 .beacon_off = qla2x00_beacon_off,
1804 .beacon_blink = qla2x00_beacon_blink,
1805 .read_optrom = qla2x00_read_optrom_data,
1806 .write_optrom = qla2x00_write_optrom_data,
1807 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1808 .start_scsi = qla2x00_start_scsi,
a9083016 1809 .abort_isp = qla2x00_abort_isp,
706f457d 1810 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1811};
1812
1813static struct isp_operations qla24xx_isp_ops = {
1814 .pci_config = qla24xx_pci_config,
1815 .reset_chip = qla24xx_reset_chip,
1816 .chip_diag = qla24xx_chip_diag,
1817 .config_rings = qla24xx_config_rings,
1818 .reset_adapter = qla24xx_reset_adapter,
1819 .nvram_config = qla24xx_nvram_config,
1820 .update_fw_options = qla24xx_update_fw_options,
1821 .load_risc = qla24xx_load_risc,
1822 .pci_info_str = qla24xx_pci_info_str,
1823 .fw_version_str = qla24xx_fw_version_str,
1824 .intr_handler = qla24xx_intr_handler,
1825 .enable_intrs = qla24xx_enable_intrs,
1826 .disable_intrs = qla24xx_disable_intrs,
1827 .abort_command = qla24xx_abort_command,
523ec773
AV		 1828 .target_reset = qla24xx_abort_target,
1829 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1830 .fabric_login = qla24xx_login_fabric,
1831 .fabric_logout = qla24xx_fabric_logout,
1832 .calc_req_entries = NULL,
1833 .build_iocbs = NULL,
1834 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1835 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1836 .read_nvram = qla24xx_read_nvram_data,
1837 .write_nvram = qla24xx_write_nvram_data,
1838 .fw_dump = qla24xx_fw_dump,
1839 .beacon_on = qla24xx_beacon_on,
1840 .beacon_off = qla24xx_beacon_off,
1841 .beacon_blink = qla24xx_beacon_blink,
1842 .read_optrom = qla24xx_read_optrom_data,
1843 .write_optrom = qla24xx_write_optrom_data,
1844 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1845 .start_scsi = qla24xx_start_scsi,
a9083016 1846 .abort_isp = qla2x00_abort_isp,
706f457d 1847 .iospace_config = qla2x00_iospace_config,
fd34f556
AV		 1848};
1849
c3a2f0df
AV		 1850static struct isp_operations qla25xx_isp_ops = {
1851 .pci_config = qla25xx_pci_config,
1852 .reset_chip = qla24xx_reset_chip,
1853 .chip_diag = qla24xx_chip_diag,
1854 .config_rings = qla24xx_config_rings,
1855 .reset_adapter = qla24xx_reset_adapter,
1856 .nvram_config = qla24xx_nvram_config,
1857 .update_fw_options = qla24xx_update_fw_options,
1858 .load_risc = qla24xx_load_risc,
1859 .pci_info_str = qla24xx_pci_info_str,
1860 .fw_version_str = qla24xx_fw_version_str,
1861 .intr_handler = qla24xx_intr_handler,
1862 .enable_intrs = qla24xx_enable_intrs,
1863 .disable_intrs = qla24xx_disable_intrs,
1864 .abort_command = qla24xx_abort_command,
523ec773
AV		 1865 .target_reset = qla24xx_abort_target,
1866 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1867 .fabric_login = qla24xx_login_fabric,
1868 .fabric_logout = qla24xx_fabric_logout,
1869 .calc_req_entries = NULL,
1870 .build_iocbs = NULL,
1871 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1872 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1873 .read_nvram = qla25xx_read_nvram_data,
1874 .write_nvram = qla25xx_write_nvram_data,
1875 .fw_dump = qla25xx_fw_dump,
1876 .beacon_on = qla24xx_beacon_on,
1877 .beacon_off = qla24xx_beacon_off,
1878 .beacon_blink = qla24xx_beacon_blink,
338c9161 1879 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1880 .write_optrom = qla24xx_write_optrom_data,
1881 .get_flash_version = qla24xx_get_flash_version,
bad75002 1882 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1883 .abort_isp = qla2x00_abort_isp,
706f457d 1884 .iospace_config = qla2x00_iospace_config,
c3a2f0df
AV		 1885};
1886
3a03eb79
AV		 1887static struct isp_operations qla81xx_isp_ops = {
1888 .pci_config = qla25xx_pci_config,
1889 .reset_chip = qla24xx_reset_chip,
1890 .chip_diag = qla24xx_chip_diag,
1891 .config_rings = qla24xx_config_rings,
1892 .reset_adapter = qla24xx_reset_adapter,
1893 .nvram_config = qla81xx_nvram_config,
1894 .update_fw_options = qla81xx_update_fw_options,
eaac30be 1895 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 1896 .pci_info_str = qla24xx_pci_info_str,
1897 .fw_version_str = qla24xx_fw_version_str,
1898 .intr_handler = qla24xx_intr_handler,
1899 .enable_intrs = qla24xx_enable_intrs,
1900 .disable_intrs = qla24xx_disable_intrs,
1901 .abort_command = qla24xx_abort_command,
1902 .target_reset = qla24xx_abort_target,
1903 .lun_reset = qla24xx_lun_reset,
1904 .fabric_login = qla24xx_login_fabric,
1905 .fabric_logout = qla24xx_fabric_logout,
1906 .calc_req_entries = NULL,
1907 .build_iocbs = NULL,
1908 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1909 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 1910 .read_nvram = NULL,
1911 .write_nvram = NULL,
3a03eb79
AV		 1912 .fw_dump = qla81xx_fw_dump,
1913 .beacon_on = qla24xx_beacon_on,
1914 .beacon_off = qla24xx_beacon_off,
6246b8a1 1915 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 1916 .read_optrom = qla25xx_read_optrom_data,
1917 .write_optrom = qla24xx_write_optrom_data,
1918 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 1919 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1920 .abort_isp = qla2x00_abort_isp,
706f457d 1921 .iospace_config = qla2x00_iospace_config,
a9083016
GM		 1922};
1923
1924static struct isp_operations qla82xx_isp_ops = {
1925 .pci_config = qla82xx_pci_config,
1926 .reset_chip = qla82xx_reset_chip,
1927 .chip_diag = qla24xx_chip_diag,
1928 .config_rings = qla82xx_config_rings,
1929 .reset_adapter = qla24xx_reset_adapter,
1930 .nvram_config = qla81xx_nvram_config,
1931 .update_fw_options = qla24xx_update_fw_options,
1932 .load_risc = qla82xx_load_risc,
9d55ca66 1933 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 1934 .fw_version_str = qla24xx_fw_version_str,
1935 .intr_handler = qla82xx_intr_handler,
1936 .enable_intrs = qla82xx_enable_intrs,
1937 .disable_intrs = qla82xx_disable_intrs,
1938 .abort_command = qla24xx_abort_command,
1939 .target_reset = qla24xx_abort_target,
1940 .lun_reset = qla24xx_lun_reset,
1941 .fabric_login = qla24xx_login_fabric,
1942 .fabric_logout = qla24xx_fabric_logout,
1943 .calc_req_entries = NULL,
1944 .build_iocbs = NULL,
1945 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1946 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1947 .read_nvram = qla24xx_read_nvram_data,
1948 .write_nvram = qla24xx_write_nvram_data,
1949 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 1950 .beacon_on = qla82xx_beacon_on,
1951 .beacon_off = qla82xx_beacon_off,
1952 .beacon_blink = NULL,
a9083016
GM		 1953 .read_optrom = qla82xx_read_optrom_data,
1954 .write_optrom = qla82xx_write_optrom_data,
1955 .get_flash_version = qla24xx_get_flash_version,
1956 .start_scsi = qla82xx_start_scsi,
1957 .abort_isp = qla82xx_abort_isp,
706f457d 1958 .iospace_config = qla82xx_iospace_config,
3a03eb79
AV		 1959};
1960
6246b8a1
GM		 1961static struct isp_operations qla83xx_isp_ops = {
1962 .pci_config = qla25xx_pci_config,
1963 .reset_chip = qla24xx_reset_chip,
1964 .chip_diag = qla24xx_chip_diag,
1965 .config_rings = qla24xx_config_rings,
1966 .reset_adapter = qla24xx_reset_adapter,
1967 .nvram_config = qla81xx_nvram_config,
1968 .update_fw_options = qla81xx_update_fw_options,
1969 .load_risc = qla81xx_load_risc,
1970 .pci_info_str = qla24xx_pci_info_str,
1971 .fw_version_str = qla24xx_fw_version_str,
1972 .intr_handler = qla24xx_intr_handler,
1973 .enable_intrs = qla24xx_enable_intrs,
1974 .disable_intrs = qla24xx_disable_intrs,
1975 .abort_command = qla24xx_abort_command,
1976 .target_reset = qla24xx_abort_target,
1977 .lun_reset = qla24xx_lun_reset,
1978 .fabric_login = qla24xx_login_fabric,
1979 .fabric_logout = qla24xx_fabric_logout,
1980 .calc_req_entries = NULL,
1981 .build_iocbs = NULL,
1982 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1983 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1984 .read_nvram = NULL,
1985 .write_nvram = NULL,
1986 .fw_dump = qla83xx_fw_dump,
1987 .beacon_on = qla24xx_beacon_on,
1988 .beacon_off = qla24xx_beacon_off,
1989 .beacon_blink = qla83xx_beacon_blink,
1990 .read_optrom = qla25xx_read_optrom_data,
1991 .write_optrom = qla24xx_write_optrom_data,
1992 .get_flash_version = qla24xx_get_flash_version,
1993 .start_scsi = qla24xx_dif_start_scsi,
1994 .abort_isp = qla2x00_abort_isp,
1995 .iospace_config = qla83xx_iospace_config,
1996};
1997
ea5b6382 1998static inline void
e315cd28 1999qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2000{
2001 ha->device_type = DT_EXTENDED_IDS;
2002 switch (ha->pdev->device) {
2003 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2004 ha->device_type |= DT_ISP2100;
2005 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2006 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2007 break;
2008 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2009 ha->device_type |= DT_ISP2200;
2010 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2011 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2012 break;
2013 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2014 ha->device_type |= DT_ISP2300;
4a59f71d 2015 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2016 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2017 break;
2018 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2019 ha->device_type |= DT_ISP2312;
4a59f71d 2020 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2021 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2022 break;
2023 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2024 ha->device_type |= DT_ISP2322;
4a59f71d 2025 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2026 if (ha->pdev->subsystem_vendor == 0x1028 &&
2027 ha->pdev->subsystem_device == 0x0170)
2028 ha->device_type |= DT_OEM_001;
441d1072 2029 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2030 break;
2031 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2032 ha->device_type |= DT_ISP6312;
441d1072 2033 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2034 break;
2035 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2036 ha->device_type |= DT_ISP6322;
441d1072 2037 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2038 break;
2039 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2040 ha->device_type |= DT_ISP2422;
4a59f71d 2041 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2042 ha->device_type |= DT_FWI2;
c76f2c01 2043 ha->device_type |= DT_IIDMA;
441d1072 2044 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2045 break;
2046 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2047 ha->device_type |= DT_ISP2432;
4a59f71d 2048 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2049 ha->device_type |= DT_FWI2;
c76f2c01 2050 ha->device_type |= DT_IIDMA;
441d1072 2051 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2052 break;
4d4df193
HK		 2053 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2054 ha->device_type |= DT_ISP8432;
2055 ha->device_type |= DT_ZIO_SUPPORTED;
2056 ha->device_type |= DT_FWI2;
2057 ha->device_type |= DT_IIDMA;
2058 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2059 break;
044cc6c8
AV		 2060 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2061 ha->device_type |= DT_ISP5422;
e428924c 2062 ha->device_type |= DT_FWI2;
441d1072 2063 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2064 break;
044cc6c8
AV		 2065 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2066 ha->device_type |= DT_ISP5432;
e428924c 2067 ha->device_type |= DT_FWI2;
441d1072 2068 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2069 break;
c3a2f0df
AV		 2070 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2071 ha->device_type |= DT_ISP2532;
2072 ha->device_type |= DT_ZIO_SUPPORTED;
2073 ha->device_type |= DT_FWI2;
2074 ha->device_type |= DT_IIDMA;
441d1072 2075 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2076 break;
3a03eb79
AV		 2077 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2078 ha->device_type |= DT_ISP8001;
2079 ha->device_type |= DT_ZIO_SUPPORTED;
2080 ha->device_type |= DT_FWI2;
2081 ha->device_type |= DT_IIDMA;
2082 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2083 break;
a9083016
GM		 2084 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2085 ha->device_type |= DT_ISP8021;
2086 ha->device_type |= DT_ZIO_SUPPORTED;
2087 ha->device_type |= DT_FWI2;
2088 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2089 /* Initialize 82XX ISP flags */
2090 qla82xx_init_flags(ha);
2091 break;
6246b8a1
GM		 2092 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2093 ha->device_type |= DT_ISP2031;
2094 ha->device_type |= DT_ZIO_SUPPORTED;
2095 ha->device_type |= DT_FWI2;
2096 ha->device_type |= DT_IIDMA;
2097 ha->device_type |= DT_T10_PI;
2098 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2099 break;
2100 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2101 ha->device_type |= DT_ISP8031;
2102 ha->device_type |= DT_ZIO_SUPPORTED;
2103 ha->device_type |= DT_FWI2;
2104 ha->device_type |= DT_IIDMA;
2105 ha->device_type |= DT_T10_PI;
2106 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2107 break;
ea5b6382 2108 }
e5b68a61 2109
a9083016
GM		 2110 if (IS_QLA82XX(ha))
2111 ha->port_no = !(ha->portnum & 1);
2112 else
2113 /* Get adapter physical port no from interrupt pin register. */
2114 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2115
e5b68a61
AC		 2116 if (ha->port_no & 1)
2117 ha->flags.port0 = 1;
2118 else
2119 ha->flags.port0 = 0;
7c3df132 2120 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2121 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2122 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 2123}
2124
1e99e33a
AV		 2125static void
2126qla2xxx_scan_start(struct Scsi_Host *shost)
2127{
e315cd28 2128 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2129
cbc8eb67
AV		 2130 if (vha->hw->flags.running_gold_fw)
2131 return;
2132
e315cd28
AC		 2133 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2134 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2135 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2136 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2137}
2138
2139static int
2140qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2141{
e315cd28 2142 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2143
e315cd28 2144 if (!vha->host)
1e99e33a 2145 return 1;
e315cd28 2146 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2147 return 1;
2148
e315cd28 2149 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2150}
2151
1da177e4
LT		 2152/*
2153 * PCI driver interface
2154 */
7ee61397
AV		 2155static int __devinit
2156qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2157{
a1541d5a 2158 int ret = -ENODEV;
1da177e4 2159 struct Scsi_Host *host;
e315cd28
AC		 2160 scsi_qla_host_t *base_vha = NULL;
2161 struct qla_hw_data *ha;
29856e28 2162 char pci_info[30];
7d613ac6 2163 char fw_str[30], wq_name[30];
5433383e 2164 struct scsi_host_template *sht;
642ef983 2165 int bars, mem_only = 0;
e315cd28 2166 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2167 struct req_que *req = NULL;
2168 struct rsp_que *rsp = NULL;
1da177e4 2169
285d0321 2170 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2171 sht = &qla2xxx_driver_template;
5433383e 2172 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2173 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2174 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2175 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2176 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2177 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2178 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2179 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2180 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2181 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031) {
285d0321 2182 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2183 mem_only = 1;
7c3df132
SK		 2184 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2185 "Mem only adapter.\n");
285d0321 2186 }
7c3df132
SK		 2187 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2188 "Bars=%d.\n", bars);
285d0321 2189
09483916
BH		 2190 if (mem_only) {
2191 if (pci_enable_device_mem(pdev))
2192 goto probe_out;
2193 } else {
2194 if (pci_enable_device(pdev))
2195 goto probe_out;
2196 }
285d0321 2197
0927678f
JB		 2198 /* This may fail but that's ok */
2199 pci_enable_pcie_error_reporting(pdev);
285d0321 2200
e315cd28
AC		 2201 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2202 if (!ha) {
7c3df132
SK		 2203 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2204 "Unable to allocate memory for ha.\n");
e315cd28 2205 goto probe_out;
1da177e4 2206 }
7c3df132
SK		 2207 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2208 "Memory allocated for ha=%p.\n", ha);
e315cd28 2209 ha->pdev = pdev;
2d70c103 2210 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2211
2212 /* Clear our data area */
285d0321 2213 ha->bars = bars;
09483916 2214 ha->mem_only = mem_only;
df4bf0bb 2215 spin_lock_init(&ha->hardware_lock);
339aa70e 2216 spin_lock_init(&ha->vport_slock);
a9b6f722 2217 mutex_init(&ha->selflogin_lock);
1da177e4 2218
ea5b6382
AV		 2219 /* Set ISP-type information. */
2220 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2221
2222 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2223 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2224 IS_QLA83XX(ha))
ca79cf66 2225 pdev->needs_freset = 1;
ca79cf66 2226
cba1e47f
CD		 2227 ha->prev_topology = 0;
2228 ha->init_cb_size = sizeof(init_cb_t);
2229 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2230 ha->optrom_size = OPTROM_SIZE_2300;
2231
abbd8870 2232 /* Assign ISP specific operations. */
1da177e4 2233 if (IS_QLA2100(ha)) {
642ef983 2234 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2235 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2236 req_length = REQUEST_ENTRY_CNT_2100;
2237 rsp_length = RESPONSE_ENTRY_CNT_2100;
2238 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2239 ha->gid_list_info_size = 4;
3a03eb79
AV		 2240 ha->flash_conf_off = ~0;
2241 ha->flash_data_off = ~0;
2242 ha->nvram_conf_off = ~0;
2243 ha->nvram_data_off = ~0;
fd34f556 2244 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2245 } else if (IS_QLA2200(ha)) {
642ef983 2246 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2247 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2248 req_length = REQUEST_ENTRY_CNT_2200;
2249 rsp_length = RESPONSE_ENTRY_CNT_2100;
2250 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2251 ha->gid_list_info_size = 4;
3a03eb79
AV		 2252 ha->flash_conf_off = ~0;
2253 ha->flash_data_off = ~0;
2254 ha->nvram_conf_off = ~0;
2255 ha->nvram_data_off = ~0;
fd34f556 2256 ha->isp_ops = &qla2100_isp_ops;
fca29703 2257 } else if (IS_QLA23XX(ha)) {
642ef983 2258 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2259 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2260 req_length = REQUEST_ENTRY_CNT_2200;
2261 rsp_length = RESPONSE_ENTRY_CNT_2300;
2262 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2263 ha->gid_list_info_size = 6;
854165f4
AV		 2264 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2265 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2266 ha->flash_conf_off = ~0;
2267 ha->flash_data_off = ~0;
2268 ha->nvram_conf_off = ~0;
2269 ha->nvram_data_off = ~0;
fd34f556 2270 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2271 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2272 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2273 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2274 req_length = REQUEST_ENTRY_CNT_24XX;
2275 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2276 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2277 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2278 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2279 ha->gid_list_info_size = 8;
854165f4 2280 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2281 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2282 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2283 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2284 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2285 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2286 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2287 } else if (IS_QLA25XX(ha)) {
642ef983 2288 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2289 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2290 req_length = REQUEST_ENTRY_CNT_24XX;
2291 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2292 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2293 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2294 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2295 ha->gid_list_info_size = 8;
2296 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2297 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2298 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2299 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2300 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2301 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2302 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2303 } else if (IS_QLA81XX(ha)) {
642ef983 2304 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2305 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2306 req_length = REQUEST_ENTRY_CNT_24XX;
2307 rsp_length = RESPONSE_ENTRY_CNT_2300;
2308 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2309 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2310 ha->gid_list_info_size = 8;
2311 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2312 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2313 ha->isp_ops = &qla81xx_isp_ops;
2314 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2315 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2316 ha->nvram_conf_off = ~0;
2317 ha->nvram_data_off = ~0;
a9083016 2318 } else if (IS_QLA82XX(ha)) {
642ef983 2319 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2320 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2321 req_length = REQUEST_ENTRY_CNT_82XX;
2322 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2323 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2324 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2325 ha->gid_list_info_size = 8;
2326 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2327 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2328 ha->isp_ops = &qla82xx_isp_ops;
2329 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2330 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2331 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2332 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2333 } else if (IS_QLA83XX(ha)) {
7d613ac6 2334 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2335 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2336 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2337 req_length = REQUEST_ENTRY_CNT_24XX;
2338 rsp_length = RESPONSE_ENTRY_CNT_2300;
2339 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2340 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2341 ha->gid_list_info_size = 8;
2342 ha->optrom_size = OPTROM_SIZE_83XX;
2343 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2344 ha->isp_ops = &qla83xx_isp_ops;
2345 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2346 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2347 ha->nvram_conf_off = ~0;
2348 ha->nvram_data_off = ~0;
1da177e4 2349 }
6246b8a1 2350
7c3df132
SK		 2351 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2352 "mbx_count=%d, req_length=%d, "
2353 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2354 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2355 "max_fibre_devices=%d.\n",
7c3df132
SK		 2356 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2357 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2358 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2359 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2360 "isp_ops=%p, flash_conf_off=%d, "
2361 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2362 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2363 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2364
2365 /* Configure PCI I/O space */
2366 ret = ha->isp_ops->iospace_config(ha);
2367 if (ret)
2368 goto probe_hw_failed;
2369
2370 ql_log_pci(ql_log_info, pdev, 0x001d,
2371 "Found an ISP%04X irq %d iobase 0x%p.\n",
2372 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2373 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2374 init_completion(&ha->mbx_cmd_comp);
2375 complete(&ha->mbx_cmd_comp);
2376 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2377 init_completion(&ha->dcbx_comp);
1da177e4 2378
2c3dfe3f 2379 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2380
53303c42 2381 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2382 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2383 "64 Bit addressing is %s.\n",
2384 ha->flags.enable_64bit_addressing ? "enable" :
2385 "disable");
73208dfd 2386 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2387 if (!ret) {
7c3df132
SK		 2388 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2389 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2390
e315cd28
AC		 2391 goto probe_hw_failed;
2392 }
2393
73208dfd 2394 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2395 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2396 req->max_q_depth = ql2xmaxqdepth;
2397
e315cd28
AC		 2398
2399 base_vha = qla2x00_create_host(sht, ha);
2400 if (!base_vha) {
a1541d5a 2401 ret = -ENOMEM;
6e9f21f3 2402 qla2x00_mem_free(ha);
2afa19a9
AC		 2403 qla2x00_free_req_que(ha, req);
2404 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2405 goto probe_hw_failed;
1da177e4
LT		 2406 }
2407
e315cd28
AC		 2408 pci_set_drvdata(pdev, base_vha);
2409
e315cd28 2410 host = base_vha->host;
2afa19a9 2411 base_vha->req = req;
73208dfd
AC		 2412 host->can_queue = req->length + 128;
2413 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2414 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2415 else
e315cd28
AC		 2416 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2417 base_vha->vp_idx;
58548cb5
GM		 2418
2419 /* Set the SG table size based on ISP type */
2420 if (!IS_FWI2_CAPABLE(ha)) {
2421 if (IS_QLA2100(ha))
2422 host->sg_tablesize = 32;
2423 } else {
2424 if (!IS_QLA82XX(ha))
2425 host->sg_tablesize = QLA_SG_ALL;
2426 }
7c3df132
SK		 2427 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2428 "can_queue=%d, req=%p, "
2429 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2430 host->can_queue, base_vha->req,
2431 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2432 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2433 host->cmd_per_lun = 3;
2434 host->unique_id = host->host_no;
e02587d7 2435 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2436 host->max_cmd_len = 32;
2437 else
2438 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2439 host->max_channel = MAX_BUSES - 1;
82515920 2440 host->max_lun = ql2xmaxlun;
e315cd28 2441 host->transportt = qla2xxx_transport_template;
9a069e19 2442 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2443
7c3df132
SK		 2444 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2445 "max_id=%d this_id=%d "
2446 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2447 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2448 host->this_id, host->cmd_per_lun, host->unique_id,
2449 host->max_cmd_len, host->max_channel, host->max_lun,
2450 host->transportt, sht->vendor_id);
2451
9a347ff4
CD		 2452que_init:
2453 /* Alloc arrays of request and response ring ptrs */
2454 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2455 ql_log(ql_log_fatal, base_vha, 0x003d,
2456 "Failed to allocate memory for queue pointers..."
2457 "aborting.\n");
2458 goto probe_init_failed;
2459 }
2460
2d70c103 2461 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2462
73208dfd
AC		 2463 /* Set up the irqs */
2464 ret = qla2x00_request_irqs(ha, rsp);
2465 if (ret)
6e9f21f3 2466 goto probe_init_failed;
90a86fc0
JC		 2467
2468 pci_save_state(pdev);
2469
9a347ff4 2470 /* Assign back pointers */
2afa19a9
AC		 2471 rsp->req = req;
2472 req->rsp = rsp;
9a347ff4 2473
08029990
AV		 2474 /* FWI2-capable only. */
2475 req->req_q_in = &ha->iobase->isp24.req_q_in;
2476 req->req_q_out = &ha->iobase->isp24.req_q_out;
2477 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2478 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2479 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2480 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2481 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2482 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2483 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2484 }
2485
a9083016
GM		 2486 if (IS_QLA82XX(ha)) {
2487 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2488 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2489 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2490 }
2491
7c3df132
SK		 2492 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2493 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2494 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2495 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2496 "req->req_q_in=%p req->req_q_out=%p "
2497 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2498 req->req_q_in, req->req_q_out,
2499 rsp->rsp_q_in, rsp->rsp_q_out);
2500 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2501 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2502 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2503 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2504 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2505 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2506
7c3df132
SK		 2507 if (qla2x00_initialize_adapter(base_vha)) {
2508 ql_log(ql_log_fatal, base_vha, 0x00d6,
2509 "Failed to initialize adapter - Adapter flags %x.\n",
2510 base_vha->device_flags);
1da177e4 2511
a9083016
GM		 2512 if (IS_QLA82XX(ha)) {
2513 qla82xx_idc_lock(ha);
2514 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2515 QLA8XXX_DEV_FAILED);
a9083016 2516 qla82xx_idc_unlock(ha);
7c3df132
SK		 2517 ql_log(ql_log_fatal, base_vha, 0x00d7,
2518 "HW State: FAILED.\n");
a9083016
GM		 2519 }
2520
a1541d5a 2521 ret = -ENODEV;
1da177e4
LT		 2522 goto probe_failed;
2523 }
2524
7163ea81
AC		 2525 if (ha->mqenable) {
2526 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2527 ql_log(ql_log_warn, base_vha, 0x00ec,
2528 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2529 goto que_init;
2530 }
2531 }
68ca949c 2532
cbc8eb67
AV		 2533 if (ha->flags.running_gold_fw)
2534 goto skip_dpc;
2535
1da177e4
LT		 2536 /*
2537 * Startup the kernel thread for this host adapter
2538 */
39a11240 2539 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2540 "%s_dpc", base_vha->host_str);
39a11240 2541 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2542 ql_log(ql_log_fatal, base_vha, 0x00ed,
2543 "Failed to start DPC thread.\n");
39a11240 2544 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2545 goto probe_failed;
2546 }
7c3df132
SK		 2547 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2548 "DPC thread started successfully.\n");
1da177e4 2549
2d70c103
NB		 2550 /*
2551 * If we're not coming up in initiator mode, we might sit for
2552 * a while without waking up the dpc thread, which leads to a
2553 * stuck process warning. So just kick the dpc once here and
2554 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2555 */
2556 qla2xxx_wake_dpc(base_vha);
2557
81178772
SK		 2558 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2559 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2560 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2561 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2562
2563 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2564 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2565 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2566 INIT_WORK(&ha->idc_state_handler,
2567 qla83xx_idc_state_handler_work);
2568 INIT_WORK(&ha->nic_core_unrecoverable,
2569 qla83xx_nic_core_unrecoverable_work);
2570 }
2571
cbc8eb67 2572skip_dpc:
e315cd28
AC		 2573 list_add_tail(&base_vha->list, &ha->vp_list);
2574 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2575
2576 /* Initialized the timer */
e315cd28 2577 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2578 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2579 "Started qla2x00_timer with "
2580 "interval=%d.\n", WATCH_INTERVAL);
2581 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2582 "Detected hba at address=%p.\n",
2583 ha);
d19044c3 2584
e02587d7 2585 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2586 if (ha->fw_attributes & BIT_4) {
9e522cd8 2587 int prot = 0, guard;
bad75002 2588 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2589 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2590 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2591 if (ql2xenabledif == 1)
2592 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2593 scsi_host_set_prot(host,
8cb2049c 2594 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2595 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2596 | SHOST_DIF_TYPE3_PROTECTION
2597 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2598 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2599 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2600
2601 guard = SHOST_DIX_GUARD_CRC;
2602
2603 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2604 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2605 guard |= SHOST_DIX_GUARD_IP;
2606
2607 scsi_host_set_guard(host, guard);
bad75002
AE		 2608 } else
2609 base_vha->flags.difdix_supported = 0;
2610 }
2611
a9083016
GM		 2612 ha->isp_ops->enable_intrs(ha);
2613
a1541d5a
AV		 2614 ret = scsi_add_host(host, &pdev->dev);
2615 if (ret)
2616 goto probe_failed;
2617
1486400f
MR		 2618 base_vha->flags.init_done = 1;
2619 base_vha->flags.online = 1;
2620
7c3df132
SK		 2621 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2622 "Init done and hba is online.\n");
2623
2d70c103
NB		 2624 if (qla_ini_mode_enabled(base_vha))
2625 scsi_scan_host(host);
2626 else
2627 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2628 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2629
e315cd28 2630 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2631
e315cd28 2632 qla2x00_init_host_attr(base_vha);
a1541d5a 2633
e315cd28 2634 qla2x00_dfs_setup(base_vha);
df613b96 2635
7c3df132
SK		 2636 ql_log(ql_log_info, base_vha, 0x00fb,
2637 "QLogic %s - %s.\n",
2638 ha->model_number, ha->model_desc ? ha->model_desc : "");
2639 ql_log(ql_log_info, base_vha, 0x00fc,
2640 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2641 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2642 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2643 base_vha->host_no,
e315cd28 2644 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2645
2d70c103
NB		 2646 qlt_add_target(ha, base_vha);
2647
1da177e4
LT		 2648 return 0;
2649
6e9f21f3 2650probe_init_failed:
2afa19a9 2651 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2652 ha->req_q_map[0] = NULL;
2653 clear_bit(0, ha->req_qid_map);
2afa19a9 2654 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2655 ha->rsp_q_map[0] = NULL;
2656 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2657 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2658
1da177e4 2659probe_failed:
b9978769
AV		 2660 if (base_vha->timer_active)
2661 qla2x00_stop_timer(base_vha);
2662 base_vha->flags.online = 0;
2663 if (ha->dpc_thread) {
2664 struct task_struct *t = ha->dpc_thread;
2665
2666 ha->dpc_thread = NULL;
2667 kthread_stop(t);
2668 }
2669
e315cd28 2670 qla2x00_free_device(base_vha);
1da177e4 2671
e315cd28 2672 scsi_host_put(base_vha->host);
1da177e4 2673
e315cd28 2674probe_hw_failed:
a9083016
GM		 2675 if (IS_QLA82XX(ha)) {
2676 qla82xx_idc_lock(ha);
2677 qla82xx_clear_drv_active(ha);
2678 qla82xx_idc_unlock(ha);
2679 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2680 if (!ql2xdbwr)
2681 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2682 } else {
2683 if (ha->iobase)
2684 iounmap(ha->iobase);
2685 }
e315cd28
AC		 2686 pci_release_selected_regions(ha->pdev, ha->bars);
2687 kfree(ha);
2688 ha = NULL;
1da177e4 2689
a1541d5a 2690probe_out:
e315cd28 2691 pci_disable_device(pdev);
a1541d5a 2692 return ret;
1da177e4 2693}
1da177e4 2694
2d70c103
NB		 2695static void
2696qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2697{
2698 struct qla_hw_data *ha = vha->hw;
2699 struct task_struct *t = ha->dpc_thread;
2700
2701 if (ha->dpc_thread == NULL)
2702 return;
2703 /*
2704 * qla2xxx_wake_dpc checks for ->dpc_thread
2705 * so we need to zero it out.
2706 */
2707 ha->dpc_thread = NULL;
2708 kthread_stop(t);
2709}
2710
e30d1756
MI		 2711static void
2712qla2x00_shutdown(struct pci_dev *pdev)
2713{
2714 scsi_qla_host_t *vha;
2715 struct qla_hw_data *ha;
2716
2717 vha = pci_get_drvdata(pdev);
2718 ha = vha->hw;
2719
2720 /* Turn-off FCE trace */
2721 if (ha->flags.fce_enabled) {
2722 qla2x00_disable_fce_trace(vha, NULL, NULL);
2723 ha->flags.fce_enabled = 0;
2724 }
2725
2726 /* Turn-off EFT trace */
2727 if (ha->eft)
2728 qla2x00_disable_eft_trace(vha);
2729
2730 /* Stop currently executing firmware. */
2731 qla2x00_try_to_stop_firmware(vha);
2732
2733 /* Turn adapter off line */
2734 vha->flags.online = 0;
2735
2736 /* turn-off interrupts on the card */
2737 if (ha->interrupts_on) {
2738 vha->flags.init_done = 0;
2739 ha->isp_ops->disable_intrs(ha);
2740 }
2741
2742 qla2x00_free_irqs(vha);
2743
2744 qla2x00_free_fw_dump(ha);
2745}
2746
4c993f76 2747static void
7ee61397 2748qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 2749{
feafb7b1 2750 scsi_qla_host_t *base_vha, *vha;
e315cd28 2751 struct qla_hw_data *ha;
feafb7b1 2752 unsigned long flags;
e315cd28 2753
9a347ff4
CD		 2754 /*
2755 * If the PCI device is disabled that means that probe failed and any
2756 * resources should be have cleaned up on probe exit.
2757 */
2758 if (!atomic_read(&pdev->enable_cnt))
2759 return;
2760
e315cd28
AC		 2761 base_vha = pci_get_drvdata(pdev);
2762 ha = base_vha->hw;
2763
2d70c103
NB		 2764 ha->flags.host_shutting_down = 1;
2765
220d36b4 2766 set_bit(UNLOADING, &base_vha->dpc_flags);
43ebf16d
AE		 2767 mutex_lock(&ha->vport_lock);
2768 while (ha->cur_vport_count) {
2769 struct Scsi_Host *scsi_host;
feafb7b1 2770
43ebf16d 2771 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 2772
43ebf16d
AE		 2773 BUG_ON(base_vha->list.next == &ha->vp_list);
2774 /* This assumes first entry in ha->vp_list is always base vha */
2775 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
2776 scsi_host = scsi_host_get(vha->host);
feafb7b1 2777
43ebf16d
AE		 2778 spin_unlock_irqrestore(&ha->vport_slock, flags);
2779 mutex_unlock(&ha->vport_lock);
2780
2781 fc_vport_terminate(vha->fc_vport);
2782 scsi_host_put(vha->host);
feafb7b1 2783
43ebf16d 2784 mutex_lock(&ha->vport_lock);
e315cd28 2785 }
43ebf16d 2786 mutex_unlock(&ha->vport_lock);
1da177e4 2787
7d613ac6
SV		 2788 if (IS_QLA8031(ha)) {
2789 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
2790 "Clearing fcoe driver presence.\n");
2791 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
2792 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
2793 "Error while clearing DRV-Presence.\n");
2794 }
2795
b9978769
AV		 2796 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
2797
e315cd28 2798 qla2x00_dfs_remove(base_vha);
c795c1e4 2799
e315cd28 2800 qla84xx_put_chip(base_vha);
c795c1e4 2801
b9978769
AV		 2802 /* Disable timer */
2803 if (base_vha->timer_active)
2804 qla2x00_stop_timer(base_vha);
2805
2806 base_vha->flags.online = 0;
2807
68ca949c
AC		 2808 /* Flush the work queue and remove it */
2809 if (ha->wq) {
2810 flush_workqueue(ha->wq);
2811 destroy_workqueue(ha->wq);
2812 ha->wq = NULL;
2813 }
2814
7d613ac6
SV		 2815 /* Cancel all work and destroy DPC workqueues */
2816 if (ha->dpc_lp_wq) {
2817 cancel_work_sync(&ha->idc_aen);
2818 destroy_workqueue(ha->dpc_lp_wq);
2819 ha->dpc_lp_wq = NULL;
2820 }
2821
2822 if (ha->dpc_hp_wq) {
2823 cancel_work_sync(&ha->nic_core_reset);
2824 cancel_work_sync(&ha->idc_state_handler);
2825 cancel_work_sync(&ha->nic_core_unrecoverable);
2826 destroy_workqueue(ha->dpc_hp_wq);
2827 ha->dpc_hp_wq = NULL;
2828 }
2829
b9978769
AV		 2830 /* Kill the kernel thread for this host */
2831 if (ha->dpc_thread) {
2832 struct task_struct *t = ha->dpc_thread;
2833
2834 /*
2835 * qla2xxx_wake_dpc checks for ->dpc_thread
2836 * so we need to zero it out.
2837 */
2838 ha->dpc_thread = NULL;
2839 kthread_stop(t);
2840 }
2d70c103 2841 qlt_remove_target(ha, base_vha);
b9978769 2842
e315cd28 2843 qla2x00_free_sysfs_attr(base_vha);
df613b96 2844
e315cd28 2845 fc_remove_host(base_vha->host);
4d4df193 2846
e315cd28 2847 scsi_remove_host(base_vha->host);
1da177e4 2848
e315cd28 2849 qla2x00_free_device(base_vha);
bdf79621 2850
e315cd28 2851 scsi_host_put(base_vha->host);
1da177e4 2852
a9083016 2853 if (IS_QLA82XX(ha)) {
b963752f
GM		 2854 qla82xx_idc_lock(ha);
2855 qla82xx_clear_drv_active(ha);
2856 qla82xx_idc_unlock(ha);
2857
a9083016
GM		 2858 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
2859 if (!ql2xdbwr)
2860 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2861 } else {
2862 if (ha->iobase)
2863 iounmap(ha->iobase);
1da177e4 2864
a9083016
GM		 2865 if (ha->mqiobase)
2866 iounmap(ha->mqiobase);
6246b8a1
GM		 2867
2868 if (IS_QLA83XX(ha) && ha->msixbase)
2869 iounmap(ha->msixbase);
a9083016 2870 }
73208dfd 2871
e315cd28
AC		 2872 pci_release_selected_regions(ha->pdev, ha->bars);
2873 kfree(ha);
2874 ha = NULL;
1da177e4 2875
90a86fc0
JC		 2876 pci_disable_pcie_error_reporting(pdev);
2877
665db93b 2878 pci_disable_device(pdev);
1da177e4
LT		 2879 pci_set_drvdata(pdev, NULL);
2880}
1da177e4
LT		 2881
2882static void
e315cd28 2883qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 2884{
e315cd28 2885 struct qla_hw_data *ha = vha->hw;
1da177e4 2886
85880801
AV		 2887 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2888
2889 /* Disable timer */
2890 if (vha->timer_active)
2891 qla2x00_stop_timer(vha);
2892
2d70c103 2893 qla2x00_stop_dpc_thread(vha);
85880801 2894
2afa19a9 2895 qla25xx_delete_queues(vha);
df613b96 2896 if (ha->flags.fce_enabled)
e315cd28 2897 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 2898
a7a167bf 2899 if (ha->eft)
e315cd28 2900 qla2x00_disable_eft_trace(vha);
a7a167bf 2901
f6ef3b18 2902 /* Stop currently executing firmware. */
e315cd28 2903 qla2x00_try_to_stop_firmware(vha);
1da177e4 2904
85880801
AV		 2905 vha->flags.online = 0;
2906
f6ef3b18 2907 /* turn-off interrupts on the card */
a9083016
GM		 2908 if (ha->interrupts_on) {
2909 vha->flags.init_done = 0;
fd34f556 2910 ha->isp_ops->disable_intrs(ha);
a9083016 2911 }
f6ef3b18 2912
e315cd28 2913 qla2x00_free_irqs(vha);
1da177e4 2914
8867048b
CD		 2915 qla2x00_free_fcports(vha);
2916
e315cd28 2917 qla2x00_mem_free(ha);
73208dfd 2918
08de2844
GM		 2919 qla82xx_md_free(vha);
2920
73208dfd 2921 qla2x00_free_queues(ha);
1da177e4
LT		 2922}
2923
8867048b
CD		 2924void qla2x00_free_fcports(struct scsi_qla_host *vha)
2925{
2926 fc_port_t *fcport, *tfcport;
2927
2928 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
2929 list_del(&fcport->list);
5f16b331 2930 qla2x00_clear_loop_id(fcport);
8867048b
CD		 2931 kfree(fcport);
2932 fcport = NULL;
2933 }
2934}
2935
d97994dc 2936static inline void
e315cd28 2937qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 2938 int defer)
2939{
d97994dc 2940 struct fc_rport *rport;
67becc00 2941 scsi_qla_host_t *base_vha;
044d78e1 2942 unsigned long flags;
d97994dc
AV		 2943
2944 if (!fcport->rport)
2945 return;
2946
2947 rport = fcport->rport;
2948 if (defer) {
67becc00 2949 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 2950 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 2951 fcport->drport = rport;
044d78e1 2952 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 2953 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
2954 qla2xxx_wake_dpc(base_vha);
2d70c103 2955 } else {
d97994dc 2956 fc_remote_port_delete(rport);
2d70c103
NB		 2957 qlt_fc_port_deleted(vha, fcport);
2958 }
d97994dc
AV		 2959}
2960
1da177e4
LT		 2961/*
2962 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
2963 *
2964 * Input: ha = adapter block pointer. fcport = port structure pointer.
2965 *
2966 * Return: None.
2967 *
2968 * Context:
2969 */
e315cd28 2970void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 2971 int do_login, int defer)
1da177e4 2972{
2c3dfe3f 2973 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 2974 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 2975 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 2976 qla2x00_schedule_rport_del(vha, fcport, defer);
2977 }
fa2a1ce5 2978 /*
1da177e4
LT		 2979 * We may need to retry the login, so don't change the state of the
2980 * port but do the retries.
2981 */
2982 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 2983 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 2984
2985 if (!do_login)
2986 return;
2987
2988 if (fcport->login_retry == 0) {
e315cd28
AC		 2989 fcport->login_retry = vha->hw->login_retry_count;
2990 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 2991
7c3df132
SK		 2992 ql_dbg(ql_dbg_disc, vha, 0x2067,
2993 "Port login retry "
1da177e4 2994 "%02x%02x%02x%02x%02x%02x%02x%02x, "
7c3df132
SK		 2995 "id = 0x%04x retry cnt=%d.\n",
2996 fcport->port_name[0], fcport->port_name[1],
2997 fcport->port_name[2], fcport->port_name[3],
2998 fcport->port_name[4], fcport->port_name[5],
2999 fcport->port_name[6], fcport->port_name[7],
3000 fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3001 }
3002}
3003
3004/*
3005 * qla2x00_mark_all_devices_lost
3006 * Updates fcport state when device goes offline.
3007 *
3008 * Input:
3009 * ha = adapter block pointer.
3010 * fcport = port structure pointer.
3011 *
3012 * Return:
3013 * None.
3014 *
3015 * Context:
3016 */
3017void
e315cd28 3018qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3019{
3020 fc_port_t *fcport;
3021
e315cd28 3022 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3023 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3024 continue;
0d6e61bc 3025
1da177e4
LT		 3026 /*
3027 * No point in marking the device as lost, if the device is
3028 * already DEAD.
3029 */
3030 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3031 continue;
e315cd28 3032 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3033 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3034 if (defer)
3035 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3036 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3037 qla2x00_schedule_rport_del(vha, fcport, defer);
3038 }
1da177e4
LT		 3039 }
3040}
3041
3042/*
3043* qla2x00_mem_alloc
3044* Allocates adapter memory.
3045*
3046* Returns:
3047* 0 = success.
e8711085 3048* !0 = failure.
1da177e4 3049*/
e8711085 3050static int
73208dfd
AC		 3051qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3052 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3053{
3054 char name[16];
1da177e4 3055
e8711085 3056 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3057 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3058 if (!ha->init_cb)
e315cd28 3059 goto fail;
e8711085 3060
2d70c103
NB		 3061 if (qlt_mem_alloc(ha) < 0)
3062 goto fail_free_init_cb;
3063
642ef983
CD		 3064 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3065 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3066 if (!ha->gid_list)
2d70c103 3067 goto fail_free_tgt_mem;
1da177e4 3068
e8711085
AV		 3069 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3070 if (!ha->srb_mempool)
e315cd28 3071 goto fail_free_gid_list;
e8711085 3072
a9083016
GM		 3073 if (IS_QLA82XX(ha)) {
3074 /* Allocate cache for CT6 Ctx. */
3075 if (!ctx_cachep) {
3076 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3077 sizeof(struct ct6_dsd), 0,
3078 SLAB_HWCACHE_ALIGN, NULL);
3079 if (!ctx_cachep)
3080 goto fail_free_gid_list;
3081 }
3082 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3083 ctx_cachep);
3084 if (!ha->ctx_mempool)
3085 goto fail_free_srb_mempool;
7c3df132
SK		 3086 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3087 "ctx_cachep=%p ctx_mempool=%p.\n",
3088 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3089 }
3090
e8711085
AV		 3091 /* Get memory for cached NVRAM */
3092 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3093 if (!ha->nvram)
a9083016 3094 goto fail_free_ctx_mempool;
e8711085 3095
e315cd28
AC		 3096 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3097 ha->pdev->device);
3098 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3099 DMA_POOL_SIZE, 8, 0);
3100 if (!ha->s_dma_pool)
3101 goto fail_free_nvram;
3102
7c3df132
SK		 3103 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3104 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3105 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3106
bad75002 3107 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3108 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3109 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3110 if (!ha->dl_dma_pool) {
7c3df132
SK		 3111 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3112 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3113 goto fail_s_dma_pool;
3114 }
3115
3116 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3117 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3118 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3119 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3120 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3121 goto fail_dl_dma_pool;
3122 }
7c3df132
SK		 3123 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3124 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3125 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3126 }
3127
e8711085
AV		 3128 /* Allocate memory for SNS commands */
3129 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3130 /* Get consistent memory allocated for SNS commands */
e8711085 3131 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3132 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3133 if (!ha->sns_cmd)
e315cd28 3134 goto fail_dma_pool;
7c3df132 3135 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3136 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3137 } else {
e315cd28 3138 /* Get consistent memory allocated for MS IOCB */
e8711085 3139 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3140 &ha->ms_iocb_dma);
e8711085 3141 if (!ha->ms_iocb)
e315cd28
AC		 3142 goto fail_dma_pool;
3143 /* Get consistent memory allocated for CT SNS commands */
e8711085 3144 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3145 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3146 if (!ha->ct_sns)
3147 goto fail_free_ms_iocb;
7c3df132
SK		 3148 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3149 "ms_iocb=%p ct_sns=%p.\n",
3150 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3151 }
3152
e315cd28 3153 /* Allocate memory for request ring */
73208dfd
AC		 3154 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3155 if (!*req) {
7c3df132
SK		 3156 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3157 "Failed to allocate memory for req.\n");
e315cd28
AC		 3158 goto fail_req;
3159 }
73208dfd
AC		 3160 (*req)->length = req_len;
3161 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3162 ((*req)->length + 1) * sizeof(request_t),
3163 &(*req)->dma, GFP_KERNEL);
3164 if (!(*req)->ring) {
7c3df132
SK		 3165 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3166 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3167 goto fail_req_ring;
3168 }
3169 /* Allocate memory for response ring */
73208dfd
AC		 3170 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3171 if (!*rsp) {
7c3df132
SK		 3172 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3173 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3174 goto fail_rsp;
3175 }
73208dfd
AC		 3176 (*rsp)->hw = ha;
3177 (*rsp)->length = rsp_len;
3178 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3179 ((*rsp)->length + 1) * sizeof(response_t),
3180 &(*rsp)->dma, GFP_KERNEL);
3181 if (!(*rsp)->ring) {
7c3df132
SK		 3182 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3183 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3184 goto fail_rsp_ring;
3185 }
73208dfd
AC		 3186 (*req)->rsp = *rsp;
3187 (*rsp)->req = *req;
7c3df132
SK		 3188 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3189 "req=%p req->length=%d req->ring=%p rsp=%p "
3190 "rsp->length=%d rsp->ring=%p.\n",
3191 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3192 (*rsp)->ring);
73208dfd
AC		 3193 /* Allocate memory for NVRAM data for vports */
3194 if (ha->nvram_npiv_size) {
3195 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3196 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3197 if (!ha->npiv_info) {
7c3df132
SK		 3198 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3199 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3200 goto fail_npiv_info;
3201 }
3202 } else
3203 ha->npiv_info = NULL;
e8711085 3204
b64b0e8f 3205 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3206 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3207 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3208 &ha->ex_init_cb_dma);
3209 if (!ha->ex_init_cb)
3210 goto fail_ex_init_cb;
7c3df132
SK		 3211 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3212 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3213 }
3214
a9083016
GM		 3215 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3216
5ff1d584
AV		 3217 /* Get consistent memory allocated for Async Port-Database. */
3218 if (!IS_FWI2_CAPABLE(ha)) {
3219 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3220 &ha->async_pd_dma);
3221 if (!ha->async_pd)
3222 goto fail_async_pd;
7c3df132
SK		 3223 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3224 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3225 }
3226
e315cd28 3227 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3228
3229 /* Allocate memory for our loop_id bitmap */
3230 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3231 GFP_KERNEL);
3232 if (!ha->loop_id_map)
3233 goto fail_async_pd;
3234 else {
3235 qla2x00_set_reserved_loop_ids(ha);
3236 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3237 "loop_id_map=%p. \n", ha->loop_id_map);
3238 }
3239
e315cd28
AC		 3240 return 1;
3241
5ff1d584
AV		 3242fail_async_pd:
3243 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3244fail_ex_init_cb:
3245 kfree(ha->npiv_info);
73208dfd
AC		 3246fail_npiv_info:
3247 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3248 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3249 (*rsp)->ring = NULL;
3250 (*rsp)->dma = 0;
e315cd28 3251fail_rsp_ring:
73208dfd 3252 kfree(*rsp);
e315cd28 3253fail_rsp:
73208dfd
AC		 3254 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3255 sizeof(request_t), (*req)->ring, (*req)->dma);
3256 (*req)->ring = NULL;
3257 (*req)->dma = 0;
e315cd28 3258fail_req_ring:
73208dfd 3259 kfree(*req);
e315cd28
AC		 3260fail_req:
3261 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3262 ha->ct_sns, ha->ct_sns_dma);
3263 ha->ct_sns = NULL;
3264 ha->ct_sns_dma = 0;
e8711085
AV		 3265fail_free_ms_iocb:
3266 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3267 ha->ms_iocb = NULL;
3268 ha->ms_iocb_dma = 0;
e315cd28 3269fail_dma_pool:
bad75002 3270 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3271 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3272 ha->fcp_cmnd_dma_pool = NULL;
3273 }
3274fail_dl_dma_pool:
bad75002 3275 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3276 dma_pool_destroy(ha->dl_dma_pool);
3277 ha->dl_dma_pool = NULL;
3278 }
3279fail_s_dma_pool:
e315cd28
AC		 3280 dma_pool_destroy(ha->s_dma_pool);
3281 ha->s_dma_pool = NULL;
e8711085
AV		 3282fail_free_nvram:
3283 kfree(ha->nvram);
3284 ha->nvram = NULL;
a9083016
GM		 3285fail_free_ctx_mempool:
3286 mempool_destroy(ha->ctx_mempool);
3287 ha->ctx_mempool = NULL;
e8711085
AV		 3288fail_free_srb_mempool:
3289 mempool_destroy(ha->srb_mempool);
3290 ha->srb_mempool = NULL;
e8711085 3291fail_free_gid_list:
642ef983
CD		 3292 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3293 ha->gid_list,
e315cd28 3294 ha->gid_list_dma);
e8711085
AV		 3295 ha->gid_list = NULL;
3296 ha->gid_list_dma = 0;
2d70c103
NB		 3297fail_free_tgt_mem:
3298 qlt_mem_free(ha);
e315cd28
AC		 3299fail_free_init_cb:
3300 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3301 ha->init_cb_dma);
3302 ha->init_cb = NULL;
3303 ha->init_cb_dma = 0;
e8711085 3304fail:
7c3df132
SK		 3305 ql_log(ql_log_fatal, NULL, 0x0030,
3306 "Memory allocation failure.\n");
e8711085 3307 return -ENOMEM;
1da177e4
LT		 3308}
3309
3310/*
e30d1756
MI		 3311* qla2x00_free_fw_dump
3312* Frees fw dump stuff.
1da177e4
LT		 3313*
3314* Input:
e30d1756 3315* ha = adapter block pointer.
1da177e4 3316*/
a824ebb3 3317static void
e30d1756 3318qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3319{
df613b96
AV		 3320 if (ha->fce)
3321 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3322 ha->fce_dma);
df613b96 3323
a7a167bf
AV		 3324 if (ha->fw_dump) {
3325 if (ha->eft)
3326 dma_free_coherent(&ha->pdev->dev,
e30d1756 3327 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3328 vfree(ha->fw_dump);
3329 }
e30d1756
MI		 3330 ha->fce = NULL;
3331 ha->fce_dma = 0;
3332 ha->eft = NULL;
3333 ha->eft_dma = 0;
3334 ha->fw_dump = NULL;
3335 ha->fw_dumped = 0;
3336 ha->fw_dump_reading = 0;
3337}
3338
3339/*
3340* qla2x00_mem_free
3341* Frees all adapter allocated memory.
3342*
3343* Input:
3344* ha = adapter block pointer.
3345*/
3346static void
3347qla2x00_mem_free(struct qla_hw_data *ha)
3348{
3349 qla2x00_free_fw_dump(ha);
3350
81178772
SK		 3351 if (ha->mctp_dump)
3352 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3353 ha->mctp_dump_dma);
3354
e30d1756
MI		 3355 if (ha->srb_mempool)
3356 mempool_destroy(ha->srb_mempool);
a7a167bf 3357
11bbc1d8
AV		 3358 if (ha->dcbx_tlv)
3359 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3360 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3361
ce0423f4
AV		 3362 if (ha->xgmac_data)
3363 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3364 ha->xgmac_data, ha->xgmac_data_dma);
3365
1da177e4
LT		 3366 if (ha->sns_cmd)
3367 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3368 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3369
3370 if (ha->ct_sns)
3371 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3372 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3373
88729e53
AV		 3374 if (ha->sfp_data)
3375 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3376
1da177e4
LT		 3377 if (ha->ms_iocb)
3378 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3379
b64b0e8f 3380 if (ha->ex_init_cb)
a9083016
GM		 3381 dma_pool_free(ha->s_dma_pool,
3382 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3383
5ff1d584
AV		 3384 if (ha->async_pd)
3385 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3386
1da177e4
LT		 3387 if (ha->s_dma_pool)
3388 dma_pool_destroy(ha->s_dma_pool);
3389
1da177e4 3390 if (ha->gid_list)
642ef983
CD		 3391 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3392 ha->gid_list, ha->gid_list_dma);
1da177e4 3393
a9083016
GM		 3394 if (IS_QLA82XX(ha)) {
3395 if (!list_empty(&ha->gbl_dsd_list)) {
3396 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3397
3398 /* clean up allocated prev pool */
3399 list_for_each_entry_safe(dsd_ptr,
3400 tdsd_ptr, &ha->gbl_dsd_list, list) {
3401 dma_pool_free(ha->dl_dma_pool,
3402 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3403 list_del(&dsd_ptr->list);
3404 kfree(dsd_ptr);
3405 }
3406 }
3407 }
3408
3409 if (ha->dl_dma_pool)
3410 dma_pool_destroy(ha->dl_dma_pool);
3411
3412 if (ha->fcp_cmnd_dma_pool)
3413 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3414
3415 if (ha->ctx_mempool)
3416 mempool_destroy(ha->ctx_mempool);
3417
2d70c103
NB		 3418 qlt_mem_free(ha);
3419
e315cd28
AC		 3420 if (ha->init_cb)
3421 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3422 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3423 vfree(ha->optrom_buffer);
3424 kfree(ha->nvram);
73208dfd 3425 kfree(ha->npiv_info);
7a67735b 3426 kfree(ha->swl);
5f16b331 3427 kfree(ha->loop_id_map);
1da177e4 3428
e8711085 3429 ha->srb_mempool = NULL;
a9083016 3430 ha->ctx_mempool = NULL;
1da177e4
LT		 3431 ha->sns_cmd = NULL;
3432 ha->sns_cmd_dma = 0;
3433 ha->ct_sns = NULL;
3434 ha->ct_sns_dma = 0;
3435 ha->ms_iocb = NULL;
3436 ha->ms_iocb_dma = 0;
1da177e4
LT		 3437 ha->init_cb = NULL;
3438 ha->init_cb_dma = 0;
b64b0e8f
AV		 3439 ha->ex_init_cb = NULL;
3440 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3441 ha->async_pd = NULL;
3442 ha->async_pd_dma = 0;
1da177e4
LT		 3443
3444 ha->s_dma_pool = NULL;
a9083016
GM		 3445 ha->dl_dma_pool = NULL;
3446 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3447
1da177e4
LT		 3448 ha->gid_list = NULL;
3449 ha->gid_list_dma = 0;
2d70c103
NB		 3450
3451 ha->tgt.atio_ring = NULL;
3452 ha->tgt.atio_dma = 0;
3453 ha->tgt.tgt_vp_map = NULL;
e315cd28 3454}
1da177e4 3455
e315cd28
AC		 3456struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3457 struct qla_hw_data *ha)
3458{
3459 struct Scsi_Host *host;
3460 struct scsi_qla_host *vha = NULL;
854165f4 3461
e315cd28
AC		 3462 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3463 if (host == NULL) {
7c3df132
SK		 3464 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3465 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3466 goto fail;
3467 }
3468
3469 /* Clear our data area */
3470 vha = shost_priv(host);
3471 memset(vha, 0, sizeof(scsi_qla_host_t));
3472
3473 vha->host = host;
3474 vha->host_no = host->host_no;
3475 vha->hw = ha;
3476
3477 INIT_LIST_HEAD(&vha->vp_fcports);
3478 INIT_LIST_HEAD(&vha->work_list);
3479 INIT_LIST_HEAD(&vha->list);
3480
f999f4c1
AV		 3481 spin_lock_init(&vha->work_lock);
3482
e315cd28 3483 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3484 ql_dbg(ql_dbg_init, vha, 0x0041,
3485 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3486 vha->host, vha->hw, vha,
3487 dev_name(&(ha->pdev->dev)));
3488
e315cd28
AC		 3489 return vha;
3490
3491fail:
3492 return vha;
1da177e4
LT		 3493}
3494
01ef66bb 3495static struct qla_work_evt *
f999f4c1 3496qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3497{
3498 struct qla_work_evt *e;
feafb7b1
AE		 3499 uint8_t bail;
3500
3501 QLA_VHA_MARK_BUSY(vha, bail);
3502 if (bail)
3503 return NULL;
0971de7f 3504
f999f4c1 3505 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3506 if (!e) {
3507 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3508 return NULL;
feafb7b1 3509 }
0971de7f
AV		 3510
3511 INIT_LIST_HEAD(&e->list);
3512 e->type = type;
3513 e->flags = QLA_EVT_FLAG_FREE;
3514 return e;
3515}
3516
01ef66bb 3517static int
f999f4c1 3518qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3519{
f999f4c1 3520 unsigned long flags;
0971de7f 3521
f999f4c1 3522 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3523 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3524 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3525 qla2xxx_wake_dpc(vha);
f999f4c1 3526
0971de7f
AV		 3527 return QLA_SUCCESS;
3528}
3529
3530int
e315cd28 3531qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3532 u32 data)
3533{
3534 struct qla_work_evt *e;
3535
f999f4c1 3536 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3537 if (!e)
3538 return QLA_FUNCTION_FAILED;
3539
3540 e->u.aen.code = code;
3541 e->u.aen.data = data;
f999f4c1 3542 return qla2x00_post_work(vha, e);
0971de7f
AV		 3543}
3544
8a659571
AV		 3545int
3546qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3547{
3548 struct qla_work_evt *e;
3549
f999f4c1 3550 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3551 if (!e)
3552 return QLA_FUNCTION_FAILED;
3553
3554 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3555 return qla2x00_post_work(vha, e);
8a659571
AV		 3556}
3557
ac280b67
AV		 3558#define qla2x00_post_async_work(name, type) \
3559int qla2x00_post_async_##name##_work( \
3560 struct scsi_qla_host *vha, \
3561 fc_port_t *fcport, uint16_t *data) \
3562{ \
3563 struct qla_work_evt *e; \
3564 \
3565 e = qla2x00_alloc_work(vha, type); \
3566 if (!e) \
3567 return QLA_FUNCTION_FAILED; \
3568 \
3569 e->u.logio.fcport = fcport; \
3570 if (data) { \
3571 e->u.logio.data[0] = data[0]; \
3572 e->u.logio.data[1] = data[1]; \
3573 } \
3574 return qla2x00_post_work(vha, e); \
3575}
3576
3577qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3578qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3579qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3580qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3581qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3582qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3583
3420d36c
AV		 3584int
3585qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3586{
3587 struct qla_work_evt *e;
3588
3589 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3590 if (!e)
3591 return QLA_FUNCTION_FAILED;
3592
3593 e->u.uevent.code = code;
3594 return qla2x00_post_work(vha, e);
3595}
3596
3597static void
3598qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3599{
3600 char event_string[40];
3601 char *envp[] = { event_string, NULL };
3602
3603 switch (code) {
3604 case QLA_UEVENT_CODE_FW_DUMP:
3605 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3606 vha->host_no);
3607 break;
3608 default:
3609 /* do nothing */
3610 break;
3611 }
3612 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3613}
3614
ac280b67 3615void
e315cd28 3616qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3617{
f999f4c1
AV		 3618 struct qla_work_evt *e, *tmp;
3619 unsigned long flags;
3620 LIST_HEAD(work);
0971de7f 3621
f999f4c1
AV		 3622 spin_lock_irqsave(&vha->work_lock, flags);
3623 list_splice_init(&vha->work_list, &work);
3624 spin_unlock_irqrestore(&vha->work_lock, flags);
3625
3626 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3627 list_del_init(&e->list);
0971de7f
AV		 3628
3629 switch (e->type) {
3630 case QLA_EVT_AEN:
e315cd28 3631 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3632 e->u.aen.code, e->u.aen.data);
3633 break;
8a659571
AV		 3634 case QLA_EVT_IDC_ACK:
3635 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3636 break;
ac280b67
AV		 3637 case QLA_EVT_ASYNC_LOGIN:
3638 qla2x00_async_login(vha, e->u.logio.fcport,
3639 e->u.logio.data);
3640 break;
3641 case QLA_EVT_ASYNC_LOGIN_DONE:
3642 qla2x00_async_login_done(vha, e->u.logio.fcport,
3643 e->u.logio.data);
3644 break;
3645 case QLA_EVT_ASYNC_LOGOUT:
3646 qla2x00_async_logout(vha, e->u.logio.fcport);
3647 break;
3648 case QLA_EVT_ASYNC_LOGOUT_DONE:
3649 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3650 e->u.logio.data);
3651 break;
5ff1d584
AV		 3652 case QLA_EVT_ASYNC_ADISC:
3653 qla2x00_async_adisc(vha, e->u.logio.fcport,
3654 e->u.logio.data);
3655 break;
3656 case QLA_EVT_ASYNC_ADISC_DONE:
3657 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3658 e->u.logio.data);
3659 break;
3420d36c
AV		 3660 case QLA_EVT_UEVENT:
3661 qla2x00_uevent_emit(vha, e->u.uevent.code);
3662 break;
0971de7f
AV		 3663 }
3664 if (e->flags & QLA_EVT_FLAG_FREE)
3665 kfree(e);
feafb7b1
AE		 3666
3667 /* For each work completed decrement vha ref count */
3668 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3669 }
e315cd28 3670}
f999f4c1 3671
e315cd28
AC		 3672/* Relogins all the fcports of a vport
3673 * Context: dpc thread
3674 */
3675void qla2x00_relogin(struct scsi_qla_host *vha)
3676{
3677 fc_port_t *fcport;
c6b2fca8 3678 int status;
e315cd28
AC		 3679 uint16_t next_loopid = 0;
3680 struct qla_hw_data *ha = vha->hw;
ac280b67 3681 uint16_t data[2];
e315cd28
AC		 3682
3683 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3684 /*
3685 * If the port is not ONLINE then try to login
3686 * to it if we haven't run out of retries.
3687 */
5ff1d584
AV		 3688 if (atomic_read(&fcport->state) != FCS_ONLINE &&
3689 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 3690 fcport->login_retry--;
e315cd28 3691 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 3692 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 3693 ha->isp_ops->fabric_logout(vha,
3694 fcport->loop_id,
3695 fcport->d_id.b.domain,
3696 fcport->d_id.b.area,
3697 fcport->d_id.b.al_pa);
3698
03bcfb57
JC		 3699 if (fcport->loop_id == FC_NO_LOOP_ID) {
3700 fcport->loop_id = next_loopid =
3701 ha->min_external_loopid;
3702 status = qla2x00_find_new_loop_id(
3703 vha, fcport);
3704 if (status != QLA_SUCCESS) {
3705 /* Ran out of IDs to use */
3706 break;
3707 }
3708 }
3709
ac280b67 3710 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 3711 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 3712 data[0] = 0;
3713 data[1] = QLA_LOGIO_LOGIN_RETRIED;
3714 status = qla2x00_post_async_login_work(
3715 vha, fcport, data);
3716 if (status == QLA_SUCCESS)
3717 continue;
3718 /* Attempt a retry. */
3719 status = 1;
aaf4d3e2 3720 } else {
ac280b67
AV		 3721 status = qla2x00_fabric_login(vha,
3722 fcport, &next_loopid);
aaf4d3e2
SK		 3723 if (status == QLA_SUCCESS) {
3724 int status2;
3725 uint8_t opts;
3726
3727 opts = 0;
3728 if (fcport->flags &
3729 FCF_FCP2_DEVICE)
3730 opts |= BIT_1;
03003960
SK		 3731 status2 =
3732 qla2x00_get_port_database(
3733 vha, fcport, opts);
aaf4d3e2
SK		 3734 if (status2 != QLA_SUCCESS)
3735 status = 1;
3736 }
3737 }
e315cd28
AC		 3738 } else
3739 status = qla2x00_local_device_login(vha,
3740 fcport);
3741
e315cd28
AC		 3742 if (status == QLA_SUCCESS) {
3743 fcport->old_loop_id = fcport->loop_id;
3744
7c3df132
SK		 3745 ql_dbg(ql_dbg_disc, vha, 0x2003,
3746 "Port login OK: logged in ID 0x%x.\n",
3747 fcport->loop_id);
e315cd28
AC		 3748
3749 qla2x00_update_fcport(vha, fcport);
3750
3751 } else if (status == 1) {
3752 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3753 /* retry the login again */
7c3df132
SK		 3754 ql_dbg(ql_dbg_disc, vha, 0x2007,
3755 "Retrying %d login again loop_id 0x%x.\n",
3756 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 3757 } else {
3758 fcport->login_retry = 0;
3759 }
3760
3761 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 3762 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 3763 }
3764 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
3765 break;
0971de7f 3766 }
0971de7f
AV		 3767}
3768
7d613ac6
SV		 3769/* Schedule work on any of the dpc-workqueues */
3770void
3771qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
3772{
3773 struct qla_hw_data *ha = base_vha->hw;
3774
3775 switch (work_code) {
3776 case MBA_IDC_AEN: /* 0x8200 */
3777 if (ha->dpc_lp_wq)
3778 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
3779 break;
3780
3781 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
3782 if (!ha->flags.nic_core_reset_hdlr_active) {
3783 if (ha->dpc_hp_wq)
3784 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
3785 } else
3786 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
3787 "NIC Core reset is already active. Skip "
3788 "scheduling it again.\n");
3789 break;
3790 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
3791 if (ha->dpc_hp_wq)
3792 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
3793 break;
3794 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
3795 if (ha->dpc_hp_wq)
3796 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
3797 break;
3798 default:
3799 ql_log(ql_log_warn, base_vha, 0xb05f,
3800 "Unknow work-code=0x%x.\n", work_code);
3801 }
3802
3803 return;
3804}
3805
3806/* Work: Perform NIC Core Unrecoverable state handling */
3807void
3808qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
3809{
3810 struct qla_hw_data *ha =
2ad1b67c 3811 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 3812 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3813 uint32_t dev_state = 0;
3814
3815 qla83xx_idc_lock(base_vha, 0);
3816 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3817 qla83xx_reset_ownership(base_vha);
3818 if (ha->flags.nic_core_reset_owner) {
3819 ha->flags.nic_core_reset_owner = 0;
3820 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3821 QLA8XXX_DEV_FAILED);
3822 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
3823 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
3824 }
3825 qla83xx_idc_unlock(base_vha, 0);
3826}
3827
3828/* Work: Execute IDC state handler */
3829void
3830qla83xx_idc_state_handler_work(struct work_struct *work)
3831{
3832 struct qla_hw_data *ha =
2ad1b67c 3833 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 3834 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3835 uint32_t dev_state = 0;
3836
3837 qla83xx_idc_lock(base_vha, 0);
3838 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3839 if (dev_state == QLA8XXX_DEV_FAILED ||
3840 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
3841 qla83xx_idc_state_handler(base_vha);
3842 qla83xx_idc_unlock(base_vha, 0);
3843}
3844
fa492630 3845static int
7d613ac6
SV		 3846qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
3847{
3848 int rval = QLA_SUCCESS;
3849 unsigned long heart_beat_wait = jiffies + (1 * HZ);
3850 uint32_t heart_beat_counter1, heart_beat_counter2;
3851
3852 do {
3853 if (time_after(jiffies, heart_beat_wait)) {
3854 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
3855 "Nic Core f/w is not alive.\n");
3856 rval = QLA_FUNCTION_FAILED;
3857 break;
3858 }
3859
3860 qla83xx_idc_lock(base_vha, 0);
3861 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3862 &heart_beat_counter1);
3863 qla83xx_idc_unlock(base_vha, 0);
3864 msleep(100);
3865 qla83xx_idc_lock(base_vha, 0);
3866 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
3867 &heart_beat_counter2);
3868 qla83xx_idc_unlock(base_vha, 0);
3869 } while (heart_beat_counter1 == heart_beat_counter2);
3870
3871 return rval;
3872}
3873
3874/* Work: Perform NIC Core Reset handling */
3875void
3876qla83xx_nic_core_reset_work(struct work_struct *work)
3877{
3878 struct qla_hw_data *ha =
3879 container_of(work, struct qla_hw_data, nic_core_reset);
3880 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3881 uint32_t dev_state = 0;
3882
81178772
SK		 3883 if (IS_QLA2031(ha)) {
3884 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
3885 ql_log(ql_log_warn, base_vha, 0xb081,
3886 "Failed to dump mctp\n");
3887 return;
3888 }
3889
7d613ac6
SV		 3890 if (!ha->flags.nic_core_reset_hdlr_active) {
3891 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
3892 qla83xx_idc_lock(base_vha, 0);
3893 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
3894 &dev_state);
3895 qla83xx_idc_unlock(base_vha, 0);
3896 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
3897 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
3898 "Nic Core f/w is alive.\n");
3899 return;
3900 }
3901 }
3902
3903 ha->flags.nic_core_reset_hdlr_active = 1;
3904 if (qla83xx_nic_core_reset(base_vha)) {
3905 /* NIC Core reset failed. */
3906 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
3907 "NIC Core reset failed.\n");
3908 }
3909 ha->flags.nic_core_reset_hdlr_active = 0;
3910 }
3911}
3912
3913/* Work: Handle 8200 IDC aens */
3914void
3915qla83xx_service_idc_aen(struct work_struct *work)
3916{
3917 struct qla_hw_data *ha =
3918 container_of(work, struct qla_hw_data, idc_aen);
3919 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
3920 uint32_t dev_state, idc_control;
3921
3922 qla83xx_idc_lock(base_vha, 0);
3923 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
3924 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
3925 qla83xx_idc_unlock(base_vha, 0);
3926 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
3927 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
3928 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
3929 "Application requested NIC Core Reset.\n");
3930 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
3931 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
3932 QLA_SUCCESS) {
3933 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
3934 "Other protocol driver requested NIC Core Reset.\n");
3935 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
3936 }
3937 } else if (dev_state == QLA8XXX_DEV_FAILED ||
3938 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
3939 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
3940 }
3941}
3942
3943static void
3944qla83xx_wait_logic(void)
3945{
3946 int i;
3947
3948 /* Yield CPU */
3949 if (!in_interrupt()) {
3950 /*
3951 * Wait about 200ms before retrying again.
3952 * This controls the number of retries for single
3953 * lock operation.
3954 */
3955 msleep(100);
3956 schedule();
3957 } else {
3958 for (i = 0; i < 20; i++)
3959 cpu_relax(); /* This a nop instr on i386 */
3960 }
3961}
3962
fa492630 3963static int
7d613ac6
SV		 3964qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
3965{
3966 int rval;
3967 uint32_t data;
3968 uint32_t idc_lck_rcvry_stage_mask = 0x3;
3969 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
3970 struct qla_hw_data *ha = base_vha->hw;
3971
3972 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
3973 if (rval)
3974 return rval;
3975
3976 if ((data & idc_lck_rcvry_stage_mask) > 0) {
3977 return QLA_SUCCESS;
3978 } else {
3979 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
3980 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
3981 data);
3982 if (rval)
3983 return rval;
3984
3985 msleep(200);
3986
3987 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
3988 &data);
3989 if (rval)
3990 return rval;
3991
3992 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
3993 data &= (IDC_LOCK_RECOVERY_STAGE2 |
3994 ~(idc_lck_rcvry_stage_mask));
3995 rval = qla83xx_wr_reg(base_vha,
3996 QLA83XX_IDC_LOCK_RECOVERY, data);
3997 if (rval)
3998 return rval;
3999
4000 /* Forcefully perform IDC UnLock */
4001 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4002 &data);
4003 if (rval)
4004 return rval;
4005 /* Clear lock-id by setting 0xff */
4006 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4007 0xff);
4008 if (rval)
4009 return rval;
4010 /* Clear lock-recovery by setting 0x0 */
4011 rval = qla83xx_wr_reg(base_vha,
4012 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4013 if (rval)
4014 return rval;
4015 } else
4016 return QLA_SUCCESS;
4017 }
4018
4019 return rval;
4020}
4021
fa492630 4022static int
7d613ac6
SV		 4023qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4024{
4025 int rval = QLA_SUCCESS;
4026 uint32_t o_drv_lockid, n_drv_lockid;
4027 unsigned long lock_recovery_timeout;
4028
4029 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4030retry_lockid:
4031 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4032 if (rval)
4033 goto exit;
4034
4035 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4036 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4037 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4038 return QLA_SUCCESS;
4039 else
4040 return QLA_FUNCTION_FAILED;
4041 }
4042
4043 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4044 if (rval)
4045 goto exit;
4046
4047 if (o_drv_lockid == n_drv_lockid) {
4048 qla83xx_wait_logic();
4049 goto retry_lockid;
4050 } else
4051 return QLA_SUCCESS;
4052
4053exit:
4054 return rval;
4055}
4056
4057void
4058qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4059{
4060 uint16_t options = (requester_id << 15) | BIT_6;
4061 uint32_t data;
4062 struct qla_hw_data *ha = base_vha->hw;
4063
4064 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4065retry_lock:
4066 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4067 == QLA_SUCCESS) {
4068 if (data) {
4069 /* Setting lock-id to our function-number */
4070 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4071 ha->portnum);
4072 } else {
4073 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
4074 "Failed to acquire IDC lock. retrying...\n");
4075
4076 /* Retry/Perform IDC-Lock recovery */
4077 if (qla83xx_idc_lock_recovery(base_vha)
4078 == QLA_SUCCESS) {
4079 qla83xx_wait_logic();
4080 goto retry_lock;
4081 } else
4082 ql_log(ql_log_warn, base_vha, 0xb075,
4083 "IDC Lock recovery FAILED.\n");
4084 }
4085
4086 }
4087
4088 return;
4089
4090 /* XXX: IDC-lock implementation using access-control mbx */
4091retry_lock2:
4092 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4093 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4094 "Failed to acquire IDC lock. retrying...\n");
4095 /* Retry/Perform IDC-Lock recovery */
4096 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4097 qla83xx_wait_logic();
4098 goto retry_lock2;
4099 } else
4100 ql_log(ql_log_warn, base_vha, 0xb076,
4101 "IDC Lock recovery FAILED.\n");
4102 }
4103
4104 return;
4105}
4106
4107void
4108qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4109{
4110 uint16_t options = (requester_id << 15) | BIT_7, retry;
4111 uint32_t data;
4112 struct qla_hw_data *ha = base_vha->hw;
4113
4114 /* IDC-unlock implementation using driver-unlock/lock-id
4115 * remote registers
4116 */
4117 retry = 0;
4118retry_unlock:
4119 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4120 == QLA_SUCCESS) {
4121 if (data == ha->portnum) {
4122 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4123 /* Clearing lock-id by setting 0xff */
4124 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4125 } else if (retry < 10) {
4126 /* SV: XXX: IDC unlock retrying needed here? */
4127
4128 /* Retry for IDC-unlock */
4129 qla83xx_wait_logic();
4130 retry++;
4131 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4132 "Failed to release IDC lock, retyring=%d\n", retry);
4133 goto retry_unlock;
4134 }
4135 } else if (retry < 10) {
4136 /* Retry for IDC-unlock */
4137 qla83xx_wait_logic();
4138 retry++;
4139 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4140 "Failed to read drv-lockid, retyring=%d\n", retry);
4141 goto retry_unlock;
4142 }
4143
4144 return;
4145
4146 /* XXX: IDC-unlock implementation using access-control mbx */
4147 retry = 0;
4148retry_unlock2:
4149 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4150 if (retry < 10) {
4151 /* Retry for IDC-unlock */
4152 qla83xx_wait_logic();
4153 retry++;
4154 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4155 "Failed to release IDC lock, retyring=%d\n", retry);
4156 goto retry_unlock2;
4157 }
4158 }
4159
4160 return;
4161}
4162
4163int
4164__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4165{
4166 int rval = QLA_SUCCESS;
4167 struct qla_hw_data *ha = vha->hw;
4168 uint32_t drv_presence;
4169
4170 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4171 if (rval == QLA_SUCCESS) {
4172 drv_presence |= (1 << ha->portnum);
4173 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4174 drv_presence);
4175 }
4176
4177 return rval;
4178}
4179
4180int
4181qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4182{
4183 int rval = QLA_SUCCESS;
4184
4185 qla83xx_idc_lock(vha, 0);
4186 rval = __qla83xx_set_drv_presence(vha);
4187 qla83xx_idc_unlock(vha, 0);
4188
4189 return rval;
4190}
4191
4192int
4193__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4194{
4195 int rval = QLA_SUCCESS;
4196 struct qla_hw_data *ha = vha->hw;
4197 uint32_t drv_presence;
4198
4199 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4200 if (rval == QLA_SUCCESS) {
4201 drv_presence &= ~(1 << ha->portnum);
4202 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4203 drv_presence);
4204 }
4205
4206 return rval;
4207}
4208
4209int
4210qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4211{
4212 int rval = QLA_SUCCESS;
4213
4214 qla83xx_idc_lock(vha, 0);
4215 rval = __qla83xx_clear_drv_presence(vha);
4216 qla83xx_idc_unlock(vha, 0);
4217
4218 return rval;
4219}
4220
fa492630 4221static void
7d613ac6
SV		 4222qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4223{
4224 struct qla_hw_data *ha = vha->hw;
4225 uint32_t drv_ack, drv_presence;
4226 unsigned long ack_timeout;
4227
4228 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4229 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4230 while (1) {
4231 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4232 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4233 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4234 break;
4235
4236 if (time_after_eq(jiffies, ack_timeout)) {
4237 ql_log(ql_log_warn, vha, 0xb067,
4238 "RESET ACK TIMEOUT! drv_presence=0x%x "
4239 "drv_ack=0x%x\n", drv_presence, drv_ack);
4240 /*
4241 * The function(s) which did not ack in time are forced
4242 * to withdraw any further participation in the IDC
4243 * reset.
4244 */
4245 if (drv_ack != drv_presence)
4246 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4247 drv_ack);
4248 break;
4249 }
4250
4251 qla83xx_idc_unlock(vha, 0);
4252 msleep(1000);
4253 qla83xx_idc_lock(vha, 0);
4254 }
4255
4256 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4257 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4258}
4259
fa492630 4260static int
7d613ac6
SV		 4261qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4262{
4263 int rval = QLA_SUCCESS;
4264 uint32_t idc_control;
4265
4266 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4267 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4268
4269 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4270 __qla83xx_get_idc_control(vha, &idc_control);
4271 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4272 __qla83xx_set_idc_control(vha, 0);
4273
4274 qla83xx_idc_unlock(vha, 0);
4275 rval = qla83xx_restart_nic_firmware(vha);
4276 qla83xx_idc_lock(vha, 0);
4277
4278 if (rval != QLA_SUCCESS) {
4279 ql_log(ql_log_fatal, vha, 0xb06a,
4280 "Failed to restart NIC f/w.\n");
4281 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4282 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4283 } else {
4284 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4285 "Success in restarting nic f/w.\n");
4286 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4287 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4288 }
4289
4290 return rval;
4291}
4292
4293/* Assumes idc_lock always held on entry */
4294int
4295qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4296{
4297 struct qla_hw_data *ha = base_vha->hw;
4298 int rval = QLA_SUCCESS;
4299 unsigned long dev_init_timeout;
4300 uint32_t dev_state;
4301
4302 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4303 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4304
4305 while (1) {
4306
4307 if (time_after_eq(jiffies, dev_init_timeout)) {
4308 ql_log(ql_log_warn, base_vha, 0xb06e,
4309 "Initialization TIMEOUT!\n");
4310 /* Init timeout. Disable further NIC Core
4311 * communication.
4312 */
4313 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4314 QLA8XXX_DEV_FAILED);
4315 ql_log(ql_log_info, base_vha, 0xb06f,
4316 "HW State: FAILED.\n");
4317 }
4318
4319 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4320 switch (dev_state) {
4321 case QLA8XXX_DEV_READY:
4322 if (ha->flags.nic_core_reset_owner)
4323 qla83xx_idc_audit(base_vha,
4324 IDC_AUDIT_COMPLETION);
4325 ha->flags.nic_core_reset_owner = 0;
4326 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4327 "Reset_owner reset by 0x%x.\n",
4328 ha->portnum);
4329 goto exit;
4330 case QLA8XXX_DEV_COLD:
4331 if (ha->flags.nic_core_reset_owner)
4332 rval = qla83xx_device_bootstrap(base_vha);
4333 else {
4334 /* Wait for AEN to change device-state */
4335 qla83xx_idc_unlock(base_vha, 0);
4336 msleep(1000);
4337 qla83xx_idc_lock(base_vha, 0);
4338 }
4339 break;
4340 case QLA8XXX_DEV_INITIALIZING:
4341 /* Wait for AEN to change device-state */
4342 qla83xx_idc_unlock(base_vha, 0);
4343 msleep(1000);
4344 qla83xx_idc_lock(base_vha, 0);
4345 break;
4346 case QLA8XXX_DEV_NEED_RESET:
4347 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4348 qla83xx_need_reset_handler(base_vha);
4349 else {
4350 /* Wait for AEN to change device-state */
4351 qla83xx_idc_unlock(base_vha, 0);
4352 msleep(1000);
4353 qla83xx_idc_lock(base_vha, 0);
4354 }
4355 /* reset timeout value after need reset handler */
4356 dev_init_timeout = jiffies +
4357 (ha->fcoe_dev_init_timeout * HZ);
4358 break;
4359 case QLA8XXX_DEV_NEED_QUIESCENT:
4360 /* XXX: DEBUG for now */
4361 qla83xx_idc_unlock(base_vha, 0);
4362 msleep(1000);
4363 qla83xx_idc_lock(base_vha, 0);
4364 break;
4365 case QLA8XXX_DEV_QUIESCENT:
4366 /* XXX: DEBUG for now */
4367 if (ha->flags.quiesce_owner)
4368 goto exit;
4369
4370 qla83xx_idc_unlock(base_vha, 0);
4371 msleep(1000);
4372 qla83xx_idc_lock(base_vha, 0);
4373 dev_init_timeout = jiffies +
4374 (ha->fcoe_dev_init_timeout * HZ);
4375 break;
4376 case QLA8XXX_DEV_FAILED:
4377 if (ha->flags.nic_core_reset_owner)
4378 qla83xx_idc_audit(base_vha,
4379 IDC_AUDIT_COMPLETION);
4380 ha->flags.nic_core_reset_owner = 0;
4381 __qla83xx_clear_drv_presence(base_vha);
4382 qla83xx_idc_unlock(base_vha, 0);
4383 qla8xxx_dev_failed_handler(base_vha);
4384 rval = QLA_FUNCTION_FAILED;
4385 qla83xx_idc_lock(base_vha, 0);
4386 goto exit;
4387 case QLA8XXX_BAD_VALUE:
4388 qla83xx_idc_unlock(base_vha, 0);
4389 msleep(1000);
4390 qla83xx_idc_lock(base_vha, 0);
4391 break;
4392 default:
4393 ql_log(ql_log_warn, base_vha, 0xb071,
4394 "Unknow Device State: %x.\n", dev_state);
4395 qla83xx_idc_unlock(base_vha, 0);
4396 qla8xxx_dev_failed_handler(base_vha);
4397 rval = QLA_FUNCTION_FAILED;
4398 qla83xx_idc_lock(base_vha, 0);
4399 goto exit;
4400 }
4401 }
4402
4403exit:
4404 return rval;
4405}
4406
1da177e4
LT		 4407/**************************************************************************
4408* qla2x00_do_dpc
4409* This kernel thread is a task that is schedule by the interrupt handler
4410* to perform the background processing for interrupts.
4411*
4412* Notes:
4413* This task always run in the context of a kernel thread. It
4414* is kick-off by the driver's detect code and starts up
4415* up one per adapter. It immediately goes to sleep and waits for
4416* some fibre event. When either the interrupt handler or
4417* the timer routine detects a event it will one of the task
4418* bits then wake us up.
4419**************************************************************************/
4420static int
4421qla2x00_do_dpc(void *data)
4422{
2c3dfe3f 4423 int rval;
e315cd28
AC		 4424 scsi_qla_host_t *base_vha;
4425 struct qla_hw_data *ha;
1da177e4 4426
e315cd28
AC		 4427 ha = (struct qla_hw_data *)data;
4428 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4429
1da177e4
LT		 4430 set_user_nice(current, -20);
4431
563585ec 4432 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4433 while (!kthread_should_stop()) {
7c3df132
SK		 4434 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4435 "DPC handler sleeping.\n");
1da177e4 4436
39a11240
CH		 4437 schedule();
4438 __set_current_state(TASK_RUNNING);
1da177e4 4439
c142caf0
AV		 4440 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4441 goto end_loop;
1da177e4 4442
85880801 4443 if (ha->flags.eeh_busy) {
7c3df132
SK		 4444 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4445 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4446 goto end_loop;
85880801
AV		 4447 }
4448
1da177e4
LT		 4449 ha->dpc_active = 1;
4450
5f28d2d7
SK		 4451 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4452 "DPC handler waking up, dpc_flags=0x%lx.\n",
4453 base_vha->dpc_flags);
1da177e4 4454
e315cd28 4455 qla2x00_do_work(base_vha);
0971de7f 4456
a9083016
GM		 4457 if (IS_QLA82XX(ha)) {
4458 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4459 &base_vha->dpc_flags)) {
4460 qla82xx_idc_lock(ha);
4461 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 4462 QLA8XXX_DEV_FAILED);
a9083016 4463 qla82xx_idc_unlock(ha);
7c3df132
SK		 4464 ql_log(ql_log_info, base_vha, 0x4004,
4465 "HW State: FAILED.\n");
a9083016
GM		 4466 qla82xx_device_state_handler(base_vha);
4467 continue;
4468 }
4469
4470 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4471 &base_vha->dpc_flags)) {
4472
7c3df132
SK		 4473 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4474 "FCoE context reset scheduled.\n");
a9083016
GM		 4475 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4476 &base_vha->dpc_flags))) {
4477 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4478 /* FCoE-ctx reset failed.
4479 * Escalate to chip-reset
4480 */
4481 set_bit(ISP_ABORT_NEEDED,
4482 &base_vha->dpc_flags);
4483 }
4484 clear_bit(ABORT_ISP_ACTIVE,
4485 &base_vha->dpc_flags);
4486 }
4487
7c3df132
SK		 4488 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4489 "FCoE context reset end.\n");
a9083016
GM		 4490 }
4491 }
4492
e315cd28
AC		 4493 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4494 &base_vha->dpc_flags)) {
1da177e4 4495
7c3df132
SK		 4496 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4497 "ISP abort scheduled.\n");
1da177e4 4498 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4499 &base_vha->dpc_flags))) {
1da177e4 4500
a9083016 4501 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4502 /* failed. retry later */
4503 set_bit(ISP_ABORT_NEEDED,
e315cd28 4504 &base_vha->dpc_flags);
99363ef8 4505 }
e315cd28
AC		 4506 clear_bit(ABORT_ISP_ACTIVE,
4507 &base_vha->dpc_flags);
99363ef8
SJ		 4508 }
4509
7c3df132
SK		 4510 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4511 "ISP abort end.\n");
1da177e4
LT		 4512 }
4513
a394aac8
DJ		 4514 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4515 &base_vha->dpc_flags)) {
e315cd28 4516 qla2x00_update_fcports(base_vha);
c9c5ced9 4517 }
d97994dc 4518
2d70c103
NB		 4519 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4520 int ret;
4521 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4522 if (ret != QLA_SUCCESS)
4523 ql_log(ql_log_warn, base_vha, 0x121,
4524 "Failed to enable receiving of RSCN "
4525 "requests: 0x%x.\n", ret);
4526 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4527 }
4528
579d12b5 4529 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4530 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4531 "Quiescence mode scheduled.\n");
8fcd6b8b
CD		 4532 if (IS_QLA82XX(ha)) {
4533 qla82xx_device_state_handler(base_vha);
4534 clear_bit(ISP_QUIESCE_NEEDED,
4535 &base_vha->dpc_flags);
4536 if (!ha->flags.quiesce_owner) {
4537 qla2x00_perform_loop_resync(base_vha);
4538
4539 qla82xx_idc_lock(ha);
4540 qla82xx_clear_qsnt_ready(base_vha);
4541 qla82xx_idc_unlock(ha);
4542 }
4543 } else {
4544 clear_bit(ISP_QUIESCE_NEEDED,
4545 &base_vha->dpc_flags);
4546 qla2x00_quiesce_io(base_vha);
579d12b5 4547 }
7c3df132
SK		 4548 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4549 "Quiescence mode end.\n");
579d12b5
SK		 4550 }
4551
e315cd28
AC		 4552 if (test_and_clear_bit(RESET_MARKER_NEEDED,
4553 &base_vha->dpc_flags) &&
4554 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4555
7c3df132
SK		 4556 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4557 "Reset marker scheduled.\n");
e315cd28
AC		 4558 qla2x00_rst_aen(base_vha);
4559 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4560 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4561 "Reset marker end.\n");
1da177e4
LT		 4562 }
4563
4564 /* Retry each device up to login retry count */
e315cd28
AC		 4565 if ((test_and_clear_bit(RELOGIN_NEEDED,
4566 &base_vha->dpc_flags)) &&
4567 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4568 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4569
7c3df132
SK		 4570 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4571 "Relogin scheduled.\n");
e315cd28 4572 qla2x00_relogin(base_vha);
7c3df132
SK		 4573 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4574 "Relogin end.\n");
1da177e4
LT		 4575 }
4576
e315cd28
AC		 4577 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
4578 &base_vha->dpc_flags)) {
1da177e4 4579
7c3df132
SK		 4580 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4581 "Loop resync scheduled.\n");
1da177e4
LT		 4582
4583 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4584 &base_vha->dpc_flags))) {
1da177e4 4585
e315cd28 4586 rval = qla2x00_loop_resync(base_vha);
1da177e4 4587
e315cd28
AC		 4588 clear_bit(LOOP_RESYNC_ACTIVE,
4589 &base_vha->dpc_flags);
1da177e4
LT		 4590 }
4591
7c3df132
SK		 4592 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4593 "Loop resync end.\n");
1da177e4
LT		 4594 }
4595
e315cd28
AC		 4596 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4597 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4598 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4599 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4600 }
4601
1da177e4 4602 if (!ha->interrupts_on)
fd34f556 4603 ha->isp_ops->enable_intrs(ha);
1da177e4 4604
e315cd28
AC		 4605 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
4606 &base_vha->dpc_flags))
4607 ha->isp_ops->beacon_blink(base_vha);
f6df144c 4608
e315cd28 4609 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 4610
1da177e4 4611 ha->dpc_active = 0;
c142caf0 4612end_loop:
563585ec 4613 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 4614 } /* End of while(1) */
563585ec 4615 __set_current_state(TASK_RUNNING);
1da177e4 4616
7c3df132
SK		 4617 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
4618 "DPC handler exiting.\n");
1da177e4
LT		 4619
4620 /*
4621 * Make sure that nobody tries to wake us up again.
4622 */
1da177e4
LT		 4623 ha->dpc_active = 0;
4624
ac280b67
AV		 4625 /* Cleanup any residual CTX SRBs. */
4626 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
4627
39a11240
CH		 4628 return 0;
4629}
4630
4631void
e315cd28 4632qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 4633{
e315cd28 4634 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 4635 struct task_struct *t = ha->dpc_thread;
4636
e315cd28 4637 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 4638 wake_up_process(t);
1da177e4
LT		 4639}
4640
1da177e4
LT		 4641/*
4642* qla2x00_rst_aen
4643* Processes asynchronous reset.
4644*
4645* Input:
4646* ha = adapter block pointer.
4647*/
4648static void
e315cd28 4649qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 4650{
e315cd28
AC		 4651 if (vha->flags.online && !vha->flags.reset_active &&
4652 !atomic_read(&vha->loop_down_timer) &&
4653 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 4654 do {
e315cd28 4655 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4656
4657 /*
4658 * Issue marker command only when we are going to start
4659 * the I/O.
4660 */
e315cd28
AC		 4661 vha->marker_needed = 1;
4662 } while (!atomic_read(&vha->loop_down_timer) &&
4663 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 4664 }
4665}
4666
1da177e4
LT		 4667/**************************************************************************
4668* qla2x00_timer
4669*
4670* Description:
4671* One second timer
4672*
4673* Context: Interrupt
4674***************************************************************************/
2c3dfe3f 4675void
e315cd28 4676qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 4677{
1da177e4 4678 unsigned long cpu_flags = 0;
1da177e4
LT		 4679 int start_dpc = 0;
4680 int index;
4681 srb_t *sp;
85880801 4682 uint16_t w;
e315cd28 4683 struct qla_hw_data *ha = vha->hw;
73208dfd 4684 struct req_que *req;
85880801 4685
a5b36321 4686 if (ha->flags.eeh_busy) {
7c3df132
SK		 4687 ql_dbg(ql_dbg_timer, vha, 0x6000,
4688 "EEH = %d, restarting timer.\n",
4689 ha->flags.eeh_busy);
a5b36321
LC		 4690 qla2x00_restart_timer(vha, WATCH_INTERVAL);
4691 return;
4692 }
4693
85880801
AV		 4694 /* Hardware read to raise pending EEH errors during mailbox waits. */
4695 if (!pci_channel_offline(ha->pdev))
4696 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 4697
cefcaba6
SK		 4698 /* Make sure qla82xx_watchdog is run only for physical port */
4699 if (!vha->vp_idx && IS_QLA82XX(ha)) {
579d12b5
SK		 4700 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
4701 start_dpc++;
4702 qla82xx_watchdog(vha);
4703 }
4704
1da177e4 4705 /* Loop down handler. */
e315cd28 4706 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 4707 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
4708 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 4709 && vha->flags.online) {
1da177e4 4710
e315cd28
AC		 4711 if (atomic_read(&vha->loop_down_timer) ==
4712 vha->loop_down_abort_time) {
1da177e4 4713
7c3df132
SK		 4714 ql_log(ql_log_info, vha, 0x6008,
4715 "Loop down - aborting the queues before time expires.\n");
1da177e4 4716
e315cd28
AC		 4717 if (!IS_QLA2100(ha) && vha->link_down_timeout)
4718 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 4719
f08b7251
AV		 4720 /*
4721 * Schedule an ISP abort to return any FCP2-device
4722 * commands.
4723 */
2c3dfe3f 4724 /* NPIV - scan physical port only */
e315cd28 4725 if (!vha->vp_idx) {
2c3dfe3f
SJ		 4726 spin_lock_irqsave(&ha->hardware_lock,
4727 cpu_flags);
73208dfd 4728 req = ha->req_q_map[0];
2c3dfe3f
SJ		 4729 for (index = 1;
4730 index < MAX_OUTSTANDING_COMMANDS;
4731 index++) {
4732 fc_port_t *sfcp;
4733
e315cd28 4734 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 4735 if (!sp)
4736 continue;
9ba56b95 4737 if (sp->type != SRB_SCSI_CMD)
cf53b069 4738 continue;
2c3dfe3f 4739 sfcp = sp->fcport;
f08b7251 4740 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 4741 continue;
bdf79621 4742
8f7daead
GM		 4743 if (IS_QLA82XX(ha))
4744 set_bit(FCOE_CTX_RESET_NEEDED,
4745 &vha->dpc_flags);
4746 else
4747 set_bit(ISP_ABORT_NEEDED,
e315cd28 4748 &vha->dpc_flags);
2c3dfe3f
SJ		 4749 break;
4750 }
4751 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 4752 cpu_flags);
1da177e4 4753 }
1da177e4
LT		 4754 start_dpc++;
4755 }
4756
4757 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 4758 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 4759 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 4760 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 4761 "Loop down - aborting ISP.\n");
4762
8f7daead
GM		 4763 if (IS_QLA82XX(ha))
4764 set_bit(FCOE_CTX_RESET_NEEDED,
4765 &vha->dpc_flags);
4766 else
4767 set_bit(ISP_ABORT_NEEDED,
4768 &vha->dpc_flags);
1da177e4
LT		 4769 }
4770 }
7c3df132
SK		 4771 ql_dbg(ql_dbg_timer, vha, 0x600a,
4772 "Loop down - seconds remaining %d.\n",
4773 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 4774 }
4775
cefcaba6
SK		 4776 /* Check if beacon LED needs to be blinked for physical host only */
4777 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc
SK		 4778 /* There is no beacon_blink function for ISP82xx */
4779 if (!IS_QLA82XX(ha)) {
4780 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
4781 start_dpc++;
4782 }
f6df144c
AV		 4783 }
4784
550bf57d 4785 /* Process any deferred work. */
e315cd28 4786 if (!list_empty(&vha->work_list))
550bf57d
AV		 4787 start_dpc++;
4788
1da177e4 4789 /* Schedule the DPC routine if needed */
e315cd28
AC		 4790 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
4791 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
4792 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 4793 start_dpc ||
e315cd28
AC		 4794 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
4795 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 4796 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
4797 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 4798 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
7c3df132
SK		 4799 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
4800 ql_dbg(ql_dbg_timer, vha, 0x600b,
4801 "isp_abort_needed=%d loop_resync_needed=%d "
4802 "fcport_update_needed=%d start_dpc=%d "
4803 "reset_marker_needed=%d",
4804 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
4805 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
4806 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
4807 start_dpc,
4808 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
4809 ql_dbg(ql_dbg_timer, vha, 0x600c,
4810 "beacon_blink_needed=%d isp_unrecoverable=%d "
4811 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
4812 "relogin_needed=%d.\n",
4813 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
4814 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
4815 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
4816 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
4817 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 4818 qla2xxx_wake_dpc(vha);
7c3df132 4819 }
1da177e4 4820
e315cd28 4821 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 4822}
4823
5433383e
AV		 4824/* Firmware interface routines. */
4825
6246b8a1 4826#define FW_BLOBS 10
5433383e
AV		 4827#define FW_ISP21XX 0
4828#define FW_ISP22XX 1
4829#define FW_ISP2300 2
4830#define FW_ISP2322 3
48c02fde 4831#define FW_ISP24XX 4
c3a2f0df 4832#define FW_ISP25XX 5
3a03eb79 4833#define FW_ISP81XX 6
a9083016 4834#define FW_ISP82XX 7
6246b8a1
GM		 4835#define FW_ISP2031 8
4836#define FW_ISP8031 9
5433383e 4837
bb8ee499
AV		 4838#define FW_FILE_ISP21XX "ql2100_fw.bin"
4839#define FW_FILE_ISP22XX "ql2200_fw.bin"
4840#define FW_FILE_ISP2300 "ql2300_fw.bin"
4841#define FW_FILE_ISP2322 "ql2322_fw.bin"
4842#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 4843#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 4844#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 4845#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 4846#define FW_FILE_ISP2031 "ql2600_fw.bin"
4847#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 4848
e1e82b6f 4849static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 4850
4851static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 4852 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
4853 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
4854 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
4855 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
4856 { .name = FW_FILE_ISP24XX, },
c3a2f0df 4857 { .name = FW_FILE_ISP25XX, },
3a03eb79 4858 { .name = FW_FILE_ISP81XX, },
a9083016 4859 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 4860 { .name = FW_FILE_ISP2031, },
4861 { .name = FW_FILE_ISP8031, },
5433383e
AV		 4862};
4863
4864struct fw_blob *
e315cd28 4865qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 4866{
e315cd28 4867 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 4868 struct fw_blob *blob;
4869
5433383e
AV		 4870 if (IS_QLA2100(ha)) {
4871 blob = &qla_fw_blobs[FW_ISP21XX];
4872 } else if (IS_QLA2200(ha)) {
4873 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 4874 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 4875 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 4876 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 4877 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 4878 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 4879 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 4880 } else if (IS_QLA25XX(ha)) {
4881 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 4882 } else if (IS_QLA81XX(ha)) {
4883 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 4884 } else if (IS_QLA82XX(ha)) {
4885 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 4886 } else if (IS_QLA2031(ha)) {
4887 blob = &qla_fw_blobs[FW_ISP2031];
4888 } else if (IS_QLA8031(ha)) {
4889 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 4890 } else {
4891 return NULL;
5433383e
AV		 4892 }
4893
e1e82b6f 4894 mutex_lock(&qla_fw_lock);
5433383e
AV		 4895 if (blob->fw)
4896 goto out;
4897
4898 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 4899 ql_log(ql_log_warn, vha, 0x0063,
4900 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 4901 blob->fw = NULL;
4902 blob = NULL;
4903 goto out;
4904 }
4905
4906out:
e1e82b6f 4907 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4908 return blob;
4909}
4910
4911static void
4912qla2x00_release_firmware(void)
4913{
4914 int idx;
4915
e1e82b6f 4916 mutex_lock(&qla_fw_lock);
5433383e 4917 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 4918 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 4919 mutex_unlock(&qla_fw_lock);
5433383e
AV		 4920}
4921
14e660e6
SJ		 4922static pci_ers_result_t
4923qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
4924{
85880801
AV		 4925 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
4926 struct qla_hw_data *ha = vha->hw;
4927
7c3df132
SK		 4928 ql_dbg(ql_dbg_aer, vha, 0x9000,
4929 "PCI error detected, state %x.\n", state);
b9b12f73 4930
14e660e6
SJ		 4931 switch (state) {
4932 case pci_channel_io_normal:
85880801 4933 ha->flags.eeh_busy = 0;
14e660e6
SJ		 4934 return PCI_ERS_RESULT_CAN_RECOVER;
4935 case pci_channel_io_frozen:
85880801 4936 ha->flags.eeh_busy = 1;
a5b36321
LC		 4937 /* For ISP82XX complete any pending mailbox cmd */
4938 if (IS_QLA82XX(ha)) {
7190575f 4939 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 4940 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
4941 qla82xx_clear_pending_mbx(vha);
a5b36321 4942 }
90a86fc0 4943 qla2x00_free_irqs(vha);
14e660e6 4944 pci_disable_device(pdev);
bddd2d65
LC		 4945 /* Return back all IOs */
4946 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 4947 return PCI_ERS_RESULT_NEED_RESET;
4948 case pci_channel_io_perm_failure:
85880801
AV		 4949 ha->flags.pci_channel_io_perm_failure = 1;
4950 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 4951 return PCI_ERS_RESULT_DISCONNECT;
4952 }
4953 return PCI_ERS_RESULT_NEED_RESET;
4954}
4955
4956static pci_ers_result_t
4957qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
4958{
4959 int risc_paused = 0;
4960 uint32_t stat;
4961 unsigned long flags;
e315cd28
AC		 4962 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
4963 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 4964 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4965 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
4966
bcc5b6d3
SK		 4967 if (IS_QLA82XX(ha))
4968 return PCI_ERS_RESULT_RECOVERED;
4969
14e660e6
SJ		 4970 spin_lock_irqsave(&ha->hardware_lock, flags);
4971 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
4972 stat = RD_REG_DWORD(&reg->hccr);
4973 if (stat & HCCR_RISC_PAUSE)
4974 risc_paused = 1;
4975 } else if (IS_QLA23XX(ha)) {
4976 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
4977 if (stat & HSR_RISC_PAUSED)
4978 risc_paused = 1;
4979 } else if (IS_FWI2_CAPABLE(ha)) {
4980 stat = RD_REG_DWORD(&reg24->host_status);
4981 if (stat & HSRX_RISC_PAUSED)
4982 risc_paused = 1;
4983 }
4984 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4985
4986 if (risc_paused) {
7c3df132
SK		 4987 ql_log(ql_log_info, base_vha, 0x9003,
4988 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 4989 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 4990
4991 return PCI_ERS_RESULT_NEED_RESET;
4992 } else
4993 return PCI_ERS_RESULT_RECOVERED;
4994}
4995
fa492630
SK		 4996static uint32_t
4997qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 4998{
4999 uint32_t rval = QLA_FUNCTION_FAILED;
5000 uint32_t drv_active = 0;
5001 struct qla_hw_data *ha = base_vha->hw;
5002 int fn;
5003 struct pci_dev *other_pdev = NULL;
5004
7c3df132
SK		 5005 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5006 "Entered %s.\n", __func__);
a5b36321
LC		 5007
5008 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5009
5010 if (base_vha->flags.online) {
5011 /* Abort all outstanding commands,
5012 * so as to be requeued later */
5013 qla2x00_abort_isp_cleanup(base_vha);
5014 }
5015
5016
5017 fn = PCI_FUNC(ha->pdev->devfn);
5018 while (fn > 0) {
5019 fn--;
7c3df132
SK		 5020 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5021 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5022 other_pdev =
5023 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5024 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5025 fn));
5026
5027 if (!other_pdev)
5028 continue;
5029 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5030 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5031 "Found PCI func available and enable at 0x%x.\n",
5032 fn);
a5b36321
LC		 5033 pci_dev_put(other_pdev);
5034 break;
5035 }
5036 pci_dev_put(other_pdev);
5037 }
5038
5039 if (!fn) {
5040 /* Reset owner */
7c3df132
SK		 5041 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5042 "This devfn is reset owner = 0x%x.\n",
5043 ha->pdev->devfn);
a5b36321
LC		 5044 qla82xx_idc_lock(ha);
5045
5046 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5047 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5048
5049 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5050 QLA82XX_IDC_VERSION);
5051
5052 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5053 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5054 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5055
5056 qla82xx_idc_unlock(ha);
5057 /* Reset if device is not already reset
5058 * drv_active would be 0 if a reset has already been done
5059 */
5060 if (drv_active)
5061 rval = qla82xx_start_firmware(base_vha);
5062 else
5063 rval = QLA_SUCCESS;
5064 qla82xx_idc_lock(ha);
5065
5066 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5067 ql_log(ql_log_info, base_vha, 0x900b,
5068 "HW State: FAILED.\n");
a5b36321
LC		 5069 qla82xx_clear_drv_active(ha);
5070 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5071 QLA8XXX_DEV_FAILED);
a5b36321 5072 } else {
7c3df132
SK		 5073 ql_log(ql_log_info, base_vha, 0x900c,
5074 "HW State: READY.\n");
a5b36321 5075 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5076 QLA8XXX_DEV_READY);
a5b36321 5077 qla82xx_idc_unlock(ha);
7190575f 5078 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5079 rval = qla82xx_restart_isp(base_vha);
5080 qla82xx_idc_lock(ha);
5081 /* Clear driver state register */
5082 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5083 qla82xx_set_drv_active(base_vha);
5084 }
5085 qla82xx_idc_unlock(ha);
5086 } else {
7c3df132
SK		 5087 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5088 "This devfn is not reset owner = 0x%x.\n",
5089 ha->pdev->devfn);
a5b36321 5090 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5091 QLA8XXX_DEV_READY)) {
7190575f 5092 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5093 rval = qla82xx_restart_isp(base_vha);
5094 qla82xx_idc_lock(ha);
5095 qla82xx_set_drv_active(base_vha);
5096 qla82xx_idc_unlock(ha);
5097 }
5098 }
5099 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5100
5101 return rval;
5102}
5103
14e660e6
SJ		 5104static pci_ers_result_t
5105qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5106{
5107 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5108 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5109 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5110 struct rsp_que *rsp;
5111 int rc, retries = 10;
09483916 5112
7c3df132
SK		 5113 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5114 "Slot Reset.\n");
85880801 5115
90a86fc0
JC		 5116 /* Workaround: qla2xxx driver which access hardware earlier
5117 * needs error state to be pci_channel_io_online.
5118 * Otherwise mailbox command timesout.
5119 */
5120 pdev->error_state = pci_channel_io_normal;
5121
5122 pci_restore_state(pdev);
5123
8c1496bd
RL		 5124 /* pci_restore_state() clears the saved_state flag of the device
5125 * save restored state which resets saved_state flag
5126 */
5127 pci_save_state(pdev);
5128
09483916
BH		 5129 if (ha->mem_only)
5130 rc = pci_enable_device_mem(pdev);
5131 else
5132 rc = pci_enable_device(pdev);
14e660e6 5133
09483916 5134 if (rc) {
7c3df132 5135 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5136 "Can't re-enable PCI device after reset.\n");
a5b36321 5137 goto exit_slot_reset;
14e660e6 5138 }
14e660e6 5139
90a86fc0
JC		 5140 rsp = ha->rsp_q_map[0];
5141 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5142 goto exit_slot_reset;
90a86fc0 5143
e315cd28 5144 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5145 goto exit_slot_reset;
5146
5147 if (IS_QLA82XX(ha)) {
5148 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5149 ret = PCI_ERS_RESULT_RECOVERED;
5150 goto exit_slot_reset;
5151 } else
5152 goto exit_slot_reset;
5153 }
14e660e6 5154
90a86fc0
JC		 5155 while (ha->flags.mbox_busy && retries--)
5156 msleep(1000);
85880801 5157
e315cd28 5158 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5159 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5160 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5161 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5162
90a86fc0 5163
a5b36321 5164exit_slot_reset:
7c3df132
SK		 5165 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5166 "slot_reset return %x.\n", ret);
85880801 5167
14e660e6
SJ		 5168 return ret;
5169}
5170
5171static void
5172qla2xxx_pci_resume(struct pci_dev *pdev)
5173{
e315cd28
AC		 5174 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5175 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5176 int ret;
5177
7c3df132
SK		 5178 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5179 "pci_resume.\n");
85880801 5180
e315cd28 5181 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5182 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5183 ql_log(ql_log_fatal, base_vha, 0x9002,
5184 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5185 }
85880801 5186
3e46f031
LC		 5187 pci_cleanup_aer_uncorrect_error_status(pdev);
5188
85880801 5189 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5190}
5191
a55b2d21 5192static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5193 .error_detected = qla2xxx_pci_error_detected,
5194 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5195 .slot_reset = qla2xxx_pci_slot_reset,
5196 .resume = qla2xxx_pci_resume,
5197};
5198
5433383e 5199static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5210 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5211 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5212 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5213 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5214 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5215 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5216 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
5433383e
AV		 5217 { 0 },
5218};
5219MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5220
fca29703 5221static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5222 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5223 .driver = {
5224 .owner = THIS_MODULE,
5225 },
fca29703 5226 .id_table = qla2xxx_pci_tbl,
7ee61397 5227 .probe = qla2x00_probe_one,
4c993f76 5228 .remove = qla2x00_remove_one,
e30d1756 5229 .shutdown = qla2x00_shutdown,
14e660e6 5230 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5231};
5232
6a03b4cd
HZ		 5233static struct file_operations apidev_fops = {
5234 .owner = THIS_MODULE,
6038f373 5235 .llseek = noop_llseek,
6a03b4cd
HZ		 5236};
5237
1da177e4
LT		 5238/**
5239 * qla2x00_module_init - Module initialization.
5240 **/
5241static int __init
5242qla2x00_module_init(void)
5243{
fca29703
AV		 5244 int ret = 0;
5245
1da177e4 5246 /* Allocate cache for SRBs. */
354d6b21 5247 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5248 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5249 if (srb_cachep == NULL) {
7c3df132
SK		 5250 ql_log(ql_log_fatal, NULL, 0x0001,
5251 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5252 return -ENOMEM;
5253 }
5254
2d70c103
NB		 5255 /* Initialize target kmem_cache and mem_pools */
5256 ret = qlt_init();
5257 if (ret < 0) {
5258 kmem_cache_destroy(srb_cachep);
5259 return ret;
5260 } else if (ret > 0) {
5261 /*
5262 * If initiator mode is explictly disabled by qlt_init(),
5263 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5264 * performing scsi_scan_target() during LOOP UP event.
5265 */
5266 qla2xxx_transport_functions.disable_target_scan = 1;
5267 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5268 }
5269
1da177e4
LT		 5270 /* Derive version string. */
5271 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5272 if (ql2xextended_error_logging)
0181944f
AV		 5273 strcat(qla2x00_version_str, "-debug");
5274
1c97a12a
AV		 5275 qla2xxx_transport_template =
5276 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5277 if (!qla2xxx_transport_template) {
5278 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5279 ql_log(ql_log_fatal, NULL, 0x0002,
5280 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5281 qlt_exit();
1da177e4 5282 return -ENODEV;
2c3dfe3f 5283 }
6a03b4cd
HZ		 5284
5285 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5286 if (apidev_major < 0) {
7c3df132
SK		 5287 ql_log(ql_log_fatal, NULL, 0x0003,
5288 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5289 }
5290
2c3dfe3f
SJ		 5291 qla2xxx_transport_vport_template =
5292 fc_attach_transport(&qla2xxx_transport_vport_functions);
5293 if (!qla2xxx_transport_vport_template) {
5294 kmem_cache_destroy(srb_cachep);
2d70c103 5295 qlt_exit();
2c3dfe3f 5296 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5297 ql_log(ql_log_fatal, NULL, 0x0004,
5298 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5299 return -ENODEV;
2c3dfe3f 5300 }
7c3df132
SK		 5301 ql_log(ql_log_info, NULL, 0x0005,
5302 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5303 qla2x00_version_str);
7ee61397 5304 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5305 if (ret) {
5306 kmem_cache_destroy(srb_cachep);
2d70c103 5307 qlt_exit();
fca29703 5308 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5309 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5310 ql_log(ql_log_fatal, NULL, 0x0006,
5311 "pci_register_driver failed...ret=%d Failing load!.\n",
5312 ret);
fca29703
AV		 5313 }
5314 return ret;
1da177e4
LT		 5315}
5316
5317/**
5318 * qla2x00_module_exit - Module cleanup.
5319 **/
5320static void __exit
5321qla2x00_module_exit(void)
5322{
6a03b4cd 5323 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5324 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5325 qla2x00_release_firmware();
354d6b21 5326 kmem_cache_destroy(srb_cachep);
2d70c103 5327 qlt_exit();
a9083016
GM		 5328 if (ctx_cachep)
5329 kmem_cache_destroy(ctx_cachep);
1da177e4 5330 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5331 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5332}
5333
5334module_init(qla2x00_module_init);
5335module_exit(qla2x00_module_exit);
5336
5337MODULE_AUTHOR("QLogic Corporation");
5338MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5339MODULE_LICENSE("GPL");
5340MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5341MODULE_FIRMWARE(FW_FILE_ISP21XX);
5342MODULE_FIRMWARE(FW_FILE_ISP22XX);
5343MODULE_FIRMWARE(FW_FILE_ISP2300);
5344MODULE_FIRMWARE(FW_FILE_ISP2322);
5345MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5346MODULE_FIRMWARE(FW_FILE_ISP25XX);
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