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scsi: qla2xxx: Add multiple queue pair functionality.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
d7459527 33struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 83module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 84MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 85 "Option to enable extended error logging,\n"
86 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
87 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
88 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
89 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
90 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
91 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
92 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
93 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 94 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
95 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 96 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 97 "\t\t0x1e400000 - Preferred value for capturing essential "
98 "debug information (equivalent to old "
99 "ql2xextended_error_logging=1).\n"
3ce8866c 100 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 101
a9083016 102int ql2xshiftctondsd = 6;
f2019cb1 103module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 104MODULE_PARM_DESC(ql2xshiftctondsd,
105 "Set to control shifting of command type processing "
106 "based on total number of SG elements.");
107
7e47e5ca 108int ql2xfdmienable=1;
de187df8 109module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 110module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 111MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 112 "Enables FDMI registrations. "
113 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 114
50280c01
CD		 115#define MAX_Q_DEPTH 32
116static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 117module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
118MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 119 "Maximum queue depth to set for each LUN. "
120 "Default is 32.");
df7baa50 121
9e522cd8
AE		 122int ql2xenabledif = 2;
123module_param(ql2xenabledif, int, S_IRUGO);
bad75002 124MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 125 " Enable T10-CRC-DIF:\n"
126 " Default is 2.\n"
127 " 0 -- No DIF Support\n"
128 " 1 -- Enable DIF for all types\n"
129 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 130
8cb2049c 131int ql2xenablehba_err_chk = 2;
bad75002
AE		 132module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
133MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 134 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 135 " Default is 2.\n"
8cb2049c
AE		 136 " 0 -- Error isolation disabled\n"
137 " 1 -- Error isolation enabled only for DIX Type 0\n"
138 " 2 -- Error isolation enabled for all Types\n");
bad75002 139
e5896bd5 140int ql2xiidmaenable=1;
f2019cb1 141module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 142MODULE_PARM_DESC(ql2xiidmaenable,
143 "Enables iIDMA settings "
144 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
145
d7459527
MH		 146int ql2xmqsupport = 1;
147module_param(ql2xmqsupport, int, S_IRUGO);
148MODULE_PARM_DESC(ql2xmqsupport,
149 "Enable on demand multiple queue pairs support "
150 "Default is 1 for supported. "
151 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 152
153int ql2xfwloadbin;
86e45bf6 154module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 155module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 156MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 157 "Option to specify location from which to load ISP firmware:.\n"
158 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 159 " interface.\n"
160 " 1 -- load firmware from flash.\n"
161 " 0 -- use default semantics.\n");
162
ae97c91e 163int ql2xetsenable;
f2019cb1 164module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 165MODULE_PARM_DESC(ql2xetsenable,
166 "Enables firmware ETS burst."
167 "Default is 0 - skip ETS enablement.");
168
6907869d 169int ql2xdbwr = 1;
86e45bf6 170module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 171MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 172 "Option to specify scheme for request queue posting.\n"
173 " 0 -- Regular doorbell.\n"
174 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 175
f4c496c1 176int ql2xtargetreset = 1;
f2019cb1 177module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 178MODULE_PARM_DESC(ql2xtargetreset,
179 "Enable target reset."
180 "Default is 1 - use hw defaults.");
181
4da26e16 182int ql2xgffidenable;
f2019cb1 183module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 184MODULE_PARM_DESC(ql2xgffidenable,
185 "Enables GFF_ID checks of port type. "
186 "Default is 0 - Do not use GFF_ID information.");
a9083016 187
3822263e 188int ql2xasynctmfenable;
f2019cb1 189module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 190MODULE_PARM_DESC(ql2xasynctmfenable,
191 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
192 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 193
194int ql2xdontresethba;
86e45bf6 195module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 196MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 197 "Option to specify reset behaviour.\n"
198 " 0 (Default) -- Reset on failure.\n"
199 " 1 -- Do not reset on failure.\n");
ed0de87c 200
1abf635d
HR		 201uint64_t ql2xmaxlun = MAX_LUNS;
202module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 203MODULE_PARM_DESC(ql2xmaxlun,
204 "Defines the maximum LU number to register with the SCSI "
205 "midlayer. Default is 65535.");
206
08de2844
GM		 207int ql2xmdcapmask = 0x1F;
208module_param(ql2xmdcapmask, int, S_IRUGO);
209MODULE_PARM_DESC(ql2xmdcapmask,
210 "Set the Minidump driver capture mask level. "
6e96fa7b 211 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 212
3aadff35 213int ql2xmdenable = 1;
08de2844
GM		 214module_param(ql2xmdenable, int, S_IRUGO);
215MODULE_PARM_DESC(ql2xmdenable,
216 "Enable/disable MiniDump. "
3aadff35
GM		 217 "0 - MiniDump disabled. "
218 "1 (Default) - MiniDump enabled.");
08de2844 219
b0d6cabd
HM		 220int ql2xexlogins = 0;
221module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
222MODULE_PARM_DESC(ql2xexlogins,
223 "Number of extended Logins. "
224 "0 (Default)- Disabled.");
225
2f56a7f1
HM		 226int ql2xexchoffld = 0;
227module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
228MODULE_PARM_DESC(ql2xexchoffld,
229 "Number of exchanges to offload. "
230 "0 (Default)- Disabled.");
231
f198cafa
HM		 232int ql2xfwholdabts = 0;
233module_param(ql2xfwholdabts, int, S_IRUGO);
234MODULE_PARM_DESC(ql2xfwholdabts,
235 "Allow FW to hold status IOCB until ABTS rsp received. "
236 "0 (Default) Do not set fw option. "
237 "1 - Set fw option to hold ABTS.");
238
1da177e4 239/*
fa2a1ce5 240 * SCSI host template entry points
1da177e4
LT		 241 */
242static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 243static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 244static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
245static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 246static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 247static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 248static int qla2xxx_eh_abort(struct scsi_cmnd *);
249static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 250static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 251static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
252static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 253
1a2fbf18 254static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 255static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 256static void qla83xx_disable_laser(scsi_qla_host_t *vha);
ce7e4af7 257
a5326f86 258struct scsi_host_template qla2xxx_driver_template = {
1da177e4 259 .module = THIS_MODULE,
cb63067a 260 .name = QLA2XXX_DRIVER_NAME,
a5326f86 261 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 262
263 .eh_abort_handler = qla2xxx_eh_abort,
264 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 265 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 266 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
267 .eh_host_reset_handler = qla2xxx_eh_host_reset,
268
269 .slave_configure = qla2xxx_slave_configure,
270
271 .slave_alloc = qla2xxx_slave_alloc,
272 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 273 .scan_finished = qla2xxx_scan_finished,
274 .scan_start = qla2xxx_scan_start,
db5ed4df 275 .change_queue_depth = scsi_change_queue_depth,
fca29703
AV		 276 .this_id = -1,
277 .cmd_per_lun = 3,
278 .use_clustering = ENABLE_CLUSTERING,
279 .sg_tablesize = SG_ALL,
280
281 .max_sectors = 0xFFFF,
afb046e2 282 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 283
284 .supported_mode = MODE_INITIATOR,
c40ecc12 285 .track_queue_depth = 1,
fca29703
AV		 286};
287
1da177e4 288static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 289struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 290
1da177e4
LT		 291/* TODO Convert to inlines
292 *
293 * Timer routines
294 */
1da177e4 295
2c3dfe3f 296__inline__ void
e315cd28 297qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 298{
e315cd28
AC		 299 init_timer(&vha->timer);
300 vha->timer.expires = jiffies + interval * HZ;
301 vha->timer.data = (unsigned long)vha;
302 vha->timer.function = (void (*)(unsigned long))func;
303 add_timer(&vha->timer);
304 vha->timer_active = 1;
1da177e4
LT		 305}
306
307static inline void
e315cd28 308qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 309{
a9083016 310 /* Currently used for 82XX only. */
7c3df132
SK		 311 if (vha->device_flags & DFLG_DEV_FAILED) {
312 ql_dbg(ql_dbg_timer, vha, 0x600d,
313 "Device in a failed state, returning.\n");
a9083016 314 return;
7c3df132 315 }
a9083016 316
e315cd28 317 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 318}
319
a824ebb3 320static __inline__ void
e315cd28 321qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 322{
e315cd28
AC		 323 del_timer_sync(&vha->timer);
324 vha->timer_active = 0;
1da177e4
LT		 325}
326
1da177e4
LT		 327static int qla2x00_do_dpc(void *data);
328
329static void qla2x00_rst_aen(scsi_qla_host_t *);
330
73208dfd
AC		 331static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
332 struct req_que **, struct rsp_que **);
e30d1756 333static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 334static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 335int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
336 struct qla_qpair *qpair);
1da177e4 337
1da177e4 338/* -------------------------------------------------------------------------- */
9a347ff4
CD		 339static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
340 struct rsp_que *rsp)
73208dfd 341{
7c3df132 342 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 343 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 344 GFP_KERNEL);
345 if (!ha->req_q_map) {
7c3df132
SK		 346 ql_log(ql_log_fatal, vha, 0x003b,
347 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 348 goto fail_req_map;
349 }
350
2afa19a9 351 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 352 GFP_KERNEL);
353 if (!ha->rsp_q_map) {
7c3df132
SK		 354 ql_log(ql_log_fatal, vha, 0x003c,
355 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 356 goto fail_rsp_map;
357 }
d7459527
MH		 358
359 if (ql2xmqsupport && ha->max_qpairs) {
360 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
361 GFP_KERNEL);
362 if (!ha->queue_pair_map) {
363 ql_log(ql_log_fatal, vha, 0x0180,
364 "Unable to allocate memory for queue pair ptrs.\n");
365 goto fail_qpair_map;
366 }
367 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
368 if (ha->base_qpair == NULL) {
369 ql_log(ql_log_warn, vha, 0x0182,
370 "Failed to allocate base queue pair memory.\n");
371 goto fail_base_qpair;
372 }
373 ha->base_qpair->req = req;
374 ha->base_qpair->rsp = rsp;
375 }
376
9a347ff4
CD		 377 /*
378 * Make sure we record at least the request and response queue zero in
379 * case we need to free them if part of the probe fails.
380 */
381 ha->rsp_q_map[0] = rsp;
382 ha->req_q_map[0] = req;
73208dfd
AC		 383 set_bit(0, ha->rsp_qid_map);
384 set_bit(0, ha->req_qid_map);
385 return 1;
386
d7459527
MH		 387fail_base_qpair:
388 kfree(ha->queue_pair_map);
389fail_qpair_map:
390 kfree(ha->rsp_q_map);
391 ha->rsp_q_map = NULL;
73208dfd
AC		 392fail_rsp_map:
393 kfree(ha->req_q_map);
394 ha->req_q_map = NULL;
395fail_req_map:
396 return -ENOMEM;
397}
398
2afa19a9 399static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 400{
8ae6d9c7
GM		 401 if (IS_QLAFX00(ha)) {
402 if (req && req->ring_fx00)
403 dma_free_coherent(&ha->pdev->dev,
404 (req->length_fx00 + 1) * sizeof(request_t),
405 req->ring_fx00, req->dma_fx00);
406 } else if (req && req->ring)
73208dfd
AC		 407 dma_free_coherent(&ha->pdev->dev,
408 (req->length + 1) * sizeof(request_t),
409 req->ring, req->dma);
410
8d93f550
CD		 411 if (req)
412 kfree(req->outstanding_cmds);
413
73208dfd
AC		 414 kfree(req);
415 req = NULL;
416}
417
2afa19a9
AC		 418static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
419{
8ae6d9c7
GM		 420 if (IS_QLAFX00(ha)) {
421 if (rsp && rsp->ring)
422 dma_free_coherent(&ha->pdev->dev,
423 (rsp->length_fx00 + 1) * sizeof(request_t),
424 rsp->ring_fx00, rsp->dma_fx00);
425 } else if (rsp && rsp->ring) {
2afa19a9
AC		 426 dma_free_coherent(&ha->pdev->dev,
427 (rsp->length + 1) * sizeof(response_t),
428 rsp->ring, rsp->dma);
8ae6d9c7 429 }
2afa19a9
AC		 430 kfree(rsp);
431 rsp = NULL;
432}
433
73208dfd
AC		 434static void qla2x00_free_queues(struct qla_hw_data *ha)
435{
436 struct req_que *req;
437 struct rsp_que *rsp;
438 int cnt;
439
2afa19a9 440 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 441 if (!test_bit(cnt, ha->req_qid_map))
442 continue;
443
73208dfd 444 req = ha->req_q_map[cnt];
2afa19a9 445 qla2x00_free_req_que(ha, req);
73208dfd 446 }
73208dfd
AC		 447 kfree(ha->req_q_map);
448 ha->req_q_map = NULL;
2afa19a9
AC		 449
450 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 451 if (!test_bit(cnt, ha->rsp_qid_map))
452 continue;
453
2afa19a9
AC		 454 rsp = ha->rsp_q_map[cnt];
455 qla2x00_free_rsp_que(ha, rsp);
456 }
457 kfree(ha->rsp_q_map);
458 ha->rsp_q_map = NULL;
73208dfd
AC		 459}
460
1da177e4 461static char *
e315cd28 462qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 463{
e315cd28 464 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 465 static char *pci_bus_modes[] = {
466 "33", "66", "100", "133",
467 };
468 uint16_t pci_bus;
469
470 strcpy(str, "PCI");
471 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
472 if (pci_bus) {
473 strcat(str, "-X (");
474 strcat(str, pci_bus_modes[pci_bus]);
475 } else {
476 pci_bus = (ha->pci_attr & BIT_8) >> 8;
477 strcat(str, " (");
478 strcat(str, pci_bus_modes[pci_bus]);
479 }
480 strcat(str, " MHz)");
481
482 return (str);
483}
484
fca29703 485static char *
e315cd28 486qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 487{
488 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 489 struct qla_hw_data *ha = vha->hw;
fca29703 490 uint32_t pci_bus;
fca29703 491
62a276f8 492 if (pci_is_pcie(ha->pdev)) {
fca29703 493 char lwstr[6];
62a276f8 494 uint32_t lstat, lspeed, lwidth;
fca29703 495
62a276f8
BH		 496 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
497 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
498 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 499
500 strcpy(str, "PCIe (");
49300af7
SK		 501 switch (lspeed) {
502 case 1:
c87a0d8c 503 strcat(str, "2.5GT/s ");
49300af7
SK		 504 break;
505 case 2:
c87a0d8c 506 strcat(str, "5.0GT/s ");
49300af7
SK		 507 break;
508 case 3:
509 strcat(str, "8.0GT/s ");
510 break;
511 default:
fca29703 512 strcat(str, "<unknown> ");
49300af7
SK		 513 break;
514 }
fca29703
AV		 515 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
516 strcat(str, lwstr);
517
518 return str;
519 }
520
521 strcpy(str, "PCI");
522 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
523 if (pci_bus == 0 || pci_bus == 8) {
524 strcat(str, " (");
525 strcat(str, pci_bus_modes[pci_bus >> 3]);
526 } else {
527 strcat(str, "-X ");
528 if (pci_bus & BIT_2)
529 strcat(str, "Mode 2");
530 else
531 strcat(str, "Mode 1");
532 strcat(str, " (");
533 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
534 }
535 strcat(str, " MHz)");
536
537 return str;
538}
539
e5f82ab8 540static char *
df57caba 541qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 542{
543 char un_str[10];
e315cd28 544 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 545
df57caba
HM		 546 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
547 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 548
549 if (ha->fw_attributes & BIT_9) {
550 strcat(str, "FLX");
551 return (str);
552 }
553
554 switch (ha->fw_attributes & 0xFF) {
555 case 0x7:
556 strcat(str, "EF");
557 break;
558 case 0x17:
559 strcat(str, "TP");
560 break;
561 case 0x37:
562 strcat(str, "IP");
563 break;
564 case 0x77:
565 strcat(str, "VI");
566 break;
567 default:
568 sprintf(un_str, "(%x)", ha->fw_attributes);
569 strcat(str, un_str);
570 break;
571 }
572 if (ha->fw_attributes & 0x100)
573 strcat(str, "X");
574
575 return (str);
576}
577
e5f82ab8 578static char *
df57caba 579qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 580{
e315cd28 581 struct qla_hw_data *ha = vha->hw;
f0883ac6 582
df57caba 583 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 584 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 585 return str;
fca29703
AV		 586}
587
9ba56b95
GM		 588void
589qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 590{
9ba56b95
GM		 591 srb_t *sp = (srb_t *)ptr;
592 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
593 struct qla_hw_data *ha = sp->fcport->vha->hw;
594 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 595
9ba56b95
GM		 596 if (sp->flags & SRB_DMA_VALID) {
597 scsi_dma_unmap(cmd);
598 sp->flags &= ~SRB_DMA_VALID;
7c3df132 599 }
fca29703 600
9ba56b95
GM		 601 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
602 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
603 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
604 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
605 }
606
607 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
608 /* List assured to be having elements */
f83adb61 609 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 610 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
611 }
612
613 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
614 dma_pool_free(ha->dl_dma_pool, ctx,
615 ((struct crc_context *)ctx)->crc_ctx_dma);
616 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
617 }
618
619 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
620 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 621
9ba56b95
GM		 622 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
623 ctx1->fcp_cmnd_dma);
624 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
625 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
626 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
627 mempool_free(ctx1, ha->ctx_mempool);
628 ctx1 = NULL;
629 }
630
631 CMD_SP(cmd) = NULL;
b00ee7d7 632 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 633}
634
d7459527 635void
9ba56b95
GM		 636qla2x00_sp_compl(void *data, void *ptr, int res)
637{
638 struct qla_hw_data *ha = (struct qla_hw_data *)data;
639 srb_t *sp = (srb_t *)ptr;
640 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
641
642 cmd->result = res;
643
644 if (atomic_read(&sp->ref_count) == 0) {
645 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
646 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
647 sp, GET_CMD_SP(sp));
648 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 649 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 650 return;
651 }
652 if (!atomic_dec_and_test(&sp->ref_count))
653 return;
654
655 qla2x00_sp_free_dma(ha, sp);
656 cmd->scsi_done(cmd);
fca29703
AV		 657}
658
d7459527
MH		 659void
660qla2xxx_qpair_sp_free_dma(void *vha, void *ptr)
661{
662 srb_t *sp = (srb_t *)ptr;
663 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
664 struct qla_hw_data *ha = sp->fcport->vha->hw;
665 void *ctx = GET_CMD_CTX_SP(sp);
666
667 if (sp->flags & SRB_DMA_VALID) {
668 scsi_dma_unmap(cmd);
669 sp->flags &= ~SRB_DMA_VALID;
670 }
671
672 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
673 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
674 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
675 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
676 }
677
678 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
679 /* List assured to be having elements */
680 qla2x00_clean_dsd_pool(ha, sp, NULL);
681 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
682 }
683
684 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
685 dma_pool_free(ha->dl_dma_pool, ctx,
686 ((struct crc_context *)ctx)->crc_ctx_dma);
687 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
688 }
689
690 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
691 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
692
693 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
694 ctx1->fcp_cmnd_dma);
695 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
696 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
697 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
698 mempool_free(ctx1, ha->ctx_mempool);
699 }
700
701 CMD_SP(cmd) = NULL;
702 qla2xxx_rel_qpair_sp(sp->qpair, sp);
703}
704
705void
706qla2xxx_qpair_sp_compl(void *data, void *ptr, int res)
707{
708 srb_t *sp = (srb_t *)ptr;
709 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
710
711 cmd->result = res;
712
713 if (atomic_read(&sp->ref_count) == 0) {
714 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
715 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
716 sp, GET_CMD_SP(sp));
717 if (ql2xextended_error_logging & ql_dbg_io)
718 WARN_ON(atomic_read(&sp->ref_count) == 0);
719 return;
720 }
721 if (!atomic_dec_and_test(&sp->ref_count))
722 return;
723
724 qla2xxx_qpair_sp_free_dma(sp->fcport->vha, sp);
725 cmd->scsi_done(cmd);
726}
727
8ae6d9c7
GM		 728/* If we are SP1 here, we need to still take and release the host_lock as SP1
729 * does not have the changes necessary to avoid taking host->host_lock.
730 */
1da177e4 731static int
f5e3e40b 732qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 733{
134ae078 734 scsi_qla_host_t *vha = shost_priv(host);
fca29703 735 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 736 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 737 struct qla_hw_data *ha = vha->hw;
738 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 739 srb_t *sp;
740 int rval;
d7459527 741 struct qla_qpair *qpair;
fca29703 742
04dfaa53
MFO		 743 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
744 cmd->result = DID_NO_CONNECT << 16;
745 goto qc24_fail_command;
746 }
747
d7459527
MH		 748 if (vha->vp_idx && vha->qpair) {
749 qpair = vha->qpair;
750 return qla2xxx_mqueuecommand(host, cmd, qpair);
751 }
752
85880801 753 if (ha->flags.eeh_busy) {
7c3df132 754 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 755 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 756 "PCI Channel IO permanent failure, exiting "
757 "cmd=%p.\n", cmd);
b9b12f73 758 cmd->result = DID_NO_CONNECT << 16;
7c3df132 759 } else {
5f28d2d7 760 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 761 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 762 cmd->result = DID_REQUEUE << 16;
7c3df132 763 }
14e660e6
SJ		 764 goto qc24_fail_command;
765 }
766
19a7b4ae
JSEC		 767 rval = fc_remote_port_chkready(rport);
768 if (rval) {
769 cmd->result = rval;
5f28d2d7 770 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 771 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
772 cmd, rval);
fca29703
AV		 773 goto qc24_fail_command;
774 }
775
bad75002
AE		 776 if (!vha->flags.difdix_supported &&
777 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 778 ql_dbg(ql_dbg_io, vha, 0x3004,
779 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
780 cmd);
bad75002
AE		 781 cmd->result = DID_NO_CONNECT << 16;
782 goto qc24_fail_command;
783 }
aa651be8
CD		 784
785 if (!fcport) {
786 cmd->result = DID_NO_CONNECT << 16;
787 goto qc24_fail_command;
788 }
789
fca29703
AV		 790 if (atomic_read(&fcport->state) != FCS_ONLINE) {
791 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 792 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 793 ql_dbg(ql_dbg_io, vha, 0x3005,
794 "Returning DNC, fcport_state=%d loop_state=%d.\n",
795 atomic_read(&fcport->state),
796 atomic_read(&base_vha->loop_state));
fca29703
AV		 797 cmd->result = DID_NO_CONNECT << 16;
798 goto qc24_fail_command;
799 }
7b594131 800 goto qc24_target_busy;
fca29703
AV		 801 }
802
e05fe292
CD		 803 /*
804 * Return target busy if we've received a non-zero retry_delay_timer
805 * in a FCP_RSP.
806 */
975f7d46
BP		 807 if (fcport->retry_delay_timestamp == 0) {
808 /* retry delay not set */
809 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 810 fcport->retry_delay_timestamp = 0;
811 else
812 goto qc24_target_busy;
813
b00ee7d7 814 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 815 if (!sp)
f5e3e40b 816 goto qc24_host_busy;
fca29703 817
9ba56b95
GM		 818 sp->u.scmd.cmd = cmd;
819 sp->type = SRB_SCSI_CMD;
820 atomic_set(&sp->ref_count, 1);
821 CMD_SP(cmd) = (void *)sp;
822 sp->free = qla2x00_sp_free_dma;
823 sp->done = qla2x00_sp_compl;
824
e315cd28 825 rval = ha->isp_ops->start_scsi(sp);
7c3df132 826 if (rval != QLA_SUCCESS) {
53016ed3 827 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 828 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 829 goto qc24_host_busy_free_sp;
7c3df132 830 }
fca29703 831
fca29703
AV		 832 return 0;
833
834qc24_host_busy_free_sp:
9ba56b95 835 qla2x00_sp_free_dma(ha, sp);
fca29703 836
f5e3e40b 837qc24_host_busy:
fca29703
AV		 838 return SCSI_MLQUEUE_HOST_BUSY;
839
7b594131
MC		 840qc24_target_busy:
841 return SCSI_MLQUEUE_TARGET_BUSY;
842
fca29703 843qc24_fail_command:
f5e3e40b 844 cmd->scsi_done(cmd);
fca29703
AV		 845
846 return 0;
847}
848
d7459527
MH		 849/* For MQ supported I/O */
850int
851qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
852 struct qla_qpair *qpair)
853{
854 scsi_qla_host_t *vha = shost_priv(host);
855 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
856 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
857 struct qla_hw_data *ha = vha->hw;
858 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
859 srb_t *sp;
860 int rval;
861
862 rval = fc_remote_port_chkready(rport);
863 if (rval) {
864 cmd->result = rval;
865 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
866 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
867 cmd, rval);
868 goto qc24_fail_command;
869 }
870
871 if (!fcport) {
872 cmd->result = DID_NO_CONNECT << 16;
873 goto qc24_fail_command;
874 }
875
876 if (atomic_read(&fcport->state) != FCS_ONLINE) {
877 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
878 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
879 ql_dbg(ql_dbg_io, vha, 0x3077,
880 "Returning DNC, fcport_state=%d loop_state=%d.\n",
881 atomic_read(&fcport->state),
882 atomic_read(&base_vha->loop_state));
883 cmd->result = DID_NO_CONNECT << 16;
884 goto qc24_fail_command;
885 }
886 goto qc24_target_busy;
887 }
888
889 /*
890 * Return target busy if we've received a non-zero retry_delay_timer
891 * in a FCP_RSP.
892 */
893 if (fcport->retry_delay_timestamp == 0) {
894 /* retry delay not set */
895 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
896 fcport->retry_delay_timestamp = 0;
897 else
898 goto qc24_target_busy;
899
900 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
901 if (!sp)
902 goto qc24_host_busy;
903
904 sp->u.scmd.cmd = cmd;
905 sp->type = SRB_SCSI_CMD;
906 atomic_set(&sp->ref_count, 1);
907 CMD_SP(cmd) = (void *)sp;
908 sp->free = qla2xxx_qpair_sp_free_dma;
909 sp->done = qla2xxx_qpair_sp_compl;
910 sp->qpair = qpair;
911
912 rval = ha->isp_ops->start_scsi_mq(sp);
913 if (rval != QLA_SUCCESS) {
914 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
915 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
916 if (rval == QLA_INTERFACE_ERROR)
917 goto qc24_fail_command;
918 goto qc24_host_busy_free_sp;
919 }
920
921 return 0;
922
923qc24_host_busy_free_sp:
924 qla2xxx_qpair_sp_free_dma(vha, sp);
925
926qc24_host_busy:
927 return SCSI_MLQUEUE_HOST_BUSY;
928
929qc24_target_busy:
930 return SCSI_MLQUEUE_TARGET_BUSY;
931
932qc24_fail_command:
933 cmd->scsi_done(cmd);
934
935 return 0;
936}
937
1da177e4
LT		 938/*
939 * qla2x00_eh_wait_on_command
940 * Waits for the command to be returned by the Firmware for some
941 * max time.
942 *
943 * Input:
1da177e4 944 * cmd = Scsi Command to wait on.
1da177e4
LT		 945 *
946 * Return:
947 * Not Found : 0
948 * Found : 1
949 */
950static int
e315cd28 951qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 952{
fe74c71f 953#define ABORT_POLLING_PERIOD 1000
478c3b03 954#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 955 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 956 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
957 struct qla_hw_data *ha = vha->hw;
f4f051eb 958 int ret = QLA_SUCCESS;
1da177e4 959
85880801 960 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 961 ql_dbg(ql_dbg_taskm, vha, 0x8005,
962 "Return:eh_wait.\n");
85880801
AV		 963 return ret;
964 }
965
d970432c 966 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 967 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 968 }
969 if (CMD_SP(cmd))
970 ret = QLA_FUNCTION_FAILED;
1da177e4 971
f4f051eb 972 return ret;
1da177e4
LT		 973}
974
975/*
976 * qla2x00_wait_for_hba_online
fa2a1ce5 977 * Wait till the HBA is online after going through
1da177e4
LT		 978 * <= MAX_RETRIES_OF_ISP_ABORT or
979 * finally HBA is disabled ie marked offline
980 *
981 * Input:
982 * ha - pointer to host adapter structure
fa2a1ce5
AV		 983 *
984 * Note:
1da177e4
LT		 985 * Does context switching-Release SPIN_LOCK
986 * (if any) before calling this routine.
987 *
988 * Return:
989 * Success (Adapter is online) : 0
990 * Failed (Adapter is offline/disabled) : 1
991 */
854165f4 992int
e315cd28 993qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 994{
fca29703
AV		 995 int return_status;
996 unsigned long wait_online;
e315cd28
AC		 997 struct qla_hw_data *ha = vha->hw;
998 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 999
fa2a1ce5 1000 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1001 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1002 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1003 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1004 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1005
1006 msleep(1000);
1007 }
e315cd28 1008 if (base_vha->flags.online)
fa2a1ce5 1009 return_status = QLA_SUCCESS;
1da177e4
LT		 1010 else
1011 return_status = QLA_FUNCTION_FAILED;
1012
1da177e4
LT		 1013 return (return_status);
1014}
1015
86fbee86 1016/*
638a1a01
SC		 1017 * qla2x00_wait_for_hba_ready
1018 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1019 *
1020 * Input:
1021 * ha - pointer to host adapter structure
1022 *
1023 * Note:
1024 * Does context switching-Release SPIN_LOCK
1025 * (if any) before calling this routine.
1026 *
86fbee86 1027 */
638a1a01
SC		 1028static void
1029qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1030{
86fbee86 1031 struct qla_hw_data *ha = vha->hw;
783e0dc4 1032 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1033
1d483901
DC		 1034 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1035 ha->flags.mbox_busy) ||
1036 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1037 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1038 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1039 break;
86fbee86 1040 msleep(1000);
783e0dc4 1041 }
86fbee86
LC		 1042}
1043
2533cf67
LC		 1044int
1045qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1046{
1047 int return_status;
1048 unsigned long wait_reset;
1049 struct qla_hw_data *ha = vha->hw;
1050 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1051
1052 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1053 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1054 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1055 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1056 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1057
1058 msleep(1000);
1059
1060 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1061 ha->flags.chip_reset_done)
1062 break;
1063 }
1064 if (ha->flags.chip_reset_done)
1065 return_status = QLA_SUCCESS;
1066 else
1067 return_status = QLA_FUNCTION_FAILED;
1068
1069 return return_status;
1070}
1071
083a469d
GM		 1072static void
1073sp_get(struct srb *sp)
1074{
1075 atomic_inc(&sp->ref_count);
1076}
1077
a465537a
SC		 1078#define ISP_REG_DISCONNECT 0xffffffffU
1079/**************************************************************************
1080* qla2x00_isp_reg_stat
1081*
1082* Description:
1083* Read the host status register of ISP before aborting the command.
1084*
1085* Input:
1086* ha = pointer to host adapter structure.
1087*
1088*
1089* Returns:
1090* Either true or false.
1091*
1092* Note: Return true if there is register disconnect.
1093**************************************************************************/
1094static inline
1095uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1096{
1097 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1098
1099 return ((RD_REG_DWORD(&reg->host_status)) == ISP_REG_DISCONNECT);
1100}
1101
1da177e4
LT		 1102/**************************************************************************
1103* qla2xxx_eh_abort
1104*
1105* Description:
1106* The abort function will abort the specified command.
1107*
1108* Input:
1109* cmd = Linux SCSI command packet to be aborted.
1110*
1111* Returns:
1112* Either SUCCESS or FAILED.
1113*
1114* Note:
2ea00202 1115* Only return FAILED if command not returned by firmware.
1da177e4 1116**************************************************************************/
e5f82ab8 1117static int
1da177e4
LT		 1118qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1119{
e315cd28 1120 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1121 srb_t *sp;
4e98d3b8 1122 int ret;
9cb78c16
HR		 1123 unsigned int id;
1124 uint64_t lun;
18e144d3 1125 unsigned long flags;
f934c9d0 1126 int rval, wait = 0;
e315cd28 1127 struct qla_hw_data *ha = vha->hw;
1da177e4 1128
a465537a
SC		 1129 if (qla2x00_isp_reg_stat(ha)) {
1130 ql_log(ql_log_info, vha, 0x8042,
1131 "PCI/Register disconnect, exiting.\n");
1132 return FAILED;
1133 }
f4f051eb 1134 if (!CMD_SP(cmd))
2ea00202 1135 return SUCCESS;
1da177e4 1136
4e98d3b8
AV		 1137 ret = fc_block_scsi_eh(cmd);
1138 if (ret != 0)
1139 return ret;
1140 ret = SUCCESS;
1141
f4f051eb
AV		 1142 id = cmd->device->id;
1143 lun = cmd->device->lun;
1da177e4 1144
e315cd28 1145 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1146 sp = (srb_t *) CMD_SP(cmd);
1147 if (!sp) {
1148 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1149 return SUCCESS;
1150 }
1da177e4 1151
7c3df132 1152 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1153 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1154 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1155
170babc3
MC		 1156 /* Get a reference to the sp and drop the lock.*/
1157 sp_get(sp);
083a469d 1158
e315cd28 1159 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1160 rval = ha->isp_ops->abort_command(sp);
1161 if (rval) {
96219424 1162 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1163 ret = SUCCESS;
96219424 1164 else
f934c9d0
CD		 1165 ret = FAILED;
1166
7c3df132 1167 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1168 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1169 } else {
7c3df132 1170 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1171 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1172 wait = 1;
1173 }
75942064
SK		 1174
1175 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 1176 sp->done(ha, sp, 0);
75942064 1177 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1178
bc91ade9
CD		 1179 /* Did the command return during mailbox execution? */
1180 if (ret == FAILED && !CMD_SP(cmd))
1181 ret = SUCCESS;
1182
f4f051eb 1183 /* Wait for the command to be returned. */
2ea00202 1184 if (wait) {
e315cd28 1185 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1186 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1187 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1188 ret = FAILED;
f4f051eb 1189 }
1da177e4 1190 }
1da177e4 1191
7c3df132 1192 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1193 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1194 vha->host_no, id, lun, wait, ret);
1da177e4 1195
f4f051eb
AV		 1196 return ret;
1197}
1da177e4 1198
4d78c973 1199int
e315cd28 1200qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1201 uint64_t l, enum nexus_wait_type type)
f4f051eb 1202{
17d98630 1203 int cnt, match, status;
18e144d3 1204 unsigned long flags;
e315cd28 1205 struct qla_hw_data *ha = vha->hw;
73208dfd 1206 struct req_que *req;
4d78c973 1207 srb_t *sp;
9ba56b95 1208 struct scsi_cmnd *cmd;
1da177e4 1209
523ec773 1210 status = QLA_SUCCESS;
17d98630 1211
e315cd28 1212 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1213 req = vha->req;
17d98630 1214 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1215 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1216 sp = req->outstanding_cmds[cnt];
1217 if (!sp)
523ec773 1218 continue;
9ba56b95 1219 if (sp->type != SRB_SCSI_CMD)
cf53b069 1220 continue;
17d98630
AC		 1221 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1222 continue;
1223 match = 0;
9ba56b95 1224 cmd = GET_CMD_SP(sp);
17d98630
AC		 1225 switch (type) {
1226 case WAIT_HOST:
1227 match = 1;
1228 break;
1229 case WAIT_TARGET:
9ba56b95 1230 match = cmd->device->id == t;
17d98630
AC		 1231 break;
1232 case WAIT_LUN:
9ba56b95
GM		 1233 match = (cmd->device->id == t &&
1234 cmd->device->lun == l);
17d98630 1235 break;
73208dfd 1236 }
17d98630
AC		 1237 if (!match)
1238 continue;
1239
1240 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1241 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1242 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1243 }
e315cd28 1244 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1245
1246 return status;
1da177e4
LT		 1247}
1248
523ec773
AV		 1249static char *reset_errors[] = {
1250 "HBA not online",
1251 "HBA not ready",
1252 "Task management failed",
1253 "Waiting for command completions",
1254};
1da177e4 1255
e5f82ab8 1256static int
523ec773 1257__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1258 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1259{
e315cd28 1260 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1261 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1262 int err;
1da177e4 1263
7c3df132 1264 if (!fcport) {
523ec773 1265 return FAILED;
7c3df132 1266 }
1da177e4 1267
4e98d3b8
AV		 1268 err = fc_block_scsi_eh(cmd);
1269 if (err != 0)
1270 return err;
1271
7c3df132 1272 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1273 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1274 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1275
523ec773 1276 err = 0;
7c3df132
SK		 1277 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1278 ql_log(ql_log_warn, vha, 0x800a,
1279 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1280 goto eh_reset_failed;
7c3df132 1281 }
523ec773 1282 err = 2;
2afa19a9 1283 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1284 != QLA_SUCCESS) {
1285 ql_log(ql_log_warn, vha, 0x800c,
1286 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1287 goto eh_reset_failed;
7c3df132 1288 }
523ec773 1289 err = 3;
e315cd28 1290 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1291 cmd->device->lun, type) != QLA_SUCCESS) {
1292 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1293 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1294 goto eh_reset_failed;
7c3df132 1295 }
523ec773 1296
7c3df132 1297 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1298 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1299 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1300
1301 return SUCCESS;
1302
4d78c973 1303eh_reset_failed:
7c3df132 1304 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1305 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1306 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1307 cmd);
523ec773
AV		 1308 return FAILED;
1309}
1da177e4 1310
523ec773
AV		 1311static int
1312qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1313{
e315cd28
AC		 1314 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1315 struct qla_hw_data *ha = vha->hw;
1da177e4 1316
a465537a
SC		 1317 if (qla2x00_isp_reg_stat(ha)) {
1318 ql_log(ql_log_info, vha, 0x803e,
1319 "PCI/Register disconnect, exiting.\n");
1320 return FAILED;
1321 }
1322
523ec773
AV		 1323 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1324 ha->isp_ops->lun_reset);
1da177e4
LT		 1325}
1326
1da177e4 1327static int
523ec773 1328qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1329{
e315cd28
AC		 1330 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1331 struct qla_hw_data *ha = vha->hw;
1da177e4 1332
a465537a
SC		 1333 if (qla2x00_isp_reg_stat(ha)) {
1334 ql_log(ql_log_info, vha, 0x803f,
1335 "PCI/Register disconnect, exiting.\n");
1336 return FAILED;
1337 }
1338
523ec773
AV		 1339 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1340 ha->isp_ops->target_reset);
1da177e4
LT		 1341}
1342
1da177e4
LT		 1343/**************************************************************************
1344* qla2xxx_eh_bus_reset
1345*
1346* Description:
1347* The bus reset function will reset the bus and abort any executing
1348* commands.
1349*
1350* Input:
1351* cmd = Linux SCSI command packet of the command that cause the
1352* bus reset.
1353*
1354* Returns:
1355* SUCCESS/FAILURE (defined as macro in scsi.h).
1356*
1357**************************************************************************/
e5f82ab8 1358static int
1da177e4
LT		 1359qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1360{
e315cd28 1361 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1362 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1363 int ret = FAILED;
9cb78c16
HR		 1364 unsigned int id;
1365 uint64_t lun;
a465537a
SC		 1366 struct qla_hw_data *ha = vha->hw;
1367
1368 if (qla2x00_isp_reg_stat(ha)) {
1369 ql_log(ql_log_info, vha, 0x8040,
1370 "PCI/Register disconnect, exiting.\n");
1371 return FAILED;
1372 }
f4f051eb 1373
f4f051eb
AV		 1374 id = cmd->device->id;
1375 lun = cmd->device->lun;
1da177e4 1376
7c3df132 1377 if (!fcport) {
f4f051eb 1378 return ret;
7c3df132 1379 }
1da177e4 1380
4e98d3b8
AV		 1381 ret = fc_block_scsi_eh(cmd);
1382 if (ret != 0)
1383 return ret;
1384 ret = FAILED;
1385
7c3df132 1386 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1387 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1388
e315cd28 1389 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1390 ql_log(ql_log_fatal, vha, 0x8013,
1391 "Wait for hba online failed board disabled.\n");
f4f051eb 1392 goto eh_bus_reset_done;
1da177e4
LT		 1393 }
1394
ad537689
SK		 1395 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1396 ret = SUCCESS;
1397
f4f051eb
AV		 1398 if (ret == FAILED)
1399 goto eh_bus_reset_done;
1da177e4 1400
9a41a62b 1401 /* Flush outstanding commands. */
4d78c973 1402 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1403 QLA_SUCCESS) {
1404 ql_log(ql_log_warn, vha, 0x8014,
1405 "Wait for pending commands failed.\n");
9a41a62b 1406 ret = FAILED;
7c3df132 1407 }
1da177e4 1408
f4f051eb 1409eh_bus_reset_done:
7c3df132 1410 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1411 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1412 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1413
f4f051eb 1414 return ret;
1da177e4
LT		 1415}
1416
1417/**************************************************************************
1418* qla2xxx_eh_host_reset
1419*
1420* Description:
1421* The reset function will reset the Adapter.
1422*
1423* Input:
1424* cmd = Linux SCSI command packet of the command that cause the
1425* adapter reset.
1426*
1427* Returns:
1428* Either SUCCESS or FAILED.
1429*
1430* Note:
1431**************************************************************************/
e5f82ab8 1432static int
1da177e4
LT		 1433qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1434{
e315cd28 1435 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1436 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1437 int ret = FAILED;
9cb78c16
HR		 1438 unsigned int id;
1439 uint64_t lun;
e315cd28 1440 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1441
a465537a
SC		 1442 if (qla2x00_isp_reg_stat(ha)) {
1443 ql_log(ql_log_info, vha, 0x8041,
1444 "PCI/Register disconnect, exiting.\n");
1445 schedule_work(&ha->board_disable);
1446 return SUCCESS;
1447 }
1448
f4f051eb
AV		 1449 id = cmd->device->id;
1450 lun = cmd->device->lun;
f4f051eb 1451
7c3df132 1452 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1453 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1454
63ee7072
CD		 1455 /*
1456 * No point in issuing another reset if one is active. Also do not
1457 * attempt a reset if we are updating flash.
1458 */
1459 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1460 goto eh_host_reset_lock;
1da177e4 1461
e315cd28
AC		 1462 if (vha != base_vha) {
1463 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1464 goto eh_host_reset_lock;
e315cd28 1465 } else {
7ec0effd 1466 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1467 if (!qla82xx_fcoe_ctx_reset(vha)) {
1468 /* Ctx reset success */
1469 ret = SUCCESS;
1470 goto eh_host_reset_lock;
1471 }
1472 /* fall thru if ctx reset failed */
1473 }
68ca949c
AC		 1474 if (ha->wq)
1475 flush_workqueue(ha->wq);
1476
e315cd28 1477 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1478 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1479 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1480 /* failed. schedule dpc to try */
1481 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1482
7c3df132
SK		 1483 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1484 ql_log(ql_log_warn, vha, 0x802a,
1485 "wait for hba online failed.\n");
e315cd28 1486 goto eh_host_reset_lock;
7c3df132 1487 }
e315cd28
AC		 1488 }
1489 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1490 }
1da177e4 1491
e315cd28 1492 /* Waiting for command to be returned to OS.*/
4d78c973 1493 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1494 QLA_SUCCESS)
f4f051eb 1495 ret = SUCCESS;
1da177e4 1496
f4f051eb 1497eh_host_reset_lock:
cfb0919c 1498 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1499 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1500 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1501
f4f051eb
AV		 1502 return ret;
1503}
1da177e4
LT		 1504
1505/*
1506* qla2x00_loop_reset
1507* Issue loop reset.
1508*
1509* Input:
1510* ha = adapter block pointer.
1511*
1512* Returns:
1513* 0 = success
1514*/
a4722cf2 1515int
e315cd28 1516qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1517{
0c8c39af 1518 int ret;
bdf79621 1519 struct fc_port *fcport;
e315cd28 1520 struct qla_hw_data *ha = vha->hw;
1da177e4 1521
5854771e
AB		 1522 if (IS_QLAFX00(ha)) {
1523 return qlafx00_loop_reset(vha);
1524 }
1525
f4c496c1 1526 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1527 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1528 if (fcport->port_type != FCT_TARGET)
1529 continue;
1530
1531 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1532 if (ret != QLA_SUCCESS) {
7c3df132 1533 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1534 "Bus Reset failed: Reset=%d "
7c3df132 1535 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1536 }
1537 }
1538 }
1539
8ae6d9c7 1540
6246b8a1 1541 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1542 atomic_set(&vha->loop_state, LOOP_DOWN);
1543 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1544 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1545 ret = qla2x00_full_login_lip(vha);
0c8c39af 1546 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1547 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1548 "full_login_lip=%d.\n", ret);
749af3d5 1549 }
0c8c39af
AV		 1550 }
1551
0d6e61bc 1552 if (ha->flags.enable_lip_reset) {
e315cd28 1553 ret = qla2x00_lip_reset(vha);
ad537689 1554 if (ret != QLA_SUCCESS)
7c3df132
SK		 1555 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1556 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1557 }
1558
1da177e4 1559 /* Issue marker command only when we are going to start the I/O */
e315cd28 1560 vha->marker_needed = 1;
1da177e4 1561
0c8c39af 1562 return QLA_SUCCESS;
1da177e4
LT		 1563}
1564
df4bf0bb 1565void
e315cd28 1566qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1567{
73208dfd 1568 int que, cnt;
df4bf0bb
AV		 1569 unsigned long flags;
1570 srb_t *sp;
e315cd28 1571 struct qla_hw_data *ha = vha->hw;
73208dfd 1572 struct req_que *req;
df4bf0bb 1573
c0cb4496
AE		 1574 qlt_host_reset_handler(ha);
1575
df4bf0bb 1576 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1577 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1578 req = ha->req_q_map[que];
73208dfd
AC		 1579 if (!req)
1580 continue;
8d93f550
CD		 1581 if (!req->outstanding_cmds)
1582 continue;
1583 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1584 sp = req->outstanding_cmds[cnt];
e612d465 1585 if (sp) {
c733ab35
MFO		 1586 /* Don't abort commands in adapter during EEH
1587 * recovery as it's not accessible/responding.
1535aa75 1588 */
c733ab35
MFO		 1589 if (!ha->flags.eeh_busy) {
1590 /* Get a reference to the sp and drop the lock.
1591 * The reference ensures this sp->done() call
1592 * - and not the call in qla2xxx_eh_abort() -
1593 * ends the SCSI command (with result 'res').
1594 */
1595 sp_get(sp);
1596 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1597 qla2xxx_eh_abort(GET_CMD_SP(sp));
1598 spin_lock_irqsave(&ha->hardware_lock, flags);
1599 }
73208dfd 1600 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1601 sp->done(vha, sp, res);
73208dfd 1602 }
df4bf0bb
AV		 1603 }
1604 }
1605 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1606}
1607
f4f051eb
AV		 1608static int
1609qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1610{
bdf79621 1611 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1612
19a7b4ae 1613 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1614 return -ENXIO;
bdf79621 1615
19a7b4ae 1616 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1617
f4f051eb
AV		 1618 return 0;
1619}
1da177e4 1620
f4f051eb
AV		 1621static int
1622qla2xxx_slave_configure(struct scsi_device *sdev)
1623{
e315cd28 1624 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1625 struct req_que *req = vha->req;
8482e118 1626
9e522cd8
AE		 1627 if (IS_T10_PI_CAPABLE(vha->hw))
1628 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1629
db5ed4df 1630 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1631 return 0;
1632}
1da177e4 1633
f4f051eb
AV		 1634static void
1635qla2xxx_slave_destroy(struct scsi_device *sdev)
1636{
1637 sdev->hostdata = NULL;
1da177e4
LT		 1638}
1639
1640/**
1641 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1642 * @ha: HA context
1643 *
1644 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1645 * supported addressing method.
1646 */
1647static void
53303c42 1648qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1649{
7524f9b9 1650 /* Assume a 32bit DMA mask. */
1da177e4 1651 ha->flags.enable_64bit_addressing = 0;
1da177e4 1652
6a35528a 1653 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1654 /* Any upper-dword bits set? */
1655 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1656 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1657 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1658 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1659 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1660 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1661 return;
1da177e4 1662 }
1da177e4 1663 }
7524f9b9 1664
284901a9
YH		 1665 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1666 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1667}
1668
fd34f556 1669static void
e315cd28 1670qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1671{
1672 unsigned long flags = 0;
1673 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1674
1675 spin_lock_irqsave(&ha->hardware_lock, flags);
1676 ha->interrupts_on = 1;
1677 /* enable risc and host interrupts */
1678 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1679 RD_REG_WORD(&reg->ictrl);
1680 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1681
1682}
1683
1684static void
e315cd28 1685qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1686{
1687 unsigned long flags = 0;
1688 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1689
1690 spin_lock_irqsave(&ha->hardware_lock, flags);
1691 ha->interrupts_on = 0;
1692 /* disable risc and host interrupts */
1693 WRT_REG_WORD(&reg->ictrl, 0);
1694 RD_REG_WORD(&reg->ictrl);
1695 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1696}
1697
1698static void
e315cd28 1699qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1700{
1701 unsigned long flags = 0;
1702 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1703
1704 spin_lock_irqsave(&ha->hardware_lock, flags);
1705 ha->interrupts_on = 1;
1706 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1707 RD_REG_DWORD(&reg->ictrl);
1708 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1709}
1710
1711static void
e315cd28 1712qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1713{
1714 unsigned long flags = 0;
1715 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1716
124f85e6
AV		 1717 if (IS_NOPOLLING_TYPE(ha))
1718 return;
fd34f556
AV		 1719 spin_lock_irqsave(&ha->hardware_lock, flags);
1720 ha->interrupts_on = 0;
1721 WRT_REG_DWORD(&reg->ictrl, 0);
1722 RD_REG_DWORD(&reg->ictrl);
1723 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1724}
1725
706f457d
GM		 1726static int
1727qla2x00_iospace_config(struct qla_hw_data *ha)
1728{
1729 resource_size_t pio;
1730 uint16_t msix;
706f457d 1731
706f457d
GM		 1732 if (pci_request_selected_regions(ha->pdev, ha->bars,
1733 QLA2XXX_DRIVER_NAME)) {
1734 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1735 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1736 pci_name(ha->pdev));
1737 goto iospace_error_exit;
1738 }
1739 if (!(ha->bars & 1))
1740 goto skip_pio;
1741
1742 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1743 pio = pci_resource_start(ha->pdev, 0);
1744 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1745 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1746 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1747 "Invalid pci I/O region size (%s).\n",
1748 pci_name(ha->pdev));
1749 pio = 0;
1750 }
1751 } else {
1752 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1753 "Region #0 no a PIO resource (%s).\n",
1754 pci_name(ha->pdev));
1755 pio = 0;
1756 }
1757 ha->pio_address = pio;
1758 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1759 "PIO address=%llu.\n",
1760 (unsigned long long)ha->pio_address);
1761
1762skip_pio:
1763 /* Use MMIO operations for all accesses. */
1764 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1765 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1766 "Region #1 not an MMIO resource (%s), aborting.\n",
1767 pci_name(ha->pdev));
1768 goto iospace_error_exit;
1769 }
1770 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1771 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1772 "Invalid PCI mem region size (%s), aborting.\n",
1773 pci_name(ha->pdev));
1774 goto iospace_error_exit;
1775 }
1776
1777 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1778 if (!ha->iobase) {
1779 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1780 "Cannot remap MMIO (%s), aborting.\n",
1781 pci_name(ha->pdev));
1782 goto iospace_error_exit;
1783 }
1784
1785 /* Determine queue resources */
1786 ha->max_req_queues = ha->max_rsp_queues = 1;
d7459527 1787 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1788 goto mqiobase_exit;
1789
1790 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1791 pci_resource_len(ha->pdev, 3));
1792 if (ha->mqiobase) {
1793 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1794 "MQIO Base=%p.\n", ha->mqiobase);
1795 /* Read MSIX vector size of the board */
1796 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1797 ha->msix_count = msix + 1;
706f457d 1798 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1799 /* MB interrupt uses 1 vector */
1800 ha->max_req_queues = ha->msix_count - 1;
1801 ha->max_rsp_queues = ha->max_req_queues;
1802 /* Queue pairs is the max value minus the base queue pair */
1803 ha->max_qpairs = ha->max_rsp_queues - 1;
1804 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1805 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1806
706f457d 1807 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1808 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1809 } else
1810 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1811 "BAR 3 not enabled.\n");
1812
1813mqiobase_exit:
1814 ha->msix_count = ha->max_rsp_queues + 1;
1815 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1816 "MSIX Count:%d.\n", ha->msix_count);
1817 return (0);
1818
1819iospace_error_exit:
1820 return (-ENOMEM);
1821}
1822
1823
6246b8a1
GM		 1824static int
1825qla83xx_iospace_config(struct qla_hw_data *ha)
1826{
1827 uint16_t msix;
6246b8a1
GM		 1828
1829 if (pci_request_selected_regions(ha->pdev, ha->bars,
1830 QLA2XXX_DRIVER_NAME)) {
1831 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1832 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1833 pci_name(ha->pdev));
1834
1835 goto iospace_error_exit;
1836 }
1837
1838 /* Use MMIO operations for all accesses. */
1839 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1840 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1841 "Invalid pci I/O region size (%s).\n",
1842 pci_name(ha->pdev));
1843 goto iospace_error_exit;
1844 }
1845 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1846 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1847 "Invalid PCI mem region size (%s), aborting\n",
1848 pci_name(ha->pdev));
1849 goto iospace_error_exit;
1850 }
1851
1852 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1853 if (!ha->iobase) {
1854 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1855 "Cannot remap MMIO (%s), aborting.\n",
1856 pci_name(ha->pdev));
1857 goto iospace_error_exit;
1858 }
1859
1860 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1861 /* 83XX 26XX always use MQ type access for queues
1862 * - mbar 2, a.k.a region 4 */
1863 ha->max_req_queues = ha->max_rsp_queues = 1;
1864 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1865 pci_resource_len(ha->pdev, 4));
1866
1867 if (!ha->mqiobase) {
1868 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1869 "BAR2/region4 not enabled\n");
1870 goto mqiobase_exit;
1871 }
1872
1873 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1874 pci_resource_len(ha->pdev, 2));
1875 if (ha->msixbase) {
1876 /* Read MSIX vector size of the board */
1877 pci_read_config_word(ha->pdev,
1878 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1879 ha->msix_count = msix + 1;
6246b8a1
GM		 1880 /* Max queues are bounded by available msix vectors */
1881 /* queue 0 uses two msix vectors */
d7459527
MH		 1882 if (ql2xmqsupport) {
1883 /* MB interrupt uses 1 vector */
1884 ha->max_req_queues = ha->msix_count - 1;
1885 ha->max_rsp_queues = ha->max_req_queues;
1886 /* Queue pairs is the max value minus
1887 * the base queue pair */
1888 ha->max_qpairs = ha->max_req_queues - 1;
1889 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc010,
1890 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1891 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1892 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1893 }
1894 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1895 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1896 } else
1897 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1898 "BAR 1 not enabled.\n");
1899
1900mqiobase_exit:
1901 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1902
1903 qlt_83xx_iospace_config(ha);
1904
6246b8a1
GM		 1905 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1906 "MSIX Count:%d.\n", ha->msix_count);
1907 return 0;
1908
1909iospace_error_exit:
1910 return -ENOMEM;
1911}
1912
fd34f556
AV		 1913static struct isp_operations qla2100_isp_ops = {
1914 .pci_config = qla2100_pci_config,
1915 .reset_chip = qla2x00_reset_chip,
1916 .chip_diag = qla2x00_chip_diag,
1917 .config_rings = qla2x00_config_rings,
1918 .reset_adapter = qla2x00_reset_adapter,
1919 .nvram_config = qla2x00_nvram_config,
1920 .update_fw_options = qla2x00_update_fw_options,
1921 .load_risc = qla2x00_load_risc,
1922 .pci_info_str = qla2x00_pci_info_str,
1923 .fw_version_str = qla2x00_fw_version_str,
1924 .intr_handler = qla2100_intr_handler,
1925 .enable_intrs = qla2x00_enable_intrs,
1926 .disable_intrs = qla2x00_disable_intrs,
1927 .abort_command = qla2x00_abort_command,
523ec773
AV		 1928 .target_reset = qla2x00_abort_target,
1929 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1930 .fabric_login = qla2x00_login_fabric,
1931 .fabric_logout = qla2x00_fabric_logout,
1932 .calc_req_entries = qla2x00_calc_iocbs_32,
1933 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1934 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1935 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1936 .read_nvram = qla2x00_read_nvram_data,
1937 .write_nvram = qla2x00_write_nvram_data,
1938 .fw_dump = qla2100_fw_dump,
1939 .beacon_on = NULL,
1940 .beacon_off = NULL,
1941 .beacon_blink = NULL,
1942 .read_optrom = qla2x00_read_optrom_data,
1943 .write_optrom = qla2x00_write_optrom_data,
1944 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1945 .start_scsi = qla2x00_start_scsi,
d7459527 1946 .start_scsi_mq = NULL,
a9083016 1947 .abort_isp = qla2x00_abort_isp,
706f457d 1948 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1949 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1950};
1951
1952static struct isp_operations qla2300_isp_ops = {
1953 .pci_config = qla2300_pci_config,
1954 .reset_chip = qla2x00_reset_chip,
1955 .chip_diag = qla2x00_chip_diag,
1956 .config_rings = qla2x00_config_rings,
1957 .reset_adapter = qla2x00_reset_adapter,
1958 .nvram_config = qla2x00_nvram_config,
1959 .update_fw_options = qla2x00_update_fw_options,
1960 .load_risc = qla2x00_load_risc,
1961 .pci_info_str = qla2x00_pci_info_str,
1962 .fw_version_str = qla2x00_fw_version_str,
1963 .intr_handler = qla2300_intr_handler,
1964 .enable_intrs = qla2x00_enable_intrs,
1965 .disable_intrs = qla2x00_disable_intrs,
1966 .abort_command = qla2x00_abort_command,
523ec773
AV		 1967 .target_reset = qla2x00_abort_target,
1968 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1969 .fabric_login = qla2x00_login_fabric,
1970 .fabric_logout = qla2x00_fabric_logout,
1971 .calc_req_entries = qla2x00_calc_iocbs_32,
1972 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1973 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1974 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1975 .read_nvram = qla2x00_read_nvram_data,
1976 .write_nvram = qla2x00_write_nvram_data,
1977 .fw_dump = qla2300_fw_dump,
1978 .beacon_on = qla2x00_beacon_on,
1979 .beacon_off = qla2x00_beacon_off,
1980 .beacon_blink = qla2x00_beacon_blink,
1981 .read_optrom = qla2x00_read_optrom_data,
1982 .write_optrom = qla2x00_write_optrom_data,
1983 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1984 .start_scsi = qla2x00_start_scsi,
d7459527 1985 .start_scsi_mq = NULL,
a9083016 1986 .abort_isp = qla2x00_abort_isp,
7ec0effd 1987 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1988 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1989};
1990
1991static struct isp_operations qla24xx_isp_ops = {
1992 .pci_config = qla24xx_pci_config,
1993 .reset_chip = qla24xx_reset_chip,
1994 .chip_diag = qla24xx_chip_diag,
1995 .config_rings = qla24xx_config_rings,
1996 .reset_adapter = qla24xx_reset_adapter,
1997 .nvram_config = qla24xx_nvram_config,
1998 .update_fw_options = qla24xx_update_fw_options,
1999 .load_risc = qla24xx_load_risc,
2000 .pci_info_str = qla24xx_pci_info_str,
2001 .fw_version_str = qla24xx_fw_version_str,
2002 .intr_handler = qla24xx_intr_handler,
2003 .enable_intrs = qla24xx_enable_intrs,
2004 .disable_intrs = qla24xx_disable_intrs,
2005 .abort_command = qla24xx_abort_command,
523ec773
AV		 2006 .target_reset = qla24xx_abort_target,
2007 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2008 .fabric_login = qla24xx_login_fabric,
2009 .fabric_logout = qla24xx_fabric_logout,
2010 .calc_req_entries = NULL,
2011 .build_iocbs = NULL,
2012 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2013 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2014 .read_nvram = qla24xx_read_nvram_data,
2015 .write_nvram = qla24xx_write_nvram_data,
2016 .fw_dump = qla24xx_fw_dump,
2017 .beacon_on = qla24xx_beacon_on,
2018 .beacon_off = qla24xx_beacon_off,
2019 .beacon_blink = qla24xx_beacon_blink,
2020 .read_optrom = qla24xx_read_optrom_data,
2021 .write_optrom = qla24xx_write_optrom_data,
2022 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2023 .start_scsi = qla24xx_start_scsi,
d7459527 2024 .start_scsi_mq = NULL,
a9083016 2025 .abort_isp = qla2x00_abort_isp,
7ec0effd 2026 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2027 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2028};
2029
c3a2f0df
AV		 2030static struct isp_operations qla25xx_isp_ops = {
2031 .pci_config = qla25xx_pci_config,
2032 .reset_chip = qla24xx_reset_chip,
2033 .chip_diag = qla24xx_chip_diag,
2034 .config_rings = qla24xx_config_rings,
2035 .reset_adapter = qla24xx_reset_adapter,
2036 .nvram_config = qla24xx_nvram_config,
2037 .update_fw_options = qla24xx_update_fw_options,
2038 .load_risc = qla24xx_load_risc,
2039 .pci_info_str = qla24xx_pci_info_str,
2040 .fw_version_str = qla24xx_fw_version_str,
2041 .intr_handler = qla24xx_intr_handler,
2042 .enable_intrs = qla24xx_enable_intrs,
2043 .disable_intrs = qla24xx_disable_intrs,
2044 .abort_command = qla24xx_abort_command,
523ec773
AV		 2045 .target_reset = qla24xx_abort_target,
2046 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2047 .fabric_login = qla24xx_login_fabric,
2048 .fabric_logout = qla24xx_fabric_logout,
2049 .calc_req_entries = NULL,
2050 .build_iocbs = NULL,
2051 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2052 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2053 .read_nvram = qla25xx_read_nvram_data,
2054 .write_nvram = qla25xx_write_nvram_data,
2055 .fw_dump = qla25xx_fw_dump,
2056 .beacon_on = qla24xx_beacon_on,
2057 .beacon_off = qla24xx_beacon_off,
2058 .beacon_blink = qla24xx_beacon_blink,
338c9161 2059 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2060 .write_optrom = qla24xx_write_optrom_data,
2061 .get_flash_version = qla24xx_get_flash_version,
bad75002 2062 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2063 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2064 .abort_isp = qla2x00_abort_isp,
7ec0effd 2065 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2066 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2067};
2068
3a03eb79
AV		 2069static struct isp_operations qla81xx_isp_ops = {
2070 .pci_config = qla25xx_pci_config,
2071 .reset_chip = qla24xx_reset_chip,
2072 .chip_diag = qla24xx_chip_diag,
2073 .config_rings = qla24xx_config_rings,
2074 .reset_adapter = qla24xx_reset_adapter,
2075 .nvram_config = qla81xx_nvram_config,
2076 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2077 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2078 .pci_info_str = qla24xx_pci_info_str,
2079 .fw_version_str = qla24xx_fw_version_str,
2080 .intr_handler = qla24xx_intr_handler,
2081 .enable_intrs = qla24xx_enable_intrs,
2082 .disable_intrs = qla24xx_disable_intrs,
2083 .abort_command = qla24xx_abort_command,
2084 .target_reset = qla24xx_abort_target,
2085 .lun_reset = qla24xx_lun_reset,
2086 .fabric_login = qla24xx_login_fabric,
2087 .fabric_logout = qla24xx_fabric_logout,
2088 .calc_req_entries = NULL,
2089 .build_iocbs = NULL,
2090 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2091 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2092 .read_nvram = NULL,
2093 .write_nvram = NULL,
3a03eb79
AV		 2094 .fw_dump = qla81xx_fw_dump,
2095 .beacon_on = qla24xx_beacon_on,
2096 .beacon_off = qla24xx_beacon_off,
6246b8a1 2097 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2098 .read_optrom = qla25xx_read_optrom_data,
2099 .write_optrom = qla24xx_write_optrom_data,
2100 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2101 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2102 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2103 .abort_isp = qla2x00_abort_isp,
7ec0effd 2104 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2105 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2106};
2107
2108static struct isp_operations qla82xx_isp_ops = {
2109 .pci_config = qla82xx_pci_config,
2110 .reset_chip = qla82xx_reset_chip,
2111 .chip_diag = qla24xx_chip_diag,
2112 .config_rings = qla82xx_config_rings,
2113 .reset_adapter = qla24xx_reset_adapter,
2114 .nvram_config = qla81xx_nvram_config,
2115 .update_fw_options = qla24xx_update_fw_options,
2116 .load_risc = qla82xx_load_risc,
9d55ca66 2117 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2118 .fw_version_str = qla24xx_fw_version_str,
2119 .intr_handler = qla82xx_intr_handler,
2120 .enable_intrs = qla82xx_enable_intrs,
2121 .disable_intrs = qla82xx_disable_intrs,
2122 .abort_command = qla24xx_abort_command,
2123 .target_reset = qla24xx_abort_target,
2124 .lun_reset = qla24xx_lun_reset,
2125 .fabric_login = qla24xx_login_fabric,
2126 .fabric_logout = qla24xx_fabric_logout,
2127 .calc_req_entries = NULL,
2128 .build_iocbs = NULL,
2129 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2130 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2131 .read_nvram = qla24xx_read_nvram_data,
2132 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2133 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2134 .beacon_on = qla82xx_beacon_on,
2135 .beacon_off = qla82xx_beacon_off,
2136 .beacon_blink = NULL,
a9083016
GM		 2137 .read_optrom = qla82xx_read_optrom_data,
2138 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2139 .get_flash_version = qla82xx_get_flash_version,
a9083016 2140 .start_scsi = qla82xx_start_scsi,
d7459527 2141 .start_scsi_mq = NULL,
a9083016 2142 .abort_isp = qla82xx_abort_isp,
706f457d 2143 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2144 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2145};
2146
7ec0effd
AD		 2147static struct isp_operations qla8044_isp_ops = {
2148 .pci_config = qla82xx_pci_config,
2149 .reset_chip = qla82xx_reset_chip,
2150 .chip_diag = qla24xx_chip_diag,
2151 .config_rings = qla82xx_config_rings,
2152 .reset_adapter = qla24xx_reset_adapter,
2153 .nvram_config = qla81xx_nvram_config,
2154 .update_fw_options = qla24xx_update_fw_options,
2155 .load_risc = qla82xx_load_risc,
2156 .pci_info_str = qla24xx_pci_info_str,
2157 .fw_version_str = qla24xx_fw_version_str,
2158 .intr_handler = qla8044_intr_handler,
2159 .enable_intrs = qla82xx_enable_intrs,
2160 .disable_intrs = qla82xx_disable_intrs,
2161 .abort_command = qla24xx_abort_command,
2162 .target_reset = qla24xx_abort_target,
2163 .lun_reset = qla24xx_lun_reset,
2164 .fabric_login = qla24xx_login_fabric,
2165 .fabric_logout = qla24xx_fabric_logout,
2166 .calc_req_entries = NULL,
2167 .build_iocbs = NULL,
2168 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2169 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2170 .read_nvram = NULL,
2171 .write_nvram = NULL,
a1b23c5a 2172 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2173 .beacon_on = qla82xx_beacon_on,
2174 .beacon_off = qla82xx_beacon_off,
2175 .beacon_blink = NULL,
888e639d 2176 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2177 .write_optrom = qla8044_write_optrom_data,
2178 .get_flash_version = qla82xx_get_flash_version,
2179 .start_scsi = qla82xx_start_scsi,
d7459527 2180 .start_scsi_mq = NULL,
7ec0effd
AD		 2181 .abort_isp = qla8044_abort_isp,
2182 .iospace_config = qla82xx_iospace_config,
2183 .initialize_adapter = qla2x00_initialize_adapter,
2184};
2185
6246b8a1
GM		 2186static struct isp_operations qla83xx_isp_ops = {
2187 .pci_config = qla25xx_pci_config,
2188 .reset_chip = qla24xx_reset_chip,
2189 .chip_diag = qla24xx_chip_diag,
2190 .config_rings = qla24xx_config_rings,
2191 .reset_adapter = qla24xx_reset_adapter,
2192 .nvram_config = qla81xx_nvram_config,
2193 .update_fw_options = qla81xx_update_fw_options,
2194 .load_risc = qla81xx_load_risc,
2195 .pci_info_str = qla24xx_pci_info_str,
2196 .fw_version_str = qla24xx_fw_version_str,
2197 .intr_handler = qla24xx_intr_handler,
2198 .enable_intrs = qla24xx_enable_intrs,
2199 .disable_intrs = qla24xx_disable_intrs,
2200 .abort_command = qla24xx_abort_command,
2201 .target_reset = qla24xx_abort_target,
2202 .lun_reset = qla24xx_lun_reset,
2203 .fabric_login = qla24xx_login_fabric,
2204 .fabric_logout = qla24xx_fabric_logout,
2205 .calc_req_entries = NULL,
2206 .build_iocbs = NULL,
2207 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2208 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2209 .read_nvram = NULL,
2210 .write_nvram = NULL,
2211 .fw_dump = qla83xx_fw_dump,
2212 .beacon_on = qla24xx_beacon_on,
2213 .beacon_off = qla24xx_beacon_off,
2214 .beacon_blink = qla83xx_beacon_blink,
2215 .read_optrom = qla25xx_read_optrom_data,
2216 .write_optrom = qla24xx_write_optrom_data,
2217 .get_flash_version = qla24xx_get_flash_version,
2218 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2219 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2220 .abort_isp = qla2x00_abort_isp,
2221 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2222 .initialize_adapter = qla2x00_initialize_adapter,
2223};
2224
2225static struct isp_operations qlafx00_isp_ops = {
2226 .pci_config = qlafx00_pci_config,
2227 .reset_chip = qlafx00_soft_reset,
2228 .chip_diag = qlafx00_chip_diag,
2229 .config_rings = qlafx00_config_rings,
2230 .reset_adapter = qlafx00_soft_reset,
2231 .nvram_config = NULL,
2232 .update_fw_options = NULL,
2233 .load_risc = NULL,
2234 .pci_info_str = qlafx00_pci_info_str,
2235 .fw_version_str = qlafx00_fw_version_str,
2236 .intr_handler = qlafx00_intr_handler,
2237 .enable_intrs = qlafx00_enable_intrs,
2238 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2239 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2240 .target_reset = qlafx00_abort_target,
2241 .lun_reset = qlafx00_lun_reset,
2242 .fabric_login = NULL,
2243 .fabric_logout = NULL,
2244 .calc_req_entries = NULL,
2245 .build_iocbs = NULL,
2246 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2247 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2248 .read_nvram = qla24xx_read_nvram_data,
2249 .write_nvram = qla24xx_write_nvram_data,
2250 .fw_dump = NULL,
2251 .beacon_on = qla24xx_beacon_on,
2252 .beacon_off = qla24xx_beacon_off,
2253 .beacon_blink = NULL,
2254 .read_optrom = qla24xx_read_optrom_data,
2255 .write_optrom = qla24xx_write_optrom_data,
2256 .get_flash_version = qla24xx_get_flash_version,
2257 .start_scsi = qlafx00_start_scsi,
d7459527 2258 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2259 .abort_isp = qlafx00_abort_isp,
2260 .iospace_config = qlafx00_iospace_config,
2261 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2262};
2263
f73cb695
CD		 2264static struct isp_operations qla27xx_isp_ops = {
2265 .pci_config = qla25xx_pci_config,
2266 .reset_chip = qla24xx_reset_chip,
2267 .chip_diag = qla24xx_chip_diag,
2268 .config_rings = qla24xx_config_rings,
2269 .reset_adapter = qla24xx_reset_adapter,
2270 .nvram_config = qla81xx_nvram_config,
2271 .update_fw_options = qla81xx_update_fw_options,
2272 .load_risc = qla81xx_load_risc,
2273 .pci_info_str = qla24xx_pci_info_str,
2274 .fw_version_str = qla24xx_fw_version_str,
2275 .intr_handler = qla24xx_intr_handler,
2276 .enable_intrs = qla24xx_enable_intrs,
2277 .disable_intrs = qla24xx_disable_intrs,
2278 .abort_command = qla24xx_abort_command,
2279 .target_reset = qla24xx_abort_target,
2280 .lun_reset = qla24xx_lun_reset,
2281 .fabric_login = qla24xx_login_fabric,
2282 .fabric_logout = qla24xx_fabric_logout,
2283 .calc_req_entries = NULL,
2284 .build_iocbs = NULL,
2285 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2286 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2287 .read_nvram = NULL,
2288 .write_nvram = NULL,
2289 .fw_dump = qla27xx_fwdump,
2290 .beacon_on = qla24xx_beacon_on,
2291 .beacon_off = qla24xx_beacon_off,
2292 .beacon_blink = qla83xx_beacon_blink,
2293 .read_optrom = qla25xx_read_optrom_data,
2294 .write_optrom = qla24xx_write_optrom_data,
2295 .get_flash_version = qla24xx_get_flash_version,
2296 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2297 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2298 .abort_isp = qla2x00_abort_isp,
2299 .iospace_config = qla83xx_iospace_config,
2300 .initialize_adapter = qla2x00_initialize_adapter,
2301};
2302
ea5b6382 2303static inline void
e315cd28 2304qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2305{
2306 ha->device_type = DT_EXTENDED_IDS;
2307 switch (ha->pdev->device) {
2308 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2309 ha->isp_type |= DT_ISP2100;
ea5b6382 2310 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2311 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2312 break;
2313 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2314 ha->isp_type |= DT_ISP2200;
ea5b6382 2315 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2316 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2317 break;
2318 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2319 ha->isp_type |= DT_ISP2300;
4a59f71d 2320 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2321 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2322 break;
2323 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2324 ha->isp_type |= DT_ISP2312;
4a59f71d 2325 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2326 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2327 break;
2328 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2329 ha->isp_type |= DT_ISP2322;
4a59f71d 2330 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2331 if (ha->pdev->subsystem_vendor == 0x1028 &&
2332 ha->pdev->subsystem_device == 0x0170)
2333 ha->device_type |= DT_OEM_001;
441d1072 2334 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2335 break;
2336 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2337 ha->isp_type |= DT_ISP6312;
441d1072 2338 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2339 break;
2340 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2341 ha->isp_type |= DT_ISP6322;
441d1072 2342 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2343 break;
2344 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2345 ha->isp_type |= DT_ISP2422;
4a59f71d 2346 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2347 ha->device_type |= DT_FWI2;
c76f2c01 2348 ha->device_type |= DT_IIDMA;
441d1072 2349 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2350 break;
2351 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2352 ha->isp_type |= DT_ISP2432;
4a59f71d 2353 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2354 ha->device_type |= DT_FWI2;
c76f2c01 2355 ha->device_type |= DT_IIDMA;
441d1072 2356 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2357 break;
4d4df193 2358 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2359 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2360 ha->device_type |= DT_ZIO_SUPPORTED;
2361 ha->device_type |= DT_FWI2;
2362 ha->device_type |= DT_IIDMA;
2363 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2364 break;
044cc6c8 2365 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2366 ha->isp_type |= DT_ISP5422;
e428924c 2367 ha->device_type |= DT_FWI2;
441d1072 2368 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2369 break;
044cc6c8 2370 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2371 ha->isp_type |= DT_ISP5432;
e428924c 2372 ha->device_type |= DT_FWI2;
441d1072 2373 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2374 break;
c3a2f0df 2375 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2376 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2377 ha->device_type |= DT_ZIO_SUPPORTED;
2378 ha->device_type |= DT_FWI2;
2379 ha->device_type |= DT_IIDMA;
441d1072 2380 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2381 break;
3a03eb79 2382 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2383 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2384 ha->device_type |= DT_ZIO_SUPPORTED;
2385 ha->device_type |= DT_FWI2;
2386 ha->device_type |= DT_IIDMA;
2387 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2388 break;
a9083016 2389 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2390 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2391 ha->device_type |= DT_ZIO_SUPPORTED;
2392 ha->device_type |= DT_FWI2;
2393 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2394 /* Initialize 82XX ISP flags */
2395 qla82xx_init_flags(ha);
2396 break;
7ec0effd 2397 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2398 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2399 ha->device_type |= DT_ZIO_SUPPORTED;
2400 ha->device_type |= DT_FWI2;
2401 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2402 /* Initialize 82XX ISP flags */
2403 qla82xx_init_flags(ha);
2404 break;
6246b8a1 2405 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2406 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2407 ha->device_type |= DT_ZIO_SUPPORTED;
2408 ha->device_type |= DT_FWI2;
2409 ha->device_type |= DT_IIDMA;
2410 ha->device_type |= DT_T10_PI;
2411 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2412 break;
2413 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2414 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2415 ha->device_type |= DT_ZIO_SUPPORTED;
2416 ha->device_type |= DT_FWI2;
2417 ha->device_type |= DT_IIDMA;
2418 ha->device_type |= DT_T10_PI;
2419 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2420 break;
8ae6d9c7 2421 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2422 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2423 break;
f73cb695 2424 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2425 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2426 ha->device_type |= DT_ZIO_SUPPORTED;
2427 ha->device_type |= DT_FWI2;
2428 ha->device_type |= DT_IIDMA;
8ce3f570 2429 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2430 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2431 break;
2c5bbbb2 2432 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2433 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2434 ha->device_type |= DT_ZIO_SUPPORTED;
2435 ha->device_type |= DT_FWI2;
2436 ha->device_type |= DT_IIDMA;
8ce3f570 2437 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2438 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2439 break;
2b48992f 2440 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2441 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2442 ha->device_type |= DT_ZIO_SUPPORTED;
2443 ha->device_type |= DT_FWI2;
2444 ha->device_type |= DT_IIDMA;
8ce3f570 2445 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2446 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2447 break;
ea5b6382 2448 }
e5b68a61 2449
a9083016 2450 if (IS_QLA82XX(ha))
43a9c38b 2451 ha->port_no = ha->portnum & 1;
f73cb695 2452 else {
a9083016
GM		 2453 /* Get adapter physical port no from interrupt pin register. */
2454 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2455 if (IS_QLA27XX(ha))
2456 ha->port_no--;
2457 else
2458 ha->port_no = !(ha->port_no & 1);
2459 }
a9083016 2460
7c3df132 2461 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2462 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2463 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2464}
2465
1e99e33a
AV		 2466static void
2467qla2xxx_scan_start(struct Scsi_Host *shost)
2468{
e315cd28 2469 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2470
cbc8eb67
AV		 2471 if (vha->hw->flags.running_gold_fw)
2472 return;
2473
e315cd28
AC		 2474 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2475 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2476 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2477 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2478}
2479
2480static int
2481qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2482{
e315cd28 2483 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2484
a5dd506e
BK		 2485 if (test_bit(UNLOADING, &vha->dpc_flags))
2486 return 1;
e315cd28 2487 if (!vha->host)
1e99e33a 2488 return 1;
e315cd28 2489 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2490 return 1;
2491
e315cd28 2492 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2493}
2494
1da177e4
LT		 2495/*
2496 * PCI driver interface
2497 */
6f039790 2498static int
7ee61397 2499qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2500{
a1541d5a 2501 int ret = -ENODEV;
1da177e4 2502 struct Scsi_Host *host;
e315cd28
AC		 2503 scsi_qla_host_t *base_vha = NULL;
2504 struct qla_hw_data *ha;
29856e28 2505 char pci_info[30];
7d613ac6 2506 char fw_str[30], wq_name[30];
5433383e 2507 struct scsi_host_template *sht;
642ef983 2508 int bars, mem_only = 0;
e315cd28 2509 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2510 struct req_que *req = NULL;
2511 struct rsp_que *rsp = NULL;
d7459527 2512
285d0321 2513 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2514 sht = &qla2xxx_driver_template;
5433383e 2515 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2516 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2517 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2518 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2519 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2520 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2521 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2522 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2523 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2524 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2525 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2526 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2527 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2528 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2529 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2530 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2531 mem_only = 1;
7c3df132
SK		 2532 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2533 "Mem only adapter.\n");
285d0321 2534 }
7c3df132
SK		 2535 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2536 "Bars=%d.\n", bars);
285d0321 2537
09483916
BH		 2538 if (mem_only) {
2539 if (pci_enable_device_mem(pdev))
2540 goto probe_out;
2541 } else {
2542 if (pci_enable_device(pdev))
2543 goto probe_out;
2544 }
285d0321 2545
0927678f
JB		 2546 /* This may fail but that's ok */
2547 pci_enable_pcie_error_reporting(pdev);
285d0321 2548
e315cd28
AC		 2549 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2550 if (!ha) {
7c3df132
SK		 2551 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2552 "Unable to allocate memory for ha.\n");
e315cd28 2553 goto probe_out;
1da177e4 2554 }
7c3df132
SK		 2555 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2556 "Memory allocated for ha=%p.\n", ha);
e315cd28 2557 ha->pdev = pdev;
2d70c103 2558 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2559 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2560 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2561 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2562 spin_lock_init(&ha->tgt.atio_lock);
2563
1da177e4
LT		 2564
2565 /* Clear our data area */
285d0321 2566 ha->bars = bars;
09483916 2567 ha->mem_only = mem_only;
df4bf0bb 2568 spin_lock_init(&ha->hardware_lock);
339aa70e 2569 spin_lock_init(&ha->vport_slock);
a9b6f722 2570 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2571 mutex_init(&ha->optrom_mutex);
1da177e4 2572
ea5b6382
AV		 2573 /* Set ISP-type information. */
2574 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2575
2576 /* Set EEH reset type to fundamental if required by hba */
95676112 2577 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2578 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2579 pdev->needs_freset = 1;
ca79cf66 2580
cba1e47f
CD		 2581 ha->prev_topology = 0;
2582 ha->init_cb_size = sizeof(init_cb_t);
2583 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2584 ha->optrom_size = OPTROM_SIZE_2300;
2585
abbd8870 2586 /* Assign ISP specific operations. */
1da177e4 2587 if (IS_QLA2100(ha)) {
642ef983 2588 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2589 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2590 req_length = REQUEST_ENTRY_CNT_2100;
2591 rsp_length = RESPONSE_ENTRY_CNT_2100;
2592 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2593 ha->gid_list_info_size = 4;
3a03eb79
AV		 2594 ha->flash_conf_off = ~0;
2595 ha->flash_data_off = ~0;
2596 ha->nvram_conf_off = ~0;
2597 ha->nvram_data_off = ~0;
fd34f556 2598 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2599 } else if (IS_QLA2200(ha)) {
642ef983 2600 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2601 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2602 req_length = REQUEST_ENTRY_CNT_2200;
2603 rsp_length = RESPONSE_ENTRY_CNT_2100;
2604 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2605 ha->gid_list_info_size = 4;
3a03eb79
AV		 2606 ha->flash_conf_off = ~0;
2607 ha->flash_data_off = ~0;
2608 ha->nvram_conf_off = ~0;
2609 ha->nvram_data_off = ~0;
fd34f556 2610 ha->isp_ops = &qla2100_isp_ops;
fca29703 2611 } else if (IS_QLA23XX(ha)) {
642ef983 2612 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2613 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2614 req_length = REQUEST_ENTRY_CNT_2200;
2615 rsp_length = RESPONSE_ENTRY_CNT_2300;
2616 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2617 ha->gid_list_info_size = 6;
854165f4
AV		 2618 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2619 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2620 ha->flash_conf_off = ~0;
2621 ha->flash_data_off = ~0;
2622 ha->nvram_conf_off = ~0;
2623 ha->nvram_data_off = ~0;
fd34f556 2624 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2625 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2626 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2627 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2628 req_length = REQUEST_ENTRY_CNT_24XX;
2629 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2630 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2631 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2632 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2633 ha->gid_list_info_size = 8;
854165f4 2634 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2635 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2636 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2637 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2638 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2639 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2640 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2641 } else if (IS_QLA25XX(ha)) {
642ef983 2642 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2643 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2644 req_length = REQUEST_ENTRY_CNT_24XX;
2645 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2646 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2647 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2648 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2649 ha->gid_list_info_size = 8;
2650 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2651 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2652 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2653 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2654 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2655 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2656 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2657 } else if (IS_QLA81XX(ha)) {
642ef983 2658 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2659 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2660 req_length = REQUEST_ENTRY_CNT_24XX;
2661 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2662 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2663 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2664 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2665 ha->gid_list_info_size = 8;
2666 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2667 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2668 ha->isp_ops = &qla81xx_isp_ops;
2669 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2670 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2671 ha->nvram_conf_off = ~0;
2672 ha->nvram_data_off = ~0;
a9083016 2673 } else if (IS_QLA82XX(ha)) {
642ef983 2674 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2675 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2676 req_length = REQUEST_ENTRY_CNT_82XX;
2677 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2678 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2679 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2680 ha->gid_list_info_size = 8;
2681 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2682 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2683 ha->isp_ops = &qla82xx_isp_ops;
2684 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2685 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2686 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2687 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2688 } else if (IS_QLA8044(ha)) {
2689 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2690 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2691 req_length = REQUEST_ENTRY_CNT_82XX;
2692 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2693 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2694 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2695 ha->gid_list_info_size = 8;
2696 ha->optrom_size = OPTROM_SIZE_83XX;
2697 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2698 ha->isp_ops = &qla8044_isp_ops;
2699 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2700 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2701 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2702 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2703 } else if (IS_QLA83XX(ha)) {
7d613ac6 2704 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2705 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2706 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2707 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2708 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2709 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2710 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2711 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2712 ha->gid_list_info_size = 8;
2713 ha->optrom_size = OPTROM_SIZE_83XX;
2714 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2715 ha->isp_ops = &qla83xx_isp_ops;
2716 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2717 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2718 ha->nvram_conf_off = ~0;
2719 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2720 } else if (IS_QLAFX00(ha)) {
2721 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2722 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2723 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2724 req_length = REQUEST_ENTRY_CNT_FX00;
2725 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2726 ha->isp_ops = &qlafx00_isp_ops;
2727 ha->port_down_retry_count = 30; /* default value */
2728 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2729 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2730 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2731 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2732 ha->mr.host_info_resend = false;
2733 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2734 } else if (IS_QLA27XX(ha)) {
2735 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2736 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2737 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2738 req_length = REQUEST_ENTRY_CNT_83XX;
2739 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2740 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2741 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2742 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2743 ha->gid_list_info_size = 8;
2744 ha->optrom_size = OPTROM_SIZE_83XX;
2745 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2746 ha->isp_ops = &qla27xx_isp_ops;
2747 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2748 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2749 ha->nvram_conf_off = ~0;
2750 ha->nvram_data_off = ~0;
1da177e4 2751 }
6246b8a1 2752
7c3df132
SK		 2753 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2754 "mbx_count=%d, req_length=%d, "
2755 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2756 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2757 "max_fibre_devices=%d.\n",
7c3df132
SK		 2758 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2759 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2760 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2761 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2762 "isp_ops=%p, flash_conf_off=%d, "
2763 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2764 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2765 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2766
2767 /* Configure PCI I/O space */
2768 ret = ha->isp_ops->iospace_config(ha);
2769 if (ret)
0a63ad12 2770 goto iospace_config_failed;
706f457d
GM		 2771
2772 ql_log_pci(ql_log_info, pdev, 0x001d,
2773 "Found an ISP%04X irq %d iobase 0x%p.\n",
2774 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2775 mutex_init(&ha->vport_lock);
d7459527 2776 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2777 init_completion(&ha->mbx_cmd_comp);
2778 complete(&ha->mbx_cmd_comp);
2779 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2780 init_completion(&ha->dcbx_comp);
f356bef1 2781 init_completion(&ha->lb_portup_comp);
1da177e4 2782
2c3dfe3f 2783 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2784
53303c42 2785 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2786 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2787 "64 Bit addressing is %s.\n",
2788 ha->flags.enable_64bit_addressing ? "enable" :
2789 "disable");
73208dfd 2790 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2791 if (ret) {
7c3df132
SK		 2792 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2793 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2794
e315cd28
AC		 2795 goto probe_hw_failed;
2796 }
2797
73208dfd 2798 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2799 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2800 req->max_q_depth = ql2xmaxqdepth;
2801
e315cd28
AC		 2802
2803 base_vha = qla2x00_create_host(sht, ha);
2804 if (!base_vha) {
a1541d5a 2805 ret = -ENOMEM;
6e9f21f3 2806 qla2x00_mem_free(ha);
2afa19a9
AC		 2807 qla2x00_free_req_que(ha, req);
2808 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2809 goto probe_hw_failed;
1da177e4
LT		 2810 }
2811
e315cd28 2812 pci_set_drvdata(pdev, base_vha);
6b383979 2813 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2814
e315cd28 2815 host = base_vha->host;
2afa19a9 2816 base_vha->req = req;
73208dfd 2817 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2818 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2819 else
e315cd28
AC		 2820 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2821 base_vha->vp_idx;
58548cb5 2822
8ae6d9c7
GM		 2823 /* Setup fcport template structure. */
2824 ha->mr.fcport.vha = base_vha;
2825 ha->mr.fcport.port_type = FCT_UNKNOWN;
2826 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2827 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2828 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2829 ha->mr.fcport.scan_state = 1;
2830
58548cb5
GM		 2831 /* Set the SG table size based on ISP type */
2832 if (!IS_FWI2_CAPABLE(ha)) {
2833 if (IS_QLA2100(ha))
2834 host->sg_tablesize = 32;
2835 } else {
2836 if (!IS_QLA82XX(ha))
2837 host->sg_tablesize = QLA_SG_ALL;
2838 }
642ef983 2839 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2840 host->cmd_per_lun = 3;
2841 host->unique_id = host->host_no;
e02587d7 2842 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2843 host->max_cmd_len = 32;
2844 else
2845 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2846 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2847 /* Older HBAs support only 16-bit LUNs */
2848 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2849 ql2xmaxlun > 0xffff)
2850 host->max_lun = 0xffff;
2851 else
2852 host->max_lun = ql2xmaxlun;
e315cd28 2853 host->transportt = qla2xxx_transport_template;
9a069e19 2854 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2855
7c3df132
SK		 2856 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2857 "max_id=%d this_id=%d "
2858 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2859 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2860 host->this_id, host->cmd_per_lun, host->unique_id,
2861 host->max_cmd_len, host->max_channel, host->max_lun,
2862 host->transportt, sht->vendor_id);
2863
d7459527
MH		 2864 /* Set up the irqs */
2865 ret = qla2x00_request_irqs(ha, rsp);
2866 if (ret)
2867 goto probe_init_failed;
2868
9a347ff4
CD		 2869 /* Alloc arrays of request and response ring ptrs */
2870 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2871 ql_log(ql_log_fatal, base_vha, 0x003d,
2872 "Failed to allocate memory for queue pointers..."
2873 "aborting.\n");
2874 goto probe_init_failed;
2875 }
2876
2d70c103 2877 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2878
90a86fc0
JC		 2879 pci_save_state(pdev);
2880
9a347ff4 2881 /* Assign back pointers */
2afa19a9
AC		 2882 rsp->req = req;
2883 req->rsp = rsp;
9a347ff4 2884
8ae6d9c7
GM		 2885 if (IS_QLAFX00(ha)) {
2886 ha->rsp_q_map[0] = rsp;
2887 ha->req_q_map[0] = req;
2888 set_bit(0, ha->req_qid_map);
2889 set_bit(0, ha->rsp_qid_map);
2890 }
2891
08029990
AV		 2892 /* FWI2-capable only. */
2893 req->req_q_in = &ha->iobase->isp24.req_q_in;
2894 req->req_q_out = &ha->iobase->isp24.req_q_out;
2895 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2896 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2897 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2898 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2899 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2900 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2901 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2902 }
2903
8ae6d9c7
GM		 2904 if (IS_QLAFX00(ha)) {
2905 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2906 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2907 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2908 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2909 }
2910
7ec0effd 2911 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2912 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2913 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2914 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2915 }
2916
7c3df132
SK		 2917 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2918 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2919 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2920 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2921 "req->req_q_in=%p req->req_q_out=%p "
2922 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2923 req->req_q_in, req->req_q_out,
2924 rsp->rsp_q_in, rsp->rsp_q_out);
2925 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2926 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2927 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2928 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2929 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2930 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2931
8ae6d9c7 2932 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2933 ql_log(ql_log_fatal, base_vha, 0x00d6,
2934 "Failed to initialize adapter - Adapter flags %x.\n",
2935 base_vha->device_flags);
1da177e4 2936
a9083016
GM		 2937 if (IS_QLA82XX(ha)) {
2938 qla82xx_idc_lock(ha);
2939 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2940 QLA8XXX_DEV_FAILED);
a9083016 2941 qla82xx_idc_unlock(ha);
7c3df132
SK		 2942 ql_log(ql_log_fatal, base_vha, 0x00d7,
2943 "HW State: FAILED.\n");
7ec0effd
AD		 2944 } else if (IS_QLA8044(ha)) {
2945 qla8044_idc_lock(ha);
2946 qla8044_wr_direct(base_vha,
2947 QLA8044_CRB_DEV_STATE_INDEX,
2948 QLA8XXX_DEV_FAILED);
2949 qla8044_idc_unlock(ha);
2950 ql_log(ql_log_fatal, base_vha, 0x0150,
2951 "HW State: FAILED.\n");
a9083016
GM		 2952 }
2953
a1541d5a 2954 ret = -ENODEV;
1da177e4
LT		 2955 goto probe_failed;
2956 }
2957
3b1bef64
CD		 2958 if (IS_QLAFX00(ha))
2959 host->can_queue = QLAFX00_MAX_CANQUEUE;
2960 else
2961 host->can_queue = req->num_outstanding_cmds - 10;
2962
2963 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2964 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2965 host->can_queue, base_vha->req,
2966 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
2967
d7459527
MH		 2968 if (ha->mqenable)
2969 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c 2970
cbc8eb67
AV		 2971 if (ha->flags.running_gold_fw)
2972 goto skip_dpc;
2973
1da177e4
LT		 2974 /*
2975 * Startup the kernel thread for this host adapter
2976 */
39a11240 2977 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2978 "%s_dpc", base_vha->host_str);
39a11240 2979 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2980 ql_log(ql_log_fatal, base_vha, 0x00ed,
2981 "Failed to start DPC thread.\n");
39a11240 2982 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2983 goto probe_failed;
2984 }
7c3df132
SK		 2985 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2986 "DPC thread started successfully.\n");
1da177e4 2987
2d70c103
NB		 2988 /*
2989 * If we're not coming up in initiator mode, we might sit for
2990 * a while without waking up the dpc thread, which leads to a
2991 * stuck process warning. So just kick the dpc once here and
2992 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2993 */
2994 qla2xxx_wake_dpc(base_vha);
2995
f3ddac19
CD		 2996 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
2997
81178772
SK		 2998 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2999 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3000 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3001 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3002
3003 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3004 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3005 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3006 INIT_WORK(&ha->idc_state_handler,
3007 qla83xx_idc_state_handler_work);
3008 INIT_WORK(&ha->nic_core_unrecoverable,
3009 qla83xx_nic_core_unrecoverable_work);
3010 }
3011
cbc8eb67 3012skip_dpc:
e315cd28
AC		 3013 list_add_tail(&base_vha->list, &ha->vp_list);
3014 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3015
3016 /* Initialized the timer */
e315cd28 3017 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3018 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3019 "Started qla2x00_timer with "
3020 "interval=%d.\n", WATCH_INTERVAL);
3021 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3022 "Detected hba at address=%p.\n",
3023 ha);
d19044c3 3024
e02587d7 3025 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3026 if (ha->fw_attributes & BIT_4) {
9e522cd8 3027 int prot = 0, guard;
bad75002 3028 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3029 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3030 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3031 if (ql2xenabledif == 1)
3032 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3033 scsi_host_set_prot(host,
8cb2049c 3034 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3035 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3036 | SHOST_DIF_TYPE3_PROTECTION
3037 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3038 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3039 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3040
3041 guard = SHOST_DIX_GUARD_CRC;
3042
3043 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3044 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3045 guard |= SHOST_DIX_GUARD_IP;
3046
3047 scsi_host_set_guard(host, guard);
bad75002
AE		 3048 } else
3049 base_vha->flags.difdix_supported = 0;
3050 }
3051
a9083016
GM		 3052 ha->isp_ops->enable_intrs(ha);
3053
1fe19ee4
AB		 3054 if (IS_QLAFX00(ha)) {
3055 ret = qlafx00_fx_disc(base_vha,
3056 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3057 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3058 QLA_SG_ALL : 128;
3059 }
3060
a1541d5a
AV		 3061 ret = scsi_add_host(host, &pdev->dev);
3062 if (ret)
3063 goto probe_failed;
3064
1486400f
MR		 3065 base_vha->flags.init_done = 1;
3066 base_vha->flags.online = 1;
edaa5c74 3067 ha->prev_minidump_failed = 0;
1486400f 3068
7c3df132
SK		 3069 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3070 "Init done and hba is online.\n");
3071
2d70c103
NB		 3072 if (qla_ini_mode_enabled(base_vha))
3073 scsi_scan_host(host);
3074 else
3075 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3076 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3077
e315cd28 3078 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3079
8ae6d9c7 3080 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3081 ret = qlafx00_fx_disc(base_vha,
3082 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3083
3084 /* Register system information */
3085 ret = qlafx00_fx_disc(base_vha,
3086 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3087 }
3088
e315cd28 3089 qla2x00_init_host_attr(base_vha);
a1541d5a 3090
e315cd28 3091 qla2x00_dfs_setup(base_vha);
df613b96 3092
03eb912a
AB		 3093 ql_log(ql_log_info, base_vha, 0x00fb,
3094 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3095 ql_log(ql_log_info, base_vha, 0x00fc,
3096 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3097 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3098 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3099 base_vha->host_no,
df57caba 3100 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3101
2d70c103
NB		 3102 qlt_add_target(ha, base_vha);
3103
6b383979 3104 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3105
3106 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3107 return -ENODEV;
3108
1da177e4
LT		 3109 return 0;
3110
6e9f21f3 3111probe_init_failed:
2afa19a9 3112 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3113 ha->req_q_map[0] = NULL;
3114 clear_bit(0, ha->req_qid_map);
2afa19a9 3115 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3116 ha->rsp_q_map[0] = NULL;
3117 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3118 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3119
1da177e4 3120probe_failed:
b9978769
AV		 3121 if (base_vha->timer_active)
3122 qla2x00_stop_timer(base_vha);
3123 base_vha->flags.online = 0;
3124 if (ha->dpc_thread) {
3125 struct task_struct *t = ha->dpc_thread;
3126
3127 ha->dpc_thread = NULL;
3128 kthread_stop(t);
3129 }
3130
e315cd28 3131 qla2x00_free_device(base_vha);
1da177e4 3132
e315cd28 3133 scsi_host_put(base_vha->host);
1da177e4 3134
e315cd28 3135probe_hw_failed:
1a2fbf18
JL		 3136 qla2x00_clear_drv_active(ha);
3137
0a63ad12 3138iospace_config_failed:
7ec0effd 3139 if (IS_P3P_TYPE(ha)) {
0a63ad12 3140 if (!ha->nx_pcibase)
f73cb695 3141 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3142 if (!ql2xdbwr)
f73cb695 3143 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3144 } else {
3145 if (ha->iobase)
3146 iounmap(ha->iobase);
8ae6d9c7
GM		 3147 if (ha->cregbase)
3148 iounmap(ha->cregbase);
a9083016 3149 }
e315cd28
AC		 3150 pci_release_selected_regions(ha->pdev, ha->bars);
3151 kfree(ha);
3152 ha = NULL;
1da177e4 3153
a1541d5a 3154probe_out:
e315cd28 3155 pci_disable_device(pdev);
a1541d5a 3156 return ret;
1da177e4 3157}
1da177e4 3158
e30d1756
MI		 3159static void
3160qla2x00_shutdown(struct pci_dev *pdev)
3161{
3162 scsi_qla_host_t *vha;
3163 struct qla_hw_data *ha;
3164
552f3f9a
MI		 3165 if (!atomic_read(&pdev->enable_cnt))
3166 return;
3167
e30d1756
MI		 3168 vha = pci_get_drvdata(pdev);
3169 ha = vha->hw;
3170
42479343
AB		 3171 /* Notify ISPFX00 firmware */
3172 if (IS_QLAFX00(ha))
3173 qlafx00_driver_shutdown(vha, 20);
3174
e30d1756
MI		 3175 /* Turn-off FCE trace */
3176 if (ha->flags.fce_enabled) {
3177 qla2x00_disable_fce_trace(vha, NULL, NULL);
3178 ha->flags.fce_enabled = 0;
3179 }
3180
3181 /* Turn-off EFT trace */
3182 if (ha->eft)
3183 qla2x00_disable_eft_trace(vha);
3184
3185 /* Stop currently executing firmware. */
3186 qla2x00_try_to_stop_firmware(vha);
3187
3188 /* Turn adapter off line */
3189 vha->flags.online = 0;
3190
3191 /* turn-off interrupts on the card */
3192 if (ha->interrupts_on) {
3193 vha->flags.init_done = 0;
3194 ha->isp_ops->disable_intrs(ha);
3195 }
3196
3197 qla2x00_free_irqs(vha);
3198
3199 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3200
3201 pci_disable_pcie_error_reporting(pdev);
3202 pci_disable_device(pdev);
e30d1756
MI		 3203}
3204
fe1b806f 3205/* Deletes all the virtual ports for a given ha */
4c993f76 3206static void
fe1b806f 3207qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3208{
fe1b806f 3209 scsi_qla_host_t *vha;
feafb7b1 3210 unsigned long flags;
e315cd28 3211
43ebf16d
AE		 3212 mutex_lock(&ha->vport_lock);
3213 while (ha->cur_vport_count) {
43ebf16d 3214 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3215
43ebf16d
AE		 3216 BUG_ON(base_vha->list.next == &ha->vp_list);
3217 /* This assumes first entry in ha->vp_list is always base vha */
3218 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3219 scsi_host_get(vha->host);
feafb7b1 3220
43ebf16d
AE		 3221 spin_unlock_irqrestore(&ha->vport_slock, flags);
3222 mutex_unlock(&ha->vport_lock);
3223
3224 fc_vport_terminate(vha->fc_vport);
3225 scsi_host_put(vha->host);
feafb7b1 3226
43ebf16d 3227 mutex_lock(&ha->vport_lock);
e315cd28 3228 }
43ebf16d 3229 mutex_unlock(&ha->vport_lock);
fe1b806f 3230}
1da177e4 3231
fe1b806f
CD		 3232/* Stops all deferred work threads */
3233static void
3234qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3235{
68ca949c
AC		 3236 /* Flush the work queue and remove it */
3237 if (ha->wq) {
3238 flush_workqueue(ha->wq);
3239 destroy_workqueue(ha->wq);
3240 ha->wq = NULL;
3241 }
3242
7d613ac6
SV		 3243 /* Cancel all work and destroy DPC workqueues */
3244 if (ha->dpc_lp_wq) {
3245 cancel_work_sync(&ha->idc_aen);
3246 destroy_workqueue(ha->dpc_lp_wq);
3247 ha->dpc_lp_wq = NULL;
3248 }
3249
3250 if (ha->dpc_hp_wq) {
3251 cancel_work_sync(&ha->nic_core_reset);
3252 cancel_work_sync(&ha->idc_state_handler);
3253 cancel_work_sync(&ha->nic_core_unrecoverable);
3254 destroy_workqueue(ha->dpc_hp_wq);
3255 ha->dpc_hp_wq = NULL;
3256 }
3257
b9978769
AV		 3258 /* Kill the kernel thread for this host */
3259 if (ha->dpc_thread) {
3260 struct task_struct *t = ha->dpc_thread;
3261
3262 /*
3263 * qla2xxx_wake_dpc checks for ->dpc_thread
3264 * so we need to zero it out.
3265 */
3266 ha->dpc_thread = NULL;
3267 kthread_stop(t);
3268 }
fe1b806f 3269}
1da177e4 3270
fe1b806f
CD		 3271static void
3272qla2x00_unmap_iobases(struct qla_hw_data *ha)
3273{
a9083016 3274 if (IS_QLA82XX(ha)) {
b963752f 3275
f73cb695 3276 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3277 if (!ql2xdbwr)
f73cb695 3278 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3279 } else {
3280 if (ha->iobase)
3281 iounmap(ha->iobase);
1da177e4 3282
8ae6d9c7
GM		 3283 if (ha->cregbase)
3284 iounmap(ha->cregbase);
3285
a9083016
GM		 3286 if (ha->mqiobase)
3287 iounmap(ha->mqiobase);
6246b8a1 3288
f73cb695 3289 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3290 iounmap(ha->msixbase);
a9083016 3291 }
fe1b806f
CD		 3292}
3293
3294static void
db7157d4 3295qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3296{
fe1b806f
CD		 3297 if (IS_QLA8044(ha)) {
3298 qla8044_idc_lock(ha);
c41afc9a 3299 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3300 qla8044_idc_unlock(ha);
3301 } else if (IS_QLA82XX(ha)) {
3302 qla82xx_idc_lock(ha);
3303 qla82xx_clear_drv_active(ha);
3304 qla82xx_idc_unlock(ha);
3305 }
3306}
3307
3308static void
3309qla2x00_remove_one(struct pci_dev *pdev)
3310{
3311 scsi_qla_host_t *base_vha;
3312 struct qla_hw_data *ha;
3313
beb9e315
JL		 3314 base_vha = pci_get_drvdata(pdev);
3315 ha = base_vha->hw;
3316
3317 /* Indicate device removal to prevent future board_disable and wait
3318 * until any pending board_disable has completed. */
3319 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3320 cancel_work_sync(&ha->board_disable);
3321
fe1b806f 3322 /*
beb9e315
JL		 3323 * If the PCI device is disabled then there was a PCI-disconnect and
3324 * qla2x00_disable_board_on_pci_error has taken care of most of the
3325 * resources.
fe1b806f 3326 */
beb9e315
JL		 3327 if (!atomic_read(&pdev->enable_cnt)) {
3328 scsi_host_put(base_vha->host);
3329 kfree(ha);
3330 pci_set_drvdata(pdev, NULL);
fe1b806f 3331 return;
beb9e315 3332 }
fe1b806f 3333
638a1a01
SC		 3334 qla2x00_wait_for_hba_ready(base_vha);
3335
783e0dc4
SC		 3336 /* if UNLOAD flag is already set, then continue unload,
3337 * where it was set first.
3338 */
3339 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3340 return;
3341
fe1b806f
CD		 3342 set_bit(UNLOADING, &base_vha->dpc_flags);
3343
3344 if (IS_QLAFX00(ha))
3345 qlafx00_driver_shutdown(base_vha, 20);
3346
3347 qla2x00_delete_all_vps(ha, base_vha);
3348
3349 if (IS_QLA8031(ha)) {
3350 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3351 "Clearing fcoe driver presence.\n");
3352 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3353 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3354 "Error while clearing DRV-Presence.\n");
3355 }
3356
3357 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3358
3359 qla2x00_dfs_remove(base_vha);
3360
3361 qla84xx_put_chip(base_vha);
3362
2d5a4c34
HM		 3363 /* Laser should be disabled only for ISP2031 */
3364 if (IS_QLA2031(ha))
3365 qla83xx_disable_laser(base_vha);
3366
fe1b806f
CD		 3367 /* Disable timer */
3368 if (base_vha->timer_active)
3369 qla2x00_stop_timer(base_vha);
3370
3371 base_vha->flags.online = 0;
3372
b0d6cabd
HM		 3373 /* free DMA memory */
3374 if (ha->exlogin_buf)
3375 qla2x00_free_exlogin_buffer(ha);
3376
2f56a7f1
HM		 3377 /* free DMA memory */
3378 if (ha->exchoffld_buf)
3379 qla2x00_free_exchoffld_buffer(ha);
3380
fe1b806f
CD		 3381 qla2x00_destroy_deferred_work(ha);
3382
3383 qlt_remove_target(ha, base_vha);
3384
3385 qla2x00_free_sysfs_attr(base_vha, true);
3386
3387 fc_remove_host(base_vha->host);
3388
3389 scsi_remove_host(base_vha->host);
3390
3391 qla2x00_free_device(base_vha);
3392
db7157d4 3393 qla2x00_clear_drv_active(ha);
fe1b806f 3394
d2749ffa
AE		 3395 scsi_host_put(base_vha->host);
3396
fe1b806f 3397 qla2x00_unmap_iobases(ha);
73208dfd 3398
e315cd28
AC		 3399 pci_release_selected_regions(ha->pdev, ha->bars);
3400 kfree(ha);
3401 ha = NULL;
1da177e4 3402
90a86fc0
JC		 3403 pci_disable_pcie_error_reporting(pdev);
3404
665db93b 3405 pci_disable_device(pdev);
1da177e4 3406}
1da177e4
LT		 3407
3408static void
e315cd28 3409qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3410{
e315cd28 3411 struct qla_hw_data *ha = vha->hw;
1da177e4 3412
85880801
AV		 3413 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3414
3415 /* Disable timer */
3416 if (vha->timer_active)
3417 qla2x00_stop_timer(vha);
3418
2afa19a9 3419 qla25xx_delete_queues(vha);
fe1b806f 3420
df613b96 3421 if (ha->flags.fce_enabled)
e315cd28 3422 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3423
a7a167bf 3424 if (ha->eft)
e315cd28 3425 qla2x00_disable_eft_trace(vha);
a7a167bf 3426
f6ef3b18 3427 /* Stop currently executing firmware. */
e315cd28 3428 qla2x00_try_to_stop_firmware(vha);
1da177e4 3429
85880801
AV		 3430 vha->flags.online = 0;
3431
f6ef3b18 3432 /* turn-off interrupts on the card */
a9083016
GM		 3433 if (ha->interrupts_on) {
3434 vha->flags.init_done = 0;
fd34f556 3435 ha->isp_ops->disable_intrs(ha);
a9083016 3436 }
f6ef3b18 3437
e315cd28 3438 qla2x00_free_irqs(vha);
1da177e4 3439
8867048b
CD		 3440 qla2x00_free_fcports(vha);
3441
e315cd28 3442 qla2x00_mem_free(ha);
73208dfd 3443
08de2844
GM		 3444 qla82xx_md_free(vha);
3445
73208dfd 3446 qla2x00_free_queues(ha);
1da177e4
LT		 3447}
3448
8867048b
CD		 3449void qla2x00_free_fcports(struct scsi_qla_host *vha)
3450{
3451 fc_port_t *fcport, *tfcport;
3452
3453 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3454 list_del(&fcport->list);
5f16b331 3455 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3456 kfree(fcport);
3457 fcport = NULL;
3458 }
3459}
3460
d97994dc 3461static inline void
e315cd28 3462qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3463 int defer)
3464{
d97994dc 3465 struct fc_rport *rport;
67becc00 3466 scsi_qla_host_t *base_vha;
044d78e1 3467 unsigned long flags;
d97994dc
AV		 3468
3469 if (!fcport->rport)
3470 return;
3471
3472 rport = fcport->rport;
3473 if (defer) {
67becc00 3474 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3475 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3476 fcport->drport = rport;
044d78e1 3477 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3478 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3479 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3480 qla2xxx_wake_dpc(base_vha);
2d70c103 3481 } else {
df673274 3482 int now;
d20ed91b
AP		 3483 if (rport)
3484 fc_remote_port_delete(rport);
df673274
AP		 3485 qlt_do_generation_tick(vha, &now);
3486 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3487 }
d97994dc
AV		 3488}
3489
1da177e4
LT		 3490/*
3491 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3492 *
3493 * Input: ha = adapter block pointer. fcport = port structure pointer.
3494 *
3495 * Return: None.
3496 *
3497 * Context:
3498 */
e315cd28 3499void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3500 int do_login, int defer)
1da177e4 3501{
8ae6d9c7
GM		 3502 if (IS_QLAFX00(vha->hw)) {
3503 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3504 qla2x00_schedule_rport_del(vha, fcport, defer);
3505 return;
3506 }
3507
2c3dfe3f 3508 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3509 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3510 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3511 qla2x00_schedule_rport_del(vha, fcport, defer);
3512 }
fa2a1ce5 3513 /*
1da177e4
LT		 3514 * We may need to retry the login, so don't change the state of the
3515 * port but do the retries.
3516 */
3517 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3518 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3519
3520 if (!do_login)
3521 return;
3522
a1d0285e
AE		 3523 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3524
1da177e4 3525 if (fcport->login_retry == 0) {
e315cd28 3526 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3527
7c3df132 3528 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3529 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3530 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3531 }
3532}
3533
3534/*
3535 * qla2x00_mark_all_devices_lost
3536 * Updates fcport state when device goes offline.
3537 *
3538 * Input:
3539 * ha = adapter block pointer.
3540 * fcport = port structure pointer.
3541 *
3542 * Return:
3543 * None.
3544 *
3545 * Context:
3546 */
3547void
e315cd28 3548qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3549{
3550 fc_port_t *fcport;
3551
e315cd28 3552 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3553 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3554 continue;
0d6e61bc 3555
1da177e4
LT		 3556 /*
3557 * No point in marking the device as lost, if the device is
3558 * already DEAD.
3559 */
3560 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3561 continue;
e315cd28 3562 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3563 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3564 if (defer)
3565 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3566 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3567 qla2x00_schedule_rport_del(vha, fcport, defer);
3568 }
1da177e4
LT		 3569 }
3570}
3571
3572/*
3573* qla2x00_mem_alloc
3574* Allocates adapter memory.
3575*
3576* Returns:
3577* 0 = success.
e8711085 3578* !0 = failure.
1da177e4 3579*/
e8711085 3580static int
73208dfd
AC		 3581qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3582 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3583{
3584 char name[16];
1da177e4 3585
e8711085 3586 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3587 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3588 if (!ha->init_cb)
e315cd28 3589 goto fail;
e8711085 3590
2d70c103
NB		 3591 if (qlt_mem_alloc(ha) < 0)
3592 goto fail_free_init_cb;
3593
642ef983
CD		 3594 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3595 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3596 if (!ha->gid_list)
2d70c103 3597 goto fail_free_tgt_mem;
1da177e4 3598
e8711085
AV		 3599 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3600 if (!ha->srb_mempool)
e315cd28 3601 goto fail_free_gid_list;
e8711085 3602
7ec0effd 3603 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3604 /* Allocate cache for CT6 Ctx. */
3605 if (!ctx_cachep) {
3606 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3607 sizeof(struct ct6_dsd), 0,
3608 SLAB_HWCACHE_ALIGN, NULL);
3609 if (!ctx_cachep)
3610 goto fail_free_gid_list;
3611 }
3612 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3613 ctx_cachep);
3614 if (!ha->ctx_mempool)
3615 goto fail_free_srb_mempool;
7c3df132
SK		 3616 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3617 "ctx_cachep=%p ctx_mempool=%p.\n",
3618 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3619 }
3620
e8711085
AV		 3621 /* Get memory for cached NVRAM */
3622 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3623 if (!ha->nvram)
a9083016 3624 goto fail_free_ctx_mempool;
e8711085 3625
e315cd28
AC		 3626 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3627 ha->pdev->device);
3628 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3629 DMA_POOL_SIZE, 8, 0);
3630 if (!ha->s_dma_pool)
3631 goto fail_free_nvram;
3632
7c3df132
SK		 3633 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3634 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3635 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3636
7ec0effd 3637 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3638 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3639 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3640 if (!ha->dl_dma_pool) {
7c3df132
SK		 3641 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3642 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3643 goto fail_s_dma_pool;
3644 }
3645
3646 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3647 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3648 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3649 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3650 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3651 goto fail_dl_dma_pool;
3652 }
7c3df132
SK		 3653 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3654 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3655 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3656 }
3657
e8711085
AV		 3658 /* Allocate memory for SNS commands */
3659 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3660 /* Get consistent memory allocated for SNS commands */
e8711085 3661 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3662 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3663 if (!ha->sns_cmd)
e315cd28 3664 goto fail_dma_pool;
7c3df132 3665 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3666 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3667 } else {
e315cd28 3668 /* Get consistent memory allocated for MS IOCB */
e8711085 3669 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3670 &ha->ms_iocb_dma);
e8711085 3671 if (!ha->ms_iocb)
e315cd28
AC		 3672 goto fail_dma_pool;
3673 /* Get consistent memory allocated for CT SNS commands */
e8711085 3674 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3675 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3676 if (!ha->ct_sns)
3677 goto fail_free_ms_iocb;
7c3df132
SK		 3678 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3679 "ms_iocb=%p ct_sns=%p.\n",
3680 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3681 }
3682
e315cd28 3683 /* Allocate memory for request ring */
73208dfd
AC		 3684 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3685 if (!*req) {
7c3df132
SK		 3686 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3687 "Failed to allocate memory for req.\n");
e315cd28
AC		 3688 goto fail_req;
3689 }
73208dfd
AC		 3690 (*req)->length = req_len;
3691 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3692 ((*req)->length + 1) * sizeof(request_t),
3693 &(*req)->dma, GFP_KERNEL);
3694 if (!(*req)->ring) {
7c3df132
SK		 3695 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3696 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3697 goto fail_req_ring;
3698 }
3699 /* Allocate memory for response ring */
73208dfd
AC		 3700 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3701 if (!*rsp) {
7c3df132
SK		 3702 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3703 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3704 goto fail_rsp;
3705 }
73208dfd
AC		 3706 (*rsp)->hw = ha;
3707 (*rsp)->length = rsp_len;
3708 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3709 ((*rsp)->length + 1) * sizeof(response_t),
3710 &(*rsp)->dma, GFP_KERNEL);
3711 if (!(*rsp)->ring) {
7c3df132
SK		 3712 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3713 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3714 goto fail_rsp_ring;
3715 }
73208dfd
AC		 3716 (*req)->rsp = *rsp;
3717 (*rsp)->req = *req;
7c3df132
SK		 3718 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3719 "req=%p req->length=%d req->ring=%p rsp=%p "
3720 "rsp->length=%d rsp->ring=%p.\n",
3721 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3722 (*rsp)->ring);
73208dfd
AC		 3723 /* Allocate memory for NVRAM data for vports */
3724 if (ha->nvram_npiv_size) {
3725 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3726 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3727 if (!ha->npiv_info) {
7c3df132
SK		 3728 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3729 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3730 goto fail_npiv_info;
3731 }
3732 } else
3733 ha->npiv_info = NULL;
e8711085 3734
b64b0e8f 3735 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3736 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3737 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3738 &ha->ex_init_cb_dma);
3739 if (!ha->ex_init_cb)
3740 goto fail_ex_init_cb;
7c3df132
SK		 3741 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3742 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3743 }
3744
a9083016
GM		 3745 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3746
5ff1d584
AV		 3747 /* Get consistent memory allocated for Async Port-Database. */
3748 if (!IS_FWI2_CAPABLE(ha)) {
3749 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3750 &ha->async_pd_dma);
3751 if (!ha->async_pd)
3752 goto fail_async_pd;
7c3df132
SK		 3753 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3754 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3755 }
3756
e315cd28 3757 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3758
3759 /* Allocate memory for our loop_id bitmap */
3760 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3761 GFP_KERNEL);
3762 if (!ha->loop_id_map)
3763 goto fail_async_pd;
3764 else {
3765 qla2x00_set_reserved_loop_ids(ha);
3766 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3767 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3768 }
3769
b2a72ec3 3770 return 0;
e315cd28 3771
5ff1d584
AV		 3772fail_async_pd:
3773 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3774fail_ex_init_cb:
3775 kfree(ha->npiv_info);
73208dfd
AC		 3776fail_npiv_info:
3777 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3778 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3779 (*rsp)->ring = NULL;
3780 (*rsp)->dma = 0;
e315cd28 3781fail_rsp_ring:
73208dfd 3782 kfree(*rsp);
e315cd28 3783fail_rsp:
73208dfd
AC		 3784 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3785 sizeof(request_t), (*req)->ring, (*req)->dma);
3786 (*req)->ring = NULL;
3787 (*req)->dma = 0;
e315cd28 3788fail_req_ring:
73208dfd 3789 kfree(*req);
e315cd28
AC		 3790fail_req:
3791 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3792 ha->ct_sns, ha->ct_sns_dma);
3793 ha->ct_sns = NULL;
3794 ha->ct_sns_dma = 0;
e8711085
AV		 3795fail_free_ms_iocb:
3796 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3797 ha->ms_iocb = NULL;
3798 ha->ms_iocb_dma = 0;
e315cd28 3799fail_dma_pool:
bad75002 3800 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3801 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3802 ha->fcp_cmnd_dma_pool = NULL;
3803 }
3804fail_dl_dma_pool:
bad75002 3805 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3806 dma_pool_destroy(ha->dl_dma_pool);
3807 ha->dl_dma_pool = NULL;
3808 }
3809fail_s_dma_pool:
e315cd28
AC		 3810 dma_pool_destroy(ha->s_dma_pool);
3811 ha->s_dma_pool = NULL;
e8711085
AV		 3812fail_free_nvram:
3813 kfree(ha->nvram);
3814 ha->nvram = NULL;
a9083016
GM		 3815fail_free_ctx_mempool:
3816 mempool_destroy(ha->ctx_mempool);
3817 ha->ctx_mempool = NULL;
e8711085
AV		 3818fail_free_srb_mempool:
3819 mempool_destroy(ha->srb_mempool);
3820 ha->srb_mempool = NULL;
e8711085 3821fail_free_gid_list:
642ef983
CD		 3822 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3823 ha->gid_list,
e315cd28 3824 ha->gid_list_dma);
e8711085
AV		 3825 ha->gid_list = NULL;
3826 ha->gid_list_dma = 0;
2d70c103
NB		 3827fail_free_tgt_mem:
3828 qlt_mem_free(ha);
e315cd28
AC		 3829fail_free_init_cb:
3830 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3831 ha->init_cb_dma);
3832 ha->init_cb = NULL;
3833 ha->init_cb_dma = 0;
e8711085 3834fail:
7c3df132
SK		 3835 ql_log(ql_log_fatal, NULL, 0x0030,
3836 "Memory allocation failure.\n");
e8711085 3837 return -ENOMEM;
1da177e4
LT		 3838}
3839
b0d6cabd
HM		 3840int
3841qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3842{
3843 int rval;
3844 uint16_t size, max_cnt, temp;
3845 struct qla_hw_data *ha = vha->hw;
3846
3847 /* Return if we don't need to alloacate any extended logins */
3848 if (!ql2xexlogins)
3849 return QLA_SUCCESS;
3850
3851 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3852 max_cnt = 0;
3853 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3854 if (rval != QLA_SUCCESS) {
3855 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3856 "Failed to get exlogin status.\n");
3857 return rval;
3858 }
3859
3860 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3861 ha->exlogin_size = (size * temp);
3862 ql_log(ql_log_info, vha, 0xd024,
3863 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3864 max_cnt, size, temp);
3865
3866 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3867 ha->exlogin_size);
3868
3869 /* Get consistent memory for extended logins */
3870 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3871 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3872 if (!ha->exlogin_buf) {
3873 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3874 "Failed to allocate memory for exlogin_buf_dma.\n");
3875 return -ENOMEM;
3876 }
3877
3878 /* Now configure the dma buffer */
3879 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3880 if (rval) {
3881 ql_log(ql_log_fatal, vha, 0x00cf,
3882 "Setup extended login buffer ****FAILED****.\n");
3883 qla2x00_free_exlogin_buffer(ha);
3884 }
3885
3886 return rval;
3887}
3888
3889/*
3890* qla2x00_free_exlogin_buffer
3891*
3892* Input:
3893* ha = adapter block pointer
3894*/
3895void
3896qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3897{
3898 if (ha->exlogin_buf) {
3899 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3900 ha->exlogin_buf, ha->exlogin_buf_dma);
3901 ha->exlogin_buf = NULL;
3902 ha->exlogin_size = 0;
3903 }
3904}
3905
2f56a7f1
HM		 3906int
3907qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3908{
3909 int rval;
3910 uint16_t size, max_cnt, temp;
3911 struct qla_hw_data *ha = vha->hw;
3912
3913 /* Return if we don't need to alloacate any extended logins */
3914 if (!ql2xexchoffld)
3915 return QLA_SUCCESS;
3916
3917 ql_log(ql_log_info, vha, 0xd014,
3918 "Exchange offload count: %d.\n", ql2xexlogins);
3919
3920 max_cnt = 0;
3921 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3922 if (rval != QLA_SUCCESS) {
3923 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3924 "Failed to get exlogin status.\n");
3925 return rval;
3926 }
3927
3928 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3929 ha->exchoffld_size = (size * temp);
3930 ql_log(ql_log_info, vha, 0xd016,
3931 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3932 max_cnt, size, temp);
3933
3934 ql_log(ql_log_info, vha, 0xd017,
3935 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3936
3937 /* Get consistent memory for extended logins */
3938 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3939 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3940 if (!ha->exchoffld_buf) {
3941 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
3942 "Failed to allocate memory for exchoffld_buf_dma.\n");
3943 return -ENOMEM;
3944 }
3945
3946 /* Now configure the dma buffer */
3947 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
3948 if (rval) {
3949 ql_log(ql_log_fatal, vha, 0xd02e,
3950 "Setup exchange offload buffer ****FAILED****.\n");
3951 qla2x00_free_exchoffld_buffer(ha);
3952 }
3953
3954 return rval;
3955}
3956
3957/*
3958* qla2x00_free_exchoffld_buffer
3959*
3960* Input:
3961* ha = adapter block pointer
3962*/
3963void
3964qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
3965{
3966 if (ha->exchoffld_buf) {
3967 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
3968 ha->exchoffld_buf, ha->exchoffld_buf_dma);
3969 ha->exchoffld_buf = NULL;
3970 ha->exchoffld_size = 0;
3971 }
3972}
3973
1da177e4 3974/*
e30d1756
MI		 3975* qla2x00_free_fw_dump
3976* Frees fw dump stuff.
1da177e4
LT		 3977*
3978* Input:
7ec0effd 3979* ha = adapter block pointer
1da177e4 3980*/
a824ebb3 3981static void
e30d1756 3982qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3983{
df613b96 3984 if (ha->fce)
f73cb695
CD		 3985 dma_free_coherent(&ha->pdev->dev,
3986 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 3987
f73cb695
CD		 3988 if (ha->eft)
3989 dma_free_coherent(&ha->pdev->dev,
3990 EFT_SIZE, ha->eft, ha->eft_dma);
3991
3992 if (ha->fw_dump)
a7a167bf 3993 vfree(ha->fw_dump);
f73cb695
CD		 3994 if (ha->fw_dump_template)
3995 vfree(ha->fw_dump_template);
3996
e30d1756
MI		 3997 ha->fce = NULL;
3998 ha->fce_dma = 0;
3999 ha->eft = NULL;
4000 ha->eft_dma = 0;
e30d1756 4001 ha->fw_dumped = 0;
61f098dd 4002 ha->fw_dump_cap_flags = 0;
e30d1756 4003 ha->fw_dump_reading = 0;
f73cb695
CD		 4004 ha->fw_dump = NULL;
4005 ha->fw_dump_len = 0;
4006 ha->fw_dump_template = NULL;
4007 ha->fw_dump_template_len = 0;
e30d1756
MI		 4008}
4009
4010/*
4011* qla2x00_mem_free
4012* Frees all adapter allocated memory.
4013*
4014* Input:
4015* ha = adapter block pointer.
4016*/
4017static void
4018qla2x00_mem_free(struct qla_hw_data *ha)
4019{
4020 qla2x00_free_fw_dump(ha);
4021
81178772
SK		 4022 if (ha->mctp_dump)
4023 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4024 ha->mctp_dump_dma);
4025
e30d1756
MI		 4026 if (ha->srb_mempool)
4027 mempool_destroy(ha->srb_mempool);
a7a167bf 4028
11bbc1d8
AV		 4029 if (ha->dcbx_tlv)
4030 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4031 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4032
ce0423f4
AV		 4033 if (ha->xgmac_data)
4034 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4035 ha->xgmac_data, ha->xgmac_data_dma);
4036
1da177e4
LT		 4037 if (ha->sns_cmd)
4038 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4039 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4040
4041 if (ha->ct_sns)
4042 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4043 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4044
88729e53
AV		 4045 if (ha->sfp_data)
4046 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4047
1da177e4
LT		 4048 if (ha->ms_iocb)
4049 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4050
b64b0e8f 4051 if (ha->ex_init_cb)
a9083016
GM		 4052 dma_pool_free(ha->s_dma_pool,
4053 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4054
5ff1d584
AV		 4055 if (ha->async_pd)
4056 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4057
1da177e4
LT		 4058 if (ha->s_dma_pool)
4059 dma_pool_destroy(ha->s_dma_pool);
4060
1da177e4 4061 if (ha->gid_list)
642ef983
CD		 4062 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4063 ha->gid_list, ha->gid_list_dma);
1da177e4 4064
a9083016
GM		 4065 if (IS_QLA82XX(ha)) {
4066 if (!list_empty(&ha->gbl_dsd_list)) {
4067 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4068
4069 /* clean up allocated prev pool */
4070 list_for_each_entry_safe(dsd_ptr,
4071 tdsd_ptr, &ha->gbl_dsd_list, list) {
4072 dma_pool_free(ha->dl_dma_pool,
4073 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4074 list_del(&dsd_ptr->list);
4075 kfree(dsd_ptr);
4076 }
4077 }
4078 }
4079
4080 if (ha->dl_dma_pool)
4081 dma_pool_destroy(ha->dl_dma_pool);
4082
4083 if (ha->fcp_cmnd_dma_pool)
4084 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4085
4086 if (ha->ctx_mempool)
4087 mempool_destroy(ha->ctx_mempool);
4088
2d70c103
NB		 4089 qlt_mem_free(ha);
4090
e315cd28
AC		 4091 if (ha->init_cb)
4092 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4093 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4094 vfree(ha->optrom_buffer);
4095 kfree(ha->nvram);
73208dfd 4096 kfree(ha->npiv_info);
7a67735b 4097 kfree(ha->swl);
5f16b331 4098 kfree(ha->loop_id_map);
1da177e4 4099
e8711085 4100 ha->srb_mempool = NULL;
a9083016 4101 ha->ctx_mempool = NULL;
1da177e4
LT		 4102 ha->sns_cmd = NULL;
4103 ha->sns_cmd_dma = 0;
4104 ha->ct_sns = NULL;
4105 ha->ct_sns_dma = 0;
4106 ha->ms_iocb = NULL;
4107 ha->ms_iocb_dma = 0;
1da177e4
LT		 4108 ha->init_cb = NULL;
4109 ha->init_cb_dma = 0;
b64b0e8f
AV		 4110 ha->ex_init_cb = NULL;
4111 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4112 ha->async_pd = NULL;
4113 ha->async_pd_dma = 0;
1da177e4
LT		 4114
4115 ha->s_dma_pool = NULL;
a9083016
GM		 4116 ha->dl_dma_pool = NULL;
4117 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4118
1da177e4
LT		 4119 ha->gid_list = NULL;
4120 ha->gid_list_dma = 0;
2d70c103
NB		 4121
4122 ha->tgt.atio_ring = NULL;
4123 ha->tgt.atio_dma = 0;
4124 ha->tgt.tgt_vp_map = NULL;
e315cd28 4125}
1da177e4 4126
e315cd28
AC		 4127struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4128 struct qla_hw_data *ha)
4129{
4130 struct Scsi_Host *host;
4131 struct scsi_qla_host *vha = NULL;
854165f4 4132
e315cd28
AC		 4133 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4134 if (host == NULL) {
7c3df132
SK		 4135 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4136 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 4137 goto fail;
4138 }
4139
4140 /* Clear our data area */
4141 vha = shost_priv(host);
4142 memset(vha, 0, sizeof(scsi_qla_host_t));
4143
4144 vha->host = host;
4145 vha->host_no = host->host_no;
4146 vha->hw = ha;
4147
4148 INIT_LIST_HEAD(&vha->vp_fcports);
4149 INIT_LIST_HEAD(&vha->work_list);
4150 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4151 INIT_LIST_HEAD(&vha->qla_cmd_list);
4152 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4153 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4154 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4155 INIT_LIST_HEAD(&vha->qp_list);
e315cd28 4156
f999f4c1 4157 spin_lock_init(&vha->work_lock);
8b2f5ff3 4158 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 4159
e315cd28 4160 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4161 ql_dbg(ql_dbg_init, vha, 0x0041,
4162 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4163 vha->host, vha->hw, vha,
4164 dev_name(&(ha->pdev->dev)));
4165
e315cd28
AC		 4166 return vha;
4167
4168fail:
4169 return vha;
1da177e4
LT		 4170}
4171
01ef66bb 4172static struct qla_work_evt *
f999f4c1 4173qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4174{
4175 struct qla_work_evt *e;
feafb7b1
AE		 4176 uint8_t bail;
4177
4178 QLA_VHA_MARK_BUSY(vha, bail);
4179 if (bail)
4180 return NULL;
0971de7f 4181
f999f4c1 4182 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4183 if (!e) {
4184 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4185 return NULL;
feafb7b1 4186 }
0971de7f
AV		 4187
4188 INIT_LIST_HEAD(&e->list);
4189 e->type = type;
4190 e->flags = QLA_EVT_FLAG_FREE;
4191 return e;
4192}
4193
01ef66bb 4194static int
f999f4c1 4195qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4196{
f999f4c1 4197 unsigned long flags;
0971de7f 4198
f999f4c1 4199 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4200 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4201 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 4202 qla2xxx_wake_dpc(vha);
f999f4c1 4203
0971de7f
AV		 4204 return QLA_SUCCESS;
4205}
4206
4207int
e315cd28 4208qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4209 u32 data)
4210{
4211 struct qla_work_evt *e;
4212
f999f4c1 4213 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4214 if (!e)
4215 return QLA_FUNCTION_FAILED;
4216
4217 e->u.aen.code = code;
4218 e->u.aen.data = data;
f999f4c1 4219 return qla2x00_post_work(vha, e);
0971de7f
AV		 4220}
4221
8a659571
AV		 4222int
4223qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4224{
4225 struct qla_work_evt *e;
4226
f999f4c1 4227 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4228 if (!e)
4229 return QLA_FUNCTION_FAILED;
4230
4231 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4232 return qla2x00_post_work(vha, e);
8a659571
AV		 4233}
4234
ac280b67
AV		 4235#define qla2x00_post_async_work(name, type) \
4236int qla2x00_post_async_##name##_work( \
4237 struct scsi_qla_host *vha, \
4238 fc_port_t *fcport, uint16_t *data) \
4239{ \
4240 struct qla_work_evt *e; \
4241 \
4242 e = qla2x00_alloc_work(vha, type); \
4243 if (!e) \
4244 return QLA_FUNCTION_FAILED; \
4245 \
4246 e->u.logio.fcport = fcport; \
4247 if (data) { \
4248 e->u.logio.data[0] = data[0]; \
4249 e->u.logio.data[1] = data[1]; \
4250 } \
4251 return qla2x00_post_work(vha, e); \
4252}
4253
4254qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4255qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4256qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4257qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4258qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4259qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4260
3420d36c
AV		 4261int
4262qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4263{
4264 struct qla_work_evt *e;
4265
4266 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4267 if (!e)
4268 return QLA_FUNCTION_FAILED;
4269
4270 e->u.uevent.code = code;
4271 return qla2x00_post_work(vha, e);
4272}
4273
4274static void
4275qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4276{
4277 char event_string[40];
4278 char *envp[] = { event_string, NULL };
4279
4280 switch (code) {
4281 case QLA_UEVENT_CODE_FW_DUMP:
4282 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4283 vha->host_no);
4284 break;
4285 default:
4286 /* do nothing */
4287 break;
4288 }
4289 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4290}
4291
8ae6d9c7
GM		 4292int
4293qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4294 uint32_t *data, int cnt)
4295{
4296 struct qla_work_evt *e;
4297
4298 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4299 if (!e)
4300 return QLA_FUNCTION_FAILED;
4301
4302 e->u.aenfx.evtcode = evtcode;
4303 e->u.aenfx.count = cnt;
4304 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4305 return qla2x00_post_work(vha, e);
4306}
4307
ac280b67 4308void
e315cd28 4309qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4310{
f999f4c1
AV		 4311 struct qla_work_evt *e, *tmp;
4312 unsigned long flags;
4313 LIST_HEAD(work);
0971de7f 4314
f999f4c1
AV		 4315 spin_lock_irqsave(&vha->work_lock, flags);
4316 list_splice_init(&vha->work_list, &work);
4317 spin_unlock_irqrestore(&vha->work_lock, flags);
4318
4319 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4320 list_del_init(&e->list);
0971de7f
AV		 4321
4322 switch (e->type) {
4323 case QLA_EVT_AEN:
e315cd28 4324 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4325 e->u.aen.code, e->u.aen.data);
4326 break;
8a659571
AV		 4327 case QLA_EVT_IDC_ACK:
4328 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4329 break;
ac280b67
AV		 4330 case QLA_EVT_ASYNC_LOGIN:
4331 qla2x00_async_login(vha, e->u.logio.fcport,
4332 e->u.logio.data);
4333 break;
4334 case QLA_EVT_ASYNC_LOGIN_DONE:
4335 qla2x00_async_login_done(vha, e->u.logio.fcport,
4336 e->u.logio.data);
4337 break;
4338 case QLA_EVT_ASYNC_LOGOUT:
4339 qla2x00_async_logout(vha, e->u.logio.fcport);
4340 break;
4341 case QLA_EVT_ASYNC_LOGOUT_DONE:
4342 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4343 e->u.logio.data);
4344 break;
5ff1d584
AV		 4345 case QLA_EVT_ASYNC_ADISC:
4346 qla2x00_async_adisc(vha, e->u.logio.fcport,
4347 e->u.logio.data);
4348 break;
4349 case QLA_EVT_ASYNC_ADISC_DONE:
4350 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4351 e->u.logio.data);
4352 break;
3420d36c
AV		 4353 case QLA_EVT_UEVENT:
4354 qla2x00_uevent_emit(vha, e->u.uevent.code);
4355 break;
8ae6d9c7
GM		 4356 case QLA_EVT_AENFX:
4357 qlafx00_process_aen(vha, e);
4358 break;
0971de7f
AV		 4359 }
4360 if (e->flags & QLA_EVT_FLAG_FREE)
4361 kfree(e);
feafb7b1
AE		 4362
4363 /* For each work completed decrement vha ref count */
4364 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4365 }
e315cd28 4366}
f999f4c1 4367
e315cd28
AC		 4368/* Relogins all the fcports of a vport
4369 * Context: dpc thread
4370 */
4371void qla2x00_relogin(struct scsi_qla_host *vha)
4372{
4373 fc_port_t *fcport;
c6b2fca8 4374 int status;
e315cd28
AC		 4375 uint16_t next_loopid = 0;
4376 struct qla_hw_data *ha = vha->hw;
ac280b67 4377 uint16_t data[2];
e315cd28
AC		 4378
4379 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4380 /*
4381 * If the port is not ONLINE then try to login
4382 * to it if we haven't run out of retries.
4383 */
5ff1d584
AV		 4384 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4385 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4386 fcport->login_retry--;
e315cd28 4387 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4388 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4389 ha->isp_ops->fabric_logout(vha,
4390 fcport->loop_id,
4391 fcport->d_id.b.domain,
4392 fcport->d_id.b.area,
4393 fcport->d_id.b.al_pa);
4394
03bcfb57
JC		 4395 if (fcport->loop_id == FC_NO_LOOP_ID) {
4396 fcport->loop_id = next_loopid =
4397 ha->min_external_loopid;
4398 status = qla2x00_find_new_loop_id(
4399 vha, fcport);
4400 if (status != QLA_SUCCESS) {
4401 /* Ran out of IDs to use */
4402 break;
4403 }
4404 }
4405
ac280b67 4406 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4407 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4408 data[0] = 0;
4409 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4410 status = qla2x00_post_async_login_work(
4411 vha, fcport, data);
4412 if (status == QLA_SUCCESS)
4413 continue;
4414 /* Attempt a retry. */
4415 status = 1;
aaf4d3e2 4416 } else {
ac280b67
AV		 4417 status = qla2x00_fabric_login(vha,
4418 fcport, &next_loopid);
aaf4d3e2
SK		 4419 if (status == QLA_SUCCESS) {
4420 int status2;
4421 uint8_t opts;
4422
4423 opts = 0;
4424 if (fcport->flags &
4425 FCF_FCP2_DEVICE)
4426 opts |= BIT_1;
03003960
SK		 4427 status2 =
4428 qla2x00_get_port_database(
4429 vha, fcport, opts);
aaf4d3e2
SK		 4430 if (status2 != QLA_SUCCESS)
4431 status = 1;
4432 }
4433 }
e315cd28
AC		 4434 } else
4435 status = qla2x00_local_device_login(vha,
4436 fcport);
4437
e315cd28
AC		 4438 if (status == QLA_SUCCESS) {
4439 fcport->old_loop_id = fcport->loop_id;
4440
7c3df132
SK		 4441 ql_dbg(ql_dbg_disc, vha, 0x2003,
4442 "Port login OK: logged in ID 0x%x.\n",
4443 fcport->loop_id);
e315cd28
AC		 4444
4445 qla2x00_update_fcport(vha, fcport);
4446
4447 } else if (status == 1) {
4448 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4449 /* retry the login again */
7c3df132
SK		 4450 ql_dbg(ql_dbg_disc, vha, 0x2007,
4451 "Retrying %d login again loop_id 0x%x.\n",
4452 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4453 } else {
4454 fcport->login_retry = 0;
4455 }
4456
4457 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4458 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4459 }
4460 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4461 break;
0971de7f 4462 }
0971de7f
AV		 4463}
4464
7d613ac6
SV		 4465/* Schedule work on any of the dpc-workqueues */
4466void
4467qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4468{
4469 struct qla_hw_data *ha = base_vha->hw;
4470
4471 switch (work_code) {
4472 case MBA_IDC_AEN: /* 0x8200 */
4473 if (ha->dpc_lp_wq)
4474 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4475 break;
4476
4477 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4478 if (!ha->flags.nic_core_reset_hdlr_active) {
4479 if (ha->dpc_hp_wq)
4480 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4481 } else
4482 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4483 "NIC Core reset is already active. Skip "
4484 "scheduling it again.\n");
4485 break;
4486 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4487 if (ha->dpc_hp_wq)
4488 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4489 break;
4490 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4491 if (ha->dpc_hp_wq)
4492 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4493 break;
4494 default:
4495 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4496 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4497 }
4498
4499 return;
4500}
4501
4502/* Work: Perform NIC Core Unrecoverable state handling */
4503void
4504qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4505{
4506 struct qla_hw_data *ha =
2ad1b67c 4507 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4508 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4509 uint32_t dev_state = 0;
4510
4511 qla83xx_idc_lock(base_vha, 0);
4512 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4513 qla83xx_reset_ownership(base_vha);
4514 if (ha->flags.nic_core_reset_owner) {
4515 ha->flags.nic_core_reset_owner = 0;
4516 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4517 QLA8XXX_DEV_FAILED);
4518 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4519 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4520 }
4521 qla83xx_idc_unlock(base_vha, 0);
4522}
4523
4524/* Work: Execute IDC state handler */
4525void
4526qla83xx_idc_state_handler_work(struct work_struct *work)
4527{
4528 struct qla_hw_data *ha =
2ad1b67c 4529 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4530 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4531 uint32_t dev_state = 0;
4532
4533 qla83xx_idc_lock(base_vha, 0);
4534 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4535 if (dev_state == QLA8XXX_DEV_FAILED ||
4536 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4537 qla83xx_idc_state_handler(base_vha);
4538 qla83xx_idc_unlock(base_vha, 0);
4539}
4540
fa492630 4541static int
7d613ac6
SV		 4542qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4543{
4544 int rval = QLA_SUCCESS;
4545 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4546 uint32_t heart_beat_counter1, heart_beat_counter2;
4547
4548 do {
4549 if (time_after(jiffies, heart_beat_wait)) {
4550 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4551 "Nic Core f/w is not alive.\n");
4552 rval = QLA_FUNCTION_FAILED;
4553 break;
4554 }
4555
4556 qla83xx_idc_lock(base_vha, 0);
4557 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4558 &heart_beat_counter1);
4559 qla83xx_idc_unlock(base_vha, 0);
4560 msleep(100);
4561 qla83xx_idc_lock(base_vha, 0);
4562 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4563 &heart_beat_counter2);
4564 qla83xx_idc_unlock(base_vha, 0);
4565 } while (heart_beat_counter1 == heart_beat_counter2);
4566
4567 return rval;
4568}
4569
4570/* Work: Perform NIC Core Reset handling */
4571void
4572qla83xx_nic_core_reset_work(struct work_struct *work)
4573{
4574 struct qla_hw_data *ha =
4575 container_of(work, struct qla_hw_data, nic_core_reset);
4576 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4577 uint32_t dev_state = 0;
4578
81178772
SK		 4579 if (IS_QLA2031(ha)) {
4580 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4581 ql_log(ql_log_warn, base_vha, 0xb081,
4582 "Failed to dump mctp\n");
4583 return;
4584 }
4585
7d613ac6
SV		 4586 if (!ha->flags.nic_core_reset_hdlr_active) {
4587 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4588 qla83xx_idc_lock(base_vha, 0);
4589 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4590 &dev_state);
4591 qla83xx_idc_unlock(base_vha, 0);
4592 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4593 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4594 "Nic Core f/w is alive.\n");
4595 return;
4596 }
4597 }
4598
4599 ha->flags.nic_core_reset_hdlr_active = 1;
4600 if (qla83xx_nic_core_reset(base_vha)) {
4601 /* NIC Core reset failed. */
4602 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4603 "NIC Core reset failed.\n");
4604 }
4605 ha->flags.nic_core_reset_hdlr_active = 0;
4606 }
4607}
4608
4609/* Work: Handle 8200 IDC aens */
4610void
4611qla83xx_service_idc_aen(struct work_struct *work)
4612{
4613 struct qla_hw_data *ha =
4614 container_of(work, struct qla_hw_data, idc_aen);
4615 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4616 uint32_t dev_state, idc_control;
4617
4618 qla83xx_idc_lock(base_vha, 0);
4619 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4620 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4621 qla83xx_idc_unlock(base_vha, 0);
4622 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4623 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4624 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4625 "Application requested NIC Core Reset.\n");
4626 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4627 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4628 QLA_SUCCESS) {
4629 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4630 "Other protocol driver requested NIC Core Reset.\n");
4631 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4632 }
4633 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4634 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4635 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4636 }
4637}
4638
4639static void
4640qla83xx_wait_logic(void)
4641{
4642 int i;
4643
4644 /* Yield CPU */
4645 if (!in_interrupt()) {
4646 /*
4647 * Wait about 200ms before retrying again.
4648 * This controls the number of retries for single
4649 * lock operation.
4650 */
4651 msleep(100);
4652 schedule();
4653 } else {
4654 for (i = 0; i < 20; i++)
4655 cpu_relax(); /* This a nop instr on i386 */
4656 }
4657}
4658
fa492630 4659static int
7d613ac6
SV		 4660qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4661{
4662 int rval;
4663 uint32_t data;
4664 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4665 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4666 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4667 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4668 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4669
4670 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4671 if (rval)
4672 return rval;
4673
4674 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4675 return QLA_SUCCESS;
4676 } else {
4677 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4678 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4679 data);
4680 if (rval)
4681 return rval;
4682
4683 msleep(200);
4684
4685 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4686 &data);
4687 if (rval)
4688 return rval;
4689
4690 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4691 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4692 ~(idc_lck_rcvry_stage_mask));
4693 rval = qla83xx_wr_reg(base_vha,
4694 QLA83XX_IDC_LOCK_RECOVERY, data);
4695 if (rval)
4696 return rval;
4697
4698 /* Forcefully perform IDC UnLock */
4699 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4700 &data);
4701 if (rval)
4702 return rval;
4703 /* Clear lock-id by setting 0xff */
4704 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4705 0xff);
4706 if (rval)
4707 return rval;
4708 /* Clear lock-recovery by setting 0x0 */
4709 rval = qla83xx_wr_reg(base_vha,
4710 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4711 if (rval)
4712 return rval;
4713 } else
4714 return QLA_SUCCESS;
4715 }
4716
4717 return rval;
4718}
4719
fa492630 4720static int
7d613ac6
SV		 4721qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4722{
4723 int rval = QLA_SUCCESS;
4724 uint32_t o_drv_lockid, n_drv_lockid;
4725 unsigned long lock_recovery_timeout;
4726
4727 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4728retry_lockid:
4729 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4730 if (rval)
4731 goto exit;
4732
4733 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4734 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4735 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4736 return QLA_SUCCESS;
4737 else
4738 return QLA_FUNCTION_FAILED;
4739 }
4740
4741 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4742 if (rval)
4743 goto exit;
4744
4745 if (o_drv_lockid == n_drv_lockid) {
4746 qla83xx_wait_logic();
4747 goto retry_lockid;
4748 } else
4749 return QLA_SUCCESS;
4750
4751exit:
4752 return rval;
4753}
4754
4755void
4756qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4757{
4758 uint16_t options = (requester_id << 15) | BIT_6;
4759 uint32_t data;
6c315553 4760 uint32_t lock_owner;
7d613ac6
SV		 4761 struct qla_hw_data *ha = base_vha->hw;
4762
4763 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4764retry_lock:
4765 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4766 == QLA_SUCCESS) {
4767 if (data) {
4768 /* Setting lock-id to our function-number */
4769 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4770 ha->portnum);
4771 } else {
6c315553
SK		 4772 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4773 &lock_owner);
7d613ac6 4774 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4775 "Failed to acquire IDC lock, acquired by %d, "
4776 "retrying...\n", lock_owner);
7d613ac6
SV		 4777
4778 /* Retry/Perform IDC-Lock recovery */
4779 if (qla83xx_idc_lock_recovery(base_vha)
4780 == QLA_SUCCESS) {
4781 qla83xx_wait_logic();
4782 goto retry_lock;
4783 } else
4784 ql_log(ql_log_warn, base_vha, 0xb075,
4785 "IDC Lock recovery FAILED.\n");
4786 }
4787
4788 }
4789
4790 return;
4791
4792 /* XXX: IDC-lock implementation using access-control mbx */
4793retry_lock2:
4794 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4795 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4796 "Failed to acquire IDC lock. retrying...\n");
4797 /* Retry/Perform IDC-Lock recovery */
4798 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4799 qla83xx_wait_logic();
4800 goto retry_lock2;
4801 } else
4802 ql_log(ql_log_warn, base_vha, 0xb076,
4803 "IDC Lock recovery FAILED.\n");
4804 }
4805
4806 return;
4807}
4808
4809void
4810qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4811{
5897cb2f
BVA		 4812#if 0
4813 uint16_t options = (requester_id << 15) | BIT_7;
4814#endif
4815 uint16_t retry;
7d613ac6
SV		 4816 uint32_t data;
4817 struct qla_hw_data *ha = base_vha->hw;
4818
4819 /* IDC-unlock implementation using driver-unlock/lock-id
4820 * remote registers
4821 */
4822 retry = 0;
4823retry_unlock:
4824 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4825 == QLA_SUCCESS) {
4826 if (data == ha->portnum) {
4827 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4828 /* Clearing lock-id by setting 0xff */
4829 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4830 } else if (retry < 10) {
4831 /* SV: XXX: IDC unlock retrying needed here? */
4832
4833 /* Retry for IDC-unlock */
4834 qla83xx_wait_logic();
4835 retry++;
4836 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 4837 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4838 goto retry_unlock;
4839 }
4840 } else if (retry < 10) {
4841 /* Retry for IDC-unlock */
4842 qla83xx_wait_logic();
4843 retry++;
4844 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 4845 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 4846 goto retry_unlock;
4847 }
4848
4849 return;
4850
5897cb2f 4851#if 0
7d613ac6
SV		 4852 /* XXX: IDC-unlock implementation using access-control mbx */
4853 retry = 0;
4854retry_unlock2:
4855 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4856 if (retry < 10) {
4857 /* Retry for IDC-unlock */
4858 qla83xx_wait_logic();
4859 retry++;
4860 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 4861 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4862 goto retry_unlock2;
4863 }
4864 }
4865
4866 return;
5897cb2f 4867#endif
7d613ac6
SV		 4868}
4869
4870int
4871__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4872{
4873 int rval = QLA_SUCCESS;
4874 struct qla_hw_data *ha = vha->hw;
4875 uint32_t drv_presence;
4876
4877 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4878 if (rval == QLA_SUCCESS) {
4879 drv_presence |= (1 << ha->portnum);
4880 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4881 drv_presence);
4882 }
4883
4884 return rval;
4885}
4886
4887int
4888qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4889{
4890 int rval = QLA_SUCCESS;
4891
4892 qla83xx_idc_lock(vha, 0);
4893 rval = __qla83xx_set_drv_presence(vha);
4894 qla83xx_idc_unlock(vha, 0);
4895
4896 return rval;
4897}
4898
4899int
4900__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4901{
4902 int rval = QLA_SUCCESS;
4903 struct qla_hw_data *ha = vha->hw;
4904 uint32_t drv_presence;
4905
4906 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4907 if (rval == QLA_SUCCESS) {
4908 drv_presence &= ~(1 << ha->portnum);
4909 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4910 drv_presence);
4911 }
4912
4913 return rval;
4914}
4915
4916int
4917qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4918{
4919 int rval = QLA_SUCCESS;
4920
4921 qla83xx_idc_lock(vha, 0);
4922 rval = __qla83xx_clear_drv_presence(vha);
4923 qla83xx_idc_unlock(vha, 0);
4924
4925 return rval;
4926}
4927
fa492630 4928static void
7d613ac6
SV		 4929qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4930{
4931 struct qla_hw_data *ha = vha->hw;
4932 uint32_t drv_ack, drv_presence;
4933 unsigned long ack_timeout;
4934
4935 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4936 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4937 while (1) {
4938 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4939 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4940 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4941 break;
4942
4943 if (time_after_eq(jiffies, ack_timeout)) {
4944 ql_log(ql_log_warn, vha, 0xb067,
4945 "RESET ACK TIMEOUT! drv_presence=0x%x "
4946 "drv_ack=0x%x\n", drv_presence, drv_ack);
4947 /*
4948 * The function(s) which did not ack in time are forced
4949 * to withdraw any further participation in the IDC
4950 * reset.
4951 */
4952 if (drv_ack != drv_presence)
4953 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4954 drv_ack);
4955 break;
4956 }
4957
4958 qla83xx_idc_unlock(vha, 0);
4959 msleep(1000);
4960 qla83xx_idc_lock(vha, 0);
4961 }
4962
4963 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4964 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4965}
4966
fa492630 4967static int
7d613ac6
SV		 4968qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4969{
4970 int rval = QLA_SUCCESS;
4971 uint32_t idc_control;
4972
4973 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4974 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4975
4976 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4977 __qla83xx_get_idc_control(vha, &idc_control);
4978 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4979 __qla83xx_set_idc_control(vha, 0);
4980
4981 qla83xx_idc_unlock(vha, 0);
4982 rval = qla83xx_restart_nic_firmware(vha);
4983 qla83xx_idc_lock(vha, 0);
4984
4985 if (rval != QLA_SUCCESS) {
4986 ql_log(ql_log_fatal, vha, 0xb06a,
4987 "Failed to restart NIC f/w.\n");
4988 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4989 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4990 } else {
4991 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4992 "Success in restarting nic f/w.\n");
4993 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4994 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4995 }
4996
4997 return rval;
4998}
4999
5000/* Assumes idc_lock always held on entry */
5001int
5002qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5003{
5004 struct qla_hw_data *ha = base_vha->hw;
5005 int rval = QLA_SUCCESS;
5006 unsigned long dev_init_timeout;
5007 uint32_t dev_state;
5008
5009 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5010 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5011
5012 while (1) {
5013
5014 if (time_after_eq(jiffies, dev_init_timeout)) {
5015 ql_log(ql_log_warn, base_vha, 0xb06e,
5016 "Initialization TIMEOUT!\n");
5017 /* Init timeout. Disable further NIC Core
5018 * communication.
5019 */
5020 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5021 QLA8XXX_DEV_FAILED);
5022 ql_log(ql_log_info, base_vha, 0xb06f,
5023 "HW State: FAILED.\n");
5024 }
5025
5026 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5027 switch (dev_state) {
5028 case QLA8XXX_DEV_READY:
5029 if (ha->flags.nic_core_reset_owner)
5030 qla83xx_idc_audit(base_vha,
5031 IDC_AUDIT_COMPLETION);
5032 ha->flags.nic_core_reset_owner = 0;
5033 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5034 "Reset_owner reset by 0x%x.\n",
5035 ha->portnum);
5036 goto exit;
5037 case QLA8XXX_DEV_COLD:
5038 if (ha->flags.nic_core_reset_owner)
5039 rval = qla83xx_device_bootstrap(base_vha);
5040 else {
5041 /* Wait for AEN to change device-state */
5042 qla83xx_idc_unlock(base_vha, 0);
5043 msleep(1000);
5044 qla83xx_idc_lock(base_vha, 0);
5045 }
5046 break;
5047 case QLA8XXX_DEV_INITIALIZING:
5048 /* Wait for AEN to change device-state */
5049 qla83xx_idc_unlock(base_vha, 0);
5050 msleep(1000);
5051 qla83xx_idc_lock(base_vha, 0);
5052 break;
5053 case QLA8XXX_DEV_NEED_RESET:
5054 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5055 qla83xx_need_reset_handler(base_vha);
5056 else {
5057 /* Wait for AEN to change device-state */
5058 qla83xx_idc_unlock(base_vha, 0);
5059 msleep(1000);
5060 qla83xx_idc_lock(base_vha, 0);
5061 }
5062 /* reset timeout value after need reset handler */
5063 dev_init_timeout = jiffies +
5064 (ha->fcoe_dev_init_timeout * HZ);
5065 break;
5066 case QLA8XXX_DEV_NEED_QUIESCENT:
5067 /* XXX: DEBUG for now */
5068 qla83xx_idc_unlock(base_vha, 0);
5069 msleep(1000);
5070 qla83xx_idc_lock(base_vha, 0);
5071 break;
5072 case QLA8XXX_DEV_QUIESCENT:
5073 /* XXX: DEBUG for now */
5074 if (ha->flags.quiesce_owner)
5075 goto exit;
5076
5077 qla83xx_idc_unlock(base_vha, 0);
5078 msleep(1000);
5079 qla83xx_idc_lock(base_vha, 0);
5080 dev_init_timeout = jiffies +
5081 (ha->fcoe_dev_init_timeout * HZ);
5082 break;
5083 case QLA8XXX_DEV_FAILED:
5084 if (ha->flags.nic_core_reset_owner)
5085 qla83xx_idc_audit(base_vha,
5086 IDC_AUDIT_COMPLETION);
5087 ha->flags.nic_core_reset_owner = 0;
5088 __qla83xx_clear_drv_presence(base_vha);
5089 qla83xx_idc_unlock(base_vha, 0);
5090 qla8xxx_dev_failed_handler(base_vha);
5091 rval = QLA_FUNCTION_FAILED;
5092 qla83xx_idc_lock(base_vha, 0);
5093 goto exit;
5094 case QLA8XXX_BAD_VALUE:
5095 qla83xx_idc_unlock(base_vha, 0);
5096 msleep(1000);
5097 qla83xx_idc_lock(base_vha, 0);
5098 break;
5099 default:
5100 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5101 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5102 qla83xx_idc_unlock(base_vha, 0);
5103 qla8xxx_dev_failed_handler(base_vha);
5104 rval = QLA_FUNCTION_FAILED;
5105 qla83xx_idc_lock(base_vha, 0);
5106 goto exit;
5107 }
5108 }
5109
5110exit:
5111 return rval;
5112}
5113
f3ddac19
CD		 5114void
5115qla2x00_disable_board_on_pci_error(struct work_struct *work)
5116{
5117 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5118 board_disable);
5119 struct pci_dev *pdev = ha->pdev;
5120 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5121
783e0dc4
SC		 5122 /* if UNLOAD flag is already set, then continue unload,
5123 * where it was set first.
5124 */
5125 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5126 return;
5127
f3ddac19
CD		 5128 ql_log(ql_log_warn, base_vha, 0x015b,
5129 "Disabling adapter.\n");
5130
5131 set_bit(UNLOADING, &base_vha->dpc_flags);
5132
5133 qla2x00_delete_all_vps(ha, base_vha);
5134
5135 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5136
5137 qla2x00_dfs_remove(base_vha);
5138
5139 qla84xx_put_chip(base_vha);
5140
5141 if (base_vha->timer_active)
5142 qla2x00_stop_timer(base_vha);
5143
5144 base_vha->flags.online = 0;
5145
5146 qla2x00_destroy_deferred_work(ha);
5147
5148 /*
5149 * Do not try to stop beacon blink as it will issue a mailbox
5150 * command.
5151 */
5152 qla2x00_free_sysfs_attr(base_vha, false);
5153
5154 fc_remove_host(base_vha->host);
5155
5156 scsi_remove_host(base_vha->host);
5157
5158 base_vha->flags.init_done = 0;
5159 qla25xx_delete_queues(base_vha);
5160 qla2x00_free_irqs(base_vha);
5161 qla2x00_free_fcports(base_vha);
5162 qla2x00_mem_free(ha);
5163 qla82xx_md_free(base_vha);
5164 qla2x00_free_queues(ha);
5165
f3ddac19
CD		 5166 qla2x00_unmap_iobases(ha);
5167
5168 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5169 pci_disable_pcie_error_reporting(pdev);
5170 pci_disable_device(pdev);
f3ddac19 5171
beb9e315
JL		 5172 /*
5173 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5174 */
f3ddac19
CD		 5175}
5176
1da177e4
LT		 5177/**************************************************************************
5178* qla2x00_do_dpc
5179* This kernel thread is a task that is schedule by the interrupt handler
5180* to perform the background processing for interrupts.
5181*
5182* Notes:
5183* This task always run in the context of a kernel thread. It
5184* is kick-off by the driver's detect code and starts up
5185* up one per adapter. It immediately goes to sleep and waits for
5186* some fibre event. When either the interrupt handler or
5187* the timer routine detects a event it will one of the task
5188* bits then wake us up.
5189**************************************************************************/
5190static int
5191qla2x00_do_dpc(void *data)
5192{
e315cd28
AC		 5193 scsi_qla_host_t *base_vha;
5194 struct qla_hw_data *ha;
d7459527
MH		 5195 uint32_t online;
5196 struct qla_qpair *qpair;
1da177e4 5197
e315cd28
AC		 5198 ha = (struct qla_hw_data *)data;
5199 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5200
8698a745 5201 set_user_nice(current, MIN_NICE);
1da177e4 5202
563585ec 5203 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5204 while (!kthread_should_stop()) {
7c3df132
SK		 5205 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5206 "DPC handler sleeping.\n");
1da177e4 5207
39a11240 5208 schedule();
1da177e4 5209
c142caf0
AV		 5210 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5211 goto end_loop;
1da177e4 5212
85880801 5213 if (ha->flags.eeh_busy) {
7c3df132
SK		 5214 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5215 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5216 goto end_loop;
85880801
AV		 5217 }
5218
1da177e4
LT		 5219 ha->dpc_active = 1;
5220
5f28d2d7
SK		 5221 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5222 "DPC handler waking up, dpc_flags=0x%lx.\n",
5223 base_vha->dpc_flags);
1da177e4 5224
a29b3dd7
JC		 5225 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5226 break;
5227
e315cd28 5228 qla2x00_do_work(base_vha);
0971de7f 5229
7ec0effd
AD		 5230 if (IS_P3P_TYPE(ha)) {
5231 if (IS_QLA8044(ha)) {
5232 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5233 &base_vha->dpc_flags)) {
5234 qla8044_idc_lock(ha);
5235 qla8044_wr_direct(base_vha,
5236 QLA8044_CRB_DEV_STATE_INDEX,
5237 QLA8XXX_DEV_FAILED);
5238 qla8044_idc_unlock(ha);
5239 ql_log(ql_log_info, base_vha, 0x4004,
5240 "HW State: FAILED.\n");
5241 qla8044_device_state_handler(base_vha);
5242 continue;
5243 }
5244
5245 } else {
5246 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5247 &base_vha->dpc_flags)) {
5248 qla82xx_idc_lock(ha);
5249 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5250 QLA8XXX_DEV_FAILED);
5251 qla82xx_idc_unlock(ha);
5252 ql_log(ql_log_info, base_vha, 0x0151,
5253 "HW State: FAILED.\n");
5254 qla82xx_device_state_handler(base_vha);
5255 continue;
5256 }
a9083016
GM		 5257 }
5258
5259 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5260 &base_vha->dpc_flags)) {
5261
7c3df132
SK		 5262 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5263 "FCoE context reset scheduled.\n");
a9083016
GM		 5264 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5265 &base_vha->dpc_flags))) {
5266 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5267 /* FCoE-ctx reset failed.
5268 * Escalate to chip-reset
5269 */
5270 set_bit(ISP_ABORT_NEEDED,
5271 &base_vha->dpc_flags);
5272 }
5273 clear_bit(ABORT_ISP_ACTIVE,
5274 &base_vha->dpc_flags);
5275 }
5276
7c3df132
SK		 5277 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5278 "FCoE context reset end.\n");
a9083016 5279 }
8ae6d9c7
GM		 5280 } else if (IS_QLAFX00(ha)) {
5281 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5282 &base_vha->dpc_flags)) {
5283 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5284 "Firmware Reset Recovery\n");
5285 if (qlafx00_reset_initialize(base_vha)) {
5286 /* Failed. Abort isp later. */
5287 if (!test_bit(UNLOADING,
f92f82d6 5288 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5289 set_bit(ISP_UNRECOVERABLE,
5290 &base_vha->dpc_flags);
5291 ql_dbg(ql_dbg_dpc, base_vha,
5292 0x4021,
5293 "Reset Recovery Failed\n");
f92f82d6 5294 }
8ae6d9c7
GM		 5295 }
5296 }
5297
5298 if (test_and_clear_bit(FX00_TARGET_SCAN,
5299 &base_vha->dpc_flags)) {
5300 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5301 "ISPFx00 Target Scan scheduled\n");
5302 if (qlafx00_rescan_isp(base_vha)) {
5303 if (!test_bit(UNLOADING,
5304 &base_vha->dpc_flags))
5305 set_bit(ISP_UNRECOVERABLE,
5306 &base_vha->dpc_flags);
5307 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5308 "ISPFx00 Target Scan Failed\n");
5309 }
5310 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5311 "ISPFx00 Target Scan End\n");
5312 }
e8f5e95d
AB		 5313 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5314 &base_vha->dpc_flags)) {
5315 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5316 "ISPFx00 Host Info resend scheduled\n");
5317 qlafx00_fx_disc(base_vha,
5318 &base_vha->hw->mr.fcport,
5319 FXDISC_REG_HOST_INFO);
5320 }
a9083016
GM		 5321 }
5322
e315cd28
AC		 5323 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5324 &base_vha->dpc_flags)) {
1da177e4 5325
7c3df132
SK		 5326 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5327 "ISP abort scheduled.\n");
1da177e4 5328 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5329 &base_vha->dpc_flags))) {
1da177e4 5330
a9083016 5331 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5332 /* failed. retry later */
5333 set_bit(ISP_ABORT_NEEDED,
e315cd28 5334 &base_vha->dpc_flags);
99363ef8 5335 }
e315cd28
AC		 5336 clear_bit(ABORT_ISP_ACTIVE,
5337 &base_vha->dpc_flags);
99363ef8
SJ		 5338 }
5339
7c3df132
SK		 5340 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5341 "ISP abort end.\n");
1da177e4
LT		 5342 }
5343
a394aac8
DJ		 5344 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5345 &base_vha->dpc_flags)) {
e315cd28 5346 qla2x00_update_fcports(base_vha);
c9c5ced9 5347 }
d97994dc 5348
2d70c103
NB		 5349 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5350 int ret;
5351 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5352 if (ret != QLA_SUCCESS)
5353 ql_log(ql_log_warn, base_vha, 0x121,
5354 "Failed to enable receiving of RSCN "
5355 "requests: 0x%x.\n", ret);
5356 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5357 }
5358
8ae6d9c7
GM		 5359 if (IS_QLAFX00(ha))
5360 goto loop_resync_check;
5361
579d12b5 5362 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5363 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5364 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5365 if (IS_P3P_TYPE(ha)) {
5366 if (IS_QLA82XX(ha))
5367 qla82xx_device_state_handler(base_vha);
5368 if (IS_QLA8044(ha))
5369 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5370 clear_bit(ISP_QUIESCE_NEEDED,
5371 &base_vha->dpc_flags);
5372 if (!ha->flags.quiesce_owner) {
5373 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5374 if (IS_QLA82XX(ha)) {
5375 qla82xx_idc_lock(ha);
5376 qla82xx_clear_qsnt_ready(
5377 base_vha);
5378 qla82xx_idc_unlock(ha);
5379 } else if (IS_QLA8044(ha)) {
5380 qla8044_idc_lock(ha);
5381 qla8044_clear_qsnt_ready(
5382 base_vha);
5383 qla8044_idc_unlock(ha);
5384 }
8fcd6b8b
CD		 5385 }
5386 } else {
5387 clear_bit(ISP_QUIESCE_NEEDED,
5388 &base_vha->dpc_flags);
5389 qla2x00_quiesce_io(base_vha);
579d12b5 5390 }
7c3df132
SK		 5391 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5392 "Quiescence mode end.\n");
579d12b5
SK		 5393 }
5394
e315cd28 5395 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5396 &base_vha->dpc_flags) &&
e315cd28 5397 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5398
7c3df132
SK		 5399 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5400 "Reset marker scheduled.\n");
e315cd28
AC		 5401 qla2x00_rst_aen(base_vha);
5402 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5403 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5404 "Reset marker end.\n");
1da177e4
LT		 5405 }
5406
5407 /* Retry each device up to login retry count */
e315cd28
AC		 5408 if ((test_and_clear_bit(RELOGIN_NEEDED,
5409 &base_vha->dpc_flags)) &&
5410 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5411 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5412
7c3df132
SK		 5413 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5414 "Relogin scheduled.\n");
e315cd28 5415 qla2x00_relogin(base_vha);
7c3df132
SK		 5416 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5417 "Relogin end.\n");
1da177e4 5418 }
8ae6d9c7 5419loop_resync_check:
e315cd28 5420 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5421 &base_vha->dpc_flags)) {
1da177e4 5422
7c3df132
SK		 5423 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5424 "Loop resync scheduled.\n");
1da177e4
LT		 5425
5426 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5427 &base_vha->dpc_flags))) {
1da177e4 5428
52c82823 5429 qla2x00_loop_resync(base_vha);
1da177e4 5430
e315cd28
AC		 5431 clear_bit(LOOP_RESYNC_ACTIVE,
5432 &base_vha->dpc_flags);
1da177e4
LT		 5433 }
5434
7c3df132
SK		 5435 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5436 "Loop resync end.\n");
1da177e4
LT		 5437 }
5438
8ae6d9c7
GM		 5439 if (IS_QLAFX00(ha))
5440 goto intr_on_check;
5441
e315cd28
AC		 5442 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5443 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5444 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5445 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5446 }
5447
8ae6d9c7 5448intr_on_check:
1da177e4 5449 if (!ha->interrupts_on)
fd34f556 5450 ha->isp_ops->enable_intrs(ha);
1da177e4 5451
e315cd28 5452 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5453 &base_vha->dpc_flags)) {
5454 if (ha->beacon_blink_led == 1)
5455 ha->isp_ops->beacon_blink(base_vha);
5456 }
f6df144c 5457
d7459527
MH		 5458 /* qpair online check */
5459 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5460 &base_vha->dpc_flags)) {
5461 if (ha->flags.eeh_busy ||
5462 ha->flags.pci_channel_io_perm_failure)
5463 online = 0;
5464 else
5465 online = 1;
5466
5467 mutex_lock(&ha->mq_lock);
5468 list_for_each_entry(qpair, &base_vha->qp_list,
5469 qp_list_elem)
5470 qpair->online = online;
5471 mutex_unlock(&ha->mq_lock);
5472 }
5473
8ae6d9c7
GM		 5474 if (!IS_QLAFX00(ha))
5475 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5476
1da177e4 5477 ha->dpc_active = 0;
c142caf0 5478end_loop:
563585ec 5479 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5480 } /* End of while(1) */
563585ec 5481 __set_current_state(TASK_RUNNING);
1da177e4 5482
7c3df132
SK		 5483 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5484 "DPC handler exiting.\n");
1da177e4
LT		 5485
5486 /*
5487 * Make sure that nobody tries to wake us up again.
5488 */
1da177e4
LT		 5489 ha->dpc_active = 0;
5490
ac280b67
AV		 5491 /* Cleanup any residual CTX SRBs. */
5492 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5493
39a11240
CH		 5494 return 0;
5495}
5496
5497void
e315cd28 5498qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5499{
e315cd28 5500 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5501 struct task_struct *t = ha->dpc_thread;
5502
e315cd28 5503 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5504 wake_up_process(t);
1da177e4
LT		 5505}
5506
1da177e4
LT		 5507/*
5508* qla2x00_rst_aen
5509* Processes asynchronous reset.
5510*
5511* Input:
5512* ha = adapter block pointer.
5513*/
5514static void
e315cd28 5515qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5516{
e315cd28
AC		 5517 if (vha->flags.online && !vha->flags.reset_active &&
5518 !atomic_read(&vha->loop_down_timer) &&
5519 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5520 do {
e315cd28 5521 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5522
5523 /*
5524 * Issue marker command only when we are going to start
5525 * the I/O.
5526 */
e315cd28
AC		 5527 vha->marker_needed = 1;
5528 } while (!atomic_read(&vha->loop_down_timer) &&
5529 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5530 }
5531}
5532
1da177e4
LT		 5533/**************************************************************************
5534* qla2x00_timer
5535*
5536* Description:
5537* One second timer
5538*
5539* Context: Interrupt
5540***************************************************************************/
2c3dfe3f 5541void
e315cd28 5542qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5543{
1da177e4 5544 unsigned long cpu_flags = 0;
1da177e4
LT		 5545 int start_dpc = 0;
5546 int index;
5547 srb_t *sp;
85880801 5548 uint16_t w;
e315cd28 5549 struct qla_hw_data *ha = vha->hw;
73208dfd 5550 struct req_que *req;
85880801 5551
a5b36321 5552 if (ha->flags.eeh_busy) {
7c3df132
SK		 5553 ql_dbg(ql_dbg_timer, vha, 0x6000,
5554 "EEH = %d, restarting timer.\n",
5555 ha->flags.eeh_busy);
a5b36321
LC		 5556 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5557 return;
5558 }
5559
f3ddac19
CD		 5560 /*
5561 * Hardware read to raise pending EEH errors during mailbox waits. If
5562 * the read returns -1 then disable the board.
5563 */
5564 if (!pci_channel_offline(ha->pdev)) {
85880801 5565 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5566 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5567 }
1da177e4 5568
cefcaba6 5569 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5570 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5571 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5572 start_dpc++;
7ec0effd
AD		 5573 if (IS_QLA82XX(ha))
5574 qla82xx_watchdog(vha);
5575 else if (IS_QLA8044(ha))
5576 qla8044_watchdog(vha);
579d12b5
SK		 5577 }
5578
8ae6d9c7
GM		 5579 if (!vha->vp_idx && IS_QLAFX00(ha))
5580 qlafx00_timer_routine(vha);
5581
1da177e4 5582 /* Loop down handler. */
e315cd28 5583 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5584 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5585 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5586 && vha->flags.online) {
1da177e4 5587
e315cd28
AC		 5588 if (atomic_read(&vha->loop_down_timer) ==
5589 vha->loop_down_abort_time) {
1da177e4 5590
7c3df132
SK		 5591 ql_log(ql_log_info, vha, 0x6008,
5592 "Loop down - aborting the queues before time expires.\n");
1da177e4 5593
e315cd28
AC		 5594 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5595 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5596
f08b7251
AV		 5597 /*
5598 * Schedule an ISP abort to return any FCP2-device
5599 * commands.
5600 */
2c3dfe3f 5601 /* NPIV - scan physical port only */
e315cd28 5602 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5603 spin_lock_irqsave(&ha->hardware_lock,
5604 cpu_flags);
73208dfd 5605 req = ha->req_q_map[0];
2c3dfe3f 5606 for (index = 1;
8d93f550 5607 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5608 index++) {
5609 fc_port_t *sfcp;
5610
e315cd28 5611 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5612 if (!sp)
5613 continue;
9ba56b95 5614 if (sp->type != SRB_SCSI_CMD)
cf53b069 5615 continue;
2c3dfe3f 5616 sfcp = sp->fcport;
f08b7251 5617 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5618 continue;
bdf79621 5619
8f7daead
GM		 5620 if (IS_QLA82XX(ha))
5621 set_bit(FCOE_CTX_RESET_NEEDED,
5622 &vha->dpc_flags);
5623 else
5624 set_bit(ISP_ABORT_NEEDED,
e315cd28 5625 &vha->dpc_flags);
2c3dfe3f
SJ		 5626 break;
5627 }
5628 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5629 cpu_flags);
1da177e4 5630 }
1da177e4
LT		 5631 start_dpc++;
5632 }
5633
5634 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5635 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5636 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5637 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5638 "Loop down - aborting ISP.\n");
5639
8f7daead
GM		 5640 if (IS_QLA82XX(ha))
5641 set_bit(FCOE_CTX_RESET_NEEDED,
5642 &vha->dpc_flags);
5643 else
5644 set_bit(ISP_ABORT_NEEDED,
5645 &vha->dpc_flags);
1da177e4
LT		 5646 }
5647 }
7c3df132
SK		 5648 ql_dbg(ql_dbg_timer, vha, 0x600a,
5649 "Loop down - seconds remaining %d.\n",
5650 atomic_read(&vha->loop_down_timer));
1da177e4 5651 }
cefcaba6
SK		 5652 /* Check if beacon LED needs to be blinked for physical host only */
5653 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5654 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5655 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5656 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5657 start_dpc++;
5658 }
f6df144c
AV		 5659 }
5660
550bf57d 5661 /* Process any deferred work. */
e315cd28 5662 if (!list_empty(&vha->work_list))
550bf57d
AV		 5663 start_dpc++;
5664
1da177e4 5665 /* Schedule the DPC routine if needed */
e315cd28
AC		 5666 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5667 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5668 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5669 start_dpc ||
e315cd28
AC		 5670 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5671 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5672 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5673 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5674 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5675 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5676 ql_dbg(ql_dbg_timer, vha, 0x600b,
5677 "isp_abort_needed=%d loop_resync_needed=%d "
5678 "fcport_update_needed=%d start_dpc=%d "
5679 "reset_marker_needed=%d",
5680 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5681 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5682 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5683 start_dpc,
5684 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5685 ql_dbg(ql_dbg_timer, vha, 0x600c,
5686 "beacon_blink_needed=%d isp_unrecoverable=%d "
5687 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5688 "relogin_needed=%d.\n",
7c3df132
SK		 5689 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5690 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5691 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5692 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5693 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5694 qla2xxx_wake_dpc(vha);
7c3df132 5695 }
1da177e4 5696
e315cd28 5697 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5698}
5699
5433383e
AV		 5700/* Firmware interface routines. */
5701
f73cb695 5702#define FW_BLOBS 11
5433383e
AV		 5703#define FW_ISP21XX 0
5704#define FW_ISP22XX 1
5705#define FW_ISP2300 2
5706#define FW_ISP2322 3
48c02fde 5707#define FW_ISP24XX 4
c3a2f0df 5708#define FW_ISP25XX 5
3a03eb79 5709#define FW_ISP81XX 6
a9083016 5710#define FW_ISP82XX 7
6246b8a1
GM		 5711#define FW_ISP2031 8
5712#define FW_ISP8031 9
2c5bbbb2 5713#define FW_ISP27XX 10
5433383e 5714
bb8ee499
AV		 5715#define FW_FILE_ISP21XX "ql2100_fw.bin"
5716#define FW_FILE_ISP22XX "ql2200_fw.bin"
5717#define FW_FILE_ISP2300 "ql2300_fw.bin"
5718#define FW_FILE_ISP2322 "ql2322_fw.bin"
5719#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5720#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5721#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5722#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5723#define FW_FILE_ISP2031 "ql2600_fw.bin"
5724#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5725#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5726
bb8ee499 5727
e1e82b6f 5728static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5729
5730static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5731 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5732 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5733 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5734 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5735 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5736 { .name = FW_FILE_ISP25XX, },
3a03eb79 5737 { .name = FW_FILE_ISP81XX, },
a9083016 5738 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5739 { .name = FW_FILE_ISP2031, },
5740 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5741 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5742};
5743
5744struct fw_blob *
e315cd28 5745qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5746{
e315cd28 5747 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5748 struct fw_blob *blob;
5749
5433383e
AV		 5750 if (IS_QLA2100(ha)) {
5751 blob = &qla_fw_blobs[FW_ISP21XX];
5752 } else if (IS_QLA2200(ha)) {
5753 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5754 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5755 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5756 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5757 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5758 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5759 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5760 } else if (IS_QLA25XX(ha)) {
5761 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5762 } else if (IS_QLA81XX(ha)) {
5763 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5764 } else if (IS_QLA82XX(ha)) {
5765 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5766 } else if (IS_QLA2031(ha)) {
5767 blob = &qla_fw_blobs[FW_ISP2031];
5768 } else if (IS_QLA8031(ha)) {
5769 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5770 } else if (IS_QLA27XX(ha)) {
5771 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5772 } else {
5773 return NULL;
5433383e
AV		 5774 }
5775
e1e82b6f 5776 mutex_lock(&qla_fw_lock);
5433383e
AV		 5777 if (blob->fw)
5778 goto out;
5779
5780 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5781 ql_log(ql_log_warn, vha, 0x0063,
5782 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5783 blob->fw = NULL;
5784 blob = NULL;
5785 goto out;
5786 }
5787
5788out:
e1e82b6f 5789 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5790 return blob;
5791}
5792
5793static void
5794qla2x00_release_firmware(void)
5795{
5796 int idx;
5797
e1e82b6f 5798 mutex_lock(&qla_fw_lock);
5433383e 5799 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5800 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5801 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5802}
5803
14e660e6
SJ		 5804static pci_ers_result_t
5805qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5806{
85880801
AV		 5807 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5808 struct qla_hw_data *ha = vha->hw;
5809
7c3df132
SK		 5810 ql_dbg(ql_dbg_aer, vha, 0x9000,
5811 "PCI error detected, state %x.\n", state);
b9b12f73 5812
14e660e6
SJ		 5813 switch (state) {
5814 case pci_channel_io_normal:
85880801 5815 ha->flags.eeh_busy = 0;
d7459527
MH		 5816 if (ql2xmqsupport) {
5817 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5818 qla2xxx_wake_dpc(vha);
5819 }
14e660e6
SJ		 5820 return PCI_ERS_RESULT_CAN_RECOVER;
5821 case pci_channel_io_frozen:
85880801 5822 ha->flags.eeh_busy = 1;
a5b36321
LC		 5823 /* For ISP82XX complete any pending mailbox cmd */
5824 if (IS_QLA82XX(ha)) {
7190575f 5825 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5826 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5827 qla82xx_clear_pending_mbx(vha);
a5b36321 5828 }
90a86fc0 5829 qla2x00_free_irqs(vha);
14e660e6 5830 pci_disable_device(pdev);
bddd2d65
LC		 5831 /* Return back all IOs */
5832 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 5833 if (ql2xmqsupport) {
5834 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5835 qla2xxx_wake_dpc(vha);
5836 }
14e660e6
SJ		 5837 return PCI_ERS_RESULT_NEED_RESET;
5838 case pci_channel_io_perm_failure:
85880801
AV		 5839 ha->flags.pci_channel_io_perm_failure = 1;
5840 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 5841 if (ql2xmqsupport) {
5842 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5843 qla2xxx_wake_dpc(vha);
5844 }
14e660e6
SJ		 5845 return PCI_ERS_RESULT_DISCONNECT;
5846 }
5847 return PCI_ERS_RESULT_NEED_RESET;
5848}
5849
5850static pci_ers_result_t
5851qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5852{
5853 int risc_paused = 0;
5854 uint32_t stat;
5855 unsigned long flags;
e315cd28
AC		 5856 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5857 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5858 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5859 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5860
bcc5b6d3
SK		 5861 if (IS_QLA82XX(ha))
5862 return PCI_ERS_RESULT_RECOVERED;
5863
14e660e6
SJ		 5864 spin_lock_irqsave(&ha->hardware_lock, flags);
5865 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5866 stat = RD_REG_DWORD(&reg->hccr);
5867 if (stat & HCCR_RISC_PAUSE)
5868 risc_paused = 1;
5869 } else if (IS_QLA23XX(ha)) {
5870 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5871 if (stat & HSR_RISC_PAUSED)
5872 risc_paused = 1;
5873 } else if (IS_FWI2_CAPABLE(ha)) {
5874 stat = RD_REG_DWORD(&reg24->host_status);
5875 if (stat & HSRX_RISC_PAUSED)
5876 risc_paused = 1;
5877 }
5878 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5879
5880 if (risc_paused) {
7c3df132
SK		 5881 ql_log(ql_log_info, base_vha, 0x9003,
5882 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5883 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5884
5885 return PCI_ERS_RESULT_NEED_RESET;
5886 } else
5887 return PCI_ERS_RESULT_RECOVERED;
5888}
5889
fa492630
SK		 5890static uint32_t
5891qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5892{
5893 uint32_t rval = QLA_FUNCTION_FAILED;
5894 uint32_t drv_active = 0;
5895 struct qla_hw_data *ha = base_vha->hw;
5896 int fn;
5897 struct pci_dev *other_pdev = NULL;
5898
7c3df132
SK		 5899 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5900 "Entered %s.\n", __func__);
a5b36321
LC		 5901
5902 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5903
5904 if (base_vha->flags.online) {
5905 /* Abort all outstanding commands,
5906 * so as to be requeued later */
5907 qla2x00_abort_isp_cleanup(base_vha);
5908 }
5909
5910
5911 fn = PCI_FUNC(ha->pdev->devfn);
5912 while (fn > 0) {
5913 fn--;
7c3df132
SK		 5914 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5915 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5916 other_pdev =
5917 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5918 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5919 fn));
5920
5921 if (!other_pdev)
5922 continue;
5923 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5924 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5925 "Found PCI func available and enable at 0x%x.\n",
5926 fn);
a5b36321
LC		 5927 pci_dev_put(other_pdev);
5928 break;
5929 }
5930 pci_dev_put(other_pdev);
5931 }
5932
5933 if (!fn) {
5934 /* Reset owner */
7c3df132
SK		 5935 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5936 "This devfn is reset owner = 0x%x.\n",
5937 ha->pdev->devfn);
a5b36321
LC		 5938 qla82xx_idc_lock(ha);
5939
5940 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5941 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5942
5943 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5944 QLA82XX_IDC_VERSION);
5945
5946 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5947 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5948 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5949
5950 qla82xx_idc_unlock(ha);
5951 /* Reset if device is not already reset
5952 * drv_active would be 0 if a reset has already been done
5953 */
5954 if (drv_active)
5955 rval = qla82xx_start_firmware(base_vha);
5956 else
5957 rval = QLA_SUCCESS;
5958 qla82xx_idc_lock(ha);
5959
5960 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5961 ql_log(ql_log_info, base_vha, 0x900b,
5962 "HW State: FAILED.\n");
a5b36321
LC		 5963 qla82xx_clear_drv_active(ha);
5964 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5965 QLA8XXX_DEV_FAILED);
a5b36321 5966 } else {
7c3df132
SK		 5967 ql_log(ql_log_info, base_vha, 0x900c,
5968 "HW State: READY.\n");
a5b36321 5969 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5970 QLA8XXX_DEV_READY);
a5b36321 5971 qla82xx_idc_unlock(ha);
7190575f 5972 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5973 rval = qla82xx_restart_isp(base_vha);
5974 qla82xx_idc_lock(ha);
5975 /* Clear driver state register */
5976 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5977 qla82xx_set_drv_active(base_vha);
5978 }
5979 qla82xx_idc_unlock(ha);
5980 } else {
7c3df132
SK		 5981 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5982 "This devfn is not reset owner = 0x%x.\n",
5983 ha->pdev->devfn);
a5b36321 5984 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5985 QLA8XXX_DEV_READY)) {
7190575f 5986 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5987 rval = qla82xx_restart_isp(base_vha);
5988 qla82xx_idc_lock(ha);
5989 qla82xx_set_drv_active(base_vha);
5990 qla82xx_idc_unlock(ha);
5991 }
5992 }
5993 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5994
5995 return rval;
5996}
5997
14e660e6
SJ		 5998static pci_ers_result_t
5999qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6000{
6001 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6002 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6003 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6004 struct rsp_que *rsp;
6005 int rc, retries = 10;
09483916 6006
7c3df132
SK		 6007 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6008 "Slot Reset.\n");
85880801 6009
90a86fc0
JC		 6010 /* Workaround: qla2xxx driver which access hardware earlier
6011 * needs error state to be pci_channel_io_online.
6012 * Otherwise mailbox command timesout.
6013 */
6014 pdev->error_state = pci_channel_io_normal;
6015
6016 pci_restore_state(pdev);
6017
8c1496bd
RL		 6018 /* pci_restore_state() clears the saved_state flag of the device
6019 * save restored state which resets saved_state flag
6020 */
6021 pci_save_state(pdev);
6022
09483916
BH		 6023 if (ha->mem_only)
6024 rc = pci_enable_device_mem(pdev);
6025 else
6026 rc = pci_enable_device(pdev);
14e660e6 6027
09483916 6028 if (rc) {
7c3df132 6029 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6030 "Can't re-enable PCI device after reset.\n");
a5b36321 6031 goto exit_slot_reset;
14e660e6 6032 }
14e660e6 6033
90a86fc0
JC		 6034 rsp = ha->rsp_q_map[0];
6035 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6036 goto exit_slot_reset;
90a86fc0 6037
e315cd28 6038 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6039 goto exit_slot_reset;
6040
6041 if (IS_QLA82XX(ha)) {
6042 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6043 ret = PCI_ERS_RESULT_RECOVERED;
6044 goto exit_slot_reset;
6045 } else
6046 goto exit_slot_reset;
6047 }
14e660e6 6048
90a86fc0
JC		 6049 while (ha->flags.mbox_busy && retries--)
6050 msleep(1000);
85880801 6051
e315cd28 6052 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6053 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6054 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6055 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6056
90a86fc0 6057
a5b36321 6058exit_slot_reset:
7c3df132
SK		 6059 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6060 "slot_reset return %x.\n", ret);
85880801 6061
14e660e6
SJ		 6062 return ret;
6063}
6064
6065static void
6066qla2xxx_pci_resume(struct pci_dev *pdev)
6067{
e315cd28
AC		 6068 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6069 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6070 int ret;
6071
7c3df132
SK		 6072 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6073 "pci_resume.\n");
85880801 6074
e315cd28 6075 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6076 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6077 ql_log(ql_log_fatal, base_vha, 0x9002,
6078 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6079 }
85880801 6080
3e46f031
LC		 6081 pci_cleanup_aer_uncorrect_error_status(pdev);
6082
85880801 6083 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6084}
6085
2d5a4c34
HM		 6086static void
6087qla83xx_disable_laser(scsi_qla_host_t *vha)
6088{
6089 uint32_t reg, data, fn;
6090 struct qla_hw_data *ha = vha->hw;
6091 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6092
6093 /* pci func #/port # */
6094 ql_dbg(ql_dbg_init, vha, 0x004b,
6095 "Disabling Laser for hba: %p\n", vha);
6096
6097 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6098 (BIT_15|BIT_14|BIT_13|BIT_12));
6099
6100 fn = (fn >> 12);
6101
6102 if (fn & 1)
6103 reg = PORT_1_2031;
6104 else
6105 reg = PORT_0_2031;
6106
6107 data = LASER_OFF_2031;
6108
6109 qla83xx_wr_reg(vha, reg, data);
6110}
6111
a55b2d21 6112static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6113 .error_detected = qla2xxx_pci_error_detected,
6114 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6115 .slot_reset = qla2xxx_pci_slot_reset,
6116 .resume = qla2xxx_pci_resume,
6117};
6118
5433383e 6119static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6120 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6121 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6122 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6123 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6124 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6125 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6126 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6127 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6128 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6129 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6130 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6131 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6132 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6133 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6134 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6135 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6136 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6137 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6138 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6139 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6140 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6141 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6142 { 0 },
6143};
6144MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6145
fca29703 6146static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6147 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6148 .driver = {
6149 .owner = THIS_MODULE,
6150 },
fca29703 6151 .id_table = qla2xxx_pci_tbl,
7ee61397 6152 .probe = qla2x00_probe_one,
4c993f76 6153 .remove = qla2x00_remove_one,
e30d1756 6154 .shutdown = qla2x00_shutdown,
14e660e6 6155 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6156};
6157
75ef9de1 6158static const struct file_operations apidev_fops = {
6a03b4cd 6159 .owner = THIS_MODULE,
6038f373 6160 .llseek = noop_llseek,
6a03b4cd
HZ		 6161};
6162
1da177e4
LT		 6163/**
6164 * qla2x00_module_init - Module initialization.
6165 **/
6166static int __init
6167qla2x00_module_init(void)
6168{
fca29703
AV		 6169 int ret = 0;
6170
1da177e4 6171 /* Allocate cache for SRBs. */
354d6b21 6172 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6173 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6174 if (srb_cachep == NULL) {
7c3df132
SK		 6175 ql_log(ql_log_fatal, NULL, 0x0001,
6176 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6177 return -ENOMEM;
6178 }
6179
2d70c103
NB		 6180 /* Initialize target kmem_cache and mem_pools */
6181 ret = qlt_init();
6182 if (ret < 0) {
6183 kmem_cache_destroy(srb_cachep);
6184 return ret;
6185 } else if (ret > 0) {
6186 /*
6187 * If initiator mode is explictly disabled by qlt_init(),
6188 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6189 * performing scsi_scan_target() during LOOP UP event.
6190 */
6191 qla2xxx_transport_functions.disable_target_scan = 1;
6192 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6193 }
6194
1da177e4
LT		 6195 /* Derive version string. */
6196 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6197 if (ql2xextended_error_logging)
0181944f
AV		 6198 strcat(qla2x00_version_str, "-debug");
6199
1c97a12a
AV		 6200 qla2xxx_transport_template =
6201 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6202 if (!qla2xxx_transport_template) {
6203 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6204 ql_log(ql_log_fatal, NULL, 0x0002,
6205 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6206 qlt_exit();
1da177e4 6207 return -ENODEV;
2c3dfe3f 6208 }
6a03b4cd
HZ		 6209
6210 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6211 if (apidev_major < 0) {
7c3df132
SK		 6212 ql_log(ql_log_fatal, NULL, 0x0003,
6213 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6214 }
6215
2c3dfe3f
SJ		 6216 qla2xxx_transport_vport_template =
6217 fc_attach_transport(&qla2xxx_transport_vport_functions);
6218 if (!qla2xxx_transport_vport_template) {
6219 kmem_cache_destroy(srb_cachep);
2d70c103 6220 qlt_exit();
2c3dfe3f 6221 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6222 ql_log(ql_log_fatal, NULL, 0x0004,
6223 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6224 return -ENODEV;
2c3dfe3f 6225 }
7c3df132
SK		 6226 ql_log(ql_log_info, NULL, 0x0005,
6227 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6228 qla2x00_version_str);
7ee61397 6229 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6230 if (ret) {
6231 kmem_cache_destroy(srb_cachep);
2d70c103 6232 qlt_exit();
fca29703 6233 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6234 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6235 ql_log(ql_log_fatal, NULL, 0x0006,
6236 "pci_register_driver failed...ret=%d Failing load!.\n",
6237 ret);
fca29703
AV		 6238 }
6239 return ret;
1da177e4
LT		 6240}
6241
6242/**
6243 * qla2x00_module_exit - Module cleanup.
6244 **/
6245static void __exit
6246qla2x00_module_exit(void)
6247{
6a03b4cd 6248 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6249 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6250 qla2x00_release_firmware();
354d6b21 6251 kmem_cache_destroy(srb_cachep);
2d70c103 6252 qlt_exit();
a9083016
GM		 6253 if (ctx_cachep)
6254 kmem_cache_destroy(ctx_cachep);
1da177e4 6255 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6256 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6257}
6258
6259module_init(qla2x00_module_init);
6260module_exit(qla2x00_module_exit);
6261
6262MODULE_AUTHOR("QLogic Corporation");
6263MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6264MODULE_LICENSE("GPL");
6265MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6266MODULE_FIRMWARE(FW_FILE_ISP21XX);
6267MODULE_FIRMWARE(FW_FILE_ISP22XX);
6268MODULE_FIRMWARE(FW_FILE_ISP2300);
6269MODULE_FIRMWARE(FW_FILE_ISP2322);
6270MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6271MODULE_FIRMWARE(FW_FILE_ISP25XX);
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