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scsi: qla2xxx: Remove extra register read
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
3822263e 203int ql2xasynctmfenable;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
1da177e4 265/*
fa2a1ce5 266 * SCSI host template entry points
1da177e4
LT		 267 */
268static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 269static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 270static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
271static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 272static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 273static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 274static int qla2xxx_eh_abort(struct scsi_cmnd *);
275static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 276static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 277static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
278static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 279
1a2fbf18 280static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 281static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 282static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 283static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 284static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 285
a5326f86 286struct scsi_host_template qla2xxx_driver_template = {
1da177e4 287 .module = THIS_MODULE,
cb63067a 288 .name = QLA2XXX_DRIVER_NAME,
a5326f86 289 .queuecommand = qla2xxx_queuecommand,
fca29703 290
b6a05c82 291 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 292 .eh_abort_handler = qla2xxx_eh_abort,
293 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 294 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 295 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
296 .eh_host_reset_handler = qla2xxx_eh_host_reset,
297
298 .slave_configure = qla2xxx_slave_configure,
299
300 .slave_alloc = qla2xxx_slave_alloc,
301 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 302 .scan_finished = qla2xxx_scan_finished,
303 .scan_start = qla2xxx_scan_start,
db5ed4df 304 .change_queue_depth = scsi_change_queue_depth,
5601236b 305 .map_queues = qla2xxx_map_queues,
fca29703
AV		 306 .this_id = -1,
307 .cmd_per_lun = 3,
308 .use_clustering = ENABLE_CLUSTERING,
309 .sg_tablesize = SG_ALL,
310
311 .max_sectors = 0xFFFF,
afb046e2 312 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 313
314 .supported_mode = MODE_INITIATOR,
c40ecc12 315 .track_queue_depth = 1,
fca29703
AV		 316};
317
1da177e4 318static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 319struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 320
1da177e4
LT		 321/* TODO Convert to inlines
322 *
323 * Timer routines
324 */
1da177e4 325
2c3dfe3f 326__inline__ void
e315cd28 327qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 328{
e315cd28
AC		 329 init_timer(&vha->timer);
330 vha->timer.expires = jiffies + interval * HZ;
331 vha->timer.data = (unsigned long)vha;
332 vha->timer.function = (void (*)(unsigned long))func;
333 add_timer(&vha->timer);
334 vha->timer_active = 1;
1da177e4
LT		 335}
336
337static inline void
e315cd28 338qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 339{
a9083016 340 /* Currently used for 82XX only. */
7c3df132
SK		 341 if (vha->device_flags & DFLG_DEV_FAILED) {
342 ql_dbg(ql_dbg_timer, vha, 0x600d,
343 "Device in a failed state, returning.\n");
a9083016 344 return;
7c3df132 345 }
a9083016 346
e315cd28 347 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 348}
349
a824ebb3 350static __inline__ void
e315cd28 351qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 352{
e315cd28
AC		 353 del_timer_sync(&vha->timer);
354 vha->timer_active = 0;
1da177e4
LT		 355}
356
1da177e4
LT		 357static int qla2x00_do_dpc(void *data);
358
359static void qla2x00_rst_aen(scsi_qla_host_t *);
360
73208dfd
AC		 361static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
362 struct req_que **, struct rsp_que **);
e30d1756 363static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 364static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 365int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
366 struct qla_qpair *qpair);
1da177e4 367
1da177e4 368/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 369static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
370 struct rsp_que *rsp)
371{
372 struct qla_hw_data *ha = vha->hw;
373 rsp->qpair = ha->base_qpair;
374 rsp->req = req;
375 ha->base_qpair->req = req;
376 ha->base_qpair->rsp = rsp;
377 ha->base_qpair->vha = vha;
378 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
379 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
380 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
381 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
cf19c45d 382 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
8abfa9e2
QT		 383 ha->base_qpair->enable_class_2 = ql2xenableclass2;
384 /* init qpair to this cpu. Will adjust at run time. */
385 qla_cpu_update(rsp->qpair, smp_processor_id());
386 ha->base_qpair->pdev = ha->pdev;
387
388 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
389 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
390}
391
9a347ff4
CD		 392static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
393 struct rsp_que *rsp)
73208dfd 394{
7c3df132 395 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 396 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 397 GFP_KERNEL);
398 if (!ha->req_q_map) {
7c3df132
SK		 399 ql_log(ql_log_fatal, vha, 0x003b,
400 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 401 goto fail_req_map;
402 }
403
2afa19a9 404 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 405 GFP_KERNEL);
406 if (!ha->rsp_q_map) {
7c3df132
SK		 407 ql_log(ql_log_fatal, vha, 0x003c,
408 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 409 goto fail_rsp_map;
410 }
d7459527 411
e326d22a
QT		 412 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
413 if (ha->base_qpair == NULL) {
414 ql_log(ql_log_warn, vha, 0x00e0,
415 "Failed to allocate base queue pair memory.\n");
416 goto fail_base_qpair;
417 }
418
8abfa9e2 419 qla_init_base_qpair(vha, req, rsp);
e326d22a 420
d7459527
MH		 421 if (ql2xmqsupport && ha->max_qpairs) {
422 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
423 GFP_KERNEL);
424 if (!ha->queue_pair_map) {
425 ql_log(ql_log_fatal, vha, 0x0180,
426 "Unable to allocate memory for queue pair ptrs.\n");
427 goto fail_qpair_map;
428 }
d7459527
MH		 429 }
430
9a347ff4
CD		 431 /*
432 * Make sure we record at least the request and response queue zero in
433 * case we need to free them if part of the probe fails.
434 */
435 ha->rsp_q_map[0] = rsp;
436 ha->req_q_map[0] = req;
73208dfd
AC		 437 set_bit(0, ha->rsp_qid_map);
438 set_bit(0, ha->req_qid_map);
439 return 1;
440
d7459527 441fail_qpair_map:
82de802a
QT		 442 kfree(ha->base_qpair);
443 ha->base_qpair = NULL;
444fail_base_qpair:
d7459527
MH		 445 kfree(ha->rsp_q_map);
446 ha->rsp_q_map = NULL;
73208dfd
AC		 447fail_rsp_map:
448 kfree(ha->req_q_map);
449 ha->req_q_map = NULL;
450fail_req_map:
451 return -ENOMEM;
452}
453
2afa19a9 454static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 455{
8ae6d9c7
GM		 456 if (IS_QLAFX00(ha)) {
457 if (req && req->ring_fx00)
458 dma_free_coherent(&ha->pdev->dev,
459 (req->length_fx00 + 1) * sizeof(request_t),
460 req->ring_fx00, req->dma_fx00);
461 } else if (req && req->ring)
73208dfd
AC		 462 dma_free_coherent(&ha->pdev->dev,
463 (req->length + 1) * sizeof(request_t),
464 req->ring, req->dma);
465
8d93f550
CD		 466 if (req)
467 kfree(req->outstanding_cmds);
468
73208dfd 469 kfree(req);
73208dfd
AC		 470}
471
2afa19a9
AC		 472static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
473{
8ae6d9c7
GM		 474 if (IS_QLAFX00(ha)) {
475 if (rsp && rsp->ring)
476 dma_free_coherent(&ha->pdev->dev,
477 (rsp->length_fx00 + 1) * sizeof(request_t),
478 rsp->ring_fx00, rsp->dma_fx00);
479 } else if (rsp && rsp->ring) {
2afa19a9
AC		 480 dma_free_coherent(&ha->pdev->dev,
481 (rsp->length + 1) * sizeof(response_t),
482 rsp->ring, rsp->dma);
8ae6d9c7 483 }
2afa19a9 484 kfree(rsp);
2afa19a9
AC		 485}
486
73208dfd
AC		 487static void qla2x00_free_queues(struct qla_hw_data *ha)
488{
489 struct req_que *req;
490 struct rsp_que *rsp;
491 int cnt;
093df737 492 unsigned long flags;
73208dfd 493
82de802a
QT		 494 if (ha->queue_pair_map) {
495 kfree(ha->queue_pair_map);
496 ha->queue_pair_map = NULL;
497 }
498 if (ha->base_qpair) {
499 kfree(ha->base_qpair);
500 ha->base_qpair = NULL;
501 }
502
093df737 503 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 504 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 505 if (!test_bit(cnt, ha->req_qid_map))
506 continue;
507
73208dfd 508 req = ha->req_q_map[cnt];
093df737
QT		 509 clear_bit(cnt, ha->req_qid_map);
510 ha->req_q_map[cnt] = NULL;
511
512 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 513 qla2x00_free_req_que(ha, req);
093df737 514 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 515 }
093df737
QT		 516 spin_unlock_irqrestore(&ha->hardware_lock, flags);
517
73208dfd
AC		 518 kfree(ha->req_q_map);
519 ha->req_q_map = NULL;
2afa19a9 520
093df737
QT		 521
522 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 523 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 524 if (!test_bit(cnt, ha->rsp_qid_map))
525 continue;
526
2afa19a9 527 rsp = ha->rsp_q_map[cnt];
c3c42394 528 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 529 ha->rsp_q_map[cnt] = NULL;
530 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 531 qla2x00_free_rsp_que(ha, rsp);
093df737 532 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 533 }
093df737
QT		 534 spin_unlock_irqrestore(&ha->hardware_lock, flags);
535
2afa19a9
AC		 536 kfree(ha->rsp_q_map);
537 ha->rsp_q_map = NULL;
73208dfd
AC		 538}
539
1da177e4 540static char *
e315cd28 541qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 542{
e315cd28 543 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 544 static char *pci_bus_modes[] = {
545 "33", "66", "100", "133",
546 };
547 uint16_t pci_bus;
548
549 strcpy(str, "PCI");
550 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
551 if (pci_bus) {
552 strcat(str, "-X (");
553 strcat(str, pci_bus_modes[pci_bus]);
554 } else {
555 pci_bus = (ha->pci_attr & BIT_8) >> 8;
556 strcat(str, " (");
557 strcat(str, pci_bus_modes[pci_bus]);
558 }
559 strcat(str, " MHz)");
560
561 return (str);
562}
563
fca29703 564static char *
e315cd28 565qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 566{
567 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 568 struct qla_hw_data *ha = vha->hw;
fca29703 569 uint32_t pci_bus;
fca29703 570
62a276f8 571 if (pci_is_pcie(ha->pdev)) {
fca29703 572 char lwstr[6];
62a276f8 573 uint32_t lstat, lspeed, lwidth;
fca29703 574
62a276f8
BH		 575 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
576 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
577 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 578
579 strcpy(str, "PCIe (");
49300af7
SK		 580 switch (lspeed) {
581 case 1:
c87a0d8c 582 strcat(str, "2.5GT/s ");
49300af7
SK		 583 break;
584 case 2:
c87a0d8c 585 strcat(str, "5.0GT/s ");
49300af7
SK		 586 break;
587 case 3:
588 strcat(str, "8.0GT/s ");
589 break;
590 default:
fca29703 591 strcat(str, "<unknown> ");
49300af7
SK		 592 break;
593 }
fca29703
AV		 594 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
595 strcat(str, lwstr);
596
597 return str;
598 }
599
600 strcpy(str, "PCI");
601 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
602 if (pci_bus == 0 || pci_bus == 8) {
603 strcat(str, " (");
604 strcat(str, pci_bus_modes[pci_bus >> 3]);
605 } else {
606 strcat(str, "-X ");
607 if (pci_bus & BIT_2)
608 strcat(str, "Mode 2");
609 else
610 strcat(str, "Mode 1");
611 strcat(str, " (");
612 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
613 }
614 strcat(str, " MHz)");
615
616 return str;
617}
618
e5f82ab8 619static char *
df57caba 620qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 621{
622 char un_str[10];
e315cd28 623 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 624
df57caba
HM		 625 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
626 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 627
628 if (ha->fw_attributes & BIT_9) {
629 strcat(str, "FLX");
630 return (str);
631 }
632
633 switch (ha->fw_attributes & 0xFF) {
634 case 0x7:
635 strcat(str, "EF");
636 break;
637 case 0x17:
638 strcat(str, "TP");
639 break;
640 case 0x37:
641 strcat(str, "IP");
642 break;
643 case 0x77:
644 strcat(str, "VI");
645 break;
646 default:
647 sprintf(un_str, "(%x)", ha->fw_attributes);
648 strcat(str, un_str);
649 break;
650 }
651 if (ha->fw_attributes & 0x100)
652 strcat(str, "X");
653
654 return (str);
655}
656
e5f82ab8 657static char *
df57caba 658qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 659{
e315cd28 660 struct qla_hw_data *ha = vha->hw;
f0883ac6 661
df57caba 662 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 663 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 664 return str;
fca29703
AV		 665}
666
9ba56b95 667void
25ff6af1 668qla2x00_sp_free_dma(void *ptr)
fca29703 669{
25ff6af1
JC		 670 srb_t *sp = ptr;
671 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 672 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 673 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 674
9ba56b95
GM		 675 if (sp->flags & SRB_DMA_VALID) {
676 scsi_dma_unmap(cmd);
677 sp->flags &= ~SRB_DMA_VALID;
7c3df132 678 }
fca29703 679
9ba56b95
GM		 680 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
681 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
682 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
683 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
684 }
685
d5ff0eed
JC		 686 if (!ctx)
687 goto end;
688
9ba56b95
GM		 689 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
690 /* List assured to be having elements */
d5ff0eed 691 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 692 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
693 }
694
695 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 696 struct crc_context *ctx0 = ctx;
697
698 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 699 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
700 }
701
702 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 703 struct ct6_dsd *ctx1 = ctx;
fca29703 704
9ba56b95 705 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 706 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 707 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
708 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
709 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
710 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 711 }
712
d5ff0eed 713end:
6fcd98fd 714 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 715 CMD_SP(cmd) = NULL;
716 qla2x00_rel_sp(sp);
717 }
9ba56b95
GM		 718}
719
d7459527 720void
25ff6af1 721qla2x00_sp_compl(void *ptr, int res)
9ba56b95 722{
25ff6af1 723 srb_t *sp = ptr;
9ba56b95
GM		 724 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
725
726 cmd->result = res;
727
728 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 729 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 730 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
731 sp, GET_CMD_SP(sp));
732 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 733 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 734 return;
735 }
736 if (!atomic_dec_and_test(&sp->ref_count))
737 return;
738
25ff6af1 739 qla2x00_sp_free_dma(sp);
9ba56b95 740 cmd->scsi_done(cmd);
fca29703
AV		 741}
742
d7459527 743void
25ff6af1 744qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 745{
746 srb_t *sp = (srb_t *)ptr;
747 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
748 struct qla_hw_data *ha = sp->fcport->vha->hw;
749 void *ctx = GET_CMD_CTX_SP(sp);
750
751 if (sp->flags & SRB_DMA_VALID) {
752 scsi_dma_unmap(cmd);
753 sp->flags &= ~SRB_DMA_VALID;
754 }
755
756 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
757 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
758 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
759 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
760 }
761
d5ff0eed
JC		 762 if (!ctx)
763 goto end;
764
d7459527
MH		 765 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
766 /* List assured to be having elements */
d5ff0eed 767 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 768 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
769 }
770
771 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 772 struct crc_context *ctx0 = ctx;
773
774 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 775 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
776 }
777
778 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 779 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 780 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
781 ctx1->fcp_cmnd_dma);
782 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
783 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
784 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
785 mempool_free(ctx1, ha->ctx_mempool);
786 }
d5ff0eed 787end:
d7459527
MH		 788 CMD_SP(cmd) = NULL;
789 qla2xxx_rel_qpair_sp(sp->qpair, sp);
790}
791
792void
25ff6af1 793qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 794{
25ff6af1 795 srb_t *sp = ptr;
d7459527
MH		 796 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
797
798 cmd->result = res;
799
800 if (atomic_read(&sp->ref_count) == 0) {
801 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
802 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
803 sp, GET_CMD_SP(sp));
804 if (ql2xextended_error_logging & ql_dbg_io)
805 WARN_ON(atomic_read(&sp->ref_count) == 0);
806 return;
807 }
808 if (!atomic_dec_and_test(&sp->ref_count))
809 return;
810
25ff6af1 811 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 812 cmd->scsi_done(cmd);
813}
814
8ae6d9c7
GM		 815/* If we are SP1 here, we need to still take and release the host_lock as SP1
816 * does not have the changes necessary to avoid taking host->host_lock.
817 */
1da177e4 818static int
f5e3e40b 819qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 820{
134ae078 821 scsi_qla_host_t *vha = shost_priv(host);
fca29703 822 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 823 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 824 struct qla_hw_data *ha = vha->hw;
825 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 826 srb_t *sp;
827 int rval;
5601236b
MH		 828 struct qla_qpair *qpair = NULL;
829 uint32_t tag;
830 uint16_t hwq;
fca29703 831
04dfaa53
MFO		 832 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
833 cmd->result = DID_NO_CONNECT << 16;
834 goto qc24_fail_command;
835 }
836
5601236b
MH		 837 if (ha->mqenable) {
838 if (shost_use_blk_mq(vha->host)) {
839 tag = blk_mq_unique_tag(cmd->request);
840 hwq = blk_mq_unique_tag_to_hwq(tag);
841 qpair = ha->queue_pair_map[hwq];
842 } else if (vha->vp_idx && vha->qpair) {
843 qpair = vha->qpair;
844 }
845
846 if (qpair)
847 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 848 }
849
85880801 850 if (ha->flags.eeh_busy) {
7c3df132 851 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 852 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 853 "PCI Channel IO permanent failure, exiting "
854 "cmd=%p.\n", cmd);
b9b12f73 855 cmd->result = DID_NO_CONNECT << 16;
7c3df132 856 } else {
5f28d2d7 857 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 858 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 859 cmd->result = DID_REQUEUE << 16;
7c3df132 860 }
14e660e6
SJ		 861 goto qc24_fail_command;
862 }
863
19a7b4ae
JSEC		 864 rval = fc_remote_port_chkready(rport);
865 if (rval) {
866 cmd->result = rval;
5f28d2d7 867 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 868 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
869 cmd, rval);
fca29703
AV		 870 goto qc24_fail_command;
871 }
872
bad75002
AE		 873 if (!vha->flags.difdix_supported &&
874 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 875 ql_dbg(ql_dbg_io, vha, 0x3004,
876 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
877 cmd);
bad75002
AE		 878 cmd->result = DID_NO_CONNECT << 16;
879 goto qc24_fail_command;
880 }
aa651be8
CD		 881
882 if (!fcport) {
883 cmd->result = DID_NO_CONNECT << 16;
884 goto qc24_fail_command;
885 }
886
fca29703
AV		 887 if (atomic_read(&fcport->state) != FCS_ONLINE) {
888 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 889 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 890 ql_dbg(ql_dbg_io, vha, 0x3005,
891 "Returning DNC, fcport_state=%d loop_state=%d.\n",
892 atomic_read(&fcport->state),
893 atomic_read(&base_vha->loop_state));
fca29703
AV		 894 cmd->result = DID_NO_CONNECT << 16;
895 goto qc24_fail_command;
896 }
7b594131 897 goto qc24_target_busy;
fca29703
AV		 898 }
899
e05fe292
CD		 900 /*
901 * Return target busy if we've received a non-zero retry_delay_timer
902 * in a FCP_RSP.
903 */
975f7d46
BP		 904 if (fcport->retry_delay_timestamp == 0) {
905 /* retry delay not set */
906 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 907 fcport->retry_delay_timestamp = 0;
908 else
909 goto qc24_target_busy;
910
b00ee7d7 911 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 912 if (!sp)
f5e3e40b 913 goto qc24_host_busy;
fca29703 914
9ba56b95
GM		 915 sp->u.scmd.cmd = cmd;
916 sp->type = SRB_SCSI_CMD;
917 atomic_set(&sp->ref_count, 1);
918 CMD_SP(cmd) = (void *)sp;
919 sp->free = qla2x00_sp_free_dma;
920 sp->done = qla2x00_sp_compl;
921
e315cd28 922 rval = ha->isp_ops->start_scsi(sp);
7c3df132 923 if (rval != QLA_SUCCESS) {
53016ed3 924 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 925 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 926 goto qc24_host_busy_free_sp;
7c3df132 927 }
fca29703 928
fca29703
AV		 929 return 0;
930
931qc24_host_busy_free_sp:
25ff6af1 932 qla2x00_sp_free_dma(sp);
fca29703 933
f5e3e40b 934qc24_host_busy:
fca29703
AV		 935 return SCSI_MLQUEUE_HOST_BUSY;
936
7b594131
MC		 937qc24_target_busy:
938 return SCSI_MLQUEUE_TARGET_BUSY;
939
fca29703 940qc24_fail_command:
f5e3e40b 941 cmd->scsi_done(cmd);
fca29703
AV		 942
943 return 0;
944}
945
d7459527
MH		 946/* For MQ supported I/O */
947int
948qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
949 struct qla_qpair *qpair)
950{
951 scsi_qla_host_t *vha = shost_priv(host);
952 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
953 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
954 struct qla_hw_data *ha = vha->hw;
955 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
956 srb_t *sp;
957 int rval;
958
959 rval = fc_remote_port_chkready(rport);
960 if (rval) {
961 cmd->result = rval;
962 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
963 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
964 cmd, rval);
965 goto qc24_fail_command;
966 }
967
968 if (!fcport) {
969 cmd->result = DID_NO_CONNECT << 16;
970 goto qc24_fail_command;
971 }
972
973 if (atomic_read(&fcport->state) != FCS_ONLINE) {
974 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
975 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
976 ql_dbg(ql_dbg_io, vha, 0x3077,
977 "Returning DNC, fcport_state=%d loop_state=%d.\n",
978 atomic_read(&fcport->state),
979 atomic_read(&base_vha->loop_state));
980 cmd->result = DID_NO_CONNECT << 16;
981 goto qc24_fail_command;
982 }
983 goto qc24_target_busy;
984 }
985
986 /*
987 * Return target busy if we've received a non-zero retry_delay_timer
988 * in a FCP_RSP.
989 */
990 if (fcport->retry_delay_timestamp == 0) {
991 /* retry delay not set */
992 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
993 fcport->retry_delay_timestamp = 0;
994 else
995 goto qc24_target_busy;
996
997 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
998 if (!sp)
999 goto qc24_host_busy;
1000
1001 sp->u.scmd.cmd = cmd;
1002 sp->type = SRB_SCSI_CMD;
1003 atomic_set(&sp->ref_count, 1);
1004 CMD_SP(cmd) = (void *)sp;
1005 sp->free = qla2xxx_qpair_sp_free_dma;
1006 sp->done = qla2xxx_qpair_sp_compl;
1007 sp->qpair = qpair;
1008
1009 rval = ha->isp_ops->start_scsi_mq(sp);
1010 if (rval != QLA_SUCCESS) {
1011 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1012 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1013 if (rval == QLA_INTERFACE_ERROR)
1014 goto qc24_fail_command;
1015 goto qc24_host_busy_free_sp;
1016 }
1017
1018 return 0;
1019
1020qc24_host_busy_free_sp:
25ff6af1 1021 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 1022
1023qc24_host_busy:
1024 return SCSI_MLQUEUE_HOST_BUSY;
1025
1026qc24_target_busy:
1027 return SCSI_MLQUEUE_TARGET_BUSY;
1028
1029qc24_fail_command:
1030 cmd->scsi_done(cmd);
1031
1032 return 0;
1033}
1034
1da177e4
LT		 1035/*
1036 * qla2x00_eh_wait_on_command
1037 * Waits for the command to be returned by the Firmware for some
1038 * max time.
1039 *
1040 * Input:
1da177e4 1041 * cmd = Scsi Command to wait on.
1da177e4
LT		 1042 *
1043 * Return:
1044 * Not Found : 0
1045 * Found : 1
1046 */
1047static int
e315cd28 1048qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1049{
fe74c71f 1050#define ABORT_POLLING_PERIOD 1000
478c3b03 1051#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1052 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1053 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1054 struct qla_hw_data *ha = vha->hw;
f4f051eb 1055 int ret = QLA_SUCCESS;
1da177e4 1056
85880801 1057 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1058 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1059 "Return:eh_wait.\n");
85880801
AV		 1060 return ret;
1061 }
1062
d970432c 1063 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1064 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1065 }
1066 if (CMD_SP(cmd))
1067 ret = QLA_FUNCTION_FAILED;
1da177e4 1068
f4f051eb 1069 return ret;
1da177e4
LT		 1070}
1071
1072/*
1073 * qla2x00_wait_for_hba_online
fa2a1ce5 1074 * Wait till the HBA is online after going through
1da177e4
LT		 1075 * <= MAX_RETRIES_OF_ISP_ABORT or
1076 * finally HBA is disabled ie marked offline
1077 *
1078 * Input:
1079 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1080 *
1081 * Note:
1da177e4
LT		 1082 * Does context switching-Release SPIN_LOCK
1083 * (if any) before calling this routine.
1084 *
1085 * Return:
1086 * Success (Adapter is online) : 0
1087 * Failed (Adapter is offline/disabled) : 1
1088 */
854165f4 1089int
e315cd28 1090qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1091{
fca29703
AV		 1092 int return_status;
1093 unsigned long wait_online;
e315cd28
AC		 1094 struct qla_hw_data *ha = vha->hw;
1095 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1096
fa2a1ce5 1097 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1098 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1099 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1100 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1101 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1102
1103 msleep(1000);
1104 }
e315cd28 1105 if (base_vha->flags.online)
fa2a1ce5 1106 return_status = QLA_SUCCESS;
1da177e4
LT		 1107 else
1108 return_status = QLA_FUNCTION_FAILED;
1109
1da177e4
LT		 1110 return (return_status);
1111}
1112
726b8548
QT		 1113static inline int test_fcport_count(scsi_qla_host_t *vha)
1114{
1115 struct qla_hw_data *ha = vha->hw;
1116 unsigned long flags;
1117 int res;
1118
1119 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1120 ql_dbg(ql_dbg_init, vha, 0x00ec,
1121 "tgt %p, fcport_count=%d\n",
1122 vha, vha->fcport_count);
726b8548
QT		 1123 res = (vha->fcport_count == 0);
1124 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1125
1126 return res;
1127}
1128
1129/*
1130 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1131 * it has dependency on UNLOADING flag to stop device discovery
1132 */
1133static void
1134qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1135{
1136 qla2x00_mark_all_devices_lost(vha, 0);
1137
1138 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1139}
1140
86fbee86 1141/*
638a1a01
SC		 1142 * qla2x00_wait_for_hba_ready
1143 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1144 *
1145 * Input:
1146 * ha - pointer to host adapter structure
1147 *
1148 * Note:
1149 * Does context switching-Release SPIN_LOCK
1150 * (if any) before calling this routine.
1151 *
86fbee86 1152 */
638a1a01
SC		 1153static void
1154qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1155{
86fbee86 1156 struct qla_hw_data *ha = vha->hw;
783e0dc4 1157 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1158
1d483901
DC		 1159 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1160 ha->flags.mbox_busy) ||
1161 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1162 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1163 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1164 break;
86fbee86 1165 msleep(1000);
783e0dc4 1166 }
86fbee86
LC		 1167}
1168
2533cf67
LC		 1169int
1170qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1171{
1172 int return_status;
1173 unsigned long wait_reset;
1174 struct qla_hw_data *ha = vha->hw;
1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1176
1177 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1178 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1179 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1180 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1181 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1182
1183 msleep(1000);
1184
1185 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1186 ha->flags.chip_reset_done)
1187 break;
1188 }
1189 if (ha->flags.chip_reset_done)
1190 return_status = QLA_SUCCESS;
1191 else
1192 return_status = QLA_FUNCTION_FAILED;
1193
1194 return return_status;
1195}
1196
083a469d
GM		 1197static void
1198sp_get(struct srb *sp)
1199{
1200 atomic_inc(&sp->ref_count);
1201}
1202
a465537a
SC		 1203#define ISP_REG_DISCONNECT 0xffffffffU
1204/**************************************************************************
1205* qla2x00_isp_reg_stat
1206*
1207* Description:
1208* Read the host status register of ISP before aborting the command.
1209*
1210* Input:
1211* ha = pointer to host adapter structure.
1212*
1213*
1214* Returns:
1215* Either true or false.
1216*
1217* Note: Return true if there is register disconnect.
1218**************************************************************************/
1219static inline
1220uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1221{
1222 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1223 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1224
bf6061b1
SC		 1225 if (IS_P3P_TYPE(ha))
1226 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1227 else
1228 return ((RD_REG_DWORD(&reg->host_status)) ==
1229 ISP_REG_DISCONNECT);
a465537a
SC		 1230}
1231
1da177e4
LT		 1232/**************************************************************************
1233* qla2xxx_eh_abort
1234*
1235* Description:
1236* The abort function will abort the specified command.
1237*
1238* Input:
1239* cmd = Linux SCSI command packet to be aborted.
1240*
1241* Returns:
1242* Either SUCCESS or FAILED.
1243*
1244* Note:
2ea00202 1245* Only return FAILED if command not returned by firmware.
1da177e4 1246**************************************************************************/
e5f82ab8 1247static int
1da177e4
LT		 1248qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1249{
e315cd28 1250 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1251 srb_t *sp;
4e98d3b8 1252 int ret;
9cb78c16
HR		 1253 unsigned int id;
1254 uint64_t lun;
18e144d3 1255 unsigned long flags;
f934c9d0 1256 int rval, wait = 0;
e315cd28 1257 struct qla_hw_data *ha = vha->hw;
1da177e4 1258
a465537a
SC		 1259 if (qla2x00_isp_reg_stat(ha)) {
1260 ql_log(ql_log_info, vha, 0x8042,
1261 "PCI/Register disconnect, exiting.\n");
1262 return FAILED;
1263 }
f4f051eb 1264 if (!CMD_SP(cmd))
2ea00202 1265 return SUCCESS;
1da177e4 1266
4e98d3b8
AV		 1267 ret = fc_block_scsi_eh(cmd);
1268 if (ret != 0)
1269 return ret;
1270 ret = SUCCESS;
1271
f4f051eb
AV		 1272 id = cmd->device->id;
1273 lun = cmd->device->lun;
1da177e4 1274
e315cd28 1275 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1276 sp = (srb_t *) CMD_SP(cmd);
1277 if (!sp) {
1278 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1279 return SUCCESS;
1280 }
1da177e4 1281
7c3df132 1282 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1283 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1284 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1285
170babc3
MC		 1286 /* Get a reference to the sp and drop the lock.*/
1287 sp_get(sp);
083a469d 1288
e315cd28 1289 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1290 rval = ha->isp_ops->abort_command(sp);
1291 if (rval) {
96219424 1292 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1293 ret = SUCCESS;
96219424 1294 else
f934c9d0
CD		 1295 ret = FAILED;
1296
7c3df132 1297 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1298 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1299 } else {
7c3df132 1300 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1301 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1302 wait = 1;
1303 }
75942064
SK		 1304
1305 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1306 sp->done(sp, 0);
75942064 1307 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1308
bc91ade9
CD		 1309 /* Did the command return during mailbox execution? */
1310 if (ret == FAILED && !CMD_SP(cmd))
1311 ret = SUCCESS;
1312
f4f051eb 1313 /* Wait for the command to be returned. */
2ea00202 1314 if (wait) {
e315cd28 1315 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1316 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1317 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1318 ret = FAILED;
f4f051eb 1319 }
1da177e4 1320 }
1da177e4 1321
7c3df132 1322 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1323 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1324 vha->host_no, id, lun, wait, ret);
1da177e4 1325
f4f051eb
AV		 1326 return ret;
1327}
1da177e4 1328
4d78c973 1329int
e315cd28 1330qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1331 uint64_t l, enum nexus_wait_type type)
f4f051eb 1332{
17d98630 1333 int cnt, match, status;
18e144d3 1334 unsigned long flags;
e315cd28 1335 struct qla_hw_data *ha = vha->hw;
73208dfd 1336 struct req_que *req;
4d78c973 1337 srb_t *sp;
9ba56b95 1338 struct scsi_cmnd *cmd;
1da177e4 1339
523ec773 1340 status = QLA_SUCCESS;
17d98630 1341
e315cd28 1342 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1343 req = vha->req;
17d98630 1344 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1345 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1346 sp = req->outstanding_cmds[cnt];
1347 if (!sp)
523ec773 1348 continue;
9ba56b95 1349 if (sp->type != SRB_SCSI_CMD)
cf53b069 1350 continue;
25ff6af1 1351 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1352 continue;
1353 match = 0;
9ba56b95 1354 cmd = GET_CMD_SP(sp);
17d98630
AC		 1355 switch (type) {
1356 case WAIT_HOST:
1357 match = 1;
1358 break;
1359 case WAIT_TARGET:
9ba56b95 1360 match = cmd->device->id == t;
17d98630
AC		 1361 break;
1362 case WAIT_LUN:
9ba56b95
GM		 1363 match = (cmd->device->id == t &&
1364 cmd->device->lun == l);
17d98630 1365 break;
73208dfd 1366 }
17d98630
AC		 1367 if (!match)
1368 continue;
1369
1370 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1371 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1372 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1373 }
e315cd28 1374 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1375
1376 return status;
1da177e4
LT		 1377}
1378
523ec773
AV		 1379static char *reset_errors[] = {
1380 "HBA not online",
1381 "HBA not ready",
1382 "Task management failed",
1383 "Waiting for command completions",
1384};
1da177e4 1385
e5f82ab8 1386static int
523ec773 1387__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1388 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1389{
e315cd28 1390 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1391 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1392 int err;
1da177e4 1393
7c3df132 1394 if (!fcport) {
523ec773 1395 return FAILED;
7c3df132 1396 }
1da177e4 1397
4e98d3b8
AV		 1398 err = fc_block_scsi_eh(cmd);
1399 if (err != 0)
1400 return err;
1401
7c3df132 1402 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1403 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1404 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1405
523ec773 1406 err = 0;
7c3df132
SK		 1407 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1408 ql_log(ql_log_warn, vha, 0x800a,
1409 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1410 goto eh_reset_failed;
7c3df132 1411 }
523ec773 1412 err = 2;
2afa19a9 1413 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1414 != QLA_SUCCESS) {
1415 ql_log(ql_log_warn, vha, 0x800c,
1416 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1417 goto eh_reset_failed;
7c3df132 1418 }
523ec773 1419 err = 3;
e315cd28 1420 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1421 cmd->device->lun, type) != QLA_SUCCESS) {
1422 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1423 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1424 goto eh_reset_failed;
7c3df132 1425 }
523ec773 1426
7c3df132 1427 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1428 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1429 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1430
1431 return SUCCESS;
1432
4d78c973 1433eh_reset_failed:
7c3df132 1434 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1435 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1436 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1437 cmd);
523ec773
AV		 1438 return FAILED;
1439}
1da177e4 1440
523ec773
AV		 1441static int
1442qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1443{
e315cd28
AC		 1444 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1445 struct qla_hw_data *ha = vha->hw;
1da177e4 1446
a465537a
SC		 1447 if (qla2x00_isp_reg_stat(ha)) {
1448 ql_log(ql_log_info, vha, 0x803e,
1449 "PCI/Register disconnect, exiting.\n");
1450 return FAILED;
1451 }
1452
523ec773
AV		 1453 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1454 ha->isp_ops->lun_reset);
1da177e4
LT		 1455}
1456
1da177e4 1457static int
523ec773 1458qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1459{
e315cd28
AC		 1460 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1461 struct qla_hw_data *ha = vha->hw;
1da177e4 1462
a465537a
SC		 1463 if (qla2x00_isp_reg_stat(ha)) {
1464 ql_log(ql_log_info, vha, 0x803f,
1465 "PCI/Register disconnect, exiting.\n");
1466 return FAILED;
1467 }
1468
523ec773
AV		 1469 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1470 ha->isp_ops->target_reset);
1da177e4
LT		 1471}
1472
1da177e4
LT		 1473/**************************************************************************
1474* qla2xxx_eh_bus_reset
1475*
1476* Description:
1477* The bus reset function will reset the bus and abort any executing
1478* commands.
1479*
1480* Input:
1481* cmd = Linux SCSI command packet of the command that cause the
1482* bus reset.
1483*
1484* Returns:
1485* SUCCESS/FAILURE (defined as macro in scsi.h).
1486*
1487**************************************************************************/
e5f82ab8 1488static int
1da177e4
LT		 1489qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1490{
e315cd28 1491 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1492 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1493 int ret = FAILED;
9cb78c16
HR		 1494 unsigned int id;
1495 uint64_t lun;
a465537a
SC		 1496 struct qla_hw_data *ha = vha->hw;
1497
1498 if (qla2x00_isp_reg_stat(ha)) {
1499 ql_log(ql_log_info, vha, 0x8040,
1500 "PCI/Register disconnect, exiting.\n");
1501 return FAILED;
1502 }
f4f051eb 1503
f4f051eb
AV		 1504 id = cmd->device->id;
1505 lun = cmd->device->lun;
1da177e4 1506
7c3df132 1507 if (!fcport) {
f4f051eb 1508 return ret;
7c3df132 1509 }
1da177e4 1510
4e98d3b8
AV		 1511 ret = fc_block_scsi_eh(cmd);
1512 if (ret != 0)
1513 return ret;
1514 ret = FAILED;
1515
7c3df132 1516 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1517 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1518
e315cd28 1519 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1520 ql_log(ql_log_fatal, vha, 0x8013,
1521 "Wait for hba online failed board disabled.\n");
f4f051eb 1522 goto eh_bus_reset_done;
1da177e4
LT		 1523 }
1524
ad537689
SK		 1525 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1526 ret = SUCCESS;
1527
f4f051eb
AV		 1528 if (ret == FAILED)
1529 goto eh_bus_reset_done;
1da177e4 1530
9a41a62b 1531 /* Flush outstanding commands. */
4d78c973 1532 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1533 QLA_SUCCESS) {
1534 ql_log(ql_log_warn, vha, 0x8014,
1535 "Wait for pending commands failed.\n");
9a41a62b 1536 ret = FAILED;
7c3df132 1537 }
1da177e4 1538
f4f051eb 1539eh_bus_reset_done:
7c3df132 1540 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1541 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1542 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1543
f4f051eb 1544 return ret;
1da177e4
LT		 1545}
1546
1547/**************************************************************************
1548* qla2xxx_eh_host_reset
1549*
1550* Description:
1551* The reset function will reset the Adapter.
1552*
1553* Input:
1554* cmd = Linux SCSI command packet of the command that cause the
1555* adapter reset.
1556*
1557* Returns:
1558* Either SUCCESS or FAILED.
1559*
1560* Note:
1561**************************************************************************/
e5f82ab8 1562static int
1da177e4
LT		 1563qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1564{
e315cd28 1565 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1566 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1567 int ret = FAILED;
9cb78c16
HR		 1568 unsigned int id;
1569 uint64_t lun;
e315cd28 1570 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1571
a465537a
SC		 1572 if (qla2x00_isp_reg_stat(ha)) {
1573 ql_log(ql_log_info, vha, 0x8041,
1574 "PCI/Register disconnect, exiting.\n");
1575 schedule_work(&ha->board_disable);
1576 return SUCCESS;
1577 }
1578
f4f051eb
AV		 1579 id = cmd->device->id;
1580 lun = cmd->device->lun;
f4f051eb 1581
7c3df132 1582 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1583 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1584
63ee7072
CD		 1585 /*
1586 * No point in issuing another reset if one is active. Also do not
1587 * attempt a reset if we are updating flash.
1588 */
1589 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1590 goto eh_host_reset_lock;
1da177e4 1591
e315cd28
AC		 1592 if (vha != base_vha) {
1593 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1594 goto eh_host_reset_lock;
e315cd28 1595 } else {
7ec0effd 1596 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1597 if (!qla82xx_fcoe_ctx_reset(vha)) {
1598 /* Ctx reset success */
1599 ret = SUCCESS;
1600 goto eh_host_reset_lock;
1601 }
1602 /* fall thru if ctx reset failed */
1603 }
68ca949c
AC		 1604 if (ha->wq)
1605 flush_workqueue(ha->wq);
1606
e315cd28 1607 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1608 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1609 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1610 /* failed. schedule dpc to try */
1611 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1612
7c3df132
SK		 1613 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1614 ql_log(ql_log_warn, vha, 0x802a,
1615 "wait for hba online failed.\n");
e315cd28 1616 goto eh_host_reset_lock;
7c3df132 1617 }
e315cd28
AC		 1618 }
1619 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1620 }
1da177e4 1621
e315cd28 1622 /* Waiting for command to be returned to OS.*/
4d78c973 1623 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1624 QLA_SUCCESS)
f4f051eb 1625 ret = SUCCESS;
1da177e4 1626
f4f051eb 1627eh_host_reset_lock:
cfb0919c 1628 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1629 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1630 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1631
f4f051eb
AV		 1632 return ret;
1633}
1da177e4
LT		 1634
1635/*
1636* qla2x00_loop_reset
1637* Issue loop reset.
1638*
1639* Input:
1640* ha = adapter block pointer.
1641*
1642* Returns:
1643* 0 = success
1644*/
a4722cf2 1645int
e315cd28 1646qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1647{
0c8c39af 1648 int ret;
bdf79621 1649 struct fc_port *fcport;
e315cd28 1650 struct qla_hw_data *ha = vha->hw;
1da177e4 1651
5854771e
AB		 1652 if (IS_QLAFX00(ha)) {
1653 return qlafx00_loop_reset(vha);
1654 }
1655
f4c496c1 1656 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1657 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1658 if (fcport->port_type != FCT_TARGET)
1659 continue;
1660
1661 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1662 if (ret != QLA_SUCCESS) {
7c3df132 1663 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1664 "Bus Reset failed: Reset=%d "
7c3df132 1665 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1666 }
1667 }
1668 }
1669
8ae6d9c7 1670
6246b8a1 1671 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1672 atomic_set(&vha->loop_state, LOOP_DOWN);
1673 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1674 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1675 ret = qla2x00_full_login_lip(vha);
0c8c39af 1676 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1677 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1678 "full_login_lip=%d.\n", ret);
749af3d5 1679 }
0c8c39af
AV		 1680 }
1681
0d6e61bc 1682 if (ha->flags.enable_lip_reset) {
e315cd28 1683 ret = qla2x00_lip_reset(vha);
ad537689 1684 if (ret != QLA_SUCCESS)
7c3df132
SK		 1685 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1686 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1687 }
1688
1da177e4 1689 /* Issue marker command only when we are going to start the I/O */
e315cd28 1690 vha->marker_needed = 1;
1da177e4 1691
0c8c39af 1692 return QLA_SUCCESS;
1da177e4
LT		 1693}
1694
df4bf0bb 1695void
e315cd28 1696qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1697{
4cd3b6eb 1698 int que, cnt, status;
df4bf0bb
AV		 1699 unsigned long flags;
1700 srb_t *sp;
e315cd28 1701 struct qla_hw_data *ha = vha->hw;
73208dfd 1702 struct req_que *req;
c5419e26
QT		 1703 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1704 struct qla_tgt_cmd *cmd;
1705 uint8_t trace = 0;
c0cb4496 1706
df4bf0bb 1707 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1708 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1709 req = ha->req_q_map[que];
73208dfd
AC		 1710 if (!req)
1711 continue;
8d93f550
CD		 1712 if (!req->outstanding_cmds)
1713 continue;
1714 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1715 sp = req->outstanding_cmds[cnt];
e612d465 1716 if (sp) {
c5419e26
QT		 1717 req->outstanding_cmds[cnt] = NULL;
1718 if (sp->cmd_type == TYPE_SRB) {
6fcd98fd 1719 if (sp->type == SRB_NVME_CMD ||
1720 sp->type == SRB_NVME_LS) {
e84067d7
DG		 1721 sp_get(sp);
1722 spin_unlock_irqrestore(
1723 &ha->hardware_lock, flags);
1724 qla_nvme_abort(ha, sp);
1725 spin_lock_irqsave(
1726 &ha->hardware_lock, flags);
1727 } else if (GET_CMD_SP(sp) &&
c5419e26
QT		 1728 !ha->flags.eeh_busy &&
1729 (sp->type == SRB_SCSI_CMD)) {
1730 /*
e84067d7
DG		 1731 * Don't abort commands in
1732 * adapter during EEH
1733 * recovery as it's not
1734 * accessible/responding.
1735 *
c5419e26
QT		 1736 * Get a reference to the sp
1737 * and drop the lock. The
1738 * reference ensures this
1739 * sp->done() call and not the
1740 * call in qla2xxx_eh_abort()
1741 * ends the SCSI command (with
1742 * result 'res').
1743 */
1744 sp_get(sp);
1745 spin_unlock_irqrestore(
1746 &ha->hardware_lock, flags);
1747 status = qla2xxx_eh_abort(
1748 GET_CMD_SP(sp));
1749 spin_lock_irqsave(
1750 &ha->hardware_lock, flags);
1751 /*
1752 * Get rid of extra reference
1753 * if immediate exit from
1754 * ql2xxx_eh_abort
1755 */
1756 if (status == FAILED &&
1757 (qla2x00_isp_reg_stat(ha)))
1758 atomic_dec(
1759 &sp->ref_count);
1760 }
1761 sp->done(sp, res);
1762 } else {
1763 if (!vha->hw->tgt.tgt_ops || !tgt ||
1764 qla_ini_mode_enabled(vha)) {
1765 if (!trace)
1766 ql_dbg(ql_dbg_tgt_mgt,
1767 vha, 0xf003,
1768 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1769 vha->dpc_flags);
1770 continue;
1771 }
1772 cmd = (struct qla_tgt_cmd *)sp;
1773 qlt_abort_cmd_on_host_reset(cmd->vha,
1774 cmd);
c733ab35 1775 }
73208dfd 1776 }
df4bf0bb
AV		 1777 }
1778 }
1779 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1780}
1781
f4f051eb
AV		 1782static int
1783qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1784{
bdf79621 1785 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1786
19a7b4ae 1787 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1788 return -ENXIO;
bdf79621 1789
19a7b4ae 1790 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1791
f4f051eb
AV		 1792 return 0;
1793}
1da177e4 1794
f4f051eb
AV		 1795static int
1796qla2xxx_slave_configure(struct scsi_device *sdev)
1797{
e315cd28 1798 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1799 struct req_que *req = vha->req;
8482e118 1800
9e522cd8
AE		 1801 if (IS_T10_PI_CAPABLE(vha->hw))
1802 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1803
db5ed4df 1804 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1805 return 0;
1806}
1da177e4 1807
f4f051eb
AV		 1808static void
1809qla2xxx_slave_destroy(struct scsi_device *sdev)
1810{
1811 sdev->hostdata = NULL;
1da177e4
LT		 1812}
1813
1814/**
1815 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1816 * @ha: HA context
1817 *
1818 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1819 * supported addressing method.
1820 */
1821static void
53303c42 1822qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1823{
7524f9b9 1824 /* Assume a 32bit DMA mask. */
1da177e4 1825 ha->flags.enable_64bit_addressing = 0;
1da177e4 1826
6a35528a 1827 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1828 /* Any upper-dword bits set? */
1829 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1830 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1831 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1832 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1833 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1834 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1835 return;
1da177e4 1836 }
1da177e4 1837 }
7524f9b9 1838
284901a9
YH		 1839 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1840 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1841}
1842
fd34f556 1843static void
e315cd28 1844qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1845{
1846 unsigned long flags = 0;
1847 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1848
1849 spin_lock_irqsave(&ha->hardware_lock, flags);
1850 ha->interrupts_on = 1;
1851 /* enable risc and host interrupts */
1852 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1853 RD_REG_WORD(&reg->ictrl);
1854 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1855
1856}
1857
1858static void
e315cd28 1859qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1860{
1861 unsigned long flags = 0;
1862 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1863
1864 spin_lock_irqsave(&ha->hardware_lock, flags);
1865 ha->interrupts_on = 0;
1866 /* disable risc and host interrupts */
1867 WRT_REG_WORD(&reg->ictrl, 0);
1868 RD_REG_WORD(&reg->ictrl);
1869 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1870}
1871
1872static void
e315cd28 1873qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1874{
1875 unsigned long flags = 0;
1876 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1877
1878 spin_lock_irqsave(&ha->hardware_lock, flags);
1879 ha->interrupts_on = 1;
1880 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1881 RD_REG_DWORD(&reg->ictrl);
1882 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1883}
1884
1885static void
e315cd28 1886qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1887{
1888 unsigned long flags = 0;
1889 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1890
124f85e6
AV		 1891 if (IS_NOPOLLING_TYPE(ha))
1892 return;
fd34f556
AV		 1893 spin_lock_irqsave(&ha->hardware_lock, flags);
1894 ha->interrupts_on = 0;
1895 WRT_REG_DWORD(&reg->ictrl, 0);
1896 RD_REG_DWORD(&reg->ictrl);
1897 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1898}
1899
706f457d
GM		 1900static int
1901qla2x00_iospace_config(struct qla_hw_data *ha)
1902{
1903 resource_size_t pio;
1904 uint16_t msix;
706f457d 1905
706f457d
GM		 1906 if (pci_request_selected_regions(ha->pdev, ha->bars,
1907 QLA2XXX_DRIVER_NAME)) {
1908 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1909 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1910 pci_name(ha->pdev));
1911 goto iospace_error_exit;
1912 }
1913 if (!(ha->bars & 1))
1914 goto skip_pio;
1915
1916 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1917 pio = pci_resource_start(ha->pdev, 0);
1918 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1919 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1920 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1921 "Invalid pci I/O region size (%s).\n",
1922 pci_name(ha->pdev));
1923 pio = 0;
1924 }
1925 } else {
1926 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1927 "Region #0 no a PIO resource (%s).\n",
1928 pci_name(ha->pdev));
1929 pio = 0;
1930 }
1931 ha->pio_address = pio;
1932 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1933 "PIO address=%llu.\n",
1934 (unsigned long long)ha->pio_address);
1935
1936skip_pio:
1937 /* Use MMIO operations for all accesses. */
1938 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1939 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1940 "Region #1 not an MMIO resource (%s), aborting.\n",
1941 pci_name(ha->pdev));
1942 goto iospace_error_exit;
1943 }
1944 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1945 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1946 "Invalid PCI mem region size (%s), aborting.\n",
1947 pci_name(ha->pdev));
1948 goto iospace_error_exit;
1949 }
1950
1951 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1952 if (!ha->iobase) {
1953 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1954 "Cannot remap MMIO (%s), aborting.\n",
1955 pci_name(ha->pdev));
1956 goto iospace_error_exit;
1957 }
1958
1959 /* Determine queue resources */
1960 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1961 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1962 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1963 goto mqiobase_exit;
1964
1965 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1966 pci_resource_len(ha->pdev, 3));
1967 if (ha->mqiobase) {
1968 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1969 "MQIO Base=%p.\n", ha->mqiobase);
1970 /* Read MSIX vector size of the board */
1971 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1972 ha->msix_count = msix + 1;
706f457d 1973 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1974 /* MB interrupt uses 1 vector */
1975 ha->max_req_queues = ha->msix_count - 1;
1976 ha->max_rsp_queues = ha->max_req_queues;
1977 /* Queue pairs is the max value minus the base queue pair */
1978 ha->max_qpairs = ha->max_rsp_queues - 1;
1979 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1980 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1981
706f457d 1982 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1983 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1984 } else
1985 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1986 "BAR 3 not enabled.\n");
1987
1988mqiobase_exit:
706f457d 1989 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1990 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1991 return (0);
1992
1993iospace_error_exit:
1994 return (-ENOMEM);
1995}
1996
1997
6246b8a1
GM		 1998static int
1999qla83xx_iospace_config(struct qla_hw_data *ha)
2000{
2001 uint16_t msix;
6246b8a1
GM		 2002
2003 if (pci_request_selected_regions(ha->pdev, ha->bars,
2004 QLA2XXX_DRIVER_NAME)) {
2005 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2006 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2007 pci_name(ha->pdev));
2008
2009 goto iospace_error_exit;
2010 }
2011
2012 /* Use MMIO operations for all accesses. */
2013 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2014 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2015 "Invalid pci I/O region size (%s).\n",
2016 pci_name(ha->pdev));
2017 goto iospace_error_exit;
2018 }
2019 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2020 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2021 "Invalid PCI mem region size (%s), aborting\n",
2022 pci_name(ha->pdev));
2023 goto iospace_error_exit;
2024 }
2025
2026 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2027 if (!ha->iobase) {
2028 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2029 "Cannot remap MMIO (%s), aborting.\n",
2030 pci_name(ha->pdev));
2031 goto iospace_error_exit;
2032 }
2033
2034 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2035 /* 83XX 26XX always use MQ type access for queues
2036 * - mbar 2, a.k.a region 4 */
2037 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2038 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2039 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2040 pci_resource_len(ha->pdev, 4));
2041
2042 if (!ha->mqiobase) {
2043 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2044 "BAR2/region4 not enabled\n");
2045 goto mqiobase_exit;
2046 }
2047
2048 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2049 pci_resource_len(ha->pdev, 2));
2050 if (ha->msixbase) {
2051 /* Read MSIX vector size of the board */
2052 pci_read_config_word(ha->pdev,
2053 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2054 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2055 /*
2056 * By default, driver uses at least two msix vectors
2057 * (default & rspq)
2058 */
d7459527
MH		 2059 if (ql2xmqsupport) {
2060 /* MB interrupt uses 1 vector */
2061 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2062
2063 /* ATIOQ needs 1 vector. That's 1 less QPair */
2064 if (QLA_TGT_MODE_ENABLED())
2065 ha->max_req_queues--;
2066
d0d2c68b
MH		 2067 ha->max_rsp_queues = ha->max_req_queues;
2068
d7459527
MH		 2069 /* Queue pairs is the max value minus
2070 * the base queue pair */
2071 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2072 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2073 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2074 }
2075 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2076 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2077 } else
2078 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2079 "BAR 1 not enabled.\n");
2080
2081mqiobase_exit:
6246b8a1 2082 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2083 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2084 return 0;
2085
2086iospace_error_exit:
2087 return -ENOMEM;
2088}
2089
fd34f556
AV		 2090static struct isp_operations qla2100_isp_ops = {
2091 .pci_config = qla2100_pci_config,
2092 .reset_chip = qla2x00_reset_chip,
2093 .chip_diag = qla2x00_chip_diag,
2094 .config_rings = qla2x00_config_rings,
2095 .reset_adapter = qla2x00_reset_adapter,
2096 .nvram_config = qla2x00_nvram_config,
2097 .update_fw_options = qla2x00_update_fw_options,
2098 .load_risc = qla2x00_load_risc,
2099 .pci_info_str = qla2x00_pci_info_str,
2100 .fw_version_str = qla2x00_fw_version_str,
2101 .intr_handler = qla2100_intr_handler,
2102 .enable_intrs = qla2x00_enable_intrs,
2103 .disable_intrs = qla2x00_disable_intrs,
2104 .abort_command = qla2x00_abort_command,
523ec773
AV		 2105 .target_reset = qla2x00_abort_target,
2106 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2107 .fabric_login = qla2x00_login_fabric,
2108 .fabric_logout = qla2x00_fabric_logout,
2109 .calc_req_entries = qla2x00_calc_iocbs_32,
2110 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2111 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2112 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2113 .read_nvram = qla2x00_read_nvram_data,
2114 .write_nvram = qla2x00_write_nvram_data,
2115 .fw_dump = qla2100_fw_dump,
2116 .beacon_on = NULL,
2117 .beacon_off = NULL,
2118 .beacon_blink = NULL,
2119 .read_optrom = qla2x00_read_optrom_data,
2120 .write_optrom = qla2x00_write_optrom_data,
2121 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2122 .start_scsi = qla2x00_start_scsi,
d7459527 2123 .start_scsi_mq = NULL,
a9083016 2124 .abort_isp = qla2x00_abort_isp,
706f457d 2125 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2126 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2127};
2128
2129static struct isp_operations qla2300_isp_ops = {
2130 .pci_config = qla2300_pci_config,
2131 .reset_chip = qla2x00_reset_chip,
2132 .chip_diag = qla2x00_chip_diag,
2133 .config_rings = qla2x00_config_rings,
2134 .reset_adapter = qla2x00_reset_adapter,
2135 .nvram_config = qla2x00_nvram_config,
2136 .update_fw_options = qla2x00_update_fw_options,
2137 .load_risc = qla2x00_load_risc,
2138 .pci_info_str = qla2x00_pci_info_str,
2139 .fw_version_str = qla2x00_fw_version_str,
2140 .intr_handler = qla2300_intr_handler,
2141 .enable_intrs = qla2x00_enable_intrs,
2142 .disable_intrs = qla2x00_disable_intrs,
2143 .abort_command = qla2x00_abort_command,
523ec773
AV		 2144 .target_reset = qla2x00_abort_target,
2145 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2146 .fabric_login = qla2x00_login_fabric,
2147 .fabric_logout = qla2x00_fabric_logout,
2148 .calc_req_entries = qla2x00_calc_iocbs_32,
2149 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2150 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2151 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2152 .read_nvram = qla2x00_read_nvram_data,
2153 .write_nvram = qla2x00_write_nvram_data,
2154 .fw_dump = qla2300_fw_dump,
2155 .beacon_on = qla2x00_beacon_on,
2156 .beacon_off = qla2x00_beacon_off,
2157 .beacon_blink = qla2x00_beacon_blink,
2158 .read_optrom = qla2x00_read_optrom_data,
2159 .write_optrom = qla2x00_write_optrom_data,
2160 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2161 .start_scsi = qla2x00_start_scsi,
d7459527 2162 .start_scsi_mq = NULL,
a9083016 2163 .abort_isp = qla2x00_abort_isp,
7ec0effd 2164 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2165 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2166};
2167
2168static struct isp_operations qla24xx_isp_ops = {
2169 .pci_config = qla24xx_pci_config,
2170 .reset_chip = qla24xx_reset_chip,
2171 .chip_diag = qla24xx_chip_diag,
2172 .config_rings = qla24xx_config_rings,
2173 .reset_adapter = qla24xx_reset_adapter,
2174 .nvram_config = qla24xx_nvram_config,
2175 .update_fw_options = qla24xx_update_fw_options,
2176 .load_risc = qla24xx_load_risc,
2177 .pci_info_str = qla24xx_pci_info_str,
2178 .fw_version_str = qla24xx_fw_version_str,
2179 .intr_handler = qla24xx_intr_handler,
2180 .enable_intrs = qla24xx_enable_intrs,
2181 .disable_intrs = qla24xx_disable_intrs,
2182 .abort_command = qla24xx_abort_command,
523ec773
AV		 2183 .target_reset = qla24xx_abort_target,
2184 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2185 .fabric_login = qla24xx_login_fabric,
2186 .fabric_logout = qla24xx_fabric_logout,
2187 .calc_req_entries = NULL,
2188 .build_iocbs = NULL,
2189 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2190 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2191 .read_nvram = qla24xx_read_nvram_data,
2192 .write_nvram = qla24xx_write_nvram_data,
2193 .fw_dump = qla24xx_fw_dump,
2194 .beacon_on = qla24xx_beacon_on,
2195 .beacon_off = qla24xx_beacon_off,
2196 .beacon_blink = qla24xx_beacon_blink,
2197 .read_optrom = qla24xx_read_optrom_data,
2198 .write_optrom = qla24xx_write_optrom_data,
2199 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2200 .start_scsi = qla24xx_start_scsi,
d7459527 2201 .start_scsi_mq = NULL,
a9083016 2202 .abort_isp = qla2x00_abort_isp,
7ec0effd 2203 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2204 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2205};
2206
c3a2f0df
AV		 2207static struct isp_operations qla25xx_isp_ops = {
2208 .pci_config = qla25xx_pci_config,
2209 .reset_chip = qla24xx_reset_chip,
2210 .chip_diag = qla24xx_chip_diag,
2211 .config_rings = qla24xx_config_rings,
2212 .reset_adapter = qla24xx_reset_adapter,
2213 .nvram_config = qla24xx_nvram_config,
2214 .update_fw_options = qla24xx_update_fw_options,
2215 .load_risc = qla24xx_load_risc,
2216 .pci_info_str = qla24xx_pci_info_str,
2217 .fw_version_str = qla24xx_fw_version_str,
2218 .intr_handler = qla24xx_intr_handler,
2219 .enable_intrs = qla24xx_enable_intrs,
2220 .disable_intrs = qla24xx_disable_intrs,
2221 .abort_command = qla24xx_abort_command,
523ec773
AV		 2222 .target_reset = qla24xx_abort_target,
2223 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2224 .fabric_login = qla24xx_login_fabric,
2225 .fabric_logout = qla24xx_fabric_logout,
2226 .calc_req_entries = NULL,
2227 .build_iocbs = NULL,
2228 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2229 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2230 .read_nvram = qla25xx_read_nvram_data,
2231 .write_nvram = qla25xx_write_nvram_data,
2232 .fw_dump = qla25xx_fw_dump,
2233 .beacon_on = qla24xx_beacon_on,
2234 .beacon_off = qla24xx_beacon_off,
2235 .beacon_blink = qla24xx_beacon_blink,
338c9161 2236 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2237 .write_optrom = qla24xx_write_optrom_data,
2238 .get_flash_version = qla24xx_get_flash_version,
bad75002 2239 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2240 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2241 .abort_isp = qla2x00_abort_isp,
7ec0effd 2242 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2243 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2244};
2245
3a03eb79
AV		 2246static struct isp_operations qla81xx_isp_ops = {
2247 .pci_config = qla25xx_pci_config,
2248 .reset_chip = qla24xx_reset_chip,
2249 .chip_diag = qla24xx_chip_diag,
2250 .config_rings = qla24xx_config_rings,
2251 .reset_adapter = qla24xx_reset_adapter,
2252 .nvram_config = qla81xx_nvram_config,
2253 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2254 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2255 .pci_info_str = qla24xx_pci_info_str,
2256 .fw_version_str = qla24xx_fw_version_str,
2257 .intr_handler = qla24xx_intr_handler,
2258 .enable_intrs = qla24xx_enable_intrs,
2259 .disable_intrs = qla24xx_disable_intrs,
2260 .abort_command = qla24xx_abort_command,
2261 .target_reset = qla24xx_abort_target,
2262 .lun_reset = qla24xx_lun_reset,
2263 .fabric_login = qla24xx_login_fabric,
2264 .fabric_logout = qla24xx_fabric_logout,
2265 .calc_req_entries = NULL,
2266 .build_iocbs = NULL,
2267 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2268 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2269 .read_nvram = NULL,
2270 .write_nvram = NULL,
3a03eb79
AV		 2271 .fw_dump = qla81xx_fw_dump,
2272 .beacon_on = qla24xx_beacon_on,
2273 .beacon_off = qla24xx_beacon_off,
6246b8a1 2274 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2275 .read_optrom = qla25xx_read_optrom_data,
2276 .write_optrom = qla24xx_write_optrom_data,
2277 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2278 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2279 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2280 .abort_isp = qla2x00_abort_isp,
7ec0effd 2281 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2282 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2283};
2284
2285static struct isp_operations qla82xx_isp_ops = {
2286 .pci_config = qla82xx_pci_config,
2287 .reset_chip = qla82xx_reset_chip,
2288 .chip_diag = qla24xx_chip_diag,
2289 .config_rings = qla82xx_config_rings,
2290 .reset_adapter = qla24xx_reset_adapter,
2291 .nvram_config = qla81xx_nvram_config,
2292 .update_fw_options = qla24xx_update_fw_options,
2293 .load_risc = qla82xx_load_risc,
9d55ca66 2294 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2295 .fw_version_str = qla24xx_fw_version_str,
2296 .intr_handler = qla82xx_intr_handler,
2297 .enable_intrs = qla82xx_enable_intrs,
2298 .disable_intrs = qla82xx_disable_intrs,
2299 .abort_command = qla24xx_abort_command,
2300 .target_reset = qla24xx_abort_target,
2301 .lun_reset = qla24xx_lun_reset,
2302 .fabric_login = qla24xx_login_fabric,
2303 .fabric_logout = qla24xx_fabric_logout,
2304 .calc_req_entries = NULL,
2305 .build_iocbs = NULL,
2306 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2307 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2308 .read_nvram = qla24xx_read_nvram_data,
2309 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2310 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2311 .beacon_on = qla82xx_beacon_on,
2312 .beacon_off = qla82xx_beacon_off,
2313 .beacon_blink = NULL,
a9083016
GM		 2314 .read_optrom = qla82xx_read_optrom_data,
2315 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2316 .get_flash_version = qla82xx_get_flash_version,
a9083016 2317 .start_scsi = qla82xx_start_scsi,
d7459527 2318 .start_scsi_mq = NULL,
a9083016 2319 .abort_isp = qla82xx_abort_isp,
706f457d 2320 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2321 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2322};
2323
7ec0effd
AD		 2324static struct isp_operations qla8044_isp_ops = {
2325 .pci_config = qla82xx_pci_config,
2326 .reset_chip = qla82xx_reset_chip,
2327 .chip_diag = qla24xx_chip_diag,
2328 .config_rings = qla82xx_config_rings,
2329 .reset_adapter = qla24xx_reset_adapter,
2330 .nvram_config = qla81xx_nvram_config,
2331 .update_fw_options = qla24xx_update_fw_options,
2332 .load_risc = qla82xx_load_risc,
2333 .pci_info_str = qla24xx_pci_info_str,
2334 .fw_version_str = qla24xx_fw_version_str,
2335 .intr_handler = qla8044_intr_handler,
2336 .enable_intrs = qla82xx_enable_intrs,
2337 .disable_intrs = qla82xx_disable_intrs,
2338 .abort_command = qla24xx_abort_command,
2339 .target_reset = qla24xx_abort_target,
2340 .lun_reset = qla24xx_lun_reset,
2341 .fabric_login = qla24xx_login_fabric,
2342 .fabric_logout = qla24xx_fabric_logout,
2343 .calc_req_entries = NULL,
2344 .build_iocbs = NULL,
2345 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2346 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2347 .read_nvram = NULL,
2348 .write_nvram = NULL,
a1b23c5a 2349 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2350 .beacon_on = qla82xx_beacon_on,
2351 .beacon_off = qla82xx_beacon_off,
2352 .beacon_blink = NULL,
888e639d 2353 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2354 .write_optrom = qla8044_write_optrom_data,
2355 .get_flash_version = qla82xx_get_flash_version,
2356 .start_scsi = qla82xx_start_scsi,
d7459527 2357 .start_scsi_mq = NULL,
7ec0effd
AD		 2358 .abort_isp = qla8044_abort_isp,
2359 .iospace_config = qla82xx_iospace_config,
2360 .initialize_adapter = qla2x00_initialize_adapter,
2361};
2362
6246b8a1
GM		 2363static struct isp_operations qla83xx_isp_ops = {
2364 .pci_config = qla25xx_pci_config,
2365 .reset_chip = qla24xx_reset_chip,
2366 .chip_diag = qla24xx_chip_diag,
2367 .config_rings = qla24xx_config_rings,
2368 .reset_adapter = qla24xx_reset_adapter,
2369 .nvram_config = qla81xx_nvram_config,
2370 .update_fw_options = qla81xx_update_fw_options,
2371 .load_risc = qla81xx_load_risc,
2372 .pci_info_str = qla24xx_pci_info_str,
2373 .fw_version_str = qla24xx_fw_version_str,
2374 .intr_handler = qla24xx_intr_handler,
2375 .enable_intrs = qla24xx_enable_intrs,
2376 .disable_intrs = qla24xx_disable_intrs,
2377 .abort_command = qla24xx_abort_command,
2378 .target_reset = qla24xx_abort_target,
2379 .lun_reset = qla24xx_lun_reset,
2380 .fabric_login = qla24xx_login_fabric,
2381 .fabric_logout = qla24xx_fabric_logout,
2382 .calc_req_entries = NULL,
2383 .build_iocbs = NULL,
2384 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2385 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2386 .read_nvram = NULL,
2387 .write_nvram = NULL,
2388 .fw_dump = qla83xx_fw_dump,
2389 .beacon_on = qla24xx_beacon_on,
2390 .beacon_off = qla24xx_beacon_off,
2391 .beacon_blink = qla83xx_beacon_blink,
2392 .read_optrom = qla25xx_read_optrom_data,
2393 .write_optrom = qla24xx_write_optrom_data,
2394 .get_flash_version = qla24xx_get_flash_version,
2395 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2396 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2397 .abort_isp = qla2x00_abort_isp,
2398 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2399 .initialize_adapter = qla2x00_initialize_adapter,
2400};
2401
2402static struct isp_operations qlafx00_isp_ops = {
2403 .pci_config = qlafx00_pci_config,
2404 .reset_chip = qlafx00_soft_reset,
2405 .chip_diag = qlafx00_chip_diag,
2406 .config_rings = qlafx00_config_rings,
2407 .reset_adapter = qlafx00_soft_reset,
2408 .nvram_config = NULL,
2409 .update_fw_options = NULL,
2410 .load_risc = NULL,
2411 .pci_info_str = qlafx00_pci_info_str,
2412 .fw_version_str = qlafx00_fw_version_str,
2413 .intr_handler = qlafx00_intr_handler,
2414 .enable_intrs = qlafx00_enable_intrs,
2415 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2416 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2417 .target_reset = qlafx00_abort_target,
2418 .lun_reset = qlafx00_lun_reset,
2419 .fabric_login = NULL,
2420 .fabric_logout = NULL,
2421 .calc_req_entries = NULL,
2422 .build_iocbs = NULL,
2423 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2424 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2425 .read_nvram = qla24xx_read_nvram_data,
2426 .write_nvram = qla24xx_write_nvram_data,
2427 .fw_dump = NULL,
2428 .beacon_on = qla24xx_beacon_on,
2429 .beacon_off = qla24xx_beacon_off,
2430 .beacon_blink = NULL,
2431 .read_optrom = qla24xx_read_optrom_data,
2432 .write_optrom = qla24xx_write_optrom_data,
2433 .get_flash_version = qla24xx_get_flash_version,
2434 .start_scsi = qlafx00_start_scsi,
d7459527 2435 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2436 .abort_isp = qlafx00_abort_isp,
2437 .iospace_config = qlafx00_iospace_config,
2438 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2439};
2440
f73cb695
CD		 2441static struct isp_operations qla27xx_isp_ops = {
2442 .pci_config = qla25xx_pci_config,
2443 .reset_chip = qla24xx_reset_chip,
2444 .chip_diag = qla24xx_chip_diag,
2445 .config_rings = qla24xx_config_rings,
2446 .reset_adapter = qla24xx_reset_adapter,
2447 .nvram_config = qla81xx_nvram_config,
2448 .update_fw_options = qla81xx_update_fw_options,
2449 .load_risc = qla81xx_load_risc,
2450 .pci_info_str = qla24xx_pci_info_str,
2451 .fw_version_str = qla24xx_fw_version_str,
2452 .intr_handler = qla24xx_intr_handler,
2453 .enable_intrs = qla24xx_enable_intrs,
2454 .disable_intrs = qla24xx_disable_intrs,
2455 .abort_command = qla24xx_abort_command,
2456 .target_reset = qla24xx_abort_target,
2457 .lun_reset = qla24xx_lun_reset,
2458 .fabric_login = qla24xx_login_fabric,
2459 .fabric_logout = qla24xx_fabric_logout,
2460 .calc_req_entries = NULL,
2461 .build_iocbs = NULL,
2462 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2463 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2464 .read_nvram = NULL,
2465 .write_nvram = NULL,
2466 .fw_dump = qla27xx_fwdump,
2467 .beacon_on = qla24xx_beacon_on,
2468 .beacon_off = qla24xx_beacon_off,
2469 .beacon_blink = qla83xx_beacon_blink,
2470 .read_optrom = qla25xx_read_optrom_data,
2471 .write_optrom = qla24xx_write_optrom_data,
2472 .get_flash_version = qla24xx_get_flash_version,
2473 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2474 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2475 .abort_isp = qla2x00_abort_isp,
2476 .iospace_config = qla83xx_iospace_config,
2477 .initialize_adapter = qla2x00_initialize_adapter,
2478};
2479
ea5b6382 2480static inline void
e315cd28 2481qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2482{
2483 ha->device_type = DT_EXTENDED_IDS;
2484 switch (ha->pdev->device) {
2485 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2486 ha->isp_type |= DT_ISP2100;
ea5b6382 2487 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2488 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2489 break;
2490 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2491 ha->isp_type |= DT_ISP2200;
ea5b6382 2492 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2493 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2494 break;
2495 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2496 ha->isp_type |= DT_ISP2300;
4a59f71d 2497 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2498 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2499 break;
2500 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2501 ha->isp_type |= DT_ISP2312;
4a59f71d 2502 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2503 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2504 break;
2505 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2506 ha->isp_type |= DT_ISP2322;
4a59f71d 2507 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2508 if (ha->pdev->subsystem_vendor == 0x1028 &&
2509 ha->pdev->subsystem_device == 0x0170)
2510 ha->device_type |= DT_OEM_001;
441d1072 2511 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2512 break;
2513 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2514 ha->isp_type |= DT_ISP6312;
441d1072 2515 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2516 break;
2517 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2518 ha->isp_type |= DT_ISP6322;
441d1072 2519 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2520 break;
2521 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2522 ha->isp_type |= DT_ISP2422;
4a59f71d 2523 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2524 ha->device_type |= DT_FWI2;
c76f2c01 2525 ha->device_type |= DT_IIDMA;
441d1072 2526 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2527 break;
2528 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2529 ha->isp_type |= DT_ISP2432;
4a59f71d 2530 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2531 ha->device_type |= DT_FWI2;
c76f2c01 2532 ha->device_type |= DT_IIDMA;
441d1072 2533 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2534 break;
4d4df193 2535 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2536 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2537 ha->device_type |= DT_ZIO_SUPPORTED;
2538 ha->device_type |= DT_FWI2;
2539 ha->device_type |= DT_IIDMA;
2540 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2541 break;
044cc6c8 2542 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2543 ha->isp_type |= DT_ISP5422;
e428924c 2544 ha->device_type |= DT_FWI2;
441d1072 2545 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2546 break;
044cc6c8 2547 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2548 ha->isp_type |= DT_ISP5432;
e428924c 2549 ha->device_type |= DT_FWI2;
441d1072 2550 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2551 break;
c3a2f0df 2552 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2553 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2554 ha->device_type |= DT_ZIO_SUPPORTED;
2555 ha->device_type |= DT_FWI2;
2556 ha->device_type |= DT_IIDMA;
441d1072 2557 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2558 break;
3a03eb79 2559 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2560 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2561 ha->device_type |= DT_ZIO_SUPPORTED;
2562 ha->device_type |= DT_FWI2;
2563 ha->device_type |= DT_IIDMA;
2564 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2565 break;
a9083016 2566 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2567 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2568 ha->device_type |= DT_ZIO_SUPPORTED;
2569 ha->device_type |= DT_FWI2;
2570 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2571 /* Initialize 82XX ISP flags */
2572 qla82xx_init_flags(ha);
2573 break;
7ec0effd 2574 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2575 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2576 ha->device_type |= DT_ZIO_SUPPORTED;
2577 ha->device_type |= DT_FWI2;
2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2579 /* Initialize 82XX ISP flags */
2580 qla82xx_init_flags(ha);
2581 break;
6246b8a1 2582 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2583 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2584 ha->device_type |= DT_ZIO_SUPPORTED;
2585 ha->device_type |= DT_FWI2;
2586 ha->device_type |= DT_IIDMA;
2587 ha->device_type |= DT_T10_PI;
2588 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2589 break;
2590 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2591 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2592 ha->device_type |= DT_ZIO_SUPPORTED;
2593 ha->device_type |= DT_FWI2;
2594 ha->device_type |= DT_IIDMA;
2595 ha->device_type |= DT_T10_PI;
2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2597 break;
8ae6d9c7 2598 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2599 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2600 break;
f73cb695 2601 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2602 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2603 ha->device_type |= DT_ZIO_SUPPORTED;
2604 ha->device_type |= DT_FWI2;
2605 ha->device_type |= DT_IIDMA;
8ce3f570 2606 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2607 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2608 break;
2c5bbbb2 2609 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2610 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2611 ha->device_type |= DT_ZIO_SUPPORTED;
2612 ha->device_type |= DT_FWI2;
2613 ha->device_type |= DT_IIDMA;
8ce3f570 2614 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2615 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2616 break;
2b48992f 2617 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2618 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2619 ha->device_type |= DT_ZIO_SUPPORTED;
2620 ha->device_type |= DT_FWI2;
2621 ha->device_type |= DT_IIDMA;
8ce3f570 2622 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2623 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2624 break;
ea5b6382 2625 }
e5b68a61 2626
a9083016 2627 if (IS_QLA82XX(ha))
43a9c38b 2628 ha->port_no = ha->portnum & 1;
f73cb695 2629 else {
a9083016
GM		 2630 /* Get adapter physical port no from interrupt pin register. */
2631 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2632 if (IS_QLA27XX(ha))
2633 ha->port_no--;
2634 else
2635 ha->port_no = !(ha->port_no & 1);
2636 }
a9083016 2637
7c3df132 2638 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2639 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2640 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2641}
2642
1e99e33a
AV		 2643static void
2644qla2xxx_scan_start(struct Scsi_Host *shost)
2645{
e315cd28 2646 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2647
cbc8eb67
AV		 2648 if (vha->hw->flags.running_gold_fw)
2649 return;
2650
e315cd28
AC		 2651 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2652 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2653 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2654 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2655}
2656
2657static int
2658qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2659{
e315cd28 2660 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2661
a5dd506e
BK		 2662 if (test_bit(UNLOADING, &vha->dpc_flags))
2663 return 1;
e315cd28 2664 if (!vha->host)
1e99e33a 2665 return 1;
e315cd28 2666 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2667 return 1;
2668
e315cd28 2669 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2670}
2671
ec7193e2
QT		 2672static void qla2x00_iocb_work_fn(struct work_struct *work)
2673{
2674 struct scsi_qla_host *vha = container_of(work,
2675 struct scsi_qla_host, iocb_work);
2676 int cnt = 0;
2677
2678 while (!list_empty(&vha->work_list)) {
2679 qla2x00_do_work(vha);
2680 cnt++;
2681 if (cnt > 10)
2682 break;
2683 }
2684}
2685
1da177e4
LT		 2686/*
2687 * PCI driver interface
2688 */
6f039790 2689static int
7ee61397 2690qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2691{
a1541d5a 2692 int ret = -ENODEV;
1da177e4 2693 struct Scsi_Host *host;
e315cd28
AC		 2694 scsi_qla_host_t *base_vha = NULL;
2695 struct qla_hw_data *ha;
29856e28 2696 char pci_info[30];
7d613ac6 2697 char fw_str[30], wq_name[30];
5433383e 2698 struct scsi_host_template *sht;
642ef983 2699 int bars, mem_only = 0;
e315cd28 2700 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2701 struct req_que *req = NULL;
2702 struct rsp_que *rsp = NULL;
5601236b 2703 int i;
d7459527 2704
285d0321 2705 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2706 sht = &qla2xxx_driver_template;
5433383e 2707 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2708 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2709 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2710 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2711 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2712 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2713 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2714 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2715 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2716 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2717 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2718 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2719 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2720 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2721 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2722 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2723 mem_only = 1;
7c3df132
SK		 2724 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2725 "Mem only adapter.\n");
285d0321 2726 }
7c3df132
SK		 2727 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2728 "Bars=%d.\n", bars);
285d0321 2729
09483916
BH		 2730 if (mem_only) {
2731 if (pci_enable_device_mem(pdev))
ddff7ed4 2732 return ret;
09483916
BH		 2733 } else {
2734 if (pci_enable_device(pdev))
ddff7ed4 2735 return ret;
09483916 2736 }
285d0321 2737
0927678f
JB		 2738 /* This may fail but that's ok */
2739 pci_enable_pcie_error_reporting(pdev);
285d0321 2740
e315cd28
AC		 2741 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2742 if (!ha) {
7c3df132
SK		 2743 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2744 "Unable to allocate memory for ha.\n");
ddff7ed4 2745 goto disable_device;
1da177e4 2746 }
7c3df132
SK		 2747 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2748 "Memory allocated for ha=%p.\n", ha);
e315cd28 2749 ha->pdev = pdev;
33e79977
QT		 2750 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2751 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2752 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2753 spin_lock_init(&ha->tgt.atio_lock);
2754
deeae7a6 2755 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2756
2757 /* Clear our data area */
285d0321 2758 ha->bars = bars;
09483916 2759 ha->mem_only = mem_only;
df4bf0bb 2760 spin_lock_init(&ha->hardware_lock);
339aa70e 2761 spin_lock_init(&ha->vport_slock);
a9b6f722 2762 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2763 mutex_init(&ha->optrom_mutex);
1da177e4 2764
ea5b6382
AV		 2765 /* Set ISP-type information. */
2766 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2767
2768 /* Set EEH reset type to fundamental if required by hba */
95676112 2769 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2770 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2771 pdev->needs_freset = 1;
ca79cf66 2772
cba1e47f
CD		 2773 ha->prev_topology = 0;
2774 ha->init_cb_size = sizeof(init_cb_t);
2775 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2776 ha->optrom_size = OPTROM_SIZE_2300;
2777
abbd8870 2778 /* Assign ISP specific operations. */
1da177e4 2779 if (IS_QLA2100(ha)) {
642ef983 2780 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2781 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2782 req_length = REQUEST_ENTRY_CNT_2100;
2783 rsp_length = RESPONSE_ENTRY_CNT_2100;
2784 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2785 ha->gid_list_info_size = 4;
3a03eb79
AV		 2786 ha->flash_conf_off = ~0;
2787 ha->flash_data_off = ~0;
2788 ha->nvram_conf_off = ~0;
2789 ha->nvram_data_off = ~0;
fd34f556 2790 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2791 } else if (IS_QLA2200(ha)) {
642ef983 2792 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2793 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2794 req_length = REQUEST_ENTRY_CNT_2200;
2795 rsp_length = RESPONSE_ENTRY_CNT_2100;
2796 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2797 ha->gid_list_info_size = 4;
3a03eb79
AV		 2798 ha->flash_conf_off = ~0;
2799 ha->flash_data_off = ~0;
2800 ha->nvram_conf_off = ~0;
2801 ha->nvram_data_off = ~0;
fd34f556 2802 ha->isp_ops = &qla2100_isp_ops;
fca29703 2803 } else if (IS_QLA23XX(ha)) {
642ef983 2804 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2805 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2806 req_length = REQUEST_ENTRY_CNT_2200;
2807 rsp_length = RESPONSE_ENTRY_CNT_2300;
2808 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2809 ha->gid_list_info_size = 6;
854165f4
AV		 2810 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2811 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2812 ha->flash_conf_off = ~0;
2813 ha->flash_data_off = ~0;
2814 ha->nvram_conf_off = ~0;
2815 ha->nvram_data_off = ~0;
fd34f556 2816 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2817 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2818 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2819 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2820 req_length = REQUEST_ENTRY_CNT_24XX;
2821 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2822 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2823 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2824 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2825 ha->gid_list_info_size = 8;
854165f4 2826 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2827 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2828 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2829 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2830 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2831 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2832 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2833 } else if (IS_QLA25XX(ha)) {
642ef983 2834 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2835 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2836 req_length = REQUEST_ENTRY_CNT_24XX;
2837 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2838 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2839 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2840 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2841 ha->gid_list_info_size = 8;
2842 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2843 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2844 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2845 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2846 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2847 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2848 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2849 } else if (IS_QLA81XX(ha)) {
642ef983 2850 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2851 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2852 req_length = REQUEST_ENTRY_CNT_24XX;
2853 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2854 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2855 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2856 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2857 ha->gid_list_info_size = 8;
2858 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2859 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2860 ha->isp_ops = &qla81xx_isp_ops;
2861 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2862 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2863 ha->nvram_conf_off = ~0;
2864 ha->nvram_data_off = ~0;
a9083016 2865 } else if (IS_QLA82XX(ha)) {
642ef983 2866 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2867 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2868 req_length = REQUEST_ENTRY_CNT_82XX;
2869 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2870 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2871 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2872 ha->gid_list_info_size = 8;
2873 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2874 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2875 ha->isp_ops = &qla82xx_isp_ops;
2876 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2877 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2878 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2879 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2880 } else if (IS_QLA8044(ha)) {
2881 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2882 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2883 req_length = REQUEST_ENTRY_CNT_82XX;
2884 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2885 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2886 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2887 ha->gid_list_info_size = 8;
2888 ha->optrom_size = OPTROM_SIZE_83XX;
2889 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2890 ha->isp_ops = &qla8044_isp_ops;
2891 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2892 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2893 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2894 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2895 } else if (IS_QLA83XX(ha)) {
7d613ac6 2896 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2897 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2898 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2899 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2900 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2901 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2902 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2903 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2904 ha->gid_list_info_size = 8;
2905 ha->optrom_size = OPTROM_SIZE_83XX;
2906 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2907 ha->isp_ops = &qla83xx_isp_ops;
2908 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2909 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2910 ha->nvram_conf_off = ~0;
2911 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2912 } else if (IS_QLAFX00(ha)) {
2913 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2914 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2915 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2916 req_length = REQUEST_ENTRY_CNT_FX00;
2917 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2918 ha->isp_ops = &qlafx00_isp_ops;
2919 ha->port_down_retry_count = 30; /* default value */
2920 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2921 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2922 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2923 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2924 ha->mr.host_info_resend = false;
2925 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2926 } else if (IS_QLA27XX(ha)) {
2927 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2928 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2929 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2930 req_length = REQUEST_ENTRY_CNT_83XX;
2931 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2932 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2933 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2934 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2935 ha->gid_list_info_size = 8;
2936 ha->optrom_size = OPTROM_SIZE_83XX;
2937 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2938 ha->isp_ops = &qla27xx_isp_ops;
2939 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2940 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2941 ha->nvram_conf_off = ~0;
2942 ha->nvram_data_off = ~0;
1da177e4 2943 }
6246b8a1 2944
7c3df132
SK		 2945 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2946 "mbx_count=%d, req_length=%d, "
2947 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2948 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2949 "max_fibre_devices=%d.\n",
7c3df132
SK		 2950 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2951 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2952 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2953 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2954 "isp_ops=%p, flash_conf_off=%d, "
2955 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2956 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2957 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2958
2959 /* Configure PCI I/O space */
2960 ret = ha->isp_ops->iospace_config(ha);
2961 if (ret)
0a63ad12 2962 goto iospace_config_failed;
706f457d
GM		 2963
2964 ql_log_pci(ql_log_info, pdev, 0x001d,
2965 "Found an ISP%04X irq %d iobase 0x%p.\n",
2966 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2967 mutex_init(&ha->vport_lock);
d7459527 2968 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2969 init_completion(&ha->mbx_cmd_comp);
2970 complete(&ha->mbx_cmd_comp);
2971 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2972 init_completion(&ha->dcbx_comp);
f356bef1 2973 init_completion(&ha->lb_portup_comp);
1da177e4 2974
2c3dfe3f 2975 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2976
53303c42 2977 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2978 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2979 "64 Bit addressing is %s.\n",
2980 ha->flags.enable_64bit_addressing ? "enable" :
2981 "disable");
73208dfd 2982 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2983 if (ret) {
7c3df132
SK		 2984 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2985 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2986
e315cd28
AC		 2987 goto probe_hw_failed;
2988 }
2989
73208dfd 2990 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2991 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2992 req->max_q_depth = ql2xmaxqdepth;
2993
e315cd28
AC		 2994
2995 base_vha = qla2x00_create_host(sht, ha);
2996 if (!base_vha) {
a1541d5a 2997 ret = -ENOMEM;
6e9f21f3 2998 qla2x00_mem_free(ha);
2afa19a9
AC		 2999 qla2x00_free_req_que(ha, req);
3000 qla2x00_free_rsp_que(ha, rsp);
e315cd28 3001 goto probe_hw_failed;
1da177e4
LT		 3002 }
3003
e315cd28 3004 pci_set_drvdata(pdev, base_vha);
6b383979 3005 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3006
e315cd28 3007 host = base_vha->host;
2afa19a9 3008 base_vha->req = req;
73208dfd 3009 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 3010 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 3011 else
e315cd28
AC		 3012 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3013 base_vha->vp_idx;
58548cb5 3014
8ae6d9c7
GM		 3015 /* Setup fcport template structure. */
3016 ha->mr.fcport.vha = base_vha;
3017 ha->mr.fcport.port_type = FCT_UNKNOWN;
3018 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3019 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3020 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3021 ha->mr.fcport.scan_state = 1;
3022
58548cb5
GM		 3023 /* Set the SG table size based on ISP type */
3024 if (!IS_FWI2_CAPABLE(ha)) {
3025 if (IS_QLA2100(ha))
3026 host->sg_tablesize = 32;
3027 } else {
3028 if (!IS_QLA82XX(ha))
3029 host->sg_tablesize = QLA_SG_ALL;
3030 }
642ef983 3031 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3032 host->cmd_per_lun = 3;
3033 host->unique_id = host->host_no;
e02587d7 3034 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3035 host->max_cmd_len = 32;
3036 else
3037 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3038 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3039 /* Older HBAs support only 16-bit LUNs */
3040 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3041 ql2xmaxlun > 0xffff)
3042 host->max_lun = 0xffff;
3043 else
3044 host->max_lun = ql2xmaxlun;
e315cd28 3045 host->transportt = qla2xxx_transport_template;
9a069e19 3046 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3047
7c3df132
SK		 3048 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3049 "max_id=%d this_id=%d "
3050 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3051 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3052 host->this_id, host->cmd_per_lun, host->unique_id,
3053 host->max_cmd_len, host->max_channel, host->max_lun,
3054 host->transportt, sht->vendor_id);
3055
d7459527
MH		 3056 /* Set up the irqs */
3057 ret = qla2x00_request_irqs(ha, rsp);
3058 if (ret)
3059 goto probe_init_failed;
3060
9a347ff4
CD		 3061 /* Alloc arrays of request and response ring ptrs */
3062 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3063 ql_log(ql_log_fatal, base_vha, 0x003d,
3064 "Failed to allocate memory for queue pointers..."
3065 "aborting.\n");
3066 goto probe_init_failed;
3067 }
3068
5601236b
MH		 3069 if (ha->mqenable && shost_use_blk_mq(host)) {
3070 /* number of hardware queues supported by blk/scsi-mq*/
3071 host->nr_hw_queues = ha->max_qpairs;
3072
3073 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3074 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3075 } else
3076 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3077 "blk/scsi-mq disabled.\n");
3078
2d70c103 3079 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3080
90a86fc0
JC		 3081 pci_save_state(pdev);
3082
9a347ff4 3083 /* Assign back pointers */
2afa19a9
AC		 3084 rsp->req = req;
3085 req->rsp = rsp;
9a347ff4 3086
8ae6d9c7
GM		 3087 if (IS_QLAFX00(ha)) {
3088 ha->rsp_q_map[0] = rsp;
3089 ha->req_q_map[0] = req;
3090 set_bit(0, ha->req_qid_map);
3091 set_bit(0, ha->rsp_qid_map);
3092 }
3093
08029990
AV		 3094 /* FWI2-capable only. */
3095 req->req_q_in = &ha->iobase->isp24.req_q_in;
3096 req->req_q_out = &ha->iobase->isp24.req_q_out;
3097 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3098 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3099 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3100 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3101 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3102 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3103 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3104 }
3105
8ae6d9c7
GM		 3106 if (IS_QLAFX00(ha)) {
3107 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3108 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3109 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3110 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3111 }
3112
7ec0effd 3113 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3114 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3115 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3116 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3117 }
3118
7c3df132
SK		 3119 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3120 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3121 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3122 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3123 "req->req_q_in=%p req->req_q_out=%p "
3124 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3125 req->req_q_in, req->req_q_out,
3126 rsp->rsp_q_in, rsp->rsp_q_out);
3127 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3128 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3129 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3130 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3131 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3132 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3133
8ae6d9c7 3134 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3135 ql_log(ql_log_fatal, base_vha, 0x00d6,
3136 "Failed to initialize adapter - Adapter flags %x.\n",
3137 base_vha->device_flags);
1da177e4 3138
a9083016
GM		 3139 if (IS_QLA82XX(ha)) {
3140 qla82xx_idc_lock(ha);
3141 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3142 QLA8XXX_DEV_FAILED);
a9083016 3143 qla82xx_idc_unlock(ha);
7c3df132
SK		 3144 ql_log(ql_log_fatal, base_vha, 0x00d7,
3145 "HW State: FAILED.\n");
7ec0effd
AD		 3146 } else if (IS_QLA8044(ha)) {
3147 qla8044_idc_lock(ha);
3148 qla8044_wr_direct(base_vha,
3149 QLA8044_CRB_DEV_STATE_INDEX,
3150 QLA8XXX_DEV_FAILED);
3151 qla8044_idc_unlock(ha);
3152 ql_log(ql_log_fatal, base_vha, 0x0150,
3153 "HW State: FAILED.\n");
a9083016
GM		 3154 }
3155
a1541d5a 3156 ret = -ENODEV;
1da177e4
LT		 3157 goto probe_failed;
3158 }
3159
3b1bef64
CD		 3160 if (IS_QLAFX00(ha))
3161 host->can_queue = QLAFX00_MAX_CANQUEUE;
3162 else
3163 host->can_queue = req->num_outstanding_cmds - 10;
3164
3165 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3166 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3167 host->can_queue, base_vha->req,
3168 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3169
e326d22a
QT		 3170 if (ha->mqenable) {
3171 bool mq = false;
3172 bool startit = false;
d7459527 3173 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
e326d22a
QT		 3174
3175 if (QLA_TGT_MODE_ENABLED()) {
3176 mq = true;
3177 startit = false;
3178 }
3179
3180 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3181 shost_use_blk_mq(host)) {
3182 mq = true;
3183 startit = true;
3184 }
3185
3186 if (mq) {
3187 /* Create start of day qpairs for Block MQ */
5601236b 3188 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3189 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3190 }
3191 }
68ca949c 3192
cbc8eb67
AV		 3193 if (ha->flags.running_gold_fw)
3194 goto skip_dpc;
3195
1da177e4
LT		 3196 /*
3197 * Startup the kernel thread for this host adapter
3198 */
39a11240 3199 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3200 "%s_dpc", base_vha->host_str);
39a11240 3201 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3202 ql_log(ql_log_fatal, base_vha, 0x00ed,
3203 "Failed to start DPC thread.\n");
39a11240 3204 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3205 goto probe_failed;
3206 }
7c3df132
SK		 3207 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3208 "DPC thread started successfully.\n");
1da177e4 3209
2d70c103
NB		 3210 /*
3211 * If we're not coming up in initiator mode, we might sit for
3212 * a while without waking up the dpc thread, which leads to a
3213 * stuck process warning. So just kick the dpc once here and
3214 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3215 */
3216 qla2xxx_wake_dpc(base_vha);
3217
ec7193e2 3218 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3219 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3220
81178772
SK		 3221 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3222 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3223 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3224 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3225
3226 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3227 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3228 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3229 INIT_WORK(&ha->idc_state_handler,
3230 qla83xx_idc_state_handler_work);
3231 INIT_WORK(&ha->nic_core_unrecoverable,
3232 qla83xx_nic_core_unrecoverable_work);
3233 }
3234
cbc8eb67 3235skip_dpc:
e315cd28
AC		 3236 list_add_tail(&base_vha->list, &ha->vp_list);
3237 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3238
3239 /* Initialized the timer */
e315cd28 3240 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3241 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3242 "Started qla2x00_timer with "
3243 "interval=%d.\n", WATCH_INTERVAL);
3244 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3245 "Detected hba at address=%p.\n",
3246 ha);
d19044c3 3247
e02587d7 3248 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3249 if (ha->fw_attributes & BIT_4) {
9e522cd8 3250 int prot = 0, guard;
bad75002 3251 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3252 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3253 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3254 if (ql2xenabledif == 1)
3255 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3256 scsi_host_set_prot(host,
8cb2049c 3257 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3258 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3259 | SHOST_DIF_TYPE3_PROTECTION
3260 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3261 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3262 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3263
3264 guard = SHOST_DIX_GUARD_CRC;
3265
3266 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3267 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3268 guard |= SHOST_DIX_GUARD_IP;
3269
3270 scsi_host_set_guard(host, guard);
bad75002
AE		 3271 } else
3272 base_vha->flags.difdix_supported = 0;
3273 }
3274
a9083016
GM		 3275 ha->isp_ops->enable_intrs(ha);
3276
1fe19ee4
AB		 3277 if (IS_QLAFX00(ha)) {
3278 ret = qlafx00_fx_disc(base_vha,
3279 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3280 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3281 QLA_SG_ALL : 128;
3282 }
3283
a1541d5a
AV		 3284 ret = scsi_add_host(host, &pdev->dev);
3285 if (ret)
3286 goto probe_failed;
3287
1486400f
MR		 3288 base_vha->flags.init_done = 1;
3289 base_vha->flags.online = 1;
edaa5c74 3290 ha->prev_minidump_failed = 0;
1486400f 3291
7c3df132
SK		 3292 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3293 "Init done and hba is online.\n");
3294
726b8548
QT		 3295 if (qla_ini_mode_enabled(base_vha) ||
3296 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3297 scsi_scan_host(host);
3298 else
3299 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3300 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3301
e315cd28 3302 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3303
8ae6d9c7 3304 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3305 ret = qlafx00_fx_disc(base_vha,
3306 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3307
3308 /* Register system information */
3309 ret = qlafx00_fx_disc(base_vha,
3310 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3311 }
3312
e315cd28 3313 qla2x00_init_host_attr(base_vha);
a1541d5a 3314
e315cd28 3315 qla2x00_dfs_setup(base_vha);
df613b96 3316
03eb912a
AB		 3317 ql_log(ql_log_info, base_vha, 0x00fb,
3318 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3319 ql_log(ql_log_info, base_vha, 0x00fc,
3320 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3321 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3322 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3323 base_vha->host_no,
df57caba 3324 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3325
2d70c103
NB		 3326 qlt_add_target(ha, base_vha);
3327
6b383979 3328 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3329
3330 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3331 return -ENODEV;
3332
1da177e4
LT		 3333 return 0;
3334
6e9f21f3 3335probe_init_failed:
2afa19a9 3336 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3337 ha->req_q_map[0] = NULL;
3338 clear_bit(0, ha->req_qid_map);
2afa19a9 3339 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3340 ha->rsp_q_map[0] = NULL;
3341 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3342 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3343
1da177e4 3344probe_failed:
b9978769
AV		 3345 if (base_vha->timer_active)
3346 qla2x00_stop_timer(base_vha);
3347 base_vha->flags.online = 0;
3348 if (ha->dpc_thread) {
3349 struct task_struct *t = ha->dpc_thread;
3350
3351 ha->dpc_thread = NULL;
3352 kthread_stop(t);
3353 }
3354
e315cd28 3355 qla2x00_free_device(base_vha);
1da177e4 3356
e315cd28 3357 scsi_host_put(base_vha->host);
1da177e4 3358
e315cd28 3359probe_hw_failed:
1a2fbf18
JL		 3360 qla2x00_clear_drv_active(ha);
3361
0a63ad12 3362iospace_config_failed:
7ec0effd 3363 if (IS_P3P_TYPE(ha)) {
0a63ad12 3364 if (!ha->nx_pcibase)
f73cb695 3365 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3366 if (!ql2xdbwr)
f73cb695 3367 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3368 } else {
3369 if (ha->iobase)
3370 iounmap(ha->iobase);
8ae6d9c7
GM		 3371 if (ha->cregbase)
3372 iounmap(ha->cregbase);
a9083016 3373 }
e315cd28
AC		 3374 pci_release_selected_regions(ha->pdev, ha->bars);
3375 kfree(ha);
1da177e4 3376
ddff7ed4 3377disable_device:
e315cd28 3378 pci_disable_device(pdev);
a1541d5a 3379 return ret;
1da177e4 3380}
1da177e4 3381
e30d1756
MI		 3382static void
3383qla2x00_shutdown(struct pci_dev *pdev)
3384{
3385 scsi_qla_host_t *vha;
3386 struct qla_hw_data *ha;
3387
3388 vha = pci_get_drvdata(pdev);
3389 ha = vha->hw;
3390
efdb5760
SC		 3391 ql_log(ql_log_info, vha, 0xfffa,
3392 "Adapter shutdown\n");
3393
3394 /*
3395 * Prevent future board_disable and wait
3396 * until any pending board_disable has completed.
3397 */
3398 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3399 cancel_work_sync(&ha->board_disable);
3400
3401 if (!atomic_read(&pdev->enable_cnt))
3402 return;
3403
42479343
AB		 3404 /* Notify ISPFX00 firmware */
3405 if (IS_QLAFX00(ha))
3406 qlafx00_driver_shutdown(vha, 20);
3407
e30d1756
MI		 3408 /* Turn-off FCE trace */
3409 if (ha->flags.fce_enabled) {
3410 qla2x00_disable_fce_trace(vha, NULL, NULL);
3411 ha->flags.fce_enabled = 0;
3412 }
3413
3414 /* Turn-off EFT trace */
3415 if (ha->eft)
3416 qla2x00_disable_eft_trace(vha);
3417
3418 /* Stop currently executing firmware. */
3419 qla2x00_try_to_stop_firmware(vha);
3420
3421 /* Turn adapter off line */
3422 vha->flags.online = 0;
3423
3424 /* turn-off interrupts on the card */
3425 if (ha->interrupts_on) {
3426 vha->flags.init_done = 0;
3427 ha->isp_ops->disable_intrs(ha);
3428 }
3429
3430 qla2x00_free_irqs(vha);
3431
3432 qla2x00_free_fw_dump(ha);
61d41f61 3433
61d41f61 3434 pci_disable_device(pdev);
efdb5760
SC		 3435 ql_log(ql_log_info, vha, 0xfffe,
3436 "Adapter shutdown successfully.\n");
e30d1756
MI		 3437}
3438
fe1b806f 3439/* Deletes all the virtual ports for a given ha */
4c993f76 3440static void
fe1b806f 3441qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3442{
fe1b806f 3443 scsi_qla_host_t *vha;
feafb7b1 3444 unsigned long flags;
e315cd28 3445
43ebf16d
AE		 3446 mutex_lock(&ha->vport_lock);
3447 while (ha->cur_vport_count) {
43ebf16d 3448 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3449
43ebf16d
AE		 3450 BUG_ON(base_vha->list.next == &ha->vp_list);
3451 /* This assumes first entry in ha->vp_list is always base vha */
3452 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3453 scsi_host_get(vha->host);
feafb7b1 3454
43ebf16d
AE		 3455 spin_unlock_irqrestore(&ha->vport_slock, flags);
3456 mutex_unlock(&ha->vport_lock);
3457
3458 fc_vport_terminate(vha->fc_vport);
3459 scsi_host_put(vha->host);
feafb7b1 3460
43ebf16d 3461 mutex_lock(&ha->vport_lock);
e315cd28 3462 }
43ebf16d 3463 mutex_unlock(&ha->vport_lock);
fe1b806f 3464}
1da177e4 3465
fe1b806f
CD		 3466/* Stops all deferred work threads */
3467static void
3468qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3469{
7d613ac6
SV		 3470 /* Cancel all work and destroy DPC workqueues */
3471 if (ha->dpc_lp_wq) {
3472 cancel_work_sync(&ha->idc_aen);
3473 destroy_workqueue(ha->dpc_lp_wq);
3474 ha->dpc_lp_wq = NULL;
3475 }
3476
3477 if (ha->dpc_hp_wq) {
3478 cancel_work_sync(&ha->nic_core_reset);
3479 cancel_work_sync(&ha->idc_state_handler);
3480 cancel_work_sync(&ha->nic_core_unrecoverable);
3481 destroy_workqueue(ha->dpc_hp_wq);
3482 ha->dpc_hp_wq = NULL;
3483 }
3484
b9978769
AV		 3485 /* Kill the kernel thread for this host */
3486 if (ha->dpc_thread) {
3487 struct task_struct *t = ha->dpc_thread;
3488
3489 /*
3490 * qla2xxx_wake_dpc checks for ->dpc_thread
3491 * so we need to zero it out.
3492 */
3493 ha->dpc_thread = NULL;
3494 kthread_stop(t);
3495 }
fe1b806f 3496}
1da177e4 3497
fe1b806f
CD		 3498static void
3499qla2x00_unmap_iobases(struct qla_hw_data *ha)
3500{
a9083016 3501 if (IS_QLA82XX(ha)) {
b963752f 3502
f73cb695 3503 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3504 if (!ql2xdbwr)
f73cb695 3505 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3506 } else {
3507 if (ha->iobase)
3508 iounmap(ha->iobase);
1da177e4 3509
8ae6d9c7
GM		 3510 if (ha->cregbase)
3511 iounmap(ha->cregbase);
3512
a9083016
GM		 3513 if (ha->mqiobase)
3514 iounmap(ha->mqiobase);
6246b8a1 3515
f73cb695 3516 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3517 iounmap(ha->msixbase);
a9083016 3518 }
fe1b806f
CD		 3519}
3520
3521static void
db7157d4 3522qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3523{
fe1b806f
CD		 3524 if (IS_QLA8044(ha)) {
3525 qla8044_idc_lock(ha);
c41afc9a 3526 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3527 qla8044_idc_unlock(ha);
3528 } else if (IS_QLA82XX(ha)) {
3529 qla82xx_idc_lock(ha);
3530 qla82xx_clear_drv_active(ha);
3531 qla82xx_idc_unlock(ha);
3532 }
3533}
3534
3535static void
3536qla2x00_remove_one(struct pci_dev *pdev)
3537{
3538 scsi_qla_host_t *base_vha;
3539 struct qla_hw_data *ha;
3540
beb9e315
JL		 3541 base_vha = pci_get_drvdata(pdev);
3542 ha = base_vha->hw;
3543
3544 /* Indicate device removal to prevent future board_disable and wait
3545 * until any pending board_disable has completed. */
3546 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3547 cancel_work_sync(&ha->board_disable);
3548
fe1b806f 3549 /*
beb9e315
JL		 3550 * If the PCI device is disabled then there was a PCI-disconnect and
3551 * qla2x00_disable_board_on_pci_error has taken care of most of the
3552 * resources.
fe1b806f 3553 */
beb9e315 3554 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3555 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3556 base_vha->gnl.l, base_vha->gnl.ldma);
3557
beb9e315
JL		 3558 scsi_host_put(base_vha->host);
3559 kfree(ha);
3560 pci_set_drvdata(pdev, NULL);
fe1b806f 3561 return;
beb9e315 3562 }
638a1a01
SC		 3563 qla2x00_wait_for_hba_ready(base_vha);
3564
726b8548
QT		 3565 /*
3566 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3567 * where it was set first.
3568 */
3569 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3570 return;
3571
fe1b806f 3572 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3573
3574 qla_nvme_delete(base_vha);
3575
726b8548
QT		 3576 dma_free_coherent(&ha->pdev->dev,
3577 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3578
3579 if (IS_QLAFX00(ha))
3580 qlafx00_driver_shutdown(base_vha, 20);
3581
3582 qla2x00_delete_all_vps(ha, base_vha);
3583
3584 if (IS_QLA8031(ha)) {
3585 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3586 "Clearing fcoe driver presence.\n");
3587 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3588 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3589 "Error while clearing DRV-Presence.\n");
3590 }
3591
3592 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3593
3594 qla2x00_dfs_remove(base_vha);
3595
3596 qla84xx_put_chip(base_vha);
3597
2d5a4c34
HM		 3598 /* Laser should be disabled only for ISP2031 */
3599 if (IS_QLA2031(ha))
3600 qla83xx_disable_laser(base_vha);
3601
fe1b806f
CD		 3602 /* Disable timer */
3603 if (base_vha->timer_active)
3604 qla2x00_stop_timer(base_vha);
3605
3606 base_vha->flags.online = 0;
3607
b0d6cabd
HM		 3608 /* free DMA memory */
3609 if (ha->exlogin_buf)
3610 qla2x00_free_exlogin_buffer(ha);
3611
2f56a7f1
HM		 3612 /* free DMA memory */
3613 if (ha->exchoffld_buf)
3614 qla2x00_free_exchoffld_buffer(ha);
3615
fe1b806f
CD		 3616 qla2x00_destroy_deferred_work(ha);
3617
3618 qlt_remove_target(ha, base_vha);
3619
3620 qla2x00_free_sysfs_attr(base_vha, true);
3621
3622 fc_remove_host(base_vha->host);
482c9dc7 3623 qlt_remove_target_resources(ha);
fe1b806f
CD		 3624
3625 scsi_remove_host(base_vha->host);
3626
3627 qla2x00_free_device(base_vha);
3628
db7157d4 3629 qla2x00_clear_drv_active(ha);
fe1b806f 3630
d2749ffa
AE		 3631 scsi_host_put(base_vha->host);
3632
fe1b806f 3633 qla2x00_unmap_iobases(ha);
73208dfd 3634
e315cd28
AC		 3635 pci_release_selected_regions(ha->pdev, ha->bars);
3636 kfree(ha);
1da177e4 3637
90a86fc0
JC		 3638 pci_disable_pcie_error_reporting(pdev);
3639
665db93b 3640 pci_disable_device(pdev);
1da177e4 3641}
1da177e4
LT		 3642
3643static void
e315cd28 3644qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3645{
e315cd28 3646 struct qla_hw_data *ha = vha->hw;
1da177e4 3647
85880801
AV		 3648 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3649
3650 /* Disable timer */
3651 if (vha->timer_active)
3652 qla2x00_stop_timer(vha);
3653
2afa19a9 3654 qla25xx_delete_queues(vha);
fe1b806f 3655
df613b96 3656 if (ha->flags.fce_enabled)
e315cd28 3657 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3658
a7a167bf 3659 if (ha->eft)
e315cd28 3660 qla2x00_disable_eft_trace(vha);
a7a167bf 3661
f6ef3b18 3662 /* Stop currently executing firmware. */
e315cd28 3663 qla2x00_try_to_stop_firmware(vha);
1da177e4 3664
85880801
AV		 3665 vha->flags.online = 0;
3666
f6ef3b18 3667 /* turn-off interrupts on the card */
a9083016
GM		 3668 if (ha->interrupts_on) {
3669 vha->flags.init_done = 0;
fd34f556 3670 ha->isp_ops->disable_intrs(ha);
a9083016 3671 }
f6ef3b18 3672
093df737
QT		 3673 qla2x00_free_fcports(vha);
3674
e315cd28 3675 qla2x00_free_irqs(vha);
1da177e4 3676
093df737
QT		 3677 /* Flush the work queue and remove it */
3678 if (ha->wq) {
3679 flush_workqueue(ha->wq);
3680 destroy_workqueue(ha->wq);
3681 ha->wq = NULL;
3682 }
3683
8867048b 3684
e315cd28 3685 qla2x00_mem_free(ha);
73208dfd 3686
08de2844
GM		 3687 qla82xx_md_free(vha);
3688
73208dfd 3689 qla2x00_free_queues(ha);
1da177e4
LT		 3690}
3691
8867048b
CD		 3692void qla2x00_free_fcports(struct scsi_qla_host *vha)
3693{
3694 fc_port_t *fcport, *tfcport;
3695
3696 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3697 list_del(&fcport->list);
5f16b331 3698 qla2x00_clear_loop_id(fcport);
8867048b 3699 kfree(fcport);
8867048b
CD		 3700 }
3701}
3702
d97994dc 3703static inline void
e315cd28 3704qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3705 int defer)
3706{
d97994dc 3707 struct fc_rport *rport;
67becc00 3708 scsi_qla_host_t *base_vha;
044d78e1 3709 unsigned long flags;
d97994dc
AV		 3710
3711 if (!fcport->rport)
3712 return;
3713
3714 rport = fcport->rport;
3715 if (defer) {
67becc00 3716 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3717 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3718 fcport->drport = rport;
044d78e1 3719 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3720 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3721 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3722 qla2xxx_wake_dpc(base_vha);
2d70c103 3723 } else {
df673274 3724 int now;
726b8548 3725 if (rport) {
83548fe2
QT		 3726 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3727 "%s %8phN. rport %p roles %x\n",
3728 __func__, fcport->port_name, rport,
3729 rport->roles);
d20ed91b 3730 fc_remote_port_delete(rport);
726b8548 3731 }
df673274 3732 qlt_do_generation_tick(vha, &now);
2d70c103 3733 }
d97994dc
AV		 3734}
3735
1da177e4
LT		 3736/*
3737 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3738 *
3739 * Input: ha = adapter block pointer. fcport = port structure pointer.
3740 *
3741 * Return: None.
3742 *
3743 * Context:
3744 */
e315cd28 3745void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3746 int do_login, int defer)
1da177e4 3747{
8ae6d9c7
GM		 3748 if (IS_QLAFX00(vha->hw)) {
3749 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3750 qla2x00_schedule_rport_del(vha, fcport, defer);
3751 return;
3752 }
3753
2c3dfe3f 3754 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3755 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3756 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3757 qla2x00_schedule_rport_del(vha, fcport, defer);
3758 }
fa2a1ce5 3759 /*
1da177e4
LT		 3760 * We may need to retry the login, so don't change the state of the
3761 * port but do the retries.
3762 */
3763 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3764 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3765
3766 if (!do_login)
3767 return;
3768
a1d0285e
AE		 3769 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3770
1da177e4 3771 if (fcport->login_retry == 0) {
e315cd28 3772 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3773
83548fe2 3774 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3775 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3776 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3777 }
3778}
3779
3780/*
3781 * qla2x00_mark_all_devices_lost
3782 * Updates fcport state when device goes offline.
3783 *
3784 * Input:
3785 * ha = adapter block pointer.
3786 * fcport = port structure pointer.
3787 *
3788 * Return:
3789 * None.
3790 *
3791 * Context:
3792 */
3793void
e315cd28 3794qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3795{
3796 fc_port_t *fcport;
3797
83548fe2
QT		 3798 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3799 "Mark all dev lost\n");
726b8548 3800
e315cd28 3801 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3802 fcport->scan_state = 0;
3803 qlt_schedule_sess_for_deletion_lock(fcport);
3804
c6d39e23 3805 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3806 continue;
0d6e61bc 3807
1da177e4
LT		 3808 /*
3809 * No point in marking the device as lost, if the device is
3810 * already DEAD.
3811 */
3812 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3813 continue;
e315cd28 3814 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3815 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3816 if (defer)
3817 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3818 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3819 qla2x00_schedule_rport_del(vha, fcport, defer);
3820 }
1da177e4
LT		 3821 }
3822}
3823
3824/*
3825* qla2x00_mem_alloc
3826* Allocates adapter memory.
3827*
3828* Returns:
3829* 0 = success.
e8711085 3830* !0 = failure.
1da177e4 3831*/
e8711085 3832static int
73208dfd
AC		 3833qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3834 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3835{
3836 char name[16];
1da177e4 3837
e8711085 3838 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3839 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3840 if (!ha->init_cb)
e315cd28 3841 goto fail;
e8711085 3842
2d70c103
NB		 3843 if (qlt_mem_alloc(ha) < 0)
3844 goto fail_free_init_cb;
3845
642ef983
CD		 3846 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3847 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3848 if (!ha->gid_list)
2d70c103 3849 goto fail_free_tgt_mem;
1da177e4 3850
e8711085
AV		 3851 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3852 if (!ha->srb_mempool)
e315cd28 3853 goto fail_free_gid_list;
e8711085 3854
7ec0effd 3855 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3856 /* Allocate cache for CT6 Ctx. */
3857 if (!ctx_cachep) {
3858 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3859 sizeof(struct ct6_dsd), 0,
3860 SLAB_HWCACHE_ALIGN, NULL);
3861 if (!ctx_cachep)
fc1ffd6c 3862 goto fail_free_srb_mempool;
a9083016
GM		 3863 }
3864 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3865 ctx_cachep);
3866 if (!ha->ctx_mempool)
3867 goto fail_free_srb_mempool;
7c3df132
SK		 3868 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3869 "ctx_cachep=%p ctx_mempool=%p.\n",
3870 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3871 }
3872
e8711085
AV		 3873 /* Get memory for cached NVRAM */
3874 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3875 if (!ha->nvram)
a9083016 3876 goto fail_free_ctx_mempool;
e8711085 3877
e315cd28
AC		 3878 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3879 ha->pdev->device);
3880 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3881 DMA_POOL_SIZE, 8, 0);
3882 if (!ha->s_dma_pool)
3883 goto fail_free_nvram;
3884
7c3df132
SK		 3885 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3886 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3887 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3888
7ec0effd 3889 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3890 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3891 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3892 if (!ha->dl_dma_pool) {
7c3df132
SK		 3893 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3894 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3895 goto fail_s_dma_pool;
3896 }
3897
3898 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3899 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3900 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3901 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3902 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3903 goto fail_dl_dma_pool;
3904 }
7c3df132
SK		 3905 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3906 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3907 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3908 }
3909
e8711085
AV		 3910 /* Allocate memory for SNS commands */
3911 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3912 /* Get consistent memory allocated for SNS commands */
e8711085 3913 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3914 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3915 if (!ha->sns_cmd)
e315cd28 3916 goto fail_dma_pool;
7c3df132 3917 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3918 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3919 } else {
e315cd28 3920 /* Get consistent memory allocated for MS IOCB */
e8711085 3921 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3922 &ha->ms_iocb_dma);
e8711085 3923 if (!ha->ms_iocb)
e315cd28
AC		 3924 goto fail_dma_pool;
3925 /* Get consistent memory allocated for CT SNS commands */
e8711085 3926 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3927 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3928 if (!ha->ct_sns)
3929 goto fail_free_ms_iocb;
7c3df132
SK		 3930 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3931 "ms_iocb=%p ct_sns=%p.\n",
3932 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3933 }
3934
e315cd28 3935 /* Allocate memory for request ring */
73208dfd
AC		 3936 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3937 if (!*req) {
7c3df132
SK		 3938 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3939 "Failed to allocate memory for req.\n");
e315cd28
AC		 3940 goto fail_req;
3941 }
73208dfd
AC		 3942 (*req)->length = req_len;
3943 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3944 ((*req)->length + 1) * sizeof(request_t),
3945 &(*req)->dma, GFP_KERNEL);
3946 if (!(*req)->ring) {
7c3df132
SK		 3947 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3948 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3949 goto fail_req_ring;
3950 }
3951 /* Allocate memory for response ring */
73208dfd
AC		 3952 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3953 if (!*rsp) {
7c3df132
SK		 3954 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3955 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3956 goto fail_rsp;
3957 }
73208dfd
AC		 3958 (*rsp)->hw = ha;
3959 (*rsp)->length = rsp_len;
3960 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3961 ((*rsp)->length + 1) * sizeof(response_t),
3962 &(*rsp)->dma, GFP_KERNEL);
3963 if (!(*rsp)->ring) {
7c3df132
SK		 3964 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3965 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3966 goto fail_rsp_ring;
3967 }
73208dfd
AC		 3968 (*req)->rsp = *rsp;
3969 (*rsp)->req = *req;
7c3df132
SK		 3970 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3971 "req=%p req->length=%d req->ring=%p rsp=%p "
3972 "rsp->length=%d rsp->ring=%p.\n",
3973 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3974 (*rsp)->ring);
73208dfd
AC		 3975 /* Allocate memory for NVRAM data for vports */
3976 if (ha->nvram_npiv_size) {
3977 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3978 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3979 if (!ha->npiv_info) {
7c3df132
SK		 3980 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3981 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3982 goto fail_npiv_info;
3983 }
3984 } else
3985 ha->npiv_info = NULL;
e8711085 3986
b64b0e8f 3987 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3988 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3989 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3990 &ha->ex_init_cb_dma);
3991 if (!ha->ex_init_cb)
3992 goto fail_ex_init_cb;
7c3df132
SK		 3993 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3994 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3995 }
3996
a9083016
GM		 3997 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3998
5ff1d584
AV		 3999 /* Get consistent memory allocated for Async Port-Database. */
4000 if (!IS_FWI2_CAPABLE(ha)) {
4001 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4002 &ha->async_pd_dma);
4003 if (!ha->async_pd)
4004 goto fail_async_pd;
7c3df132
SK		 4005 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4006 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4007 }
4008
e315cd28 4009 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4010
4011 /* Allocate memory for our loop_id bitmap */
4012 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4013 GFP_KERNEL);
4014 if (!ha->loop_id_map)
fc1ffd6c 4015 goto fail_loop_id_map;
5f16b331
CD		 4016 else {
4017 qla2x00_set_reserved_loop_ids(ha);
4018 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4019 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4020 }
4021
b2a72ec3 4022 return 0;
e315cd28 4023
fc1ffd6c
QT		 4024fail_loop_id_map:
4025 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4026fail_async_pd:
4027 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4028fail_ex_init_cb:
4029 kfree(ha->npiv_info);
73208dfd
AC		 4030fail_npiv_info:
4031 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4032 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4033 (*rsp)->ring = NULL;
4034 (*rsp)->dma = 0;
e315cd28 4035fail_rsp_ring:
73208dfd 4036 kfree(*rsp);
e315cd28 4037fail_rsp:
73208dfd
AC		 4038 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4039 sizeof(request_t), (*req)->ring, (*req)->dma);
4040 (*req)->ring = NULL;
4041 (*req)->dma = 0;
e315cd28 4042fail_req_ring:
73208dfd 4043 kfree(*req);
e315cd28
AC		 4044fail_req:
4045 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4046 ha->ct_sns, ha->ct_sns_dma);
4047 ha->ct_sns = NULL;
4048 ha->ct_sns_dma = 0;
e8711085
AV		 4049fail_free_ms_iocb:
4050 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4051 ha->ms_iocb = NULL;
4052 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4053
4054 if (ha->sns_cmd)
4055 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4056 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4057fail_dma_pool:
bad75002 4058 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4059 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4060 ha->fcp_cmnd_dma_pool = NULL;
4061 }
4062fail_dl_dma_pool:
bad75002 4063 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4064 dma_pool_destroy(ha->dl_dma_pool);
4065 ha->dl_dma_pool = NULL;
4066 }
4067fail_s_dma_pool:
e315cd28
AC		 4068 dma_pool_destroy(ha->s_dma_pool);
4069 ha->s_dma_pool = NULL;
e8711085
AV		 4070fail_free_nvram:
4071 kfree(ha->nvram);
4072 ha->nvram = NULL;
a9083016 4073fail_free_ctx_mempool:
fc1ffd6c
QT		 4074 if (ha->ctx_mempool)
4075 mempool_destroy(ha->ctx_mempool);
a9083016 4076 ha->ctx_mempool = NULL;
e8711085 4077fail_free_srb_mempool:
fc1ffd6c
QT		 4078 if (ha->srb_mempool)
4079 mempool_destroy(ha->srb_mempool);
e8711085 4080 ha->srb_mempool = NULL;
e8711085 4081fail_free_gid_list:
642ef983
CD		 4082 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4083 ha->gid_list,
e315cd28 4084 ha->gid_list_dma);
e8711085
AV		 4085 ha->gid_list = NULL;
4086 ha->gid_list_dma = 0;
2d70c103
NB		 4087fail_free_tgt_mem:
4088 qlt_mem_free(ha);
e315cd28
AC		 4089fail_free_init_cb:
4090 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4091 ha->init_cb_dma);
4092 ha->init_cb = NULL;
4093 ha->init_cb_dma = 0;
e8711085 4094fail:
7c3df132
SK		 4095 ql_log(ql_log_fatal, NULL, 0x0030,
4096 "Memory allocation failure.\n");
e8711085 4097 return -ENOMEM;
1da177e4
LT		 4098}
4099
b0d6cabd
HM		 4100int
4101qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4102{
4103 int rval;
4104 uint16_t size, max_cnt, temp;
4105 struct qla_hw_data *ha = vha->hw;
4106
4107 /* Return if we don't need to alloacate any extended logins */
4108 if (!ql2xexlogins)
4109 return QLA_SUCCESS;
4110
99e1b683
QT		 4111 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4112 return QLA_SUCCESS;
4113
b0d6cabd
HM		 4114 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4115 max_cnt = 0;
4116 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4117 if (rval != QLA_SUCCESS) {
4118 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4119 "Failed to get exlogin status.\n");
4120 return rval;
4121 }
4122
4123 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4124 temp *= size;
4125
4126 if (temp != ha->exlogin_size) {
4127 qla2x00_free_exlogin_buffer(ha);
4128 ha->exlogin_size = temp;
4129
4130 ql_log(ql_log_info, vha, 0xd024,
4131 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4132 max_cnt, size, temp);
4133
4134 ql_log(ql_log_info, vha, 0xd025,
4135 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4136
4137 /* Get consistent memory for extended logins */
4138 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4139 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4140 if (!ha->exlogin_buf) {
4141 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4142 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4143 return -ENOMEM;
4144 }
b0d6cabd
HM		 4145 }
4146
4147 /* Now configure the dma buffer */
4148 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4149 if (rval) {
83548fe2 4150 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4151 "Setup extended login buffer ****FAILED****.\n");
4152 qla2x00_free_exlogin_buffer(ha);
4153 }
4154
4155 return rval;
4156}
4157
4158/*
4159* qla2x00_free_exlogin_buffer
4160*
4161* Input:
4162* ha = adapter block pointer
4163*/
4164void
4165qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4166{
4167 if (ha->exlogin_buf) {
4168 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4169 ha->exlogin_buf, ha->exlogin_buf_dma);
4170 ha->exlogin_buf = NULL;
4171 ha->exlogin_size = 0;
4172 }
4173}
4174
99e1b683
QT		 4175static void
4176qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4177{
4178 u32 temp;
4179 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4180
4181 if (qla_ini_mode_enabled(vha)) {
4182 if (ql2xiniexchg > max_cnt)
4183 ql2xiniexchg = max_cnt;
4184
4185 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4186 *ret_cnt = ql2xiniexchg;
4187 } else if (qla_tgt_mode_enabled(vha)) {
4188 if (ql2xexchoffld > max_cnt)
4189 ql2xexchoffld = max_cnt;
4190
4191 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4192 *ret_cnt = ql2xexchoffld;
4193 } else if (qla_dual_mode_enabled(vha)) {
4194 temp = ql2xiniexchg + ql2xexchoffld;
4195 if (temp > max_cnt) {
4196 ql2xiniexchg -= (temp - max_cnt)/2;
4197 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4198 temp = max_cnt;
4199 }
4200
4201 if (temp > FW_DEF_EXCHANGES_CNT)
4202 *ret_cnt = temp;
4203 }
4204}
4205
2f56a7f1
HM		 4206int
4207qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4208{
4209 int rval;
99e1b683
QT		 4210 u16 size, max_cnt;
4211 u32 temp;
2f56a7f1
HM		 4212 struct qla_hw_data *ha = vha->hw;
4213
99e1b683
QT		 4214 if (!ha->flags.exchoffld_enabled)
4215 return QLA_SUCCESS;
4216
4217 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4218 return QLA_SUCCESS;
4219
2f56a7f1
HM		 4220 max_cnt = 0;
4221 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4222 if (rval != QLA_SUCCESS) {
4223 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4224 "Failed to get exlogin status.\n");
4225 return rval;
4226 }
4227
99e1b683
QT		 4228 qla2x00_number_of_exch(vha, &temp, max_cnt);
4229 temp *= size;
2f56a7f1 4230
99e1b683
QT		 4231 if (temp != ha->exchoffld_size) {
4232 qla2x00_free_exchoffld_buffer(ha);
4233 ha->exchoffld_size = temp;
4234
4235 ql_log(ql_log_info, vha, 0xd016,
4236 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4237 max_cnt, size, temp);
4238
4239 ql_log(ql_log_info, vha, 0xd017,
4240 "Exchange Buffers requested size = 0x%x\n",
4241 ha->exchoffld_size);
4242
4243 /* Get consistent memory for extended logins */
4244 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4245 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4246 if (!ha->exchoffld_buf) {
4247 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4248 "Failed to allocate memory for exchoffld_buf_dma.\n");
4249 return -ENOMEM;
4250 }
2f56a7f1
HM		 4251 }
4252
4253 /* Now configure the dma buffer */
99e1b683 4254 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4255 if (rval) {
4256 ql_log(ql_log_fatal, vha, 0xd02e,
4257 "Setup exchange offload buffer ****FAILED****.\n");
4258 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4259 } else {
4260 /* re-adjust number of target exchange */
4261 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4262
4263 if (qla_ini_mode_enabled(vha))
4264 icb->exchange_count = 0;
4265 else
4266 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4267 }
4268
4269 return rval;
4270}
4271
4272/*
4273* qla2x00_free_exchoffld_buffer
4274*
4275* Input:
4276* ha = adapter block pointer
4277*/
4278void
4279qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4280{
4281 if (ha->exchoffld_buf) {
4282 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4283 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4284 ha->exchoffld_buf = NULL;
4285 ha->exchoffld_size = 0;
4286 }
4287}
4288
1da177e4 4289/*
e30d1756
MI		 4290* qla2x00_free_fw_dump
4291* Frees fw dump stuff.
1da177e4
LT		 4292*
4293* Input:
7ec0effd 4294* ha = adapter block pointer
1da177e4 4295*/
a824ebb3 4296static void
e30d1756 4297qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4298{
df613b96 4299 if (ha->fce)
f73cb695
CD		 4300 dma_free_coherent(&ha->pdev->dev,
4301 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4302
f73cb695
CD		 4303 if (ha->eft)
4304 dma_free_coherent(&ha->pdev->dev,
4305 EFT_SIZE, ha->eft, ha->eft_dma);
4306
4307 if (ha->fw_dump)
a7a167bf 4308 vfree(ha->fw_dump);
f73cb695
CD		 4309 if (ha->fw_dump_template)
4310 vfree(ha->fw_dump_template);
4311
e30d1756
MI		 4312 ha->fce = NULL;
4313 ha->fce_dma = 0;
4314 ha->eft = NULL;
4315 ha->eft_dma = 0;
e30d1756 4316 ha->fw_dumped = 0;
61f098dd 4317 ha->fw_dump_cap_flags = 0;
e30d1756 4318 ha->fw_dump_reading = 0;
f73cb695
CD		 4319 ha->fw_dump = NULL;
4320 ha->fw_dump_len = 0;
4321 ha->fw_dump_template = NULL;
4322 ha->fw_dump_template_len = 0;
e30d1756
MI		 4323}
4324
4325/*
4326* qla2x00_mem_free
4327* Frees all adapter allocated memory.
4328*
4329* Input:
4330* ha = adapter block pointer.
4331*/
4332static void
4333qla2x00_mem_free(struct qla_hw_data *ha)
4334{
4335 qla2x00_free_fw_dump(ha);
4336
81178772
SK		 4337 if (ha->mctp_dump)
4338 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4339 ha->mctp_dump_dma);
4340
e30d1756
MI		 4341 if (ha->srb_mempool)
4342 mempool_destroy(ha->srb_mempool);
a7a167bf 4343
11bbc1d8
AV		 4344 if (ha->dcbx_tlv)
4345 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4346 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4347
ce0423f4
AV		 4348 if (ha->xgmac_data)
4349 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4350 ha->xgmac_data, ha->xgmac_data_dma);
4351
1da177e4
LT		 4352 if (ha->sns_cmd)
4353 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4354 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4355
4356 if (ha->ct_sns)
4357 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4358 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4359
88729e53
AV		 4360 if (ha->sfp_data)
4361 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4362
1da177e4
LT		 4363 if (ha->ms_iocb)
4364 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4365
b64b0e8f 4366 if (ha->ex_init_cb)
a9083016
GM		 4367 dma_pool_free(ha->s_dma_pool,
4368 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4369
5ff1d584
AV		 4370 if (ha->async_pd)
4371 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4372
1da177e4
LT		 4373 if (ha->s_dma_pool)
4374 dma_pool_destroy(ha->s_dma_pool);
4375
1da177e4 4376 if (ha->gid_list)
642ef983
CD		 4377 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4378 ha->gid_list, ha->gid_list_dma);
1da177e4 4379
a9083016
GM		 4380 if (IS_QLA82XX(ha)) {
4381 if (!list_empty(&ha->gbl_dsd_list)) {
4382 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4383
4384 /* clean up allocated prev pool */
4385 list_for_each_entry_safe(dsd_ptr,
4386 tdsd_ptr, &ha->gbl_dsd_list, list) {
4387 dma_pool_free(ha->dl_dma_pool,
4388 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4389 list_del(&dsd_ptr->list);
4390 kfree(dsd_ptr);
4391 }
4392 }
4393 }
4394
4395 if (ha->dl_dma_pool)
4396 dma_pool_destroy(ha->dl_dma_pool);
4397
4398 if (ha->fcp_cmnd_dma_pool)
4399 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4400
4401 if (ha->ctx_mempool)
4402 mempool_destroy(ha->ctx_mempool);
4403
2d70c103
NB		 4404 qlt_mem_free(ha);
4405
e315cd28
AC		 4406 if (ha->init_cb)
4407 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4408 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4409 vfree(ha->optrom_buffer);
4410 kfree(ha->nvram);
73208dfd 4411 kfree(ha->npiv_info);
7a67735b 4412 kfree(ha->swl);
5f16b331 4413 kfree(ha->loop_id_map);
1da177e4 4414
e8711085 4415 ha->srb_mempool = NULL;
a9083016 4416 ha->ctx_mempool = NULL;
1da177e4
LT		 4417 ha->sns_cmd = NULL;
4418 ha->sns_cmd_dma = 0;
4419 ha->ct_sns = NULL;
4420 ha->ct_sns_dma = 0;
4421 ha->ms_iocb = NULL;
4422 ha->ms_iocb_dma = 0;
1da177e4
LT		 4423 ha->init_cb = NULL;
4424 ha->init_cb_dma = 0;
b64b0e8f
AV		 4425 ha->ex_init_cb = NULL;
4426 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4427 ha->async_pd = NULL;
4428 ha->async_pd_dma = 0;
1da177e4
LT		 4429
4430 ha->s_dma_pool = NULL;
a9083016
GM		 4431 ha->dl_dma_pool = NULL;
4432 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4433
1da177e4
LT		 4434 ha->gid_list = NULL;
4435 ha->gid_list_dma = 0;
2d70c103
NB		 4436
4437 ha->tgt.atio_ring = NULL;
4438 ha->tgt.atio_dma = 0;
4439 ha->tgt.tgt_vp_map = NULL;
e315cd28 4440}
1da177e4 4441
e315cd28
AC		 4442struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4443 struct qla_hw_data *ha)
4444{
4445 struct Scsi_Host *host;
4446 struct scsi_qla_host *vha = NULL;
854165f4 4447
e315cd28 4448 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4449 if (!host) {
7c3df132
SK		 4450 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4451 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4452 return NULL;
e315cd28
AC		 4453 }
4454
4455 /* Clear our data area */
4456 vha = shost_priv(host);
4457 memset(vha, 0, sizeof(scsi_qla_host_t));
4458
4459 vha->host = host;
4460 vha->host_no = host->host_no;
4461 vha->hw = ha;
4462
4463 INIT_LIST_HEAD(&vha->vp_fcports);
4464 INIT_LIST_HEAD(&vha->work_list);
4465 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4466 INIT_LIST_HEAD(&vha->qla_cmd_list);
4467 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4468 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4469 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4470 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4471 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4472 INIT_LIST_HEAD(&vha->nvme_rport_list);
e315cd28 4473
f999f4c1 4474 spin_lock_init(&vha->work_lock);
8b2f5ff3 4475 spin_lock_init(&vha->cmd_list_lock);
726b8548 4476 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4477 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4478
2fdbc65e
BVA		 4479 vha->gnl.size = sizeof(struct get_name_list_extended) *
4480 (ha->max_loop_id + 1);
41dc529a
QT		 4481 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4482 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4483 if (!vha->gnl.l) {
83548fe2 4484 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4485 "Alloc failed for name list.\n");
4486 scsi_remove_host(vha->host);
4487 return NULL;
4488 }
f999f4c1 4489
e315cd28 4490 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4491 ql_dbg(ql_dbg_init, vha, 0x0041,
4492 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4493 vha->host, vha->hw, vha,
4494 dev_name(&(ha->pdev->dev)));
4495
e315cd28 4496 return vha;
1da177e4
LT		 4497}
4498
726b8548 4499struct qla_work_evt *
f999f4c1 4500qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4501{
4502 struct qla_work_evt *e;
feafb7b1
AE		 4503 uint8_t bail;
4504
4505 QLA_VHA_MARK_BUSY(vha, bail);
4506 if (bail)
4507 return NULL;
0971de7f 4508
f999f4c1 4509 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4510 if (!e) {
4511 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4512 return NULL;
feafb7b1 4513 }
0971de7f
AV		 4514
4515 INIT_LIST_HEAD(&e->list);
4516 e->type = type;
4517 e->flags = QLA_EVT_FLAG_FREE;
4518 return e;
4519}
4520
726b8548 4521int
f999f4c1 4522qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4523{
f999f4c1 4524 unsigned long flags;
0971de7f 4525
f999f4c1 4526 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4527 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4528 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4529
4530 if (QLA_EARLY_LINKUP(vha->hw))
4531 schedule_work(&vha->iocb_work);
4532 else
4533 qla2xxx_wake_dpc(vha);
f999f4c1 4534
0971de7f
AV		 4535 return QLA_SUCCESS;
4536}
4537
4538int
e315cd28 4539qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4540 u32 data)
4541{
4542 struct qla_work_evt *e;
4543
f999f4c1 4544 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4545 if (!e)
4546 return QLA_FUNCTION_FAILED;
4547
4548 e->u.aen.code = code;
4549 e->u.aen.data = data;
f999f4c1 4550 return qla2x00_post_work(vha, e);
0971de7f
AV		 4551}
4552
8a659571
AV		 4553int
4554qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4555{
4556 struct qla_work_evt *e;
4557
f999f4c1 4558 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4559 if (!e)
4560 return QLA_FUNCTION_FAILED;
4561
4562 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4563 return qla2x00_post_work(vha, e);
8a659571
AV		 4564}
4565
ac280b67
AV		 4566#define qla2x00_post_async_work(name, type) \
4567int qla2x00_post_async_##name##_work( \
4568 struct scsi_qla_host *vha, \
4569 fc_port_t *fcport, uint16_t *data) \
4570{ \
4571 struct qla_work_evt *e; \
4572 \
4573 e = qla2x00_alloc_work(vha, type); \
4574 if (!e) \
4575 return QLA_FUNCTION_FAILED; \
4576 \
4577 e->u.logio.fcport = fcport; \
4578 if (data) { \
4579 e->u.logio.data[0] = data[0]; \
4580 e->u.logio.data[1] = data[1]; \
4581 } \
4582 return qla2x00_post_work(vha, e); \
4583}
4584
4585qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4586qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4587qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4588qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4589qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4590
3420d36c
AV		 4591int
4592qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4593{
4594 struct qla_work_evt *e;
4595
4596 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4597 if (!e)
4598 return QLA_FUNCTION_FAILED;
4599
4600 e->u.uevent.code = code;
4601 return qla2x00_post_work(vha, e);
4602}
4603
4604static void
4605qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4606{
4607 char event_string[40];
4608 char *envp[] = { event_string, NULL };
4609
4610 switch (code) {
4611 case QLA_UEVENT_CODE_FW_DUMP:
4612 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4613 vha->host_no);
4614 break;
4615 default:
4616 /* do nothing */
4617 break;
4618 }
4619 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4620}
4621
8ae6d9c7
GM		 4622int
4623qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4624 uint32_t *data, int cnt)
4625{
4626 struct qla_work_evt *e;
4627
4628 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4629 if (!e)
4630 return QLA_FUNCTION_FAILED;
4631
4632 e->u.aenfx.evtcode = evtcode;
4633 e->u.aenfx.count = cnt;
4634 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4635 return qla2x00_post_work(vha, e);
4636}
4637
726b8548
QT		 4638int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4639{
4640 struct qla_work_evt *e;
4641
4642 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4643 if (!e)
4644 return QLA_FUNCTION_FAILED;
4645
4646 e->u.fcport.fcport = fcport;
4647 return qla2x00_post_work(vha, e);
4648}
4649
4650static
4651void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4652{
4653 unsigned long flags;
4654 fc_port_t *fcport = NULL;
4655 struct qlt_plogi_ack_t *pla =
4656 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4657
4658 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4659 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4660 if (fcport) {
4661 fcport->d_id = e->u.new_sess.id;
4662 if (pla) {
4663 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4664 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4665 /* we took an extra ref_count to prevent PLOGI ACK when
4666 * fcport/sess has not been created.
4667 */
4668 pla->ref_count--;
4669 }
4670 } else {
4671 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4672 if (fcport) {
4673 fcport->d_id = e->u.new_sess.id;
4674 fcport->scan_state = QLA_FCPORT_FOUND;
4675 fcport->flags |= FCF_FABRIC_DEVICE;
4676 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4677
4678 memcpy(fcport->port_name, e->u.new_sess.port_name,
4679 WWN_SIZE);
4680 list_add_tail(&fcport->list, &vha->vp_fcports);
4681
4682 if (pla) {
4683 qlt_plogi_ack_link(vha, pla, fcport,
4684 QLT_PLOGI_LINK_SAME_WWN);
4685 pla->ref_count--;
4686 }
4687 }
4688 }
4689 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4690
4691 if (fcport) {
4692 if (pla)
4693 qlt_plogi_ack_unref(vha, pla);
4694 else
4695 qla24xx_async_gnl(vha, fcport);
4696 }
4697}
4698
ac280b67 4699void
e315cd28 4700qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4701{
f999f4c1
AV		 4702 struct qla_work_evt *e, *tmp;
4703 unsigned long flags;
4704 LIST_HEAD(work);
0971de7f 4705
f999f4c1
AV		 4706 spin_lock_irqsave(&vha->work_lock, flags);
4707 list_splice_init(&vha->work_list, &work);
4708 spin_unlock_irqrestore(&vha->work_lock, flags);
4709
4710 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4711 list_del_init(&e->list);
0971de7f
AV		 4712
4713 switch (e->type) {
4714 case QLA_EVT_AEN:
e315cd28 4715 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4716 e->u.aen.code, e->u.aen.data);
4717 break;
8a659571
AV		 4718 case QLA_EVT_IDC_ACK:
4719 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4720 break;
ac280b67
AV		 4721 case QLA_EVT_ASYNC_LOGIN:
4722 qla2x00_async_login(vha, e->u.logio.fcport,
4723 e->u.logio.data);
4724 break;
ac280b67
AV		 4725 case QLA_EVT_ASYNC_LOGOUT:
4726 qla2x00_async_logout(vha, e->u.logio.fcport);
4727 break;
4728 case QLA_EVT_ASYNC_LOGOUT_DONE:
4729 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4730 e->u.logio.data);
4731 break;
5ff1d584
AV		 4732 case QLA_EVT_ASYNC_ADISC:
4733 qla2x00_async_adisc(vha, e->u.logio.fcport,
4734 e->u.logio.data);
4735 break;
4736 case QLA_EVT_ASYNC_ADISC_DONE:
4737 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4738 e->u.logio.data);
4739 break;
3420d36c
AV		 4740 case QLA_EVT_UEVENT:
4741 qla2x00_uevent_emit(vha, e->u.uevent.code);
4742 break;
8ae6d9c7
GM		 4743 case QLA_EVT_AENFX:
4744 qlafx00_process_aen(vha, e);
4745 break;
726b8548
QT		 4746 case QLA_EVT_GIDPN:
4747 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4748 break;
4749 case QLA_EVT_GPNID:
4750 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4751 break;
4752 case QLA_EVT_GPNID_DONE:
4753 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4754 break;
4755 case QLA_EVT_NEW_SESS:
4756 qla24xx_create_new_sess(vha, e);
4757 break;
4758 case QLA_EVT_GPDB:
4759 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4760 e->u.fcport.opt);
4761 break;
a5d42f4c
DG		 4762 case QLA_EVT_PRLI:
4763 qla24xx_async_prli(vha, e->u.fcport.fcport);
4764 break;
726b8548
QT		 4765 case QLA_EVT_GPSC:
4766 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4767 break;
4768 case QLA_EVT_UPD_FCPORT:
4769 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4770 break;
4771 case QLA_EVT_GNL:
4772 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4773 break;
4774 case QLA_EVT_NACK:
4775 qla24xx_do_nack_work(vha, e);
4776 break;
0971de7f
AV		 4777 }
4778 if (e->flags & QLA_EVT_FLAG_FREE)
4779 kfree(e);
feafb7b1
AE		 4780
4781 /* For each work completed decrement vha ref count */
4782 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4783 }
e315cd28 4784}
f999f4c1 4785
e315cd28
AC		 4786/* Relogins all the fcports of a vport
4787 * Context: dpc thread
4788 */
4789void qla2x00_relogin(struct scsi_qla_host *vha)
4790{
4791 fc_port_t *fcport;
c6b2fca8 4792 int status;
726b8548 4793 struct event_arg ea;
e315cd28
AC		 4794
4795 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4796 /*
4797 * If the port is not ONLINE then try to login
4798 * to it if we haven't run out of retries.
4799 */
5ff1d584
AV		 4800 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4801 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4802 fcport->login_retry--;
e315cd28 4803 if (fcport->flags & FCF_FABRIC_DEVICE) {
83548fe2 4804 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4805 "%s %8phC DS %d LS %d\n", __func__,
4806 fcport->port_name, fcport->disc_state,
4807 fcport->fw_login_state);
4808 memset(&ea, 0, sizeof(ea));
4809 ea.event = FCME_RELOGIN;
4810 ea.fcport = fcport;
4811 qla2x00_fcport_event_handler(vha, &ea);
4812 } else {
e315cd28
AC		 4813 status = qla2x00_local_device_login(vha,
4814 fcport);
726b8548
QT		 4815 if (status == QLA_SUCCESS) {
4816 fcport->old_loop_id = fcport->loop_id;
4817 ql_dbg(ql_dbg_disc, vha, 0x2003,
4818 "Port login OK: logged in ID 0x%x.\n",
4819 fcport->loop_id);
4820 qla2x00_update_fcport(vha, fcport);
4821 } else if (status == 1) {
4822 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4823 /* retry the login again */
4824 ql_dbg(ql_dbg_disc, vha, 0x2007,
4825 "Retrying %d login again loop_id 0x%x.\n",
4826 fcport->login_retry,
4827 fcport->loop_id);
4828 } else {
4829 fcport->login_retry = 0;
4830 }
e315cd28 4831
726b8548
QT		 4832 if (fcport->login_retry == 0 &&
4833 status != QLA_SUCCESS)
4834 qla2x00_clear_loop_id(fcport);
e315cd28 4835 }
e315cd28
AC		 4836 }
4837 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4838 break;
0971de7f 4839 }
0971de7f
AV		 4840}
4841
7d613ac6
SV		 4842/* Schedule work on any of the dpc-workqueues */
4843void
4844qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4845{
4846 struct qla_hw_data *ha = base_vha->hw;
4847
4848 switch (work_code) {
4849 case MBA_IDC_AEN: /* 0x8200 */
4850 if (ha->dpc_lp_wq)
4851 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4852 break;
4853
4854 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4855 if (!ha->flags.nic_core_reset_hdlr_active) {
4856 if (ha->dpc_hp_wq)
4857 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4858 } else
4859 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4860 "NIC Core reset is already active. Skip "
4861 "scheduling it again.\n");
4862 break;
4863 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4864 if (ha->dpc_hp_wq)
4865 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4866 break;
4867 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4868 if (ha->dpc_hp_wq)
4869 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4870 break;
4871 default:
4872 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4873 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4874 }
4875
4876 return;
4877}
4878
4879/* Work: Perform NIC Core Unrecoverable state handling */
4880void
4881qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4882{
4883 struct qla_hw_data *ha =
2ad1b67c 4884 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4885 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4886 uint32_t dev_state = 0;
4887
4888 qla83xx_idc_lock(base_vha, 0);
4889 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4890 qla83xx_reset_ownership(base_vha);
4891 if (ha->flags.nic_core_reset_owner) {
4892 ha->flags.nic_core_reset_owner = 0;
4893 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4894 QLA8XXX_DEV_FAILED);
4895 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4896 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4897 }
4898 qla83xx_idc_unlock(base_vha, 0);
4899}
4900
4901/* Work: Execute IDC state handler */
4902void
4903qla83xx_idc_state_handler_work(struct work_struct *work)
4904{
4905 struct qla_hw_data *ha =
2ad1b67c 4906 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4907 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4908 uint32_t dev_state = 0;
4909
4910 qla83xx_idc_lock(base_vha, 0);
4911 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4912 if (dev_state == QLA8XXX_DEV_FAILED ||
4913 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4914 qla83xx_idc_state_handler(base_vha);
4915 qla83xx_idc_unlock(base_vha, 0);
4916}
4917
fa492630 4918static int
7d613ac6
SV		 4919qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4920{
4921 int rval = QLA_SUCCESS;
4922 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4923 uint32_t heart_beat_counter1, heart_beat_counter2;
4924
4925 do {
4926 if (time_after(jiffies, heart_beat_wait)) {
4927 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4928 "Nic Core f/w is not alive.\n");
4929 rval = QLA_FUNCTION_FAILED;
4930 break;
4931 }
4932
4933 qla83xx_idc_lock(base_vha, 0);
4934 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4935 &heart_beat_counter1);
4936 qla83xx_idc_unlock(base_vha, 0);
4937 msleep(100);
4938 qla83xx_idc_lock(base_vha, 0);
4939 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4940 &heart_beat_counter2);
4941 qla83xx_idc_unlock(base_vha, 0);
4942 } while (heart_beat_counter1 == heart_beat_counter2);
4943
4944 return rval;
4945}
4946
4947/* Work: Perform NIC Core Reset handling */
4948void
4949qla83xx_nic_core_reset_work(struct work_struct *work)
4950{
4951 struct qla_hw_data *ha =
4952 container_of(work, struct qla_hw_data, nic_core_reset);
4953 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4954 uint32_t dev_state = 0;
4955
81178772
SK		 4956 if (IS_QLA2031(ha)) {
4957 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4958 ql_log(ql_log_warn, base_vha, 0xb081,
4959 "Failed to dump mctp\n");
4960 return;
4961 }
4962
7d613ac6
SV		 4963 if (!ha->flags.nic_core_reset_hdlr_active) {
4964 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4965 qla83xx_idc_lock(base_vha, 0);
4966 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4967 &dev_state);
4968 qla83xx_idc_unlock(base_vha, 0);
4969 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4970 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4971 "Nic Core f/w is alive.\n");
4972 return;
4973 }
4974 }
4975
4976 ha->flags.nic_core_reset_hdlr_active = 1;
4977 if (qla83xx_nic_core_reset(base_vha)) {
4978 /* NIC Core reset failed. */
4979 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4980 "NIC Core reset failed.\n");
4981 }
4982 ha->flags.nic_core_reset_hdlr_active = 0;
4983 }
4984}
4985
4986/* Work: Handle 8200 IDC aens */
4987void
4988qla83xx_service_idc_aen(struct work_struct *work)
4989{
4990 struct qla_hw_data *ha =
4991 container_of(work, struct qla_hw_data, idc_aen);
4992 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4993 uint32_t dev_state, idc_control;
4994
4995 qla83xx_idc_lock(base_vha, 0);
4996 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4997 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4998 qla83xx_idc_unlock(base_vha, 0);
4999 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5000 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5001 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5002 "Application requested NIC Core Reset.\n");
5003 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5004 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5005 QLA_SUCCESS) {
5006 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5007 "Other protocol driver requested NIC Core Reset.\n");
5008 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5009 }
5010 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5011 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5012 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5013 }
5014}
5015
5016static void
5017qla83xx_wait_logic(void)
5018{
5019 int i;
5020
5021 /* Yield CPU */
5022 if (!in_interrupt()) {
5023 /*
5024 * Wait about 200ms before retrying again.
5025 * This controls the number of retries for single
5026 * lock operation.
5027 */
5028 msleep(100);
5029 schedule();
5030 } else {
5031 for (i = 0; i < 20; i++)
5032 cpu_relax(); /* This a nop instr on i386 */
5033 }
5034}
5035
fa492630 5036static int
7d613ac6
SV		 5037qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5038{
5039 int rval;
5040 uint32_t data;
5041 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5042 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5043 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5044 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5045 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5046
5047 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5048 if (rval)
5049 return rval;
5050
5051 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5052 return QLA_SUCCESS;
5053 } else {
5054 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5055 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5056 data);
5057 if (rval)
5058 return rval;
5059
5060 msleep(200);
5061
5062 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5063 &data);
5064 if (rval)
5065 return rval;
5066
5067 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5068 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5069 ~(idc_lck_rcvry_stage_mask));
5070 rval = qla83xx_wr_reg(base_vha,
5071 QLA83XX_IDC_LOCK_RECOVERY, data);
5072 if (rval)
5073 return rval;
5074
5075 /* Forcefully perform IDC UnLock */
5076 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5077 &data);
5078 if (rval)
5079 return rval;
5080 /* Clear lock-id by setting 0xff */
5081 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5082 0xff);
5083 if (rval)
5084 return rval;
5085 /* Clear lock-recovery by setting 0x0 */
5086 rval = qla83xx_wr_reg(base_vha,
5087 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5088 if (rval)
5089 return rval;
5090 } else
5091 return QLA_SUCCESS;
5092 }
5093
5094 return rval;
5095}
5096
fa492630 5097static int
7d613ac6
SV		 5098qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5099{
5100 int rval = QLA_SUCCESS;
5101 uint32_t o_drv_lockid, n_drv_lockid;
5102 unsigned long lock_recovery_timeout;
5103
5104 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5105retry_lockid:
5106 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5107 if (rval)
5108 goto exit;
5109
5110 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5111 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5112 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5113 return QLA_SUCCESS;
5114 else
5115 return QLA_FUNCTION_FAILED;
5116 }
5117
5118 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5119 if (rval)
5120 goto exit;
5121
5122 if (o_drv_lockid == n_drv_lockid) {
5123 qla83xx_wait_logic();
5124 goto retry_lockid;
5125 } else
5126 return QLA_SUCCESS;
5127
5128exit:
5129 return rval;
5130}
5131
5132void
5133qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5134{
5135 uint16_t options = (requester_id << 15) | BIT_6;
5136 uint32_t data;
6c315553 5137 uint32_t lock_owner;
7d613ac6
SV		 5138 struct qla_hw_data *ha = base_vha->hw;
5139
5140 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5141retry_lock:
5142 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5143 == QLA_SUCCESS) {
5144 if (data) {
5145 /* Setting lock-id to our function-number */
5146 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5147 ha->portnum);
5148 } else {
6c315553
SK		 5149 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5150 &lock_owner);
7d613ac6 5151 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5152 "Failed to acquire IDC lock, acquired by %d, "
5153 "retrying...\n", lock_owner);
7d613ac6
SV		 5154
5155 /* Retry/Perform IDC-Lock recovery */
5156 if (qla83xx_idc_lock_recovery(base_vha)
5157 == QLA_SUCCESS) {
5158 qla83xx_wait_logic();
5159 goto retry_lock;
5160 } else
5161 ql_log(ql_log_warn, base_vha, 0xb075,
5162 "IDC Lock recovery FAILED.\n");
5163 }
5164
5165 }
5166
5167 return;
5168
5169 /* XXX: IDC-lock implementation using access-control mbx */
5170retry_lock2:
5171 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5172 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5173 "Failed to acquire IDC lock. retrying...\n");
5174 /* Retry/Perform IDC-Lock recovery */
5175 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5176 qla83xx_wait_logic();
5177 goto retry_lock2;
5178 } else
5179 ql_log(ql_log_warn, base_vha, 0xb076,
5180 "IDC Lock recovery FAILED.\n");
5181 }
5182
5183 return;
5184}
5185
5186void
5187qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5188{
5897cb2f
BVA		 5189#if 0
5190 uint16_t options = (requester_id << 15) | BIT_7;
5191#endif
5192 uint16_t retry;
7d613ac6
SV		 5193 uint32_t data;
5194 struct qla_hw_data *ha = base_vha->hw;
5195
5196 /* IDC-unlock implementation using driver-unlock/lock-id
5197 * remote registers
5198 */
5199 retry = 0;
5200retry_unlock:
5201 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5202 == QLA_SUCCESS) {
5203 if (data == ha->portnum) {
5204 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5205 /* Clearing lock-id by setting 0xff */
5206 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5207 } else if (retry < 10) {
5208 /* SV: XXX: IDC unlock retrying needed here? */
5209
5210 /* Retry for IDC-unlock */
5211 qla83xx_wait_logic();
5212 retry++;
5213 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5214 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5215 goto retry_unlock;
5216 }
5217 } else if (retry < 10) {
5218 /* Retry for IDC-unlock */
5219 qla83xx_wait_logic();
5220 retry++;
5221 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5222 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5223 goto retry_unlock;
5224 }
5225
5226 return;
5227
5897cb2f 5228#if 0
7d613ac6
SV		 5229 /* XXX: IDC-unlock implementation using access-control mbx */
5230 retry = 0;
5231retry_unlock2:
5232 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5233 if (retry < 10) {
5234 /* Retry for IDC-unlock */
5235 qla83xx_wait_logic();
5236 retry++;
5237 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5238 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5239 goto retry_unlock2;
5240 }
5241 }
5242
5243 return;
5897cb2f 5244#endif
7d613ac6
SV		 5245}
5246
5247int
5248__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5249{
5250 int rval = QLA_SUCCESS;
5251 struct qla_hw_data *ha = vha->hw;
5252 uint32_t drv_presence;
5253
5254 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5255 if (rval == QLA_SUCCESS) {
5256 drv_presence |= (1 << ha->portnum);
5257 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5258 drv_presence);
5259 }
5260
5261 return rval;
5262}
5263
5264int
5265qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5266{
5267 int rval = QLA_SUCCESS;
5268
5269 qla83xx_idc_lock(vha, 0);
5270 rval = __qla83xx_set_drv_presence(vha);
5271 qla83xx_idc_unlock(vha, 0);
5272
5273 return rval;
5274}
5275
5276int
5277__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5278{
5279 int rval = QLA_SUCCESS;
5280 struct qla_hw_data *ha = vha->hw;
5281 uint32_t drv_presence;
5282
5283 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5284 if (rval == QLA_SUCCESS) {
5285 drv_presence &= ~(1 << ha->portnum);
5286 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5287 drv_presence);
5288 }
5289
5290 return rval;
5291}
5292
5293int
5294qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5295{
5296 int rval = QLA_SUCCESS;
5297
5298 qla83xx_idc_lock(vha, 0);
5299 rval = __qla83xx_clear_drv_presence(vha);
5300 qla83xx_idc_unlock(vha, 0);
5301
5302 return rval;
5303}
5304
fa492630 5305static void
7d613ac6
SV		 5306qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5307{
5308 struct qla_hw_data *ha = vha->hw;
5309 uint32_t drv_ack, drv_presence;
5310 unsigned long ack_timeout;
5311
5312 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5313 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5314 while (1) {
5315 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5316 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5317 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5318 break;
5319
5320 if (time_after_eq(jiffies, ack_timeout)) {
5321 ql_log(ql_log_warn, vha, 0xb067,
5322 "RESET ACK TIMEOUT! drv_presence=0x%x "
5323 "drv_ack=0x%x\n", drv_presence, drv_ack);
5324 /*
5325 * The function(s) which did not ack in time are forced
5326 * to withdraw any further participation in the IDC
5327 * reset.
5328 */
5329 if (drv_ack != drv_presence)
5330 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5331 drv_ack);
5332 break;
5333 }
5334
5335 qla83xx_idc_unlock(vha, 0);
5336 msleep(1000);
5337 qla83xx_idc_lock(vha, 0);
5338 }
5339
5340 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5341 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5342}
5343
fa492630 5344static int
7d613ac6
SV		 5345qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5346{
5347 int rval = QLA_SUCCESS;
5348 uint32_t idc_control;
5349
5350 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5351 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5352
5353 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5354 __qla83xx_get_idc_control(vha, &idc_control);
5355 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5356 __qla83xx_set_idc_control(vha, 0);
5357
5358 qla83xx_idc_unlock(vha, 0);
5359 rval = qla83xx_restart_nic_firmware(vha);
5360 qla83xx_idc_lock(vha, 0);
5361
5362 if (rval != QLA_SUCCESS) {
5363 ql_log(ql_log_fatal, vha, 0xb06a,
5364 "Failed to restart NIC f/w.\n");
5365 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5366 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5367 } else {
5368 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5369 "Success in restarting nic f/w.\n");
5370 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5371 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5372 }
5373
5374 return rval;
5375}
5376
5377/* Assumes idc_lock always held on entry */
5378int
5379qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5380{
5381 struct qla_hw_data *ha = base_vha->hw;
5382 int rval = QLA_SUCCESS;
5383 unsigned long dev_init_timeout;
5384 uint32_t dev_state;
5385
5386 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5387 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5388
5389 while (1) {
5390
5391 if (time_after_eq(jiffies, dev_init_timeout)) {
5392 ql_log(ql_log_warn, base_vha, 0xb06e,
5393 "Initialization TIMEOUT!\n");
5394 /* Init timeout. Disable further NIC Core
5395 * communication.
5396 */
5397 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5398 QLA8XXX_DEV_FAILED);
5399 ql_log(ql_log_info, base_vha, 0xb06f,
5400 "HW State: FAILED.\n");
5401 }
5402
5403 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5404 switch (dev_state) {
5405 case QLA8XXX_DEV_READY:
5406 if (ha->flags.nic_core_reset_owner)
5407 qla83xx_idc_audit(base_vha,
5408 IDC_AUDIT_COMPLETION);
5409 ha->flags.nic_core_reset_owner = 0;
5410 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5411 "Reset_owner reset by 0x%x.\n",
5412 ha->portnum);
5413 goto exit;
5414 case QLA8XXX_DEV_COLD:
5415 if (ha->flags.nic_core_reset_owner)
5416 rval = qla83xx_device_bootstrap(base_vha);
5417 else {
5418 /* Wait for AEN to change device-state */
5419 qla83xx_idc_unlock(base_vha, 0);
5420 msleep(1000);
5421 qla83xx_idc_lock(base_vha, 0);
5422 }
5423 break;
5424 case QLA8XXX_DEV_INITIALIZING:
5425 /* Wait for AEN to change device-state */
5426 qla83xx_idc_unlock(base_vha, 0);
5427 msleep(1000);
5428 qla83xx_idc_lock(base_vha, 0);
5429 break;
5430 case QLA8XXX_DEV_NEED_RESET:
5431 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5432 qla83xx_need_reset_handler(base_vha);
5433 else {
5434 /* Wait for AEN to change device-state */
5435 qla83xx_idc_unlock(base_vha, 0);
5436 msleep(1000);
5437 qla83xx_idc_lock(base_vha, 0);
5438 }
5439 /* reset timeout value after need reset handler */
5440 dev_init_timeout = jiffies +
5441 (ha->fcoe_dev_init_timeout * HZ);
5442 break;
5443 case QLA8XXX_DEV_NEED_QUIESCENT:
5444 /* XXX: DEBUG for now */
5445 qla83xx_idc_unlock(base_vha, 0);
5446 msleep(1000);
5447 qla83xx_idc_lock(base_vha, 0);
5448 break;
5449 case QLA8XXX_DEV_QUIESCENT:
5450 /* XXX: DEBUG for now */
5451 if (ha->flags.quiesce_owner)
5452 goto exit;
5453
5454 qla83xx_idc_unlock(base_vha, 0);
5455 msleep(1000);
5456 qla83xx_idc_lock(base_vha, 0);
5457 dev_init_timeout = jiffies +
5458 (ha->fcoe_dev_init_timeout * HZ);
5459 break;
5460 case QLA8XXX_DEV_FAILED:
5461 if (ha->flags.nic_core_reset_owner)
5462 qla83xx_idc_audit(base_vha,
5463 IDC_AUDIT_COMPLETION);
5464 ha->flags.nic_core_reset_owner = 0;
5465 __qla83xx_clear_drv_presence(base_vha);
5466 qla83xx_idc_unlock(base_vha, 0);
5467 qla8xxx_dev_failed_handler(base_vha);
5468 rval = QLA_FUNCTION_FAILED;
5469 qla83xx_idc_lock(base_vha, 0);
5470 goto exit;
5471 case QLA8XXX_BAD_VALUE:
5472 qla83xx_idc_unlock(base_vha, 0);
5473 msleep(1000);
5474 qla83xx_idc_lock(base_vha, 0);
5475 break;
5476 default:
5477 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5478 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5479 qla83xx_idc_unlock(base_vha, 0);
5480 qla8xxx_dev_failed_handler(base_vha);
5481 rval = QLA_FUNCTION_FAILED;
5482 qla83xx_idc_lock(base_vha, 0);
5483 goto exit;
5484 }
5485 }
5486
5487exit:
5488 return rval;
5489}
5490
f3ddac19
CD		 5491void
5492qla2x00_disable_board_on_pci_error(struct work_struct *work)
5493{
5494 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5495 board_disable);
5496 struct pci_dev *pdev = ha->pdev;
5497 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5498
726b8548
QT		 5499 /*
5500 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5501 * where it was set first.
5502 */
5503 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5504 return;
5505
f3ddac19
CD		 5506 ql_log(ql_log_warn, base_vha, 0x015b,
5507 "Disabling adapter.\n");
5508
efdb5760
SC		 5509 if (!atomic_read(&pdev->enable_cnt)) {
5510 ql_log(ql_log_info, base_vha, 0xfffc,
5511 "PCI device disabled, no action req for PCI error=%lx\n",
5512 base_vha->pci_flags);
5513 return;
5514 }
5515
726b8548
QT		 5516 qla2x00_wait_for_sess_deletion(base_vha);
5517
f3ddac19
CD		 5518 set_bit(UNLOADING, &base_vha->dpc_flags);
5519
5520 qla2x00_delete_all_vps(ha, base_vha);
5521
5522 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5523
5524 qla2x00_dfs_remove(base_vha);
5525
5526 qla84xx_put_chip(base_vha);
5527
5528 if (base_vha->timer_active)
5529 qla2x00_stop_timer(base_vha);
5530
5531 base_vha->flags.online = 0;
5532
5533 qla2x00_destroy_deferred_work(ha);
5534
5535 /*
5536 * Do not try to stop beacon blink as it will issue a mailbox
5537 * command.
5538 */
5539 qla2x00_free_sysfs_attr(base_vha, false);
5540
5541 fc_remove_host(base_vha->host);
5542
5543 scsi_remove_host(base_vha->host);
5544
5545 base_vha->flags.init_done = 0;
5546 qla25xx_delete_queues(base_vha);
f3ddac19 5547 qla2x00_free_fcports(base_vha);
093df737 5548 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5549 qla2x00_mem_free(ha);
5550 qla82xx_md_free(base_vha);
5551 qla2x00_free_queues(ha);
5552
f3ddac19
CD		 5553 qla2x00_unmap_iobases(ha);
5554
5555 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5556 pci_disable_pcie_error_reporting(pdev);
5557 pci_disable_device(pdev);
f3ddac19 5558
beb9e315
JL		 5559 /*
5560 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5561 */
f3ddac19
CD		 5562}
5563
1da177e4
LT		 5564/**************************************************************************
5565* qla2x00_do_dpc
5566* This kernel thread is a task that is schedule by the interrupt handler
5567* to perform the background processing for interrupts.
5568*
5569* Notes:
5570* This task always run in the context of a kernel thread. It
5571* is kick-off by the driver's detect code and starts up
5572* up one per adapter. It immediately goes to sleep and waits for
5573* some fibre event. When either the interrupt handler or
5574* the timer routine detects a event it will one of the task
5575* bits then wake us up.
5576**************************************************************************/
5577static int
5578qla2x00_do_dpc(void *data)
5579{
e315cd28
AC		 5580 scsi_qla_host_t *base_vha;
5581 struct qla_hw_data *ha;
d7459527
MH		 5582 uint32_t online;
5583 struct qla_qpair *qpair;
1da177e4 5584
e315cd28
AC		 5585 ha = (struct qla_hw_data *)data;
5586 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5587
8698a745 5588 set_user_nice(current, MIN_NICE);
1da177e4 5589
563585ec 5590 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5591 while (!kthread_should_stop()) {
7c3df132
SK		 5592 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5593 "DPC handler sleeping.\n");
1da177e4 5594
39a11240 5595 schedule();
1da177e4 5596
c142caf0
AV		 5597 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5598 goto end_loop;
1da177e4 5599
85880801 5600 if (ha->flags.eeh_busy) {
7c3df132
SK		 5601 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5602 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5603 goto end_loop;
85880801
AV		 5604 }
5605
1da177e4
LT		 5606 ha->dpc_active = 1;
5607
5f28d2d7
SK		 5608 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5609 "DPC handler waking up, dpc_flags=0x%lx.\n",
5610 base_vha->dpc_flags);
1da177e4 5611
a29b3dd7
JC		 5612 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5613 break;
5614
e315cd28 5615 qla2x00_do_work(base_vha);
0971de7f 5616
7ec0effd
AD		 5617 if (IS_P3P_TYPE(ha)) {
5618 if (IS_QLA8044(ha)) {
5619 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5620 &base_vha->dpc_flags)) {
5621 qla8044_idc_lock(ha);
5622 qla8044_wr_direct(base_vha,
5623 QLA8044_CRB_DEV_STATE_INDEX,
5624 QLA8XXX_DEV_FAILED);
5625 qla8044_idc_unlock(ha);
5626 ql_log(ql_log_info, base_vha, 0x4004,
5627 "HW State: FAILED.\n");
5628 qla8044_device_state_handler(base_vha);
5629 continue;
5630 }
5631
5632 } else {
5633 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5634 &base_vha->dpc_flags)) {
5635 qla82xx_idc_lock(ha);
5636 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5637 QLA8XXX_DEV_FAILED);
5638 qla82xx_idc_unlock(ha);
5639 ql_log(ql_log_info, base_vha, 0x0151,
5640 "HW State: FAILED.\n");
5641 qla82xx_device_state_handler(base_vha);
5642 continue;
5643 }
a9083016
GM		 5644 }
5645
5646 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5647 &base_vha->dpc_flags)) {
5648
7c3df132
SK		 5649 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5650 "FCoE context reset scheduled.\n");
a9083016
GM		 5651 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5652 &base_vha->dpc_flags))) {
5653 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5654 /* FCoE-ctx reset failed.
5655 * Escalate to chip-reset
5656 */
5657 set_bit(ISP_ABORT_NEEDED,
5658 &base_vha->dpc_flags);
5659 }
5660 clear_bit(ABORT_ISP_ACTIVE,
5661 &base_vha->dpc_flags);
5662 }
5663
7c3df132
SK		 5664 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5665 "FCoE context reset end.\n");
a9083016 5666 }
8ae6d9c7
GM		 5667 } else if (IS_QLAFX00(ha)) {
5668 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5669 &base_vha->dpc_flags)) {
5670 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5671 "Firmware Reset Recovery\n");
5672 if (qlafx00_reset_initialize(base_vha)) {
5673 /* Failed. Abort isp later. */
5674 if (!test_bit(UNLOADING,
f92f82d6 5675 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5676 set_bit(ISP_UNRECOVERABLE,
5677 &base_vha->dpc_flags);
5678 ql_dbg(ql_dbg_dpc, base_vha,
5679 0x4021,
5680 "Reset Recovery Failed\n");
f92f82d6 5681 }
8ae6d9c7
GM		 5682 }
5683 }
5684
5685 if (test_and_clear_bit(FX00_TARGET_SCAN,
5686 &base_vha->dpc_flags)) {
5687 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5688 "ISPFx00 Target Scan scheduled\n");
5689 if (qlafx00_rescan_isp(base_vha)) {
5690 if (!test_bit(UNLOADING,
5691 &base_vha->dpc_flags))
5692 set_bit(ISP_UNRECOVERABLE,
5693 &base_vha->dpc_flags);
5694 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5695 "ISPFx00 Target Scan Failed\n");
5696 }
5697 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5698 "ISPFx00 Target Scan End\n");
5699 }
e8f5e95d
AB		 5700 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5701 &base_vha->dpc_flags)) {
5702 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5703 "ISPFx00 Host Info resend scheduled\n");
5704 qlafx00_fx_disc(base_vha,
5705 &base_vha->hw->mr.fcport,
5706 FXDISC_REG_HOST_INFO);
5707 }
a9083016
GM		 5708 }
5709
e315cd28
AC		 5710 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5711 &base_vha->dpc_flags)) {
1da177e4 5712
7c3df132
SK		 5713 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5714 "ISP abort scheduled.\n");
1da177e4 5715 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5716 &base_vha->dpc_flags))) {
1da177e4 5717
a9083016 5718 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5719 /* failed. retry later */
5720 set_bit(ISP_ABORT_NEEDED,
e315cd28 5721 &base_vha->dpc_flags);
99363ef8 5722 }
e315cd28
AC		 5723 clear_bit(ABORT_ISP_ACTIVE,
5724 &base_vha->dpc_flags);
99363ef8
SJ		 5725 }
5726
7c3df132
SK		 5727 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5728 "ISP abort end.\n");
1da177e4
LT		 5729 }
5730
a394aac8
DJ		 5731 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5732 &base_vha->dpc_flags)) {
e315cd28 5733 qla2x00_update_fcports(base_vha);
c9c5ced9 5734 }
d97994dc 5735
8ae6d9c7
GM		 5736 if (IS_QLAFX00(ha))
5737 goto loop_resync_check;
5738
579d12b5 5739 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5740 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5741 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5742 if (IS_P3P_TYPE(ha)) {
5743 if (IS_QLA82XX(ha))
5744 qla82xx_device_state_handler(base_vha);
5745 if (IS_QLA8044(ha))
5746 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5747 clear_bit(ISP_QUIESCE_NEEDED,
5748 &base_vha->dpc_flags);
5749 if (!ha->flags.quiesce_owner) {
5750 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5751 if (IS_QLA82XX(ha)) {
5752 qla82xx_idc_lock(ha);
5753 qla82xx_clear_qsnt_ready(
5754 base_vha);
5755 qla82xx_idc_unlock(ha);
5756 } else if (IS_QLA8044(ha)) {
5757 qla8044_idc_lock(ha);
5758 qla8044_clear_qsnt_ready(
5759 base_vha);
5760 qla8044_idc_unlock(ha);
5761 }
8fcd6b8b
CD		 5762 }
5763 } else {
5764 clear_bit(ISP_QUIESCE_NEEDED,
5765 &base_vha->dpc_flags);
5766 qla2x00_quiesce_io(base_vha);
579d12b5 5767 }
7c3df132
SK		 5768 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5769 "Quiescence mode end.\n");
579d12b5
SK		 5770 }
5771
e315cd28 5772 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5773 &base_vha->dpc_flags) &&
e315cd28 5774 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5775
7c3df132
SK		 5776 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5777 "Reset marker scheduled.\n");
e315cd28
AC		 5778 qla2x00_rst_aen(base_vha);
5779 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5780 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5781 "Reset marker end.\n");
1da177e4
LT		 5782 }
5783
5784 /* Retry each device up to login retry count */
e315cd28
AC		 5785 if ((test_and_clear_bit(RELOGIN_NEEDED,
5786 &base_vha->dpc_flags)) &&
5787 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5788 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5789
7c3df132
SK		 5790 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5791 "Relogin scheduled.\n");
e315cd28 5792 qla2x00_relogin(base_vha);
7c3df132
SK		 5793 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5794 "Relogin end.\n");
1da177e4 5795 }
8ae6d9c7 5796loop_resync_check:
e315cd28 5797 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5798 &base_vha->dpc_flags)) {
1da177e4 5799
7c3df132
SK		 5800 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5801 "Loop resync scheduled.\n");
1da177e4
LT		 5802
5803 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5804 &base_vha->dpc_flags))) {
1da177e4 5805
52c82823 5806 qla2x00_loop_resync(base_vha);
1da177e4 5807
e315cd28
AC		 5808 clear_bit(LOOP_RESYNC_ACTIVE,
5809 &base_vha->dpc_flags);
1da177e4
LT		 5810 }
5811
7c3df132
SK		 5812 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5813 "Loop resync end.\n");
1da177e4
LT		 5814 }
5815
8ae6d9c7
GM		 5816 if (IS_QLAFX00(ha))
5817 goto intr_on_check;
5818
e315cd28
AC		 5819 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5820 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5821 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5822 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5823 }
5824
8ae6d9c7 5825intr_on_check:
1da177e4 5826 if (!ha->interrupts_on)
fd34f556 5827 ha->isp_ops->enable_intrs(ha);
1da177e4 5828
e315cd28 5829 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5830 &base_vha->dpc_flags)) {
5831 if (ha->beacon_blink_led == 1)
5832 ha->isp_ops->beacon_blink(base_vha);
5833 }
f6df144c 5834
d7459527
MH		 5835 /* qpair online check */
5836 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5837 &base_vha->dpc_flags)) {
5838 if (ha->flags.eeh_busy ||
5839 ha->flags.pci_channel_io_perm_failure)
5840 online = 0;
5841 else
5842 online = 1;
5843
5844 mutex_lock(&ha->mq_lock);
5845 list_for_each_entry(qpair, &base_vha->qp_list,
5846 qp_list_elem)
5847 qpair->online = online;
5848 mutex_unlock(&ha->mq_lock);
5849 }
5850
deeae7a6
DG		 5851 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
5852 ql_log(ql_log_info, base_vha, 0xffffff,
5853 "nvme: SET ZIO Activity exchange threshold to %d.\n",
5854 ha->nvme_last_rptd_aen);
5855 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
5856 ql_log(ql_log_info, base_vha, 0xffffff,
5857 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
5858 ha->nvme_last_rptd_aen);
5859 }
5860 }
5861
8ae6d9c7
GM		 5862 if (!IS_QLAFX00(ha))
5863 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5864
1da177e4 5865 ha->dpc_active = 0;
c142caf0 5866end_loop:
563585ec 5867 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5868 } /* End of while(1) */
563585ec 5869 __set_current_state(TASK_RUNNING);
1da177e4 5870
7c3df132
SK		 5871 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5872 "DPC handler exiting.\n");
1da177e4
LT		 5873
5874 /*
5875 * Make sure that nobody tries to wake us up again.
5876 */
1da177e4
LT		 5877 ha->dpc_active = 0;
5878
ac280b67
AV		 5879 /* Cleanup any residual CTX SRBs. */
5880 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5881
39a11240
CH		 5882 return 0;
5883}
5884
5885void
e315cd28 5886qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5887{
e315cd28 5888 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5889 struct task_struct *t = ha->dpc_thread;
5890
e315cd28 5891 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5892 wake_up_process(t);
1da177e4
LT		 5893}
5894
1da177e4
LT		 5895/*
5896* qla2x00_rst_aen
5897* Processes asynchronous reset.
5898*
5899* Input:
5900* ha = adapter block pointer.
5901*/
5902static void
e315cd28 5903qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5904{
e315cd28
AC		 5905 if (vha->flags.online && !vha->flags.reset_active &&
5906 !atomic_read(&vha->loop_down_timer) &&
5907 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5908 do {
e315cd28 5909 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5910
5911 /*
5912 * Issue marker command only when we are going to start
5913 * the I/O.
5914 */
e315cd28
AC		 5915 vha->marker_needed = 1;
5916 } while (!atomic_read(&vha->loop_down_timer) &&
5917 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5918 }
5919}
5920
1da177e4
LT		 5921/**************************************************************************
5922* qla2x00_timer
5923*
5924* Description:
5925* One second timer
5926*
5927* Context: Interrupt
5928***************************************************************************/
2c3dfe3f 5929void
e315cd28 5930qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5931{
1da177e4 5932 unsigned long cpu_flags = 0;
1da177e4
LT		 5933 int start_dpc = 0;
5934 int index;
5935 srb_t *sp;
85880801 5936 uint16_t w;
e315cd28 5937 struct qla_hw_data *ha = vha->hw;
73208dfd 5938 struct req_que *req;
85880801 5939
a5b36321 5940 if (ha->flags.eeh_busy) {
7c3df132
SK		 5941 ql_dbg(ql_dbg_timer, vha, 0x6000,
5942 "EEH = %d, restarting timer.\n",
5943 ha->flags.eeh_busy);
a5b36321
LC		 5944 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5945 return;
5946 }
5947
f3ddac19
CD		 5948 /*
5949 * Hardware read to raise pending EEH errors during mailbox waits. If
5950 * the read returns -1 then disable the board.
5951 */
5952 if (!pci_channel_offline(ha->pdev)) {
85880801 5953 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5954 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5955 }
1da177e4 5956
cefcaba6 5957 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5958 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5959 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5960 start_dpc++;
7ec0effd
AD		 5961 if (IS_QLA82XX(ha))
5962 qla82xx_watchdog(vha);
5963 else if (IS_QLA8044(ha))
5964 qla8044_watchdog(vha);
579d12b5
SK		 5965 }
5966
8ae6d9c7
GM		 5967 if (!vha->vp_idx && IS_QLAFX00(ha))
5968 qlafx00_timer_routine(vha);
5969
1da177e4 5970 /* Loop down handler. */
e315cd28 5971 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5972 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5973 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5974 && vha->flags.online) {
1da177e4 5975
e315cd28
AC		 5976 if (atomic_read(&vha->loop_down_timer) ==
5977 vha->loop_down_abort_time) {
1da177e4 5978
7c3df132
SK		 5979 ql_log(ql_log_info, vha, 0x6008,
5980 "Loop down - aborting the queues before time expires.\n");
1da177e4 5981
e315cd28
AC		 5982 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5983 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5984
f08b7251
AV		 5985 /*
5986 * Schedule an ISP abort to return any FCP2-device
5987 * commands.
5988 */
2c3dfe3f 5989 /* NPIV - scan physical port only */
e315cd28 5990 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5991 spin_lock_irqsave(&ha->hardware_lock,
5992 cpu_flags);
73208dfd 5993 req = ha->req_q_map[0];
2c3dfe3f 5994 for (index = 1;
8d93f550 5995 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5996 index++) {
5997 fc_port_t *sfcp;
5998
e315cd28 5999 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6000 if (!sp)
6001 continue;
c5419e26
QT		 6002 if (sp->cmd_type != TYPE_SRB)
6003 continue;
9ba56b95 6004 if (sp->type != SRB_SCSI_CMD)
cf53b069 6005 continue;
2c3dfe3f 6006 sfcp = sp->fcport;
f08b7251 6007 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6008 continue;
bdf79621 6009
8f7daead
GM		 6010 if (IS_QLA82XX(ha))
6011 set_bit(FCOE_CTX_RESET_NEEDED,
6012 &vha->dpc_flags);
6013 else
6014 set_bit(ISP_ABORT_NEEDED,
e315cd28 6015 &vha->dpc_flags);
2c3dfe3f
SJ		 6016 break;
6017 }
6018 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6019 cpu_flags);
1da177e4 6020 }
1da177e4
LT		 6021 start_dpc++;
6022 }
6023
6024 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6025 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6026 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6027 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6028 "Loop down - aborting ISP.\n");
6029
8f7daead
GM		 6030 if (IS_QLA82XX(ha))
6031 set_bit(FCOE_CTX_RESET_NEEDED,
6032 &vha->dpc_flags);
6033 else
6034 set_bit(ISP_ABORT_NEEDED,
6035 &vha->dpc_flags);
1da177e4
LT		 6036 }
6037 }
7c3df132
SK		 6038 ql_dbg(ql_dbg_timer, vha, 0x600a,
6039 "Loop down - seconds remaining %d.\n",
6040 atomic_read(&vha->loop_down_timer));
1da177e4 6041 }
cefcaba6
SK		 6042 /* Check if beacon LED needs to be blinked for physical host only */
6043 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6044 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6045 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6046 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6047 start_dpc++;
6048 }
f6df144c
AV		 6049 }
6050
550bf57d 6051 /* Process any deferred work. */
e315cd28 6052 if (!list_empty(&vha->work_list))
550bf57d
AV		 6053 start_dpc++;
6054
7401bc18
DG		 6055 /*
6056 * FC-NVME
6057 * see if the active AEN count has changed from what was last reported.
6058 */
deeae7a6
DG		 6059 if (!vha->vp_idx &&
6060 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6061 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6062 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6063 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6064 ha->nvme_last_rptd_aen);
6065 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6066 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6067 start_dpc++;
7401bc18
DG		 6068 }
6069
1da177e4 6070 /* Schedule the DPC routine if needed */
e315cd28
AC		 6071 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6072 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6073 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6074 start_dpc ||
e315cd28
AC		 6075 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6076 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6077 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6078 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6079 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6080 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6081 ql_dbg(ql_dbg_timer, vha, 0x600b,
6082 "isp_abort_needed=%d loop_resync_needed=%d "
6083 "fcport_update_needed=%d start_dpc=%d "
6084 "reset_marker_needed=%d",
6085 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6086 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6087 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6088 start_dpc,
6089 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6090 ql_dbg(ql_dbg_timer, vha, 0x600c,
6091 "beacon_blink_needed=%d isp_unrecoverable=%d "
6092 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6093 "relogin_needed=%d.\n",
7c3df132
SK		 6094 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6095 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6096 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6097 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6098 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6099 qla2xxx_wake_dpc(vha);
7c3df132 6100 }
1da177e4 6101
e315cd28 6102 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6103}
6104
5433383e
AV		 6105/* Firmware interface routines. */
6106
f73cb695 6107#define FW_BLOBS 11
5433383e
AV		 6108#define FW_ISP21XX 0
6109#define FW_ISP22XX 1
6110#define FW_ISP2300 2
6111#define FW_ISP2322 3
48c02fde 6112#define FW_ISP24XX 4
c3a2f0df 6113#define FW_ISP25XX 5
3a03eb79 6114#define FW_ISP81XX 6
a9083016 6115#define FW_ISP82XX 7
6246b8a1
GM		 6116#define FW_ISP2031 8
6117#define FW_ISP8031 9
2c5bbbb2 6118#define FW_ISP27XX 10
5433383e 6119
bb8ee499
AV		 6120#define FW_FILE_ISP21XX "ql2100_fw.bin"
6121#define FW_FILE_ISP22XX "ql2200_fw.bin"
6122#define FW_FILE_ISP2300 "ql2300_fw.bin"
6123#define FW_FILE_ISP2322 "ql2322_fw.bin"
6124#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6125#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6126#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6127#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6128#define FW_FILE_ISP2031 "ql2600_fw.bin"
6129#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6130#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6131
bb8ee499 6132
e1e82b6f 6133static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6134
6135static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6136 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6137 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6138 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6139 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6140 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6141 { .name = FW_FILE_ISP25XX, },
3a03eb79 6142 { .name = FW_FILE_ISP81XX, },
a9083016 6143 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6144 { .name = FW_FILE_ISP2031, },
6145 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6146 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6147};
6148
6149struct fw_blob *
e315cd28 6150qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6151{
e315cd28 6152 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6153 struct fw_blob *blob;
6154
5433383e
AV		 6155 if (IS_QLA2100(ha)) {
6156 blob = &qla_fw_blobs[FW_ISP21XX];
6157 } else if (IS_QLA2200(ha)) {
6158 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6159 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6160 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6161 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6162 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6163 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6164 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6165 } else if (IS_QLA25XX(ha)) {
6166 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6167 } else if (IS_QLA81XX(ha)) {
6168 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6169 } else if (IS_QLA82XX(ha)) {
6170 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6171 } else if (IS_QLA2031(ha)) {
6172 blob = &qla_fw_blobs[FW_ISP2031];
6173 } else if (IS_QLA8031(ha)) {
6174 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6175 } else if (IS_QLA27XX(ha)) {
6176 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6177 } else {
6178 return NULL;
5433383e
AV		 6179 }
6180
e1e82b6f 6181 mutex_lock(&qla_fw_lock);
5433383e
AV		 6182 if (blob->fw)
6183 goto out;
6184
6185 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6186 ql_log(ql_log_warn, vha, 0x0063,
6187 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6188 blob->fw = NULL;
6189 blob = NULL;
6190 goto out;
6191 }
6192
6193out:
e1e82b6f 6194 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6195 return blob;
6196}
6197
6198static void
6199qla2x00_release_firmware(void)
6200{
6201 int idx;
6202
e1e82b6f 6203 mutex_lock(&qla_fw_lock);
5433383e 6204 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6205 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6206 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6207}
6208
14e660e6
SJ		 6209static pci_ers_result_t
6210qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6211{
85880801
AV		 6212 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6213 struct qla_hw_data *ha = vha->hw;
6214
7c3df132
SK		 6215 ql_dbg(ql_dbg_aer, vha, 0x9000,
6216 "PCI error detected, state %x.\n", state);
b9b12f73 6217
efdb5760
SC		 6218 if (!atomic_read(&pdev->enable_cnt)) {
6219 ql_log(ql_log_info, vha, 0xffff,
6220 "PCI device is disabled,state %x\n", state);
6221 return PCI_ERS_RESULT_NEED_RESET;
6222 }
6223
14e660e6
SJ		 6224 switch (state) {
6225 case pci_channel_io_normal:
85880801 6226 ha->flags.eeh_busy = 0;
d7459527
MH		 6227 if (ql2xmqsupport) {
6228 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6229 qla2xxx_wake_dpc(vha);
6230 }
14e660e6
SJ		 6231 return PCI_ERS_RESULT_CAN_RECOVER;
6232 case pci_channel_io_frozen:
85880801 6233 ha->flags.eeh_busy = 1;
a5b36321
LC		 6234 /* For ISP82XX complete any pending mailbox cmd */
6235 if (IS_QLA82XX(ha)) {
7190575f 6236 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6237 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6238 qla82xx_clear_pending_mbx(vha);
a5b36321 6239 }
90a86fc0 6240 qla2x00_free_irqs(vha);
14e660e6 6241 pci_disable_device(pdev);
bddd2d65
LC		 6242 /* Return back all IOs */
6243 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6244 if (ql2xmqsupport) {
6245 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6246 qla2xxx_wake_dpc(vha);
6247 }
14e660e6
SJ		 6248 return PCI_ERS_RESULT_NEED_RESET;
6249 case pci_channel_io_perm_failure:
85880801
AV		 6250 ha->flags.pci_channel_io_perm_failure = 1;
6251 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6252 if (ql2xmqsupport) {
6253 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6254 qla2xxx_wake_dpc(vha);
6255 }
14e660e6
SJ		 6256 return PCI_ERS_RESULT_DISCONNECT;
6257 }
6258 return PCI_ERS_RESULT_NEED_RESET;
6259}
6260
6261static pci_ers_result_t
6262qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6263{
6264 int risc_paused = 0;
6265 uint32_t stat;
6266 unsigned long flags;
e315cd28
AC		 6267 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6268 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6269 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6270 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6271
bcc5b6d3
SK		 6272 if (IS_QLA82XX(ha))
6273 return PCI_ERS_RESULT_RECOVERED;
6274
14e660e6
SJ		 6275 spin_lock_irqsave(&ha->hardware_lock, flags);
6276 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6277 stat = RD_REG_DWORD(&reg->hccr);
6278 if (stat & HCCR_RISC_PAUSE)
6279 risc_paused = 1;
6280 } else if (IS_QLA23XX(ha)) {
6281 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6282 if (stat & HSR_RISC_PAUSED)
6283 risc_paused = 1;
6284 } else if (IS_FWI2_CAPABLE(ha)) {
6285 stat = RD_REG_DWORD(&reg24->host_status);
6286 if (stat & HSRX_RISC_PAUSED)
6287 risc_paused = 1;
6288 }
6289 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6290
6291 if (risc_paused) {
7c3df132
SK		 6292 ql_log(ql_log_info, base_vha, 0x9003,
6293 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6294 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6295
6296 return PCI_ERS_RESULT_NEED_RESET;
6297 } else
6298 return PCI_ERS_RESULT_RECOVERED;
6299}
6300
fa492630
SK		 6301static uint32_t
6302qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6303{
6304 uint32_t rval = QLA_FUNCTION_FAILED;
6305 uint32_t drv_active = 0;
6306 struct qla_hw_data *ha = base_vha->hw;
6307 int fn;
6308 struct pci_dev *other_pdev = NULL;
6309
7c3df132
SK		 6310 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6311 "Entered %s.\n", __func__);
a5b36321
LC		 6312
6313 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6314
6315 if (base_vha->flags.online) {
6316 /* Abort all outstanding commands,
6317 * so as to be requeued later */
6318 qla2x00_abort_isp_cleanup(base_vha);
6319 }
6320
6321
6322 fn = PCI_FUNC(ha->pdev->devfn);
6323 while (fn > 0) {
6324 fn--;
7c3df132
SK		 6325 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6326 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6327 other_pdev =
6328 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6329 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6330 fn));
6331
6332 if (!other_pdev)
6333 continue;
6334 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6335 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6336 "Found PCI func available and enable at 0x%x.\n",
6337 fn);
a5b36321
LC		 6338 pci_dev_put(other_pdev);
6339 break;
6340 }
6341 pci_dev_put(other_pdev);
6342 }
6343
6344 if (!fn) {
6345 /* Reset owner */
7c3df132
SK		 6346 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6347 "This devfn is reset owner = 0x%x.\n",
6348 ha->pdev->devfn);
a5b36321
LC		 6349 qla82xx_idc_lock(ha);
6350
6351 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6352 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6353
6354 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6355 QLA82XX_IDC_VERSION);
6356
6357 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6358 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6359 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6360
6361 qla82xx_idc_unlock(ha);
6362 /* Reset if device is not already reset
6363 * drv_active would be 0 if a reset has already been done
6364 */
6365 if (drv_active)
6366 rval = qla82xx_start_firmware(base_vha);
6367 else
6368 rval = QLA_SUCCESS;
6369 qla82xx_idc_lock(ha);
6370
6371 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6372 ql_log(ql_log_info, base_vha, 0x900b,
6373 "HW State: FAILED.\n");
a5b36321
LC		 6374 qla82xx_clear_drv_active(ha);
6375 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6376 QLA8XXX_DEV_FAILED);
a5b36321 6377 } else {
7c3df132
SK		 6378 ql_log(ql_log_info, base_vha, 0x900c,
6379 "HW State: READY.\n");
a5b36321 6380 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6381 QLA8XXX_DEV_READY);
a5b36321 6382 qla82xx_idc_unlock(ha);
7190575f 6383 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6384 rval = qla82xx_restart_isp(base_vha);
6385 qla82xx_idc_lock(ha);
6386 /* Clear driver state register */
6387 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6388 qla82xx_set_drv_active(base_vha);
6389 }
6390 qla82xx_idc_unlock(ha);
6391 } else {
7c3df132
SK		 6392 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6393 "This devfn is not reset owner = 0x%x.\n",
6394 ha->pdev->devfn);
a5b36321 6395 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6396 QLA8XXX_DEV_READY)) {
7190575f 6397 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6398 rval = qla82xx_restart_isp(base_vha);
6399 qla82xx_idc_lock(ha);
6400 qla82xx_set_drv_active(base_vha);
6401 qla82xx_idc_unlock(ha);
6402 }
6403 }
6404 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6405
6406 return rval;
6407}
6408
14e660e6
SJ		 6409static pci_ers_result_t
6410qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6411{
6412 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6413 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6414 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6415 struct rsp_que *rsp;
6416 int rc, retries = 10;
09483916 6417
7c3df132
SK		 6418 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6419 "Slot Reset.\n");
85880801 6420
90a86fc0
JC		 6421 /* Workaround: qla2xxx driver which access hardware earlier
6422 * needs error state to be pci_channel_io_online.
6423 * Otherwise mailbox command timesout.
6424 */
6425 pdev->error_state = pci_channel_io_normal;
6426
6427 pci_restore_state(pdev);
6428
8c1496bd
RL		 6429 /* pci_restore_state() clears the saved_state flag of the device
6430 * save restored state which resets saved_state flag
6431 */
6432 pci_save_state(pdev);
6433
09483916
BH		 6434 if (ha->mem_only)
6435 rc = pci_enable_device_mem(pdev);
6436 else
6437 rc = pci_enable_device(pdev);
14e660e6 6438
09483916 6439 if (rc) {
7c3df132 6440 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6441 "Can't re-enable PCI device after reset.\n");
a5b36321 6442 goto exit_slot_reset;
14e660e6 6443 }
14e660e6 6444
90a86fc0
JC		 6445 rsp = ha->rsp_q_map[0];
6446 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6447 goto exit_slot_reset;
90a86fc0 6448
e315cd28 6449 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6450 goto exit_slot_reset;
6451
6452 if (IS_QLA82XX(ha)) {
6453 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6454 ret = PCI_ERS_RESULT_RECOVERED;
6455 goto exit_slot_reset;
6456 } else
6457 goto exit_slot_reset;
6458 }
14e660e6 6459
90a86fc0
JC		 6460 while (ha->flags.mbox_busy && retries--)
6461 msleep(1000);
85880801 6462
e315cd28 6463 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6464 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6465 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6466 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6467
90a86fc0 6468
a5b36321 6469exit_slot_reset:
7c3df132
SK		 6470 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6471 "slot_reset return %x.\n", ret);
85880801 6472
14e660e6
SJ		 6473 return ret;
6474}
6475
6476static void
6477qla2xxx_pci_resume(struct pci_dev *pdev)
6478{
e315cd28
AC		 6479 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6480 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6481 int ret;
6482
7c3df132
SK		 6483 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6484 "pci_resume.\n");
85880801 6485
e315cd28 6486 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6487 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6488 ql_log(ql_log_fatal, base_vha, 0x9002,
6489 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6490 }
85880801 6491
3e46f031
LC		 6492 pci_cleanup_aer_uncorrect_error_status(pdev);
6493
85880801 6494 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6495}
6496
2d5a4c34
HM		 6497static void
6498qla83xx_disable_laser(scsi_qla_host_t *vha)
6499{
6500 uint32_t reg, data, fn;
6501 struct qla_hw_data *ha = vha->hw;
6502 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6503
6504 /* pci func #/port # */
6505 ql_dbg(ql_dbg_init, vha, 0x004b,
6506 "Disabling Laser for hba: %p\n", vha);
6507
6508 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6509 (BIT_15|BIT_14|BIT_13|BIT_12));
6510
6511 fn = (fn >> 12);
6512
6513 if (fn & 1)
6514 reg = PORT_1_2031;
6515 else
6516 reg = PORT_0_2031;
6517
6518 data = LASER_OFF_2031;
6519
6520 qla83xx_wr_reg(vha, reg, data);
6521}
6522
5601236b
MH		 6523static int qla2xxx_map_queues(struct Scsi_Host *shost)
6524{
6525 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6526
6527 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6528}
6529
a55b2d21 6530static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6531 .error_detected = qla2xxx_pci_error_detected,
6532 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6533 .slot_reset = qla2xxx_pci_slot_reset,
6534 .resume = qla2xxx_pci_resume,
6535};
6536
5433383e 6537static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6538 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6539 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6540 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6541 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6542 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6543 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6544 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6545 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6546 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6547 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6548 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6549 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6550 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6551 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6552 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6553 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6554 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6555 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6556 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6557 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6558 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6559 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6560 { 0 },
6561};
6562MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6563
fca29703 6564static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6565 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6566 .driver = {
6567 .owner = THIS_MODULE,
6568 },
fca29703 6569 .id_table = qla2xxx_pci_tbl,
7ee61397 6570 .probe = qla2x00_probe_one,
4c993f76 6571 .remove = qla2x00_remove_one,
e30d1756 6572 .shutdown = qla2x00_shutdown,
14e660e6 6573 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6574};
6575
75ef9de1 6576static const struct file_operations apidev_fops = {
6a03b4cd 6577 .owner = THIS_MODULE,
6038f373 6578 .llseek = noop_llseek,
6a03b4cd
HZ		 6579};
6580
1da177e4
LT		 6581/**
6582 * qla2x00_module_init - Module initialization.
6583 **/
6584static int __init
6585qla2x00_module_init(void)
6586{
fca29703
AV		 6587 int ret = 0;
6588
1da177e4 6589 /* Allocate cache for SRBs. */
354d6b21 6590 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6591 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6592 if (srb_cachep == NULL) {
7c3df132
SK		 6593 ql_log(ql_log_fatal, NULL, 0x0001,
6594 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6595 return -ENOMEM;
6596 }
6597
2d70c103
NB		 6598 /* Initialize target kmem_cache and mem_pools */
6599 ret = qlt_init();
6600 if (ret < 0) {
6601 kmem_cache_destroy(srb_cachep);
6602 return ret;
6603 } else if (ret > 0) {
6604 /*
6605 * If initiator mode is explictly disabled by qlt_init(),
6606 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6607 * performing scsi_scan_target() during LOOP UP event.
6608 */
6609 qla2xxx_transport_functions.disable_target_scan = 1;
6610 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6611 }
6612
1da177e4
LT		 6613 /* Derive version string. */
6614 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6615 if (ql2xextended_error_logging)
0181944f
AV		 6616 strcat(qla2x00_version_str, "-debug");
6617
1c97a12a
AV		 6618 qla2xxx_transport_template =
6619 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6620 if (!qla2xxx_transport_template) {
6621 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6622 ql_log(ql_log_fatal, NULL, 0x0002,
6623 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6624 qlt_exit();
1da177e4 6625 return -ENODEV;
2c3dfe3f 6626 }
6a03b4cd
HZ		 6627
6628 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6629 if (apidev_major < 0) {
7c3df132
SK		 6630 ql_log(ql_log_fatal, NULL, 0x0003,
6631 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6632 }
6633
2c3dfe3f
SJ		 6634 qla2xxx_transport_vport_template =
6635 fc_attach_transport(&qla2xxx_transport_vport_functions);
6636 if (!qla2xxx_transport_vport_template) {
6637 kmem_cache_destroy(srb_cachep);
2d70c103 6638 qlt_exit();
2c3dfe3f 6639 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6640 ql_log(ql_log_fatal, NULL, 0x0004,
6641 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6642 return -ENODEV;
2c3dfe3f 6643 }
7c3df132
SK		 6644 ql_log(ql_log_info, NULL, 0x0005,
6645 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6646 qla2x00_version_str);
7ee61397 6647 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6648 if (ret) {
6649 kmem_cache_destroy(srb_cachep);
2d70c103 6650 qlt_exit();
fca29703 6651 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6652 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6653 ql_log(ql_log_fatal, NULL, 0x0006,
6654 "pci_register_driver failed...ret=%d Failing load!.\n",
6655 ret);
fca29703
AV		 6656 }
6657 return ret;
1da177e4
LT		 6658}
6659
6660/**
6661 * qla2x00_module_exit - Module cleanup.
6662 **/
6663static void __exit
6664qla2x00_module_exit(void)
6665{
6a03b4cd 6666 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6667 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6668 qla2x00_release_firmware();
354d6b21 6669 kmem_cache_destroy(srb_cachep);
2d70c103 6670 qlt_exit();
a9083016
GM		 6671 if (ctx_cachep)
6672 kmem_cache_destroy(ctx_cachep);
1da177e4 6673 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6674 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6675}
6676
6677module_init(qla2x00_module_init);
6678module_exit(qla2x00_module_exit);
6679
6680MODULE_AUTHOR("QLogic Corporation");
6681MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6682MODULE_LICENSE("GPL");
6683MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6684MODULE_FIRMWARE(FW_FILE_ISP21XX);
6685MODULE_FIRMWARE(FW_FILE_ISP22XX);
6686MODULE_FIRMWARE(FW_FILE_ISP2300);
6687MODULE_FIRMWARE(FW_FILE_ISP2322);
6688MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6689MODULE_FIRMWARE(FW_FILE_ISP25XX);
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