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[SCSI] qla2xxx: Perform warm reset every 2 minutes if firmware load fails for ISPFX00.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
1e63395c 3 * Copyright (c) 2003-2013 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
1da177e4
LT		 16#include <scsi/scsi_tcq.h>
17#include <scsi/scsicam.h>
18#include <scsi/scsi_transport.h>
19#include <scsi/scsi_transport_fc.h>
20
2d70c103
NB		 21#include "qla_target.h"
22
1da177e4
LT		 23/*
24 * Driver version
25 */
26char qla2x00_version_str[40];
27
6a03b4cd
HZ		 28static int apidev_major;
29
1da177e4
LT		 30/*
31 * SRB allocation cache
32 */
e18b890b 33static struct kmem_cache *srb_cachep;
1da177e4 34
a9083016
GM		 35/*
36 * CT6 CTX allocation cache
37 */
38static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 39/*
40 * error level for logging
41 */
42int ql_errlev = ql_log_all;
a9083016 43
fa492630 44static int ql2xenableclass2;
2d70c103
NB		 45module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
46MODULE_PARM_DESC(ql2xenableclass2,
47 "Specify if Class 2 operations are supported from the very "
48 "beginning. Default is 0 - class 2 not supported.");
49
8ae6d9c7 50
1da177e4 51int ql2xlogintimeout = 20;
f2019cb1 52module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 53MODULE_PARM_DESC(ql2xlogintimeout,
54 "Login timeout value in seconds.");
55
a7b61842 56int qlport_down_retry;
f2019cb1 57module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 58MODULE_PARM_DESC(qlport_down_retry,
900d9f98 59 "Maximum number of command retries to a port that returns "
1da177e4
LT		 60 "a PORT-DOWN status.");
61
1da177e4
LT		 62int ql2xplogiabsentdevice;
63module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
64MODULE_PARM_DESC(ql2xplogiabsentdevice,
65 "Option to enable PLOGI to devices that are not present after "
900d9f98 66 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 67 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
68
1da177e4 69int ql2xloginretrycount = 0;
f2019cb1 70module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 71MODULE_PARM_DESC(ql2xloginretrycount,
72 "Specify an alternate value for the NVRAM login retry count.");
73
a7a167bf 74int ql2xallocfwdump = 1;
f2019cb1 75module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 76MODULE_PARM_DESC(ql2xallocfwdump,
77 "Option to enable allocation of memory for a firmware dump "
78 "during HBA initialization. Memory allocation requirements "
79 "vary by ISP type. Default is 1 - allocate memory.");
80
11010fec 81int ql2xextended_error_logging;
27d94035 82module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 83MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 84 "Option to enable extended error logging,\n"
85 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
86 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
87 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
88 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
89 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
90 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
91 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
92 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 93 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
94 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 95 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 96 "\t\t0x1e400000 - Preferred value for capturing essential "
97 "debug information (equivalent to old "
98 "ql2xextended_error_logging=1).\n"
3ce8866c 99 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 100
a9083016 101int ql2xshiftctondsd = 6;
f2019cb1 102module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 103MODULE_PARM_DESC(ql2xshiftctondsd,
104 "Set to control shifting of command type processing "
105 "based on total number of SG elements.");
106
7e47e5ca 107int ql2xfdmienable=1;
f2019cb1 108module_param(ql2xfdmienable, int, S_IRUGO);
cca5335c 109MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 110 "Enables FDMI registrations. "
111 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 112
3c290d0b 113int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 114module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
115MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 116 "Maximum queue depth to set for each LUN. "
117 "Default is 32.");
df7baa50 118
9e522cd8
AE		 119int ql2xenabledif = 2;
120module_param(ql2xenabledif, int, S_IRUGO);
bad75002
AE		 121MODULE_PARM_DESC(ql2xenabledif,
122 " Enable T10-CRC-DIF "
8cb2049c
AE		 123 " Default is 0 - No DIF Support. 1 - Enable it"
124 ", 2 - Enable DIF for all types, except Type 0.");
bad75002 125
8cb2049c 126int ql2xenablehba_err_chk = 2;
bad75002
AE		 127module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
128MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c
AE		 129 " Enable T10-CRC-DIF Error isolation by HBA:\n"
130 " Default is 1.\n"
131 " 0 -- Error isolation disabled\n"
132 " 1 -- Error isolation enabled only for DIX Type 0\n"
133 " 2 -- Error isolation enabled for all Types\n");
bad75002 134
e5896bd5 135int ql2xiidmaenable=1;
f2019cb1 136module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 137MODULE_PARM_DESC(ql2xiidmaenable,
138 "Enables iIDMA settings "
139 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
140
73208dfd 141int ql2xmaxqueues = 1;
f2019cb1 142module_param(ql2xmaxqueues, int, S_IRUGO);
73208dfd
AC		 143MODULE_PARM_DESC(ql2xmaxqueues,
144 "Enables MQ settings "
ae68230c
JP		 145 "Default is 1 for single queue. Set it to number "
146 "of queues in MQ mode.");
68ca949c
AC		 147
148int ql2xmultique_tag;
f2019cb1 149module_param(ql2xmultique_tag, int, S_IRUGO);
68ca949c
AC		 150MODULE_PARM_DESC(ql2xmultique_tag,
151 "Enables CPU affinity settings for the driver "
152 "Default is 0 for no affinity of request and response IO. "
153 "Set it to 1 to turn on the cpu affinity.");
e337d907
AV		 154
155int ql2xfwloadbin;
86e45bf6 156module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
82515920
AV		 202uint ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, uint, S_IRUGO);
204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
1da177e4 221/*
fa2a1ce5 222 * SCSI host template entry points
1da177e4
LT		 223 */
224static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 225static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 226static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
227static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 228static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 229static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 230static int qla2xxx_eh_abort(struct scsi_cmnd *);
231static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 232static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 233static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
234static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 235
e881a172 236static int qla2x00_change_queue_depth(struct scsi_device *, int, int);
ce7e4af7 237static int qla2x00_change_queue_type(struct scsi_device *, int);
3491255e 238static void qla2x00_free_device(scsi_qla_host_t *);
ce7e4af7 239
a5326f86 240struct scsi_host_template qla2xxx_driver_template = {
1da177e4 241 .module = THIS_MODULE,
cb63067a 242 .name = QLA2XXX_DRIVER_NAME,
a5326f86 243 .queuecommand = qla2xxx_queuecommand,
fca29703
AV		 244
245 .eh_abort_handler = qla2xxx_eh_abort,
246 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 247 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 248 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
249 .eh_host_reset_handler = qla2xxx_eh_host_reset,
250
251 .slave_configure = qla2xxx_slave_configure,
252
253 .slave_alloc = qla2xxx_slave_alloc,
254 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 255 .scan_finished = qla2xxx_scan_finished,
256 .scan_start = qla2xxx_scan_start,
ce7e4af7
AV		 257 .change_queue_depth = qla2x00_change_queue_depth,
258 .change_queue_type = qla2x00_change_queue_type,
fca29703
AV		 259 .this_id = -1,
260 .cmd_per_lun = 3,
261 .use_clustering = ENABLE_CLUSTERING,
262 .sg_tablesize = SG_ALL,
263
264 .max_sectors = 0xFFFF,
afb046e2 265 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 266
267 .supported_mode = MODE_INITIATOR,
fca29703
AV		 268};
269
1da177e4 270static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 271struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 272
1da177e4
LT		 273/* TODO Convert to inlines
274 *
275 * Timer routines
276 */
1da177e4 277
2c3dfe3f 278__inline__ void
e315cd28 279qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 280{
e315cd28
AC		 281 init_timer(&vha->timer);
282 vha->timer.expires = jiffies + interval * HZ;
283 vha->timer.data = (unsigned long)vha;
284 vha->timer.function = (void (*)(unsigned long))func;
285 add_timer(&vha->timer);
286 vha->timer_active = 1;
1da177e4
LT		 287}
288
289static inline void
e315cd28 290qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 291{
a9083016 292 /* Currently used for 82XX only. */
7c3df132
SK		 293 if (vha->device_flags & DFLG_DEV_FAILED) {
294 ql_dbg(ql_dbg_timer, vha, 0x600d,
295 "Device in a failed state, returning.\n");
a9083016 296 return;
7c3df132 297 }
a9083016 298
e315cd28 299 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 300}
301
a824ebb3 302static __inline__ void
e315cd28 303qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 304{
e315cd28
AC		 305 del_timer_sync(&vha->timer);
306 vha->timer_active = 0;
1da177e4
LT		 307}
308
1da177e4
LT		 309static int qla2x00_do_dpc(void *data);
310
311static void qla2x00_rst_aen(scsi_qla_host_t *);
312
73208dfd
AC		 313static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
314 struct req_que **, struct rsp_que **);
e30d1756 315static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 316static void qla2x00_mem_free(struct qla_hw_data *);
1da177e4 317
1da177e4 318/* -------------------------------------------------------------------------- */
9a347ff4
CD		 319static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
320 struct rsp_que *rsp)
73208dfd 321{
7c3df132 322 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 323 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 324 GFP_KERNEL);
325 if (!ha->req_q_map) {
7c3df132
SK		 326 ql_log(ql_log_fatal, vha, 0x003b,
327 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 328 goto fail_req_map;
329 }
330
2afa19a9 331 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 332 GFP_KERNEL);
333 if (!ha->rsp_q_map) {
7c3df132
SK		 334 ql_log(ql_log_fatal, vha, 0x003c,
335 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 336 goto fail_rsp_map;
337 }
9a347ff4
CD		 338 /*
339 * Make sure we record at least the request and response queue zero in
340 * case we need to free them if part of the probe fails.
341 */
342 ha->rsp_q_map[0] = rsp;
343 ha->req_q_map[0] = req;
73208dfd
AC		 344 set_bit(0, ha->rsp_qid_map);
345 set_bit(0, ha->req_qid_map);
346 return 1;
347
348fail_rsp_map:
349 kfree(ha->req_q_map);
350 ha->req_q_map = NULL;
351fail_req_map:
352 return -ENOMEM;
353}
354
2afa19a9 355static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 356{
8ae6d9c7
GM		 357 if (IS_QLAFX00(ha)) {
358 if (req && req->ring_fx00)
359 dma_free_coherent(&ha->pdev->dev,
360 (req->length_fx00 + 1) * sizeof(request_t),
361 req->ring_fx00, req->dma_fx00);
362 } else if (req && req->ring)
73208dfd
AC		 363 dma_free_coherent(&ha->pdev->dev,
364 (req->length + 1) * sizeof(request_t),
365 req->ring, req->dma);
366
8d93f550
CD		 367 if (req)
368 kfree(req->outstanding_cmds);
369
73208dfd
AC		 370 kfree(req);
371 req = NULL;
372}
373
2afa19a9
AC		 374static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
375{
8ae6d9c7
GM		 376 if (IS_QLAFX00(ha)) {
377 if (rsp && rsp->ring)
378 dma_free_coherent(&ha->pdev->dev,
379 (rsp->length_fx00 + 1) * sizeof(request_t),
380 rsp->ring_fx00, rsp->dma_fx00);
381 } else if (rsp && rsp->ring) {
2afa19a9
AC		 382 dma_free_coherent(&ha->pdev->dev,
383 (rsp->length + 1) * sizeof(response_t),
384 rsp->ring, rsp->dma);
8ae6d9c7 385 }
2afa19a9
AC		 386 kfree(rsp);
387 rsp = NULL;
388}
389
73208dfd
AC		 390static void qla2x00_free_queues(struct qla_hw_data *ha)
391{
392 struct req_que *req;
393 struct rsp_que *rsp;
394 int cnt;
395
2afa19a9 396 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
73208dfd 397 req = ha->req_q_map[cnt];
2afa19a9 398 qla2x00_free_req_que(ha, req);
73208dfd 399 }
73208dfd
AC		 400 kfree(ha->req_q_map);
401 ha->req_q_map = NULL;
2afa19a9
AC		 402
403 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
404 rsp = ha->rsp_q_map[cnt];
405 qla2x00_free_rsp_que(ha, rsp);
406 }
407 kfree(ha->rsp_q_map);
408 ha->rsp_q_map = NULL;
73208dfd
AC		 409}
410
68ca949c
AC		 411static int qla25xx_setup_mode(struct scsi_qla_host *vha)
412{
413 uint16_t options = 0;
414 int ques, req, ret;
415 struct qla_hw_data *ha = vha->hw;
416
7163ea81 417 if (!(ha->fw_attributes & BIT_6)) {
7c3df132
SK		 418 ql_log(ql_log_warn, vha, 0x00d8,
419 "Firmware is not multi-queue capable.\n");
7163ea81
AC		 420 goto fail;
421 }
68ca949c 422 if (ql2xmultique_tag) {
68ca949c
AC		 423 /* create a request queue for IO */
424 options |= BIT_7;
425 req = qla25xx_create_req_que(ha, options, 0, 0, -1,
426 QLA_DEFAULT_QUE_QOS);
427 if (!req) {
7c3df132
SK		 428 ql_log(ql_log_warn, vha, 0x00e0,
429 "Failed to create request queue.\n");
68ca949c
AC		 430 goto fail;
431 }
278274d5 432 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
68ca949c
AC		 433 vha->req = ha->req_q_map[req];
434 options |= BIT_1;
435 for (ques = 1; ques < ha->max_rsp_queues; ques++) {
436 ret = qla25xx_create_rsp_que(ha, options, 0, 0, req);
437 if (!ret) {
7c3df132
SK		 438 ql_log(ql_log_warn, vha, 0x00e8,
439 "Failed to create response queue.\n");
68ca949c
AC		 440 goto fail2;
441 }
442 }
7163ea81 443 ha->flags.cpu_affinity_enabled = 1;
7c3df132
SK		 444 ql_dbg(ql_dbg_multiq, vha, 0xc007,
445 "CPU affinity mode enalbed, "
446 "no. of response queues:%d no. of request queues:%d.\n",
447 ha->max_rsp_queues, ha->max_req_queues);
448 ql_dbg(ql_dbg_init, vha, 0x00e9,
449 "CPU affinity mode enalbed, "
450 "no. of response queues:%d no. of request queues:%d.\n",
451 ha->max_rsp_queues, ha->max_req_queues);
68ca949c
AC		 452 }
453 return 0;
454fail2:
455 qla25xx_delete_queues(vha);
7163ea81
AC		 456 destroy_workqueue(ha->wq);
457 ha->wq = NULL;
0cd33fcf 458 vha->req = ha->req_q_map[0];
68ca949c
AC		 459fail:
460 ha->mqenable = 0;
7163ea81
AC		 461 kfree(ha->req_q_map);
462 kfree(ha->rsp_q_map);
463 ha->max_req_queues = ha->max_rsp_queues = 1;
68ca949c
AC		 464 return 1;
465}
466
1da177e4 467static char *
e315cd28 468qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 469{
e315cd28 470 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 471 static char *pci_bus_modes[] = {
472 "33", "66", "100", "133",
473 };
474 uint16_t pci_bus;
475
476 strcpy(str, "PCI");
477 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
478 if (pci_bus) {
479 strcat(str, "-X (");
480 strcat(str, pci_bus_modes[pci_bus]);
481 } else {
482 pci_bus = (ha->pci_attr & BIT_8) >> 8;
483 strcat(str, " (");
484 strcat(str, pci_bus_modes[pci_bus]);
485 }
486 strcat(str, " MHz)");
487
488 return (str);
489}
490
fca29703 491static char *
e315cd28 492qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 493{
494 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 495 struct qla_hw_data *ha = vha->hw;
fca29703
AV		 496 uint32_t pci_bus;
497 int pcie_reg;
498
e67f1321 499 pcie_reg = pci_pcie_cap(ha->pdev);
fca29703
AV		 500 if (pcie_reg) {
501 char lwstr[6];
502 uint16_t pcie_lstat, lspeed, lwidth;
503
e67f1321 504 pcie_reg += PCI_EXP_LNKCAP;
fca29703
AV		 505 pci_read_config_word(ha->pdev, pcie_reg, &pcie_lstat);
506 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
507 lwidth = (pcie_lstat &
508 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4;
509
510 strcpy(str, "PCIe (");
49300af7
SK		 511 switch (lspeed) {
512 case 1:
c87a0d8c 513 strcat(str, "2.5GT/s ");
49300af7
SK		 514 break;
515 case 2:
c87a0d8c 516 strcat(str, "5.0GT/s ");
49300af7
SK		 517 break;
518 case 3:
519 strcat(str, "8.0GT/s ");
520 break;
521 default:
fca29703 522 strcat(str, "<unknown> ");
49300af7
SK		 523 break;
524 }
fca29703
AV		 525 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
526 strcat(str, lwstr);
527
528 return str;
529 }
530
531 strcpy(str, "PCI");
532 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
533 if (pci_bus == 0 || pci_bus == 8) {
534 strcat(str, " (");
535 strcat(str, pci_bus_modes[pci_bus >> 3]);
536 } else {
537 strcat(str, "-X ");
538 if (pci_bus & BIT_2)
539 strcat(str, "Mode 2");
540 else
541 strcat(str, "Mode 1");
542 strcat(str, " (");
543 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
544 }
545 strcat(str, " MHz)");
546
547 return str;
548}
549
e5f82ab8 550static char *
e315cd28 551qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str)
1da177e4
LT		 552{
553 char un_str[10];
e315cd28 554 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 555
1da177e4
LT		 556 sprintf(str, "%d.%02d.%02d ", ha->fw_major_version,
557 ha->fw_minor_version,
558 ha->fw_subminor_version);
559
560 if (ha->fw_attributes & BIT_9) {
561 strcat(str, "FLX");
562 return (str);
563 }
564
565 switch (ha->fw_attributes & 0xFF) {
566 case 0x7:
567 strcat(str, "EF");
568 break;
569 case 0x17:
570 strcat(str, "TP");
571 break;
572 case 0x37:
573 strcat(str, "IP");
574 break;
575 case 0x77:
576 strcat(str, "VI");
577 break;
578 default:
579 sprintf(un_str, "(%x)", ha->fw_attributes);
580 strcat(str, un_str);
581 break;
582 }
583 if (ha->fw_attributes & 0x100)
584 strcat(str, "X");
585
586 return (str);
587}
588
e5f82ab8 589static char *
e315cd28 590qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str)
fca29703 591{
e315cd28 592 struct qla_hw_data *ha = vha->hw;
f0883ac6 593
3a03eb79
AV		 594 sprintf(str, "%d.%02d.%02d (%x)", ha->fw_major_version,
595 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 596 return str;
fca29703
AV		 597}
598
9ba56b95
GM		 599void
600qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 601{
9ba56b95
GM		 602 srb_t *sp = (srb_t *)ptr;
603 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
604 struct qla_hw_data *ha = sp->fcport->vha->hw;
605 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 606
9ba56b95
GM		 607 if (sp->flags & SRB_DMA_VALID) {
608 scsi_dma_unmap(cmd);
609 sp->flags &= ~SRB_DMA_VALID;
7c3df132 610 }
fca29703 611
9ba56b95
GM		 612 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
613 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
614 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
615 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
616 }
617
618 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
619 /* List assured to be having elements */
620 qla2x00_clean_dsd_pool(ha, sp);
621 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
622 }
623
624 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
625 dma_pool_free(ha->dl_dma_pool, ctx,
626 ((struct crc_context *)ctx)->crc_ctx_dma);
627 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
628 }
629
630 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
631 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 632
9ba56b95
GM		 633 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
634 ctx1->fcp_cmnd_dma);
635 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
636 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
637 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
638 mempool_free(ctx1, ha->ctx_mempool);
639 ctx1 = NULL;
640 }
641
642 CMD_SP(cmd) = NULL;
b00ee7d7 643 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 644}
645
14b06808 646static void
9ba56b95
GM		 647qla2x00_sp_compl(void *data, void *ptr, int res)
648{
649 struct qla_hw_data *ha = (struct qla_hw_data *)data;
650 srb_t *sp = (srb_t *)ptr;
651 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
652
653 cmd->result = res;
654
655 if (atomic_read(&sp->ref_count) == 0) {
656 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
657 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
658 sp, GET_CMD_SP(sp));
659 if (ql2xextended_error_logging & ql_dbg_io)
660 BUG();
661 return;
662 }
663 if (!atomic_dec_and_test(&sp->ref_count))
664 return;
665
666 qla2x00_sp_free_dma(ha, sp);
667 cmd->scsi_done(cmd);
fca29703
AV		 668}
669
8ae6d9c7
GM		 670/* If we are SP1 here, we need to still take and release the host_lock as SP1
671 * does not have the changes necessary to avoid taking host->host_lock.
672 */
1da177e4 673static int
f5e3e40b 674qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 675{
134ae078 676 scsi_qla_host_t *vha = shost_priv(host);
fca29703 677 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 678 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 679 struct qla_hw_data *ha = vha->hw;
680 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 681 srb_t *sp;
682 int rval;
683
85880801 684 if (ha->flags.eeh_busy) {
7c3df132 685 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 686 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 687 "PCI Channel IO permanent failure, exiting "
688 "cmd=%p.\n", cmd);
b9b12f73 689 cmd->result = DID_NO_CONNECT << 16;
7c3df132 690 } else {
5f28d2d7 691 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 692 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 693 cmd->result = DID_REQUEUE << 16;
7c3df132 694 }
14e660e6
SJ		 695 goto qc24_fail_command;
696 }
697
19a7b4ae
JSEC		 698 rval = fc_remote_port_chkready(rport);
699 if (rval) {
700 cmd->result = rval;
5f28d2d7 701 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 702 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
703 cmd, rval);
fca29703
AV		 704 goto qc24_fail_command;
705 }
706
bad75002
AE		 707 if (!vha->flags.difdix_supported &&
708 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 709 ql_dbg(ql_dbg_io, vha, 0x3004,
710 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
711 cmd);
bad75002
AE		 712 cmd->result = DID_NO_CONNECT << 16;
713 goto qc24_fail_command;
714 }
aa651be8
CD		 715
716 if (!fcport) {
717 cmd->result = DID_NO_CONNECT << 16;
718 goto qc24_fail_command;
719 }
720
fca29703
AV		 721 if (atomic_read(&fcport->state) != FCS_ONLINE) {
722 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 723 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 724 ql_dbg(ql_dbg_io, vha, 0x3005,
725 "Returning DNC, fcport_state=%d loop_state=%d.\n",
726 atomic_read(&fcport->state),
727 atomic_read(&base_vha->loop_state));
fca29703
AV		 728 cmd->result = DID_NO_CONNECT << 16;
729 goto qc24_fail_command;
730 }
7b594131 731 goto qc24_target_busy;
fca29703
AV		 732 }
733
b00ee7d7 734 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
3c290d0b
CD		 735 if (!sp) {
736 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
f5e3e40b 737 goto qc24_host_busy;
3c290d0b 738 }
fca29703 739
9ba56b95
GM		 740 sp->u.scmd.cmd = cmd;
741 sp->type = SRB_SCSI_CMD;
742 atomic_set(&sp->ref_count, 1);
743 CMD_SP(cmd) = (void *)sp;
744 sp->free = qla2x00_sp_free_dma;
745 sp->done = qla2x00_sp_compl;
746
e315cd28 747 rval = ha->isp_ops->start_scsi(sp);
7c3df132 748 if (rval != QLA_SUCCESS) {
53016ed3 749 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 750 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
3c290d0b 751 set_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags);
fca29703 752 goto qc24_host_busy_free_sp;
7c3df132 753 }
fca29703 754
fca29703
AV		 755 return 0;
756
757qc24_host_busy_free_sp:
9ba56b95 758 qla2x00_sp_free_dma(ha, sp);
fca29703 759
f5e3e40b 760qc24_host_busy:
fca29703
AV		 761 return SCSI_MLQUEUE_HOST_BUSY;
762
7b594131
MC		 763qc24_target_busy:
764 return SCSI_MLQUEUE_TARGET_BUSY;
765
fca29703 766qc24_fail_command:
f5e3e40b 767 cmd->scsi_done(cmd);
fca29703
AV		 768
769 return 0;
770}
771
1da177e4
LT		 772/*
773 * qla2x00_eh_wait_on_command
774 * Waits for the command to be returned by the Firmware for some
775 * max time.
776 *
777 * Input:
1da177e4 778 * cmd = Scsi Command to wait on.
1da177e4
LT		 779 *
780 * Return:
781 * Not Found : 0
782 * Found : 1
783 */
784static int
e315cd28 785qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 786{
fe74c71f
AV		 787#define ABORT_POLLING_PERIOD 1000
788#define ABORT_WAIT_ITER ((10 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 789 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 790 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
791 struct qla_hw_data *ha = vha->hw;
f4f051eb 792 int ret = QLA_SUCCESS;
1da177e4 793
85880801 794 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 795 ql_dbg(ql_dbg_taskm, vha, 0x8005,
796 "Return:eh_wait.\n");
85880801
AV		 797 return ret;
798 }
799
d970432c 800 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 801 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 802 }
803 if (CMD_SP(cmd))
804 ret = QLA_FUNCTION_FAILED;
1da177e4 805
f4f051eb 806 return ret;
1da177e4
LT		 807}
808
809/*
810 * qla2x00_wait_for_hba_online
fa2a1ce5 811 * Wait till the HBA is online after going through
1da177e4
LT		 812 * <= MAX_RETRIES_OF_ISP_ABORT or
813 * finally HBA is disabled ie marked offline
814 *
815 * Input:
816 * ha - pointer to host adapter structure
fa2a1ce5
AV		 817 *
818 * Note:
1da177e4
LT		 819 * Does context switching-Release SPIN_LOCK
820 * (if any) before calling this routine.
821 *
822 * Return:
823 * Success (Adapter is online) : 0
824 * Failed (Adapter is offline/disabled) : 1
825 */
854165f4 826int
e315cd28 827qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 828{
fca29703
AV		 829 int return_status;
830 unsigned long wait_online;
e315cd28
AC		 831 struct qla_hw_data *ha = vha->hw;
832 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 833
fa2a1ce5 834 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 835 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
836 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
837 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
838 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 839
840 msleep(1000);
841 }
e315cd28 842 if (base_vha->flags.online)
fa2a1ce5 843 return_status = QLA_SUCCESS;
1da177e4
LT		 844 else
845 return_status = QLA_FUNCTION_FAILED;
846
1da177e4
LT		 847 return (return_status);
848}
849
86fbee86
LC		 850/*
851 * qla2x00_wait_for_reset_ready
852 * Wait till the HBA is online after going through
853 * <= MAX_RETRIES_OF_ISP_ABORT or
854 * finally HBA is disabled ie marked offline or flash
855 * operations are in progress.
856 *
857 * Input:
858 * ha - pointer to host adapter structure
859 *
860 * Note:
861 * Does context switching-Release SPIN_LOCK
862 * (if any) before calling this routine.
863 *
864 * Return:
865 * Success (Adapter is online/no flash ops) : 0
866 * Failed (Adapter is offline/disabled/flash ops in progress) : 1
867 */
3dbe756a 868static int
86fbee86
LC		 869qla2x00_wait_for_reset_ready(scsi_qla_host_t *vha)
870{
871 int return_status;
872 unsigned long wait_online;
873 struct qla_hw_data *ha = vha->hw;
874 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
875
876 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
877 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
878 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
879 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
880 ha->optrom_state != QLA_SWAITING ||
881 ha->dpc_active) && time_before(jiffies, wait_online))
882 msleep(1000);
883
884 if (base_vha->flags.online && ha->optrom_state == QLA_SWAITING)
885 return_status = QLA_SUCCESS;
886 else
887 return_status = QLA_FUNCTION_FAILED;
888
7c3df132
SK		 889 ql_dbg(ql_dbg_taskm, vha, 0x8019,
890 "%s return status=%d.\n", __func__, return_status);
86fbee86
LC		 891
892 return return_status;
893}
894
2533cf67
LC		 895int
896qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
897{
898 int return_status;
899 unsigned long wait_reset;
900 struct qla_hw_data *ha = vha->hw;
901 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
902
903 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
904 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
905 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
906 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
907 ha->dpc_active) && time_before(jiffies, wait_reset)) {
908
909 msleep(1000);
910
911 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
912 ha->flags.chip_reset_done)
913 break;
914 }
915 if (ha->flags.chip_reset_done)
916 return_status = QLA_SUCCESS;
917 else
918 return_status = QLA_FUNCTION_FAILED;
919
920 return return_status;
921}
922
083a469d
GM		 923static void
924sp_get(struct srb *sp)
925{
926 atomic_inc(&sp->ref_count);
927}
928
1da177e4
LT		 929/**************************************************************************
930* qla2xxx_eh_abort
931*
932* Description:
933* The abort function will abort the specified command.
934*
935* Input:
936* cmd = Linux SCSI command packet to be aborted.
937*
938* Returns:
939* Either SUCCESS or FAILED.
940*
941* Note:
2ea00202 942* Only return FAILED if command not returned by firmware.
1da177e4 943**************************************************************************/
e5f82ab8 944static int
1da177e4
LT		 945qla2xxx_eh_abort(struct scsi_cmnd *cmd)
946{
e315cd28 947 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 948 srb_t *sp;
4e98d3b8 949 int ret;
f4f051eb 950 unsigned int id, lun;
18e144d3 951 unsigned long flags;
2ea00202 952 int wait = 0;
e315cd28 953 struct qla_hw_data *ha = vha->hw;
1da177e4 954
f4f051eb 955 if (!CMD_SP(cmd))
2ea00202 956 return SUCCESS;
1da177e4 957
4e98d3b8
AV		 958 ret = fc_block_scsi_eh(cmd);
959 if (ret != 0)
960 return ret;
961 ret = SUCCESS;
962
f4f051eb
AV		 963 id = cmd->device->id;
964 lun = cmd->device->lun;
1da177e4 965
e315cd28 966 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 967 sp = (srb_t *) CMD_SP(cmd);
968 if (!sp) {
969 spin_unlock_irqrestore(&ha->hardware_lock, flags);
970 return SUCCESS;
971 }
1da177e4 972
7c3df132 973 ql_dbg(ql_dbg_taskm, vha, 0x8002,
cfb0919c
CD		 974 "Aborting from RISC nexus=%ld:%d:%d sp=%p cmd=%p\n",
975 vha->host_no, id, lun, sp, cmd);
17d98630 976
170babc3
MC		 977 /* Get a reference to the sp and drop the lock.*/
978 sp_get(sp);
083a469d 979
e315cd28 980 spin_unlock_irqrestore(&ha->hardware_lock, flags);
170babc3 981 if (ha->isp_ops->abort_command(sp)) {
a55aac79 982 ret = FAILED;
7c3df132 983 ql_dbg(ql_dbg_taskm, vha, 0x8003,
cfb0919c 984 "Abort command mbx failed cmd=%p.\n", cmd);
170babc3 985 } else {
7c3df132 986 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 987 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 988 wait = 1;
989 }
75942064
SK		 990
991 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 992 sp->done(ha, sp, 0);
75942064 993 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 994
bc91ade9
CD		 995 /* Did the command return during mailbox execution? */
996 if (ret == FAILED && !CMD_SP(cmd))
997 ret = SUCCESS;
998
f4f051eb 999 /* Wait for the command to be returned. */
2ea00202 1000 if (wait) {
e315cd28 1001 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1002 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1003 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1004 ret = FAILED;
f4f051eb 1005 }
1da177e4 1006 }
1da177e4 1007
7c3df132 1008 ql_log(ql_log_info, vha, 0x801c,
cfb0919c
CD		 1009 "Abort command issued nexus=%ld:%d:%d -- %d %x.\n",
1010 vha->host_no, id, lun, wait, ret);
1da177e4 1011
f4f051eb
AV		 1012 return ret;
1013}
1da177e4 1014
4d78c973 1015int
e315cd28 1016qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
4d78c973 1017 unsigned int l, enum nexus_wait_type type)
f4f051eb 1018{
17d98630 1019 int cnt, match, status;
18e144d3 1020 unsigned long flags;
e315cd28 1021 struct qla_hw_data *ha = vha->hw;
73208dfd 1022 struct req_que *req;
4d78c973 1023 srb_t *sp;
9ba56b95 1024 struct scsi_cmnd *cmd;
1da177e4 1025
523ec773 1026 status = QLA_SUCCESS;
17d98630 1027
e315cd28 1028 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1029 req = vha->req;
17d98630 1030 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1031 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1032 sp = req->outstanding_cmds[cnt];
1033 if (!sp)
523ec773 1034 continue;
9ba56b95 1035 if (sp->type != SRB_SCSI_CMD)
cf53b069 1036 continue;
17d98630
AC		 1037 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1038 continue;
1039 match = 0;
9ba56b95 1040 cmd = GET_CMD_SP(sp);
17d98630
AC		 1041 switch (type) {
1042 case WAIT_HOST:
1043 match = 1;
1044 break;
1045 case WAIT_TARGET:
9ba56b95 1046 match = cmd->device->id == t;
17d98630
AC		 1047 break;
1048 case WAIT_LUN:
9ba56b95
GM		 1049 match = (cmd->device->id == t &&
1050 cmd->device->lun == l);
17d98630 1051 break;
73208dfd 1052 }
17d98630
AC		 1053 if (!match)
1054 continue;
1055
1056 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1057 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1058 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1059 }
e315cd28 1060 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1061
1062 return status;
1da177e4
LT		 1063}
1064
523ec773
AV		 1065static char *reset_errors[] = {
1066 "HBA not online",
1067 "HBA not ready",
1068 "Task management failed",
1069 "Waiting for command completions",
1070};
1da177e4 1071
e5f82ab8 1072static int
523ec773 1073__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
2afa19a9 1074 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, unsigned int, int))
1da177e4 1075{
e315cd28 1076 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1077 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1078 int err;
1da177e4 1079
7c3df132 1080 if (!fcport) {
523ec773 1081 return FAILED;
7c3df132 1082 }
1da177e4 1083
4e98d3b8
AV		 1084 err = fc_block_scsi_eh(cmd);
1085 if (err != 0)
1086 return err;
1087
7c3df132 1088 ql_log(ql_log_info, vha, 0x8009,
cfb0919c 1089 "%s RESET ISSUED nexus=%ld:%d:%d cmd=%p.\n", name, vha->host_no,
7c3df132 1090 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1091
523ec773 1092 err = 0;
7c3df132
SK		 1093 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1094 ql_log(ql_log_warn, vha, 0x800a,
1095 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1096 goto eh_reset_failed;
7c3df132 1097 }
523ec773 1098 err = 2;
2afa19a9 1099 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1100 != QLA_SUCCESS) {
1101 ql_log(ql_log_warn, vha, 0x800c,
1102 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1103 goto eh_reset_failed;
7c3df132 1104 }
523ec773 1105 err = 3;
e315cd28 1106 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1107 cmd->device->lun, type) != QLA_SUCCESS) {
1108 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1109 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1110 goto eh_reset_failed;
7c3df132 1111 }
523ec773 1112
7c3df132 1113 ql_log(ql_log_info, vha, 0x800e,
cfb0919c
CD		 1114 "%s RESET SUCCEEDED nexus:%ld:%d:%d cmd=%p.\n", name,
1115 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1116
1117 return SUCCESS;
1118
4d78c973 1119eh_reset_failed:
7c3df132 1120 ql_log(ql_log_info, vha, 0x800f,
cfb0919c
CD		 1121 "%s RESET FAILED: %s nexus=%ld:%d:%d cmd=%p.\n", name,
1122 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1123 cmd);
523ec773
AV		 1124 return FAILED;
1125}
1da177e4 1126
523ec773
AV		 1127static int
1128qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1129{
e315cd28
AC		 1130 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1131 struct qla_hw_data *ha = vha->hw;
1da177e4 1132
523ec773
AV		 1133 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1134 ha->isp_ops->lun_reset);
1da177e4
LT		 1135}
1136
1da177e4 1137static int
523ec773 1138qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1139{
e315cd28
AC		 1140 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1141 struct qla_hw_data *ha = vha->hw;
1da177e4 1142
523ec773
AV		 1143 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1144 ha->isp_ops->target_reset);
1da177e4
LT		 1145}
1146
1da177e4
LT		 1147/**************************************************************************
1148* qla2xxx_eh_bus_reset
1149*
1150* Description:
1151* The bus reset function will reset the bus and abort any executing
1152* commands.
1153*
1154* Input:
1155* cmd = Linux SCSI command packet of the command that cause the
1156* bus reset.
1157*
1158* Returns:
1159* SUCCESS/FAILURE (defined as macro in scsi.h).
1160*
1161**************************************************************************/
e5f82ab8 1162static int
1da177e4
LT		 1163qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1164{
e315cd28 1165 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1166 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1167 int ret = FAILED;
f4f051eb 1168 unsigned int id, lun;
f4f051eb 1169
f4f051eb
AV		 1170 id = cmd->device->id;
1171 lun = cmd->device->lun;
1da177e4 1172
7c3df132 1173 if (!fcport) {
f4f051eb 1174 return ret;
7c3df132 1175 }
1da177e4 1176
4e98d3b8
AV		 1177 ret = fc_block_scsi_eh(cmd);
1178 if (ret != 0)
1179 return ret;
1180 ret = FAILED;
1181
7c3df132 1182 ql_log(ql_log_info, vha, 0x8012,
46270afe 1183 "BUS RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1184
e315cd28 1185 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1186 ql_log(ql_log_fatal, vha, 0x8013,
1187 "Wait for hba online failed board disabled.\n");
f4f051eb 1188 goto eh_bus_reset_done;
1da177e4
LT		 1189 }
1190
ad537689
SK		 1191 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1192 ret = SUCCESS;
1193
f4f051eb
AV		 1194 if (ret == FAILED)
1195 goto eh_bus_reset_done;
1da177e4 1196
9a41a62b 1197 /* Flush outstanding commands. */
4d78c973 1198 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1199 QLA_SUCCESS) {
1200 ql_log(ql_log_warn, vha, 0x8014,
1201 "Wait for pending commands failed.\n");
9a41a62b 1202 ret = FAILED;
7c3df132 1203 }
1da177e4 1204
f4f051eb 1205eh_bus_reset_done:
7c3df132 1206 ql_log(ql_log_warn, vha, 0x802b,
cfb0919c 1207 "BUS RESET %s nexus=%ld:%d:%d.\n",
d6a03581 1208 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1209
f4f051eb 1210 return ret;
1da177e4
LT		 1211}
1212
1213/**************************************************************************
1214* qla2xxx_eh_host_reset
1215*
1216* Description:
1217* The reset function will reset the Adapter.
1218*
1219* Input:
1220* cmd = Linux SCSI command packet of the command that cause the
1221* adapter reset.
1222*
1223* Returns:
1224* Either SUCCESS or FAILED.
1225*
1226* Note:
1227**************************************************************************/
e5f82ab8 1228static int
1da177e4
LT		 1229qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1230{
e315cd28 1231 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1232 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1233 int ret = FAILED;
f4f051eb 1234 unsigned int id, lun;
e315cd28 1235 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1236
f4f051eb
AV		 1237 id = cmd->device->id;
1238 lun = cmd->device->lun;
f4f051eb 1239
7c3df132 1240 ql_log(ql_log_info, vha, 0x8018,
cfb0919c 1241 "ADAPTER RESET ISSUED nexus=%ld:%d:%d.\n", vha->host_no, id, lun);
1da177e4 1242
86fbee86 1243 if (qla2x00_wait_for_reset_ready(vha) != QLA_SUCCESS)
f4f051eb 1244 goto eh_host_reset_lock;
1da177e4 1245
e315cd28
AC		 1246 if (vha != base_vha) {
1247 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1248 goto eh_host_reset_lock;
e315cd28 1249 } else {
7ec0effd 1250 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1251 if (!qla82xx_fcoe_ctx_reset(vha)) {
1252 /* Ctx reset success */
1253 ret = SUCCESS;
1254 goto eh_host_reset_lock;
1255 }
1256 /* fall thru if ctx reset failed */
1257 }
68ca949c
AC		 1258 if (ha->wq)
1259 flush_workqueue(ha->wq);
1260
e315cd28 1261 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1262 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1263 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1264 /* failed. schedule dpc to try */
1265 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1266
7c3df132
SK		 1267 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1268 ql_log(ql_log_warn, vha, 0x802a,
1269 "wait for hba online failed.\n");
e315cd28 1270 goto eh_host_reset_lock;
7c3df132 1271 }
e315cd28
AC		 1272 }
1273 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1274 }
1da177e4 1275
e315cd28 1276 /* Waiting for command to be returned to OS.*/
4d78c973 1277 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1278 QLA_SUCCESS)
f4f051eb 1279 ret = SUCCESS;
1da177e4 1280
f4f051eb 1281eh_host_reset_lock:
cfb0919c
CD		 1282 ql_log(ql_log_info, vha, 0x8017,
1283 "ADAPTER RESET %s nexus=%ld:%d:%d.\n",
1284 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1285
f4f051eb
AV		 1286 return ret;
1287}
1da177e4
LT		 1288
1289/*
1290* qla2x00_loop_reset
1291* Issue loop reset.
1292*
1293* Input:
1294* ha = adapter block pointer.
1295*
1296* Returns:
1297* 0 = success
1298*/
a4722cf2 1299int
e315cd28 1300qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1301{
0c8c39af 1302 int ret;
bdf79621 1303 struct fc_port *fcport;
e315cd28 1304 struct qla_hw_data *ha = vha->hw;
1da177e4 1305
f4c496c1 1306 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1307 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1308 if (fcport->port_type != FCT_TARGET)
1309 continue;
1310
1311 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1312 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1313 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1314 "Bus Reset failed: Target Reset=%d "
1315 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1316 }
1317 }
1318 }
1319
8ae6d9c7
GM		 1320 if (IS_QLAFX00(ha))
1321 return QLA_SUCCESS;
1322
6246b8a1 1323 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1324 atomic_set(&vha->loop_state, LOOP_DOWN);
1325 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1326 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1327 ret = qla2x00_full_login_lip(vha);
0c8c39af 1328 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1329 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1330 "full_login_lip=%d.\n", ret);
749af3d5 1331 }
0c8c39af
AV		 1332 }
1333
0d6e61bc 1334 if (ha->flags.enable_lip_reset) {
e315cd28 1335 ret = qla2x00_lip_reset(vha);
ad537689 1336 if (ret != QLA_SUCCESS)
7c3df132
SK		 1337 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1338 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1339 }
1340
1da177e4 1341 /* Issue marker command only when we are going to start the I/O */
e315cd28 1342 vha->marker_needed = 1;
1da177e4 1343
0c8c39af 1344 return QLA_SUCCESS;
1da177e4
LT		 1345}
1346
df4bf0bb 1347void
e315cd28 1348qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1349{
73208dfd 1350 int que, cnt;
df4bf0bb
AV		 1351 unsigned long flags;
1352 srb_t *sp;
e315cd28 1353 struct qla_hw_data *ha = vha->hw;
73208dfd 1354 struct req_que *req;
df4bf0bb
AV		 1355
1356 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1357 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1358 req = ha->req_q_map[que];
73208dfd
AC		 1359 if (!req)
1360 continue;
8d93f550
CD		 1361 if (!req->outstanding_cmds)
1362 continue;
1363 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1364 sp = req->outstanding_cmds[cnt];
e612d465 1365 if (sp) {
73208dfd 1366 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1367 sp->done(vha, sp, res);
73208dfd 1368 }
df4bf0bb
AV		 1369 }
1370 }
1371 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1372}
1373
f4f051eb
AV		 1374static int
1375qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1376{
bdf79621 1377 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1378
19a7b4ae 1379 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1380 return -ENXIO;
bdf79621 1381
19a7b4ae 1382 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1383
f4f051eb
AV		 1384 return 0;
1385}
1da177e4 1386
f4f051eb
AV		 1387static int
1388qla2xxx_slave_configure(struct scsi_device *sdev)
1389{
e315cd28 1390 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1391 struct req_que *req = vha->req;
8482e118 1392
9e522cd8
AE		 1393 if (IS_T10_PI_CAPABLE(vha->hw))
1394 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1395
f4f051eb 1396 if (sdev->tagged_supported)
73208dfd 1397 scsi_activate_tcq(sdev, req->max_q_depth);
f4f051eb 1398 else
73208dfd 1399 scsi_deactivate_tcq(sdev, req->max_q_depth);
f4f051eb
AV		 1400 return 0;
1401}
1da177e4 1402
f4f051eb
AV		 1403static void
1404qla2xxx_slave_destroy(struct scsi_device *sdev)
1405{
1406 sdev->hostdata = NULL;
1da177e4
LT		 1407}
1408
c45dd305
GM		 1409static void qla2x00_handle_queue_full(struct scsi_device *sdev, int qdepth)
1410{
1411 fc_port_t *fcport = (struct fc_port *) sdev->hostdata;
1412
1413 if (!scsi_track_queue_full(sdev, qdepth))
1414 return;
1415
7c3df132 1416 ql_dbg(ql_dbg_io, fcport->vha, 0x3029,
cfb0919c
CD		 1417 "Queue depth adjusted-down to %d for nexus=%ld:%d:%d.\n",
1418 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1419}
1420
1421static void qla2x00_adjust_sdev_qdepth_up(struct scsi_device *sdev, int qdepth)
1422{
1423 fc_port_t *fcport = sdev->hostdata;
1424 struct scsi_qla_host *vha = fcport->vha;
c45dd305
GM		 1425 struct req_que *req = NULL;
1426
1427 req = vha->req;
1428 if (!req)
1429 return;
1430
1431 if (req->max_q_depth <= sdev->queue_depth || req->max_q_depth < qdepth)
1432 return;
1433
1434 if (sdev->ordered_tags)
1435 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, qdepth);
1436 else
1437 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, qdepth);
1438
7c3df132 1439 ql_dbg(ql_dbg_io, vha, 0x302a,
cfb0919c
CD		 1440 "Queue depth adjusted-up to %d for nexus=%ld:%d:%d.\n",
1441 sdev->queue_depth, fcport->vha->host_no, sdev->id, sdev->lun);
c45dd305
GM		 1442}
1443
ce7e4af7 1444static int
e881a172 1445qla2x00_change_queue_depth(struct scsi_device *sdev, int qdepth, int reason)
ce7e4af7 1446{
c45dd305
GM		 1447 switch (reason) {
1448 case SCSI_QDEPTH_DEFAULT:
1449 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
1450 break;
1451 case SCSI_QDEPTH_QFULL:
1452 qla2x00_handle_queue_full(sdev, qdepth);
1453 break;
1454 case SCSI_QDEPTH_RAMP_UP:
1455 qla2x00_adjust_sdev_qdepth_up(sdev, qdepth);
1456 break;
1457 default:
08002af2 1458 return -EOPNOTSUPP;
c45dd305 1459 }
e881a172 1460
ce7e4af7
AV		 1461 return sdev->queue_depth;
1462}
1463
1464static int
1465qla2x00_change_queue_type(struct scsi_device *sdev, int tag_type)
1466{
1467 if (sdev->tagged_supported) {
1468 scsi_set_tag_type(sdev, tag_type);
1469 if (tag_type)
1470 scsi_activate_tcq(sdev, sdev->queue_depth);
1471 else
1472 scsi_deactivate_tcq(sdev, sdev->queue_depth);
1473 } else
1474 tag_type = 0;
1475
1476 return tag_type;
1477}
1478
3c290d0b
CD		 1479static void
1480qla2x00_host_ramp_down_queuedepth(scsi_qla_host_t *vha)
1481{
1482 scsi_qla_host_t *vp;
1483 struct Scsi_Host *shost;
1484 struct scsi_device *sdev;
1485 struct qla_hw_data *ha = vha->hw;
1486 unsigned long flags;
1487
1488 ha->host_last_rampdown_time = jiffies;
1489
1490 if (ha->cfg_lun_q_depth <= vha->host->cmd_per_lun)
1491 return;
1492
1493 if ((ha->cfg_lun_q_depth / 2) < vha->host->cmd_per_lun)
1494 ha->cfg_lun_q_depth = vha->host->cmd_per_lun;
1495 else
1496 ha->cfg_lun_q_depth = ha->cfg_lun_q_depth / 2;
1497
1498 /*
1499 * Geometrically ramp down the queue depth for all devices on this
1500 * adapter
1501 */
1502 spin_lock_irqsave(&ha->vport_slock, flags);
1503 list_for_each_entry(vp, &ha->vp_list, list) {
1504 shost = vp->host;
1505 shost_for_each_device(sdev, shost) {
1506 if (sdev->queue_depth > shost->cmd_per_lun) {
1507 if (sdev->queue_depth < ha->cfg_lun_q_depth)
1508 continue;
1509 ql_log(ql_log_warn, vp, 0x3031,
1510 "%ld:%d:%d: Ramping down queue depth to %d",
1511 vp->host_no, sdev->id, sdev->lun,
1512 ha->cfg_lun_q_depth);
1513 qla2x00_change_queue_depth(sdev,
1514 ha->cfg_lun_q_depth, SCSI_QDEPTH_DEFAULT);
1515 }
1516 }
1517 }
1518 spin_unlock_irqrestore(&ha->vport_slock, flags);
1519
1520 return;
1521}
1522
1523static void
1524qla2x00_host_ramp_up_queuedepth(scsi_qla_host_t *vha)
1525{
1526 scsi_qla_host_t *vp;
1527 struct Scsi_Host *shost;
1528 struct scsi_device *sdev;
1529 struct qla_hw_data *ha = vha->hw;
1530 unsigned long flags;
1531
1532 ha->host_last_rampup_time = jiffies;
1533 ha->cfg_lun_q_depth++;
1534
1535 /*
1536 * Linearly ramp up the queue depth for all devices on this
1537 * adapter
1538 */
1539 spin_lock_irqsave(&ha->vport_slock, flags);
1540 list_for_each_entry(vp, &ha->vp_list, list) {
1541 shost = vp->host;
1542 shost_for_each_device(sdev, shost) {
1543 if (sdev->queue_depth > ha->cfg_lun_q_depth)
1544 continue;
1545 qla2x00_change_queue_depth(sdev, ha->cfg_lun_q_depth,
1546 SCSI_QDEPTH_RAMP_UP);
1547 }
1548 }
1549 spin_unlock_irqrestore(&ha->vport_slock, flags);
1550
1551 return;
1552}
1553
1da177e4
LT		 1554/**
1555 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1556 * @ha: HA context
1557 *
1558 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1559 * supported addressing method.
1560 */
1561static void
53303c42 1562qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1563{
7524f9b9 1564 /* Assume a 32bit DMA mask. */
1da177e4 1565 ha->flags.enable_64bit_addressing = 0;
1da177e4 1566
6a35528a 1567 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1568 /* Any upper-dword bits set? */
1569 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1570 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1571 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1572 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1573 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1574 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1575 return;
1da177e4 1576 }
1da177e4 1577 }
7524f9b9 1578
284901a9
YH		 1579 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1580 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1581}
1582
fd34f556 1583static void
e315cd28 1584qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1585{
1586 unsigned long flags = 0;
1587 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1588
1589 spin_lock_irqsave(&ha->hardware_lock, flags);
1590 ha->interrupts_on = 1;
1591 /* enable risc and host interrupts */
1592 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1593 RD_REG_WORD(&reg->ictrl);
1594 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1595
1596}
1597
1598static void
e315cd28 1599qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1600{
1601 unsigned long flags = 0;
1602 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1603
1604 spin_lock_irqsave(&ha->hardware_lock, flags);
1605 ha->interrupts_on = 0;
1606 /* disable risc and host interrupts */
1607 WRT_REG_WORD(&reg->ictrl, 0);
1608 RD_REG_WORD(&reg->ictrl);
1609 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1610}
1611
1612static void
e315cd28 1613qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1614{
1615 unsigned long flags = 0;
1616 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1617
1618 spin_lock_irqsave(&ha->hardware_lock, flags);
1619 ha->interrupts_on = 1;
1620 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1621 RD_REG_DWORD(&reg->ictrl);
1622 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1623}
1624
1625static void
e315cd28 1626qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1627{
1628 unsigned long flags = 0;
1629 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1630
124f85e6
AV		 1631 if (IS_NOPOLLING_TYPE(ha))
1632 return;
fd34f556
AV		 1633 spin_lock_irqsave(&ha->hardware_lock, flags);
1634 ha->interrupts_on = 0;
1635 WRT_REG_DWORD(&reg->ictrl, 0);
1636 RD_REG_DWORD(&reg->ictrl);
1637 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1638}
1639
706f457d
GM		 1640static int
1641qla2x00_iospace_config(struct qla_hw_data *ha)
1642{
1643 resource_size_t pio;
1644 uint16_t msix;
1645 int cpus;
1646
706f457d
GM		 1647 if (pci_request_selected_regions(ha->pdev, ha->bars,
1648 QLA2XXX_DRIVER_NAME)) {
1649 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1650 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1651 pci_name(ha->pdev));
1652 goto iospace_error_exit;
1653 }
1654 if (!(ha->bars & 1))
1655 goto skip_pio;
1656
1657 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1658 pio = pci_resource_start(ha->pdev, 0);
1659 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1660 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1661 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1662 "Invalid pci I/O region size (%s).\n",
1663 pci_name(ha->pdev));
1664 pio = 0;
1665 }
1666 } else {
1667 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1668 "Region #0 no a PIO resource (%s).\n",
1669 pci_name(ha->pdev));
1670 pio = 0;
1671 }
1672 ha->pio_address = pio;
1673 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1674 "PIO address=%llu.\n",
1675 (unsigned long long)ha->pio_address);
1676
1677skip_pio:
1678 /* Use MMIO operations for all accesses. */
1679 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1680 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1681 "Region #1 not an MMIO resource (%s), aborting.\n",
1682 pci_name(ha->pdev));
1683 goto iospace_error_exit;
1684 }
1685 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1686 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1687 "Invalid PCI mem region size (%s), aborting.\n",
1688 pci_name(ha->pdev));
1689 goto iospace_error_exit;
1690 }
1691
1692 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1693 if (!ha->iobase) {
1694 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1695 "Cannot remap MMIO (%s), aborting.\n",
1696 pci_name(ha->pdev));
1697 goto iospace_error_exit;
1698 }
1699
1700 /* Determine queue resources */
1701 ha->max_req_queues = ha->max_rsp_queues = 1;
1702 if ((ql2xmaxqueues <= 1 && !ql2xmultique_tag) ||
1703 (ql2xmaxqueues > 1 && ql2xmultique_tag) ||
1704 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
1705 goto mqiobase_exit;
1706
1707 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1708 pci_resource_len(ha->pdev, 3));
1709 if (ha->mqiobase) {
1710 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1711 "MQIO Base=%p.\n", ha->mqiobase);
1712 /* Read MSIX vector size of the board */
1713 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
1714 ha->msix_count = msix;
1715 /* Max queues are bounded by available msix vectors */
1716 /* queue 0 uses two msix vectors */
1717 if (ql2xmultique_tag) {
1718 cpus = num_online_cpus();
1719 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1720 (cpus + 1) : (ha->msix_count - 1);
1721 ha->max_req_queues = 2;
1722 } else if (ql2xmaxqueues > 1) {
1723 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1724 QLA_MQ_SIZE : ql2xmaxqueues;
1725 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc008,
1726 "QoS mode set, max no of request queues:%d.\n",
1727 ha->max_req_queues);
1728 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0019,
1729 "QoS mode set, max no of request queues:%d.\n",
1730 ha->max_req_queues);
1731 }
1732 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
1733 "MSI-X vector count: %d.\n", msix);
1734 } else
1735 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1736 "BAR 3 not enabled.\n");
1737
1738mqiobase_exit:
1739 ha->msix_count = ha->max_rsp_queues + 1;
1740 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
1741 "MSIX Count:%d.\n", ha->msix_count);
1742 return (0);
1743
1744iospace_error_exit:
1745 return (-ENOMEM);
1746}
1747
1748
6246b8a1
GM		 1749static int
1750qla83xx_iospace_config(struct qla_hw_data *ha)
1751{
1752 uint16_t msix;
1753 int cpus;
1754
1755 if (pci_request_selected_regions(ha->pdev, ha->bars,
1756 QLA2XXX_DRIVER_NAME)) {
1757 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1758 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1759 pci_name(ha->pdev));
1760
1761 goto iospace_error_exit;
1762 }
1763
1764 /* Use MMIO operations for all accesses. */
1765 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1766 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1767 "Invalid pci I/O region size (%s).\n",
1768 pci_name(ha->pdev));
1769 goto iospace_error_exit;
1770 }
1771 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1772 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1773 "Invalid PCI mem region size (%s), aborting\n",
1774 pci_name(ha->pdev));
1775 goto iospace_error_exit;
1776 }
1777
1778 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1779 if (!ha->iobase) {
1780 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1781 "Cannot remap MMIO (%s), aborting.\n",
1782 pci_name(ha->pdev));
1783 goto iospace_error_exit;
1784 }
1785
1786 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1787 /* 83XX 26XX always use MQ type access for queues
1788 * - mbar 2, a.k.a region 4 */
1789 ha->max_req_queues = ha->max_rsp_queues = 1;
1790 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1791 pci_resource_len(ha->pdev, 4));
1792
1793 if (!ha->mqiobase) {
1794 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1795 "BAR2/region4 not enabled\n");
1796 goto mqiobase_exit;
1797 }
1798
1799 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1800 pci_resource_len(ha->pdev, 2));
1801 if (ha->msixbase) {
1802 /* Read MSIX vector size of the board */
1803 pci_read_config_word(ha->pdev,
1804 QLA_83XX_PCI_MSIX_CONTROL, &msix);
1805 ha->msix_count = msix;
1806 /* Max queues are bounded by available msix vectors */
1807 /* queue 0 uses two msix vectors */
1808 if (ql2xmultique_tag) {
1809 cpus = num_online_cpus();
1810 ha->max_rsp_queues = (ha->msix_count - 1 > cpus) ?
1811 (cpus + 1) : (ha->msix_count - 1);
1812 ha->max_req_queues = 2;
1813 } else if (ql2xmaxqueues > 1) {
1814 ha->max_req_queues = ql2xmaxqueues > QLA_MQ_SIZE ?
1815 QLA_MQ_SIZE : ql2xmaxqueues;
1816 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc00c,
1817 "QoS mode set, max no of request queues:%d.\n",
1818 ha->max_req_queues);
1819 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
1820 "QoS mode set, max no of request queues:%d.\n",
1821 ha->max_req_queues);
1822 }
1823 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
1824 "MSI-X vector count: %d.\n", msix);
1825 } else
1826 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1827 "BAR 1 not enabled.\n");
1828
1829mqiobase_exit:
1830 ha->msix_count = ha->max_rsp_queues + 1;
aa230bc5
AE		 1831
1832 qlt_83xx_iospace_config(ha);
1833
6246b8a1
GM		 1834 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
1835 "MSIX Count:%d.\n", ha->msix_count);
1836 return 0;
1837
1838iospace_error_exit:
1839 return -ENOMEM;
1840}
1841
fd34f556
AV		 1842static struct isp_operations qla2100_isp_ops = {
1843 .pci_config = qla2100_pci_config,
1844 .reset_chip = qla2x00_reset_chip,
1845 .chip_diag = qla2x00_chip_diag,
1846 .config_rings = qla2x00_config_rings,
1847 .reset_adapter = qla2x00_reset_adapter,
1848 .nvram_config = qla2x00_nvram_config,
1849 .update_fw_options = qla2x00_update_fw_options,
1850 .load_risc = qla2x00_load_risc,
1851 .pci_info_str = qla2x00_pci_info_str,
1852 .fw_version_str = qla2x00_fw_version_str,
1853 .intr_handler = qla2100_intr_handler,
1854 .enable_intrs = qla2x00_enable_intrs,
1855 .disable_intrs = qla2x00_disable_intrs,
1856 .abort_command = qla2x00_abort_command,
523ec773
AV		 1857 .target_reset = qla2x00_abort_target,
1858 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1859 .fabric_login = qla2x00_login_fabric,
1860 .fabric_logout = qla2x00_fabric_logout,
1861 .calc_req_entries = qla2x00_calc_iocbs_32,
1862 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1863 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1864 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1865 .read_nvram = qla2x00_read_nvram_data,
1866 .write_nvram = qla2x00_write_nvram_data,
1867 .fw_dump = qla2100_fw_dump,
1868 .beacon_on = NULL,
1869 .beacon_off = NULL,
1870 .beacon_blink = NULL,
1871 .read_optrom = qla2x00_read_optrom_data,
1872 .write_optrom = qla2x00_write_optrom_data,
1873 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1874 .start_scsi = qla2x00_start_scsi,
a9083016 1875 .abort_isp = qla2x00_abort_isp,
706f457d 1876 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1877 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1878};
1879
1880static struct isp_operations qla2300_isp_ops = {
1881 .pci_config = qla2300_pci_config,
1882 .reset_chip = qla2x00_reset_chip,
1883 .chip_diag = qla2x00_chip_diag,
1884 .config_rings = qla2x00_config_rings,
1885 .reset_adapter = qla2x00_reset_adapter,
1886 .nvram_config = qla2x00_nvram_config,
1887 .update_fw_options = qla2x00_update_fw_options,
1888 .load_risc = qla2x00_load_risc,
1889 .pci_info_str = qla2x00_pci_info_str,
1890 .fw_version_str = qla2x00_fw_version_str,
1891 .intr_handler = qla2300_intr_handler,
1892 .enable_intrs = qla2x00_enable_intrs,
1893 .disable_intrs = qla2x00_disable_intrs,
1894 .abort_command = qla2x00_abort_command,
523ec773
AV		 1895 .target_reset = qla2x00_abort_target,
1896 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1897 .fabric_login = qla2x00_login_fabric,
1898 .fabric_logout = qla2x00_fabric_logout,
1899 .calc_req_entries = qla2x00_calc_iocbs_32,
1900 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1901 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1902 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1903 .read_nvram = qla2x00_read_nvram_data,
1904 .write_nvram = qla2x00_write_nvram_data,
1905 .fw_dump = qla2300_fw_dump,
1906 .beacon_on = qla2x00_beacon_on,
1907 .beacon_off = qla2x00_beacon_off,
1908 .beacon_blink = qla2x00_beacon_blink,
1909 .read_optrom = qla2x00_read_optrom_data,
1910 .write_optrom = qla2x00_write_optrom_data,
1911 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1912 .start_scsi = qla2x00_start_scsi,
a9083016 1913 .abort_isp = qla2x00_abort_isp,
7ec0effd 1914 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1915 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1916};
1917
1918static struct isp_operations qla24xx_isp_ops = {
1919 .pci_config = qla24xx_pci_config,
1920 .reset_chip = qla24xx_reset_chip,
1921 .chip_diag = qla24xx_chip_diag,
1922 .config_rings = qla24xx_config_rings,
1923 .reset_adapter = qla24xx_reset_adapter,
1924 .nvram_config = qla24xx_nvram_config,
1925 .update_fw_options = qla24xx_update_fw_options,
1926 .load_risc = qla24xx_load_risc,
1927 .pci_info_str = qla24xx_pci_info_str,
1928 .fw_version_str = qla24xx_fw_version_str,
1929 .intr_handler = qla24xx_intr_handler,
1930 .enable_intrs = qla24xx_enable_intrs,
1931 .disable_intrs = qla24xx_disable_intrs,
1932 .abort_command = qla24xx_abort_command,
523ec773
AV		 1933 .target_reset = qla24xx_abort_target,
1934 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 1935 .fabric_login = qla24xx_login_fabric,
1936 .fabric_logout = qla24xx_fabric_logout,
1937 .calc_req_entries = NULL,
1938 .build_iocbs = NULL,
1939 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1940 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1941 .read_nvram = qla24xx_read_nvram_data,
1942 .write_nvram = qla24xx_write_nvram_data,
1943 .fw_dump = qla24xx_fw_dump,
1944 .beacon_on = qla24xx_beacon_on,
1945 .beacon_off = qla24xx_beacon_off,
1946 .beacon_blink = qla24xx_beacon_blink,
1947 .read_optrom = qla24xx_read_optrom_data,
1948 .write_optrom = qla24xx_write_optrom_data,
1949 .get_flash_version = qla24xx_get_flash_version,
e315cd28 1950 .start_scsi = qla24xx_start_scsi,
a9083016 1951 .abort_isp = qla2x00_abort_isp,
7ec0effd 1952 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1953 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1954};
1955
c3a2f0df
AV		 1956static struct isp_operations qla25xx_isp_ops = {
1957 .pci_config = qla25xx_pci_config,
1958 .reset_chip = qla24xx_reset_chip,
1959 .chip_diag = qla24xx_chip_diag,
1960 .config_rings = qla24xx_config_rings,
1961 .reset_adapter = qla24xx_reset_adapter,
1962 .nvram_config = qla24xx_nvram_config,
1963 .update_fw_options = qla24xx_update_fw_options,
1964 .load_risc = qla24xx_load_risc,
1965 .pci_info_str = qla24xx_pci_info_str,
1966 .fw_version_str = qla24xx_fw_version_str,
1967 .intr_handler = qla24xx_intr_handler,
1968 .enable_intrs = qla24xx_enable_intrs,
1969 .disable_intrs = qla24xx_disable_intrs,
1970 .abort_command = qla24xx_abort_command,
523ec773
AV		 1971 .target_reset = qla24xx_abort_target,
1972 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 1973 .fabric_login = qla24xx_login_fabric,
1974 .fabric_logout = qla24xx_fabric_logout,
1975 .calc_req_entries = NULL,
1976 .build_iocbs = NULL,
1977 .prep_ms_iocb = qla24xx_prep_ms_iocb,
1978 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
1979 .read_nvram = qla25xx_read_nvram_data,
1980 .write_nvram = qla25xx_write_nvram_data,
1981 .fw_dump = qla25xx_fw_dump,
1982 .beacon_on = qla24xx_beacon_on,
1983 .beacon_off = qla24xx_beacon_off,
1984 .beacon_blink = qla24xx_beacon_blink,
338c9161 1985 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 1986 .write_optrom = qla24xx_write_optrom_data,
1987 .get_flash_version = qla24xx_get_flash_version,
bad75002 1988 .start_scsi = qla24xx_dif_start_scsi,
a9083016 1989 .abort_isp = qla2x00_abort_isp,
7ec0effd 1990 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1991 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 1992};
1993
3a03eb79
AV		 1994static struct isp_operations qla81xx_isp_ops = {
1995 .pci_config = qla25xx_pci_config,
1996 .reset_chip = qla24xx_reset_chip,
1997 .chip_diag = qla24xx_chip_diag,
1998 .config_rings = qla24xx_config_rings,
1999 .reset_adapter = qla24xx_reset_adapter,
2000 .nvram_config = qla81xx_nvram_config,
2001 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2002 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2003 .pci_info_str = qla24xx_pci_info_str,
2004 .fw_version_str = qla24xx_fw_version_str,
2005 .intr_handler = qla24xx_intr_handler,
2006 .enable_intrs = qla24xx_enable_intrs,
2007 .disable_intrs = qla24xx_disable_intrs,
2008 .abort_command = qla24xx_abort_command,
2009 .target_reset = qla24xx_abort_target,
2010 .lun_reset = qla24xx_lun_reset,
2011 .fabric_login = qla24xx_login_fabric,
2012 .fabric_logout = qla24xx_fabric_logout,
2013 .calc_req_entries = NULL,
2014 .build_iocbs = NULL,
2015 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2016 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2017 .read_nvram = NULL,
2018 .write_nvram = NULL,
3a03eb79
AV		 2019 .fw_dump = qla81xx_fw_dump,
2020 .beacon_on = qla24xx_beacon_on,
2021 .beacon_off = qla24xx_beacon_off,
6246b8a1 2022 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2023 .read_optrom = qla25xx_read_optrom_data,
2024 .write_optrom = qla24xx_write_optrom_data,
2025 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2026 .start_scsi = qla24xx_dif_start_scsi,
a9083016 2027 .abort_isp = qla2x00_abort_isp,
7ec0effd 2028 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2029 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2030};
2031
2032static struct isp_operations qla82xx_isp_ops = {
2033 .pci_config = qla82xx_pci_config,
2034 .reset_chip = qla82xx_reset_chip,
2035 .chip_diag = qla24xx_chip_diag,
2036 .config_rings = qla82xx_config_rings,
2037 .reset_adapter = qla24xx_reset_adapter,
2038 .nvram_config = qla81xx_nvram_config,
2039 .update_fw_options = qla24xx_update_fw_options,
2040 .load_risc = qla82xx_load_risc,
9d55ca66 2041 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2042 .fw_version_str = qla24xx_fw_version_str,
2043 .intr_handler = qla82xx_intr_handler,
2044 .enable_intrs = qla82xx_enable_intrs,
2045 .disable_intrs = qla82xx_disable_intrs,
2046 .abort_command = qla24xx_abort_command,
2047 .target_reset = qla24xx_abort_target,
2048 .lun_reset = qla24xx_lun_reset,
2049 .fabric_login = qla24xx_login_fabric,
2050 .fabric_logout = qla24xx_fabric_logout,
2051 .calc_req_entries = NULL,
2052 .build_iocbs = NULL,
2053 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2054 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2055 .read_nvram = qla24xx_read_nvram_data,
2056 .write_nvram = qla24xx_write_nvram_data,
2057 .fw_dump = qla24xx_fw_dump,
999916dc
SK		 2058 .beacon_on = qla82xx_beacon_on,
2059 .beacon_off = qla82xx_beacon_off,
2060 .beacon_blink = NULL,
a9083016
GM		 2061 .read_optrom = qla82xx_read_optrom_data,
2062 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2063 .get_flash_version = qla82xx_get_flash_version,
a9083016
GM		 2064 .start_scsi = qla82xx_start_scsi,
2065 .abort_isp = qla82xx_abort_isp,
706f457d 2066 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2067 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2068};
2069
7ec0effd
AD		 2070static struct isp_operations qla8044_isp_ops = {
2071 .pci_config = qla82xx_pci_config,
2072 .reset_chip = qla82xx_reset_chip,
2073 .chip_diag = qla24xx_chip_diag,
2074 .config_rings = qla82xx_config_rings,
2075 .reset_adapter = qla24xx_reset_adapter,
2076 .nvram_config = qla81xx_nvram_config,
2077 .update_fw_options = qla24xx_update_fw_options,
2078 .load_risc = qla82xx_load_risc,
2079 .pci_info_str = qla24xx_pci_info_str,
2080 .fw_version_str = qla24xx_fw_version_str,
2081 .intr_handler = qla8044_intr_handler,
2082 .enable_intrs = qla82xx_enable_intrs,
2083 .disable_intrs = qla82xx_disable_intrs,
2084 .abort_command = qla24xx_abort_command,
2085 .target_reset = qla24xx_abort_target,
2086 .lun_reset = qla24xx_lun_reset,
2087 .fabric_login = qla24xx_login_fabric,
2088 .fabric_logout = qla24xx_fabric_logout,
2089 .calc_req_entries = NULL,
2090 .build_iocbs = NULL,
2091 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2092 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2093 .read_nvram = NULL,
2094 .write_nvram = NULL,
2095 .fw_dump = qla24xx_fw_dump,
2096 .beacon_on = qla82xx_beacon_on,
2097 .beacon_off = qla82xx_beacon_off,
2098 .beacon_blink = NULL,
2099 .read_optrom = qla82xx_read_optrom_data,
2100 .write_optrom = qla8044_write_optrom_data,
2101 .get_flash_version = qla82xx_get_flash_version,
2102 .start_scsi = qla82xx_start_scsi,
2103 .abort_isp = qla8044_abort_isp,
2104 .iospace_config = qla82xx_iospace_config,
2105 .initialize_adapter = qla2x00_initialize_adapter,
2106};
2107
6246b8a1
GM		 2108static struct isp_operations qla83xx_isp_ops = {
2109 .pci_config = qla25xx_pci_config,
2110 .reset_chip = qla24xx_reset_chip,
2111 .chip_diag = qla24xx_chip_diag,
2112 .config_rings = qla24xx_config_rings,
2113 .reset_adapter = qla24xx_reset_adapter,
2114 .nvram_config = qla81xx_nvram_config,
2115 .update_fw_options = qla81xx_update_fw_options,
2116 .load_risc = qla81xx_load_risc,
2117 .pci_info_str = qla24xx_pci_info_str,
2118 .fw_version_str = qla24xx_fw_version_str,
2119 .intr_handler = qla24xx_intr_handler,
2120 .enable_intrs = qla24xx_enable_intrs,
2121 .disable_intrs = qla24xx_disable_intrs,
2122 .abort_command = qla24xx_abort_command,
2123 .target_reset = qla24xx_abort_target,
2124 .lun_reset = qla24xx_lun_reset,
2125 .fabric_login = qla24xx_login_fabric,
2126 .fabric_logout = qla24xx_fabric_logout,
2127 .calc_req_entries = NULL,
2128 .build_iocbs = NULL,
2129 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2130 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2131 .read_nvram = NULL,
2132 .write_nvram = NULL,
2133 .fw_dump = qla83xx_fw_dump,
2134 .beacon_on = qla24xx_beacon_on,
2135 .beacon_off = qla24xx_beacon_off,
2136 .beacon_blink = qla83xx_beacon_blink,
2137 .read_optrom = qla25xx_read_optrom_data,
2138 .write_optrom = qla24xx_write_optrom_data,
2139 .get_flash_version = qla24xx_get_flash_version,
2140 .start_scsi = qla24xx_dif_start_scsi,
2141 .abort_isp = qla2x00_abort_isp,
2142 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2143 .initialize_adapter = qla2x00_initialize_adapter,
2144};
2145
2146static struct isp_operations qlafx00_isp_ops = {
2147 .pci_config = qlafx00_pci_config,
2148 .reset_chip = qlafx00_soft_reset,
2149 .chip_diag = qlafx00_chip_diag,
2150 .config_rings = qlafx00_config_rings,
2151 .reset_adapter = qlafx00_soft_reset,
2152 .nvram_config = NULL,
2153 .update_fw_options = NULL,
2154 .load_risc = NULL,
2155 .pci_info_str = qlafx00_pci_info_str,
2156 .fw_version_str = qlafx00_fw_version_str,
2157 .intr_handler = qlafx00_intr_handler,
2158 .enable_intrs = qlafx00_enable_intrs,
2159 .disable_intrs = qlafx00_disable_intrs,
2160 .abort_command = qlafx00_abort_command,
2161 .target_reset = qlafx00_abort_target,
2162 .lun_reset = qlafx00_lun_reset,
2163 .fabric_login = NULL,
2164 .fabric_logout = NULL,
2165 .calc_req_entries = NULL,
2166 .build_iocbs = NULL,
2167 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2168 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2169 .read_nvram = qla24xx_read_nvram_data,
2170 .write_nvram = qla24xx_write_nvram_data,
2171 .fw_dump = NULL,
2172 .beacon_on = qla24xx_beacon_on,
2173 .beacon_off = qla24xx_beacon_off,
2174 .beacon_blink = NULL,
2175 .read_optrom = qla24xx_read_optrom_data,
2176 .write_optrom = qla24xx_write_optrom_data,
2177 .get_flash_version = qla24xx_get_flash_version,
2178 .start_scsi = qlafx00_start_scsi,
2179 .abort_isp = qlafx00_abort_isp,
2180 .iospace_config = qlafx00_iospace_config,
2181 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2182};
2183
ea5b6382 2184static inline void
e315cd28 2185qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2186{
2187 ha->device_type = DT_EXTENDED_IDS;
2188 switch (ha->pdev->device) {
2189 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2190 ha->device_type |= DT_ISP2100;
2191 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2192 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2193 break;
2194 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2195 ha->device_type |= DT_ISP2200;
2196 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2197 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2198 break;
2199 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2200 ha->device_type |= DT_ISP2300;
4a59f71d 2201 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2202 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2203 break;
2204 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2205 ha->device_type |= DT_ISP2312;
4a59f71d 2206 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2207 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2208 break;
2209 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2210 ha->device_type |= DT_ISP2322;
4a59f71d 2211 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2212 if (ha->pdev->subsystem_vendor == 0x1028 &&
2213 ha->pdev->subsystem_device == 0x0170)
2214 ha->device_type |= DT_OEM_001;
441d1072 2215 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2216 break;
2217 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2218 ha->device_type |= DT_ISP6312;
441d1072 2219 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2220 break;
2221 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2222 ha->device_type |= DT_ISP6322;
441d1072 2223 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2224 break;
2225 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2226 ha->device_type |= DT_ISP2422;
4a59f71d 2227 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2228 ha->device_type |= DT_FWI2;
c76f2c01 2229 ha->device_type |= DT_IIDMA;
441d1072 2230 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2231 break;
2232 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2233 ha->device_type |= DT_ISP2432;
4a59f71d 2234 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2235 ha->device_type |= DT_FWI2;
c76f2c01 2236 ha->device_type |= DT_IIDMA;
441d1072 2237 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2238 break;
4d4df193
HK		 2239 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2240 ha->device_type |= DT_ISP8432;
2241 ha->device_type |= DT_ZIO_SUPPORTED;
2242 ha->device_type |= DT_FWI2;
2243 ha->device_type |= DT_IIDMA;
2244 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2245 break;
044cc6c8
AV		 2246 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2247 ha->device_type |= DT_ISP5422;
e428924c 2248 ha->device_type |= DT_FWI2;
441d1072 2249 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2250 break;
044cc6c8
AV		 2251 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2252 ha->device_type |= DT_ISP5432;
e428924c 2253 ha->device_type |= DT_FWI2;
441d1072 2254 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2255 break;
c3a2f0df
AV		 2256 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2257 ha->device_type |= DT_ISP2532;
2258 ha->device_type |= DT_ZIO_SUPPORTED;
2259 ha->device_type |= DT_FWI2;
2260 ha->device_type |= DT_IIDMA;
441d1072 2261 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2262 break;
3a03eb79
AV		 2263 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2264 ha->device_type |= DT_ISP8001;
2265 ha->device_type |= DT_ZIO_SUPPORTED;
2266 ha->device_type |= DT_FWI2;
2267 ha->device_type |= DT_IIDMA;
2268 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2269 break;
a9083016
GM		 2270 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2271 ha->device_type |= DT_ISP8021;
2272 ha->device_type |= DT_ZIO_SUPPORTED;
2273 ha->device_type |= DT_FWI2;
2274 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2275 /* Initialize 82XX ISP flags */
2276 qla82xx_init_flags(ha);
2277 break;
7ec0effd
AD		 2278 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2279 ha->device_type |= DT_ISP8044;
2280 ha->device_type |= DT_ZIO_SUPPORTED;
2281 ha->device_type |= DT_FWI2;
2282 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2283 /* Initialize 82XX ISP flags */
2284 qla82xx_init_flags(ha);
2285 break;
6246b8a1
GM		 2286 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2287 ha->device_type |= DT_ISP2031;
2288 ha->device_type |= DT_ZIO_SUPPORTED;
2289 ha->device_type |= DT_FWI2;
2290 ha->device_type |= DT_IIDMA;
2291 ha->device_type |= DT_T10_PI;
2292 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2293 break;
2294 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2295 ha->device_type |= DT_ISP8031;
2296 ha->device_type |= DT_ZIO_SUPPORTED;
2297 ha->device_type |= DT_FWI2;
2298 ha->device_type |= DT_IIDMA;
2299 ha->device_type |= DT_T10_PI;
2300 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2301 break;
8ae6d9c7
GM		 2302 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2303 ha->device_type |= DT_ISPFX00;
2304 break;
ea5b6382 2305 }
e5b68a61 2306
a9083016
GM		 2307 if (IS_QLA82XX(ha))
2308 ha->port_no = !(ha->portnum & 1);
2309 else
2310 /* Get adapter physical port no from interrupt pin register. */
2311 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2312
e5b68a61
AC		 2313 if (ha->port_no & 1)
2314 ha->flags.port0 = 1;
2315 else
2316 ha->flags.port0 = 0;
7c3df132 2317 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2318 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
7c3df132 2319 ha->device_type, ha->flags.port0, ha->fw_srisc_address);
ea5b6382
AV		 2320}
2321
1e99e33a
AV		 2322static void
2323qla2xxx_scan_start(struct Scsi_Host *shost)
2324{
e315cd28 2325 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2326
cbc8eb67
AV		 2327 if (vha->hw->flags.running_gold_fw)
2328 return;
2329
e315cd28
AC		 2330 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2331 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2332 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2333 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2334}
2335
2336static int
2337qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2338{
e315cd28 2339 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2340
e315cd28 2341 if (!vha->host)
1e99e33a 2342 return 1;
e315cd28 2343 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2344 return 1;
2345
e315cd28 2346 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2347}
2348
1da177e4
LT		 2349/*
2350 * PCI driver interface
2351 */
6f039790 2352static int
7ee61397 2353qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2354{
a1541d5a 2355 int ret = -ENODEV;
1da177e4 2356 struct Scsi_Host *host;
e315cd28
AC		 2357 scsi_qla_host_t *base_vha = NULL;
2358 struct qla_hw_data *ha;
29856e28 2359 char pci_info[30];
7d613ac6 2360 char fw_str[30], wq_name[30];
5433383e 2361 struct scsi_host_template *sht;
642ef983 2362 int bars, mem_only = 0;
e315cd28 2363 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2364 struct req_que *req = NULL;
2365 struct rsp_que *rsp = NULL;
285d0321 2366 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2367 sht = &qla2xxx_driver_template;
5433383e 2368 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2369 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2370 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2371 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2372 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2373 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2374 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2375 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2376 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2377 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd
AD		 2378 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2379 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044) {
285d0321 2380 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2381 mem_only = 1;
7c3df132
SK		 2382 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2383 "Mem only adapter.\n");
285d0321 2384 }
7c3df132
SK		 2385 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2386 "Bars=%d.\n", bars);
285d0321 2387
09483916
BH		 2388 if (mem_only) {
2389 if (pci_enable_device_mem(pdev))
2390 goto probe_out;
2391 } else {
2392 if (pci_enable_device(pdev))
2393 goto probe_out;
2394 }
285d0321 2395
0927678f
JB		 2396 /* This may fail but that's ok */
2397 pci_enable_pcie_error_reporting(pdev);
285d0321 2398
e315cd28
AC		 2399 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2400 if (!ha) {
7c3df132
SK		 2401 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2402 "Unable to allocate memory for ha.\n");
e315cd28 2403 goto probe_out;
1da177e4 2404 }
7c3df132
SK		 2405 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2406 "Memory allocated for ha=%p.\n", ha);
e315cd28 2407 ha->pdev = pdev;
2d70c103 2408 ha->tgt.enable_class_2 = ql2xenableclass2;
1da177e4
LT		 2409
2410 /* Clear our data area */
285d0321 2411 ha->bars = bars;
09483916 2412 ha->mem_only = mem_only;
df4bf0bb 2413 spin_lock_init(&ha->hardware_lock);
339aa70e 2414 spin_lock_init(&ha->vport_slock);
a9b6f722 2415 mutex_init(&ha->selflogin_lock);
1da177e4 2416
ea5b6382
AV		 2417 /* Set ISP-type information. */
2418 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2419
2420 /* Set EEH reset type to fundamental if required by hba */
95676112
JC		 2421 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2422 IS_QLA83XX(ha))
ca79cf66 2423 pdev->needs_freset = 1;
ca79cf66 2424
cba1e47f
CD		 2425 ha->prev_topology = 0;
2426 ha->init_cb_size = sizeof(init_cb_t);
2427 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2428 ha->optrom_size = OPTROM_SIZE_2300;
3c290d0b 2429 ha->cfg_lun_q_depth = ql2xmaxqdepth;
cba1e47f 2430
abbd8870 2431 /* Assign ISP specific operations. */
1da177e4 2432 if (IS_QLA2100(ha)) {
642ef983 2433 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2434 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2435 req_length = REQUEST_ENTRY_CNT_2100;
2436 rsp_length = RESPONSE_ENTRY_CNT_2100;
2437 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2438 ha->gid_list_info_size = 4;
3a03eb79
AV		 2439 ha->flash_conf_off = ~0;
2440 ha->flash_data_off = ~0;
2441 ha->nvram_conf_off = ~0;
2442 ha->nvram_data_off = ~0;
fd34f556 2443 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2444 } else if (IS_QLA2200(ha)) {
642ef983 2445 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2446 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2447 req_length = REQUEST_ENTRY_CNT_2200;
2448 rsp_length = RESPONSE_ENTRY_CNT_2100;
2449 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2450 ha->gid_list_info_size = 4;
3a03eb79
AV		 2451 ha->flash_conf_off = ~0;
2452 ha->flash_data_off = ~0;
2453 ha->nvram_conf_off = ~0;
2454 ha->nvram_data_off = ~0;
fd34f556 2455 ha->isp_ops = &qla2100_isp_ops;
fca29703 2456 } else if (IS_QLA23XX(ha)) {
642ef983 2457 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2458 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2459 req_length = REQUEST_ENTRY_CNT_2200;
2460 rsp_length = RESPONSE_ENTRY_CNT_2300;
2461 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2462 ha->gid_list_info_size = 6;
854165f4
AV		 2463 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2464 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2465 ha->flash_conf_off = ~0;
2466 ha->flash_data_off = ~0;
2467 ha->nvram_conf_off = ~0;
2468 ha->nvram_data_off = ~0;
fd34f556 2469 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2470 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2471 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2472 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2473 req_length = REQUEST_ENTRY_CNT_24XX;
2474 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2475 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2476 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2477 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2478 ha->gid_list_info_size = 8;
854165f4 2479 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2480 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2481 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2482 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2483 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2484 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2485 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2486 } else if (IS_QLA25XX(ha)) {
642ef983 2487 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2488 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2489 req_length = REQUEST_ENTRY_CNT_24XX;
2490 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2491 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2492 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2493 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2494 ha->gid_list_info_size = 8;
2495 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2496 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2497 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2498 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2499 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2500 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2501 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2502 } else if (IS_QLA81XX(ha)) {
642ef983 2503 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2504 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2505 req_length = REQUEST_ENTRY_CNT_24XX;
2506 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2507 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2508 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2509 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2510 ha->gid_list_info_size = 8;
2511 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2512 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2513 ha->isp_ops = &qla81xx_isp_ops;
2514 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2515 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2516 ha->nvram_conf_off = ~0;
2517 ha->nvram_data_off = ~0;
a9083016 2518 } else if (IS_QLA82XX(ha)) {
642ef983 2519 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2520 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2521 req_length = REQUEST_ENTRY_CNT_82XX;
2522 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2523 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2524 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2525 ha->gid_list_info_size = 8;
2526 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2527 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2528 ha->isp_ops = &qla82xx_isp_ops;
2529 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2530 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2531 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2532 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2533 } else if (IS_QLA8044(ha)) {
2534 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2535 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2536 req_length = REQUEST_ENTRY_CNT_82XX;
2537 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2538 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2539 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2540 ha->gid_list_info_size = 8;
2541 ha->optrom_size = OPTROM_SIZE_83XX;
2542 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2543 ha->isp_ops = &qla8044_isp_ops;
2544 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2545 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2546 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2547 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2548 } else if (IS_QLA83XX(ha)) {
7d613ac6 2549 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2550 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1
GM		 2551 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2552 req_length = REQUEST_ENTRY_CNT_24XX;
2553 rsp_length = RESPONSE_ENTRY_CNT_2300;
b8aa4bdf 2554 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2555 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2556 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2557 ha->gid_list_info_size = 8;
2558 ha->optrom_size = OPTROM_SIZE_83XX;
2559 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2560 ha->isp_ops = &qla83xx_isp_ops;
2561 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2562 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2563 ha->nvram_conf_off = ~0;
2564 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2565 } else if (IS_QLAFX00(ha)) {
2566 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2567 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2568 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2569 req_length = REQUEST_ENTRY_CNT_FX00;
2570 rsp_length = RESPONSE_ENTRY_CNT_FX00;
2571 ha->init_cb_size = sizeof(struct init_cb_fx);
2572 ha->isp_ops = &qlafx00_isp_ops;
2573 ha->port_down_retry_count = 30; /* default value */
2574 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2575 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
2576 ha->mr.fw_hbt_en = 1;
1da177e4 2577 }
6246b8a1 2578
7c3df132
SK		 2579 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2580 "mbx_count=%d, req_length=%d, "
2581 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2582 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2583 "max_fibre_devices=%d.\n",
7c3df132
SK		 2584 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2585 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2586 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2587 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2588 "isp_ops=%p, flash_conf_off=%d, "
2589 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2590 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2591 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2592
2593 /* Configure PCI I/O space */
2594 ret = ha->isp_ops->iospace_config(ha);
2595 if (ret)
0a63ad12 2596 goto iospace_config_failed;
706f457d
GM		 2597
2598 ql_log_pci(ql_log_info, pdev, 0x001d,
2599 "Found an ISP%04X irq %d iobase 0x%p.\n",
2600 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2601 mutex_init(&ha->vport_lock);
0b05a1f0
MB		 2602 init_completion(&ha->mbx_cmd_comp);
2603 complete(&ha->mbx_cmd_comp);
2604 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2605 init_completion(&ha->dcbx_comp);
f356bef1 2606 init_completion(&ha->lb_portup_comp);
1da177e4 2607
2c3dfe3f 2608 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2609
53303c42 2610 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2611 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2612 "64 Bit addressing is %s.\n",
2613 ha->flags.enable_64bit_addressing ? "enable" :
2614 "disable");
73208dfd 2615 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
e315cd28 2616 if (!ret) {
7c3df132
SK		 2617 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2618 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2619
e315cd28
AC		 2620 goto probe_hw_failed;
2621 }
2622
73208dfd 2623 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2624 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2625 req->max_q_depth = ql2xmaxqdepth;
2626
e315cd28
AC		 2627
2628 base_vha = qla2x00_create_host(sht, ha);
2629 if (!base_vha) {
a1541d5a 2630 ret = -ENOMEM;
6e9f21f3 2631 qla2x00_mem_free(ha);
2afa19a9
AC		 2632 qla2x00_free_req_que(ha, req);
2633 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2634 goto probe_hw_failed;
1da177e4
LT		 2635 }
2636
e315cd28
AC		 2637 pci_set_drvdata(pdev, base_vha);
2638
e315cd28 2639 host = base_vha->host;
2afa19a9 2640 base_vha->req = req;
8ae6d9c7
GM		 2641 if (IS_QLAFX00(ha))
2642 host->can_queue = 1024;
2643 else
2644 host->can_queue = req->length + 128;
73208dfd 2645 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2646 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2647 else
e315cd28
AC		 2648 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2649 base_vha->vp_idx;
58548cb5 2650
8ae6d9c7
GM		 2651 /* Setup fcport template structure. */
2652 ha->mr.fcport.vha = base_vha;
2653 ha->mr.fcport.port_type = FCT_UNKNOWN;
2654 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2655 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2656 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2657 ha->mr.fcport.scan_state = 1;
2658
58548cb5
GM		 2659 /* Set the SG table size based on ISP type */
2660 if (!IS_FWI2_CAPABLE(ha)) {
2661 if (IS_QLA2100(ha))
2662 host->sg_tablesize = 32;
2663 } else {
2664 if (!IS_QLA82XX(ha))
2665 host->sg_tablesize = QLA_SG_ALL;
2666 }
7c3df132
SK		 2667 ql_dbg(ql_dbg_init, base_vha, 0x0032,
2668 "can_queue=%d, req=%p, "
2669 "mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
2670 host->can_queue, base_vha->req,
2671 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
642ef983 2672 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2673 host->cmd_per_lun = 3;
2674 host->unique_id = host->host_no;
e02587d7 2675 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2676 host->max_cmd_len = 32;
2677 else
2678 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2679 host->max_channel = MAX_BUSES - 1;
82515920 2680 host->max_lun = ql2xmaxlun;
e315cd28 2681 host->transportt = qla2xxx_transport_template;
9a069e19 2682 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2683
7c3df132
SK		 2684 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2685 "max_id=%d this_id=%d "
2686 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
d8424f68 2687 "max_lun=%d transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2688 host->this_id, host->cmd_per_lun, host->unique_id,
2689 host->max_cmd_len, host->max_channel, host->max_lun,
2690 host->transportt, sht->vendor_id);
2691
9a347ff4
CD		 2692que_init:
2693 /* Alloc arrays of request and response ring ptrs */
2694 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2695 ql_log(ql_log_fatal, base_vha, 0x003d,
2696 "Failed to allocate memory for queue pointers..."
2697 "aborting.\n");
2698 goto probe_init_failed;
2699 }
2700
2d70c103 2701 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2702
73208dfd
AC		 2703 /* Set up the irqs */
2704 ret = qla2x00_request_irqs(ha, rsp);
2705 if (ret)
6e9f21f3 2706 goto probe_init_failed;
90a86fc0
JC		 2707
2708 pci_save_state(pdev);
2709
9a347ff4 2710 /* Assign back pointers */
2afa19a9
AC		 2711 rsp->req = req;
2712 req->rsp = rsp;
9a347ff4 2713
8ae6d9c7
GM		 2714 if (IS_QLAFX00(ha)) {
2715 ha->rsp_q_map[0] = rsp;
2716 ha->req_q_map[0] = req;
2717 set_bit(0, ha->req_qid_map);
2718 set_bit(0, ha->rsp_qid_map);
2719 }
2720
08029990
AV		 2721 /* FWI2-capable only. */
2722 req->req_q_in = &ha->iobase->isp24.req_q_in;
2723 req->req_q_out = &ha->iobase->isp24.req_q_out;
2724 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2725 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
6246b8a1 2726 if (ha->mqenable || IS_QLA83XX(ha)) {
08029990
AV		 2727 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2728 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2729 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2730 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2731 }
2732
8ae6d9c7
GM		 2733 if (IS_QLAFX00(ha)) {
2734 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2735 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2736 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2737 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2738 }
2739
7ec0effd 2740 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2741 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2742 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2743 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2744 }
2745
7c3df132
SK		 2746 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2747 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2748 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2749 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2750 "req->req_q_in=%p req->req_q_out=%p "
2751 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2752 req->req_q_in, req->req_q_out,
2753 rsp->rsp_q_in, rsp->rsp_q_out);
2754 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2755 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2756 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2757 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2758 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2759 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2760
8ae6d9c7 2761 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2762 ql_log(ql_log_fatal, base_vha, 0x00d6,
2763 "Failed to initialize adapter - Adapter flags %x.\n",
2764 base_vha->device_flags);
1da177e4 2765
a9083016
GM		 2766 if (IS_QLA82XX(ha)) {
2767 qla82xx_idc_lock(ha);
2768 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2769 QLA8XXX_DEV_FAILED);
a9083016 2770 qla82xx_idc_unlock(ha);
7c3df132
SK		 2771 ql_log(ql_log_fatal, base_vha, 0x00d7,
2772 "HW State: FAILED.\n");
7ec0effd
AD		 2773 } else if (IS_QLA8044(ha)) {
2774 qla8044_idc_lock(ha);
2775 qla8044_wr_direct(base_vha,
2776 QLA8044_CRB_DEV_STATE_INDEX,
2777 QLA8XXX_DEV_FAILED);
2778 qla8044_idc_unlock(ha);
2779 ql_log(ql_log_fatal, base_vha, 0x0150,
2780 "HW State: FAILED.\n");
a9083016
GM		 2781 }
2782
a1541d5a 2783 ret = -ENODEV;
1da177e4
LT		 2784 goto probe_failed;
2785 }
2786
7163ea81
AC		 2787 if (ha->mqenable) {
2788 if (qla25xx_setup_mode(base_vha)) {
7c3df132
SK		 2789 ql_log(ql_log_warn, base_vha, 0x00ec,
2790 "Failed to create queues, falling back to single queue mode.\n");
7163ea81
AC		 2791 goto que_init;
2792 }
2793 }
68ca949c 2794
cbc8eb67
AV		 2795 if (ha->flags.running_gold_fw)
2796 goto skip_dpc;
2797
1da177e4
LT		 2798 /*
2799 * Startup the kernel thread for this host adapter
2800 */
39a11240 2801 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 2802 "%s_dpc", base_vha->host_str);
39a11240 2803 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 2804 ql_log(ql_log_fatal, base_vha, 0x00ed,
2805 "Failed to start DPC thread.\n");
39a11240 2806 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 2807 goto probe_failed;
2808 }
7c3df132
SK		 2809 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
2810 "DPC thread started successfully.\n");
1da177e4 2811
2d70c103
NB		 2812 /*
2813 * If we're not coming up in initiator mode, we might sit for
2814 * a while without waking up the dpc thread, which leads to a
2815 * stuck process warning. So just kick the dpc once here and
2816 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
2817 */
2818 qla2xxx_wake_dpc(base_vha);
2819
81178772
SK		 2820 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
2821 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
2822 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
2823 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
2824
2825 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
2826 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
2827 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
2828 INIT_WORK(&ha->idc_state_handler,
2829 qla83xx_idc_state_handler_work);
2830 INIT_WORK(&ha->nic_core_unrecoverable,
2831 qla83xx_nic_core_unrecoverable_work);
2832 }
2833
cbc8eb67 2834skip_dpc:
e315cd28
AC		 2835 list_add_tail(&base_vha->list, &ha->vp_list);
2836 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 2837
2838 /* Initialized the timer */
e315cd28 2839 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 2840 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
2841 "Started qla2x00_timer with "
2842 "interval=%d.\n", WATCH_INTERVAL);
2843 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
2844 "Detected hba at address=%p.\n",
2845 ha);
d19044c3 2846
e02587d7 2847 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 2848 if (ha->fw_attributes & BIT_4) {
9e522cd8 2849 int prot = 0, guard;
bad75002 2850 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 2851 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
2852 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 2853 if (ql2xenabledif == 1)
2854 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 2855 scsi_host_set_prot(host,
8cb2049c 2856 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 2857 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 2858 | SHOST_DIF_TYPE3_PROTECTION
2859 | SHOST_DIX_TYPE1_PROTECTION
0c470874 2860 | SHOST_DIX_TYPE2_PROTECTION
bad75002 2861 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 2862
2863 guard = SHOST_DIX_GUARD_CRC;
2864
2865 if (IS_PI_IPGUARD_CAPABLE(ha) &&
2866 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
2867 guard |= SHOST_DIX_GUARD_IP;
2868
2869 scsi_host_set_guard(host, guard);
bad75002
AE		 2870 } else
2871 base_vha->flags.difdix_supported = 0;
2872 }
2873
a9083016
GM		 2874 ha->isp_ops->enable_intrs(ha);
2875
a1541d5a
AV		 2876 ret = scsi_add_host(host, &pdev->dev);
2877 if (ret)
2878 goto probe_failed;
2879
1486400f
MR		 2880 base_vha->flags.init_done = 1;
2881 base_vha->flags.online = 1;
2882
7c3df132
SK		 2883 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
2884 "Init done and hba is online.\n");
2885
2d70c103
NB		 2886 if (qla_ini_mode_enabled(base_vha))
2887 scsi_scan_host(host);
2888 else
2889 ql_dbg(ql_dbg_init, base_vha, 0x0122,
2890 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 2891
e315cd28 2892 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 2893
8ae6d9c7
GM		 2894 if (IS_QLAFX00(ha)) {
2895 ret = qlafx00_fx_disc(base_vha,
2896 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
2897
2898 ret = qlafx00_fx_disc(base_vha,
2899 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
2900
2901 /* Register system information */
2902 ret = qlafx00_fx_disc(base_vha,
2903 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
2904 }
2905
e315cd28 2906 qla2x00_init_host_attr(base_vha);
a1541d5a 2907
e315cd28 2908 qla2x00_dfs_setup(base_vha);
df613b96 2909
7c3df132 2910 ql_log(ql_log_info, base_vha, 0x00fb,
c5dcfaac 2911 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 2912 ql_log(ql_log_info, base_vha, 0x00fc,
2913 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
2914 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
2915 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
2916 base_vha->host_no,
e315cd28 2917 ha->isp_ops->fw_version_str(base_vha, fw_str));
1da177e4 2918
2d70c103
NB		 2919 qlt_add_target(ha, base_vha);
2920
1da177e4
LT		 2921 return 0;
2922
6e9f21f3 2923probe_init_failed:
2afa19a9 2924 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 2925 ha->req_q_map[0] = NULL;
2926 clear_bit(0, ha->req_qid_map);
2afa19a9 2927 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 2928 ha->rsp_q_map[0] = NULL;
2929 clear_bit(0, ha->rsp_qid_map);
2afa19a9 2930 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 2931
1da177e4 2932probe_failed:
b9978769
AV		 2933 if (base_vha->timer_active)
2934 qla2x00_stop_timer(base_vha);
2935 base_vha->flags.online = 0;
2936 if (ha->dpc_thread) {
2937 struct task_struct *t = ha->dpc_thread;
2938
2939 ha->dpc_thread = NULL;
2940 kthread_stop(t);
2941 }
2942
e315cd28 2943 qla2x00_free_device(base_vha);
1da177e4 2944
e315cd28 2945 scsi_host_put(base_vha->host);
1da177e4 2946
e315cd28 2947probe_hw_failed:
a9083016
GM		 2948 if (IS_QLA82XX(ha)) {
2949 qla82xx_idc_lock(ha);
2950 qla82xx_clear_drv_active(ha);
2951 qla82xx_idc_unlock(ha);
0a63ad12 2952 }
7ec0effd
AD		 2953 if (IS_QLA8044(ha)) {
2954 qla8044_idc_lock(ha);
2955 qla8044_clear_drv_active(base_vha);
2956 qla8044_idc_unlock(ha);
2957 }
0a63ad12 2958iospace_config_failed:
7ec0effd 2959 if (IS_P3P_TYPE(ha)) {
0a63ad12
SK		 2960 if (!ha->nx_pcibase)
2961 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
a9083016
GM		 2962 if (!ql2xdbwr)
2963 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
2964 } else {
2965 if (ha->iobase)
2966 iounmap(ha->iobase);
8ae6d9c7
GM		 2967 if (ha->cregbase)
2968 iounmap(ha->cregbase);
a9083016 2969 }
e315cd28
AC		 2970 pci_release_selected_regions(ha->pdev, ha->bars);
2971 kfree(ha);
2972 ha = NULL;
1da177e4 2973
a1541d5a 2974probe_out:
e315cd28 2975 pci_disable_device(pdev);
a1541d5a 2976 return ret;
1da177e4 2977}
1da177e4 2978
2d70c103
NB		 2979static void
2980qla2x00_stop_dpc_thread(scsi_qla_host_t *vha)
2981{
2982 struct qla_hw_data *ha = vha->hw;
2983 struct task_struct *t = ha->dpc_thread;
2984
2985 if (ha->dpc_thread == NULL)
2986 return;
2987 /*
2988 * qla2xxx_wake_dpc checks for ->dpc_thread
2989 * so we need to zero it out.
2990 */
2991 ha->dpc_thread = NULL;
2992 kthread_stop(t);
2993}
2994
e30d1756
MI		 2995static void
2996qla2x00_shutdown(struct pci_dev *pdev)
2997{
2998 scsi_qla_host_t *vha;
2999 struct qla_hw_data *ha;
3000
552f3f9a
MI		 3001 if (!atomic_read(&pdev->enable_cnt))
3002 return;
3003
e30d1756
MI		 3004 vha = pci_get_drvdata(pdev);
3005 ha = vha->hw;
3006
3007 /* Turn-off FCE trace */
3008 if (ha->flags.fce_enabled) {
3009 qla2x00_disable_fce_trace(vha, NULL, NULL);
3010 ha->flags.fce_enabled = 0;
3011 }
3012
3013 /* Turn-off EFT trace */
3014 if (ha->eft)
3015 qla2x00_disable_eft_trace(vha);
3016
3017 /* Stop currently executing firmware. */
3018 qla2x00_try_to_stop_firmware(vha);
3019
3020 /* Turn adapter off line */
3021 vha->flags.online = 0;
3022
3023 /* turn-off interrupts on the card */
3024 if (ha->interrupts_on) {
3025 vha->flags.init_done = 0;
3026 ha->isp_ops->disable_intrs(ha);
3027 }
3028
3029 qla2x00_free_irqs(vha);
3030
3031 qla2x00_free_fw_dump(ha);
3032}
3033
4c993f76 3034static void
7ee61397 3035qla2x00_remove_one(struct pci_dev *pdev)
1da177e4 3036{
feafb7b1 3037 scsi_qla_host_t *base_vha, *vha;
e315cd28 3038 struct qla_hw_data *ha;
feafb7b1 3039 unsigned long flags;
e315cd28 3040
9a347ff4
CD		 3041 /*
3042 * If the PCI device is disabled that means that probe failed and any
3043 * resources should be have cleaned up on probe exit.
3044 */
3045 if (!atomic_read(&pdev->enable_cnt))
3046 return;
3047
e315cd28
AC		 3048 base_vha = pci_get_drvdata(pdev);
3049 ha = base_vha->hw;
3050
2d70c103
NB		 3051 ha->flags.host_shutting_down = 1;
3052
220d36b4 3053 set_bit(UNLOADING, &base_vha->dpc_flags);
43ebf16d
AE		 3054 mutex_lock(&ha->vport_lock);
3055 while (ha->cur_vport_count) {
43ebf16d 3056 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3057
43ebf16d
AE		 3058 BUG_ON(base_vha->list.next == &ha->vp_list);
3059 /* This assumes first entry in ha->vp_list is always base vha */
3060 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
6e97c9d5 3061 scsi_host_get(vha->host);
feafb7b1 3062
43ebf16d
AE		 3063 spin_unlock_irqrestore(&ha->vport_slock, flags);
3064 mutex_unlock(&ha->vport_lock);
3065
3066 fc_vport_terminate(vha->fc_vport);
3067 scsi_host_put(vha->host);
feafb7b1 3068
43ebf16d 3069 mutex_lock(&ha->vport_lock);
e315cd28 3070 }
43ebf16d 3071 mutex_unlock(&ha->vport_lock);
1da177e4 3072
7d613ac6
SV		 3073 if (IS_QLA8031(ha)) {
3074 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3075 "Clearing fcoe driver presence.\n");
3076 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3077 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3078 "Error while clearing DRV-Presence.\n");
3079 }
3080
b9978769
AV		 3081 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3082
e315cd28 3083 qla2x00_dfs_remove(base_vha);
c795c1e4 3084
e315cd28 3085 qla84xx_put_chip(base_vha);
c795c1e4 3086
b9978769
AV		 3087 /* Disable timer */
3088 if (base_vha->timer_active)
3089 qla2x00_stop_timer(base_vha);
3090
3091 base_vha->flags.online = 0;
3092
68ca949c
AC		 3093 /* Flush the work queue and remove it */
3094 if (ha->wq) {
3095 flush_workqueue(ha->wq);
3096 destroy_workqueue(ha->wq);
3097 ha->wq = NULL;
3098 }
3099
7d613ac6
SV		 3100 /* Cancel all work and destroy DPC workqueues */
3101 if (ha->dpc_lp_wq) {
3102 cancel_work_sync(&ha->idc_aen);
3103 destroy_workqueue(ha->dpc_lp_wq);
3104 ha->dpc_lp_wq = NULL;
3105 }
3106
3107 if (ha->dpc_hp_wq) {
3108 cancel_work_sync(&ha->nic_core_reset);
3109 cancel_work_sync(&ha->idc_state_handler);
3110 cancel_work_sync(&ha->nic_core_unrecoverable);
3111 destroy_workqueue(ha->dpc_hp_wq);
3112 ha->dpc_hp_wq = NULL;
3113 }
3114
b9978769
AV		 3115 /* Kill the kernel thread for this host */
3116 if (ha->dpc_thread) {
3117 struct task_struct *t = ha->dpc_thread;
3118
3119 /*
3120 * qla2xxx_wake_dpc checks for ->dpc_thread
3121 * so we need to zero it out.
3122 */
3123 ha->dpc_thread = NULL;
3124 kthread_stop(t);
3125 }
2d70c103 3126 qlt_remove_target(ha, base_vha);
b9978769 3127
e315cd28 3128 qla2x00_free_sysfs_attr(base_vha);
df613b96 3129
e315cd28 3130 fc_remove_host(base_vha->host);
4d4df193 3131
e315cd28 3132 scsi_remove_host(base_vha->host);
1da177e4 3133
e315cd28 3134 qla2x00_free_device(base_vha);
bdf79621 3135
e315cd28 3136 scsi_host_put(base_vha->host);
1da177e4 3137
7ec0effd
AD		 3138 if (IS_QLA8044(ha)) {
3139 qla8044_idc_lock(ha);
3140 qla8044_clear_drv_active(base_vha);
3141 qla8044_idc_unlock(ha);
3142 }
a9083016 3143 if (IS_QLA82XX(ha)) {
b963752f
GM		 3144 qla82xx_idc_lock(ha);
3145 qla82xx_clear_drv_active(ha);
3146 qla82xx_idc_unlock(ha);
3147
a9083016
GM		 3148 iounmap((device_reg_t __iomem *)ha->nx_pcibase);
3149 if (!ql2xdbwr)
3150 iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr);
3151 } else {
3152 if (ha->iobase)
3153 iounmap(ha->iobase);
1da177e4 3154
8ae6d9c7
GM		 3155 if (ha->cregbase)
3156 iounmap(ha->cregbase);
3157
a9083016
GM		 3158 if (ha->mqiobase)
3159 iounmap(ha->mqiobase);
6246b8a1
GM		 3160
3161 if (IS_QLA83XX(ha) && ha->msixbase)
3162 iounmap(ha->msixbase);
a9083016 3163 }
73208dfd 3164
e315cd28
AC		 3165 pci_release_selected_regions(ha->pdev, ha->bars);
3166 kfree(ha);
3167 ha = NULL;
1da177e4 3168
90a86fc0
JC		 3169 pci_disable_pcie_error_reporting(pdev);
3170
665db93b 3171 pci_disable_device(pdev);
1da177e4
LT		 3172 pci_set_drvdata(pdev, NULL);
3173}
1da177e4
LT		 3174
3175static void
e315cd28 3176qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3177{
e315cd28 3178 struct qla_hw_data *ha = vha->hw;
1da177e4 3179
85880801
AV		 3180 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3181
3182 /* Disable timer */
3183 if (vha->timer_active)
3184 qla2x00_stop_timer(vha);
3185
2d70c103 3186 qla2x00_stop_dpc_thread(vha);
85880801 3187
2afa19a9 3188 qla25xx_delete_queues(vha);
df613b96 3189 if (ha->flags.fce_enabled)
e315cd28 3190 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3191
a7a167bf 3192 if (ha->eft)
e315cd28 3193 qla2x00_disable_eft_trace(vha);
a7a167bf 3194
f6ef3b18 3195 /* Stop currently executing firmware. */
e315cd28 3196 qla2x00_try_to_stop_firmware(vha);
1da177e4 3197
85880801
AV		 3198 vha->flags.online = 0;
3199
f6ef3b18 3200 /* turn-off interrupts on the card */
a9083016
GM		 3201 if (ha->interrupts_on) {
3202 vha->flags.init_done = 0;
fd34f556 3203 ha->isp_ops->disable_intrs(ha);
a9083016 3204 }
f6ef3b18 3205
e315cd28 3206 qla2x00_free_irqs(vha);
1da177e4 3207
8867048b
CD		 3208 qla2x00_free_fcports(vha);
3209
e315cd28 3210 qla2x00_mem_free(ha);
73208dfd 3211
08de2844
GM		 3212 qla82xx_md_free(vha);
3213
73208dfd 3214 qla2x00_free_queues(ha);
1da177e4
LT		 3215}
3216
8867048b
CD		 3217void qla2x00_free_fcports(struct scsi_qla_host *vha)
3218{
3219 fc_port_t *fcport, *tfcport;
3220
3221 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3222 list_del(&fcport->list);
5f16b331 3223 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3224 kfree(fcport);
3225 fcport = NULL;
3226 }
3227}
3228
d97994dc 3229static inline void
e315cd28 3230qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3231 int defer)
3232{
d97994dc 3233 struct fc_rport *rport;
67becc00 3234 scsi_qla_host_t *base_vha;
044d78e1 3235 unsigned long flags;
d97994dc
AV		 3236
3237 if (!fcport->rport)
3238 return;
3239
3240 rport = fcport->rport;
3241 if (defer) {
67becc00 3242 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3243 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3244 fcport->drport = rport;
044d78e1 3245 spin_unlock_irqrestore(vha->host->host_lock, flags);
67becc00
AV		 3246 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3247 qla2xxx_wake_dpc(base_vha);
2d70c103 3248 } else {
d97994dc 3249 fc_remote_port_delete(rport);
2d70c103
NB		 3250 qlt_fc_port_deleted(vha, fcport);
3251 }
d97994dc
AV		 3252}
3253
1da177e4
LT		 3254/*
3255 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3256 *
3257 * Input: ha = adapter block pointer. fcport = port structure pointer.
3258 *
3259 * Return: None.
3260 *
3261 * Context:
3262 */
e315cd28 3263void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3264 int do_login, int defer)
1da177e4 3265{
8ae6d9c7
GM		 3266 if (IS_QLAFX00(vha->hw)) {
3267 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3268 qla2x00_schedule_rport_del(vha, fcport, defer);
3269 return;
3270 }
3271
2c3dfe3f 3272 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3273 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3274 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3275 qla2x00_schedule_rport_del(vha, fcport, defer);
3276 }
fa2a1ce5 3277 /*
1da177e4
LT		 3278 * We may need to retry the login, so don't change the state of the
3279 * port but do the retries.
3280 */
3281 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3282 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3283
3284 if (!do_login)
3285 return;
3286
3287 if (fcport->login_retry == 0) {
e315cd28
AC		 3288 fcport->login_retry = vha->hw->login_retry_count;
3289 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4 3290
7c3df132 3291 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3292 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3293 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3294 }
3295}
3296
3297/*
3298 * qla2x00_mark_all_devices_lost
3299 * Updates fcport state when device goes offline.
3300 *
3301 * Input:
3302 * ha = adapter block pointer.
3303 * fcport = port structure pointer.
3304 *
3305 * Return:
3306 * None.
3307 *
3308 * Context:
3309 */
3310void
e315cd28 3311qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3312{
3313 fc_port_t *fcport;
3314
e315cd28 3315 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3316 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3317 continue;
0d6e61bc 3318
1da177e4
LT		 3319 /*
3320 * No point in marking the device as lost, if the device is
3321 * already DEAD.
3322 */
3323 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3324 continue;
e315cd28 3325 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3326 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3327 if (defer)
3328 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3329 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3330 qla2x00_schedule_rport_del(vha, fcport, defer);
3331 }
1da177e4
LT		 3332 }
3333}
3334
3335/*
3336* qla2x00_mem_alloc
3337* Allocates adapter memory.
3338*
3339* Returns:
3340* 0 = success.
e8711085 3341* !0 = failure.
1da177e4 3342*/
e8711085 3343static int
73208dfd
AC		 3344qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3345 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3346{
3347 char name[16];
1da177e4 3348
e8711085 3349 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3350 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3351 if (!ha->init_cb)
e315cd28 3352 goto fail;
e8711085 3353
2d70c103
NB		 3354 if (qlt_mem_alloc(ha) < 0)
3355 goto fail_free_init_cb;
3356
642ef983
CD		 3357 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3358 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3359 if (!ha->gid_list)
2d70c103 3360 goto fail_free_tgt_mem;
1da177e4 3361
e8711085
AV		 3362 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3363 if (!ha->srb_mempool)
e315cd28 3364 goto fail_free_gid_list;
e8711085 3365
7ec0effd 3366 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3367 /* Allocate cache for CT6 Ctx. */
3368 if (!ctx_cachep) {
3369 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3370 sizeof(struct ct6_dsd), 0,
3371 SLAB_HWCACHE_ALIGN, NULL);
3372 if (!ctx_cachep)
3373 goto fail_free_gid_list;
3374 }
3375 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3376 ctx_cachep);
3377 if (!ha->ctx_mempool)
3378 goto fail_free_srb_mempool;
7c3df132
SK		 3379 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3380 "ctx_cachep=%p ctx_mempool=%p.\n",
3381 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3382 }
3383
e8711085
AV		 3384 /* Get memory for cached NVRAM */
3385 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3386 if (!ha->nvram)
a9083016 3387 goto fail_free_ctx_mempool;
e8711085 3388
e315cd28
AC		 3389 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3390 ha->pdev->device);
3391 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3392 DMA_POOL_SIZE, 8, 0);
3393 if (!ha->s_dma_pool)
3394 goto fail_free_nvram;
3395
7c3df132
SK		 3396 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3397 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3398 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3399
7ec0effd 3400 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3401 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3402 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3403 if (!ha->dl_dma_pool) {
7c3df132
SK		 3404 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3405 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3406 goto fail_s_dma_pool;
3407 }
3408
3409 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3410 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3411 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3412 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3413 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3414 goto fail_dl_dma_pool;
3415 }
7c3df132
SK		 3416 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3417 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3418 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3419 }
3420
e8711085
AV		 3421 /* Allocate memory for SNS commands */
3422 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3423 /* Get consistent memory allocated for SNS commands */
e8711085 3424 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3425 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3426 if (!ha->sns_cmd)
e315cd28 3427 goto fail_dma_pool;
7c3df132 3428 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3429 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3430 } else {
e315cd28 3431 /* Get consistent memory allocated for MS IOCB */
e8711085 3432 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3433 &ha->ms_iocb_dma);
e8711085 3434 if (!ha->ms_iocb)
e315cd28
AC		 3435 goto fail_dma_pool;
3436 /* Get consistent memory allocated for CT SNS commands */
e8711085 3437 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3438 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3439 if (!ha->ct_sns)
3440 goto fail_free_ms_iocb;
7c3df132
SK		 3441 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3442 "ms_iocb=%p ct_sns=%p.\n",
3443 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3444 }
3445
e315cd28 3446 /* Allocate memory for request ring */
73208dfd
AC		 3447 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3448 if (!*req) {
7c3df132
SK		 3449 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3450 "Failed to allocate memory for req.\n");
e315cd28
AC		 3451 goto fail_req;
3452 }
73208dfd
AC		 3453 (*req)->length = req_len;
3454 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3455 ((*req)->length + 1) * sizeof(request_t),
3456 &(*req)->dma, GFP_KERNEL);
3457 if (!(*req)->ring) {
7c3df132
SK		 3458 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3459 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3460 goto fail_req_ring;
3461 }
3462 /* Allocate memory for response ring */
73208dfd
AC		 3463 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3464 if (!*rsp) {
7c3df132
SK		 3465 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3466 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3467 goto fail_rsp;
3468 }
73208dfd
AC		 3469 (*rsp)->hw = ha;
3470 (*rsp)->length = rsp_len;
3471 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3472 ((*rsp)->length + 1) * sizeof(response_t),
3473 &(*rsp)->dma, GFP_KERNEL);
3474 if (!(*rsp)->ring) {
7c3df132
SK		 3475 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3476 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3477 goto fail_rsp_ring;
3478 }
73208dfd
AC		 3479 (*req)->rsp = *rsp;
3480 (*rsp)->req = *req;
7c3df132
SK		 3481 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3482 "req=%p req->length=%d req->ring=%p rsp=%p "
3483 "rsp->length=%d rsp->ring=%p.\n",
3484 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3485 (*rsp)->ring);
73208dfd
AC		 3486 /* Allocate memory for NVRAM data for vports */
3487 if (ha->nvram_npiv_size) {
3488 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3489 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3490 if (!ha->npiv_info) {
7c3df132
SK		 3491 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3492 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3493 goto fail_npiv_info;
3494 }
3495 } else
3496 ha->npiv_info = NULL;
e8711085 3497
b64b0e8f 3498 /* Get consistent memory allocated for EX-INIT-CB. */
6246b8a1 3499 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha)) {
b64b0e8f
AV		 3500 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3501 &ha->ex_init_cb_dma);
3502 if (!ha->ex_init_cb)
3503 goto fail_ex_init_cb;
7c3df132
SK		 3504 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3505 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3506 }
3507
a9083016
GM		 3508 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3509
5ff1d584
AV		 3510 /* Get consistent memory allocated for Async Port-Database. */
3511 if (!IS_FWI2_CAPABLE(ha)) {
3512 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3513 &ha->async_pd_dma);
3514 if (!ha->async_pd)
3515 goto fail_async_pd;
7c3df132
SK		 3516 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3517 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3518 }
3519
e315cd28 3520 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3521
3522 /* Allocate memory for our loop_id bitmap */
3523 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3524 GFP_KERNEL);
3525 if (!ha->loop_id_map)
3526 goto fail_async_pd;
3527 else {
3528 qla2x00_set_reserved_loop_ids(ha);
3529 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
3530 "loop_id_map=%p. \n", ha->loop_id_map);
3531 }
3532
e315cd28
AC		 3533 return 1;
3534
5ff1d584
AV		 3535fail_async_pd:
3536 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3537fail_ex_init_cb:
3538 kfree(ha->npiv_info);
73208dfd
AC		 3539fail_npiv_info:
3540 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3541 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3542 (*rsp)->ring = NULL;
3543 (*rsp)->dma = 0;
e315cd28 3544fail_rsp_ring:
73208dfd 3545 kfree(*rsp);
e315cd28 3546fail_rsp:
73208dfd
AC		 3547 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3548 sizeof(request_t), (*req)->ring, (*req)->dma);
3549 (*req)->ring = NULL;
3550 (*req)->dma = 0;
e315cd28 3551fail_req_ring:
73208dfd 3552 kfree(*req);
e315cd28
AC		 3553fail_req:
3554 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3555 ha->ct_sns, ha->ct_sns_dma);
3556 ha->ct_sns = NULL;
3557 ha->ct_sns_dma = 0;
e8711085
AV		 3558fail_free_ms_iocb:
3559 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3560 ha->ms_iocb = NULL;
3561 ha->ms_iocb_dma = 0;
e315cd28 3562fail_dma_pool:
bad75002 3563 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3564 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3565 ha->fcp_cmnd_dma_pool = NULL;
3566 }
3567fail_dl_dma_pool:
bad75002 3568 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3569 dma_pool_destroy(ha->dl_dma_pool);
3570 ha->dl_dma_pool = NULL;
3571 }
3572fail_s_dma_pool:
e315cd28
AC		 3573 dma_pool_destroy(ha->s_dma_pool);
3574 ha->s_dma_pool = NULL;
e8711085
AV		 3575fail_free_nvram:
3576 kfree(ha->nvram);
3577 ha->nvram = NULL;
a9083016
GM		 3578fail_free_ctx_mempool:
3579 mempool_destroy(ha->ctx_mempool);
3580 ha->ctx_mempool = NULL;
e8711085
AV		 3581fail_free_srb_mempool:
3582 mempool_destroy(ha->srb_mempool);
3583 ha->srb_mempool = NULL;
e8711085 3584fail_free_gid_list:
642ef983
CD		 3585 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3586 ha->gid_list,
e315cd28 3587 ha->gid_list_dma);
e8711085
AV		 3588 ha->gid_list = NULL;
3589 ha->gid_list_dma = 0;
2d70c103
NB		 3590fail_free_tgt_mem:
3591 qlt_mem_free(ha);
e315cd28
AC		 3592fail_free_init_cb:
3593 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3594 ha->init_cb_dma);
3595 ha->init_cb = NULL;
3596 ha->init_cb_dma = 0;
e8711085 3597fail:
7c3df132
SK		 3598 ql_log(ql_log_fatal, NULL, 0x0030,
3599 "Memory allocation failure.\n");
e8711085 3600 return -ENOMEM;
1da177e4
LT		 3601}
3602
3603/*
e30d1756
MI		 3604* qla2x00_free_fw_dump
3605* Frees fw dump stuff.
1da177e4
LT		 3606*
3607* Input:
7ec0effd 3608* ha = adapter block pointer
1da177e4 3609*/
a824ebb3 3610static void
e30d1756 3611qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 3612{
df613b96
AV		 3613 if (ha->fce)
3614 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
e30d1756 3615 ha->fce_dma);
df613b96 3616
a7a167bf
AV		 3617 if (ha->fw_dump) {
3618 if (ha->eft)
3619 dma_free_coherent(&ha->pdev->dev,
e30d1756 3620 ntohl(ha->fw_dump->eft_size), ha->eft, ha->eft_dma);
a7a167bf
AV		 3621 vfree(ha->fw_dump);
3622 }
e30d1756
MI		 3623 ha->fce = NULL;
3624 ha->fce_dma = 0;
3625 ha->eft = NULL;
3626 ha->eft_dma = 0;
3627 ha->fw_dump = NULL;
3628 ha->fw_dumped = 0;
3629 ha->fw_dump_reading = 0;
3630}
3631
3632/*
3633* qla2x00_mem_free
3634* Frees all adapter allocated memory.
3635*
3636* Input:
3637* ha = adapter block pointer.
3638*/
3639static void
3640qla2x00_mem_free(struct qla_hw_data *ha)
3641{
3642 qla2x00_free_fw_dump(ha);
3643
81178772
SK		 3644 if (ha->mctp_dump)
3645 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
3646 ha->mctp_dump_dma);
3647
e30d1756
MI		 3648 if (ha->srb_mempool)
3649 mempool_destroy(ha->srb_mempool);
a7a167bf 3650
11bbc1d8
AV		 3651 if (ha->dcbx_tlv)
3652 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
3653 ha->dcbx_tlv, ha->dcbx_tlv_dma);
3654
ce0423f4
AV		 3655 if (ha->xgmac_data)
3656 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
3657 ha->xgmac_data, ha->xgmac_data_dma);
3658
1da177e4
LT		 3659 if (ha->sns_cmd)
3660 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 3661 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 3662
3663 if (ha->ct_sns)
3664 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 3665 ha->ct_sns, ha->ct_sns_dma);
1da177e4 3666
88729e53
AV		 3667 if (ha->sfp_data)
3668 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
3669
1da177e4
LT		 3670 if (ha->ms_iocb)
3671 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3672
b64b0e8f 3673 if (ha->ex_init_cb)
a9083016
GM		 3674 dma_pool_free(ha->s_dma_pool,
3675 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 3676
5ff1d584
AV		 3677 if (ha->async_pd)
3678 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
3679
1da177e4
LT		 3680 if (ha->s_dma_pool)
3681 dma_pool_destroy(ha->s_dma_pool);
3682
1da177e4 3683 if (ha->gid_list)
642ef983
CD		 3684 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3685 ha->gid_list, ha->gid_list_dma);
1da177e4 3686
a9083016
GM		 3687 if (IS_QLA82XX(ha)) {
3688 if (!list_empty(&ha->gbl_dsd_list)) {
3689 struct dsd_dma *dsd_ptr, *tdsd_ptr;
3690
3691 /* clean up allocated prev pool */
3692 list_for_each_entry_safe(dsd_ptr,
3693 tdsd_ptr, &ha->gbl_dsd_list, list) {
3694 dma_pool_free(ha->dl_dma_pool,
3695 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
3696 list_del(&dsd_ptr->list);
3697 kfree(dsd_ptr);
3698 }
3699 }
3700 }
3701
3702 if (ha->dl_dma_pool)
3703 dma_pool_destroy(ha->dl_dma_pool);
3704
3705 if (ha->fcp_cmnd_dma_pool)
3706 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3707
3708 if (ha->ctx_mempool)
3709 mempool_destroy(ha->ctx_mempool);
3710
2d70c103
NB		 3711 qlt_mem_free(ha);
3712
e315cd28
AC		 3713 if (ha->init_cb)
3714 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 3715 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 3716 vfree(ha->optrom_buffer);
3717 kfree(ha->nvram);
73208dfd 3718 kfree(ha->npiv_info);
7a67735b 3719 kfree(ha->swl);
5f16b331 3720 kfree(ha->loop_id_map);
1da177e4 3721
e8711085 3722 ha->srb_mempool = NULL;
a9083016 3723 ha->ctx_mempool = NULL;
1da177e4
LT		 3724 ha->sns_cmd = NULL;
3725 ha->sns_cmd_dma = 0;
3726 ha->ct_sns = NULL;
3727 ha->ct_sns_dma = 0;
3728 ha->ms_iocb = NULL;
3729 ha->ms_iocb_dma = 0;
1da177e4
LT		 3730 ha->init_cb = NULL;
3731 ha->init_cb_dma = 0;
b64b0e8f
AV		 3732 ha->ex_init_cb = NULL;
3733 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 3734 ha->async_pd = NULL;
3735 ha->async_pd_dma = 0;
1da177e4
LT		 3736
3737 ha->s_dma_pool = NULL;
a9083016
GM		 3738 ha->dl_dma_pool = NULL;
3739 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 3740
1da177e4
LT		 3741 ha->gid_list = NULL;
3742 ha->gid_list_dma = 0;
2d70c103
NB		 3743
3744 ha->tgt.atio_ring = NULL;
3745 ha->tgt.atio_dma = 0;
3746 ha->tgt.tgt_vp_map = NULL;
e315cd28 3747}
1da177e4 3748
e315cd28
AC		 3749struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
3750 struct qla_hw_data *ha)
3751{
3752 struct Scsi_Host *host;
3753 struct scsi_qla_host *vha = NULL;
854165f4 3754
e315cd28
AC		 3755 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
3756 if (host == NULL) {
7c3df132
SK		 3757 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
3758 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 3759 goto fail;
3760 }
3761
3762 /* Clear our data area */
3763 vha = shost_priv(host);
3764 memset(vha, 0, sizeof(scsi_qla_host_t));
3765
3766 vha->host = host;
3767 vha->host_no = host->host_no;
3768 vha->hw = ha;
3769
3770 INIT_LIST_HEAD(&vha->vp_fcports);
3771 INIT_LIST_HEAD(&vha->work_list);
3772 INIT_LIST_HEAD(&vha->list);
3773
f999f4c1
AV		 3774 spin_lock_init(&vha->work_lock);
3775
e315cd28 3776 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 3777 ql_dbg(ql_dbg_init, vha, 0x0041,
3778 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
3779 vha->host, vha->hw, vha,
3780 dev_name(&(ha->pdev->dev)));
3781
e315cd28
AC		 3782 return vha;
3783
3784fail:
3785 return vha;
1da177e4
LT		 3786}
3787
01ef66bb 3788static struct qla_work_evt *
f999f4c1 3789qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 3790{
3791 struct qla_work_evt *e;
feafb7b1
AE		 3792 uint8_t bail;
3793
3794 QLA_VHA_MARK_BUSY(vha, bail);
3795 if (bail)
3796 return NULL;
0971de7f 3797
f999f4c1 3798 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 3799 if (!e) {
3800 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 3801 return NULL;
feafb7b1 3802 }
0971de7f
AV		 3803
3804 INIT_LIST_HEAD(&e->list);
3805 e->type = type;
3806 e->flags = QLA_EVT_FLAG_FREE;
3807 return e;
3808}
3809
01ef66bb 3810static int
f999f4c1 3811qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 3812{
f999f4c1 3813 unsigned long flags;
0971de7f 3814
f999f4c1 3815 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 3816 list_add_tail(&e->list, &vha->work_list);
f999f4c1 3817 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 3818 qla2xxx_wake_dpc(vha);
f999f4c1 3819
0971de7f
AV		 3820 return QLA_SUCCESS;
3821}
3822
3823int
e315cd28 3824qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 3825 u32 data)
3826{
3827 struct qla_work_evt *e;
3828
f999f4c1 3829 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 3830 if (!e)
3831 return QLA_FUNCTION_FAILED;
3832
3833 e->u.aen.code = code;
3834 e->u.aen.data = data;
f999f4c1 3835 return qla2x00_post_work(vha, e);
0971de7f
AV		 3836}
3837
8a659571
AV		 3838int
3839qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
3840{
3841 struct qla_work_evt *e;
3842
f999f4c1 3843 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 3844 if (!e)
3845 return QLA_FUNCTION_FAILED;
3846
3847 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 3848 return qla2x00_post_work(vha, e);
8a659571
AV		 3849}
3850
ac280b67
AV		 3851#define qla2x00_post_async_work(name, type) \
3852int qla2x00_post_async_##name##_work( \
3853 struct scsi_qla_host *vha, \
3854 fc_port_t *fcport, uint16_t *data) \
3855{ \
3856 struct qla_work_evt *e; \
3857 \
3858 e = qla2x00_alloc_work(vha, type); \
3859 if (!e) \
3860 return QLA_FUNCTION_FAILED; \
3861 \
3862 e->u.logio.fcport = fcport; \
3863 if (data) { \
3864 e->u.logio.data[0] = data[0]; \
3865 e->u.logio.data[1] = data[1]; \
3866 } \
3867 return qla2x00_post_work(vha, e); \
3868}
3869
3870qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
3871qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
3872qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
3873qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 3874qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
3875qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 3876
3420d36c
AV		 3877int
3878qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
3879{
3880 struct qla_work_evt *e;
3881
3882 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
3883 if (!e)
3884 return QLA_FUNCTION_FAILED;
3885
3886 e->u.uevent.code = code;
3887 return qla2x00_post_work(vha, e);
3888}
3889
3890static void
3891qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
3892{
3893 char event_string[40];
3894 char *envp[] = { event_string, NULL };
3895
3896 switch (code) {
3897 case QLA_UEVENT_CODE_FW_DUMP:
3898 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
3899 vha->host_no);
3900 break;
3901 default:
3902 /* do nothing */
3903 break;
3904 }
3905 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
3906}
3907
8ae6d9c7
GM		 3908int
3909qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
3910 uint32_t *data, int cnt)
3911{
3912 struct qla_work_evt *e;
3913
3914 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
3915 if (!e)
3916 return QLA_FUNCTION_FAILED;
3917
3918 e->u.aenfx.evtcode = evtcode;
3919 e->u.aenfx.count = cnt;
3920 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
3921 return qla2x00_post_work(vha, e);
3922}
3923
ac280b67 3924void
e315cd28 3925qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 3926{
f999f4c1
AV		 3927 struct qla_work_evt *e, *tmp;
3928 unsigned long flags;
3929 LIST_HEAD(work);
0971de7f 3930
f999f4c1
AV		 3931 spin_lock_irqsave(&vha->work_lock, flags);
3932 list_splice_init(&vha->work_list, &work);
3933 spin_unlock_irqrestore(&vha->work_lock, flags);
3934
3935 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 3936 list_del_init(&e->list);
0971de7f
AV		 3937
3938 switch (e->type) {
3939 case QLA_EVT_AEN:
e315cd28 3940 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 3941 e->u.aen.code, e->u.aen.data);
3942 break;
8a659571
AV		 3943 case QLA_EVT_IDC_ACK:
3944 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
3945 break;
ac280b67
AV		 3946 case QLA_EVT_ASYNC_LOGIN:
3947 qla2x00_async_login(vha, e->u.logio.fcport,
3948 e->u.logio.data);
3949 break;
3950 case QLA_EVT_ASYNC_LOGIN_DONE:
3951 qla2x00_async_login_done(vha, e->u.logio.fcport,
3952 e->u.logio.data);
3953 break;
3954 case QLA_EVT_ASYNC_LOGOUT:
3955 qla2x00_async_logout(vha, e->u.logio.fcport);
3956 break;
3957 case QLA_EVT_ASYNC_LOGOUT_DONE:
3958 qla2x00_async_logout_done(vha, e->u.logio.fcport,
3959 e->u.logio.data);
3960 break;
5ff1d584
AV		 3961 case QLA_EVT_ASYNC_ADISC:
3962 qla2x00_async_adisc(vha, e->u.logio.fcport,
3963 e->u.logio.data);
3964 break;
3965 case QLA_EVT_ASYNC_ADISC_DONE:
3966 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
3967 e->u.logio.data);
3968 break;
3420d36c
AV		 3969 case QLA_EVT_UEVENT:
3970 qla2x00_uevent_emit(vha, e->u.uevent.code);
3971 break;
8ae6d9c7
GM		 3972 case QLA_EVT_AENFX:
3973 qlafx00_process_aen(vha, e);
3974 break;
0971de7f
AV		 3975 }
3976 if (e->flags & QLA_EVT_FLAG_FREE)
3977 kfree(e);
feafb7b1
AE		 3978
3979 /* For each work completed decrement vha ref count */
3980 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 3981 }
e315cd28 3982}
f999f4c1 3983
e315cd28
AC		 3984/* Relogins all the fcports of a vport
3985 * Context: dpc thread
3986 */
3987void qla2x00_relogin(struct scsi_qla_host *vha)
3988{
3989 fc_port_t *fcport;
c6b2fca8 3990 int status;
e315cd28
AC		 3991 uint16_t next_loopid = 0;
3992 struct qla_hw_data *ha = vha->hw;
ac280b67 3993 uint16_t data[2];
e315cd28
AC		 3994
3995 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3996 /*
3997 * If the port is not ONLINE then try to login
3998 * to it if we haven't run out of retries.
3999 */
5ff1d584
AV		 4000 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4001 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4002 fcport->login_retry--;
e315cd28 4003 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4004 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4005 ha->isp_ops->fabric_logout(vha,
4006 fcport->loop_id,
4007 fcport->d_id.b.domain,
4008 fcport->d_id.b.area,
4009 fcport->d_id.b.al_pa);
4010
03bcfb57
JC		 4011 if (fcport->loop_id == FC_NO_LOOP_ID) {
4012 fcport->loop_id = next_loopid =
4013 ha->min_external_loopid;
4014 status = qla2x00_find_new_loop_id(
4015 vha, fcport);
4016 if (status != QLA_SUCCESS) {
4017 /* Ran out of IDs to use */
4018 break;
4019 }
4020 }
4021
ac280b67 4022 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4023 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4024 data[0] = 0;
4025 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4026 status = qla2x00_post_async_login_work(
4027 vha, fcport, data);
4028 if (status == QLA_SUCCESS)
4029 continue;
4030 /* Attempt a retry. */
4031 status = 1;
aaf4d3e2 4032 } else {
ac280b67
AV		 4033 status = qla2x00_fabric_login(vha,
4034 fcport, &next_loopid);
aaf4d3e2
SK		 4035 if (status == QLA_SUCCESS) {
4036 int status2;
4037 uint8_t opts;
4038
4039 opts = 0;
4040 if (fcport->flags &
4041 FCF_FCP2_DEVICE)
4042 opts |= BIT_1;
03003960
SK		 4043 status2 =
4044 qla2x00_get_port_database(
4045 vha, fcport, opts);
aaf4d3e2
SK		 4046 if (status2 != QLA_SUCCESS)
4047 status = 1;
4048 }
4049 }
e315cd28
AC		 4050 } else
4051 status = qla2x00_local_device_login(vha,
4052 fcport);
4053
e315cd28
AC		 4054 if (status == QLA_SUCCESS) {
4055 fcport->old_loop_id = fcport->loop_id;
4056
7c3df132
SK		 4057 ql_dbg(ql_dbg_disc, vha, 0x2003,
4058 "Port login OK: logged in ID 0x%x.\n",
4059 fcport->loop_id);
e315cd28
AC		 4060
4061 qla2x00_update_fcport(vha, fcport);
4062
4063 } else if (status == 1) {
4064 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4065 /* retry the login again */
7c3df132
SK		 4066 ql_dbg(ql_dbg_disc, vha, 0x2007,
4067 "Retrying %d login again loop_id 0x%x.\n",
4068 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4069 } else {
4070 fcport->login_retry = 0;
4071 }
4072
4073 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4074 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4075 }
4076 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4077 break;
0971de7f 4078 }
0971de7f
AV		 4079}
4080
7d613ac6
SV		 4081/* Schedule work on any of the dpc-workqueues */
4082void
4083qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4084{
4085 struct qla_hw_data *ha = base_vha->hw;
4086
4087 switch (work_code) {
4088 case MBA_IDC_AEN: /* 0x8200 */
4089 if (ha->dpc_lp_wq)
4090 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4091 break;
4092
4093 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4094 if (!ha->flags.nic_core_reset_hdlr_active) {
4095 if (ha->dpc_hp_wq)
4096 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4097 } else
4098 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4099 "NIC Core reset is already active. Skip "
4100 "scheduling it again.\n");
4101 break;
4102 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4103 if (ha->dpc_hp_wq)
4104 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4105 break;
4106 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4107 if (ha->dpc_hp_wq)
4108 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4109 break;
4110 default:
4111 ql_log(ql_log_warn, base_vha, 0xb05f,
4112 "Unknow work-code=0x%x.\n", work_code);
4113 }
4114
4115 return;
4116}
4117
4118/* Work: Perform NIC Core Unrecoverable state handling */
4119void
4120qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4121{
4122 struct qla_hw_data *ha =
2ad1b67c 4123 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4124 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4125 uint32_t dev_state = 0;
4126
4127 qla83xx_idc_lock(base_vha, 0);
4128 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4129 qla83xx_reset_ownership(base_vha);
4130 if (ha->flags.nic_core_reset_owner) {
4131 ha->flags.nic_core_reset_owner = 0;
4132 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4133 QLA8XXX_DEV_FAILED);
4134 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4135 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4136 }
4137 qla83xx_idc_unlock(base_vha, 0);
4138}
4139
4140/* Work: Execute IDC state handler */
4141void
4142qla83xx_idc_state_handler_work(struct work_struct *work)
4143{
4144 struct qla_hw_data *ha =
2ad1b67c 4145 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4146 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4147 uint32_t dev_state = 0;
4148
4149 qla83xx_idc_lock(base_vha, 0);
4150 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4151 if (dev_state == QLA8XXX_DEV_FAILED ||
4152 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4153 qla83xx_idc_state_handler(base_vha);
4154 qla83xx_idc_unlock(base_vha, 0);
4155}
4156
fa492630 4157static int
7d613ac6
SV		 4158qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4159{
4160 int rval = QLA_SUCCESS;
4161 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4162 uint32_t heart_beat_counter1, heart_beat_counter2;
4163
4164 do {
4165 if (time_after(jiffies, heart_beat_wait)) {
4166 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4167 "Nic Core f/w is not alive.\n");
4168 rval = QLA_FUNCTION_FAILED;
4169 break;
4170 }
4171
4172 qla83xx_idc_lock(base_vha, 0);
4173 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4174 &heart_beat_counter1);
4175 qla83xx_idc_unlock(base_vha, 0);
4176 msleep(100);
4177 qla83xx_idc_lock(base_vha, 0);
4178 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4179 &heart_beat_counter2);
4180 qla83xx_idc_unlock(base_vha, 0);
4181 } while (heart_beat_counter1 == heart_beat_counter2);
4182
4183 return rval;
4184}
4185
4186/* Work: Perform NIC Core Reset handling */
4187void
4188qla83xx_nic_core_reset_work(struct work_struct *work)
4189{
4190 struct qla_hw_data *ha =
4191 container_of(work, struct qla_hw_data, nic_core_reset);
4192 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4193 uint32_t dev_state = 0;
4194
81178772
SK		 4195 if (IS_QLA2031(ha)) {
4196 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4197 ql_log(ql_log_warn, base_vha, 0xb081,
4198 "Failed to dump mctp\n");
4199 return;
4200 }
4201
7d613ac6
SV		 4202 if (!ha->flags.nic_core_reset_hdlr_active) {
4203 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4204 qla83xx_idc_lock(base_vha, 0);
4205 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4206 &dev_state);
4207 qla83xx_idc_unlock(base_vha, 0);
4208 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4209 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4210 "Nic Core f/w is alive.\n");
4211 return;
4212 }
4213 }
4214
4215 ha->flags.nic_core_reset_hdlr_active = 1;
4216 if (qla83xx_nic_core_reset(base_vha)) {
4217 /* NIC Core reset failed. */
4218 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4219 "NIC Core reset failed.\n");
4220 }
4221 ha->flags.nic_core_reset_hdlr_active = 0;
4222 }
4223}
4224
4225/* Work: Handle 8200 IDC aens */
4226void
4227qla83xx_service_idc_aen(struct work_struct *work)
4228{
4229 struct qla_hw_data *ha =
4230 container_of(work, struct qla_hw_data, idc_aen);
4231 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4232 uint32_t dev_state, idc_control;
4233
4234 qla83xx_idc_lock(base_vha, 0);
4235 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4236 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4237 qla83xx_idc_unlock(base_vha, 0);
4238 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4239 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4240 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4241 "Application requested NIC Core Reset.\n");
4242 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4243 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4244 QLA_SUCCESS) {
4245 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4246 "Other protocol driver requested NIC Core Reset.\n");
4247 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4248 }
4249 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4250 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4251 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4252 }
4253}
4254
4255static void
4256qla83xx_wait_logic(void)
4257{
4258 int i;
4259
4260 /* Yield CPU */
4261 if (!in_interrupt()) {
4262 /*
4263 * Wait about 200ms before retrying again.
4264 * This controls the number of retries for single
4265 * lock operation.
4266 */
4267 msleep(100);
4268 schedule();
4269 } else {
4270 for (i = 0; i < 20; i++)
4271 cpu_relax(); /* This a nop instr on i386 */
4272 }
4273}
4274
fa492630 4275static int
7d613ac6
SV		 4276qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4277{
4278 int rval;
4279 uint32_t data;
4280 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4281 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4282 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4283 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4284 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4285
4286 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4287 if (rval)
4288 return rval;
4289
4290 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4291 return QLA_SUCCESS;
4292 } else {
4293 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4294 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4295 data);
4296 if (rval)
4297 return rval;
4298
4299 msleep(200);
4300
4301 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4302 &data);
4303 if (rval)
4304 return rval;
4305
4306 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4307 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4308 ~(idc_lck_rcvry_stage_mask));
4309 rval = qla83xx_wr_reg(base_vha,
4310 QLA83XX_IDC_LOCK_RECOVERY, data);
4311 if (rval)
4312 return rval;
4313
4314 /* Forcefully perform IDC UnLock */
4315 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4316 &data);
4317 if (rval)
4318 return rval;
4319 /* Clear lock-id by setting 0xff */
4320 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4321 0xff);
4322 if (rval)
4323 return rval;
4324 /* Clear lock-recovery by setting 0x0 */
4325 rval = qla83xx_wr_reg(base_vha,
4326 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4327 if (rval)
4328 return rval;
4329 } else
4330 return QLA_SUCCESS;
4331 }
4332
4333 return rval;
4334}
4335
fa492630 4336static int
7d613ac6
SV		 4337qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4338{
4339 int rval = QLA_SUCCESS;
4340 uint32_t o_drv_lockid, n_drv_lockid;
4341 unsigned long lock_recovery_timeout;
4342
4343 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4344retry_lockid:
4345 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4346 if (rval)
4347 goto exit;
4348
4349 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4350 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4351 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4352 return QLA_SUCCESS;
4353 else
4354 return QLA_FUNCTION_FAILED;
4355 }
4356
4357 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4358 if (rval)
4359 goto exit;
4360
4361 if (o_drv_lockid == n_drv_lockid) {
4362 qla83xx_wait_logic();
4363 goto retry_lockid;
4364 } else
4365 return QLA_SUCCESS;
4366
4367exit:
4368 return rval;
4369}
4370
4371void
4372qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4373{
4374 uint16_t options = (requester_id << 15) | BIT_6;
4375 uint32_t data;
6c315553 4376 uint32_t lock_owner;
7d613ac6
SV		 4377 struct qla_hw_data *ha = base_vha->hw;
4378
4379 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4380retry_lock:
4381 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4382 == QLA_SUCCESS) {
4383 if (data) {
4384 /* Setting lock-id to our function-number */
4385 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4386 ha->portnum);
4387 } else {
6c315553
SK		 4388 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4389 &lock_owner);
7d613ac6 4390 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4391 "Failed to acquire IDC lock, acquired by %d, "
4392 "retrying...\n", lock_owner);
7d613ac6
SV		 4393
4394 /* Retry/Perform IDC-Lock recovery */
4395 if (qla83xx_idc_lock_recovery(base_vha)
4396 == QLA_SUCCESS) {
4397 qla83xx_wait_logic();
4398 goto retry_lock;
4399 } else
4400 ql_log(ql_log_warn, base_vha, 0xb075,
4401 "IDC Lock recovery FAILED.\n");
4402 }
4403
4404 }
4405
4406 return;
4407
4408 /* XXX: IDC-lock implementation using access-control mbx */
4409retry_lock2:
4410 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4411 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4412 "Failed to acquire IDC lock. retrying...\n");
4413 /* Retry/Perform IDC-Lock recovery */
4414 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4415 qla83xx_wait_logic();
4416 goto retry_lock2;
4417 } else
4418 ql_log(ql_log_warn, base_vha, 0xb076,
4419 "IDC Lock recovery FAILED.\n");
4420 }
4421
4422 return;
4423}
4424
4425void
4426qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4427{
4428 uint16_t options = (requester_id << 15) | BIT_7, retry;
4429 uint32_t data;
4430 struct qla_hw_data *ha = base_vha->hw;
4431
4432 /* IDC-unlock implementation using driver-unlock/lock-id
4433 * remote registers
4434 */
4435 retry = 0;
4436retry_unlock:
4437 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4438 == QLA_SUCCESS) {
4439 if (data == ha->portnum) {
4440 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4441 /* Clearing lock-id by setting 0xff */
4442 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4443 } else if (retry < 10) {
4444 /* SV: XXX: IDC unlock retrying needed here? */
4445
4446 /* Retry for IDC-unlock */
4447 qla83xx_wait_logic();
4448 retry++;
4449 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
4450 "Failed to release IDC lock, retyring=%d\n", retry);
4451 goto retry_unlock;
4452 }
4453 } else if (retry < 10) {
4454 /* Retry for IDC-unlock */
4455 qla83xx_wait_logic();
4456 retry++;
4457 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
4458 "Failed to read drv-lockid, retyring=%d\n", retry);
4459 goto retry_unlock;
4460 }
4461
4462 return;
4463
4464 /* XXX: IDC-unlock implementation using access-control mbx */
4465 retry = 0;
4466retry_unlock2:
4467 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4468 if (retry < 10) {
4469 /* Retry for IDC-unlock */
4470 qla83xx_wait_logic();
4471 retry++;
4472 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
4473 "Failed to release IDC lock, retyring=%d\n", retry);
4474 goto retry_unlock2;
4475 }
4476 }
4477
4478 return;
4479}
4480
4481int
4482__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4483{
4484 int rval = QLA_SUCCESS;
4485 struct qla_hw_data *ha = vha->hw;
4486 uint32_t drv_presence;
4487
4488 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4489 if (rval == QLA_SUCCESS) {
4490 drv_presence |= (1 << ha->portnum);
4491 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4492 drv_presence);
4493 }
4494
4495 return rval;
4496}
4497
4498int
4499qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4500{
4501 int rval = QLA_SUCCESS;
4502
4503 qla83xx_idc_lock(vha, 0);
4504 rval = __qla83xx_set_drv_presence(vha);
4505 qla83xx_idc_unlock(vha, 0);
4506
4507 return rval;
4508}
4509
4510int
4511__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4512{
4513 int rval = QLA_SUCCESS;
4514 struct qla_hw_data *ha = vha->hw;
4515 uint32_t drv_presence;
4516
4517 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4518 if (rval == QLA_SUCCESS) {
4519 drv_presence &= ~(1 << ha->portnum);
4520 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4521 drv_presence);
4522 }
4523
4524 return rval;
4525}
4526
4527int
4528qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4529{
4530 int rval = QLA_SUCCESS;
4531
4532 qla83xx_idc_lock(vha, 0);
4533 rval = __qla83xx_clear_drv_presence(vha);
4534 qla83xx_idc_unlock(vha, 0);
4535
4536 return rval;
4537}
4538
fa492630 4539static void
7d613ac6
SV		 4540qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4541{
4542 struct qla_hw_data *ha = vha->hw;
4543 uint32_t drv_ack, drv_presence;
4544 unsigned long ack_timeout;
4545
4546 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4547 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4548 while (1) {
4549 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4550 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4551 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 4552 break;
4553
4554 if (time_after_eq(jiffies, ack_timeout)) {
4555 ql_log(ql_log_warn, vha, 0xb067,
4556 "RESET ACK TIMEOUT! drv_presence=0x%x "
4557 "drv_ack=0x%x\n", drv_presence, drv_ack);
4558 /*
4559 * The function(s) which did not ack in time are forced
4560 * to withdraw any further participation in the IDC
4561 * reset.
4562 */
4563 if (drv_ack != drv_presence)
4564 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4565 drv_ack);
4566 break;
4567 }
4568
4569 qla83xx_idc_unlock(vha, 0);
4570 msleep(1000);
4571 qla83xx_idc_lock(vha, 0);
4572 }
4573
4574 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
4575 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
4576}
4577
fa492630 4578static int
7d613ac6
SV		 4579qla83xx_device_bootstrap(scsi_qla_host_t *vha)
4580{
4581 int rval = QLA_SUCCESS;
4582 uint32_t idc_control;
4583
4584 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
4585 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
4586
4587 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
4588 __qla83xx_get_idc_control(vha, &idc_control);
4589 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
4590 __qla83xx_set_idc_control(vha, 0);
4591
4592 qla83xx_idc_unlock(vha, 0);
4593 rval = qla83xx_restart_nic_firmware(vha);
4594 qla83xx_idc_lock(vha, 0);
4595
4596 if (rval != QLA_SUCCESS) {
4597 ql_log(ql_log_fatal, vha, 0xb06a,
4598 "Failed to restart NIC f/w.\n");
4599 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
4600 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
4601 } else {
4602 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
4603 "Success in restarting nic f/w.\n");
4604 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
4605 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
4606 }
4607
4608 return rval;
4609}
4610
4611/* Assumes idc_lock always held on entry */
4612int
4613qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
4614{
4615 struct qla_hw_data *ha = base_vha->hw;
4616 int rval = QLA_SUCCESS;
4617 unsigned long dev_init_timeout;
4618 uint32_t dev_state;
4619
4620 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
4621 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
4622
4623 while (1) {
4624
4625 if (time_after_eq(jiffies, dev_init_timeout)) {
4626 ql_log(ql_log_warn, base_vha, 0xb06e,
4627 "Initialization TIMEOUT!\n");
4628 /* Init timeout. Disable further NIC Core
4629 * communication.
4630 */
4631 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4632 QLA8XXX_DEV_FAILED);
4633 ql_log(ql_log_info, base_vha, 0xb06f,
4634 "HW State: FAILED.\n");
4635 }
4636
4637 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4638 switch (dev_state) {
4639 case QLA8XXX_DEV_READY:
4640 if (ha->flags.nic_core_reset_owner)
4641 qla83xx_idc_audit(base_vha,
4642 IDC_AUDIT_COMPLETION);
4643 ha->flags.nic_core_reset_owner = 0;
4644 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
4645 "Reset_owner reset by 0x%x.\n",
4646 ha->portnum);
4647 goto exit;
4648 case QLA8XXX_DEV_COLD:
4649 if (ha->flags.nic_core_reset_owner)
4650 rval = qla83xx_device_bootstrap(base_vha);
4651 else {
4652 /* Wait for AEN to change device-state */
4653 qla83xx_idc_unlock(base_vha, 0);
4654 msleep(1000);
4655 qla83xx_idc_lock(base_vha, 0);
4656 }
4657 break;
4658 case QLA8XXX_DEV_INITIALIZING:
4659 /* Wait for AEN to change device-state */
4660 qla83xx_idc_unlock(base_vha, 0);
4661 msleep(1000);
4662 qla83xx_idc_lock(base_vha, 0);
4663 break;
4664 case QLA8XXX_DEV_NEED_RESET:
4665 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
4666 qla83xx_need_reset_handler(base_vha);
4667 else {
4668 /* Wait for AEN to change device-state */
4669 qla83xx_idc_unlock(base_vha, 0);
4670 msleep(1000);
4671 qla83xx_idc_lock(base_vha, 0);
4672 }
4673 /* reset timeout value after need reset handler */
4674 dev_init_timeout = jiffies +
4675 (ha->fcoe_dev_init_timeout * HZ);
4676 break;
4677 case QLA8XXX_DEV_NEED_QUIESCENT:
4678 /* XXX: DEBUG for now */
4679 qla83xx_idc_unlock(base_vha, 0);
4680 msleep(1000);
4681 qla83xx_idc_lock(base_vha, 0);
4682 break;
4683 case QLA8XXX_DEV_QUIESCENT:
4684 /* XXX: DEBUG for now */
4685 if (ha->flags.quiesce_owner)
4686 goto exit;
4687
4688 qla83xx_idc_unlock(base_vha, 0);
4689 msleep(1000);
4690 qla83xx_idc_lock(base_vha, 0);
4691 dev_init_timeout = jiffies +
4692 (ha->fcoe_dev_init_timeout * HZ);
4693 break;
4694 case QLA8XXX_DEV_FAILED:
4695 if (ha->flags.nic_core_reset_owner)
4696 qla83xx_idc_audit(base_vha,
4697 IDC_AUDIT_COMPLETION);
4698 ha->flags.nic_core_reset_owner = 0;
4699 __qla83xx_clear_drv_presence(base_vha);
4700 qla83xx_idc_unlock(base_vha, 0);
4701 qla8xxx_dev_failed_handler(base_vha);
4702 rval = QLA_FUNCTION_FAILED;
4703 qla83xx_idc_lock(base_vha, 0);
4704 goto exit;
4705 case QLA8XXX_BAD_VALUE:
4706 qla83xx_idc_unlock(base_vha, 0);
4707 msleep(1000);
4708 qla83xx_idc_lock(base_vha, 0);
4709 break;
4710 default:
4711 ql_log(ql_log_warn, base_vha, 0xb071,
4712 "Unknow Device State: %x.\n", dev_state);
4713 qla83xx_idc_unlock(base_vha, 0);
4714 qla8xxx_dev_failed_handler(base_vha);
4715 rval = QLA_FUNCTION_FAILED;
4716 qla83xx_idc_lock(base_vha, 0);
4717 goto exit;
4718 }
4719 }
4720
4721exit:
4722 return rval;
4723}
4724
1da177e4
LT		 4725/**************************************************************************
4726* qla2x00_do_dpc
4727* This kernel thread is a task that is schedule by the interrupt handler
4728* to perform the background processing for interrupts.
4729*
4730* Notes:
4731* This task always run in the context of a kernel thread. It
4732* is kick-off by the driver's detect code and starts up
4733* up one per adapter. It immediately goes to sleep and waits for
4734* some fibre event. When either the interrupt handler or
4735* the timer routine detects a event it will one of the task
4736* bits then wake us up.
4737**************************************************************************/
4738static int
4739qla2x00_do_dpc(void *data)
4740{
2c3dfe3f 4741 int rval;
e315cd28
AC		 4742 scsi_qla_host_t *base_vha;
4743 struct qla_hw_data *ha;
1da177e4 4744
e315cd28
AC		 4745 ha = (struct qla_hw_data *)data;
4746 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 4747
1da177e4
LT		 4748 set_user_nice(current, -20);
4749
563585ec 4750 set_current_state(TASK_INTERRUPTIBLE);
39a11240 4751 while (!kthread_should_stop()) {
7c3df132
SK		 4752 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
4753 "DPC handler sleeping.\n");
1da177e4 4754
39a11240
CH		 4755 schedule();
4756 __set_current_state(TASK_RUNNING);
1da177e4 4757
c142caf0
AV		 4758 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
4759 goto end_loop;
1da177e4 4760
85880801 4761 if (ha->flags.eeh_busy) {
7c3df132
SK		 4762 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
4763 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 4764 goto end_loop;
85880801
AV		 4765 }
4766
1da177e4
LT		 4767 ha->dpc_active = 1;
4768
5f28d2d7
SK		 4769 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
4770 "DPC handler waking up, dpc_flags=0x%lx.\n",
4771 base_vha->dpc_flags);
1da177e4 4772
e315cd28 4773 qla2x00_do_work(base_vha);
0971de7f 4774
7ec0effd
AD		 4775 if (IS_P3P_TYPE(ha)) {
4776 if (IS_QLA8044(ha)) {
4777 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4778 &base_vha->dpc_flags)) {
4779 qla8044_idc_lock(ha);
4780 qla8044_wr_direct(base_vha,
4781 QLA8044_CRB_DEV_STATE_INDEX,
4782 QLA8XXX_DEV_FAILED);
4783 qla8044_idc_unlock(ha);
4784 ql_log(ql_log_info, base_vha, 0x4004,
4785 "HW State: FAILED.\n");
4786 qla8044_device_state_handler(base_vha);
4787 continue;
4788 }
4789
4790 } else {
4791 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4792 &base_vha->dpc_flags)) {
4793 qla82xx_idc_lock(ha);
4794 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
4795 QLA8XXX_DEV_FAILED);
4796 qla82xx_idc_unlock(ha);
4797 ql_log(ql_log_info, base_vha, 0x0151,
4798 "HW State: FAILED.\n");
4799 qla82xx_device_state_handler(base_vha);
4800 continue;
4801 }
a9083016
GM		 4802 }
4803
4804 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
4805 &base_vha->dpc_flags)) {
4806
7c3df132
SK		 4807 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
4808 "FCoE context reset scheduled.\n");
a9083016
GM		 4809 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
4810 &base_vha->dpc_flags))) {
4811 if (qla82xx_fcoe_ctx_reset(base_vha)) {
4812 /* FCoE-ctx reset failed.
4813 * Escalate to chip-reset
4814 */
4815 set_bit(ISP_ABORT_NEEDED,
4816 &base_vha->dpc_flags);
4817 }
4818 clear_bit(ABORT_ISP_ACTIVE,
4819 &base_vha->dpc_flags);
4820 }
4821
7c3df132
SK		 4822 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
4823 "FCoE context reset end.\n");
a9083016 4824 }
8ae6d9c7
GM		 4825 } else if (IS_QLAFX00(ha)) {
4826 if (test_and_clear_bit(ISP_UNRECOVERABLE,
4827 &base_vha->dpc_flags)) {
4828 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
4829 "Firmware Reset Recovery\n");
4830 if (qlafx00_reset_initialize(base_vha)) {
4831 /* Failed. Abort isp later. */
4832 if (!test_bit(UNLOADING,
4833 &base_vha->dpc_flags))
4834 set_bit(ISP_UNRECOVERABLE,
4835 &base_vha->dpc_flags);
4836 ql_dbg(ql_dbg_dpc, base_vha,
4837 0x4021,
4838 "Reset Recovery Failed\n");
4839 }
4840 }
4841
4842 if (test_and_clear_bit(FX00_TARGET_SCAN,
4843 &base_vha->dpc_flags)) {
4844 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
4845 "ISPFx00 Target Scan scheduled\n");
4846 if (qlafx00_rescan_isp(base_vha)) {
4847 if (!test_bit(UNLOADING,
4848 &base_vha->dpc_flags))
4849 set_bit(ISP_UNRECOVERABLE,
4850 &base_vha->dpc_flags);
4851 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
4852 "ISPFx00 Target Scan Failed\n");
4853 }
4854 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
4855 "ISPFx00 Target Scan End\n");
4856 }
a9083016
GM		 4857 }
4858
e315cd28
AC		 4859 if (test_and_clear_bit(ISP_ABORT_NEEDED,
4860 &base_vha->dpc_flags)) {
1da177e4 4861
7c3df132
SK		 4862 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
4863 "ISP abort scheduled.\n");
1da177e4 4864 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 4865 &base_vha->dpc_flags))) {
1da177e4 4866
a9083016 4867 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 4868 /* failed. retry later */
4869 set_bit(ISP_ABORT_NEEDED,
e315cd28 4870 &base_vha->dpc_flags);
99363ef8 4871 }
e315cd28
AC		 4872 clear_bit(ABORT_ISP_ACTIVE,
4873 &base_vha->dpc_flags);
99363ef8
SJ		 4874 }
4875
7c3df132
SK		 4876 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
4877 "ISP abort end.\n");
1da177e4
LT		 4878 }
4879
a394aac8
DJ		 4880 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
4881 &base_vha->dpc_flags)) {
e315cd28 4882 qla2x00_update_fcports(base_vha);
c9c5ced9 4883 }
d97994dc 4884
2d70c103
NB		 4885 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
4886 int ret;
4887 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
4888 if (ret != QLA_SUCCESS)
4889 ql_log(ql_log_warn, base_vha, 0x121,
4890 "Failed to enable receiving of RSCN "
4891 "requests: 0x%x.\n", ret);
4892 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
4893 }
4894
8ae6d9c7
GM		 4895 if (IS_QLAFX00(ha))
4896 goto loop_resync_check;
4897
579d12b5 4898 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 4899 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
4900 "Quiescence mode scheduled.\n");
7ec0effd
AD		 4901 if (IS_P3P_TYPE(ha)) {
4902 if (IS_QLA82XX(ha))
4903 qla82xx_device_state_handler(base_vha);
4904 if (IS_QLA8044(ha))
4905 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 4906 clear_bit(ISP_QUIESCE_NEEDED,
4907 &base_vha->dpc_flags);
4908 if (!ha->flags.quiesce_owner) {
4909 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 4910 if (IS_QLA82XX(ha)) {
4911 qla82xx_idc_lock(ha);
4912 qla82xx_clear_qsnt_ready(
4913 base_vha);
4914 qla82xx_idc_unlock(ha);
4915 } else if (IS_QLA8044(ha)) {
4916 qla8044_idc_lock(ha);
4917 qla8044_clear_qsnt_ready(
4918 base_vha);
4919 qla8044_idc_unlock(ha);
4920 }
8fcd6b8b
CD		 4921 }
4922 } else {
4923 clear_bit(ISP_QUIESCE_NEEDED,
4924 &base_vha->dpc_flags);
4925 qla2x00_quiesce_io(base_vha);
579d12b5 4926 }
7c3df132
SK		 4927 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
4928 "Quiescence mode end.\n");
579d12b5
SK		 4929 }
4930
e315cd28 4931 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 4932 &base_vha->dpc_flags) &&
e315cd28 4933 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 4934
7c3df132
SK		 4935 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
4936 "Reset marker scheduled.\n");
e315cd28
AC		 4937 qla2x00_rst_aen(base_vha);
4938 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 4939 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
4940 "Reset marker end.\n");
1da177e4
LT		 4941 }
4942
4943 /* Retry each device up to login retry count */
e315cd28
AC		 4944 if ((test_and_clear_bit(RELOGIN_NEEDED,
4945 &base_vha->dpc_flags)) &&
4946 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
4947 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 4948
7c3df132
SK		 4949 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
4950 "Relogin scheduled.\n");
e315cd28 4951 qla2x00_relogin(base_vha);
7c3df132
SK		 4952 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
4953 "Relogin end.\n");
1da177e4 4954 }
8ae6d9c7 4955loop_resync_check:
e315cd28 4956 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 4957 &base_vha->dpc_flags)) {
1da177e4 4958
7c3df132
SK		 4959 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
4960 "Loop resync scheduled.\n");
1da177e4
LT		 4961
4962 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 4963 &base_vha->dpc_flags))) {
1da177e4 4964
e315cd28 4965 rval = qla2x00_loop_resync(base_vha);
1da177e4 4966
e315cd28
AC		 4967 clear_bit(LOOP_RESYNC_ACTIVE,
4968 &base_vha->dpc_flags);
1da177e4
LT		 4969 }
4970
7c3df132
SK		 4971 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
4972 "Loop resync end.\n");
1da177e4
LT		 4973 }
4974
8ae6d9c7
GM		 4975 if (IS_QLAFX00(ha))
4976 goto intr_on_check;
4977
e315cd28
AC		 4978 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
4979 atomic_read(&base_vha->loop_state) == LOOP_READY) {
4980 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
4981 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 4982 }
4983
3c290d0b
CD		 4984 if (test_and_clear_bit(HOST_RAMP_DOWN_QUEUE_DEPTH,
4985 &base_vha->dpc_flags)) {
4986 /* Prevents simultaneous ramp up and down */
4987 clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4988 &base_vha->dpc_flags);
4989 qla2x00_host_ramp_down_queuedepth(base_vha);
4990 }
4991
4992 if (test_and_clear_bit(HOST_RAMP_UP_QUEUE_DEPTH,
4993 &base_vha->dpc_flags))
4994 qla2x00_host_ramp_up_queuedepth(base_vha);
8ae6d9c7 4995intr_on_check:
1da177e4 4996 if (!ha->interrupts_on)
fd34f556 4997 ha->isp_ops->enable_intrs(ha);
1da177e4 4998
e315cd28
AC		 4999 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
5000 &base_vha->dpc_flags))
5001 ha->isp_ops->beacon_blink(base_vha);
f6df144c 5002
8ae6d9c7
GM		 5003 if (!IS_QLAFX00(ha))
5004 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5005
1da177e4 5006 ha->dpc_active = 0;
c142caf0 5007end_loop:
563585ec 5008 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5009 } /* End of while(1) */
563585ec 5010 __set_current_state(TASK_RUNNING);
1da177e4 5011
7c3df132
SK		 5012 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5013 "DPC handler exiting.\n");
1da177e4
LT		 5014
5015 /*
5016 * Make sure that nobody tries to wake us up again.
5017 */
1da177e4
LT		 5018 ha->dpc_active = 0;
5019
ac280b67
AV		 5020 /* Cleanup any residual CTX SRBs. */
5021 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5022
39a11240
CH		 5023 return 0;
5024}
5025
5026void
e315cd28 5027qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5028{
e315cd28 5029 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5030 struct task_struct *t = ha->dpc_thread;
5031
e315cd28 5032 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5033 wake_up_process(t);
1da177e4
LT		 5034}
5035
1da177e4
LT		 5036/*
5037* qla2x00_rst_aen
5038* Processes asynchronous reset.
5039*
5040* Input:
5041* ha = adapter block pointer.
5042*/
5043static void
e315cd28 5044qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5045{
e315cd28
AC		 5046 if (vha->flags.online && !vha->flags.reset_active &&
5047 !atomic_read(&vha->loop_down_timer) &&
5048 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5049 do {
e315cd28 5050 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5051
5052 /*
5053 * Issue marker command only when we are going to start
5054 * the I/O.
5055 */
e315cd28
AC		 5056 vha->marker_needed = 1;
5057 } while (!atomic_read(&vha->loop_down_timer) &&
5058 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5059 }
5060}
5061
1da177e4
LT		 5062/**************************************************************************
5063* qla2x00_timer
5064*
5065* Description:
5066* One second timer
5067*
5068* Context: Interrupt
5069***************************************************************************/
2c3dfe3f 5070void
e315cd28 5071qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5072{
1da177e4 5073 unsigned long cpu_flags = 0;
1da177e4
LT		 5074 int start_dpc = 0;
5075 int index;
5076 srb_t *sp;
85880801 5077 uint16_t w;
e315cd28 5078 struct qla_hw_data *ha = vha->hw;
73208dfd 5079 struct req_que *req;
85880801 5080
a5b36321 5081 if (ha->flags.eeh_busy) {
7c3df132
SK		 5082 ql_dbg(ql_dbg_timer, vha, 0x6000,
5083 "EEH = %d, restarting timer.\n",
5084 ha->flags.eeh_busy);
a5b36321
LC		 5085 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5086 return;
5087 }
5088
85880801
AV		 5089 /* Hardware read to raise pending EEH errors during mailbox waits. */
5090 if (!pci_channel_offline(ha->pdev))
5091 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
1da177e4 5092
cefcaba6 5093 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5094 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5095 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5096 start_dpc++;
7ec0effd
AD		 5097 if (IS_QLA82XX(ha))
5098 qla82xx_watchdog(vha);
5099 else if (IS_QLA8044(ha))
5100 qla8044_watchdog(vha);
579d12b5
SK		 5101 }
5102
8ae6d9c7
GM		 5103 if (!vha->vp_idx && IS_QLAFX00(ha))
5104 qlafx00_timer_routine(vha);
5105
1da177e4 5106 /* Loop down handler. */
e315cd28 5107 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5108 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5109 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5110 && vha->flags.online) {
1da177e4 5111
e315cd28
AC		 5112 if (atomic_read(&vha->loop_down_timer) ==
5113 vha->loop_down_abort_time) {
1da177e4 5114
7c3df132
SK		 5115 ql_log(ql_log_info, vha, 0x6008,
5116 "Loop down - aborting the queues before time expires.\n");
1da177e4 5117
e315cd28
AC		 5118 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5119 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5120
f08b7251
AV		 5121 /*
5122 * Schedule an ISP abort to return any FCP2-device
5123 * commands.
5124 */
2c3dfe3f 5125 /* NPIV - scan physical port only */
e315cd28 5126 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5127 spin_lock_irqsave(&ha->hardware_lock,
5128 cpu_flags);
73208dfd 5129 req = ha->req_q_map[0];
2c3dfe3f 5130 for (index = 1;
8d93f550 5131 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5132 index++) {
5133 fc_port_t *sfcp;
5134
e315cd28 5135 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5136 if (!sp)
5137 continue;
9ba56b95 5138 if (sp->type != SRB_SCSI_CMD)
cf53b069 5139 continue;
2c3dfe3f 5140 sfcp = sp->fcport;
f08b7251 5141 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5142 continue;
bdf79621 5143
8f7daead
GM		 5144 if (IS_QLA82XX(ha))
5145 set_bit(FCOE_CTX_RESET_NEEDED,
5146 &vha->dpc_flags);
5147 else
5148 set_bit(ISP_ABORT_NEEDED,
e315cd28 5149 &vha->dpc_flags);
2c3dfe3f
SJ		 5150 break;
5151 }
5152 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5153 cpu_flags);
1da177e4 5154 }
1da177e4
LT		 5155 start_dpc++;
5156 }
5157
5158 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5159 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5160 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5161 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5162 "Loop down - aborting ISP.\n");
5163
8f7daead
GM		 5164 if (IS_QLA82XX(ha))
5165 set_bit(FCOE_CTX_RESET_NEEDED,
5166 &vha->dpc_flags);
5167 else
5168 set_bit(ISP_ABORT_NEEDED,
5169 &vha->dpc_flags);
1da177e4
LT		 5170 }
5171 }
7c3df132
SK		 5172 ql_dbg(ql_dbg_timer, vha, 0x600a,
5173 "Loop down - seconds remaining %d.\n",
5174 atomic_read(&vha->loop_down_timer));
1da177e4
LT		 5175 }
5176
cefcaba6
SK		 5177 /* Check if beacon LED needs to be blinked for physical host only */
5178 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5179 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5180 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5181 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5182 start_dpc++;
5183 }
f6df144c
AV		 5184 }
5185
550bf57d 5186 /* Process any deferred work. */
e315cd28 5187 if (!list_empty(&vha->work_list))
550bf57d
AV		 5188 start_dpc++;
5189
1da177e4 5190 /* Schedule the DPC routine if needed */
e315cd28
AC		 5191 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5192 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5193 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5194 start_dpc ||
e315cd28
AC		 5195 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5196 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5197 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5198 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5199 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
3c290d0b
CD		 5200 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) ||
5201 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags) ||
5202 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags))) {
7c3df132
SK		 5203 ql_dbg(ql_dbg_timer, vha, 0x600b,
5204 "isp_abort_needed=%d loop_resync_needed=%d "
5205 "fcport_update_needed=%d start_dpc=%d "
5206 "reset_marker_needed=%d",
5207 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5208 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5209 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5210 start_dpc,
5211 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5212 ql_dbg(ql_dbg_timer, vha, 0x600c,
5213 "beacon_blink_needed=%d isp_unrecoverable=%d "
5214 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
3c290d0b
CD		 5215 "relogin_needed=%d, host_ramp_down_needed=%d "
5216 "host_ramp_up_needed=%d.\n",
7c3df132
SK		 5217 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5218 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5219 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5220 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
3c290d0b
CD		 5221 test_bit(RELOGIN_NEEDED, &vha->dpc_flags),
5222 test_bit(HOST_RAMP_UP_QUEUE_DEPTH, &vha->dpc_flags),
5223 test_bit(HOST_RAMP_DOWN_QUEUE_DEPTH, &vha->dpc_flags));
e315cd28 5224 qla2xxx_wake_dpc(vha);
7c3df132 5225 }
1da177e4 5226
e315cd28 5227 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5228}
5229
5433383e
AV		 5230/* Firmware interface routines. */
5231
6246b8a1 5232#define FW_BLOBS 10
5433383e
AV		 5233#define FW_ISP21XX 0
5234#define FW_ISP22XX 1
5235#define FW_ISP2300 2
5236#define FW_ISP2322 3
48c02fde 5237#define FW_ISP24XX 4
c3a2f0df 5238#define FW_ISP25XX 5
3a03eb79 5239#define FW_ISP81XX 6
a9083016 5240#define FW_ISP82XX 7
6246b8a1
GM		 5241#define FW_ISP2031 8
5242#define FW_ISP8031 9
5433383e 5243
bb8ee499
AV		 5244#define FW_FILE_ISP21XX "ql2100_fw.bin"
5245#define FW_FILE_ISP22XX "ql2200_fw.bin"
5246#define FW_FILE_ISP2300 "ql2300_fw.bin"
5247#define FW_FILE_ISP2322 "ql2322_fw.bin"
5248#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5249#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5250#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5251#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5252#define FW_FILE_ISP2031 "ql2600_fw.bin"
5253#define FW_FILE_ISP8031 "ql8300_fw.bin"
bb8ee499 5254
e1e82b6f 5255static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5256
5257static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5258 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5259 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5260 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5261 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5262 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5263 { .name = FW_FILE_ISP25XX, },
3a03eb79 5264 { .name = FW_FILE_ISP81XX, },
a9083016 5265 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5266 { .name = FW_FILE_ISP2031, },
5267 { .name = FW_FILE_ISP8031, },
5433383e
AV		 5268};
5269
5270struct fw_blob *
e315cd28 5271qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5272{
e315cd28 5273 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5274 struct fw_blob *blob;
5275
5433383e
AV		 5276 if (IS_QLA2100(ha)) {
5277 blob = &qla_fw_blobs[FW_ISP21XX];
5278 } else if (IS_QLA2200(ha)) {
5279 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5280 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5281 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5282 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5283 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5284 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5285 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5286 } else if (IS_QLA25XX(ha)) {
5287 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5288 } else if (IS_QLA81XX(ha)) {
5289 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5290 } else if (IS_QLA82XX(ha)) {
5291 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5292 } else if (IS_QLA2031(ha)) {
5293 blob = &qla_fw_blobs[FW_ISP2031];
5294 } else if (IS_QLA8031(ha)) {
5295 blob = &qla_fw_blobs[FW_ISP8031];
8a655229
DC		 5296 } else {
5297 return NULL;
5433383e
AV		 5298 }
5299
e1e82b6f 5300 mutex_lock(&qla_fw_lock);
5433383e
AV		 5301 if (blob->fw)
5302 goto out;
5303
5304 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5305 ql_log(ql_log_warn, vha, 0x0063,
5306 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5307 blob->fw = NULL;
5308 blob = NULL;
5309 goto out;
5310 }
5311
5312out:
e1e82b6f 5313 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5314 return blob;
5315}
5316
5317static void
5318qla2x00_release_firmware(void)
5319{
5320 int idx;
5321
e1e82b6f 5322 mutex_lock(&qla_fw_lock);
5433383e 5323 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5324 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5325 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5326}
5327
14e660e6
SJ		 5328static pci_ers_result_t
5329qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5330{
85880801
AV		 5331 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5332 struct qla_hw_data *ha = vha->hw;
5333
7c3df132
SK		 5334 ql_dbg(ql_dbg_aer, vha, 0x9000,
5335 "PCI error detected, state %x.\n", state);
b9b12f73 5336
14e660e6
SJ		 5337 switch (state) {
5338 case pci_channel_io_normal:
85880801 5339 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5340 return PCI_ERS_RESULT_CAN_RECOVER;
5341 case pci_channel_io_frozen:
85880801 5342 ha->flags.eeh_busy = 1;
a5b36321
LC		 5343 /* For ISP82XX complete any pending mailbox cmd */
5344 if (IS_QLA82XX(ha)) {
7190575f 5345 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5346 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5347 qla82xx_clear_pending_mbx(vha);
a5b36321 5348 }
90a86fc0 5349 qla2x00_free_irqs(vha);
14e660e6 5350 pci_disable_device(pdev);
bddd2d65
LC		 5351 /* Return back all IOs */
5352 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
14e660e6
SJ		 5353 return PCI_ERS_RESULT_NEED_RESET;
5354 case pci_channel_io_perm_failure:
85880801
AV		 5355 ha->flags.pci_channel_io_perm_failure = 1;
5356 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
14e660e6
SJ		 5357 return PCI_ERS_RESULT_DISCONNECT;
5358 }
5359 return PCI_ERS_RESULT_NEED_RESET;
5360}
5361
5362static pci_ers_result_t
5363qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5364{
5365 int risc_paused = 0;
5366 uint32_t stat;
5367 unsigned long flags;
e315cd28
AC		 5368 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5369 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5370 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5371 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5372
bcc5b6d3
SK		 5373 if (IS_QLA82XX(ha))
5374 return PCI_ERS_RESULT_RECOVERED;
5375
14e660e6
SJ		 5376 spin_lock_irqsave(&ha->hardware_lock, flags);
5377 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5378 stat = RD_REG_DWORD(&reg->hccr);
5379 if (stat & HCCR_RISC_PAUSE)
5380 risc_paused = 1;
5381 } else if (IS_QLA23XX(ha)) {
5382 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5383 if (stat & HSR_RISC_PAUSED)
5384 risc_paused = 1;
5385 } else if (IS_FWI2_CAPABLE(ha)) {
5386 stat = RD_REG_DWORD(&reg24->host_status);
5387 if (stat & HSRX_RISC_PAUSED)
5388 risc_paused = 1;
5389 }
5390 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5391
5392 if (risc_paused) {
7c3df132
SK		 5393 ql_log(ql_log_info, base_vha, 0x9003,
5394 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5395 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5396
5397 return PCI_ERS_RESULT_NEED_RESET;
5398 } else
5399 return PCI_ERS_RESULT_RECOVERED;
5400}
5401
fa492630
SK		 5402static uint32_t
5403qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5404{
5405 uint32_t rval = QLA_FUNCTION_FAILED;
5406 uint32_t drv_active = 0;
5407 struct qla_hw_data *ha = base_vha->hw;
5408 int fn;
5409 struct pci_dev *other_pdev = NULL;
5410
7c3df132
SK		 5411 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5412 "Entered %s.\n", __func__);
a5b36321
LC		 5413
5414 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5415
5416 if (base_vha->flags.online) {
5417 /* Abort all outstanding commands,
5418 * so as to be requeued later */
5419 qla2x00_abort_isp_cleanup(base_vha);
5420 }
5421
5422
5423 fn = PCI_FUNC(ha->pdev->devfn);
5424 while (fn > 0) {
5425 fn--;
7c3df132
SK		 5426 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5427 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5428 other_pdev =
5429 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5430 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5431 fn));
5432
5433 if (!other_pdev)
5434 continue;
5435 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5436 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5437 "Found PCI func available and enable at 0x%x.\n",
5438 fn);
a5b36321
LC		 5439 pci_dev_put(other_pdev);
5440 break;
5441 }
5442 pci_dev_put(other_pdev);
5443 }
5444
5445 if (!fn) {
5446 /* Reset owner */
7c3df132
SK		 5447 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5448 "This devfn is reset owner = 0x%x.\n",
5449 ha->pdev->devfn);
a5b36321
LC		 5450 qla82xx_idc_lock(ha);
5451
5452 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5453 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 5454
5455 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
5456 QLA82XX_IDC_VERSION);
5457
5458 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 5459 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
5460 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 5461
5462 qla82xx_idc_unlock(ha);
5463 /* Reset if device is not already reset
5464 * drv_active would be 0 if a reset has already been done
5465 */
5466 if (drv_active)
5467 rval = qla82xx_start_firmware(base_vha);
5468 else
5469 rval = QLA_SUCCESS;
5470 qla82xx_idc_lock(ha);
5471
5472 if (rval != QLA_SUCCESS) {
7c3df132
SK		 5473 ql_log(ql_log_info, base_vha, 0x900b,
5474 "HW State: FAILED.\n");
a5b36321
LC		 5475 qla82xx_clear_drv_active(ha);
5476 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5477 QLA8XXX_DEV_FAILED);
a5b36321 5478 } else {
7c3df132
SK		 5479 ql_log(ql_log_info, base_vha, 0x900c,
5480 "HW State: READY.\n");
a5b36321 5481 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 5482 QLA8XXX_DEV_READY);
a5b36321 5483 qla82xx_idc_unlock(ha);
7190575f 5484 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5485 rval = qla82xx_restart_isp(base_vha);
5486 qla82xx_idc_lock(ha);
5487 /* Clear driver state register */
5488 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
5489 qla82xx_set_drv_active(base_vha);
5490 }
5491 qla82xx_idc_unlock(ha);
5492 } else {
7c3df132
SK		 5493 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
5494 "This devfn is not reset owner = 0x%x.\n",
5495 ha->pdev->devfn);
a5b36321 5496 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 5497 QLA8XXX_DEV_READY)) {
7190575f 5498 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 5499 rval = qla82xx_restart_isp(base_vha);
5500 qla82xx_idc_lock(ha);
5501 qla82xx_set_drv_active(base_vha);
5502 qla82xx_idc_unlock(ha);
5503 }
5504 }
5505 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5506
5507 return rval;
5508}
5509
14e660e6
SJ		 5510static pci_ers_result_t
5511qla2xxx_pci_slot_reset(struct pci_dev *pdev)
5512{
5513 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 5514 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5515 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 5516 struct rsp_que *rsp;
5517 int rc, retries = 10;
09483916 5518
7c3df132
SK		 5519 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
5520 "Slot Reset.\n");
85880801 5521
90a86fc0
JC		 5522 /* Workaround: qla2xxx driver which access hardware earlier
5523 * needs error state to be pci_channel_io_online.
5524 * Otherwise mailbox command timesout.
5525 */
5526 pdev->error_state = pci_channel_io_normal;
5527
5528 pci_restore_state(pdev);
5529
8c1496bd
RL		 5530 /* pci_restore_state() clears the saved_state flag of the device
5531 * save restored state which resets saved_state flag
5532 */
5533 pci_save_state(pdev);
5534
09483916
BH		 5535 if (ha->mem_only)
5536 rc = pci_enable_device_mem(pdev);
5537 else
5538 rc = pci_enable_device(pdev);
14e660e6 5539
09483916 5540 if (rc) {
7c3df132 5541 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 5542 "Can't re-enable PCI device after reset.\n");
a5b36321 5543 goto exit_slot_reset;
14e660e6 5544 }
14e660e6 5545
90a86fc0
JC		 5546 rsp = ha->rsp_q_map[0];
5547 if (qla2x00_request_irqs(ha, rsp))
a5b36321 5548 goto exit_slot_reset;
90a86fc0 5549
e315cd28 5550 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 5551 goto exit_slot_reset;
5552
5553 if (IS_QLA82XX(ha)) {
5554 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
5555 ret = PCI_ERS_RESULT_RECOVERED;
5556 goto exit_slot_reset;
5557 } else
5558 goto exit_slot_reset;
5559 }
14e660e6 5560
90a86fc0
JC		 5561 while (ha->flags.mbox_busy && retries--)
5562 msleep(1000);
85880801 5563
e315cd28 5564 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 5565 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 5566 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 5567 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 5568
90a86fc0 5569
a5b36321 5570exit_slot_reset:
7c3df132
SK		 5571 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
5572 "slot_reset return %x.\n", ret);
85880801 5573
14e660e6
SJ		 5574 return ret;
5575}
5576
5577static void
5578qla2xxx_pci_resume(struct pci_dev *pdev)
5579{
e315cd28
AC		 5580 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5581 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5582 int ret;
5583
7c3df132
SK		 5584 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
5585 "pci_resume.\n");
85880801 5586
e315cd28 5587 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 5588 if (ret != QLA_SUCCESS) {
7c3df132
SK		 5589 ql_log(ql_log_fatal, base_vha, 0x9002,
5590 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 5591 }
85880801 5592
3e46f031
LC		 5593 pci_cleanup_aer_uncorrect_error_status(pdev);
5594
85880801 5595 ha->flags.eeh_busy = 0;
14e660e6
SJ		 5596}
5597
a55b2d21 5598static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 5599 .error_detected = qla2xxx_pci_error_detected,
5600 .mmio_enabled = qla2xxx_pci_mmio_enabled,
5601 .slot_reset = qla2xxx_pci_slot_reset,
5602 .resume = qla2xxx_pci_resume,
5603};
5604
5433383e 5605static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 5606 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
5607 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
5608 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
5609 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
5610 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
5611 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
5612 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
5613 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
5614 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 5615 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 5616 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
5617 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 5618 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 5619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 5620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 5621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 5622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 5623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 5624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
5433383e
AV		 5625 { 0 },
5626};
5627MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
5628
fca29703 5629static struct pci_driver qla2xxx_pci_driver = {
cb63067a 5630 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 5631 .driver = {
5632 .owner = THIS_MODULE,
5633 },
fca29703 5634 .id_table = qla2xxx_pci_tbl,
7ee61397 5635 .probe = qla2x00_probe_one,
4c993f76 5636 .remove = qla2x00_remove_one,
e30d1756 5637 .shutdown = qla2x00_shutdown,
14e660e6 5638 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 5639};
5640
75ef9de1 5641static const struct file_operations apidev_fops = {
6a03b4cd 5642 .owner = THIS_MODULE,
6038f373 5643 .llseek = noop_llseek,
6a03b4cd
HZ		 5644};
5645
1da177e4
LT		 5646/**
5647 * qla2x00_module_init - Module initialization.
5648 **/
5649static int __init
5650qla2x00_module_init(void)
5651{
fca29703
AV		 5652 int ret = 0;
5653
1da177e4 5654 /* Allocate cache for SRBs. */
354d6b21 5655 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 5656 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 5657 if (srb_cachep == NULL) {
7c3df132
SK		 5658 ql_log(ql_log_fatal, NULL, 0x0001,
5659 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 5660 return -ENOMEM;
5661 }
5662
2d70c103
NB		 5663 /* Initialize target kmem_cache and mem_pools */
5664 ret = qlt_init();
5665 if (ret < 0) {
5666 kmem_cache_destroy(srb_cachep);
5667 return ret;
5668 } else if (ret > 0) {
5669 /*
5670 * If initiator mode is explictly disabled by qlt_init(),
5671 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
5672 * performing scsi_scan_target() during LOOP UP event.
5673 */
5674 qla2xxx_transport_functions.disable_target_scan = 1;
5675 qla2xxx_transport_vport_functions.disable_target_scan = 1;
5676 }
5677
1da177e4
LT		 5678 /* Derive version string. */
5679 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 5680 if (ql2xextended_error_logging)
0181944f
AV		 5681 strcat(qla2x00_version_str, "-debug");
5682
1c97a12a
AV		 5683 qla2xxx_transport_template =
5684 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 5685 if (!qla2xxx_transport_template) {
5686 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 5687 ql_log(ql_log_fatal, NULL, 0x0002,
5688 "fc_attach_transport failed...Failing load!.\n");
2d70c103 5689 qlt_exit();
1da177e4 5690 return -ENODEV;
2c3dfe3f 5691 }
6a03b4cd
HZ		 5692
5693 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
5694 if (apidev_major < 0) {
7c3df132
SK		 5695 ql_log(ql_log_fatal, NULL, 0x0003,
5696 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 5697 }
5698
2c3dfe3f
SJ		 5699 qla2xxx_transport_vport_template =
5700 fc_attach_transport(&qla2xxx_transport_vport_functions);
5701 if (!qla2xxx_transport_vport_template) {
5702 kmem_cache_destroy(srb_cachep);
2d70c103 5703 qlt_exit();
2c3dfe3f 5704 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 5705 ql_log(ql_log_fatal, NULL, 0x0004,
5706 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 5707 return -ENODEV;
2c3dfe3f 5708 }
7c3df132
SK		 5709 ql_log(ql_log_info, NULL, 0x0005,
5710 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 5711 qla2x00_version_str);
7ee61397 5712 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 5713 if (ret) {
5714 kmem_cache_destroy(srb_cachep);
2d70c103 5715 qlt_exit();
fca29703 5716 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5717 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 5718 ql_log(ql_log_fatal, NULL, 0x0006,
5719 "pci_register_driver failed...ret=%d Failing load!.\n",
5720 ret);
fca29703
AV		 5721 }
5722 return ret;
1da177e4
LT		 5723}
5724
5725/**
5726 * qla2x00_module_exit - Module cleanup.
5727 **/
5728static void __exit
5729qla2x00_module_exit(void)
5730{
6a03b4cd 5731 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 5732 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 5733 qla2x00_release_firmware();
354d6b21 5734 kmem_cache_destroy(srb_cachep);
2d70c103 5735 qlt_exit();
a9083016
GM		 5736 if (ctx_cachep)
5737 kmem_cache_destroy(ctx_cachep);
1da177e4 5738 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 5739 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 5740}
5741
5742module_init(qla2x00_module_init);
5743module_exit(qla2x00_module_exit);
5744
5745MODULE_AUTHOR("QLogic Corporation");
5746MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
5747MODULE_LICENSE("GPL");
5748MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 5749MODULE_FIRMWARE(FW_FILE_ISP21XX);
5750MODULE_FIRMWARE(FW_FILE_ISP22XX);
5751MODULE_FIRMWARE(FW_FILE_ISP2300);
5752MODULE_FIRMWARE(FW_FILE_ISP2322);
5753MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 5754MODULE_FIRMWARE(FW_FILE_ISP25XX);
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