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scsi: qla2xxx: Update fw_started flags at qpair creation.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
3822263e 203int ql2xasynctmfenable;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
1da177e4 265/*
fa2a1ce5 266 * SCSI host template entry points
1da177e4
LT		 267 */
268static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 269static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 270static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
271static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 272static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 273static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 274static int qla2xxx_eh_abort(struct scsi_cmnd *);
275static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 276static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 277static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
278static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 279
1a2fbf18 280static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 281static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 282static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 283static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 284static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 285
a5326f86 286struct scsi_host_template qla2xxx_driver_template = {
1da177e4 287 .module = THIS_MODULE,
cb63067a 288 .name = QLA2XXX_DRIVER_NAME,
a5326f86 289 .queuecommand = qla2xxx_queuecommand,
fca29703 290
b6a05c82 291 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 292 .eh_abort_handler = qla2xxx_eh_abort,
293 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 294 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 295 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
296 .eh_host_reset_handler = qla2xxx_eh_host_reset,
297
298 .slave_configure = qla2xxx_slave_configure,
299
300 .slave_alloc = qla2xxx_slave_alloc,
301 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 302 .scan_finished = qla2xxx_scan_finished,
303 .scan_start = qla2xxx_scan_start,
db5ed4df 304 .change_queue_depth = scsi_change_queue_depth,
5601236b 305 .map_queues = qla2xxx_map_queues,
fca29703
AV		 306 .this_id = -1,
307 .cmd_per_lun = 3,
308 .use_clustering = ENABLE_CLUSTERING,
309 .sg_tablesize = SG_ALL,
310
311 .max_sectors = 0xFFFF,
afb046e2 312 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 313
314 .supported_mode = MODE_INITIATOR,
c40ecc12 315 .track_queue_depth = 1,
fca29703
AV		 316};
317
1da177e4 318static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 319struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 320
1da177e4
LT		 321/* TODO Convert to inlines
322 *
323 * Timer routines
324 */
1da177e4 325
2c3dfe3f 326__inline__ void
e315cd28 327qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 328{
e315cd28
AC		 329 init_timer(&vha->timer);
330 vha->timer.expires = jiffies + interval * HZ;
331 vha->timer.data = (unsigned long)vha;
332 vha->timer.function = (void (*)(unsigned long))func;
333 add_timer(&vha->timer);
334 vha->timer_active = 1;
1da177e4
LT		 335}
336
337static inline void
e315cd28 338qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 339{
a9083016 340 /* Currently used for 82XX only. */
7c3df132
SK		 341 if (vha->device_flags & DFLG_DEV_FAILED) {
342 ql_dbg(ql_dbg_timer, vha, 0x600d,
343 "Device in a failed state, returning.\n");
a9083016 344 return;
7c3df132 345 }
a9083016 346
e315cd28 347 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 348}
349
a824ebb3 350static __inline__ void
e315cd28 351qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 352{
e315cd28
AC		 353 del_timer_sync(&vha->timer);
354 vha->timer_active = 0;
1da177e4
LT		 355}
356
1da177e4
LT		 357static int qla2x00_do_dpc(void *data);
358
359static void qla2x00_rst_aen(scsi_qla_host_t *);
360
73208dfd
AC		 361static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
362 struct req_que **, struct rsp_que **);
e30d1756 363static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 364static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 365int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
366 struct qla_qpair *qpair);
1da177e4 367
1da177e4 368/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 369static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
370 struct rsp_que *rsp)
371{
372 struct qla_hw_data *ha = vha->hw;
373 rsp->qpair = ha->base_qpair;
374 rsp->req = req;
375 ha->base_qpair->req = req;
376 ha->base_qpair->rsp = rsp;
377 ha->base_qpair->vha = vha;
378 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
379 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
380 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
381 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
382 ha->base_qpair->enable_class_2 = ql2xenableclass2;
383 /* init qpair to this cpu. Will adjust at run time. */
384 qla_cpu_update(rsp->qpair, smp_processor_id());
385 ha->base_qpair->pdev = ha->pdev;
386
387 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
388 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
389}
390
9a347ff4
CD		 391static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
392 struct rsp_que *rsp)
73208dfd 393{
7c3df132 394 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 395 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 396 GFP_KERNEL);
397 if (!ha->req_q_map) {
7c3df132
SK		 398 ql_log(ql_log_fatal, vha, 0x003b,
399 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 400 goto fail_req_map;
401 }
402
2afa19a9 403 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 404 GFP_KERNEL);
405 if (!ha->rsp_q_map) {
7c3df132
SK		 406 ql_log(ql_log_fatal, vha, 0x003c,
407 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 408 goto fail_rsp_map;
409 }
d7459527 410
e326d22a
QT		 411 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
412 if (ha->base_qpair == NULL) {
413 ql_log(ql_log_warn, vha, 0x00e0,
414 "Failed to allocate base queue pair memory.\n");
415 goto fail_base_qpair;
416 }
417
8abfa9e2 418 qla_init_base_qpair(vha, req, rsp);
e326d22a 419
d7459527
MH		 420 if (ql2xmqsupport && ha->max_qpairs) {
421 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
422 GFP_KERNEL);
423 if (!ha->queue_pair_map) {
424 ql_log(ql_log_fatal, vha, 0x0180,
425 "Unable to allocate memory for queue pair ptrs.\n");
426 goto fail_qpair_map;
427 }
d7459527
MH		 428 }
429
9a347ff4
CD		 430 /*
431 * Make sure we record at least the request and response queue zero in
432 * case we need to free them if part of the probe fails.
433 */
434 ha->rsp_q_map[0] = rsp;
435 ha->req_q_map[0] = req;
73208dfd
AC		 436 set_bit(0, ha->rsp_qid_map);
437 set_bit(0, ha->req_qid_map);
438 return 1;
439
d7459527 440fail_qpair_map:
82de802a
QT		 441 kfree(ha->base_qpair);
442 ha->base_qpair = NULL;
443fail_base_qpair:
d7459527
MH		 444 kfree(ha->rsp_q_map);
445 ha->rsp_q_map = NULL;
73208dfd
AC		 446fail_rsp_map:
447 kfree(ha->req_q_map);
448 ha->req_q_map = NULL;
449fail_req_map:
450 return -ENOMEM;
451}
452
2afa19a9 453static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 454{
8ae6d9c7
GM		 455 if (IS_QLAFX00(ha)) {
456 if (req && req->ring_fx00)
457 dma_free_coherent(&ha->pdev->dev,
458 (req->length_fx00 + 1) * sizeof(request_t),
459 req->ring_fx00, req->dma_fx00);
460 } else if (req && req->ring)
73208dfd
AC		 461 dma_free_coherent(&ha->pdev->dev,
462 (req->length + 1) * sizeof(request_t),
463 req->ring, req->dma);
464
8d93f550
CD		 465 if (req)
466 kfree(req->outstanding_cmds);
467
73208dfd 468 kfree(req);
73208dfd
AC		 469}
470
2afa19a9
AC		 471static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
472{
8ae6d9c7
GM		 473 if (IS_QLAFX00(ha)) {
474 if (rsp && rsp->ring)
475 dma_free_coherent(&ha->pdev->dev,
476 (rsp->length_fx00 + 1) * sizeof(request_t),
477 rsp->ring_fx00, rsp->dma_fx00);
478 } else if (rsp && rsp->ring) {
2afa19a9
AC		 479 dma_free_coherent(&ha->pdev->dev,
480 (rsp->length + 1) * sizeof(response_t),
481 rsp->ring, rsp->dma);
8ae6d9c7 482 }
2afa19a9 483 kfree(rsp);
2afa19a9
AC		 484}
485
73208dfd
AC		 486static void qla2x00_free_queues(struct qla_hw_data *ha)
487{
488 struct req_que *req;
489 struct rsp_que *rsp;
490 int cnt;
093df737 491 unsigned long flags;
73208dfd 492
82de802a
QT		 493 if (ha->queue_pair_map) {
494 kfree(ha->queue_pair_map);
495 ha->queue_pair_map = NULL;
496 }
497 if (ha->base_qpair) {
498 kfree(ha->base_qpair);
499 ha->base_qpair = NULL;
500 }
501
093df737 502 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 503 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 504 if (!test_bit(cnt, ha->req_qid_map))
505 continue;
506
73208dfd 507 req = ha->req_q_map[cnt];
093df737
QT		 508 clear_bit(cnt, ha->req_qid_map);
509 ha->req_q_map[cnt] = NULL;
510
511 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 512 qla2x00_free_req_que(ha, req);
093df737 513 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 514 }
093df737
QT		 515 spin_unlock_irqrestore(&ha->hardware_lock, flags);
516
73208dfd
AC		 517 kfree(ha->req_q_map);
518 ha->req_q_map = NULL;
2afa19a9 519
093df737
QT		 520
521 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 522 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 523 if (!test_bit(cnt, ha->rsp_qid_map))
524 continue;
525
2afa19a9 526 rsp = ha->rsp_q_map[cnt];
c3c42394 527 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 528 ha->rsp_q_map[cnt] = NULL;
529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 530 qla2x00_free_rsp_que(ha, rsp);
093df737 531 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 532 }
093df737
QT		 533 spin_unlock_irqrestore(&ha->hardware_lock, flags);
534
2afa19a9
AC		 535 kfree(ha->rsp_q_map);
536 ha->rsp_q_map = NULL;
73208dfd
AC		 537}
538
1da177e4 539static char *
e315cd28 540qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 541{
e315cd28 542 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 543 static char *pci_bus_modes[] = {
544 "33", "66", "100", "133",
545 };
546 uint16_t pci_bus;
547
548 strcpy(str, "PCI");
549 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
550 if (pci_bus) {
551 strcat(str, "-X (");
552 strcat(str, pci_bus_modes[pci_bus]);
553 } else {
554 pci_bus = (ha->pci_attr & BIT_8) >> 8;
555 strcat(str, " (");
556 strcat(str, pci_bus_modes[pci_bus]);
557 }
558 strcat(str, " MHz)");
559
560 return (str);
561}
562
fca29703 563static char *
e315cd28 564qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 565{
566 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 567 struct qla_hw_data *ha = vha->hw;
fca29703 568 uint32_t pci_bus;
fca29703 569
62a276f8 570 if (pci_is_pcie(ha->pdev)) {
fca29703 571 char lwstr[6];
62a276f8 572 uint32_t lstat, lspeed, lwidth;
fca29703 573
62a276f8
BH		 574 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
575 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
576 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 577
578 strcpy(str, "PCIe (");
49300af7
SK		 579 switch (lspeed) {
580 case 1:
c87a0d8c 581 strcat(str, "2.5GT/s ");
49300af7
SK		 582 break;
583 case 2:
c87a0d8c 584 strcat(str, "5.0GT/s ");
49300af7
SK		 585 break;
586 case 3:
587 strcat(str, "8.0GT/s ");
588 break;
589 default:
fca29703 590 strcat(str, "<unknown> ");
49300af7
SK		 591 break;
592 }
fca29703
AV		 593 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
594 strcat(str, lwstr);
595
596 return str;
597 }
598
599 strcpy(str, "PCI");
600 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
601 if (pci_bus == 0 || pci_bus == 8) {
602 strcat(str, " (");
603 strcat(str, pci_bus_modes[pci_bus >> 3]);
604 } else {
605 strcat(str, "-X ");
606 if (pci_bus & BIT_2)
607 strcat(str, "Mode 2");
608 else
609 strcat(str, "Mode 1");
610 strcat(str, " (");
611 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
612 }
613 strcat(str, " MHz)");
614
615 return str;
616}
617
e5f82ab8 618static char *
df57caba 619qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 620{
621 char un_str[10];
e315cd28 622 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 623
df57caba
HM		 624 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
625 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 626
627 if (ha->fw_attributes & BIT_9) {
628 strcat(str, "FLX");
629 return (str);
630 }
631
632 switch (ha->fw_attributes & 0xFF) {
633 case 0x7:
634 strcat(str, "EF");
635 break;
636 case 0x17:
637 strcat(str, "TP");
638 break;
639 case 0x37:
640 strcat(str, "IP");
641 break;
642 case 0x77:
643 strcat(str, "VI");
644 break;
645 default:
646 sprintf(un_str, "(%x)", ha->fw_attributes);
647 strcat(str, un_str);
648 break;
649 }
650 if (ha->fw_attributes & 0x100)
651 strcat(str, "X");
652
653 return (str);
654}
655
e5f82ab8 656static char *
df57caba 657qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 658{
e315cd28 659 struct qla_hw_data *ha = vha->hw;
f0883ac6 660
df57caba 661 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 662 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 663 return str;
fca29703
AV		 664}
665
9ba56b95 666void
25ff6af1 667qla2x00_sp_free_dma(void *ptr)
fca29703 668{
25ff6af1
JC		 669 srb_t *sp = ptr;
670 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 671 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 672 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 673
9ba56b95
GM		 674 if (sp->flags & SRB_DMA_VALID) {
675 scsi_dma_unmap(cmd);
676 sp->flags &= ~SRB_DMA_VALID;
7c3df132 677 }
fca29703 678
9ba56b95
GM		 679 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
680 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
681 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
682 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
683 }
684
d5ff0eed
JC		 685 if (!ctx)
686 goto end;
687
9ba56b95
GM		 688 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
689 /* List assured to be having elements */
d5ff0eed 690 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 691 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
692 }
693
694 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 695 struct crc_context *ctx0 = ctx;
696
697 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 698 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
699 }
700
701 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 702 struct ct6_dsd *ctx1 = ctx;
fca29703 703
9ba56b95 704 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 705 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 706 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
707 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
708 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
709 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 710 }
711
d5ff0eed 712end:
6fcd98fd 713 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 714 CMD_SP(cmd) = NULL;
715 qla2x00_rel_sp(sp);
716 }
9ba56b95
GM		 717}
718
d7459527 719void
25ff6af1 720qla2x00_sp_compl(void *ptr, int res)
9ba56b95 721{
25ff6af1 722 srb_t *sp = ptr;
9ba56b95
GM		 723 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
724
725 cmd->result = res;
726
727 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 728 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 729 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
730 sp, GET_CMD_SP(sp));
731 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 732 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 733 return;
734 }
735 if (!atomic_dec_and_test(&sp->ref_count))
736 return;
737
25ff6af1 738 qla2x00_sp_free_dma(sp);
9ba56b95 739 cmd->scsi_done(cmd);
fca29703
AV		 740}
741
d7459527 742void
25ff6af1 743qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 744{
745 srb_t *sp = (srb_t *)ptr;
746 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
747 struct qla_hw_data *ha = sp->fcport->vha->hw;
748 void *ctx = GET_CMD_CTX_SP(sp);
749
750 if (sp->flags & SRB_DMA_VALID) {
751 scsi_dma_unmap(cmd);
752 sp->flags &= ~SRB_DMA_VALID;
753 }
754
755 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
756 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
757 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
758 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
759 }
760
d5ff0eed
JC		 761 if (!ctx)
762 goto end;
763
d7459527
MH		 764 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
765 /* List assured to be having elements */
d5ff0eed 766 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 767 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
768 }
769
770 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 771 struct crc_context *ctx0 = ctx;
772
773 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 774 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
775 }
776
777 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 778 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 779 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
780 ctx1->fcp_cmnd_dma);
781 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
782 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
783 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
784 mempool_free(ctx1, ha->ctx_mempool);
785 }
d5ff0eed 786end:
d7459527
MH		 787 CMD_SP(cmd) = NULL;
788 qla2xxx_rel_qpair_sp(sp->qpair, sp);
789}
790
791void
25ff6af1 792qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 793{
25ff6af1 794 srb_t *sp = ptr;
d7459527
MH		 795 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
796
797 cmd->result = res;
798
799 if (atomic_read(&sp->ref_count) == 0) {
800 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
801 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
802 sp, GET_CMD_SP(sp));
803 if (ql2xextended_error_logging & ql_dbg_io)
804 WARN_ON(atomic_read(&sp->ref_count) == 0);
805 return;
806 }
807 if (!atomic_dec_and_test(&sp->ref_count))
808 return;
809
25ff6af1 810 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 811 cmd->scsi_done(cmd);
812}
813
8ae6d9c7
GM		 814/* If we are SP1 here, we need to still take and release the host_lock as SP1
815 * does not have the changes necessary to avoid taking host->host_lock.
816 */
1da177e4 817static int
f5e3e40b 818qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 819{
134ae078 820 scsi_qla_host_t *vha = shost_priv(host);
fca29703 821 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 822 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 823 struct qla_hw_data *ha = vha->hw;
824 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 825 srb_t *sp;
826 int rval;
5601236b
MH		 827 struct qla_qpair *qpair = NULL;
828 uint32_t tag;
829 uint16_t hwq;
fca29703 830
04dfaa53
MFO		 831 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
832 cmd->result = DID_NO_CONNECT << 16;
833 goto qc24_fail_command;
834 }
835
5601236b
MH		 836 if (ha->mqenable) {
837 if (shost_use_blk_mq(vha->host)) {
838 tag = blk_mq_unique_tag(cmd->request);
839 hwq = blk_mq_unique_tag_to_hwq(tag);
840 qpair = ha->queue_pair_map[hwq];
841 } else if (vha->vp_idx && vha->qpair) {
842 qpair = vha->qpair;
843 }
844
845 if (qpair)
846 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 847 }
848
85880801 849 if (ha->flags.eeh_busy) {
7c3df132 850 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 851 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 852 "PCI Channel IO permanent failure, exiting "
853 "cmd=%p.\n", cmd);
b9b12f73 854 cmd->result = DID_NO_CONNECT << 16;
7c3df132 855 } else {
5f28d2d7 856 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 857 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 858 cmd->result = DID_REQUEUE << 16;
7c3df132 859 }
14e660e6
SJ		 860 goto qc24_fail_command;
861 }
862
19a7b4ae
JSEC		 863 rval = fc_remote_port_chkready(rport);
864 if (rval) {
865 cmd->result = rval;
5f28d2d7 866 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 867 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
868 cmd, rval);
fca29703
AV		 869 goto qc24_fail_command;
870 }
871
bad75002
AE		 872 if (!vha->flags.difdix_supported &&
873 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 874 ql_dbg(ql_dbg_io, vha, 0x3004,
875 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
876 cmd);
bad75002
AE		 877 cmd->result = DID_NO_CONNECT << 16;
878 goto qc24_fail_command;
879 }
aa651be8
CD		 880
881 if (!fcport) {
882 cmd->result = DID_NO_CONNECT << 16;
883 goto qc24_fail_command;
884 }
885
fca29703
AV		 886 if (atomic_read(&fcport->state) != FCS_ONLINE) {
887 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 888 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 889 ql_dbg(ql_dbg_io, vha, 0x3005,
890 "Returning DNC, fcport_state=%d loop_state=%d.\n",
891 atomic_read(&fcport->state),
892 atomic_read(&base_vha->loop_state));
fca29703
AV		 893 cmd->result = DID_NO_CONNECT << 16;
894 goto qc24_fail_command;
895 }
7b594131 896 goto qc24_target_busy;
fca29703
AV		 897 }
898
e05fe292
CD		 899 /*
900 * Return target busy if we've received a non-zero retry_delay_timer
901 * in a FCP_RSP.
902 */
975f7d46
BP		 903 if (fcport->retry_delay_timestamp == 0) {
904 /* retry delay not set */
905 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 906 fcport->retry_delay_timestamp = 0;
907 else
908 goto qc24_target_busy;
909
b00ee7d7 910 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 911 if (!sp)
f5e3e40b 912 goto qc24_host_busy;
fca29703 913
9ba56b95
GM		 914 sp->u.scmd.cmd = cmd;
915 sp->type = SRB_SCSI_CMD;
916 atomic_set(&sp->ref_count, 1);
917 CMD_SP(cmd) = (void *)sp;
918 sp->free = qla2x00_sp_free_dma;
919 sp->done = qla2x00_sp_compl;
920
e315cd28 921 rval = ha->isp_ops->start_scsi(sp);
7c3df132 922 if (rval != QLA_SUCCESS) {
53016ed3 923 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 924 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 925 goto qc24_host_busy_free_sp;
7c3df132 926 }
fca29703 927
fca29703
AV		 928 return 0;
929
930qc24_host_busy_free_sp:
25ff6af1 931 qla2x00_sp_free_dma(sp);
fca29703 932
f5e3e40b 933qc24_host_busy:
fca29703
AV		 934 return SCSI_MLQUEUE_HOST_BUSY;
935
7b594131
MC		 936qc24_target_busy:
937 return SCSI_MLQUEUE_TARGET_BUSY;
938
fca29703 939qc24_fail_command:
f5e3e40b 940 cmd->scsi_done(cmd);
fca29703
AV		 941
942 return 0;
943}
944
d7459527
MH		 945/* For MQ supported I/O */
946int
947qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
948 struct qla_qpair *qpair)
949{
950 scsi_qla_host_t *vha = shost_priv(host);
951 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
952 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
953 struct qla_hw_data *ha = vha->hw;
954 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
955 srb_t *sp;
956 int rval;
957
958 rval = fc_remote_port_chkready(rport);
959 if (rval) {
960 cmd->result = rval;
961 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
962 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
963 cmd, rval);
964 goto qc24_fail_command;
965 }
966
967 if (!fcport) {
968 cmd->result = DID_NO_CONNECT << 16;
969 goto qc24_fail_command;
970 }
971
972 if (atomic_read(&fcport->state) != FCS_ONLINE) {
973 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
974 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
975 ql_dbg(ql_dbg_io, vha, 0x3077,
976 "Returning DNC, fcport_state=%d loop_state=%d.\n",
977 atomic_read(&fcport->state),
978 atomic_read(&base_vha->loop_state));
979 cmd->result = DID_NO_CONNECT << 16;
980 goto qc24_fail_command;
981 }
982 goto qc24_target_busy;
983 }
984
985 /*
986 * Return target busy if we've received a non-zero retry_delay_timer
987 * in a FCP_RSP.
988 */
989 if (fcport->retry_delay_timestamp == 0) {
990 /* retry delay not set */
991 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
992 fcport->retry_delay_timestamp = 0;
993 else
994 goto qc24_target_busy;
995
996 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
997 if (!sp)
998 goto qc24_host_busy;
999
1000 sp->u.scmd.cmd = cmd;
1001 sp->type = SRB_SCSI_CMD;
1002 atomic_set(&sp->ref_count, 1);
1003 CMD_SP(cmd) = (void *)sp;
1004 sp->free = qla2xxx_qpair_sp_free_dma;
1005 sp->done = qla2xxx_qpair_sp_compl;
1006 sp->qpair = qpair;
1007
1008 rval = ha->isp_ops->start_scsi_mq(sp);
1009 if (rval != QLA_SUCCESS) {
1010 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1011 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1012 if (rval == QLA_INTERFACE_ERROR)
1013 goto qc24_fail_command;
1014 goto qc24_host_busy_free_sp;
1015 }
1016
1017 return 0;
1018
1019qc24_host_busy_free_sp:
25ff6af1 1020 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 1021
1022qc24_host_busy:
1023 return SCSI_MLQUEUE_HOST_BUSY;
1024
1025qc24_target_busy:
1026 return SCSI_MLQUEUE_TARGET_BUSY;
1027
1028qc24_fail_command:
1029 cmd->scsi_done(cmd);
1030
1031 return 0;
1032}
1033
1da177e4
LT		 1034/*
1035 * qla2x00_eh_wait_on_command
1036 * Waits for the command to be returned by the Firmware for some
1037 * max time.
1038 *
1039 * Input:
1da177e4 1040 * cmd = Scsi Command to wait on.
1da177e4
LT		 1041 *
1042 * Return:
1043 * Not Found : 0
1044 * Found : 1
1045 */
1046static int
e315cd28 1047qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1048{
fe74c71f 1049#define ABORT_POLLING_PERIOD 1000
478c3b03 1050#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1051 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1052 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1053 struct qla_hw_data *ha = vha->hw;
f4f051eb 1054 int ret = QLA_SUCCESS;
1da177e4 1055
85880801 1056 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1057 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1058 "Return:eh_wait.\n");
85880801
AV		 1059 return ret;
1060 }
1061
d970432c 1062 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1063 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1064 }
1065 if (CMD_SP(cmd))
1066 ret = QLA_FUNCTION_FAILED;
1da177e4 1067
f4f051eb 1068 return ret;
1da177e4
LT		 1069}
1070
1071/*
1072 * qla2x00_wait_for_hba_online
fa2a1ce5 1073 * Wait till the HBA is online after going through
1da177e4
LT		 1074 * <= MAX_RETRIES_OF_ISP_ABORT or
1075 * finally HBA is disabled ie marked offline
1076 *
1077 * Input:
1078 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1079 *
1080 * Note:
1da177e4
LT		 1081 * Does context switching-Release SPIN_LOCK
1082 * (if any) before calling this routine.
1083 *
1084 * Return:
1085 * Success (Adapter is online) : 0
1086 * Failed (Adapter is offline/disabled) : 1
1087 */
854165f4 1088int
e315cd28 1089qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1090{
fca29703
AV		 1091 int return_status;
1092 unsigned long wait_online;
e315cd28
AC		 1093 struct qla_hw_data *ha = vha->hw;
1094 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1095
fa2a1ce5 1096 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1097 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1098 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1099 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1100 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1101
1102 msleep(1000);
1103 }
e315cd28 1104 if (base_vha->flags.online)
fa2a1ce5 1105 return_status = QLA_SUCCESS;
1da177e4
LT		 1106 else
1107 return_status = QLA_FUNCTION_FAILED;
1108
1da177e4
LT		 1109 return (return_status);
1110}
1111
726b8548
QT		 1112static inline int test_fcport_count(scsi_qla_host_t *vha)
1113{
1114 struct qla_hw_data *ha = vha->hw;
1115 unsigned long flags;
1116 int res;
1117
1118 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1119 ql_dbg(ql_dbg_init, vha, 0x00ec,
1120 "tgt %p, fcport_count=%d\n",
1121 vha, vha->fcport_count);
726b8548
QT		 1122 res = (vha->fcport_count == 0);
1123 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1124
1125 return res;
1126}
1127
1128/*
1129 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1130 * it has dependency on UNLOADING flag to stop device discovery
1131 */
1132static void
1133qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1134{
1135 qla2x00_mark_all_devices_lost(vha, 0);
1136
1137 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1138}
1139
86fbee86 1140/*
638a1a01
SC		 1141 * qla2x00_wait_for_hba_ready
1142 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1143 *
1144 * Input:
1145 * ha - pointer to host adapter structure
1146 *
1147 * Note:
1148 * Does context switching-Release SPIN_LOCK
1149 * (if any) before calling this routine.
1150 *
86fbee86 1151 */
638a1a01
SC		 1152static void
1153qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1154{
86fbee86 1155 struct qla_hw_data *ha = vha->hw;
783e0dc4 1156 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1157
1d483901
DC		 1158 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1159 ha->flags.mbox_busy) ||
1160 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1161 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1162 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1163 break;
86fbee86 1164 msleep(1000);
783e0dc4 1165 }
86fbee86
LC		 1166}
1167
2533cf67
LC		 1168int
1169qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1170{
1171 int return_status;
1172 unsigned long wait_reset;
1173 struct qla_hw_data *ha = vha->hw;
1174 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1175
1176 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1177 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1178 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1179 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1180 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1181
1182 msleep(1000);
1183
1184 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1185 ha->flags.chip_reset_done)
1186 break;
1187 }
1188 if (ha->flags.chip_reset_done)
1189 return_status = QLA_SUCCESS;
1190 else
1191 return_status = QLA_FUNCTION_FAILED;
1192
1193 return return_status;
1194}
1195
083a469d
GM		 1196static void
1197sp_get(struct srb *sp)
1198{
1199 atomic_inc(&sp->ref_count);
1200}
1201
a465537a
SC		 1202#define ISP_REG_DISCONNECT 0xffffffffU
1203/**************************************************************************
1204* qla2x00_isp_reg_stat
1205*
1206* Description:
1207* Read the host status register of ISP before aborting the command.
1208*
1209* Input:
1210* ha = pointer to host adapter structure.
1211*
1212*
1213* Returns:
1214* Either true or false.
1215*
1216* Note: Return true if there is register disconnect.
1217**************************************************************************/
1218static inline
1219uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1220{
1221 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1222 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1223
bf6061b1
SC		 1224 if (IS_P3P_TYPE(ha))
1225 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1226 else
1227 return ((RD_REG_DWORD(&reg->host_status)) ==
1228 ISP_REG_DISCONNECT);
a465537a
SC		 1229}
1230
1da177e4
LT		 1231/**************************************************************************
1232* qla2xxx_eh_abort
1233*
1234* Description:
1235* The abort function will abort the specified command.
1236*
1237* Input:
1238* cmd = Linux SCSI command packet to be aborted.
1239*
1240* Returns:
1241* Either SUCCESS or FAILED.
1242*
1243* Note:
2ea00202 1244* Only return FAILED if command not returned by firmware.
1da177e4 1245**************************************************************************/
e5f82ab8 1246static int
1da177e4
LT		 1247qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1248{
e315cd28 1249 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1250 srb_t *sp;
4e98d3b8 1251 int ret;
9cb78c16
HR		 1252 unsigned int id;
1253 uint64_t lun;
18e144d3 1254 unsigned long flags;
f934c9d0 1255 int rval, wait = 0;
e315cd28 1256 struct qla_hw_data *ha = vha->hw;
1da177e4 1257
a465537a
SC		 1258 if (qla2x00_isp_reg_stat(ha)) {
1259 ql_log(ql_log_info, vha, 0x8042,
1260 "PCI/Register disconnect, exiting.\n");
1261 return FAILED;
1262 }
f4f051eb 1263 if (!CMD_SP(cmd))
2ea00202 1264 return SUCCESS;
1da177e4 1265
4e98d3b8
AV		 1266 ret = fc_block_scsi_eh(cmd);
1267 if (ret != 0)
1268 return ret;
1269 ret = SUCCESS;
1270
f4f051eb
AV		 1271 id = cmd->device->id;
1272 lun = cmd->device->lun;
1da177e4 1273
e315cd28 1274 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1275 sp = (srb_t *) CMD_SP(cmd);
1276 if (!sp) {
1277 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1278 return SUCCESS;
1279 }
1da177e4 1280
7c3df132 1281 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1282 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1283 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1284
170babc3
MC		 1285 /* Get a reference to the sp and drop the lock.*/
1286 sp_get(sp);
083a469d 1287
e315cd28 1288 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1289 rval = ha->isp_ops->abort_command(sp);
1290 if (rval) {
96219424 1291 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1292 ret = SUCCESS;
96219424 1293 else
f934c9d0
CD		 1294 ret = FAILED;
1295
7c3df132 1296 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1297 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1298 } else {
7c3df132 1299 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1300 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1301 wait = 1;
1302 }
75942064
SK		 1303
1304 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1305 sp->done(sp, 0);
75942064 1306 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1307
bc91ade9
CD		 1308 /* Did the command return during mailbox execution? */
1309 if (ret == FAILED && !CMD_SP(cmd))
1310 ret = SUCCESS;
1311
f4f051eb 1312 /* Wait for the command to be returned. */
2ea00202 1313 if (wait) {
e315cd28 1314 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1315 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1316 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1317 ret = FAILED;
f4f051eb 1318 }
1da177e4 1319 }
1da177e4 1320
7c3df132 1321 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1322 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1323 vha->host_no, id, lun, wait, ret);
1da177e4 1324
f4f051eb
AV		 1325 return ret;
1326}
1da177e4 1327
4d78c973 1328int
e315cd28 1329qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1330 uint64_t l, enum nexus_wait_type type)
f4f051eb 1331{
17d98630 1332 int cnt, match, status;
18e144d3 1333 unsigned long flags;
e315cd28 1334 struct qla_hw_data *ha = vha->hw;
73208dfd 1335 struct req_que *req;
4d78c973 1336 srb_t *sp;
9ba56b95 1337 struct scsi_cmnd *cmd;
1da177e4 1338
523ec773 1339 status = QLA_SUCCESS;
17d98630 1340
e315cd28 1341 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1342 req = vha->req;
17d98630 1343 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1344 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1345 sp = req->outstanding_cmds[cnt];
1346 if (!sp)
523ec773 1347 continue;
9ba56b95 1348 if (sp->type != SRB_SCSI_CMD)
cf53b069 1349 continue;
25ff6af1 1350 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1351 continue;
1352 match = 0;
9ba56b95 1353 cmd = GET_CMD_SP(sp);
17d98630
AC		 1354 switch (type) {
1355 case WAIT_HOST:
1356 match = 1;
1357 break;
1358 case WAIT_TARGET:
9ba56b95 1359 match = cmd->device->id == t;
17d98630
AC		 1360 break;
1361 case WAIT_LUN:
9ba56b95
GM		 1362 match = (cmd->device->id == t &&
1363 cmd->device->lun == l);
17d98630 1364 break;
73208dfd 1365 }
17d98630
AC		 1366 if (!match)
1367 continue;
1368
1369 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1370 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1371 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1372 }
e315cd28 1373 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1374
1375 return status;
1da177e4
LT		 1376}
1377
523ec773
AV		 1378static char *reset_errors[] = {
1379 "HBA not online",
1380 "HBA not ready",
1381 "Task management failed",
1382 "Waiting for command completions",
1383};
1da177e4 1384
e5f82ab8 1385static int
523ec773 1386__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1387 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1388{
e315cd28 1389 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1390 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1391 int err;
1da177e4 1392
7c3df132 1393 if (!fcport) {
523ec773 1394 return FAILED;
7c3df132 1395 }
1da177e4 1396
4e98d3b8
AV		 1397 err = fc_block_scsi_eh(cmd);
1398 if (err != 0)
1399 return err;
1400
7c3df132 1401 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1402 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1403 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1404
523ec773 1405 err = 0;
7c3df132
SK		 1406 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1407 ql_log(ql_log_warn, vha, 0x800a,
1408 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1409 goto eh_reset_failed;
7c3df132 1410 }
523ec773 1411 err = 2;
2afa19a9 1412 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1413 != QLA_SUCCESS) {
1414 ql_log(ql_log_warn, vha, 0x800c,
1415 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1416 goto eh_reset_failed;
7c3df132 1417 }
523ec773 1418 err = 3;
e315cd28 1419 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1420 cmd->device->lun, type) != QLA_SUCCESS) {
1421 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1422 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1423 goto eh_reset_failed;
7c3df132 1424 }
523ec773 1425
7c3df132 1426 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1427 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1428 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1429
1430 return SUCCESS;
1431
4d78c973 1432eh_reset_failed:
7c3df132 1433 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1434 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1435 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1436 cmd);
523ec773
AV		 1437 return FAILED;
1438}
1da177e4 1439
523ec773
AV		 1440static int
1441qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1442{
e315cd28
AC		 1443 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1444 struct qla_hw_data *ha = vha->hw;
1da177e4 1445
a465537a
SC		 1446 if (qla2x00_isp_reg_stat(ha)) {
1447 ql_log(ql_log_info, vha, 0x803e,
1448 "PCI/Register disconnect, exiting.\n");
1449 return FAILED;
1450 }
1451
523ec773
AV		 1452 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1453 ha->isp_ops->lun_reset);
1da177e4
LT		 1454}
1455
1da177e4 1456static int
523ec773 1457qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1458{
e315cd28
AC		 1459 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1460 struct qla_hw_data *ha = vha->hw;
1da177e4 1461
a465537a
SC		 1462 if (qla2x00_isp_reg_stat(ha)) {
1463 ql_log(ql_log_info, vha, 0x803f,
1464 "PCI/Register disconnect, exiting.\n");
1465 return FAILED;
1466 }
1467
523ec773
AV		 1468 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1469 ha->isp_ops->target_reset);
1da177e4
LT		 1470}
1471
1da177e4
LT		 1472/**************************************************************************
1473* qla2xxx_eh_bus_reset
1474*
1475* Description:
1476* The bus reset function will reset the bus and abort any executing
1477* commands.
1478*
1479* Input:
1480* cmd = Linux SCSI command packet of the command that cause the
1481* bus reset.
1482*
1483* Returns:
1484* SUCCESS/FAILURE (defined as macro in scsi.h).
1485*
1486**************************************************************************/
e5f82ab8 1487static int
1da177e4
LT		 1488qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1489{
e315cd28 1490 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1491 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1492 int ret = FAILED;
9cb78c16
HR		 1493 unsigned int id;
1494 uint64_t lun;
a465537a
SC		 1495 struct qla_hw_data *ha = vha->hw;
1496
1497 if (qla2x00_isp_reg_stat(ha)) {
1498 ql_log(ql_log_info, vha, 0x8040,
1499 "PCI/Register disconnect, exiting.\n");
1500 return FAILED;
1501 }
f4f051eb 1502
f4f051eb
AV		 1503 id = cmd->device->id;
1504 lun = cmd->device->lun;
1da177e4 1505
7c3df132 1506 if (!fcport) {
f4f051eb 1507 return ret;
7c3df132 1508 }
1da177e4 1509
4e98d3b8
AV		 1510 ret = fc_block_scsi_eh(cmd);
1511 if (ret != 0)
1512 return ret;
1513 ret = FAILED;
1514
7c3df132 1515 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1516 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1517
e315cd28 1518 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1519 ql_log(ql_log_fatal, vha, 0x8013,
1520 "Wait for hba online failed board disabled.\n");
f4f051eb 1521 goto eh_bus_reset_done;
1da177e4
LT		 1522 }
1523
ad537689
SK		 1524 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1525 ret = SUCCESS;
1526
f4f051eb
AV		 1527 if (ret == FAILED)
1528 goto eh_bus_reset_done;
1da177e4 1529
9a41a62b 1530 /* Flush outstanding commands. */
4d78c973 1531 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1532 QLA_SUCCESS) {
1533 ql_log(ql_log_warn, vha, 0x8014,
1534 "Wait for pending commands failed.\n");
9a41a62b 1535 ret = FAILED;
7c3df132 1536 }
1da177e4 1537
f4f051eb 1538eh_bus_reset_done:
7c3df132 1539 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1540 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1541 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1542
f4f051eb 1543 return ret;
1da177e4
LT		 1544}
1545
1546/**************************************************************************
1547* qla2xxx_eh_host_reset
1548*
1549* Description:
1550* The reset function will reset the Adapter.
1551*
1552* Input:
1553* cmd = Linux SCSI command packet of the command that cause the
1554* adapter reset.
1555*
1556* Returns:
1557* Either SUCCESS or FAILED.
1558*
1559* Note:
1560**************************************************************************/
e5f82ab8 1561static int
1da177e4
LT		 1562qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1563{
e315cd28 1564 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1565 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1566 int ret = FAILED;
9cb78c16
HR		 1567 unsigned int id;
1568 uint64_t lun;
e315cd28 1569 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1570
a465537a
SC		 1571 if (qla2x00_isp_reg_stat(ha)) {
1572 ql_log(ql_log_info, vha, 0x8041,
1573 "PCI/Register disconnect, exiting.\n");
1574 schedule_work(&ha->board_disable);
1575 return SUCCESS;
1576 }
1577
f4f051eb
AV		 1578 id = cmd->device->id;
1579 lun = cmd->device->lun;
f4f051eb 1580
7c3df132 1581 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1582 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1583
63ee7072
CD		 1584 /*
1585 * No point in issuing another reset if one is active. Also do not
1586 * attempt a reset if we are updating flash.
1587 */
1588 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1589 goto eh_host_reset_lock;
1da177e4 1590
e315cd28
AC		 1591 if (vha != base_vha) {
1592 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1593 goto eh_host_reset_lock;
e315cd28 1594 } else {
7ec0effd 1595 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1596 if (!qla82xx_fcoe_ctx_reset(vha)) {
1597 /* Ctx reset success */
1598 ret = SUCCESS;
1599 goto eh_host_reset_lock;
1600 }
1601 /* fall thru if ctx reset failed */
1602 }
68ca949c
AC		 1603 if (ha->wq)
1604 flush_workqueue(ha->wq);
1605
e315cd28 1606 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1607 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1608 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1609 /* failed. schedule dpc to try */
1610 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1611
7c3df132
SK		 1612 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1613 ql_log(ql_log_warn, vha, 0x802a,
1614 "wait for hba online failed.\n");
e315cd28 1615 goto eh_host_reset_lock;
7c3df132 1616 }
e315cd28
AC		 1617 }
1618 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1619 }
1da177e4 1620
e315cd28 1621 /* Waiting for command to be returned to OS.*/
4d78c973 1622 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1623 QLA_SUCCESS)
f4f051eb 1624 ret = SUCCESS;
1da177e4 1625
f4f051eb 1626eh_host_reset_lock:
cfb0919c 1627 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1628 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1629 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1630
f4f051eb
AV		 1631 return ret;
1632}
1da177e4
LT		 1633
1634/*
1635* qla2x00_loop_reset
1636* Issue loop reset.
1637*
1638* Input:
1639* ha = adapter block pointer.
1640*
1641* Returns:
1642* 0 = success
1643*/
a4722cf2 1644int
e315cd28 1645qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1646{
0c8c39af 1647 int ret;
bdf79621 1648 struct fc_port *fcport;
e315cd28 1649 struct qla_hw_data *ha = vha->hw;
1da177e4 1650
5854771e
AB		 1651 if (IS_QLAFX00(ha)) {
1652 return qlafx00_loop_reset(vha);
1653 }
1654
f4c496c1 1655 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1656 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1657 if (fcport->port_type != FCT_TARGET)
1658 continue;
1659
1660 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1661 if (ret != QLA_SUCCESS) {
7c3df132 1662 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1663 "Bus Reset failed: Reset=%d "
7c3df132 1664 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1665 }
1666 }
1667 }
1668
8ae6d9c7 1669
6246b8a1 1670 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1671 atomic_set(&vha->loop_state, LOOP_DOWN);
1672 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1673 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1674 ret = qla2x00_full_login_lip(vha);
0c8c39af 1675 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1676 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1677 "full_login_lip=%d.\n", ret);
749af3d5 1678 }
0c8c39af
AV		 1679 }
1680
0d6e61bc 1681 if (ha->flags.enable_lip_reset) {
e315cd28 1682 ret = qla2x00_lip_reset(vha);
ad537689 1683 if (ret != QLA_SUCCESS)
7c3df132
SK		 1684 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1685 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1686 }
1687
1da177e4 1688 /* Issue marker command only when we are going to start the I/O */
e315cd28 1689 vha->marker_needed = 1;
1da177e4 1690
0c8c39af 1691 return QLA_SUCCESS;
1da177e4
LT		 1692}
1693
df4bf0bb 1694void
e315cd28 1695qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1696{
4cd3b6eb 1697 int que, cnt, status;
df4bf0bb
AV		 1698 unsigned long flags;
1699 srb_t *sp;
e315cd28 1700 struct qla_hw_data *ha = vha->hw;
73208dfd 1701 struct req_que *req;
c5419e26
QT		 1702 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1703 struct qla_tgt_cmd *cmd;
1704 uint8_t trace = 0;
c0cb4496 1705
df4bf0bb 1706 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1707 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1708 req = ha->req_q_map[que];
73208dfd
AC		 1709 if (!req)
1710 continue;
8d93f550
CD		 1711 if (!req->outstanding_cmds)
1712 continue;
1713 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1714 sp = req->outstanding_cmds[cnt];
e612d465 1715 if (sp) {
c5419e26
QT		 1716 req->outstanding_cmds[cnt] = NULL;
1717 if (sp->cmd_type == TYPE_SRB) {
6fcd98fd 1718 if (sp->type == SRB_NVME_CMD ||
1719 sp->type == SRB_NVME_LS) {
e84067d7
DG		 1720 sp_get(sp);
1721 spin_unlock_irqrestore(
1722 &ha->hardware_lock, flags);
1723 qla_nvme_abort(ha, sp);
1724 spin_lock_irqsave(
1725 &ha->hardware_lock, flags);
1726 } else if (GET_CMD_SP(sp) &&
c5419e26
QT		 1727 !ha->flags.eeh_busy &&
1728 (sp->type == SRB_SCSI_CMD)) {
1729 /*
e84067d7
DG		 1730 * Don't abort commands in
1731 * adapter during EEH
1732 * recovery as it's not
1733 * accessible/responding.
1734 *
c5419e26
QT		 1735 * Get a reference to the sp
1736 * and drop the lock. The
1737 * reference ensures this
1738 * sp->done() call and not the
1739 * call in qla2xxx_eh_abort()
1740 * ends the SCSI command (with
1741 * result 'res').
1742 */
1743 sp_get(sp);
1744 spin_unlock_irqrestore(
1745 &ha->hardware_lock, flags);
1746 status = qla2xxx_eh_abort(
1747 GET_CMD_SP(sp));
1748 spin_lock_irqsave(
1749 &ha->hardware_lock, flags);
1750 /*
1751 * Get rid of extra reference
1752 * if immediate exit from
1753 * ql2xxx_eh_abort
1754 */
1755 if (status == FAILED &&
1756 (qla2x00_isp_reg_stat(ha)))
1757 atomic_dec(
1758 &sp->ref_count);
1759 }
1760 sp->done(sp, res);
1761 } else {
1762 if (!vha->hw->tgt.tgt_ops || !tgt ||
1763 qla_ini_mode_enabled(vha)) {
1764 if (!trace)
1765 ql_dbg(ql_dbg_tgt_mgt,
1766 vha, 0xf003,
1767 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1768 vha->dpc_flags);
1769 continue;
1770 }
1771 cmd = (struct qla_tgt_cmd *)sp;
1772 qlt_abort_cmd_on_host_reset(cmd->vha,
1773 cmd);
c733ab35 1774 }
73208dfd 1775 }
df4bf0bb
AV		 1776 }
1777 }
1778 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1779}
1780
f4f051eb
AV		 1781static int
1782qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1783{
bdf79621 1784 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1785
19a7b4ae 1786 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1787 return -ENXIO;
bdf79621 1788
19a7b4ae 1789 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1790
f4f051eb
AV		 1791 return 0;
1792}
1da177e4 1793
f4f051eb
AV		 1794static int
1795qla2xxx_slave_configure(struct scsi_device *sdev)
1796{
e315cd28 1797 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1798 struct req_que *req = vha->req;
8482e118 1799
9e522cd8
AE		 1800 if (IS_T10_PI_CAPABLE(vha->hw))
1801 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1802
db5ed4df 1803 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1804 return 0;
1805}
1da177e4 1806
f4f051eb
AV		 1807static void
1808qla2xxx_slave_destroy(struct scsi_device *sdev)
1809{
1810 sdev->hostdata = NULL;
1da177e4
LT		 1811}
1812
1813/**
1814 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1815 * @ha: HA context
1816 *
1817 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1818 * supported addressing method.
1819 */
1820static void
53303c42 1821qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1822{
7524f9b9 1823 /* Assume a 32bit DMA mask. */
1da177e4 1824 ha->flags.enable_64bit_addressing = 0;
1da177e4 1825
6a35528a 1826 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1827 /* Any upper-dword bits set? */
1828 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1829 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1830 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1831 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1832 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1833 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1834 return;
1da177e4 1835 }
1da177e4 1836 }
7524f9b9 1837
284901a9
YH		 1838 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1839 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1840}
1841
fd34f556 1842static void
e315cd28 1843qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1844{
1845 unsigned long flags = 0;
1846 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1847
1848 spin_lock_irqsave(&ha->hardware_lock, flags);
1849 ha->interrupts_on = 1;
1850 /* enable risc and host interrupts */
1851 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1852 RD_REG_WORD(&reg->ictrl);
1853 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1854
1855}
1856
1857static void
e315cd28 1858qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1859{
1860 unsigned long flags = 0;
1861 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1862
1863 spin_lock_irqsave(&ha->hardware_lock, flags);
1864 ha->interrupts_on = 0;
1865 /* disable risc and host interrupts */
1866 WRT_REG_WORD(&reg->ictrl, 0);
1867 RD_REG_WORD(&reg->ictrl);
1868 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1869}
1870
1871static void
e315cd28 1872qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1873{
1874 unsigned long flags = 0;
1875 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1876
1877 spin_lock_irqsave(&ha->hardware_lock, flags);
1878 ha->interrupts_on = 1;
1879 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1880 RD_REG_DWORD(&reg->ictrl);
1881 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1882}
1883
1884static void
e315cd28 1885qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1886{
1887 unsigned long flags = 0;
1888 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1889
124f85e6
AV		 1890 if (IS_NOPOLLING_TYPE(ha))
1891 return;
fd34f556
AV		 1892 spin_lock_irqsave(&ha->hardware_lock, flags);
1893 ha->interrupts_on = 0;
1894 WRT_REG_DWORD(&reg->ictrl, 0);
1895 RD_REG_DWORD(&reg->ictrl);
1896 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1897}
1898
706f457d
GM		 1899static int
1900qla2x00_iospace_config(struct qla_hw_data *ha)
1901{
1902 resource_size_t pio;
1903 uint16_t msix;
706f457d 1904
706f457d
GM		 1905 if (pci_request_selected_regions(ha->pdev, ha->bars,
1906 QLA2XXX_DRIVER_NAME)) {
1907 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1908 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1909 pci_name(ha->pdev));
1910 goto iospace_error_exit;
1911 }
1912 if (!(ha->bars & 1))
1913 goto skip_pio;
1914
1915 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1916 pio = pci_resource_start(ha->pdev, 0);
1917 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1918 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1919 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1920 "Invalid pci I/O region size (%s).\n",
1921 pci_name(ha->pdev));
1922 pio = 0;
1923 }
1924 } else {
1925 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1926 "Region #0 no a PIO resource (%s).\n",
1927 pci_name(ha->pdev));
1928 pio = 0;
1929 }
1930 ha->pio_address = pio;
1931 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1932 "PIO address=%llu.\n",
1933 (unsigned long long)ha->pio_address);
1934
1935skip_pio:
1936 /* Use MMIO operations for all accesses. */
1937 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1938 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1939 "Region #1 not an MMIO resource (%s), aborting.\n",
1940 pci_name(ha->pdev));
1941 goto iospace_error_exit;
1942 }
1943 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1944 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1945 "Invalid PCI mem region size (%s), aborting.\n",
1946 pci_name(ha->pdev));
1947 goto iospace_error_exit;
1948 }
1949
1950 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1951 if (!ha->iobase) {
1952 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1953 "Cannot remap MMIO (%s), aborting.\n",
1954 pci_name(ha->pdev));
1955 goto iospace_error_exit;
1956 }
1957
1958 /* Determine queue resources */
1959 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1960 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1961 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1962 goto mqiobase_exit;
1963
1964 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1965 pci_resource_len(ha->pdev, 3));
1966 if (ha->mqiobase) {
1967 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1968 "MQIO Base=%p.\n", ha->mqiobase);
1969 /* Read MSIX vector size of the board */
1970 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1971 ha->msix_count = msix + 1;
706f457d 1972 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1973 /* MB interrupt uses 1 vector */
1974 ha->max_req_queues = ha->msix_count - 1;
1975 ha->max_rsp_queues = ha->max_req_queues;
1976 /* Queue pairs is the max value minus the base queue pair */
1977 ha->max_qpairs = ha->max_rsp_queues - 1;
1978 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1979 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1980
706f457d 1981 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1982 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1983 } else
1984 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1985 "BAR 3 not enabled.\n");
1986
1987mqiobase_exit:
706f457d 1988 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1989 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1990 return (0);
1991
1992iospace_error_exit:
1993 return (-ENOMEM);
1994}
1995
1996
6246b8a1
GM		 1997static int
1998qla83xx_iospace_config(struct qla_hw_data *ha)
1999{
2000 uint16_t msix;
6246b8a1
GM		 2001
2002 if (pci_request_selected_regions(ha->pdev, ha->bars,
2003 QLA2XXX_DRIVER_NAME)) {
2004 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2005 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2006 pci_name(ha->pdev));
2007
2008 goto iospace_error_exit;
2009 }
2010
2011 /* Use MMIO operations for all accesses. */
2012 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2013 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2014 "Invalid pci I/O region size (%s).\n",
2015 pci_name(ha->pdev));
2016 goto iospace_error_exit;
2017 }
2018 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2019 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2020 "Invalid PCI mem region size (%s), aborting\n",
2021 pci_name(ha->pdev));
2022 goto iospace_error_exit;
2023 }
2024
2025 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2026 if (!ha->iobase) {
2027 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2028 "Cannot remap MMIO (%s), aborting.\n",
2029 pci_name(ha->pdev));
2030 goto iospace_error_exit;
2031 }
2032
2033 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2034 /* 83XX 26XX always use MQ type access for queues
2035 * - mbar 2, a.k.a region 4 */
2036 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2037 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2038 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2039 pci_resource_len(ha->pdev, 4));
2040
2041 if (!ha->mqiobase) {
2042 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2043 "BAR2/region4 not enabled\n");
2044 goto mqiobase_exit;
2045 }
2046
2047 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2048 pci_resource_len(ha->pdev, 2));
2049 if (ha->msixbase) {
2050 /* Read MSIX vector size of the board */
2051 pci_read_config_word(ha->pdev,
2052 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2053 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2054 /*
2055 * By default, driver uses at least two msix vectors
2056 * (default & rspq)
2057 */
d7459527
MH		 2058 if (ql2xmqsupport) {
2059 /* MB interrupt uses 1 vector */
2060 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2061
2062 /* ATIOQ needs 1 vector. That's 1 less QPair */
2063 if (QLA_TGT_MODE_ENABLED())
2064 ha->max_req_queues--;
2065
d0d2c68b
MH		 2066 ha->max_rsp_queues = ha->max_req_queues;
2067
d7459527
MH		 2068 /* Queue pairs is the max value minus
2069 * the base queue pair */
2070 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2071 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2072 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2073 }
2074 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2075 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2076 } else
2077 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2078 "BAR 1 not enabled.\n");
2079
2080mqiobase_exit:
6246b8a1 2081 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2082 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2083 return 0;
2084
2085iospace_error_exit:
2086 return -ENOMEM;
2087}
2088
fd34f556
AV		 2089static struct isp_operations qla2100_isp_ops = {
2090 .pci_config = qla2100_pci_config,
2091 .reset_chip = qla2x00_reset_chip,
2092 .chip_diag = qla2x00_chip_diag,
2093 .config_rings = qla2x00_config_rings,
2094 .reset_adapter = qla2x00_reset_adapter,
2095 .nvram_config = qla2x00_nvram_config,
2096 .update_fw_options = qla2x00_update_fw_options,
2097 .load_risc = qla2x00_load_risc,
2098 .pci_info_str = qla2x00_pci_info_str,
2099 .fw_version_str = qla2x00_fw_version_str,
2100 .intr_handler = qla2100_intr_handler,
2101 .enable_intrs = qla2x00_enable_intrs,
2102 .disable_intrs = qla2x00_disable_intrs,
2103 .abort_command = qla2x00_abort_command,
523ec773
AV		 2104 .target_reset = qla2x00_abort_target,
2105 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2106 .fabric_login = qla2x00_login_fabric,
2107 .fabric_logout = qla2x00_fabric_logout,
2108 .calc_req_entries = qla2x00_calc_iocbs_32,
2109 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2110 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2111 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2112 .read_nvram = qla2x00_read_nvram_data,
2113 .write_nvram = qla2x00_write_nvram_data,
2114 .fw_dump = qla2100_fw_dump,
2115 .beacon_on = NULL,
2116 .beacon_off = NULL,
2117 .beacon_blink = NULL,
2118 .read_optrom = qla2x00_read_optrom_data,
2119 .write_optrom = qla2x00_write_optrom_data,
2120 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2121 .start_scsi = qla2x00_start_scsi,
d7459527 2122 .start_scsi_mq = NULL,
a9083016 2123 .abort_isp = qla2x00_abort_isp,
706f457d 2124 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2125 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2126};
2127
2128static struct isp_operations qla2300_isp_ops = {
2129 .pci_config = qla2300_pci_config,
2130 .reset_chip = qla2x00_reset_chip,
2131 .chip_diag = qla2x00_chip_diag,
2132 .config_rings = qla2x00_config_rings,
2133 .reset_adapter = qla2x00_reset_adapter,
2134 .nvram_config = qla2x00_nvram_config,
2135 .update_fw_options = qla2x00_update_fw_options,
2136 .load_risc = qla2x00_load_risc,
2137 .pci_info_str = qla2x00_pci_info_str,
2138 .fw_version_str = qla2x00_fw_version_str,
2139 .intr_handler = qla2300_intr_handler,
2140 .enable_intrs = qla2x00_enable_intrs,
2141 .disable_intrs = qla2x00_disable_intrs,
2142 .abort_command = qla2x00_abort_command,
523ec773
AV		 2143 .target_reset = qla2x00_abort_target,
2144 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2145 .fabric_login = qla2x00_login_fabric,
2146 .fabric_logout = qla2x00_fabric_logout,
2147 .calc_req_entries = qla2x00_calc_iocbs_32,
2148 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2149 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2150 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2151 .read_nvram = qla2x00_read_nvram_data,
2152 .write_nvram = qla2x00_write_nvram_data,
2153 .fw_dump = qla2300_fw_dump,
2154 .beacon_on = qla2x00_beacon_on,
2155 .beacon_off = qla2x00_beacon_off,
2156 .beacon_blink = qla2x00_beacon_blink,
2157 .read_optrom = qla2x00_read_optrom_data,
2158 .write_optrom = qla2x00_write_optrom_data,
2159 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2160 .start_scsi = qla2x00_start_scsi,
d7459527 2161 .start_scsi_mq = NULL,
a9083016 2162 .abort_isp = qla2x00_abort_isp,
7ec0effd 2163 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2164 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2165};
2166
2167static struct isp_operations qla24xx_isp_ops = {
2168 .pci_config = qla24xx_pci_config,
2169 .reset_chip = qla24xx_reset_chip,
2170 .chip_diag = qla24xx_chip_diag,
2171 .config_rings = qla24xx_config_rings,
2172 .reset_adapter = qla24xx_reset_adapter,
2173 .nvram_config = qla24xx_nvram_config,
2174 .update_fw_options = qla24xx_update_fw_options,
2175 .load_risc = qla24xx_load_risc,
2176 .pci_info_str = qla24xx_pci_info_str,
2177 .fw_version_str = qla24xx_fw_version_str,
2178 .intr_handler = qla24xx_intr_handler,
2179 .enable_intrs = qla24xx_enable_intrs,
2180 .disable_intrs = qla24xx_disable_intrs,
2181 .abort_command = qla24xx_abort_command,
523ec773
AV		 2182 .target_reset = qla24xx_abort_target,
2183 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2184 .fabric_login = qla24xx_login_fabric,
2185 .fabric_logout = qla24xx_fabric_logout,
2186 .calc_req_entries = NULL,
2187 .build_iocbs = NULL,
2188 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2189 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2190 .read_nvram = qla24xx_read_nvram_data,
2191 .write_nvram = qla24xx_write_nvram_data,
2192 .fw_dump = qla24xx_fw_dump,
2193 .beacon_on = qla24xx_beacon_on,
2194 .beacon_off = qla24xx_beacon_off,
2195 .beacon_blink = qla24xx_beacon_blink,
2196 .read_optrom = qla24xx_read_optrom_data,
2197 .write_optrom = qla24xx_write_optrom_data,
2198 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2199 .start_scsi = qla24xx_start_scsi,
d7459527 2200 .start_scsi_mq = NULL,
a9083016 2201 .abort_isp = qla2x00_abort_isp,
7ec0effd 2202 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2203 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2204};
2205
c3a2f0df
AV		 2206static struct isp_operations qla25xx_isp_ops = {
2207 .pci_config = qla25xx_pci_config,
2208 .reset_chip = qla24xx_reset_chip,
2209 .chip_diag = qla24xx_chip_diag,
2210 .config_rings = qla24xx_config_rings,
2211 .reset_adapter = qla24xx_reset_adapter,
2212 .nvram_config = qla24xx_nvram_config,
2213 .update_fw_options = qla24xx_update_fw_options,
2214 .load_risc = qla24xx_load_risc,
2215 .pci_info_str = qla24xx_pci_info_str,
2216 .fw_version_str = qla24xx_fw_version_str,
2217 .intr_handler = qla24xx_intr_handler,
2218 .enable_intrs = qla24xx_enable_intrs,
2219 .disable_intrs = qla24xx_disable_intrs,
2220 .abort_command = qla24xx_abort_command,
523ec773
AV		 2221 .target_reset = qla24xx_abort_target,
2222 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2223 .fabric_login = qla24xx_login_fabric,
2224 .fabric_logout = qla24xx_fabric_logout,
2225 .calc_req_entries = NULL,
2226 .build_iocbs = NULL,
2227 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2228 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2229 .read_nvram = qla25xx_read_nvram_data,
2230 .write_nvram = qla25xx_write_nvram_data,
2231 .fw_dump = qla25xx_fw_dump,
2232 .beacon_on = qla24xx_beacon_on,
2233 .beacon_off = qla24xx_beacon_off,
2234 .beacon_blink = qla24xx_beacon_blink,
338c9161 2235 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2236 .write_optrom = qla24xx_write_optrom_data,
2237 .get_flash_version = qla24xx_get_flash_version,
bad75002 2238 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2239 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2240 .abort_isp = qla2x00_abort_isp,
7ec0effd 2241 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2242 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2243};
2244
3a03eb79
AV		 2245static struct isp_operations qla81xx_isp_ops = {
2246 .pci_config = qla25xx_pci_config,
2247 .reset_chip = qla24xx_reset_chip,
2248 .chip_diag = qla24xx_chip_diag,
2249 .config_rings = qla24xx_config_rings,
2250 .reset_adapter = qla24xx_reset_adapter,
2251 .nvram_config = qla81xx_nvram_config,
2252 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2253 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2254 .pci_info_str = qla24xx_pci_info_str,
2255 .fw_version_str = qla24xx_fw_version_str,
2256 .intr_handler = qla24xx_intr_handler,
2257 .enable_intrs = qla24xx_enable_intrs,
2258 .disable_intrs = qla24xx_disable_intrs,
2259 .abort_command = qla24xx_abort_command,
2260 .target_reset = qla24xx_abort_target,
2261 .lun_reset = qla24xx_lun_reset,
2262 .fabric_login = qla24xx_login_fabric,
2263 .fabric_logout = qla24xx_fabric_logout,
2264 .calc_req_entries = NULL,
2265 .build_iocbs = NULL,
2266 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2267 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2268 .read_nvram = NULL,
2269 .write_nvram = NULL,
3a03eb79
AV		 2270 .fw_dump = qla81xx_fw_dump,
2271 .beacon_on = qla24xx_beacon_on,
2272 .beacon_off = qla24xx_beacon_off,
6246b8a1 2273 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2274 .read_optrom = qla25xx_read_optrom_data,
2275 .write_optrom = qla24xx_write_optrom_data,
2276 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2277 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2278 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2279 .abort_isp = qla2x00_abort_isp,
7ec0effd 2280 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2281 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2282};
2283
2284static struct isp_operations qla82xx_isp_ops = {
2285 .pci_config = qla82xx_pci_config,
2286 .reset_chip = qla82xx_reset_chip,
2287 .chip_diag = qla24xx_chip_diag,
2288 .config_rings = qla82xx_config_rings,
2289 .reset_adapter = qla24xx_reset_adapter,
2290 .nvram_config = qla81xx_nvram_config,
2291 .update_fw_options = qla24xx_update_fw_options,
2292 .load_risc = qla82xx_load_risc,
9d55ca66 2293 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2294 .fw_version_str = qla24xx_fw_version_str,
2295 .intr_handler = qla82xx_intr_handler,
2296 .enable_intrs = qla82xx_enable_intrs,
2297 .disable_intrs = qla82xx_disable_intrs,
2298 .abort_command = qla24xx_abort_command,
2299 .target_reset = qla24xx_abort_target,
2300 .lun_reset = qla24xx_lun_reset,
2301 .fabric_login = qla24xx_login_fabric,
2302 .fabric_logout = qla24xx_fabric_logout,
2303 .calc_req_entries = NULL,
2304 .build_iocbs = NULL,
2305 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2306 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2307 .read_nvram = qla24xx_read_nvram_data,
2308 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2309 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2310 .beacon_on = qla82xx_beacon_on,
2311 .beacon_off = qla82xx_beacon_off,
2312 .beacon_blink = NULL,
a9083016
GM		 2313 .read_optrom = qla82xx_read_optrom_data,
2314 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2315 .get_flash_version = qla82xx_get_flash_version,
a9083016 2316 .start_scsi = qla82xx_start_scsi,
d7459527 2317 .start_scsi_mq = NULL,
a9083016 2318 .abort_isp = qla82xx_abort_isp,
706f457d 2319 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2320 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2321};
2322
7ec0effd
AD		 2323static struct isp_operations qla8044_isp_ops = {
2324 .pci_config = qla82xx_pci_config,
2325 .reset_chip = qla82xx_reset_chip,
2326 .chip_diag = qla24xx_chip_diag,
2327 .config_rings = qla82xx_config_rings,
2328 .reset_adapter = qla24xx_reset_adapter,
2329 .nvram_config = qla81xx_nvram_config,
2330 .update_fw_options = qla24xx_update_fw_options,
2331 .load_risc = qla82xx_load_risc,
2332 .pci_info_str = qla24xx_pci_info_str,
2333 .fw_version_str = qla24xx_fw_version_str,
2334 .intr_handler = qla8044_intr_handler,
2335 .enable_intrs = qla82xx_enable_intrs,
2336 .disable_intrs = qla82xx_disable_intrs,
2337 .abort_command = qla24xx_abort_command,
2338 .target_reset = qla24xx_abort_target,
2339 .lun_reset = qla24xx_lun_reset,
2340 .fabric_login = qla24xx_login_fabric,
2341 .fabric_logout = qla24xx_fabric_logout,
2342 .calc_req_entries = NULL,
2343 .build_iocbs = NULL,
2344 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2345 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2346 .read_nvram = NULL,
2347 .write_nvram = NULL,
a1b23c5a 2348 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2349 .beacon_on = qla82xx_beacon_on,
2350 .beacon_off = qla82xx_beacon_off,
2351 .beacon_blink = NULL,
888e639d 2352 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2353 .write_optrom = qla8044_write_optrom_data,
2354 .get_flash_version = qla82xx_get_flash_version,
2355 .start_scsi = qla82xx_start_scsi,
d7459527 2356 .start_scsi_mq = NULL,
7ec0effd
AD		 2357 .abort_isp = qla8044_abort_isp,
2358 .iospace_config = qla82xx_iospace_config,
2359 .initialize_adapter = qla2x00_initialize_adapter,
2360};
2361
6246b8a1
GM		 2362static struct isp_operations qla83xx_isp_ops = {
2363 .pci_config = qla25xx_pci_config,
2364 .reset_chip = qla24xx_reset_chip,
2365 .chip_diag = qla24xx_chip_diag,
2366 .config_rings = qla24xx_config_rings,
2367 .reset_adapter = qla24xx_reset_adapter,
2368 .nvram_config = qla81xx_nvram_config,
2369 .update_fw_options = qla81xx_update_fw_options,
2370 .load_risc = qla81xx_load_risc,
2371 .pci_info_str = qla24xx_pci_info_str,
2372 .fw_version_str = qla24xx_fw_version_str,
2373 .intr_handler = qla24xx_intr_handler,
2374 .enable_intrs = qla24xx_enable_intrs,
2375 .disable_intrs = qla24xx_disable_intrs,
2376 .abort_command = qla24xx_abort_command,
2377 .target_reset = qla24xx_abort_target,
2378 .lun_reset = qla24xx_lun_reset,
2379 .fabric_login = qla24xx_login_fabric,
2380 .fabric_logout = qla24xx_fabric_logout,
2381 .calc_req_entries = NULL,
2382 .build_iocbs = NULL,
2383 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2384 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2385 .read_nvram = NULL,
2386 .write_nvram = NULL,
2387 .fw_dump = qla83xx_fw_dump,
2388 .beacon_on = qla24xx_beacon_on,
2389 .beacon_off = qla24xx_beacon_off,
2390 .beacon_blink = qla83xx_beacon_blink,
2391 .read_optrom = qla25xx_read_optrom_data,
2392 .write_optrom = qla24xx_write_optrom_data,
2393 .get_flash_version = qla24xx_get_flash_version,
2394 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2395 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2396 .abort_isp = qla2x00_abort_isp,
2397 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2398 .initialize_adapter = qla2x00_initialize_adapter,
2399};
2400
2401static struct isp_operations qlafx00_isp_ops = {
2402 .pci_config = qlafx00_pci_config,
2403 .reset_chip = qlafx00_soft_reset,
2404 .chip_diag = qlafx00_chip_diag,
2405 .config_rings = qlafx00_config_rings,
2406 .reset_adapter = qlafx00_soft_reset,
2407 .nvram_config = NULL,
2408 .update_fw_options = NULL,
2409 .load_risc = NULL,
2410 .pci_info_str = qlafx00_pci_info_str,
2411 .fw_version_str = qlafx00_fw_version_str,
2412 .intr_handler = qlafx00_intr_handler,
2413 .enable_intrs = qlafx00_enable_intrs,
2414 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2415 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2416 .target_reset = qlafx00_abort_target,
2417 .lun_reset = qlafx00_lun_reset,
2418 .fabric_login = NULL,
2419 .fabric_logout = NULL,
2420 .calc_req_entries = NULL,
2421 .build_iocbs = NULL,
2422 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2423 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2424 .read_nvram = qla24xx_read_nvram_data,
2425 .write_nvram = qla24xx_write_nvram_data,
2426 .fw_dump = NULL,
2427 .beacon_on = qla24xx_beacon_on,
2428 .beacon_off = qla24xx_beacon_off,
2429 .beacon_blink = NULL,
2430 .read_optrom = qla24xx_read_optrom_data,
2431 .write_optrom = qla24xx_write_optrom_data,
2432 .get_flash_version = qla24xx_get_flash_version,
2433 .start_scsi = qlafx00_start_scsi,
d7459527 2434 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2435 .abort_isp = qlafx00_abort_isp,
2436 .iospace_config = qlafx00_iospace_config,
2437 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2438};
2439
f73cb695
CD		 2440static struct isp_operations qla27xx_isp_ops = {
2441 .pci_config = qla25xx_pci_config,
2442 .reset_chip = qla24xx_reset_chip,
2443 .chip_diag = qla24xx_chip_diag,
2444 .config_rings = qla24xx_config_rings,
2445 .reset_adapter = qla24xx_reset_adapter,
2446 .nvram_config = qla81xx_nvram_config,
2447 .update_fw_options = qla81xx_update_fw_options,
2448 .load_risc = qla81xx_load_risc,
2449 .pci_info_str = qla24xx_pci_info_str,
2450 .fw_version_str = qla24xx_fw_version_str,
2451 .intr_handler = qla24xx_intr_handler,
2452 .enable_intrs = qla24xx_enable_intrs,
2453 .disable_intrs = qla24xx_disable_intrs,
2454 .abort_command = qla24xx_abort_command,
2455 .target_reset = qla24xx_abort_target,
2456 .lun_reset = qla24xx_lun_reset,
2457 .fabric_login = qla24xx_login_fabric,
2458 .fabric_logout = qla24xx_fabric_logout,
2459 .calc_req_entries = NULL,
2460 .build_iocbs = NULL,
2461 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2462 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2463 .read_nvram = NULL,
2464 .write_nvram = NULL,
2465 .fw_dump = qla27xx_fwdump,
2466 .beacon_on = qla24xx_beacon_on,
2467 .beacon_off = qla24xx_beacon_off,
2468 .beacon_blink = qla83xx_beacon_blink,
2469 .read_optrom = qla25xx_read_optrom_data,
2470 .write_optrom = qla24xx_write_optrom_data,
2471 .get_flash_version = qla24xx_get_flash_version,
2472 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2473 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2474 .abort_isp = qla2x00_abort_isp,
2475 .iospace_config = qla83xx_iospace_config,
2476 .initialize_adapter = qla2x00_initialize_adapter,
2477};
2478
ea5b6382 2479static inline void
e315cd28 2480qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2481{
2482 ha->device_type = DT_EXTENDED_IDS;
2483 switch (ha->pdev->device) {
2484 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2485 ha->isp_type |= DT_ISP2100;
ea5b6382 2486 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2487 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2488 break;
2489 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2490 ha->isp_type |= DT_ISP2200;
ea5b6382 2491 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2492 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2493 break;
2494 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2495 ha->isp_type |= DT_ISP2300;
4a59f71d 2496 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2497 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2498 break;
2499 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2500 ha->isp_type |= DT_ISP2312;
4a59f71d 2501 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2502 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2503 break;
2504 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2505 ha->isp_type |= DT_ISP2322;
4a59f71d 2506 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2507 if (ha->pdev->subsystem_vendor == 0x1028 &&
2508 ha->pdev->subsystem_device == 0x0170)
2509 ha->device_type |= DT_OEM_001;
441d1072 2510 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2511 break;
2512 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2513 ha->isp_type |= DT_ISP6312;
441d1072 2514 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2515 break;
2516 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2517 ha->isp_type |= DT_ISP6322;
441d1072 2518 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2519 break;
2520 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2521 ha->isp_type |= DT_ISP2422;
4a59f71d 2522 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2523 ha->device_type |= DT_FWI2;
c76f2c01 2524 ha->device_type |= DT_IIDMA;
441d1072 2525 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2526 break;
2527 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2528 ha->isp_type |= DT_ISP2432;
4a59f71d 2529 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2530 ha->device_type |= DT_FWI2;
c76f2c01 2531 ha->device_type |= DT_IIDMA;
441d1072 2532 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2533 break;
4d4df193 2534 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2535 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2536 ha->device_type |= DT_ZIO_SUPPORTED;
2537 ha->device_type |= DT_FWI2;
2538 ha->device_type |= DT_IIDMA;
2539 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2540 break;
044cc6c8 2541 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2542 ha->isp_type |= DT_ISP5422;
e428924c 2543 ha->device_type |= DT_FWI2;
441d1072 2544 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2545 break;
044cc6c8 2546 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2547 ha->isp_type |= DT_ISP5432;
e428924c 2548 ha->device_type |= DT_FWI2;
441d1072 2549 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2550 break;
c3a2f0df 2551 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2552 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2553 ha->device_type |= DT_ZIO_SUPPORTED;
2554 ha->device_type |= DT_FWI2;
2555 ha->device_type |= DT_IIDMA;
441d1072 2556 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2557 break;
3a03eb79 2558 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2559 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2560 ha->device_type |= DT_ZIO_SUPPORTED;
2561 ha->device_type |= DT_FWI2;
2562 ha->device_type |= DT_IIDMA;
2563 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2564 break;
a9083016 2565 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2566 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2567 ha->device_type |= DT_ZIO_SUPPORTED;
2568 ha->device_type |= DT_FWI2;
2569 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2570 /* Initialize 82XX ISP flags */
2571 qla82xx_init_flags(ha);
2572 break;
7ec0effd 2573 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2574 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2575 ha->device_type |= DT_ZIO_SUPPORTED;
2576 ha->device_type |= DT_FWI2;
2577 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2578 /* Initialize 82XX ISP flags */
2579 qla82xx_init_flags(ha);
2580 break;
6246b8a1 2581 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2582 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2583 ha->device_type |= DT_ZIO_SUPPORTED;
2584 ha->device_type |= DT_FWI2;
2585 ha->device_type |= DT_IIDMA;
2586 ha->device_type |= DT_T10_PI;
2587 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2588 break;
2589 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2590 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2591 ha->device_type |= DT_ZIO_SUPPORTED;
2592 ha->device_type |= DT_FWI2;
2593 ha->device_type |= DT_IIDMA;
2594 ha->device_type |= DT_T10_PI;
2595 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2596 break;
8ae6d9c7 2597 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2598 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2599 break;
f73cb695 2600 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2601 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2602 ha->device_type |= DT_ZIO_SUPPORTED;
2603 ha->device_type |= DT_FWI2;
2604 ha->device_type |= DT_IIDMA;
8ce3f570 2605 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2606 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2607 break;
2c5bbbb2 2608 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2609 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2610 ha->device_type |= DT_ZIO_SUPPORTED;
2611 ha->device_type |= DT_FWI2;
2612 ha->device_type |= DT_IIDMA;
8ce3f570 2613 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2614 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2615 break;
2b48992f 2616 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2617 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2618 ha->device_type |= DT_ZIO_SUPPORTED;
2619 ha->device_type |= DT_FWI2;
2620 ha->device_type |= DT_IIDMA;
8ce3f570 2621 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2622 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2623 break;
ea5b6382 2624 }
e5b68a61 2625
a9083016 2626 if (IS_QLA82XX(ha))
43a9c38b 2627 ha->port_no = ha->portnum & 1;
f73cb695 2628 else {
a9083016
GM		 2629 /* Get adapter physical port no from interrupt pin register. */
2630 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2631 if (IS_QLA27XX(ha))
2632 ha->port_no--;
2633 else
2634 ha->port_no = !(ha->port_no & 1);
2635 }
a9083016 2636
7c3df132 2637 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2638 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2639 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2640}
2641
1e99e33a
AV		 2642static void
2643qla2xxx_scan_start(struct Scsi_Host *shost)
2644{
e315cd28 2645 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2646
cbc8eb67
AV		 2647 if (vha->hw->flags.running_gold_fw)
2648 return;
2649
e315cd28
AC		 2650 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2651 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2652 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2653 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2654}
2655
2656static int
2657qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2658{
e315cd28 2659 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2660
a5dd506e
BK		 2661 if (test_bit(UNLOADING, &vha->dpc_flags))
2662 return 1;
e315cd28 2663 if (!vha->host)
1e99e33a 2664 return 1;
e315cd28 2665 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2666 return 1;
2667
e315cd28 2668 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2669}
2670
ec7193e2
QT		 2671static void qla2x00_iocb_work_fn(struct work_struct *work)
2672{
2673 struct scsi_qla_host *vha = container_of(work,
2674 struct scsi_qla_host, iocb_work);
2675 int cnt = 0;
2676
2677 while (!list_empty(&vha->work_list)) {
2678 qla2x00_do_work(vha);
2679 cnt++;
2680 if (cnt > 10)
2681 break;
2682 }
2683}
2684
1da177e4
LT		 2685/*
2686 * PCI driver interface
2687 */
6f039790 2688static int
7ee61397 2689qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2690{
a1541d5a 2691 int ret = -ENODEV;
1da177e4 2692 struct Scsi_Host *host;
e315cd28
AC		 2693 scsi_qla_host_t *base_vha = NULL;
2694 struct qla_hw_data *ha;
29856e28 2695 char pci_info[30];
7d613ac6 2696 char fw_str[30], wq_name[30];
5433383e 2697 struct scsi_host_template *sht;
642ef983 2698 int bars, mem_only = 0;
e315cd28 2699 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2700 struct req_que *req = NULL;
2701 struct rsp_que *rsp = NULL;
5601236b 2702 int i;
d7459527 2703
285d0321 2704 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2705 sht = &qla2xxx_driver_template;
5433383e 2706 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2707 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2708 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2709 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2710 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2711 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2712 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2713 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2714 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2715 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2716 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2717 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2718 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2719 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2720 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2721 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2722 mem_only = 1;
7c3df132
SK		 2723 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2724 "Mem only adapter.\n");
285d0321 2725 }
7c3df132
SK		 2726 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2727 "Bars=%d.\n", bars);
285d0321 2728
09483916
BH		 2729 if (mem_only) {
2730 if (pci_enable_device_mem(pdev))
ddff7ed4 2731 return ret;
09483916
BH		 2732 } else {
2733 if (pci_enable_device(pdev))
ddff7ed4 2734 return ret;
09483916 2735 }
285d0321 2736
0927678f
JB		 2737 /* This may fail but that's ok */
2738 pci_enable_pcie_error_reporting(pdev);
285d0321 2739
e315cd28
AC		 2740 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2741 if (!ha) {
7c3df132
SK		 2742 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2743 "Unable to allocate memory for ha.\n");
ddff7ed4 2744 goto disable_device;
1da177e4 2745 }
7c3df132
SK		 2746 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2747 "Memory allocated for ha=%p.\n", ha);
e315cd28 2748 ha->pdev = pdev;
33e79977
QT		 2749 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2750 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2751 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2752 spin_lock_init(&ha->tgt.atio_lock);
2753
deeae7a6 2754 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2755
2756 /* Clear our data area */
285d0321 2757 ha->bars = bars;
09483916 2758 ha->mem_only = mem_only;
df4bf0bb 2759 spin_lock_init(&ha->hardware_lock);
339aa70e 2760 spin_lock_init(&ha->vport_slock);
a9b6f722 2761 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2762 mutex_init(&ha->optrom_mutex);
1da177e4 2763
ea5b6382
AV		 2764 /* Set ISP-type information. */
2765 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2766
2767 /* Set EEH reset type to fundamental if required by hba */
95676112 2768 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2769 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2770 pdev->needs_freset = 1;
ca79cf66 2771
cba1e47f
CD		 2772 ha->prev_topology = 0;
2773 ha->init_cb_size = sizeof(init_cb_t);
2774 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2775 ha->optrom_size = OPTROM_SIZE_2300;
2776
abbd8870 2777 /* Assign ISP specific operations. */
1da177e4 2778 if (IS_QLA2100(ha)) {
642ef983 2779 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2780 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2781 req_length = REQUEST_ENTRY_CNT_2100;
2782 rsp_length = RESPONSE_ENTRY_CNT_2100;
2783 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2784 ha->gid_list_info_size = 4;
3a03eb79
AV		 2785 ha->flash_conf_off = ~0;
2786 ha->flash_data_off = ~0;
2787 ha->nvram_conf_off = ~0;
2788 ha->nvram_data_off = ~0;
fd34f556 2789 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2790 } else if (IS_QLA2200(ha)) {
642ef983 2791 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2792 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2793 req_length = REQUEST_ENTRY_CNT_2200;
2794 rsp_length = RESPONSE_ENTRY_CNT_2100;
2795 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2796 ha->gid_list_info_size = 4;
3a03eb79
AV		 2797 ha->flash_conf_off = ~0;
2798 ha->flash_data_off = ~0;
2799 ha->nvram_conf_off = ~0;
2800 ha->nvram_data_off = ~0;
fd34f556 2801 ha->isp_ops = &qla2100_isp_ops;
fca29703 2802 } else if (IS_QLA23XX(ha)) {
642ef983 2803 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2804 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2805 req_length = REQUEST_ENTRY_CNT_2200;
2806 rsp_length = RESPONSE_ENTRY_CNT_2300;
2807 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2808 ha->gid_list_info_size = 6;
854165f4
AV		 2809 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2810 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2811 ha->flash_conf_off = ~0;
2812 ha->flash_data_off = ~0;
2813 ha->nvram_conf_off = ~0;
2814 ha->nvram_data_off = ~0;
fd34f556 2815 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2816 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2817 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2818 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2819 req_length = REQUEST_ENTRY_CNT_24XX;
2820 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2821 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2822 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2823 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2824 ha->gid_list_info_size = 8;
854165f4 2825 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2826 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2827 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2828 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2829 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2830 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2831 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2832 } else if (IS_QLA25XX(ha)) {
642ef983 2833 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2834 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2835 req_length = REQUEST_ENTRY_CNT_24XX;
2836 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2837 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2838 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2839 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2840 ha->gid_list_info_size = 8;
2841 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2842 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2843 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2844 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2845 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2846 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2847 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2848 } else if (IS_QLA81XX(ha)) {
642ef983 2849 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2850 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2851 req_length = REQUEST_ENTRY_CNT_24XX;
2852 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2853 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2854 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2855 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2856 ha->gid_list_info_size = 8;
2857 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2858 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2859 ha->isp_ops = &qla81xx_isp_ops;
2860 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2861 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2862 ha->nvram_conf_off = ~0;
2863 ha->nvram_data_off = ~0;
a9083016 2864 } else if (IS_QLA82XX(ha)) {
642ef983 2865 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2866 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2867 req_length = REQUEST_ENTRY_CNT_82XX;
2868 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2869 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2870 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2871 ha->gid_list_info_size = 8;
2872 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2873 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2874 ha->isp_ops = &qla82xx_isp_ops;
2875 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2876 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2877 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2878 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2879 } else if (IS_QLA8044(ha)) {
2880 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2881 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2882 req_length = REQUEST_ENTRY_CNT_82XX;
2883 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2884 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2885 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2886 ha->gid_list_info_size = 8;
2887 ha->optrom_size = OPTROM_SIZE_83XX;
2888 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2889 ha->isp_ops = &qla8044_isp_ops;
2890 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2891 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2892 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2893 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2894 } else if (IS_QLA83XX(ha)) {
7d613ac6 2895 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2896 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2897 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2898 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2899 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2900 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2901 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2902 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2903 ha->gid_list_info_size = 8;
2904 ha->optrom_size = OPTROM_SIZE_83XX;
2905 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2906 ha->isp_ops = &qla83xx_isp_ops;
2907 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2908 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2909 ha->nvram_conf_off = ~0;
2910 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2911 } else if (IS_QLAFX00(ha)) {
2912 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2913 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2914 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2915 req_length = REQUEST_ENTRY_CNT_FX00;
2916 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2917 ha->isp_ops = &qlafx00_isp_ops;
2918 ha->port_down_retry_count = 30; /* default value */
2919 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2920 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2921 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2922 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2923 ha->mr.host_info_resend = false;
2924 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2925 } else if (IS_QLA27XX(ha)) {
2926 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2927 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2928 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2929 req_length = REQUEST_ENTRY_CNT_83XX;
2930 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2931 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2932 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2933 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2934 ha->gid_list_info_size = 8;
2935 ha->optrom_size = OPTROM_SIZE_83XX;
2936 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2937 ha->isp_ops = &qla27xx_isp_ops;
2938 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2939 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2940 ha->nvram_conf_off = ~0;
2941 ha->nvram_data_off = ~0;
1da177e4 2942 }
6246b8a1 2943
7c3df132
SK		 2944 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2945 "mbx_count=%d, req_length=%d, "
2946 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2947 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2948 "max_fibre_devices=%d.\n",
7c3df132
SK		 2949 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2950 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2951 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2952 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2953 "isp_ops=%p, flash_conf_off=%d, "
2954 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2955 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2956 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2957
2958 /* Configure PCI I/O space */
2959 ret = ha->isp_ops->iospace_config(ha);
2960 if (ret)
0a63ad12 2961 goto iospace_config_failed;
706f457d
GM		 2962
2963 ql_log_pci(ql_log_info, pdev, 0x001d,
2964 "Found an ISP%04X irq %d iobase 0x%p.\n",
2965 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2966 mutex_init(&ha->vport_lock);
d7459527 2967 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2968 init_completion(&ha->mbx_cmd_comp);
2969 complete(&ha->mbx_cmd_comp);
2970 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2971 init_completion(&ha->dcbx_comp);
f356bef1 2972 init_completion(&ha->lb_portup_comp);
1da177e4 2973
2c3dfe3f 2974 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2975
53303c42 2976 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2977 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2978 "64 Bit addressing is %s.\n",
2979 ha->flags.enable_64bit_addressing ? "enable" :
2980 "disable");
73208dfd 2981 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2982 if (ret) {
7c3df132
SK		 2983 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2984 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2985
e315cd28
AC		 2986 goto probe_hw_failed;
2987 }
2988
73208dfd 2989 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2990 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2991 req->max_q_depth = ql2xmaxqdepth;
2992
e315cd28
AC		 2993
2994 base_vha = qla2x00_create_host(sht, ha);
2995 if (!base_vha) {
a1541d5a 2996 ret = -ENOMEM;
6e9f21f3 2997 qla2x00_mem_free(ha);
2afa19a9
AC		 2998 qla2x00_free_req_que(ha, req);
2999 qla2x00_free_rsp_que(ha, rsp);
e315cd28 3000 goto probe_hw_failed;
1da177e4
LT		 3001 }
3002
e315cd28 3003 pci_set_drvdata(pdev, base_vha);
6b383979 3004 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3005
e315cd28 3006 host = base_vha->host;
2afa19a9 3007 base_vha->req = req;
73208dfd 3008 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 3009 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 3010 else
e315cd28
AC		 3011 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3012 base_vha->vp_idx;
58548cb5 3013
8ae6d9c7
GM		 3014 /* Setup fcport template structure. */
3015 ha->mr.fcport.vha = base_vha;
3016 ha->mr.fcport.port_type = FCT_UNKNOWN;
3017 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3018 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3019 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3020 ha->mr.fcport.scan_state = 1;
3021
58548cb5
GM		 3022 /* Set the SG table size based on ISP type */
3023 if (!IS_FWI2_CAPABLE(ha)) {
3024 if (IS_QLA2100(ha))
3025 host->sg_tablesize = 32;
3026 } else {
3027 if (!IS_QLA82XX(ha))
3028 host->sg_tablesize = QLA_SG_ALL;
3029 }
642ef983 3030 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3031 host->cmd_per_lun = 3;
3032 host->unique_id = host->host_no;
e02587d7 3033 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3034 host->max_cmd_len = 32;
3035 else
3036 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3037 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3038 /* Older HBAs support only 16-bit LUNs */
3039 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3040 ql2xmaxlun > 0xffff)
3041 host->max_lun = 0xffff;
3042 else
3043 host->max_lun = ql2xmaxlun;
e315cd28 3044 host->transportt = qla2xxx_transport_template;
9a069e19 3045 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3046
7c3df132
SK		 3047 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3048 "max_id=%d this_id=%d "
3049 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3050 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3051 host->this_id, host->cmd_per_lun, host->unique_id,
3052 host->max_cmd_len, host->max_channel, host->max_lun,
3053 host->transportt, sht->vendor_id);
3054
d7459527
MH		 3055 /* Set up the irqs */
3056 ret = qla2x00_request_irqs(ha, rsp);
3057 if (ret)
3058 goto probe_init_failed;
3059
9a347ff4
CD		 3060 /* Alloc arrays of request and response ring ptrs */
3061 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3062 ql_log(ql_log_fatal, base_vha, 0x003d,
3063 "Failed to allocate memory for queue pointers..."
3064 "aborting.\n");
3065 goto probe_init_failed;
3066 }
3067
5601236b
MH		 3068 if (ha->mqenable && shost_use_blk_mq(host)) {
3069 /* number of hardware queues supported by blk/scsi-mq*/
3070 host->nr_hw_queues = ha->max_qpairs;
3071
3072 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3073 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3074 } else
3075 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3076 "blk/scsi-mq disabled.\n");
3077
2d70c103 3078 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3079
90a86fc0
JC		 3080 pci_save_state(pdev);
3081
9a347ff4 3082 /* Assign back pointers */
2afa19a9
AC		 3083 rsp->req = req;
3084 req->rsp = rsp;
9a347ff4 3085
8ae6d9c7
GM		 3086 if (IS_QLAFX00(ha)) {
3087 ha->rsp_q_map[0] = rsp;
3088 ha->req_q_map[0] = req;
3089 set_bit(0, ha->req_qid_map);
3090 set_bit(0, ha->rsp_qid_map);
3091 }
3092
08029990
AV		 3093 /* FWI2-capable only. */
3094 req->req_q_in = &ha->iobase->isp24.req_q_in;
3095 req->req_q_out = &ha->iobase->isp24.req_q_out;
3096 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3097 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3098 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3099 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3100 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3101 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3102 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3103 }
3104
8ae6d9c7
GM		 3105 if (IS_QLAFX00(ha)) {
3106 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3107 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3108 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3109 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3110 }
3111
7ec0effd 3112 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3113 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3114 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3115 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3116 }
3117
7c3df132
SK		 3118 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3119 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3120 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3121 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3122 "req->req_q_in=%p req->req_q_out=%p "
3123 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3124 req->req_q_in, req->req_q_out,
3125 rsp->rsp_q_in, rsp->rsp_q_out);
3126 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3127 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3128 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3129 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3130 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3131 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3132
8ae6d9c7 3133 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3134 ql_log(ql_log_fatal, base_vha, 0x00d6,
3135 "Failed to initialize adapter - Adapter flags %x.\n",
3136 base_vha->device_flags);
1da177e4 3137
a9083016
GM		 3138 if (IS_QLA82XX(ha)) {
3139 qla82xx_idc_lock(ha);
3140 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3141 QLA8XXX_DEV_FAILED);
a9083016 3142 qla82xx_idc_unlock(ha);
7c3df132
SK		 3143 ql_log(ql_log_fatal, base_vha, 0x00d7,
3144 "HW State: FAILED.\n");
7ec0effd
AD		 3145 } else if (IS_QLA8044(ha)) {
3146 qla8044_idc_lock(ha);
3147 qla8044_wr_direct(base_vha,
3148 QLA8044_CRB_DEV_STATE_INDEX,
3149 QLA8XXX_DEV_FAILED);
3150 qla8044_idc_unlock(ha);
3151 ql_log(ql_log_fatal, base_vha, 0x0150,
3152 "HW State: FAILED.\n");
a9083016
GM		 3153 }
3154
a1541d5a 3155 ret = -ENODEV;
1da177e4
LT		 3156 goto probe_failed;
3157 }
3158
3b1bef64
CD		 3159 if (IS_QLAFX00(ha))
3160 host->can_queue = QLAFX00_MAX_CANQUEUE;
3161 else
3162 host->can_queue = req->num_outstanding_cmds - 10;
3163
3164 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3165 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3166 host->can_queue, base_vha->req,
3167 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3168
e326d22a
QT		 3169 if (ha->mqenable) {
3170 bool mq = false;
3171 bool startit = false;
d7459527 3172 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
e326d22a
QT		 3173
3174 if (QLA_TGT_MODE_ENABLED()) {
3175 mq = true;
3176 startit = false;
3177 }
3178
3179 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3180 shost_use_blk_mq(host)) {
3181 mq = true;
3182 startit = true;
3183 }
3184
3185 if (mq) {
3186 /* Create start of day qpairs for Block MQ */
5601236b 3187 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3188 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3189 }
3190 }
68ca949c 3191
cbc8eb67
AV		 3192 if (ha->flags.running_gold_fw)
3193 goto skip_dpc;
3194
1da177e4
LT		 3195 /*
3196 * Startup the kernel thread for this host adapter
3197 */
39a11240 3198 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3199 "%s_dpc", base_vha->host_str);
39a11240 3200 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3201 ql_log(ql_log_fatal, base_vha, 0x00ed,
3202 "Failed to start DPC thread.\n");
39a11240 3203 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3204 goto probe_failed;
3205 }
7c3df132
SK		 3206 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3207 "DPC thread started successfully.\n");
1da177e4 3208
2d70c103
NB		 3209 /*
3210 * If we're not coming up in initiator mode, we might sit for
3211 * a while without waking up the dpc thread, which leads to a
3212 * stuck process warning. So just kick the dpc once here and
3213 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3214 */
3215 qla2xxx_wake_dpc(base_vha);
3216
ec7193e2 3217 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3218 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3219
81178772
SK		 3220 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3221 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3222 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3223 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3224
3225 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3226 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3227 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3228 INIT_WORK(&ha->idc_state_handler,
3229 qla83xx_idc_state_handler_work);
3230 INIT_WORK(&ha->nic_core_unrecoverable,
3231 qla83xx_nic_core_unrecoverable_work);
3232 }
3233
cbc8eb67 3234skip_dpc:
e315cd28
AC		 3235 list_add_tail(&base_vha->list, &ha->vp_list);
3236 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3237
3238 /* Initialized the timer */
e315cd28 3239 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3240 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3241 "Started qla2x00_timer with "
3242 "interval=%d.\n", WATCH_INTERVAL);
3243 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3244 "Detected hba at address=%p.\n",
3245 ha);
d19044c3 3246
e02587d7 3247 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3248 if (ha->fw_attributes & BIT_4) {
9e522cd8 3249 int prot = 0, guard;
bad75002 3250 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3251 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3252 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3253 if (ql2xenabledif == 1)
3254 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3255 scsi_host_set_prot(host,
8cb2049c 3256 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3257 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3258 | SHOST_DIF_TYPE3_PROTECTION
3259 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3260 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3261 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3262
3263 guard = SHOST_DIX_GUARD_CRC;
3264
3265 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3266 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3267 guard |= SHOST_DIX_GUARD_IP;
3268
3269 scsi_host_set_guard(host, guard);
bad75002
AE		 3270 } else
3271 base_vha->flags.difdix_supported = 0;
3272 }
3273
a9083016
GM		 3274 ha->isp_ops->enable_intrs(ha);
3275
1fe19ee4
AB		 3276 if (IS_QLAFX00(ha)) {
3277 ret = qlafx00_fx_disc(base_vha,
3278 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3279 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3280 QLA_SG_ALL : 128;
3281 }
3282
a1541d5a
AV		 3283 ret = scsi_add_host(host, &pdev->dev);
3284 if (ret)
3285 goto probe_failed;
3286
1486400f
MR		 3287 base_vha->flags.init_done = 1;
3288 base_vha->flags.online = 1;
edaa5c74 3289 ha->prev_minidump_failed = 0;
1486400f 3290
7c3df132
SK		 3291 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3292 "Init done and hba is online.\n");
3293
726b8548
QT		 3294 if (qla_ini_mode_enabled(base_vha) ||
3295 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3296 scsi_scan_host(host);
3297 else
3298 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3299 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3300
e315cd28 3301 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3302
8ae6d9c7 3303 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3304 ret = qlafx00_fx_disc(base_vha,
3305 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3306
3307 /* Register system information */
3308 ret = qlafx00_fx_disc(base_vha,
3309 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3310 }
3311
e315cd28 3312 qla2x00_init_host_attr(base_vha);
a1541d5a 3313
e315cd28 3314 qla2x00_dfs_setup(base_vha);
df613b96 3315
03eb912a
AB		 3316 ql_log(ql_log_info, base_vha, 0x00fb,
3317 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3318 ql_log(ql_log_info, base_vha, 0x00fc,
3319 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3320 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3321 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3322 base_vha->host_no,
df57caba 3323 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3324
2d70c103
NB		 3325 qlt_add_target(ha, base_vha);
3326
6b383979 3327 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3328
3329 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3330 return -ENODEV;
3331
1da177e4
LT		 3332 return 0;
3333
6e9f21f3 3334probe_init_failed:
2afa19a9 3335 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3336 ha->req_q_map[0] = NULL;
3337 clear_bit(0, ha->req_qid_map);
2afa19a9 3338 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3339 ha->rsp_q_map[0] = NULL;
3340 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3341 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3342
1da177e4 3343probe_failed:
b9978769
AV		 3344 if (base_vha->timer_active)
3345 qla2x00_stop_timer(base_vha);
3346 base_vha->flags.online = 0;
3347 if (ha->dpc_thread) {
3348 struct task_struct *t = ha->dpc_thread;
3349
3350 ha->dpc_thread = NULL;
3351 kthread_stop(t);
3352 }
3353
e315cd28 3354 qla2x00_free_device(base_vha);
1da177e4 3355
e315cd28 3356 scsi_host_put(base_vha->host);
1da177e4 3357
e315cd28 3358probe_hw_failed:
1a2fbf18
JL		 3359 qla2x00_clear_drv_active(ha);
3360
0a63ad12 3361iospace_config_failed:
7ec0effd 3362 if (IS_P3P_TYPE(ha)) {
0a63ad12 3363 if (!ha->nx_pcibase)
f73cb695 3364 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3365 if (!ql2xdbwr)
f73cb695 3366 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3367 } else {
3368 if (ha->iobase)
3369 iounmap(ha->iobase);
8ae6d9c7
GM		 3370 if (ha->cregbase)
3371 iounmap(ha->cregbase);
a9083016 3372 }
e315cd28
AC		 3373 pci_release_selected_regions(ha->pdev, ha->bars);
3374 kfree(ha);
1da177e4 3375
ddff7ed4 3376disable_device:
e315cd28 3377 pci_disable_device(pdev);
a1541d5a 3378 return ret;
1da177e4 3379}
1da177e4 3380
e30d1756
MI		 3381static void
3382qla2x00_shutdown(struct pci_dev *pdev)
3383{
3384 scsi_qla_host_t *vha;
3385 struct qla_hw_data *ha;
3386
552f3f9a
MI		 3387 if (!atomic_read(&pdev->enable_cnt))
3388 return;
3389
e30d1756
MI		 3390 vha = pci_get_drvdata(pdev);
3391 ha = vha->hw;
3392
42479343
AB		 3393 /* Notify ISPFX00 firmware */
3394 if (IS_QLAFX00(ha))
3395 qlafx00_driver_shutdown(vha, 20);
3396
e30d1756
MI		 3397 /* Turn-off FCE trace */
3398 if (ha->flags.fce_enabled) {
3399 qla2x00_disable_fce_trace(vha, NULL, NULL);
3400 ha->flags.fce_enabled = 0;
3401 }
3402
3403 /* Turn-off EFT trace */
3404 if (ha->eft)
3405 qla2x00_disable_eft_trace(vha);
3406
3407 /* Stop currently executing firmware. */
3408 qla2x00_try_to_stop_firmware(vha);
3409
3410 /* Turn adapter off line */
3411 vha->flags.online = 0;
3412
3413 /* turn-off interrupts on the card */
3414 if (ha->interrupts_on) {
3415 vha->flags.init_done = 0;
3416 ha->isp_ops->disable_intrs(ha);
3417 }
3418
3419 qla2x00_free_irqs(vha);
3420
3421 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3422
3423 pci_disable_pcie_error_reporting(pdev);
3424 pci_disable_device(pdev);
e30d1756
MI		 3425}
3426
fe1b806f 3427/* Deletes all the virtual ports for a given ha */
4c993f76 3428static void
fe1b806f 3429qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3430{
fe1b806f 3431 scsi_qla_host_t *vha;
feafb7b1 3432 unsigned long flags;
e315cd28 3433
43ebf16d
AE		 3434 mutex_lock(&ha->vport_lock);
3435 while (ha->cur_vport_count) {
43ebf16d 3436 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3437
43ebf16d
AE		 3438 BUG_ON(base_vha->list.next == &ha->vp_list);
3439 /* This assumes first entry in ha->vp_list is always base vha */
3440 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3441 scsi_host_get(vha->host);
feafb7b1 3442
43ebf16d
AE		 3443 spin_unlock_irqrestore(&ha->vport_slock, flags);
3444 mutex_unlock(&ha->vport_lock);
3445
3446 fc_vport_terminate(vha->fc_vport);
3447 scsi_host_put(vha->host);
feafb7b1 3448
43ebf16d 3449 mutex_lock(&ha->vport_lock);
e315cd28 3450 }
43ebf16d 3451 mutex_unlock(&ha->vport_lock);
fe1b806f 3452}
1da177e4 3453
fe1b806f
CD		 3454/* Stops all deferred work threads */
3455static void
3456qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3457{
7d613ac6
SV		 3458 /* Cancel all work and destroy DPC workqueues */
3459 if (ha->dpc_lp_wq) {
3460 cancel_work_sync(&ha->idc_aen);
3461 destroy_workqueue(ha->dpc_lp_wq);
3462 ha->dpc_lp_wq = NULL;
3463 }
3464
3465 if (ha->dpc_hp_wq) {
3466 cancel_work_sync(&ha->nic_core_reset);
3467 cancel_work_sync(&ha->idc_state_handler);
3468 cancel_work_sync(&ha->nic_core_unrecoverable);
3469 destroy_workqueue(ha->dpc_hp_wq);
3470 ha->dpc_hp_wq = NULL;
3471 }
3472
b9978769
AV		 3473 /* Kill the kernel thread for this host */
3474 if (ha->dpc_thread) {
3475 struct task_struct *t = ha->dpc_thread;
3476
3477 /*
3478 * qla2xxx_wake_dpc checks for ->dpc_thread
3479 * so we need to zero it out.
3480 */
3481 ha->dpc_thread = NULL;
3482 kthread_stop(t);
3483 }
fe1b806f 3484}
1da177e4 3485
fe1b806f
CD		 3486static void
3487qla2x00_unmap_iobases(struct qla_hw_data *ha)
3488{
a9083016 3489 if (IS_QLA82XX(ha)) {
b963752f 3490
f73cb695 3491 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3492 if (!ql2xdbwr)
f73cb695 3493 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3494 } else {
3495 if (ha->iobase)
3496 iounmap(ha->iobase);
1da177e4 3497
8ae6d9c7
GM		 3498 if (ha->cregbase)
3499 iounmap(ha->cregbase);
3500
a9083016
GM		 3501 if (ha->mqiobase)
3502 iounmap(ha->mqiobase);
6246b8a1 3503
f73cb695 3504 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3505 iounmap(ha->msixbase);
a9083016 3506 }
fe1b806f
CD		 3507}
3508
3509static void
db7157d4 3510qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3511{
fe1b806f
CD		 3512 if (IS_QLA8044(ha)) {
3513 qla8044_idc_lock(ha);
c41afc9a 3514 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3515 qla8044_idc_unlock(ha);
3516 } else if (IS_QLA82XX(ha)) {
3517 qla82xx_idc_lock(ha);
3518 qla82xx_clear_drv_active(ha);
3519 qla82xx_idc_unlock(ha);
3520 }
3521}
3522
3523static void
3524qla2x00_remove_one(struct pci_dev *pdev)
3525{
3526 scsi_qla_host_t *base_vha;
3527 struct qla_hw_data *ha;
3528
beb9e315
JL		 3529 base_vha = pci_get_drvdata(pdev);
3530 ha = base_vha->hw;
3531
3532 /* Indicate device removal to prevent future board_disable and wait
3533 * until any pending board_disable has completed. */
3534 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3535 cancel_work_sync(&ha->board_disable);
3536
fe1b806f 3537 /*
beb9e315
JL		 3538 * If the PCI device is disabled then there was a PCI-disconnect and
3539 * qla2x00_disable_board_on_pci_error has taken care of most of the
3540 * resources.
fe1b806f 3541 */
beb9e315 3542 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3543 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3544 base_vha->gnl.l, base_vha->gnl.ldma);
3545
beb9e315
JL		 3546 scsi_host_put(base_vha->host);
3547 kfree(ha);
3548 pci_set_drvdata(pdev, NULL);
fe1b806f 3549 return;
beb9e315 3550 }
638a1a01
SC		 3551 qla2x00_wait_for_hba_ready(base_vha);
3552
726b8548
QT		 3553 /*
3554 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3555 * where it was set first.
3556 */
3557 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3558 return;
3559
fe1b806f 3560 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3561
3562 qla_nvme_delete(base_vha);
3563
726b8548
QT		 3564 dma_free_coherent(&ha->pdev->dev,
3565 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3566
3567 if (IS_QLAFX00(ha))
3568 qlafx00_driver_shutdown(base_vha, 20);
3569
3570 qla2x00_delete_all_vps(ha, base_vha);
3571
3572 if (IS_QLA8031(ha)) {
3573 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3574 "Clearing fcoe driver presence.\n");
3575 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3576 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3577 "Error while clearing DRV-Presence.\n");
3578 }
3579
3580 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3581
3582 qla2x00_dfs_remove(base_vha);
3583
3584 qla84xx_put_chip(base_vha);
3585
2d5a4c34
HM		 3586 /* Laser should be disabled only for ISP2031 */
3587 if (IS_QLA2031(ha))
3588 qla83xx_disable_laser(base_vha);
3589
fe1b806f
CD		 3590 /* Disable timer */
3591 if (base_vha->timer_active)
3592 qla2x00_stop_timer(base_vha);
3593
3594 base_vha->flags.online = 0;
3595
b0d6cabd
HM		 3596 /* free DMA memory */
3597 if (ha->exlogin_buf)
3598 qla2x00_free_exlogin_buffer(ha);
3599
2f56a7f1
HM		 3600 /* free DMA memory */
3601 if (ha->exchoffld_buf)
3602 qla2x00_free_exchoffld_buffer(ha);
3603
fe1b806f
CD		 3604 qla2x00_destroy_deferred_work(ha);
3605
3606 qlt_remove_target(ha, base_vha);
3607
3608 qla2x00_free_sysfs_attr(base_vha, true);
3609
3610 fc_remove_host(base_vha->host);
482c9dc7 3611 qlt_remove_target_resources(ha);
fe1b806f
CD		 3612
3613 scsi_remove_host(base_vha->host);
3614
3615 qla2x00_free_device(base_vha);
3616
db7157d4 3617 qla2x00_clear_drv_active(ha);
fe1b806f 3618
d2749ffa
AE		 3619 scsi_host_put(base_vha->host);
3620
fe1b806f 3621 qla2x00_unmap_iobases(ha);
73208dfd 3622
e315cd28
AC		 3623 pci_release_selected_regions(ha->pdev, ha->bars);
3624 kfree(ha);
1da177e4 3625
90a86fc0
JC		 3626 pci_disable_pcie_error_reporting(pdev);
3627
665db93b 3628 pci_disable_device(pdev);
1da177e4 3629}
1da177e4
LT		 3630
3631static void
e315cd28 3632qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3633{
e315cd28 3634 struct qla_hw_data *ha = vha->hw;
1da177e4 3635
85880801
AV		 3636 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3637
3638 /* Disable timer */
3639 if (vha->timer_active)
3640 qla2x00_stop_timer(vha);
3641
2afa19a9 3642 qla25xx_delete_queues(vha);
fe1b806f 3643
df613b96 3644 if (ha->flags.fce_enabled)
e315cd28 3645 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3646
a7a167bf 3647 if (ha->eft)
e315cd28 3648 qla2x00_disable_eft_trace(vha);
a7a167bf 3649
f6ef3b18 3650 /* Stop currently executing firmware. */
e315cd28 3651 qla2x00_try_to_stop_firmware(vha);
1da177e4 3652
85880801
AV		 3653 vha->flags.online = 0;
3654
f6ef3b18 3655 /* turn-off interrupts on the card */
a9083016
GM		 3656 if (ha->interrupts_on) {
3657 vha->flags.init_done = 0;
fd34f556 3658 ha->isp_ops->disable_intrs(ha);
a9083016 3659 }
f6ef3b18 3660
093df737
QT		 3661 qla2x00_free_fcports(vha);
3662
e315cd28 3663 qla2x00_free_irqs(vha);
1da177e4 3664
093df737
QT		 3665 /* Flush the work queue and remove it */
3666 if (ha->wq) {
3667 flush_workqueue(ha->wq);
3668 destroy_workqueue(ha->wq);
3669 ha->wq = NULL;
3670 }
3671
8867048b 3672
e315cd28 3673 qla2x00_mem_free(ha);
73208dfd 3674
08de2844
GM		 3675 qla82xx_md_free(vha);
3676
73208dfd 3677 qla2x00_free_queues(ha);
1da177e4
LT		 3678}
3679
8867048b
CD		 3680void qla2x00_free_fcports(struct scsi_qla_host *vha)
3681{
3682 fc_port_t *fcport, *tfcport;
3683
3684 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3685 list_del(&fcport->list);
5f16b331 3686 qla2x00_clear_loop_id(fcport);
8867048b 3687 kfree(fcport);
8867048b
CD		 3688 }
3689}
3690
d97994dc 3691static inline void
e315cd28 3692qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3693 int defer)
3694{
d97994dc 3695 struct fc_rport *rport;
67becc00 3696 scsi_qla_host_t *base_vha;
044d78e1 3697 unsigned long flags;
d97994dc
AV		 3698
3699 if (!fcport->rport)
3700 return;
3701
3702 rport = fcport->rport;
3703 if (defer) {
67becc00 3704 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3705 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3706 fcport->drport = rport;
044d78e1 3707 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3708 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3709 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3710 qla2xxx_wake_dpc(base_vha);
2d70c103 3711 } else {
df673274 3712 int now;
726b8548 3713 if (rport) {
83548fe2
QT		 3714 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3715 "%s %8phN. rport %p roles %x\n",
3716 __func__, fcport->port_name, rport,
3717 rport->roles);
d20ed91b 3718 fc_remote_port_delete(rport);
726b8548 3719 }
df673274 3720 qlt_do_generation_tick(vha, &now);
2d70c103 3721 }
d97994dc
AV		 3722}
3723
1da177e4
LT		 3724/*
3725 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3726 *
3727 * Input: ha = adapter block pointer. fcport = port structure pointer.
3728 *
3729 * Return: None.
3730 *
3731 * Context:
3732 */
e315cd28 3733void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3734 int do_login, int defer)
1da177e4 3735{
8ae6d9c7
GM		 3736 if (IS_QLAFX00(vha->hw)) {
3737 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3738 qla2x00_schedule_rport_del(vha, fcport, defer);
3739 return;
3740 }
3741
2c3dfe3f 3742 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3743 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3744 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3745 qla2x00_schedule_rport_del(vha, fcport, defer);
3746 }
fa2a1ce5 3747 /*
1da177e4
LT		 3748 * We may need to retry the login, so don't change the state of the
3749 * port but do the retries.
3750 */
3751 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3752 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3753
3754 if (!do_login)
3755 return;
3756
a1d0285e
AE		 3757 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3758
1da177e4 3759 if (fcport->login_retry == 0) {
e315cd28 3760 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3761
83548fe2 3762 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3763 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3764 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3765 }
3766}
3767
3768/*
3769 * qla2x00_mark_all_devices_lost
3770 * Updates fcport state when device goes offline.
3771 *
3772 * Input:
3773 * ha = adapter block pointer.
3774 * fcport = port structure pointer.
3775 *
3776 * Return:
3777 * None.
3778 *
3779 * Context:
3780 */
3781void
e315cd28 3782qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3783{
3784 fc_port_t *fcport;
3785
83548fe2
QT		 3786 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3787 "Mark all dev lost\n");
726b8548 3788
e315cd28 3789 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3790 fcport->scan_state = 0;
3791 qlt_schedule_sess_for_deletion_lock(fcport);
3792
c6d39e23 3793 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3794 continue;
0d6e61bc 3795
1da177e4
LT		 3796 /*
3797 * No point in marking the device as lost, if the device is
3798 * already DEAD.
3799 */
3800 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3801 continue;
e315cd28 3802 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3803 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3804 if (defer)
3805 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3806 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3807 qla2x00_schedule_rport_del(vha, fcport, defer);
3808 }
1da177e4
LT		 3809 }
3810}
3811
3812/*
3813* qla2x00_mem_alloc
3814* Allocates adapter memory.
3815*
3816* Returns:
3817* 0 = success.
e8711085 3818* !0 = failure.
1da177e4 3819*/
e8711085 3820static int
73208dfd
AC		 3821qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3822 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3823{
3824 char name[16];
1da177e4 3825
e8711085 3826 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3827 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3828 if (!ha->init_cb)
e315cd28 3829 goto fail;
e8711085 3830
2d70c103
NB		 3831 if (qlt_mem_alloc(ha) < 0)
3832 goto fail_free_init_cb;
3833
642ef983
CD		 3834 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3835 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3836 if (!ha->gid_list)
2d70c103 3837 goto fail_free_tgt_mem;
1da177e4 3838
e8711085
AV		 3839 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3840 if (!ha->srb_mempool)
e315cd28 3841 goto fail_free_gid_list;
e8711085 3842
7ec0effd 3843 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3844 /* Allocate cache for CT6 Ctx. */
3845 if (!ctx_cachep) {
3846 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3847 sizeof(struct ct6_dsd), 0,
3848 SLAB_HWCACHE_ALIGN, NULL);
3849 if (!ctx_cachep)
fc1ffd6c 3850 goto fail_free_srb_mempool;
a9083016
GM		 3851 }
3852 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3853 ctx_cachep);
3854 if (!ha->ctx_mempool)
3855 goto fail_free_srb_mempool;
7c3df132
SK		 3856 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3857 "ctx_cachep=%p ctx_mempool=%p.\n",
3858 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3859 }
3860
e8711085
AV		 3861 /* Get memory for cached NVRAM */
3862 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3863 if (!ha->nvram)
a9083016 3864 goto fail_free_ctx_mempool;
e8711085 3865
e315cd28
AC		 3866 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3867 ha->pdev->device);
3868 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3869 DMA_POOL_SIZE, 8, 0);
3870 if (!ha->s_dma_pool)
3871 goto fail_free_nvram;
3872
7c3df132
SK		 3873 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3874 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3875 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3876
7ec0effd 3877 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3878 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3879 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3880 if (!ha->dl_dma_pool) {
7c3df132
SK		 3881 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3882 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3883 goto fail_s_dma_pool;
3884 }
3885
3886 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3887 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3888 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3889 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3890 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3891 goto fail_dl_dma_pool;
3892 }
7c3df132
SK		 3893 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3894 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3895 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3896 }
3897
e8711085
AV		 3898 /* Allocate memory for SNS commands */
3899 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3900 /* Get consistent memory allocated for SNS commands */
e8711085 3901 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3902 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3903 if (!ha->sns_cmd)
e315cd28 3904 goto fail_dma_pool;
7c3df132 3905 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3906 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3907 } else {
e315cd28 3908 /* Get consistent memory allocated for MS IOCB */
e8711085 3909 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3910 &ha->ms_iocb_dma);
e8711085 3911 if (!ha->ms_iocb)
e315cd28
AC		 3912 goto fail_dma_pool;
3913 /* Get consistent memory allocated for CT SNS commands */
e8711085 3914 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3915 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3916 if (!ha->ct_sns)
3917 goto fail_free_ms_iocb;
7c3df132
SK		 3918 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3919 "ms_iocb=%p ct_sns=%p.\n",
3920 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3921 }
3922
e315cd28 3923 /* Allocate memory for request ring */
73208dfd
AC		 3924 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3925 if (!*req) {
7c3df132
SK		 3926 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3927 "Failed to allocate memory for req.\n");
e315cd28
AC		 3928 goto fail_req;
3929 }
73208dfd
AC		 3930 (*req)->length = req_len;
3931 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3932 ((*req)->length + 1) * sizeof(request_t),
3933 &(*req)->dma, GFP_KERNEL);
3934 if (!(*req)->ring) {
7c3df132
SK		 3935 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3936 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3937 goto fail_req_ring;
3938 }
3939 /* Allocate memory for response ring */
73208dfd
AC		 3940 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3941 if (!*rsp) {
7c3df132
SK		 3942 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3943 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3944 goto fail_rsp;
3945 }
73208dfd
AC		 3946 (*rsp)->hw = ha;
3947 (*rsp)->length = rsp_len;
3948 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3949 ((*rsp)->length + 1) * sizeof(response_t),
3950 &(*rsp)->dma, GFP_KERNEL);
3951 if (!(*rsp)->ring) {
7c3df132
SK		 3952 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3953 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3954 goto fail_rsp_ring;
3955 }
73208dfd
AC		 3956 (*req)->rsp = *rsp;
3957 (*rsp)->req = *req;
7c3df132
SK		 3958 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3959 "req=%p req->length=%d req->ring=%p rsp=%p "
3960 "rsp->length=%d rsp->ring=%p.\n",
3961 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3962 (*rsp)->ring);
73208dfd
AC		 3963 /* Allocate memory for NVRAM data for vports */
3964 if (ha->nvram_npiv_size) {
3965 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3966 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3967 if (!ha->npiv_info) {
7c3df132
SK		 3968 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3969 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3970 goto fail_npiv_info;
3971 }
3972 } else
3973 ha->npiv_info = NULL;
e8711085 3974
b64b0e8f 3975 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3976 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3977 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3978 &ha->ex_init_cb_dma);
3979 if (!ha->ex_init_cb)
3980 goto fail_ex_init_cb;
7c3df132
SK		 3981 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3982 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3983 }
3984
a9083016
GM		 3985 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3986
5ff1d584
AV		 3987 /* Get consistent memory allocated for Async Port-Database. */
3988 if (!IS_FWI2_CAPABLE(ha)) {
3989 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3990 &ha->async_pd_dma);
3991 if (!ha->async_pd)
3992 goto fail_async_pd;
7c3df132
SK		 3993 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3994 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3995 }
3996
e315cd28 3997 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3998
3999 /* Allocate memory for our loop_id bitmap */
4000 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4001 GFP_KERNEL);
4002 if (!ha->loop_id_map)
fc1ffd6c 4003 goto fail_loop_id_map;
5f16b331
CD		 4004 else {
4005 qla2x00_set_reserved_loop_ids(ha);
4006 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4007 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4008 }
4009
b2a72ec3 4010 return 0;
e315cd28 4011
fc1ffd6c
QT		 4012fail_loop_id_map:
4013 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4014fail_async_pd:
4015 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4016fail_ex_init_cb:
4017 kfree(ha->npiv_info);
73208dfd
AC		 4018fail_npiv_info:
4019 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4020 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4021 (*rsp)->ring = NULL;
4022 (*rsp)->dma = 0;
e315cd28 4023fail_rsp_ring:
73208dfd 4024 kfree(*rsp);
e315cd28 4025fail_rsp:
73208dfd
AC		 4026 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4027 sizeof(request_t), (*req)->ring, (*req)->dma);
4028 (*req)->ring = NULL;
4029 (*req)->dma = 0;
e315cd28 4030fail_req_ring:
73208dfd 4031 kfree(*req);
e315cd28
AC		 4032fail_req:
4033 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4034 ha->ct_sns, ha->ct_sns_dma);
4035 ha->ct_sns = NULL;
4036 ha->ct_sns_dma = 0;
e8711085
AV		 4037fail_free_ms_iocb:
4038 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4039 ha->ms_iocb = NULL;
4040 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4041
4042 if (ha->sns_cmd)
4043 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4044 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4045fail_dma_pool:
bad75002 4046 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4047 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4048 ha->fcp_cmnd_dma_pool = NULL;
4049 }
4050fail_dl_dma_pool:
bad75002 4051 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4052 dma_pool_destroy(ha->dl_dma_pool);
4053 ha->dl_dma_pool = NULL;
4054 }
4055fail_s_dma_pool:
e315cd28
AC		 4056 dma_pool_destroy(ha->s_dma_pool);
4057 ha->s_dma_pool = NULL;
e8711085
AV		 4058fail_free_nvram:
4059 kfree(ha->nvram);
4060 ha->nvram = NULL;
a9083016 4061fail_free_ctx_mempool:
fc1ffd6c
QT		 4062 if (ha->ctx_mempool)
4063 mempool_destroy(ha->ctx_mempool);
a9083016 4064 ha->ctx_mempool = NULL;
e8711085 4065fail_free_srb_mempool:
fc1ffd6c
QT		 4066 if (ha->srb_mempool)
4067 mempool_destroy(ha->srb_mempool);
e8711085 4068 ha->srb_mempool = NULL;
e8711085 4069fail_free_gid_list:
642ef983
CD		 4070 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4071 ha->gid_list,
e315cd28 4072 ha->gid_list_dma);
e8711085
AV		 4073 ha->gid_list = NULL;
4074 ha->gid_list_dma = 0;
2d70c103
NB		 4075fail_free_tgt_mem:
4076 qlt_mem_free(ha);
e315cd28
AC		 4077fail_free_init_cb:
4078 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4079 ha->init_cb_dma);
4080 ha->init_cb = NULL;
4081 ha->init_cb_dma = 0;
e8711085 4082fail:
7c3df132
SK		 4083 ql_log(ql_log_fatal, NULL, 0x0030,
4084 "Memory allocation failure.\n");
e8711085 4085 return -ENOMEM;
1da177e4
LT		 4086}
4087
b0d6cabd
HM		 4088int
4089qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4090{
4091 int rval;
4092 uint16_t size, max_cnt, temp;
4093 struct qla_hw_data *ha = vha->hw;
4094
4095 /* Return if we don't need to alloacate any extended logins */
4096 if (!ql2xexlogins)
4097 return QLA_SUCCESS;
4098
99e1b683
QT		 4099 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4100 return QLA_SUCCESS;
4101
b0d6cabd
HM		 4102 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4103 max_cnt = 0;
4104 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4105 if (rval != QLA_SUCCESS) {
4106 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4107 "Failed to get exlogin status.\n");
4108 return rval;
4109 }
4110
4111 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4112 temp *= size;
4113
4114 if (temp != ha->exlogin_size) {
4115 qla2x00_free_exlogin_buffer(ha);
4116 ha->exlogin_size = temp;
4117
4118 ql_log(ql_log_info, vha, 0xd024,
4119 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4120 max_cnt, size, temp);
4121
4122 ql_log(ql_log_info, vha, 0xd025,
4123 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4124
4125 /* Get consistent memory for extended logins */
4126 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4127 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4128 if (!ha->exlogin_buf) {
4129 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4130 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4131 return -ENOMEM;
4132 }
b0d6cabd
HM		 4133 }
4134
4135 /* Now configure the dma buffer */
4136 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4137 if (rval) {
83548fe2 4138 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4139 "Setup extended login buffer ****FAILED****.\n");
4140 qla2x00_free_exlogin_buffer(ha);
4141 }
4142
4143 return rval;
4144}
4145
4146/*
4147* qla2x00_free_exlogin_buffer
4148*
4149* Input:
4150* ha = adapter block pointer
4151*/
4152void
4153qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4154{
4155 if (ha->exlogin_buf) {
4156 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4157 ha->exlogin_buf, ha->exlogin_buf_dma);
4158 ha->exlogin_buf = NULL;
4159 ha->exlogin_size = 0;
4160 }
4161}
4162
99e1b683
QT		 4163static void
4164qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4165{
4166 u32 temp;
4167 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4168
4169 if (qla_ini_mode_enabled(vha)) {
4170 if (ql2xiniexchg > max_cnt)
4171 ql2xiniexchg = max_cnt;
4172
4173 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4174 *ret_cnt = ql2xiniexchg;
4175 } else if (qla_tgt_mode_enabled(vha)) {
4176 if (ql2xexchoffld > max_cnt)
4177 ql2xexchoffld = max_cnt;
4178
4179 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4180 *ret_cnt = ql2xexchoffld;
4181 } else if (qla_dual_mode_enabled(vha)) {
4182 temp = ql2xiniexchg + ql2xexchoffld;
4183 if (temp > max_cnt) {
4184 ql2xiniexchg -= (temp - max_cnt)/2;
4185 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4186 temp = max_cnt;
4187 }
4188
4189 if (temp > FW_DEF_EXCHANGES_CNT)
4190 *ret_cnt = temp;
4191 }
4192}
4193
2f56a7f1
HM		 4194int
4195qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4196{
4197 int rval;
99e1b683
QT		 4198 u16 size, max_cnt;
4199 u32 temp;
2f56a7f1
HM		 4200 struct qla_hw_data *ha = vha->hw;
4201
99e1b683
QT		 4202 if (!ha->flags.exchoffld_enabled)
4203 return QLA_SUCCESS;
4204
4205 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4206 return QLA_SUCCESS;
4207
2f56a7f1
HM		 4208 max_cnt = 0;
4209 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4210 if (rval != QLA_SUCCESS) {
4211 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4212 "Failed to get exlogin status.\n");
4213 return rval;
4214 }
4215
99e1b683
QT		 4216 qla2x00_number_of_exch(vha, &temp, max_cnt);
4217 temp *= size;
2f56a7f1 4218
99e1b683
QT		 4219 if (temp != ha->exchoffld_size) {
4220 qla2x00_free_exchoffld_buffer(ha);
4221 ha->exchoffld_size = temp;
4222
4223 ql_log(ql_log_info, vha, 0xd016,
4224 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4225 max_cnt, size, temp);
4226
4227 ql_log(ql_log_info, vha, 0xd017,
4228 "Exchange Buffers requested size = 0x%x\n",
4229 ha->exchoffld_size);
4230
4231 /* Get consistent memory for extended logins */
4232 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4233 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4234 if (!ha->exchoffld_buf) {
4235 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4236 "Failed to allocate memory for exchoffld_buf_dma.\n");
4237 return -ENOMEM;
4238 }
2f56a7f1
HM		 4239 }
4240
4241 /* Now configure the dma buffer */
99e1b683 4242 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4243 if (rval) {
4244 ql_log(ql_log_fatal, vha, 0xd02e,
4245 "Setup exchange offload buffer ****FAILED****.\n");
4246 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4247 } else {
4248 /* re-adjust number of target exchange */
4249 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4250
4251 if (qla_ini_mode_enabled(vha))
4252 icb->exchange_count = 0;
4253 else
4254 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4255 }
4256
4257 return rval;
4258}
4259
4260/*
4261* qla2x00_free_exchoffld_buffer
4262*
4263* Input:
4264* ha = adapter block pointer
4265*/
4266void
4267qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4268{
4269 if (ha->exchoffld_buf) {
4270 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4271 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4272 ha->exchoffld_buf = NULL;
4273 ha->exchoffld_size = 0;
4274 }
4275}
4276
1da177e4 4277/*
e30d1756
MI		 4278* qla2x00_free_fw_dump
4279* Frees fw dump stuff.
1da177e4
LT		 4280*
4281* Input:
7ec0effd 4282* ha = adapter block pointer
1da177e4 4283*/
a824ebb3 4284static void
e30d1756 4285qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4286{
df613b96 4287 if (ha->fce)
f73cb695
CD		 4288 dma_free_coherent(&ha->pdev->dev,
4289 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4290
f73cb695
CD		 4291 if (ha->eft)
4292 dma_free_coherent(&ha->pdev->dev,
4293 EFT_SIZE, ha->eft, ha->eft_dma);
4294
4295 if (ha->fw_dump)
a7a167bf 4296 vfree(ha->fw_dump);
f73cb695
CD		 4297 if (ha->fw_dump_template)
4298 vfree(ha->fw_dump_template);
4299
e30d1756
MI		 4300 ha->fce = NULL;
4301 ha->fce_dma = 0;
4302 ha->eft = NULL;
4303 ha->eft_dma = 0;
e30d1756 4304 ha->fw_dumped = 0;
61f098dd 4305 ha->fw_dump_cap_flags = 0;
e30d1756 4306 ha->fw_dump_reading = 0;
f73cb695
CD		 4307 ha->fw_dump = NULL;
4308 ha->fw_dump_len = 0;
4309 ha->fw_dump_template = NULL;
4310 ha->fw_dump_template_len = 0;
e30d1756
MI		 4311}
4312
4313/*
4314* qla2x00_mem_free
4315* Frees all adapter allocated memory.
4316*
4317* Input:
4318* ha = adapter block pointer.
4319*/
4320static void
4321qla2x00_mem_free(struct qla_hw_data *ha)
4322{
4323 qla2x00_free_fw_dump(ha);
4324
81178772
SK		 4325 if (ha->mctp_dump)
4326 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4327 ha->mctp_dump_dma);
4328
e30d1756
MI		 4329 if (ha->srb_mempool)
4330 mempool_destroy(ha->srb_mempool);
a7a167bf 4331
11bbc1d8
AV		 4332 if (ha->dcbx_tlv)
4333 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4334 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4335
ce0423f4
AV		 4336 if (ha->xgmac_data)
4337 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4338 ha->xgmac_data, ha->xgmac_data_dma);
4339
1da177e4
LT		 4340 if (ha->sns_cmd)
4341 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4342 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4343
4344 if (ha->ct_sns)
4345 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4346 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4347
88729e53
AV		 4348 if (ha->sfp_data)
4349 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4350
1da177e4
LT		 4351 if (ha->ms_iocb)
4352 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4353
b64b0e8f 4354 if (ha->ex_init_cb)
a9083016
GM		 4355 dma_pool_free(ha->s_dma_pool,
4356 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4357
5ff1d584
AV		 4358 if (ha->async_pd)
4359 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4360
1da177e4
LT		 4361 if (ha->s_dma_pool)
4362 dma_pool_destroy(ha->s_dma_pool);
4363
1da177e4 4364 if (ha->gid_list)
642ef983
CD		 4365 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4366 ha->gid_list, ha->gid_list_dma);
1da177e4 4367
a9083016
GM		 4368 if (IS_QLA82XX(ha)) {
4369 if (!list_empty(&ha->gbl_dsd_list)) {
4370 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4371
4372 /* clean up allocated prev pool */
4373 list_for_each_entry_safe(dsd_ptr,
4374 tdsd_ptr, &ha->gbl_dsd_list, list) {
4375 dma_pool_free(ha->dl_dma_pool,
4376 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4377 list_del(&dsd_ptr->list);
4378 kfree(dsd_ptr);
4379 }
4380 }
4381 }
4382
4383 if (ha->dl_dma_pool)
4384 dma_pool_destroy(ha->dl_dma_pool);
4385
4386 if (ha->fcp_cmnd_dma_pool)
4387 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4388
4389 if (ha->ctx_mempool)
4390 mempool_destroy(ha->ctx_mempool);
4391
2d70c103
NB		 4392 qlt_mem_free(ha);
4393
e315cd28
AC		 4394 if (ha->init_cb)
4395 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4396 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4397 vfree(ha->optrom_buffer);
4398 kfree(ha->nvram);
73208dfd 4399 kfree(ha->npiv_info);
7a67735b 4400 kfree(ha->swl);
5f16b331 4401 kfree(ha->loop_id_map);
1da177e4 4402
e8711085 4403 ha->srb_mempool = NULL;
a9083016 4404 ha->ctx_mempool = NULL;
1da177e4
LT		 4405 ha->sns_cmd = NULL;
4406 ha->sns_cmd_dma = 0;
4407 ha->ct_sns = NULL;
4408 ha->ct_sns_dma = 0;
4409 ha->ms_iocb = NULL;
4410 ha->ms_iocb_dma = 0;
1da177e4
LT		 4411 ha->init_cb = NULL;
4412 ha->init_cb_dma = 0;
b64b0e8f
AV		 4413 ha->ex_init_cb = NULL;
4414 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4415 ha->async_pd = NULL;
4416 ha->async_pd_dma = 0;
1da177e4
LT		 4417
4418 ha->s_dma_pool = NULL;
a9083016
GM		 4419 ha->dl_dma_pool = NULL;
4420 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4421
1da177e4
LT		 4422 ha->gid_list = NULL;
4423 ha->gid_list_dma = 0;
2d70c103
NB		 4424
4425 ha->tgt.atio_ring = NULL;
4426 ha->tgt.atio_dma = 0;
4427 ha->tgt.tgt_vp_map = NULL;
e315cd28 4428}
1da177e4 4429
e315cd28
AC		 4430struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4431 struct qla_hw_data *ha)
4432{
4433 struct Scsi_Host *host;
4434 struct scsi_qla_host *vha = NULL;
854165f4 4435
e315cd28 4436 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4437 if (!host) {
7c3df132
SK		 4438 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4439 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4440 return NULL;
e315cd28
AC		 4441 }
4442
4443 /* Clear our data area */
4444 vha = shost_priv(host);
4445 memset(vha, 0, sizeof(scsi_qla_host_t));
4446
4447 vha->host = host;
4448 vha->host_no = host->host_no;
4449 vha->hw = ha;
4450
4451 INIT_LIST_HEAD(&vha->vp_fcports);
4452 INIT_LIST_HEAD(&vha->work_list);
4453 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4454 INIT_LIST_HEAD(&vha->qla_cmd_list);
4455 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4456 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4457 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4458 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4459 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4460 INIT_LIST_HEAD(&vha->nvme_rport_list);
e315cd28 4461
f999f4c1 4462 spin_lock_init(&vha->work_lock);
8b2f5ff3 4463 spin_lock_init(&vha->cmd_list_lock);
726b8548 4464 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4465 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4466
2fdbc65e
BVA		 4467 vha->gnl.size = sizeof(struct get_name_list_extended) *
4468 (ha->max_loop_id + 1);
41dc529a
QT		 4469 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4470 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4471 if (!vha->gnl.l) {
83548fe2 4472 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4473 "Alloc failed for name list.\n");
4474 scsi_remove_host(vha->host);
4475 return NULL;
4476 }
f999f4c1 4477
e315cd28 4478 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4479 ql_dbg(ql_dbg_init, vha, 0x0041,
4480 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4481 vha->host, vha->hw, vha,
4482 dev_name(&(ha->pdev->dev)));
4483
e315cd28 4484 return vha;
1da177e4
LT		 4485}
4486
726b8548 4487struct qla_work_evt *
f999f4c1 4488qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4489{
4490 struct qla_work_evt *e;
feafb7b1
AE		 4491 uint8_t bail;
4492
4493 QLA_VHA_MARK_BUSY(vha, bail);
4494 if (bail)
4495 return NULL;
0971de7f 4496
f999f4c1 4497 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4498 if (!e) {
4499 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4500 return NULL;
feafb7b1 4501 }
0971de7f
AV		 4502
4503 INIT_LIST_HEAD(&e->list);
4504 e->type = type;
4505 e->flags = QLA_EVT_FLAG_FREE;
4506 return e;
4507}
4508
726b8548 4509int
f999f4c1 4510qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4511{
f999f4c1 4512 unsigned long flags;
0971de7f 4513
f999f4c1 4514 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4515 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4516 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4517
4518 if (QLA_EARLY_LINKUP(vha->hw))
4519 schedule_work(&vha->iocb_work);
4520 else
4521 qla2xxx_wake_dpc(vha);
f999f4c1 4522
0971de7f
AV		 4523 return QLA_SUCCESS;
4524}
4525
4526int
e315cd28 4527qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4528 u32 data)
4529{
4530 struct qla_work_evt *e;
4531
f999f4c1 4532 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4533 if (!e)
4534 return QLA_FUNCTION_FAILED;
4535
4536 e->u.aen.code = code;
4537 e->u.aen.data = data;
f999f4c1 4538 return qla2x00_post_work(vha, e);
0971de7f
AV		 4539}
4540
8a659571
AV		 4541int
4542qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4543{
4544 struct qla_work_evt *e;
4545
f999f4c1 4546 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4547 if (!e)
4548 return QLA_FUNCTION_FAILED;
4549
4550 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4551 return qla2x00_post_work(vha, e);
8a659571
AV		 4552}
4553
ac280b67
AV		 4554#define qla2x00_post_async_work(name, type) \
4555int qla2x00_post_async_##name##_work( \
4556 struct scsi_qla_host *vha, \
4557 fc_port_t *fcport, uint16_t *data) \
4558{ \
4559 struct qla_work_evt *e; \
4560 \
4561 e = qla2x00_alloc_work(vha, type); \
4562 if (!e) \
4563 return QLA_FUNCTION_FAILED; \
4564 \
4565 e->u.logio.fcport = fcport; \
4566 if (data) { \
4567 e->u.logio.data[0] = data[0]; \
4568 e->u.logio.data[1] = data[1]; \
4569 } \
4570 return qla2x00_post_work(vha, e); \
4571}
4572
4573qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4574qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4575qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4576qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4577qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4578
3420d36c
AV		 4579int
4580qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4581{
4582 struct qla_work_evt *e;
4583
4584 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4585 if (!e)
4586 return QLA_FUNCTION_FAILED;
4587
4588 e->u.uevent.code = code;
4589 return qla2x00_post_work(vha, e);
4590}
4591
4592static void
4593qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4594{
4595 char event_string[40];
4596 char *envp[] = { event_string, NULL };
4597
4598 switch (code) {
4599 case QLA_UEVENT_CODE_FW_DUMP:
4600 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4601 vha->host_no);
4602 break;
4603 default:
4604 /* do nothing */
4605 break;
4606 }
4607 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4608}
4609
8ae6d9c7
GM		 4610int
4611qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4612 uint32_t *data, int cnt)
4613{
4614 struct qla_work_evt *e;
4615
4616 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4617 if (!e)
4618 return QLA_FUNCTION_FAILED;
4619
4620 e->u.aenfx.evtcode = evtcode;
4621 e->u.aenfx.count = cnt;
4622 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4623 return qla2x00_post_work(vha, e);
4624}
4625
726b8548
QT		 4626int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4627{
4628 struct qla_work_evt *e;
4629
4630 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4631 if (!e)
4632 return QLA_FUNCTION_FAILED;
4633
4634 e->u.fcport.fcport = fcport;
4635 return qla2x00_post_work(vha, e);
4636}
4637
4638static
4639void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4640{
4641 unsigned long flags;
4642 fc_port_t *fcport = NULL;
4643 struct qlt_plogi_ack_t *pla =
4644 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4645
4646 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4647 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4648 if (fcport) {
4649 fcport->d_id = e->u.new_sess.id;
4650 if (pla) {
4651 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4652 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4653 /* we took an extra ref_count to prevent PLOGI ACK when
4654 * fcport/sess has not been created.
4655 */
4656 pla->ref_count--;
4657 }
4658 } else {
4659 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4660 if (fcport) {
4661 fcport->d_id = e->u.new_sess.id;
4662 fcport->scan_state = QLA_FCPORT_FOUND;
4663 fcport->flags |= FCF_FABRIC_DEVICE;
4664 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4665
4666 memcpy(fcport->port_name, e->u.new_sess.port_name,
4667 WWN_SIZE);
4668 list_add_tail(&fcport->list, &vha->vp_fcports);
4669
4670 if (pla) {
4671 qlt_plogi_ack_link(vha, pla, fcport,
4672 QLT_PLOGI_LINK_SAME_WWN);
4673 pla->ref_count--;
4674 }
4675 }
4676 }
4677 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4678
4679 if (fcport) {
4680 if (pla)
4681 qlt_plogi_ack_unref(vha, pla);
4682 else
4683 qla24xx_async_gnl(vha, fcport);
4684 }
4685}
4686
ac280b67 4687void
e315cd28 4688qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4689{
f999f4c1
AV		 4690 struct qla_work_evt *e, *tmp;
4691 unsigned long flags;
4692 LIST_HEAD(work);
0971de7f 4693
f999f4c1
AV		 4694 spin_lock_irqsave(&vha->work_lock, flags);
4695 list_splice_init(&vha->work_list, &work);
4696 spin_unlock_irqrestore(&vha->work_lock, flags);
4697
4698 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4699 list_del_init(&e->list);
0971de7f
AV		 4700
4701 switch (e->type) {
4702 case QLA_EVT_AEN:
e315cd28 4703 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4704 e->u.aen.code, e->u.aen.data);
4705 break;
8a659571
AV		 4706 case QLA_EVT_IDC_ACK:
4707 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4708 break;
ac280b67
AV		 4709 case QLA_EVT_ASYNC_LOGIN:
4710 qla2x00_async_login(vha, e->u.logio.fcport,
4711 e->u.logio.data);
4712 break;
ac280b67
AV		 4713 case QLA_EVT_ASYNC_LOGOUT:
4714 qla2x00_async_logout(vha, e->u.logio.fcport);
4715 break;
4716 case QLA_EVT_ASYNC_LOGOUT_DONE:
4717 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4718 e->u.logio.data);
4719 break;
5ff1d584
AV		 4720 case QLA_EVT_ASYNC_ADISC:
4721 qla2x00_async_adisc(vha, e->u.logio.fcport,
4722 e->u.logio.data);
4723 break;
4724 case QLA_EVT_ASYNC_ADISC_DONE:
4725 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4726 e->u.logio.data);
4727 break;
3420d36c
AV		 4728 case QLA_EVT_UEVENT:
4729 qla2x00_uevent_emit(vha, e->u.uevent.code);
4730 break;
8ae6d9c7
GM		 4731 case QLA_EVT_AENFX:
4732 qlafx00_process_aen(vha, e);
4733 break;
726b8548
QT		 4734 case QLA_EVT_GIDPN:
4735 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4736 break;
4737 case QLA_EVT_GPNID:
4738 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4739 break;
4740 case QLA_EVT_GPNID_DONE:
4741 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4742 break;
4743 case QLA_EVT_NEW_SESS:
4744 qla24xx_create_new_sess(vha, e);
4745 break;
4746 case QLA_EVT_GPDB:
4747 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4748 e->u.fcport.opt);
4749 break;
a5d42f4c
DG		 4750 case QLA_EVT_PRLI:
4751 qla24xx_async_prli(vha, e->u.fcport.fcport);
4752 break;
726b8548
QT		 4753 case QLA_EVT_GPSC:
4754 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4755 break;
4756 case QLA_EVT_UPD_FCPORT:
4757 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4758 break;
4759 case QLA_EVT_GNL:
4760 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4761 break;
4762 case QLA_EVT_NACK:
4763 qla24xx_do_nack_work(vha, e);
4764 break;
0971de7f
AV		 4765 }
4766 if (e->flags & QLA_EVT_FLAG_FREE)
4767 kfree(e);
feafb7b1
AE		 4768
4769 /* For each work completed decrement vha ref count */
4770 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4771 }
e315cd28 4772}
f999f4c1 4773
e315cd28
AC		 4774/* Relogins all the fcports of a vport
4775 * Context: dpc thread
4776 */
4777void qla2x00_relogin(struct scsi_qla_host *vha)
4778{
4779 fc_port_t *fcport;
c6b2fca8 4780 int status;
726b8548 4781 struct event_arg ea;
e315cd28
AC		 4782
4783 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4784 /*
4785 * If the port is not ONLINE then try to login
4786 * to it if we haven't run out of retries.
4787 */
5ff1d584
AV		 4788 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4789 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4790 fcport->login_retry--;
e315cd28 4791 if (fcport->flags & FCF_FABRIC_DEVICE) {
83548fe2 4792 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4793 "%s %8phC DS %d LS %d\n", __func__,
4794 fcport->port_name, fcport->disc_state,
4795 fcport->fw_login_state);
4796 memset(&ea, 0, sizeof(ea));
4797 ea.event = FCME_RELOGIN;
4798 ea.fcport = fcport;
4799 qla2x00_fcport_event_handler(vha, &ea);
4800 } else {
e315cd28
AC		 4801 status = qla2x00_local_device_login(vha,
4802 fcport);
726b8548
QT		 4803 if (status == QLA_SUCCESS) {
4804 fcport->old_loop_id = fcport->loop_id;
4805 ql_dbg(ql_dbg_disc, vha, 0x2003,
4806 "Port login OK: logged in ID 0x%x.\n",
4807 fcport->loop_id);
4808 qla2x00_update_fcport(vha, fcport);
4809 } else if (status == 1) {
4810 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4811 /* retry the login again */
4812 ql_dbg(ql_dbg_disc, vha, 0x2007,
4813 "Retrying %d login again loop_id 0x%x.\n",
4814 fcport->login_retry,
4815 fcport->loop_id);
4816 } else {
4817 fcport->login_retry = 0;
4818 }
e315cd28 4819
726b8548
QT		 4820 if (fcport->login_retry == 0 &&
4821 status != QLA_SUCCESS)
4822 qla2x00_clear_loop_id(fcport);
e315cd28 4823 }
e315cd28
AC		 4824 }
4825 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4826 break;
0971de7f 4827 }
0971de7f
AV		 4828}
4829
7d613ac6
SV		 4830/* Schedule work on any of the dpc-workqueues */
4831void
4832qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4833{
4834 struct qla_hw_data *ha = base_vha->hw;
4835
4836 switch (work_code) {
4837 case MBA_IDC_AEN: /* 0x8200 */
4838 if (ha->dpc_lp_wq)
4839 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4840 break;
4841
4842 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4843 if (!ha->flags.nic_core_reset_hdlr_active) {
4844 if (ha->dpc_hp_wq)
4845 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4846 } else
4847 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4848 "NIC Core reset is already active. Skip "
4849 "scheduling it again.\n");
4850 break;
4851 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4852 if (ha->dpc_hp_wq)
4853 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4854 break;
4855 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4856 if (ha->dpc_hp_wq)
4857 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4858 break;
4859 default:
4860 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4861 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4862 }
4863
4864 return;
4865}
4866
4867/* Work: Perform NIC Core Unrecoverable state handling */
4868void
4869qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4870{
4871 struct qla_hw_data *ha =
2ad1b67c 4872 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4873 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4874 uint32_t dev_state = 0;
4875
4876 qla83xx_idc_lock(base_vha, 0);
4877 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4878 qla83xx_reset_ownership(base_vha);
4879 if (ha->flags.nic_core_reset_owner) {
4880 ha->flags.nic_core_reset_owner = 0;
4881 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4882 QLA8XXX_DEV_FAILED);
4883 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4884 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4885 }
4886 qla83xx_idc_unlock(base_vha, 0);
4887}
4888
4889/* Work: Execute IDC state handler */
4890void
4891qla83xx_idc_state_handler_work(struct work_struct *work)
4892{
4893 struct qla_hw_data *ha =
2ad1b67c 4894 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4895 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4896 uint32_t dev_state = 0;
4897
4898 qla83xx_idc_lock(base_vha, 0);
4899 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4900 if (dev_state == QLA8XXX_DEV_FAILED ||
4901 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4902 qla83xx_idc_state_handler(base_vha);
4903 qla83xx_idc_unlock(base_vha, 0);
4904}
4905
fa492630 4906static int
7d613ac6
SV		 4907qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4908{
4909 int rval = QLA_SUCCESS;
4910 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4911 uint32_t heart_beat_counter1, heart_beat_counter2;
4912
4913 do {
4914 if (time_after(jiffies, heart_beat_wait)) {
4915 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4916 "Nic Core f/w is not alive.\n");
4917 rval = QLA_FUNCTION_FAILED;
4918 break;
4919 }
4920
4921 qla83xx_idc_lock(base_vha, 0);
4922 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4923 &heart_beat_counter1);
4924 qla83xx_idc_unlock(base_vha, 0);
4925 msleep(100);
4926 qla83xx_idc_lock(base_vha, 0);
4927 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4928 &heart_beat_counter2);
4929 qla83xx_idc_unlock(base_vha, 0);
4930 } while (heart_beat_counter1 == heart_beat_counter2);
4931
4932 return rval;
4933}
4934
4935/* Work: Perform NIC Core Reset handling */
4936void
4937qla83xx_nic_core_reset_work(struct work_struct *work)
4938{
4939 struct qla_hw_data *ha =
4940 container_of(work, struct qla_hw_data, nic_core_reset);
4941 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4942 uint32_t dev_state = 0;
4943
81178772
SK		 4944 if (IS_QLA2031(ha)) {
4945 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4946 ql_log(ql_log_warn, base_vha, 0xb081,
4947 "Failed to dump mctp\n");
4948 return;
4949 }
4950
7d613ac6
SV		 4951 if (!ha->flags.nic_core_reset_hdlr_active) {
4952 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4953 qla83xx_idc_lock(base_vha, 0);
4954 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4955 &dev_state);
4956 qla83xx_idc_unlock(base_vha, 0);
4957 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4958 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4959 "Nic Core f/w is alive.\n");
4960 return;
4961 }
4962 }
4963
4964 ha->flags.nic_core_reset_hdlr_active = 1;
4965 if (qla83xx_nic_core_reset(base_vha)) {
4966 /* NIC Core reset failed. */
4967 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4968 "NIC Core reset failed.\n");
4969 }
4970 ha->flags.nic_core_reset_hdlr_active = 0;
4971 }
4972}
4973
4974/* Work: Handle 8200 IDC aens */
4975void
4976qla83xx_service_idc_aen(struct work_struct *work)
4977{
4978 struct qla_hw_data *ha =
4979 container_of(work, struct qla_hw_data, idc_aen);
4980 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4981 uint32_t dev_state, idc_control;
4982
4983 qla83xx_idc_lock(base_vha, 0);
4984 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4985 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4986 qla83xx_idc_unlock(base_vha, 0);
4987 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4988 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4989 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4990 "Application requested NIC Core Reset.\n");
4991 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4992 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4993 QLA_SUCCESS) {
4994 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4995 "Other protocol driver requested NIC Core Reset.\n");
4996 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4997 }
4998 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4999 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5000 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5001 }
5002}
5003
5004static void
5005qla83xx_wait_logic(void)
5006{
5007 int i;
5008
5009 /* Yield CPU */
5010 if (!in_interrupt()) {
5011 /*
5012 * Wait about 200ms before retrying again.
5013 * This controls the number of retries for single
5014 * lock operation.
5015 */
5016 msleep(100);
5017 schedule();
5018 } else {
5019 for (i = 0; i < 20; i++)
5020 cpu_relax(); /* This a nop instr on i386 */
5021 }
5022}
5023
fa492630 5024static int
7d613ac6
SV		 5025qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5026{
5027 int rval;
5028 uint32_t data;
5029 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5030 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5031 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5032 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5033 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5034
5035 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5036 if (rval)
5037 return rval;
5038
5039 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5040 return QLA_SUCCESS;
5041 } else {
5042 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5043 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5044 data);
5045 if (rval)
5046 return rval;
5047
5048 msleep(200);
5049
5050 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5051 &data);
5052 if (rval)
5053 return rval;
5054
5055 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5056 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5057 ~(idc_lck_rcvry_stage_mask));
5058 rval = qla83xx_wr_reg(base_vha,
5059 QLA83XX_IDC_LOCK_RECOVERY, data);
5060 if (rval)
5061 return rval;
5062
5063 /* Forcefully perform IDC UnLock */
5064 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5065 &data);
5066 if (rval)
5067 return rval;
5068 /* Clear lock-id by setting 0xff */
5069 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5070 0xff);
5071 if (rval)
5072 return rval;
5073 /* Clear lock-recovery by setting 0x0 */
5074 rval = qla83xx_wr_reg(base_vha,
5075 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5076 if (rval)
5077 return rval;
5078 } else
5079 return QLA_SUCCESS;
5080 }
5081
5082 return rval;
5083}
5084
fa492630 5085static int
7d613ac6
SV		 5086qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5087{
5088 int rval = QLA_SUCCESS;
5089 uint32_t o_drv_lockid, n_drv_lockid;
5090 unsigned long lock_recovery_timeout;
5091
5092 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5093retry_lockid:
5094 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5095 if (rval)
5096 goto exit;
5097
5098 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5099 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5100 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5101 return QLA_SUCCESS;
5102 else
5103 return QLA_FUNCTION_FAILED;
5104 }
5105
5106 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5107 if (rval)
5108 goto exit;
5109
5110 if (o_drv_lockid == n_drv_lockid) {
5111 qla83xx_wait_logic();
5112 goto retry_lockid;
5113 } else
5114 return QLA_SUCCESS;
5115
5116exit:
5117 return rval;
5118}
5119
5120void
5121qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5122{
5123 uint16_t options = (requester_id << 15) | BIT_6;
5124 uint32_t data;
6c315553 5125 uint32_t lock_owner;
7d613ac6
SV		 5126 struct qla_hw_data *ha = base_vha->hw;
5127
5128 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5129retry_lock:
5130 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5131 == QLA_SUCCESS) {
5132 if (data) {
5133 /* Setting lock-id to our function-number */
5134 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5135 ha->portnum);
5136 } else {
6c315553
SK		 5137 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5138 &lock_owner);
7d613ac6 5139 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5140 "Failed to acquire IDC lock, acquired by %d, "
5141 "retrying...\n", lock_owner);
7d613ac6
SV		 5142
5143 /* Retry/Perform IDC-Lock recovery */
5144 if (qla83xx_idc_lock_recovery(base_vha)
5145 == QLA_SUCCESS) {
5146 qla83xx_wait_logic();
5147 goto retry_lock;
5148 } else
5149 ql_log(ql_log_warn, base_vha, 0xb075,
5150 "IDC Lock recovery FAILED.\n");
5151 }
5152
5153 }
5154
5155 return;
5156
5157 /* XXX: IDC-lock implementation using access-control mbx */
5158retry_lock2:
5159 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5160 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5161 "Failed to acquire IDC lock. retrying...\n");
5162 /* Retry/Perform IDC-Lock recovery */
5163 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5164 qla83xx_wait_logic();
5165 goto retry_lock2;
5166 } else
5167 ql_log(ql_log_warn, base_vha, 0xb076,
5168 "IDC Lock recovery FAILED.\n");
5169 }
5170
5171 return;
5172}
5173
5174void
5175qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5176{
5897cb2f
BVA		 5177#if 0
5178 uint16_t options = (requester_id << 15) | BIT_7;
5179#endif
5180 uint16_t retry;
7d613ac6
SV		 5181 uint32_t data;
5182 struct qla_hw_data *ha = base_vha->hw;
5183
5184 /* IDC-unlock implementation using driver-unlock/lock-id
5185 * remote registers
5186 */
5187 retry = 0;
5188retry_unlock:
5189 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5190 == QLA_SUCCESS) {
5191 if (data == ha->portnum) {
5192 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5193 /* Clearing lock-id by setting 0xff */
5194 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5195 } else if (retry < 10) {
5196 /* SV: XXX: IDC unlock retrying needed here? */
5197
5198 /* Retry for IDC-unlock */
5199 qla83xx_wait_logic();
5200 retry++;
5201 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5202 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5203 goto retry_unlock;
5204 }
5205 } else if (retry < 10) {
5206 /* Retry for IDC-unlock */
5207 qla83xx_wait_logic();
5208 retry++;
5209 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5210 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5211 goto retry_unlock;
5212 }
5213
5214 return;
5215
5897cb2f 5216#if 0
7d613ac6
SV		 5217 /* XXX: IDC-unlock implementation using access-control mbx */
5218 retry = 0;
5219retry_unlock2:
5220 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5221 if (retry < 10) {
5222 /* Retry for IDC-unlock */
5223 qla83xx_wait_logic();
5224 retry++;
5225 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5226 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5227 goto retry_unlock2;
5228 }
5229 }
5230
5231 return;
5897cb2f 5232#endif
7d613ac6
SV		 5233}
5234
5235int
5236__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5237{
5238 int rval = QLA_SUCCESS;
5239 struct qla_hw_data *ha = vha->hw;
5240 uint32_t drv_presence;
5241
5242 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5243 if (rval == QLA_SUCCESS) {
5244 drv_presence |= (1 << ha->portnum);
5245 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5246 drv_presence);
5247 }
5248
5249 return rval;
5250}
5251
5252int
5253qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5254{
5255 int rval = QLA_SUCCESS;
5256
5257 qla83xx_idc_lock(vha, 0);
5258 rval = __qla83xx_set_drv_presence(vha);
5259 qla83xx_idc_unlock(vha, 0);
5260
5261 return rval;
5262}
5263
5264int
5265__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5266{
5267 int rval = QLA_SUCCESS;
5268 struct qla_hw_data *ha = vha->hw;
5269 uint32_t drv_presence;
5270
5271 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5272 if (rval == QLA_SUCCESS) {
5273 drv_presence &= ~(1 << ha->portnum);
5274 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5275 drv_presence);
5276 }
5277
5278 return rval;
5279}
5280
5281int
5282qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5283{
5284 int rval = QLA_SUCCESS;
5285
5286 qla83xx_idc_lock(vha, 0);
5287 rval = __qla83xx_clear_drv_presence(vha);
5288 qla83xx_idc_unlock(vha, 0);
5289
5290 return rval;
5291}
5292
fa492630 5293static void
7d613ac6
SV		 5294qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5295{
5296 struct qla_hw_data *ha = vha->hw;
5297 uint32_t drv_ack, drv_presence;
5298 unsigned long ack_timeout;
5299
5300 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5301 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5302 while (1) {
5303 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5304 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5305 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5306 break;
5307
5308 if (time_after_eq(jiffies, ack_timeout)) {
5309 ql_log(ql_log_warn, vha, 0xb067,
5310 "RESET ACK TIMEOUT! drv_presence=0x%x "
5311 "drv_ack=0x%x\n", drv_presence, drv_ack);
5312 /*
5313 * The function(s) which did not ack in time are forced
5314 * to withdraw any further participation in the IDC
5315 * reset.
5316 */
5317 if (drv_ack != drv_presence)
5318 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5319 drv_ack);
5320 break;
5321 }
5322
5323 qla83xx_idc_unlock(vha, 0);
5324 msleep(1000);
5325 qla83xx_idc_lock(vha, 0);
5326 }
5327
5328 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5329 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5330}
5331
fa492630 5332static int
7d613ac6
SV		 5333qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5334{
5335 int rval = QLA_SUCCESS;
5336 uint32_t idc_control;
5337
5338 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5339 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5340
5341 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5342 __qla83xx_get_idc_control(vha, &idc_control);
5343 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5344 __qla83xx_set_idc_control(vha, 0);
5345
5346 qla83xx_idc_unlock(vha, 0);
5347 rval = qla83xx_restart_nic_firmware(vha);
5348 qla83xx_idc_lock(vha, 0);
5349
5350 if (rval != QLA_SUCCESS) {
5351 ql_log(ql_log_fatal, vha, 0xb06a,
5352 "Failed to restart NIC f/w.\n");
5353 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5354 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5355 } else {
5356 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5357 "Success in restarting nic f/w.\n");
5358 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5359 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5360 }
5361
5362 return rval;
5363}
5364
5365/* Assumes idc_lock always held on entry */
5366int
5367qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5368{
5369 struct qla_hw_data *ha = base_vha->hw;
5370 int rval = QLA_SUCCESS;
5371 unsigned long dev_init_timeout;
5372 uint32_t dev_state;
5373
5374 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5375 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5376
5377 while (1) {
5378
5379 if (time_after_eq(jiffies, dev_init_timeout)) {
5380 ql_log(ql_log_warn, base_vha, 0xb06e,
5381 "Initialization TIMEOUT!\n");
5382 /* Init timeout. Disable further NIC Core
5383 * communication.
5384 */
5385 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5386 QLA8XXX_DEV_FAILED);
5387 ql_log(ql_log_info, base_vha, 0xb06f,
5388 "HW State: FAILED.\n");
5389 }
5390
5391 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5392 switch (dev_state) {
5393 case QLA8XXX_DEV_READY:
5394 if (ha->flags.nic_core_reset_owner)
5395 qla83xx_idc_audit(base_vha,
5396 IDC_AUDIT_COMPLETION);
5397 ha->flags.nic_core_reset_owner = 0;
5398 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5399 "Reset_owner reset by 0x%x.\n",
5400 ha->portnum);
5401 goto exit;
5402 case QLA8XXX_DEV_COLD:
5403 if (ha->flags.nic_core_reset_owner)
5404 rval = qla83xx_device_bootstrap(base_vha);
5405 else {
5406 /* Wait for AEN to change device-state */
5407 qla83xx_idc_unlock(base_vha, 0);
5408 msleep(1000);
5409 qla83xx_idc_lock(base_vha, 0);
5410 }
5411 break;
5412 case QLA8XXX_DEV_INITIALIZING:
5413 /* Wait for AEN to change device-state */
5414 qla83xx_idc_unlock(base_vha, 0);
5415 msleep(1000);
5416 qla83xx_idc_lock(base_vha, 0);
5417 break;
5418 case QLA8XXX_DEV_NEED_RESET:
5419 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5420 qla83xx_need_reset_handler(base_vha);
5421 else {
5422 /* Wait for AEN to change device-state */
5423 qla83xx_idc_unlock(base_vha, 0);
5424 msleep(1000);
5425 qla83xx_idc_lock(base_vha, 0);
5426 }
5427 /* reset timeout value after need reset handler */
5428 dev_init_timeout = jiffies +
5429 (ha->fcoe_dev_init_timeout * HZ);
5430 break;
5431 case QLA8XXX_DEV_NEED_QUIESCENT:
5432 /* XXX: DEBUG for now */
5433 qla83xx_idc_unlock(base_vha, 0);
5434 msleep(1000);
5435 qla83xx_idc_lock(base_vha, 0);
5436 break;
5437 case QLA8XXX_DEV_QUIESCENT:
5438 /* XXX: DEBUG for now */
5439 if (ha->flags.quiesce_owner)
5440 goto exit;
5441
5442 qla83xx_idc_unlock(base_vha, 0);
5443 msleep(1000);
5444 qla83xx_idc_lock(base_vha, 0);
5445 dev_init_timeout = jiffies +
5446 (ha->fcoe_dev_init_timeout * HZ);
5447 break;
5448 case QLA8XXX_DEV_FAILED:
5449 if (ha->flags.nic_core_reset_owner)
5450 qla83xx_idc_audit(base_vha,
5451 IDC_AUDIT_COMPLETION);
5452 ha->flags.nic_core_reset_owner = 0;
5453 __qla83xx_clear_drv_presence(base_vha);
5454 qla83xx_idc_unlock(base_vha, 0);
5455 qla8xxx_dev_failed_handler(base_vha);
5456 rval = QLA_FUNCTION_FAILED;
5457 qla83xx_idc_lock(base_vha, 0);
5458 goto exit;
5459 case QLA8XXX_BAD_VALUE:
5460 qla83xx_idc_unlock(base_vha, 0);
5461 msleep(1000);
5462 qla83xx_idc_lock(base_vha, 0);
5463 break;
5464 default:
5465 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5466 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5467 qla83xx_idc_unlock(base_vha, 0);
5468 qla8xxx_dev_failed_handler(base_vha);
5469 rval = QLA_FUNCTION_FAILED;
5470 qla83xx_idc_lock(base_vha, 0);
5471 goto exit;
5472 }
5473 }
5474
5475exit:
5476 return rval;
5477}
5478
f3ddac19
CD		 5479void
5480qla2x00_disable_board_on_pci_error(struct work_struct *work)
5481{
5482 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5483 board_disable);
5484 struct pci_dev *pdev = ha->pdev;
5485 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5486
726b8548
QT		 5487 /*
5488 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5489 * where it was set first.
5490 */
5491 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5492 return;
5493
f3ddac19
CD		 5494 ql_log(ql_log_warn, base_vha, 0x015b,
5495 "Disabling adapter.\n");
5496
726b8548
QT		 5497 qla2x00_wait_for_sess_deletion(base_vha);
5498
f3ddac19
CD		 5499 set_bit(UNLOADING, &base_vha->dpc_flags);
5500
5501 qla2x00_delete_all_vps(ha, base_vha);
5502
5503 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5504
5505 qla2x00_dfs_remove(base_vha);
5506
5507 qla84xx_put_chip(base_vha);
5508
5509 if (base_vha->timer_active)
5510 qla2x00_stop_timer(base_vha);
5511
5512 base_vha->flags.online = 0;
5513
5514 qla2x00_destroy_deferred_work(ha);
5515
5516 /*
5517 * Do not try to stop beacon blink as it will issue a mailbox
5518 * command.
5519 */
5520 qla2x00_free_sysfs_attr(base_vha, false);
5521
5522 fc_remove_host(base_vha->host);
5523
5524 scsi_remove_host(base_vha->host);
5525
5526 base_vha->flags.init_done = 0;
5527 qla25xx_delete_queues(base_vha);
f3ddac19 5528 qla2x00_free_fcports(base_vha);
093df737 5529 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5530 qla2x00_mem_free(ha);
5531 qla82xx_md_free(base_vha);
5532 qla2x00_free_queues(ha);
5533
f3ddac19
CD		 5534 qla2x00_unmap_iobases(ha);
5535
5536 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5537 pci_disable_pcie_error_reporting(pdev);
5538 pci_disable_device(pdev);
f3ddac19 5539
beb9e315
JL		 5540 /*
5541 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5542 */
f3ddac19
CD		 5543}
5544
1da177e4
LT		 5545/**************************************************************************
5546* qla2x00_do_dpc
5547* This kernel thread is a task that is schedule by the interrupt handler
5548* to perform the background processing for interrupts.
5549*
5550* Notes:
5551* This task always run in the context of a kernel thread. It
5552* is kick-off by the driver's detect code and starts up
5553* up one per adapter. It immediately goes to sleep and waits for
5554* some fibre event. When either the interrupt handler or
5555* the timer routine detects a event it will one of the task
5556* bits then wake us up.
5557**************************************************************************/
5558static int
5559qla2x00_do_dpc(void *data)
5560{
e315cd28
AC		 5561 scsi_qla_host_t *base_vha;
5562 struct qla_hw_data *ha;
d7459527
MH		 5563 uint32_t online;
5564 struct qla_qpair *qpair;
1da177e4 5565
e315cd28
AC		 5566 ha = (struct qla_hw_data *)data;
5567 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5568
8698a745 5569 set_user_nice(current, MIN_NICE);
1da177e4 5570
563585ec 5571 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5572 while (!kthread_should_stop()) {
7c3df132
SK		 5573 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5574 "DPC handler sleeping.\n");
1da177e4 5575
39a11240 5576 schedule();
1da177e4 5577
c142caf0
AV		 5578 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5579 goto end_loop;
1da177e4 5580
85880801 5581 if (ha->flags.eeh_busy) {
7c3df132
SK		 5582 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5583 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5584 goto end_loop;
85880801
AV		 5585 }
5586
1da177e4
LT		 5587 ha->dpc_active = 1;
5588
5f28d2d7
SK		 5589 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5590 "DPC handler waking up, dpc_flags=0x%lx.\n",
5591 base_vha->dpc_flags);
1da177e4 5592
a29b3dd7
JC		 5593 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5594 break;
5595
e315cd28 5596 qla2x00_do_work(base_vha);
0971de7f 5597
7ec0effd
AD		 5598 if (IS_P3P_TYPE(ha)) {
5599 if (IS_QLA8044(ha)) {
5600 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5601 &base_vha->dpc_flags)) {
5602 qla8044_idc_lock(ha);
5603 qla8044_wr_direct(base_vha,
5604 QLA8044_CRB_DEV_STATE_INDEX,
5605 QLA8XXX_DEV_FAILED);
5606 qla8044_idc_unlock(ha);
5607 ql_log(ql_log_info, base_vha, 0x4004,
5608 "HW State: FAILED.\n");
5609 qla8044_device_state_handler(base_vha);
5610 continue;
5611 }
5612
5613 } else {
5614 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5615 &base_vha->dpc_flags)) {
5616 qla82xx_idc_lock(ha);
5617 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5618 QLA8XXX_DEV_FAILED);
5619 qla82xx_idc_unlock(ha);
5620 ql_log(ql_log_info, base_vha, 0x0151,
5621 "HW State: FAILED.\n");
5622 qla82xx_device_state_handler(base_vha);
5623 continue;
5624 }
a9083016
GM		 5625 }
5626
5627 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5628 &base_vha->dpc_flags)) {
5629
7c3df132
SK		 5630 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5631 "FCoE context reset scheduled.\n");
a9083016
GM		 5632 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5633 &base_vha->dpc_flags))) {
5634 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5635 /* FCoE-ctx reset failed.
5636 * Escalate to chip-reset
5637 */
5638 set_bit(ISP_ABORT_NEEDED,
5639 &base_vha->dpc_flags);
5640 }
5641 clear_bit(ABORT_ISP_ACTIVE,
5642 &base_vha->dpc_flags);
5643 }
5644
7c3df132
SK		 5645 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5646 "FCoE context reset end.\n");
a9083016 5647 }
8ae6d9c7
GM		 5648 } else if (IS_QLAFX00(ha)) {
5649 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5650 &base_vha->dpc_flags)) {
5651 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5652 "Firmware Reset Recovery\n");
5653 if (qlafx00_reset_initialize(base_vha)) {
5654 /* Failed. Abort isp later. */
5655 if (!test_bit(UNLOADING,
f92f82d6 5656 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5657 set_bit(ISP_UNRECOVERABLE,
5658 &base_vha->dpc_flags);
5659 ql_dbg(ql_dbg_dpc, base_vha,
5660 0x4021,
5661 "Reset Recovery Failed\n");
f92f82d6 5662 }
8ae6d9c7
GM		 5663 }
5664 }
5665
5666 if (test_and_clear_bit(FX00_TARGET_SCAN,
5667 &base_vha->dpc_flags)) {
5668 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5669 "ISPFx00 Target Scan scheduled\n");
5670 if (qlafx00_rescan_isp(base_vha)) {
5671 if (!test_bit(UNLOADING,
5672 &base_vha->dpc_flags))
5673 set_bit(ISP_UNRECOVERABLE,
5674 &base_vha->dpc_flags);
5675 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5676 "ISPFx00 Target Scan Failed\n");
5677 }
5678 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5679 "ISPFx00 Target Scan End\n");
5680 }
e8f5e95d
AB		 5681 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5682 &base_vha->dpc_flags)) {
5683 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5684 "ISPFx00 Host Info resend scheduled\n");
5685 qlafx00_fx_disc(base_vha,
5686 &base_vha->hw->mr.fcport,
5687 FXDISC_REG_HOST_INFO);
5688 }
a9083016
GM		 5689 }
5690
e315cd28
AC		 5691 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5692 &base_vha->dpc_flags)) {
1da177e4 5693
7c3df132
SK		 5694 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5695 "ISP abort scheduled.\n");
1da177e4 5696 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5697 &base_vha->dpc_flags))) {
1da177e4 5698
a9083016 5699 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5700 /* failed. retry later */
5701 set_bit(ISP_ABORT_NEEDED,
e315cd28 5702 &base_vha->dpc_flags);
99363ef8 5703 }
e315cd28
AC		 5704 clear_bit(ABORT_ISP_ACTIVE,
5705 &base_vha->dpc_flags);
99363ef8
SJ		 5706 }
5707
7c3df132
SK		 5708 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5709 "ISP abort end.\n");
1da177e4
LT		 5710 }
5711
a394aac8
DJ		 5712 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5713 &base_vha->dpc_flags)) {
e315cd28 5714 qla2x00_update_fcports(base_vha);
c9c5ced9 5715 }
d97994dc 5716
8ae6d9c7
GM		 5717 if (IS_QLAFX00(ha))
5718 goto loop_resync_check;
5719
579d12b5 5720 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5721 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5722 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5723 if (IS_P3P_TYPE(ha)) {
5724 if (IS_QLA82XX(ha))
5725 qla82xx_device_state_handler(base_vha);
5726 if (IS_QLA8044(ha))
5727 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5728 clear_bit(ISP_QUIESCE_NEEDED,
5729 &base_vha->dpc_flags);
5730 if (!ha->flags.quiesce_owner) {
5731 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5732 if (IS_QLA82XX(ha)) {
5733 qla82xx_idc_lock(ha);
5734 qla82xx_clear_qsnt_ready(
5735 base_vha);
5736 qla82xx_idc_unlock(ha);
5737 } else if (IS_QLA8044(ha)) {
5738 qla8044_idc_lock(ha);
5739 qla8044_clear_qsnt_ready(
5740 base_vha);
5741 qla8044_idc_unlock(ha);
5742 }
8fcd6b8b
CD		 5743 }
5744 } else {
5745 clear_bit(ISP_QUIESCE_NEEDED,
5746 &base_vha->dpc_flags);
5747 qla2x00_quiesce_io(base_vha);
579d12b5 5748 }
7c3df132
SK		 5749 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5750 "Quiescence mode end.\n");
579d12b5
SK		 5751 }
5752
e315cd28 5753 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5754 &base_vha->dpc_flags) &&
e315cd28 5755 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5756
7c3df132
SK		 5757 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5758 "Reset marker scheduled.\n");
e315cd28
AC		 5759 qla2x00_rst_aen(base_vha);
5760 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5761 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5762 "Reset marker end.\n");
1da177e4
LT		 5763 }
5764
5765 /* Retry each device up to login retry count */
e315cd28
AC		 5766 if ((test_and_clear_bit(RELOGIN_NEEDED,
5767 &base_vha->dpc_flags)) &&
5768 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5769 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5770
7c3df132
SK		 5771 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5772 "Relogin scheduled.\n");
e315cd28 5773 qla2x00_relogin(base_vha);
7c3df132
SK		 5774 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5775 "Relogin end.\n");
1da177e4 5776 }
8ae6d9c7 5777loop_resync_check:
e315cd28 5778 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5779 &base_vha->dpc_flags)) {
1da177e4 5780
7c3df132
SK		 5781 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5782 "Loop resync scheduled.\n");
1da177e4
LT		 5783
5784 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5785 &base_vha->dpc_flags))) {
1da177e4 5786
52c82823 5787 qla2x00_loop_resync(base_vha);
1da177e4 5788
e315cd28
AC		 5789 clear_bit(LOOP_RESYNC_ACTIVE,
5790 &base_vha->dpc_flags);
1da177e4
LT		 5791 }
5792
7c3df132
SK		 5793 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5794 "Loop resync end.\n");
1da177e4
LT		 5795 }
5796
8ae6d9c7
GM		 5797 if (IS_QLAFX00(ha))
5798 goto intr_on_check;
5799
e315cd28
AC		 5800 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5801 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5802 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5803 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5804 }
5805
8ae6d9c7 5806intr_on_check:
1da177e4 5807 if (!ha->interrupts_on)
fd34f556 5808 ha->isp_ops->enable_intrs(ha);
1da177e4 5809
e315cd28 5810 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5811 &base_vha->dpc_flags)) {
5812 if (ha->beacon_blink_led == 1)
5813 ha->isp_ops->beacon_blink(base_vha);
5814 }
f6df144c 5815
d7459527
MH		 5816 /* qpair online check */
5817 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5818 &base_vha->dpc_flags)) {
5819 if (ha->flags.eeh_busy ||
5820 ha->flags.pci_channel_io_perm_failure)
5821 online = 0;
5822 else
5823 online = 1;
5824
5825 mutex_lock(&ha->mq_lock);
5826 list_for_each_entry(qpair, &base_vha->qp_list,
5827 qp_list_elem)
5828 qpair->online = online;
5829 mutex_unlock(&ha->mq_lock);
5830 }
5831
deeae7a6
DG		 5832 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
5833 ql_log(ql_log_info, base_vha, 0xffffff,
5834 "nvme: SET ZIO Activity exchange threshold to %d.\n",
5835 ha->nvme_last_rptd_aen);
5836 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
5837 ql_log(ql_log_info, base_vha, 0xffffff,
5838 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
5839 ha->nvme_last_rptd_aen);
5840 }
5841 }
5842
8ae6d9c7
GM		 5843 if (!IS_QLAFX00(ha))
5844 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5845
1da177e4 5846 ha->dpc_active = 0;
c142caf0 5847end_loop:
563585ec 5848 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5849 } /* End of while(1) */
563585ec 5850 __set_current_state(TASK_RUNNING);
1da177e4 5851
7c3df132
SK		 5852 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5853 "DPC handler exiting.\n");
1da177e4
LT		 5854
5855 /*
5856 * Make sure that nobody tries to wake us up again.
5857 */
1da177e4
LT		 5858 ha->dpc_active = 0;
5859
ac280b67
AV		 5860 /* Cleanup any residual CTX SRBs. */
5861 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5862
39a11240
CH		 5863 return 0;
5864}
5865
5866void
e315cd28 5867qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5868{
e315cd28 5869 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5870 struct task_struct *t = ha->dpc_thread;
5871
e315cd28 5872 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5873 wake_up_process(t);
1da177e4
LT		 5874}
5875
1da177e4
LT		 5876/*
5877* qla2x00_rst_aen
5878* Processes asynchronous reset.
5879*
5880* Input:
5881* ha = adapter block pointer.
5882*/
5883static void
e315cd28 5884qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5885{
e315cd28
AC		 5886 if (vha->flags.online && !vha->flags.reset_active &&
5887 !atomic_read(&vha->loop_down_timer) &&
5888 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5889 do {
e315cd28 5890 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5891
5892 /*
5893 * Issue marker command only when we are going to start
5894 * the I/O.
5895 */
e315cd28
AC		 5896 vha->marker_needed = 1;
5897 } while (!atomic_read(&vha->loop_down_timer) &&
5898 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5899 }
5900}
5901
1da177e4
LT		 5902/**************************************************************************
5903* qla2x00_timer
5904*
5905* Description:
5906* One second timer
5907*
5908* Context: Interrupt
5909***************************************************************************/
2c3dfe3f 5910void
e315cd28 5911qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5912{
1da177e4 5913 unsigned long cpu_flags = 0;
1da177e4
LT		 5914 int start_dpc = 0;
5915 int index;
5916 srb_t *sp;
85880801 5917 uint16_t w;
e315cd28 5918 struct qla_hw_data *ha = vha->hw;
73208dfd 5919 struct req_que *req;
85880801 5920
a5b36321 5921 if (ha->flags.eeh_busy) {
7c3df132
SK		 5922 ql_dbg(ql_dbg_timer, vha, 0x6000,
5923 "EEH = %d, restarting timer.\n",
5924 ha->flags.eeh_busy);
a5b36321
LC		 5925 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5926 return;
5927 }
5928
f3ddac19
CD		 5929 /*
5930 * Hardware read to raise pending EEH errors during mailbox waits. If
5931 * the read returns -1 then disable the board.
5932 */
5933 if (!pci_channel_offline(ha->pdev)) {
85880801 5934 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5935 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5936 }
1da177e4 5937
cefcaba6 5938 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5939 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5940 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5941 start_dpc++;
7ec0effd
AD		 5942 if (IS_QLA82XX(ha))
5943 qla82xx_watchdog(vha);
5944 else if (IS_QLA8044(ha))
5945 qla8044_watchdog(vha);
579d12b5
SK		 5946 }
5947
8ae6d9c7
GM		 5948 if (!vha->vp_idx && IS_QLAFX00(ha))
5949 qlafx00_timer_routine(vha);
5950
1da177e4 5951 /* Loop down handler. */
e315cd28 5952 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5953 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5954 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5955 && vha->flags.online) {
1da177e4 5956
e315cd28
AC		 5957 if (atomic_read(&vha->loop_down_timer) ==
5958 vha->loop_down_abort_time) {
1da177e4 5959
7c3df132
SK		 5960 ql_log(ql_log_info, vha, 0x6008,
5961 "Loop down - aborting the queues before time expires.\n");
1da177e4 5962
e315cd28
AC		 5963 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5964 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5965
f08b7251
AV		 5966 /*
5967 * Schedule an ISP abort to return any FCP2-device
5968 * commands.
5969 */
2c3dfe3f 5970 /* NPIV - scan physical port only */
e315cd28 5971 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5972 spin_lock_irqsave(&ha->hardware_lock,
5973 cpu_flags);
73208dfd 5974 req = ha->req_q_map[0];
2c3dfe3f 5975 for (index = 1;
8d93f550 5976 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5977 index++) {
5978 fc_port_t *sfcp;
5979
e315cd28 5980 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5981 if (!sp)
5982 continue;
c5419e26
QT		 5983 if (sp->cmd_type != TYPE_SRB)
5984 continue;
9ba56b95 5985 if (sp->type != SRB_SCSI_CMD)
cf53b069 5986 continue;
2c3dfe3f 5987 sfcp = sp->fcport;
f08b7251 5988 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5989 continue;
bdf79621 5990
8f7daead
GM		 5991 if (IS_QLA82XX(ha))
5992 set_bit(FCOE_CTX_RESET_NEEDED,
5993 &vha->dpc_flags);
5994 else
5995 set_bit(ISP_ABORT_NEEDED,
e315cd28 5996 &vha->dpc_flags);
2c3dfe3f
SJ		 5997 break;
5998 }
5999 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6000 cpu_flags);
1da177e4 6001 }
1da177e4
LT		 6002 start_dpc++;
6003 }
6004
6005 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6006 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6007 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6008 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6009 "Loop down - aborting ISP.\n");
6010
8f7daead
GM		 6011 if (IS_QLA82XX(ha))
6012 set_bit(FCOE_CTX_RESET_NEEDED,
6013 &vha->dpc_flags);
6014 else
6015 set_bit(ISP_ABORT_NEEDED,
6016 &vha->dpc_flags);
1da177e4
LT		 6017 }
6018 }
7c3df132
SK		 6019 ql_dbg(ql_dbg_timer, vha, 0x600a,
6020 "Loop down - seconds remaining %d.\n",
6021 atomic_read(&vha->loop_down_timer));
1da177e4 6022 }
cefcaba6
SK		 6023 /* Check if beacon LED needs to be blinked for physical host only */
6024 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6025 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6026 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6027 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6028 start_dpc++;
6029 }
f6df144c
AV		 6030 }
6031
550bf57d 6032 /* Process any deferred work. */
e315cd28 6033 if (!list_empty(&vha->work_list))
550bf57d
AV		 6034 start_dpc++;
6035
7401bc18
DG		 6036 /*
6037 * FC-NVME
6038 * see if the active AEN count has changed from what was last reported.
6039 */
deeae7a6
DG		 6040 if (!vha->vp_idx &&
6041 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6042 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6043 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6044 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6045 ha->nvme_last_rptd_aen);
6046 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6047 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6048 start_dpc++;
7401bc18
DG		 6049 }
6050
1da177e4 6051 /* Schedule the DPC routine if needed */
e315cd28
AC		 6052 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6053 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6054 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6055 start_dpc ||
e315cd28
AC		 6056 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6057 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6058 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6059 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6060 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6061 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6062 ql_dbg(ql_dbg_timer, vha, 0x600b,
6063 "isp_abort_needed=%d loop_resync_needed=%d "
6064 "fcport_update_needed=%d start_dpc=%d "
6065 "reset_marker_needed=%d",
6066 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6067 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6068 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6069 start_dpc,
6070 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6071 ql_dbg(ql_dbg_timer, vha, 0x600c,
6072 "beacon_blink_needed=%d isp_unrecoverable=%d "
6073 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6074 "relogin_needed=%d.\n",
7c3df132
SK		 6075 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6076 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6077 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6078 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6079 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6080 qla2xxx_wake_dpc(vha);
7c3df132 6081 }
1da177e4 6082
e315cd28 6083 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6084}
6085
5433383e
AV		 6086/* Firmware interface routines. */
6087
f73cb695 6088#define FW_BLOBS 11
5433383e
AV		 6089#define FW_ISP21XX 0
6090#define FW_ISP22XX 1
6091#define FW_ISP2300 2
6092#define FW_ISP2322 3
48c02fde 6093#define FW_ISP24XX 4
c3a2f0df 6094#define FW_ISP25XX 5
3a03eb79 6095#define FW_ISP81XX 6
a9083016 6096#define FW_ISP82XX 7
6246b8a1
GM		 6097#define FW_ISP2031 8
6098#define FW_ISP8031 9
2c5bbbb2 6099#define FW_ISP27XX 10
5433383e 6100
bb8ee499
AV		 6101#define FW_FILE_ISP21XX "ql2100_fw.bin"
6102#define FW_FILE_ISP22XX "ql2200_fw.bin"
6103#define FW_FILE_ISP2300 "ql2300_fw.bin"
6104#define FW_FILE_ISP2322 "ql2322_fw.bin"
6105#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6106#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6107#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6108#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6109#define FW_FILE_ISP2031 "ql2600_fw.bin"
6110#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6111#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6112
bb8ee499 6113
e1e82b6f 6114static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6115
6116static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6117 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6118 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6119 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6120 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6121 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6122 { .name = FW_FILE_ISP25XX, },
3a03eb79 6123 { .name = FW_FILE_ISP81XX, },
a9083016 6124 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6125 { .name = FW_FILE_ISP2031, },
6126 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6127 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6128};
6129
6130struct fw_blob *
e315cd28 6131qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6132{
e315cd28 6133 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6134 struct fw_blob *blob;
6135
5433383e
AV		 6136 if (IS_QLA2100(ha)) {
6137 blob = &qla_fw_blobs[FW_ISP21XX];
6138 } else if (IS_QLA2200(ha)) {
6139 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6140 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6141 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6142 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6143 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6144 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6145 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6146 } else if (IS_QLA25XX(ha)) {
6147 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6148 } else if (IS_QLA81XX(ha)) {
6149 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6150 } else if (IS_QLA82XX(ha)) {
6151 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6152 } else if (IS_QLA2031(ha)) {
6153 blob = &qla_fw_blobs[FW_ISP2031];
6154 } else if (IS_QLA8031(ha)) {
6155 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6156 } else if (IS_QLA27XX(ha)) {
6157 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6158 } else {
6159 return NULL;
5433383e
AV		 6160 }
6161
e1e82b6f 6162 mutex_lock(&qla_fw_lock);
5433383e
AV		 6163 if (blob->fw)
6164 goto out;
6165
6166 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6167 ql_log(ql_log_warn, vha, 0x0063,
6168 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6169 blob->fw = NULL;
6170 blob = NULL;
6171 goto out;
6172 }
6173
6174out:
e1e82b6f 6175 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6176 return blob;
6177}
6178
6179static void
6180qla2x00_release_firmware(void)
6181{
6182 int idx;
6183
e1e82b6f 6184 mutex_lock(&qla_fw_lock);
5433383e 6185 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6186 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6187 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6188}
6189
14e660e6
SJ		 6190static pci_ers_result_t
6191qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6192{
85880801
AV		 6193 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6194 struct qla_hw_data *ha = vha->hw;
6195
7c3df132
SK		 6196 ql_dbg(ql_dbg_aer, vha, 0x9000,
6197 "PCI error detected, state %x.\n", state);
b9b12f73 6198
14e660e6
SJ		 6199 switch (state) {
6200 case pci_channel_io_normal:
85880801 6201 ha->flags.eeh_busy = 0;
d7459527
MH		 6202 if (ql2xmqsupport) {
6203 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6204 qla2xxx_wake_dpc(vha);
6205 }
14e660e6
SJ		 6206 return PCI_ERS_RESULT_CAN_RECOVER;
6207 case pci_channel_io_frozen:
85880801 6208 ha->flags.eeh_busy = 1;
a5b36321
LC		 6209 /* For ISP82XX complete any pending mailbox cmd */
6210 if (IS_QLA82XX(ha)) {
7190575f 6211 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6212 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6213 qla82xx_clear_pending_mbx(vha);
a5b36321 6214 }
90a86fc0 6215 qla2x00_free_irqs(vha);
14e660e6 6216 pci_disable_device(pdev);
bddd2d65
LC		 6217 /* Return back all IOs */
6218 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6219 if (ql2xmqsupport) {
6220 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6221 qla2xxx_wake_dpc(vha);
6222 }
14e660e6
SJ		 6223 return PCI_ERS_RESULT_NEED_RESET;
6224 case pci_channel_io_perm_failure:
85880801
AV		 6225 ha->flags.pci_channel_io_perm_failure = 1;
6226 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6227 if (ql2xmqsupport) {
6228 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6229 qla2xxx_wake_dpc(vha);
6230 }
14e660e6
SJ		 6231 return PCI_ERS_RESULT_DISCONNECT;
6232 }
6233 return PCI_ERS_RESULT_NEED_RESET;
6234}
6235
6236static pci_ers_result_t
6237qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6238{
6239 int risc_paused = 0;
6240 uint32_t stat;
6241 unsigned long flags;
e315cd28
AC		 6242 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6243 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6244 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6245 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6246
bcc5b6d3
SK		 6247 if (IS_QLA82XX(ha))
6248 return PCI_ERS_RESULT_RECOVERED;
6249
14e660e6
SJ		 6250 spin_lock_irqsave(&ha->hardware_lock, flags);
6251 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6252 stat = RD_REG_DWORD(&reg->hccr);
6253 if (stat & HCCR_RISC_PAUSE)
6254 risc_paused = 1;
6255 } else if (IS_QLA23XX(ha)) {
6256 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6257 if (stat & HSR_RISC_PAUSED)
6258 risc_paused = 1;
6259 } else if (IS_FWI2_CAPABLE(ha)) {
6260 stat = RD_REG_DWORD(&reg24->host_status);
6261 if (stat & HSRX_RISC_PAUSED)
6262 risc_paused = 1;
6263 }
6264 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6265
6266 if (risc_paused) {
7c3df132
SK		 6267 ql_log(ql_log_info, base_vha, 0x9003,
6268 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6269 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6270
6271 return PCI_ERS_RESULT_NEED_RESET;
6272 } else
6273 return PCI_ERS_RESULT_RECOVERED;
6274}
6275
fa492630
SK		 6276static uint32_t
6277qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6278{
6279 uint32_t rval = QLA_FUNCTION_FAILED;
6280 uint32_t drv_active = 0;
6281 struct qla_hw_data *ha = base_vha->hw;
6282 int fn;
6283 struct pci_dev *other_pdev = NULL;
6284
7c3df132
SK		 6285 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6286 "Entered %s.\n", __func__);
a5b36321
LC		 6287
6288 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6289
6290 if (base_vha->flags.online) {
6291 /* Abort all outstanding commands,
6292 * so as to be requeued later */
6293 qla2x00_abort_isp_cleanup(base_vha);
6294 }
6295
6296
6297 fn = PCI_FUNC(ha->pdev->devfn);
6298 while (fn > 0) {
6299 fn--;
7c3df132
SK		 6300 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6301 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6302 other_pdev =
6303 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6304 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6305 fn));
6306
6307 if (!other_pdev)
6308 continue;
6309 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6310 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6311 "Found PCI func available and enable at 0x%x.\n",
6312 fn);
a5b36321
LC		 6313 pci_dev_put(other_pdev);
6314 break;
6315 }
6316 pci_dev_put(other_pdev);
6317 }
6318
6319 if (!fn) {
6320 /* Reset owner */
7c3df132
SK		 6321 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6322 "This devfn is reset owner = 0x%x.\n",
6323 ha->pdev->devfn);
a5b36321
LC		 6324 qla82xx_idc_lock(ha);
6325
6326 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6327 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6328
6329 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6330 QLA82XX_IDC_VERSION);
6331
6332 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6333 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6334 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6335
6336 qla82xx_idc_unlock(ha);
6337 /* Reset if device is not already reset
6338 * drv_active would be 0 if a reset has already been done
6339 */
6340 if (drv_active)
6341 rval = qla82xx_start_firmware(base_vha);
6342 else
6343 rval = QLA_SUCCESS;
6344 qla82xx_idc_lock(ha);
6345
6346 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6347 ql_log(ql_log_info, base_vha, 0x900b,
6348 "HW State: FAILED.\n");
a5b36321
LC		 6349 qla82xx_clear_drv_active(ha);
6350 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6351 QLA8XXX_DEV_FAILED);
a5b36321 6352 } else {
7c3df132
SK		 6353 ql_log(ql_log_info, base_vha, 0x900c,
6354 "HW State: READY.\n");
a5b36321 6355 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6356 QLA8XXX_DEV_READY);
a5b36321 6357 qla82xx_idc_unlock(ha);
7190575f 6358 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6359 rval = qla82xx_restart_isp(base_vha);
6360 qla82xx_idc_lock(ha);
6361 /* Clear driver state register */
6362 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6363 qla82xx_set_drv_active(base_vha);
6364 }
6365 qla82xx_idc_unlock(ha);
6366 } else {
7c3df132
SK		 6367 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6368 "This devfn is not reset owner = 0x%x.\n",
6369 ha->pdev->devfn);
a5b36321 6370 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6371 QLA8XXX_DEV_READY)) {
7190575f 6372 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6373 rval = qla82xx_restart_isp(base_vha);
6374 qla82xx_idc_lock(ha);
6375 qla82xx_set_drv_active(base_vha);
6376 qla82xx_idc_unlock(ha);
6377 }
6378 }
6379 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6380
6381 return rval;
6382}
6383
14e660e6
SJ		 6384static pci_ers_result_t
6385qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6386{
6387 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6388 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6389 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6390 struct rsp_que *rsp;
6391 int rc, retries = 10;
09483916 6392
7c3df132
SK		 6393 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6394 "Slot Reset.\n");
85880801 6395
90a86fc0
JC		 6396 /* Workaround: qla2xxx driver which access hardware earlier
6397 * needs error state to be pci_channel_io_online.
6398 * Otherwise mailbox command timesout.
6399 */
6400 pdev->error_state = pci_channel_io_normal;
6401
6402 pci_restore_state(pdev);
6403
8c1496bd
RL		 6404 /* pci_restore_state() clears the saved_state flag of the device
6405 * save restored state which resets saved_state flag
6406 */
6407 pci_save_state(pdev);
6408
09483916
BH		 6409 if (ha->mem_only)
6410 rc = pci_enable_device_mem(pdev);
6411 else
6412 rc = pci_enable_device(pdev);
14e660e6 6413
09483916 6414 if (rc) {
7c3df132 6415 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6416 "Can't re-enable PCI device after reset.\n");
a5b36321 6417 goto exit_slot_reset;
14e660e6 6418 }
14e660e6 6419
90a86fc0
JC		 6420 rsp = ha->rsp_q_map[0];
6421 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6422 goto exit_slot_reset;
90a86fc0 6423
e315cd28 6424 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6425 goto exit_slot_reset;
6426
6427 if (IS_QLA82XX(ha)) {
6428 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6429 ret = PCI_ERS_RESULT_RECOVERED;
6430 goto exit_slot_reset;
6431 } else
6432 goto exit_slot_reset;
6433 }
14e660e6 6434
90a86fc0
JC		 6435 while (ha->flags.mbox_busy && retries--)
6436 msleep(1000);
85880801 6437
e315cd28 6438 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6439 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6440 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6441 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6442
90a86fc0 6443
a5b36321 6444exit_slot_reset:
7c3df132
SK		 6445 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6446 "slot_reset return %x.\n", ret);
85880801 6447
14e660e6
SJ		 6448 return ret;
6449}
6450
6451static void
6452qla2xxx_pci_resume(struct pci_dev *pdev)
6453{
e315cd28
AC		 6454 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6455 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6456 int ret;
6457
7c3df132
SK		 6458 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6459 "pci_resume.\n");
85880801 6460
e315cd28 6461 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6462 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6463 ql_log(ql_log_fatal, base_vha, 0x9002,
6464 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6465 }
85880801 6466
3e46f031
LC		 6467 pci_cleanup_aer_uncorrect_error_status(pdev);
6468
85880801 6469 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6470}
6471
2d5a4c34
HM		 6472static void
6473qla83xx_disable_laser(scsi_qla_host_t *vha)
6474{
6475 uint32_t reg, data, fn;
6476 struct qla_hw_data *ha = vha->hw;
6477 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6478
6479 /* pci func #/port # */
6480 ql_dbg(ql_dbg_init, vha, 0x004b,
6481 "Disabling Laser for hba: %p\n", vha);
6482
6483 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6484 (BIT_15|BIT_14|BIT_13|BIT_12));
6485
6486 fn = (fn >> 12);
6487
6488 if (fn & 1)
6489 reg = PORT_1_2031;
6490 else
6491 reg = PORT_0_2031;
6492
6493 data = LASER_OFF_2031;
6494
6495 qla83xx_wr_reg(vha, reg, data);
6496}
6497
5601236b
MH		 6498static int qla2xxx_map_queues(struct Scsi_Host *shost)
6499{
6500 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6501
6502 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6503}
6504
a55b2d21 6505static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6506 .error_detected = qla2xxx_pci_error_detected,
6507 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6508 .slot_reset = qla2xxx_pci_slot_reset,
6509 .resume = qla2xxx_pci_resume,
6510};
6511
5433383e 6512static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6513 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6514 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6515 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6516 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6517 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6518 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6519 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6520 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6521 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6522 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6523 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6524 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6525 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6526 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6527 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6528 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6529 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6530 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6531 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6532 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6533 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6534 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6535 { 0 },
6536};
6537MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6538
fca29703 6539static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6540 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6541 .driver = {
6542 .owner = THIS_MODULE,
6543 },
fca29703 6544 .id_table = qla2xxx_pci_tbl,
7ee61397 6545 .probe = qla2x00_probe_one,
4c993f76 6546 .remove = qla2x00_remove_one,
e30d1756 6547 .shutdown = qla2x00_shutdown,
14e660e6 6548 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6549};
6550
75ef9de1 6551static const struct file_operations apidev_fops = {
6a03b4cd 6552 .owner = THIS_MODULE,
6038f373 6553 .llseek = noop_llseek,
6a03b4cd
HZ		 6554};
6555
1da177e4
LT		 6556/**
6557 * qla2x00_module_init - Module initialization.
6558 **/
6559static int __init
6560qla2x00_module_init(void)
6561{
fca29703
AV		 6562 int ret = 0;
6563
1da177e4 6564 /* Allocate cache for SRBs. */
354d6b21 6565 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6566 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6567 if (srb_cachep == NULL) {
7c3df132
SK		 6568 ql_log(ql_log_fatal, NULL, 0x0001,
6569 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6570 return -ENOMEM;
6571 }
6572
2d70c103
NB		 6573 /* Initialize target kmem_cache and mem_pools */
6574 ret = qlt_init();
6575 if (ret < 0) {
6576 kmem_cache_destroy(srb_cachep);
6577 return ret;
6578 } else if (ret > 0) {
6579 /*
6580 * If initiator mode is explictly disabled by qlt_init(),
6581 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6582 * performing scsi_scan_target() during LOOP UP event.
6583 */
6584 qla2xxx_transport_functions.disable_target_scan = 1;
6585 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6586 }
6587
1da177e4
LT		 6588 /* Derive version string. */
6589 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6590 if (ql2xextended_error_logging)
0181944f
AV		 6591 strcat(qla2x00_version_str, "-debug");
6592
1c97a12a
AV		 6593 qla2xxx_transport_template =
6594 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6595 if (!qla2xxx_transport_template) {
6596 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6597 ql_log(ql_log_fatal, NULL, 0x0002,
6598 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6599 qlt_exit();
1da177e4 6600 return -ENODEV;
2c3dfe3f 6601 }
6a03b4cd
HZ		 6602
6603 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6604 if (apidev_major < 0) {
7c3df132
SK		 6605 ql_log(ql_log_fatal, NULL, 0x0003,
6606 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6607 }
6608
2c3dfe3f
SJ		 6609 qla2xxx_transport_vport_template =
6610 fc_attach_transport(&qla2xxx_transport_vport_functions);
6611 if (!qla2xxx_transport_vport_template) {
6612 kmem_cache_destroy(srb_cachep);
2d70c103 6613 qlt_exit();
2c3dfe3f 6614 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6615 ql_log(ql_log_fatal, NULL, 0x0004,
6616 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6617 return -ENODEV;
2c3dfe3f 6618 }
7c3df132
SK		 6619 ql_log(ql_log_info, NULL, 0x0005,
6620 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6621 qla2x00_version_str);
7ee61397 6622 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6623 if (ret) {
6624 kmem_cache_destroy(srb_cachep);
2d70c103 6625 qlt_exit();
fca29703 6626 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6627 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6628 ql_log(ql_log_fatal, NULL, 0x0006,
6629 "pci_register_driver failed...ret=%d Failing load!.\n",
6630 ret);
fca29703
AV		 6631 }
6632 return ret;
1da177e4
LT		 6633}
6634
6635/**
6636 * qla2x00_module_exit - Module cleanup.
6637 **/
6638static void __exit
6639qla2x00_module_exit(void)
6640{
6a03b4cd 6641 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6642 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6643 qla2x00_release_firmware();
354d6b21 6644 kmem_cache_destroy(srb_cachep);
2d70c103 6645 qlt_exit();
a9083016
GM		 6646 if (ctx_cachep)
6647 kmem_cache_destroy(ctx_cachep);
1da177e4 6648 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6649 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6650}
6651
6652module_init(qla2x00_module_init);
6653module_exit(qla2x00_module_exit);
6654
6655MODULE_AUTHOR("QLogic Corporation");
6656MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6657MODULE_LICENSE("GPL");
6658MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6659MODULE_FIRMWARE(FW_FILE_ISP21XX);
6660MODULE_FIRMWARE(FW_FILE_ISP22XX);
6661MODULE_FIRMWARE(FW_FILE_ISP2300);
6662MODULE_FIRMWARE(FW_FILE_ISP2322);
6663MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6664MODULE_FIRMWARE(FW_FILE_ISP25XX);
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