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scsi: lpfc: prevent potential null pointer dereference
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
41dc529a
QT		 240int ql2xmvasynctoatio = 1;
241module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
242MODULE_PARM_DESC(ql2xmvasynctoatio,
243 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
244 "0 (Default). Do not move IOCBs"
245 "1 - Move IOCBs.");
246
1da177e4 247/*
fa2a1ce5 248 * SCSI host template entry points
1da177e4
LT		 249 */
250static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 251static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 252static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
253static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 254static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 255static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 256static int qla2xxx_eh_abort(struct scsi_cmnd *);
257static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 258static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 259static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
260static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 261
1a2fbf18 262static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 263static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 264static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 265static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 266
a5326f86 267struct scsi_host_template qla2xxx_driver_template = {
1da177e4 268 .module = THIS_MODULE,
cb63067a 269 .name = QLA2XXX_DRIVER_NAME,
a5326f86 270 .queuecommand = qla2xxx_queuecommand,
fca29703 271
b6a05c82 272 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 273 .eh_abort_handler = qla2xxx_eh_abort,
274 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 275 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 276 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
277 .eh_host_reset_handler = qla2xxx_eh_host_reset,
278
279 .slave_configure = qla2xxx_slave_configure,
280
281 .slave_alloc = qla2xxx_slave_alloc,
282 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 283 .scan_finished = qla2xxx_scan_finished,
284 .scan_start = qla2xxx_scan_start,
db5ed4df 285 .change_queue_depth = scsi_change_queue_depth,
5601236b 286 .map_queues = qla2xxx_map_queues,
fca29703
AV		 287 .this_id = -1,
288 .cmd_per_lun = 3,
289 .use_clustering = ENABLE_CLUSTERING,
290 .sg_tablesize = SG_ALL,
291
292 .max_sectors = 0xFFFF,
afb046e2 293 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 294
295 .supported_mode = MODE_INITIATOR,
c40ecc12 296 .track_queue_depth = 1,
fca29703
AV		 297};
298
1da177e4 299static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 300struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 301
1da177e4
LT		 302/* TODO Convert to inlines
303 *
304 * Timer routines
305 */
1da177e4 306
2c3dfe3f 307__inline__ void
e315cd28 308qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 309{
e315cd28
AC		 310 init_timer(&vha->timer);
311 vha->timer.expires = jiffies + interval * HZ;
312 vha->timer.data = (unsigned long)vha;
313 vha->timer.function = (void (*)(unsigned long))func;
314 add_timer(&vha->timer);
315 vha->timer_active = 1;
1da177e4
LT		 316}
317
318static inline void
e315cd28 319qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 320{
a9083016 321 /* Currently used for 82XX only. */
7c3df132
SK		 322 if (vha->device_flags & DFLG_DEV_FAILED) {
323 ql_dbg(ql_dbg_timer, vha, 0x600d,
324 "Device in a failed state, returning.\n");
a9083016 325 return;
7c3df132 326 }
a9083016 327
e315cd28 328 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 329}
330
a824ebb3 331static __inline__ void
e315cd28 332qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 333{
e315cd28
AC		 334 del_timer_sync(&vha->timer);
335 vha->timer_active = 0;
1da177e4
LT		 336}
337
1da177e4
LT		 338static int qla2x00_do_dpc(void *data);
339
340static void qla2x00_rst_aen(scsi_qla_host_t *);
341
73208dfd
AC		 342static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
343 struct req_que **, struct rsp_que **);
e30d1756 344static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 345static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 346int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
347 struct qla_qpair *qpair);
1da177e4 348
1da177e4 349/* -------------------------------------------------------------------------- */
9a347ff4
CD		 350static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
351 struct rsp_que *rsp)
73208dfd 352{
7c3df132 353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 354 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 355 GFP_KERNEL);
356 if (!ha->req_q_map) {
7c3df132
SK		 357 ql_log(ql_log_fatal, vha, 0x003b,
358 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 359 goto fail_req_map;
360 }
361
2afa19a9 362 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 363 GFP_KERNEL);
364 if (!ha->rsp_q_map) {
7c3df132
SK		 365 ql_log(ql_log_fatal, vha, 0x003c,
366 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 367 goto fail_rsp_map;
368 }
d7459527
MH		 369
370 if (ql2xmqsupport && ha->max_qpairs) {
371 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
372 GFP_KERNEL);
373 if (!ha->queue_pair_map) {
374 ql_log(ql_log_fatal, vha, 0x0180,
375 "Unable to allocate memory for queue pair ptrs.\n");
376 goto fail_qpair_map;
377 }
378 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
379 if (ha->base_qpair == NULL) {
380 ql_log(ql_log_warn, vha, 0x0182,
381 "Failed to allocate base queue pair memory.\n");
382 goto fail_base_qpair;
383 }
384 ha->base_qpair->req = req;
385 ha->base_qpair->rsp = rsp;
386 }
387
9a347ff4
CD		 388 /*
389 * Make sure we record at least the request and response queue zero in
390 * case we need to free them if part of the probe fails.
391 */
392 ha->rsp_q_map[0] = rsp;
393 ha->req_q_map[0] = req;
73208dfd
AC		 394 set_bit(0, ha->rsp_qid_map);
395 set_bit(0, ha->req_qid_map);
396 return 1;
397
d7459527
MH		 398fail_base_qpair:
399 kfree(ha->queue_pair_map);
400fail_qpair_map:
401 kfree(ha->rsp_q_map);
402 ha->rsp_q_map = NULL;
73208dfd
AC		 403fail_rsp_map:
404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
406fail_req_map:
407 return -ENOMEM;
408}
409
2afa19a9 410static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 411{
8ae6d9c7
GM		 412 if (IS_QLAFX00(ha)) {
413 if (req && req->ring_fx00)
414 dma_free_coherent(&ha->pdev->dev,
415 (req->length_fx00 + 1) * sizeof(request_t),
416 req->ring_fx00, req->dma_fx00);
417 } else if (req && req->ring)
73208dfd
AC		 418 dma_free_coherent(&ha->pdev->dev,
419 (req->length + 1) * sizeof(request_t),
420 req->ring, req->dma);
421
8d93f550
CD		 422 if (req)
423 kfree(req->outstanding_cmds);
424
73208dfd 425 kfree(req);
73208dfd
AC		 426}
427
2afa19a9
AC		 428static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
429{
8ae6d9c7
GM		 430 if (IS_QLAFX00(ha)) {
431 if (rsp && rsp->ring)
432 dma_free_coherent(&ha->pdev->dev,
433 (rsp->length_fx00 + 1) * sizeof(request_t),
434 rsp->ring_fx00, rsp->dma_fx00);
435 } else if (rsp && rsp->ring) {
2afa19a9
AC		 436 dma_free_coherent(&ha->pdev->dev,
437 (rsp->length + 1) * sizeof(response_t),
438 rsp->ring, rsp->dma);
8ae6d9c7 439 }
2afa19a9 440 kfree(rsp);
2afa19a9
AC		 441}
442
73208dfd
AC		 443static void qla2x00_free_queues(struct qla_hw_data *ha)
444{
445 struct req_que *req;
446 struct rsp_que *rsp;
447 int cnt;
093df737 448 unsigned long flags;
73208dfd 449
093df737 450 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 451 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 452 if (!test_bit(cnt, ha->req_qid_map))
453 continue;
454
73208dfd 455 req = ha->req_q_map[cnt];
093df737
QT		 456 clear_bit(cnt, ha->req_qid_map);
457 ha->req_q_map[cnt] = NULL;
458
459 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 460 qla2x00_free_req_que(ha, req);
093df737 461 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 462 }
093df737
QT		 463 spin_unlock_irqrestore(&ha->hardware_lock, flags);
464
73208dfd
AC		 465 kfree(ha->req_q_map);
466 ha->req_q_map = NULL;
2afa19a9 467
093df737
QT		 468
469 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 470 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 471 if (!test_bit(cnt, ha->rsp_qid_map))
472 continue;
473
2afa19a9 474 rsp = ha->rsp_q_map[cnt];
c3c42394 475 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 476 ha->rsp_q_map[cnt] = NULL;
477 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 478 qla2x00_free_rsp_que(ha, rsp);
093df737 479 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 480 }
093df737
QT		 481 spin_unlock_irqrestore(&ha->hardware_lock, flags);
482
2afa19a9
AC		 483 kfree(ha->rsp_q_map);
484 ha->rsp_q_map = NULL;
73208dfd
AC		 485}
486
1da177e4 487static char *
e315cd28 488qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 489{
e315cd28 490 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 491 static char *pci_bus_modes[] = {
492 "33", "66", "100", "133",
493 };
494 uint16_t pci_bus;
495
496 strcpy(str, "PCI");
497 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
498 if (pci_bus) {
499 strcat(str, "-X (");
500 strcat(str, pci_bus_modes[pci_bus]);
501 } else {
502 pci_bus = (ha->pci_attr & BIT_8) >> 8;
503 strcat(str, " (");
504 strcat(str, pci_bus_modes[pci_bus]);
505 }
506 strcat(str, " MHz)");
507
508 return (str);
509}
510
fca29703 511static char *
e315cd28 512qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 513{
514 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 515 struct qla_hw_data *ha = vha->hw;
fca29703 516 uint32_t pci_bus;
fca29703 517
62a276f8 518 if (pci_is_pcie(ha->pdev)) {
fca29703 519 char lwstr[6];
62a276f8 520 uint32_t lstat, lspeed, lwidth;
fca29703 521
62a276f8
BH		 522 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
523 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
524 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 525
526 strcpy(str, "PCIe (");
49300af7
SK		 527 switch (lspeed) {
528 case 1:
c87a0d8c 529 strcat(str, "2.5GT/s ");
49300af7
SK		 530 break;
531 case 2:
c87a0d8c 532 strcat(str, "5.0GT/s ");
49300af7
SK		 533 break;
534 case 3:
535 strcat(str, "8.0GT/s ");
536 break;
537 default:
fca29703 538 strcat(str, "<unknown> ");
49300af7
SK		 539 break;
540 }
fca29703
AV		 541 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
542 strcat(str, lwstr);
543
544 return str;
545 }
546
547 strcpy(str, "PCI");
548 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
549 if (pci_bus == 0 || pci_bus == 8) {
550 strcat(str, " (");
551 strcat(str, pci_bus_modes[pci_bus >> 3]);
552 } else {
553 strcat(str, "-X ");
554 if (pci_bus & BIT_2)
555 strcat(str, "Mode 2");
556 else
557 strcat(str, "Mode 1");
558 strcat(str, " (");
559 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
560 }
561 strcat(str, " MHz)");
562
563 return str;
564}
565
e5f82ab8 566static char *
df57caba 567qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 568{
569 char un_str[10];
e315cd28 570 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 571
df57caba
HM		 572 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
573 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 574
575 if (ha->fw_attributes & BIT_9) {
576 strcat(str, "FLX");
577 return (str);
578 }
579
580 switch (ha->fw_attributes & 0xFF) {
581 case 0x7:
582 strcat(str, "EF");
583 break;
584 case 0x17:
585 strcat(str, "TP");
586 break;
587 case 0x37:
588 strcat(str, "IP");
589 break;
590 case 0x77:
591 strcat(str, "VI");
592 break;
593 default:
594 sprintf(un_str, "(%x)", ha->fw_attributes);
595 strcat(str, un_str);
596 break;
597 }
598 if (ha->fw_attributes & 0x100)
599 strcat(str, "X");
600
601 return (str);
602}
603
e5f82ab8 604static char *
df57caba 605qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 606{
e315cd28 607 struct qla_hw_data *ha = vha->hw;
f0883ac6 608
df57caba 609 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 610 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 611 return str;
fca29703
AV		 612}
613
9ba56b95 614void
25ff6af1 615qla2x00_sp_free_dma(void *ptr)
fca29703 616{
25ff6af1
JC		 617 srb_t *sp = ptr;
618 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 619 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 620 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 621
9ba56b95
GM		 622 if (sp->flags & SRB_DMA_VALID) {
623 scsi_dma_unmap(cmd);
624 sp->flags &= ~SRB_DMA_VALID;
7c3df132 625 }
fca29703 626
9ba56b95
GM		 627 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
628 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
629 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
630 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
631 }
632
d5ff0eed
JC		 633 if (!ctx)
634 goto end;
635
9ba56b95
GM		 636 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
637 /* List assured to be having elements */
d5ff0eed 638 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 639 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
640 }
641
642 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 643 struct crc_context *ctx0 = ctx;
644
645 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 646 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
647 }
648
649 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 650 struct ct6_dsd *ctx1 = ctx;
fca29703 651
9ba56b95 652 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 653 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 654 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
655 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
656 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
657 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 658 }
659
d5ff0eed 660end:
9ba56b95 661 CMD_SP(cmd) = NULL;
25ff6af1 662 qla2x00_rel_sp(sp);
9ba56b95
GM		 663}
664
d7459527 665void
25ff6af1 666qla2x00_sp_compl(void *ptr, int res)
9ba56b95 667{
25ff6af1 668 srb_t *sp = ptr;
9ba56b95
GM		 669 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
670
671 cmd->result = res;
672
673 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 674 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 675 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
676 sp, GET_CMD_SP(sp));
677 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 678 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 679 return;
680 }
681 if (!atomic_dec_and_test(&sp->ref_count))
682 return;
683
25ff6af1 684 qla2x00_sp_free_dma(sp);
9ba56b95 685 cmd->scsi_done(cmd);
fca29703
AV		 686}
687
d7459527 688void
25ff6af1 689qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 690{
691 srb_t *sp = (srb_t *)ptr;
692 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
693 struct qla_hw_data *ha = sp->fcport->vha->hw;
694 void *ctx = GET_CMD_CTX_SP(sp);
695
696 if (sp->flags & SRB_DMA_VALID) {
697 scsi_dma_unmap(cmd);
698 sp->flags &= ~SRB_DMA_VALID;
699 }
700
701 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
702 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
703 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
704 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
705 }
706
d5ff0eed
JC		 707 if (!ctx)
708 goto end;
709
d7459527
MH		 710 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
711 /* List assured to be having elements */
d5ff0eed 712 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 713 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
714 }
715
716 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 717 struct crc_context *ctx0 = ctx;
718
719 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 720 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
721 }
722
723 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 724 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 725 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
726 ctx1->fcp_cmnd_dma);
727 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
728 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
729 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
730 mempool_free(ctx1, ha->ctx_mempool);
731 }
d5ff0eed 732end:
d7459527
MH		 733 CMD_SP(cmd) = NULL;
734 qla2xxx_rel_qpair_sp(sp->qpair, sp);
735}
736
737void
25ff6af1 738qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 739{
25ff6af1 740 srb_t *sp = ptr;
d7459527
MH		 741 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
742
743 cmd->result = res;
744
745 if (atomic_read(&sp->ref_count) == 0) {
746 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
747 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
748 sp, GET_CMD_SP(sp));
749 if (ql2xextended_error_logging & ql_dbg_io)
750 WARN_ON(atomic_read(&sp->ref_count) == 0);
751 return;
752 }
753 if (!atomic_dec_and_test(&sp->ref_count))
754 return;
755
25ff6af1 756 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 757 cmd->scsi_done(cmd);
758}
759
8ae6d9c7
GM		 760/* If we are SP1 here, we need to still take and release the host_lock as SP1
761 * does not have the changes necessary to avoid taking host->host_lock.
762 */
1da177e4 763static int
f5e3e40b 764qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 765{
134ae078 766 scsi_qla_host_t *vha = shost_priv(host);
fca29703 767 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 768 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 769 struct qla_hw_data *ha = vha->hw;
770 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 771 srb_t *sp;
772 int rval;
5601236b
MH		 773 struct qla_qpair *qpair = NULL;
774 uint32_t tag;
775 uint16_t hwq;
fca29703 776
04dfaa53
MFO		 777 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
778 cmd->result = DID_NO_CONNECT << 16;
779 goto qc24_fail_command;
780 }
781
5601236b
MH		 782 if (ha->mqenable) {
783 if (shost_use_blk_mq(vha->host)) {
784 tag = blk_mq_unique_tag(cmd->request);
785 hwq = blk_mq_unique_tag_to_hwq(tag);
786 qpair = ha->queue_pair_map[hwq];
787 } else if (vha->vp_idx && vha->qpair) {
788 qpair = vha->qpair;
789 }
790
791 if (qpair)
792 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 793 }
794
85880801 795 if (ha->flags.eeh_busy) {
7c3df132 796 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 797 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 798 "PCI Channel IO permanent failure, exiting "
799 "cmd=%p.\n", cmd);
b9b12f73 800 cmd->result = DID_NO_CONNECT << 16;
7c3df132 801 } else {
5f28d2d7 802 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 803 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 804 cmd->result = DID_REQUEUE << 16;
7c3df132 805 }
14e660e6
SJ		 806 goto qc24_fail_command;
807 }
808
19a7b4ae
JSEC		 809 rval = fc_remote_port_chkready(rport);
810 if (rval) {
811 cmd->result = rval;
5f28d2d7 812 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 813 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
814 cmd, rval);
fca29703
AV		 815 goto qc24_fail_command;
816 }
817
bad75002
AE		 818 if (!vha->flags.difdix_supported &&
819 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 820 ql_dbg(ql_dbg_io, vha, 0x3004,
821 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
822 cmd);
bad75002
AE		 823 cmd->result = DID_NO_CONNECT << 16;
824 goto qc24_fail_command;
825 }
aa651be8
CD		 826
827 if (!fcport) {
828 cmd->result = DID_NO_CONNECT << 16;
829 goto qc24_fail_command;
830 }
831
fca29703
AV		 832 if (atomic_read(&fcport->state) != FCS_ONLINE) {
833 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 834 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 835 ql_dbg(ql_dbg_io, vha, 0x3005,
836 "Returning DNC, fcport_state=%d loop_state=%d.\n",
837 atomic_read(&fcport->state),
838 atomic_read(&base_vha->loop_state));
fca29703
AV		 839 cmd->result = DID_NO_CONNECT << 16;
840 goto qc24_fail_command;
841 }
7b594131 842 goto qc24_target_busy;
fca29703
AV		 843 }
844
e05fe292
CD		 845 /*
846 * Return target busy if we've received a non-zero retry_delay_timer
847 * in a FCP_RSP.
848 */
975f7d46
BP		 849 if (fcport->retry_delay_timestamp == 0) {
850 /* retry delay not set */
851 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 852 fcport->retry_delay_timestamp = 0;
853 else
854 goto qc24_target_busy;
855
b00ee7d7 856 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 857 if (!sp)
f5e3e40b 858 goto qc24_host_busy;
fca29703 859
9ba56b95
GM		 860 sp->u.scmd.cmd = cmd;
861 sp->type = SRB_SCSI_CMD;
862 atomic_set(&sp->ref_count, 1);
863 CMD_SP(cmd) = (void *)sp;
864 sp->free = qla2x00_sp_free_dma;
865 sp->done = qla2x00_sp_compl;
866
e315cd28 867 rval = ha->isp_ops->start_scsi(sp);
7c3df132 868 if (rval != QLA_SUCCESS) {
53016ed3 869 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 870 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 871 goto qc24_host_busy_free_sp;
7c3df132 872 }
fca29703 873
fca29703
AV		 874 return 0;
875
876qc24_host_busy_free_sp:
25ff6af1 877 qla2x00_sp_free_dma(sp);
fca29703 878
f5e3e40b 879qc24_host_busy:
fca29703
AV		 880 return SCSI_MLQUEUE_HOST_BUSY;
881
7b594131
MC		 882qc24_target_busy:
883 return SCSI_MLQUEUE_TARGET_BUSY;
884
fca29703 885qc24_fail_command:
f5e3e40b 886 cmd->scsi_done(cmd);
fca29703
AV		 887
888 return 0;
889}
890
d7459527
MH		 891/* For MQ supported I/O */
892int
893qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
894 struct qla_qpair *qpair)
895{
896 scsi_qla_host_t *vha = shost_priv(host);
897 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
898 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
899 struct qla_hw_data *ha = vha->hw;
900 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
901 srb_t *sp;
902 int rval;
903
904 rval = fc_remote_port_chkready(rport);
905 if (rval) {
906 cmd->result = rval;
907 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
908 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
909 cmd, rval);
910 goto qc24_fail_command;
911 }
912
913 if (!fcport) {
914 cmd->result = DID_NO_CONNECT << 16;
915 goto qc24_fail_command;
916 }
917
918 if (atomic_read(&fcport->state) != FCS_ONLINE) {
919 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
920 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
921 ql_dbg(ql_dbg_io, vha, 0x3077,
922 "Returning DNC, fcport_state=%d loop_state=%d.\n",
923 atomic_read(&fcport->state),
924 atomic_read(&base_vha->loop_state));
925 cmd->result = DID_NO_CONNECT << 16;
926 goto qc24_fail_command;
927 }
928 goto qc24_target_busy;
929 }
930
931 /*
932 * Return target busy if we've received a non-zero retry_delay_timer
933 * in a FCP_RSP.
934 */
935 if (fcport->retry_delay_timestamp == 0) {
936 /* retry delay not set */
937 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
938 fcport->retry_delay_timestamp = 0;
939 else
940 goto qc24_target_busy;
941
942 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
943 if (!sp)
944 goto qc24_host_busy;
945
946 sp->u.scmd.cmd = cmd;
947 sp->type = SRB_SCSI_CMD;
948 atomic_set(&sp->ref_count, 1);
949 CMD_SP(cmd) = (void *)sp;
950 sp->free = qla2xxx_qpair_sp_free_dma;
951 sp->done = qla2xxx_qpair_sp_compl;
952 sp->qpair = qpair;
953
954 rval = ha->isp_ops->start_scsi_mq(sp);
955 if (rval != QLA_SUCCESS) {
956 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
957 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
958 if (rval == QLA_INTERFACE_ERROR)
959 goto qc24_fail_command;
960 goto qc24_host_busy_free_sp;
961 }
962
963 return 0;
964
965qc24_host_busy_free_sp:
25ff6af1 966 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 967
968qc24_host_busy:
969 return SCSI_MLQUEUE_HOST_BUSY;
970
971qc24_target_busy:
972 return SCSI_MLQUEUE_TARGET_BUSY;
973
974qc24_fail_command:
975 cmd->scsi_done(cmd);
976
977 return 0;
978}
979
1da177e4
LT		 980/*
981 * qla2x00_eh_wait_on_command
982 * Waits for the command to be returned by the Firmware for some
983 * max time.
984 *
985 * Input:
1da177e4 986 * cmd = Scsi Command to wait on.
1da177e4
LT		 987 *
988 * Return:
989 * Not Found : 0
990 * Found : 1
991 */
992static int
e315cd28 993qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 994{
fe74c71f 995#define ABORT_POLLING_PERIOD 1000
478c3b03 996#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 997 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 998 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
999 struct qla_hw_data *ha = vha->hw;
f4f051eb 1000 int ret = QLA_SUCCESS;
1da177e4 1001
85880801 1002 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1003 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1004 "Return:eh_wait.\n");
85880801
AV		 1005 return ret;
1006 }
1007
d970432c 1008 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1009 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1010 }
1011 if (CMD_SP(cmd))
1012 ret = QLA_FUNCTION_FAILED;
1da177e4 1013
f4f051eb 1014 return ret;
1da177e4
LT		 1015}
1016
1017/*
1018 * qla2x00_wait_for_hba_online
fa2a1ce5 1019 * Wait till the HBA is online after going through
1da177e4
LT		 1020 * <= MAX_RETRIES_OF_ISP_ABORT or
1021 * finally HBA is disabled ie marked offline
1022 *
1023 * Input:
1024 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1025 *
1026 * Note:
1da177e4
LT		 1027 * Does context switching-Release SPIN_LOCK
1028 * (if any) before calling this routine.
1029 *
1030 * Return:
1031 * Success (Adapter is online) : 0
1032 * Failed (Adapter is offline/disabled) : 1
1033 */
854165f4 1034int
e315cd28 1035qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1036{
fca29703
AV		 1037 int return_status;
1038 unsigned long wait_online;
e315cd28
AC		 1039 struct qla_hw_data *ha = vha->hw;
1040 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1041
fa2a1ce5 1042 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1043 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1044 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1045 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1046 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1047
1048 msleep(1000);
1049 }
e315cd28 1050 if (base_vha->flags.online)
fa2a1ce5 1051 return_status = QLA_SUCCESS;
1da177e4
LT		 1052 else
1053 return_status = QLA_FUNCTION_FAILED;
1054
1da177e4
LT		 1055 return (return_status);
1056}
1057
726b8548
QT		 1058static inline int test_fcport_count(scsi_qla_host_t *vha)
1059{
1060 struct qla_hw_data *ha = vha->hw;
1061 unsigned long flags;
1062 int res;
1063
1064 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1065 ql_dbg(ql_dbg_init, vha, 0xffff,
1066 "tgt %p, fcport_count=%d\n",
1067 vha, vha->fcport_count);
1068 res = (vha->fcport_count == 0);
1069 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1070
1071 return res;
1072}
1073
1074/*
1075 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1076 * it has dependency on UNLOADING flag to stop device discovery
1077 */
1078static void
1079qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1080{
1081 qla2x00_mark_all_devices_lost(vha, 0);
1082
1083 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1084}
1085
86fbee86 1086/*
638a1a01
SC		 1087 * qla2x00_wait_for_hba_ready
1088 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1089 *
1090 * Input:
1091 * ha - pointer to host adapter structure
1092 *
1093 * Note:
1094 * Does context switching-Release SPIN_LOCK
1095 * (if any) before calling this routine.
1096 *
86fbee86 1097 */
638a1a01
SC		 1098static void
1099qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1100{
86fbee86 1101 struct qla_hw_data *ha = vha->hw;
783e0dc4 1102 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1103
1d483901
DC		 1104 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1105 ha->flags.mbox_busy) ||
1106 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1107 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1108 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1109 break;
86fbee86 1110 msleep(1000);
783e0dc4 1111 }
86fbee86
LC		 1112}
1113
2533cf67
LC		 1114int
1115qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1116{
1117 int return_status;
1118 unsigned long wait_reset;
1119 struct qla_hw_data *ha = vha->hw;
1120 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1121
1122 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1123 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1124 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1125 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1126 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1127
1128 msleep(1000);
1129
1130 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1131 ha->flags.chip_reset_done)
1132 break;
1133 }
1134 if (ha->flags.chip_reset_done)
1135 return_status = QLA_SUCCESS;
1136 else
1137 return_status = QLA_FUNCTION_FAILED;
1138
1139 return return_status;
1140}
1141
083a469d
GM		 1142static void
1143sp_get(struct srb *sp)
1144{
1145 atomic_inc(&sp->ref_count);
1146}
1147
a465537a
SC		 1148#define ISP_REG_DISCONNECT 0xffffffffU
1149/**************************************************************************
1150* qla2x00_isp_reg_stat
1151*
1152* Description:
1153* Read the host status register of ISP before aborting the command.
1154*
1155* Input:
1156* ha = pointer to host adapter structure.
1157*
1158*
1159* Returns:
1160* Either true or false.
1161*
1162* Note: Return true if there is register disconnect.
1163**************************************************************************/
1164static inline
1165uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1166{
1167 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1168 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1169
bf6061b1
SC		 1170 if (IS_P3P_TYPE(ha))
1171 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1172 else
1173 return ((RD_REG_DWORD(&reg->host_status)) ==
1174 ISP_REG_DISCONNECT);
a465537a
SC		 1175}
1176
1da177e4
LT		 1177/**************************************************************************
1178* qla2xxx_eh_abort
1179*
1180* Description:
1181* The abort function will abort the specified command.
1182*
1183* Input:
1184* cmd = Linux SCSI command packet to be aborted.
1185*
1186* Returns:
1187* Either SUCCESS or FAILED.
1188*
1189* Note:
2ea00202 1190* Only return FAILED if command not returned by firmware.
1da177e4 1191**************************************************************************/
e5f82ab8 1192static int
1da177e4
LT		 1193qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1194{
e315cd28 1195 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1196 srb_t *sp;
4e98d3b8 1197 int ret;
9cb78c16
HR		 1198 unsigned int id;
1199 uint64_t lun;
18e144d3 1200 unsigned long flags;
f934c9d0 1201 int rval, wait = 0;
e315cd28 1202 struct qla_hw_data *ha = vha->hw;
1da177e4 1203
a465537a
SC		 1204 if (qla2x00_isp_reg_stat(ha)) {
1205 ql_log(ql_log_info, vha, 0x8042,
1206 "PCI/Register disconnect, exiting.\n");
1207 return FAILED;
1208 }
f4f051eb 1209 if (!CMD_SP(cmd))
2ea00202 1210 return SUCCESS;
1da177e4 1211
4e98d3b8
AV		 1212 ret = fc_block_scsi_eh(cmd);
1213 if (ret != 0)
1214 return ret;
1215 ret = SUCCESS;
1216
f4f051eb
AV		 1217 id = cmd->device->id;
1218 lun = cmd->device->lun;
1da177e4 1219
e315cd28 1220 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1221 sp = (srb_t *) CMD_SP(cmd);
1222 if (!sp) {
1223 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1224 return SUCCESS;
1225 }
1da177e4 1226
7c3df132 1227 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1228 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1229 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1230
170babc3
MC		 1231 /* Get a reference to the sp and drop the lock.*/
1232 sp_get(sp);
083a469d 1233
e315cd28 1234 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1235 rval = ha->isp_ops->abort_command(sp);
1236 if (rval) {
96219424 1237 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1238 ret = SUCCESS;
96219424 1239 else
f934c9d0
CD		 1240 ret = FAILED;
1241
7c3df132 1242 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1243 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1244 } else {
7c3df132 1245 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1246 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1247 wait = 1;
1248 }
75942064
SK		 1249
1250 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1251 sp->done(sp, 0);
75942064 1252 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1253
bc91ade9
CD		 1254 /* Did the command return during mailbox execution? */
1255 if (ret == FAILED && !CMD_SP(cmd))
1256 ret = SUCCESS;
1257
f4f051eb 1258 /* Wait for the command to be returned. */
2ea00202 1259 if (wait) {
e315cd28 1260 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1261 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1262 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1263 ret = FAILED;
f4f051eb 1264 }
1da177e4 1265 }
1da177e4 1266
7c3df132 1267 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1268 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1269 vha->host_no, id, lun, wait, ret);
1da177e4 1270
f4f051eb
AV		 1271 return ret;
1272}
1da177e4 1273
4d78c973 1274int
e315cd28 1275qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1276 uint64_t l, enum nexus_wait_type type)
f4f051eb 1277{
17d98630 1278 int cnt, match, status;
18e144d3 1279 unsigned long flags;
e315cd28 1280 struct qla_hw_data *ha = vha->hw;
73208dfd 1281 struct req_que *req;
4d78c973 1282 srb_t *sp;
9ba56b95 1283 struct scsi_cmnd *cmd;
1da177e4 1284
523ec773 1285 status = QLA_SUCCESS;
17d98630 1286
e315cd28 1287 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1288 req = vha->req;
17d98630 1289 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1290 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1291 sp = req->outstanding_cmds[cnt];
1292 if (!sp)
523ec773 1293 continue;
9ba56b95 1294 if (sp->type != SRB_SCSI_CMD)
cf53b069 1295 continue;
25ff6af1 1296 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1297 continue;
1298 match = 0;
9ba56b95 1299 cmd = GET_CMD_SP(sp);
17d98630
AC		 1300 switch (type) {
1301 case WAIT_HOST:
1302 match = 1;
1303 break;
1304 case WAIT_TARGET:
9ba56b95 1305 match = cmd->device->id == t;
17d98630
AC		 1306 break;
1307 case WAIT_LUN:
9ba56b95
GM		 1308 match = (cmd->device->id == t &&
1309 cmd->device->lun == l);
17d98630 1310 break;
73208dfd 1311 }
17d98630
AC		 1312 if (!match)
1313 continue;
1314
1315 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1316 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1317 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1318 }
e315cd28 1319 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1320
1321 return status;
1da177e4
LT		 1322}
1323
523ec773
AV		 1324static char *reset_errors[] = {
1325 "HBA not online",
1326 "HBA not ready",
1327 "Task management failed",
1328 "Waiting for command completions",
1329};
1da177e4 1330
e5f82ab8 1331static int
523ec773 1332__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1333 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1334{
e315cd28 1335 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1336 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1337 int err;
1da177e4 1338
7c3df132 1339 if (!fcport) {
523ec773 1340 return FAILED;
7c3df132 1341 }
1da177e4 1342
4e98d3b8
AV		 1343 err = fc_block_scsi_eh(cmd);
1344 if (err != 0)
1345 return err;
1346
7c3df132 1347 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1348 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1349 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1350
523ec773 1351 err = 0;
7c3df132
SK		 1352 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1353 ql_log(ql_log_warn, vha, 0x800a,
1354 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1355 goto eh_reset_failed;
7c3df132 1356 }
523ec773 1357 err = 2;
2afa19a9 1358 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1359 != QLA_SUCCESS) {
1360 ql_log(ql_log_warn, vha, 0x800c,
1361 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1362 goto eh_reset_failed;
7c3df132 1363 }
523ec773 1364 err = 3;
e315cd28 1365 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1366 cmd->device->lun, type) != QLA_SUCCESS) {
1367 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1368 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1369 goto eh_reset_failed;
7c3df132 1370 }
523ec773 1371
7c3df132 1372 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1373 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1374 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1375
1376 return SUCCESS;
1377
4d78c973 1378eh_reset_failed:
7c3df132 1379 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1380 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1381 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1382 cmd);
523ec773
AV		 1383 return FAILED;
1384}
1da177e4 1385
523ec773
AV		 1386static int
1387qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1388{
e315cd28
AC		 1389 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1390 struct qla_hw_data *ha = vha->hw;
1da177e4 1391
a465537a
SC		 1392 if (qla2x00_isp_reg_stat(ha)) {
1393 ql_log(ql_log_info, vha, 0x803e,
1394 "PCI/Register disconnect, exiting.\n");
1395 return FAILED;
1396 }
1397
523ec773
AV		 1398 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1399 ha->isp_ops->lun_reset);
1da177e4
LT		 1400}
1401
1da177e4 1402static int
523ec773 1403qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1404{
e315cd28
AC		 1405 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1406 struct qla_hw_data *ha = vha->hw;
1da177e4 1407
a465537a
SC		 1408 if (qla2x00_isp_reg_stat(ha)) {
1409 ql_log(ql_log_info, vha, 0x803f,
1410 "PCI/Register disconnect, exiting.\n");
1411 return FAILED;
1412 }
1413
523ec773
AV		 1414 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1415 ha->isp_ops->target_reset);
1da177e4
LT		 1416}
1417
1da177e4
LT		 1418/**************************************************************************
1419* qla2xxx_eh_bus_reset
1420*
1421* Description:
1422* The bus reset function will reset the bus and abort any executing
1423* commands.
1424*
1425* Input:
1426* cmd = Linux SCSI command packet of the command that cause the
1427* bus reset.
1428*
1429* Returns:
1430* SUCCESS/FAILURE (defined as macro in scsi.h).
1431*
1432**************************************************************************/
e5f82ab8 1433static int
1da177e4
LT		 1434qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1435{
e315cd28 1436 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1437 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1438 int ret = FAILED;
9cb78c16
HR		 1439 unsigned int id;
1440 uint64_t lun;
a465537a
SC		 1441 struct qla_hw_data *ha = vha->hw;
1442
1443 if (qla2x00_isp_reg_stat(ha)) {
1444 ql_log(ql_log_info, vha, 0x8040,
1445 "PCI/Register disconnect, exiting.\n");
1446 return FAILED;
1447 }
f4f051eb 1448
f4f051eb
AV		 1449 id = cmd->device->id;
1450 lun = cmd->device->lun;
1da177e4 1451
7c3df132 1452 if (!fcport) {
f4f051eb 1453 return ret;
7c3df132 1454 }
1da177e4 1455
4e98d3b8
AV		 1456 ret = fc_block_scsi_eh(cmd);
1457 if (ret != 0)
1458 return ret;
1459 ret = FAILED;
1460
7c3df132 1461 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1462 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1463
e315cd28 1464 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1465 ql_log(ql_log_fatal, vha, 0x8013,
1466 "Wait for hba online failed board disabled.\n");
f4f051eb 1467 goto eh_bus_reset_done;
1da177e4
LT		 1468 }
1469
ad537689
SK		 1470 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1471 ret = SUCCESS;
1472
f4f051eb
AV		 1473 if (ret == FAILED)
1474 goto eh_bus_reset_done;
1da177e4 1475
9a41a62b 1476 /* Flush outstanding commands. */
4d78c973 1477 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1478 QLA_SUCCESS) {
1479 ql_log(ql_log_warn, vha, 0x8014,
1480 "Wait for pending commands failed.\n");
9a41a62b 1481 ret = FAILED;
7c3df132 1482 }
1da177e4 1483
f4f051eb 1484eh_bus_reset_done:
7c3df132 1485 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1486 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1487 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1488
f4f051eb 1489 return ret;
1da177e4
LT		 1490}
1491
1492/**************************************************************************
1493* qla2xxx_eh_host_reset
1494*
1495* Description:
1496* The reset function will reset the Adapter.
1497*
1498* Input:
1499* cmd = Linux SCSI command packet of the command that cause the
1500* adapter reset.
1501*
1502* Returns:
1503* Either SUCCESS or FAILED.
1504*
1505* Note:
1506**************************************************************************/
e5f82ab8 1507static int
1da177e4
LT		 1508qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1509{
e315cd28 1510 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1511 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1512 int ret = FAILED;
9cb78c16
HR		 1513 unsigned int id;
1514 uint64_t lun;
e315cd28 1515 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1516
a465537a
SC		 1517 if (qla2x00_isp_reg_stat(ha)) {
1518 ql_log(ql_log_info, vha, 0x8041,
1519 "PCI/Register disconnect, exiting.\n");
1520 schedule_work(&ha->board_disable);
1521 return SUCCESS;
1522 }
1523
f4f051eb
AV		 1524 id = cmd->device->id;
1525 lun = cmd->device->lun;
f4f051eb 1526
7c3df132 1527 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1528 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1529
63ee7072
CD		 1530 /*
1531 * No point in issuing another reset if one is active. Also do not
1532 * attempt a reset if we are updating flash.
1533 */
1534 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1535 goto eh_host_reset_lock;
1da177e4 1536
e315cd28
AC		 1537 if (vha != base_vha) {
1538 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1539 goto eh_host_reset_lock;
e315cd28 1540 } else {
7ec0effd 1541 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1542 if (!qla82xx_fcoe_ctx_reset(vha)) {
1543 /* Ctx reset success */
1544 ret = SUCCESS;
1545 goto eh_host_reset_lock;
1546 }
1547 /* fall thru if ctx reset failed */
1548 }
68ca949c
AC		 1549 if (ha->wq)
1550 flush_workqueue(ha->wq);
1551
e315cd28 1552 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1553 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1554 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1555 /* failed. schedule dpc to try */
1556 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1557
7c3df132
SK		 1558 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1559 ql_log(ql_log_warn, vha, 0x802a,
1560 "wait for hba online failed.\n");
e315cd28 1561 goto eh_host_reset_lock;
7c3df132 1562 }
e315cd28
AC		 1563 }
1564 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1565 }
1da177e4 1566
e315cd28 1567 /* Waiting for command to be returned to OS.*/
4d78c973 1568 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1569 QLA_SUCCESS)
f4f051eb 1570 ret = SUCCESS;
1da177e4 1571
f4f051eb 1572eh_host_reset_lock:
cfb0919c 1573 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1574 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1575 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1576
f4f051eb
AV		 1577 return ret;
1578}
1da177e4
LT		 1579
1580/*
1581* qla2x00_loop_reset
1582* Issue loop reset.
1583*
1584* Input:
1585* ha = adapter block pointer.
1586*
1587* Returns:
1588* 0 = success
1589*/
a4722cf2 1590int
e315cd28 1591qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1592{
0c8c39af 1593 int ret;
bdf79621 1594 struct fc_port *fcport;
e315cd28 1595 struct qla_hw_data *ha = vha->hw;
1da177e4 1596
5854771e
AB		 1597 if (IS_QLAFX00(ha)) {
1598 return qlafx00_loop_reset(vha);
1599 }
1600
f4c496c1 1601 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1602 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1603 if (fcport->port_type != FCT_TARGET)
1604 continue;
1605
1606 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1607 if (ret != QLA_SUCCESS) {
7c3df132 1608 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1609 "Bus Reset failed: Reset=%d "
7c3df132 1610 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1611 }
1612 }
1613 }
1614
8ae6d9c7 1615
6246b8a1 1616 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1617 atomic_set(&vha->loop_state, LOOP_DOWN);
1618 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1619 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1620 ret = qla2x00_full_login_lip(vha);
0c8c39af 1621 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1622 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1623 "full_login_lip=%d.\n", ret);
749af3d5 1624 }
0c8c39af
AV		 1625 }
1626
0d6e61bc 1627 if (ha->flags.enable_lip_reset) {
e315cd28 1628 ret = qla2x00_lip_reset(vha);
ad537689 1629 if (ret != QLA_SUCCESS)
7c3df132
SK		 1630 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1631 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1632 }
1633
1da177e4 1634 /* Issue marker command only when we are going to start the I/O */
e315cd28 1635 vha->marker_needed = 1;
1da177e4 1636
0c8c39af 1637 return QLA_SUCCESS;
1da177e4
LT		 1638}
1639
df4bf0bb 1640void
e315cd28 1641qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1642{
73208dfd 1643 int que, cnt;
df4bf0bb
AV		 1644 unsigned long flags;
1645 srb_t *sp;
e315cd28 1646 struct qla_hw_data *ha = vha->hw;
73208dfd 1647 struct req_que *req;
df4bf0bb 1648
c0cb4496
AE		 1649 qlt_host_reset_handler(ha);
1650
df4bf0bb 1651 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1652 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1653 req = ha->req_q_map[que];
73208dfd
AC		 1654 if (!req)
1655 continue;
8d93f550
CD		 1656 if (!req->outstanding_cmds)
1657 continue;
1658 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1659 sp = req->outstanding_cmds[cnt];
e612d465 1660 if (sp) {
c733ab35
MFO		 1661 /* Don't abort commands in adapter during EEH
1662 * recovery as it's not accessible/responding.
1535aa75 1663 */
5f7c2bee
BK		 1664 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1665 (sp->type == SRB_SCSI_CMD)) {
c733ab35
MFO		 1666 /* Get a reference to the sp and drop the lock.
1667 * The reference ensures this sp->done() call
1668 * - and not the call in qla2xxx_eh_abort() -
1669 * ends the SCSI command (with result 'res').
1670 */
1671 sp_get(sp);
1672 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1673 qla2xxx_eh_abort(GET_CMD_SP(sp));
1674 spin_lock_irqsave(&ha->hardware_lock, flags);
1675 }
73208dfd 1676 req->outstanding_cmds[cnt] = NULL;
25ff6af1 1677 sp->done(sp, res);
73208dfd 1678 }
df4bf0bb
AV		 1679 }
1680 }
1681 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1682}
1683
f4f051eb
AV		 1684static int
1685qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1686{
bdf79621 1687 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1688
19a7b4ae 1689 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1690 return -ENXIO;
bdf79621 1691
19a7b4ae 1692 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1693
f4f051eb
AV		 1694 return 0;
1695}
1da177e4 1696
f4f051eb
AV		 1697static int
1698qla2xxx_slave_configure(struct scsi_device *sdev)
1699{
e315cd28 1700 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1701 struct req_que *req = vha->req;
8482e118 1702
9e522cd8
AE		 1703 if (IS_T10_PI_CAPABLE(vha->hw))
1704 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1705
db5ed4df 1706 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1707 return 0;
1708}
1da177e4 1709
f4f051eb
AV		 1710static void
1711qla2xxx_slave_destroy(struct scsi_device *sdev)
1712{
1713 sdev->hostdata = NULL;
1da177e4
LT		 1714}
1715
1716/**
1717 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1718 * @ha: HA context
1719 *
1720 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1721 * supported addressing method.
1722 */
1723static void
53303c42 1724qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1725{
7524f9b9 1726 /* Assume a 32bit DMA mask. */
1da177e4 1727 ha->flags.enable_64bit_addressing = 0;
1da177e4 1728
6a35528a 1729 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1730 /* Any upper-dword bits set? */
1731 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1732 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1733 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1734 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1735 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1736 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1737 return;
1da177e4 1738 }
1da177e4 1739 }
7524f9b9 1740
284901a9
YH		 1741 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1742 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1743}
1744
fd34f556 1745static void
e315cd28 1746qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1747{
1748 unsigned long flags = 0;
1749 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1750
1751 spin_lock_irqsave(&ha->hardware_lock, flags);
1752 ha->interrupts_on = 1;
1753 /* enable risc and host interrupts */
1754 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1755 RD_REG_WORD(&reg->ictrl);
1756 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1757
1758}
1759
1760static void
e315cd28 1761qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1762{
1763 unsigned long flags = 0;
1764 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1765
1766 spin_lock_irqsave(&ha->hardware_lock, flags);
1767 ha->interrupts_on = 0;
1768 /* disable risc and host interrupts */
1769 WRT_REG_WORD(&reg->ictrl, 0);
1770 RD_REG_WORD(&reg->ictrl);
1771 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1772}
1773
1774static void
e315cd28 1775qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1776{
1777 unsigned long flags = 0;
1778 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1779
1780 spin_lock_irqsave(&ha->hardware_lock, flags);
1781 ha->interrupts_on = 1;
1782 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1783 RD_REG_DWORD(&reg->ictrl);
1784 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1785}
1786
1787static void
e315cd28 1788qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1789{
1790 unsigned long flags = 0;
1791 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1792
124f85e6
AV		 1793 if (IS_NOPOLLING_TYPE(ha))
1794 return;
fd34f556
AV		 1795 spin_lock_irqsave(&ha->hardware_lock, flags);
1796 ha->interrupts_on = 0;
1797 WRT_REG_DWORD(&reg->ictrl, 0);
1798 RD_REG_DWORD(&reg->ictrl);
1799 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1800}
1801
706f457d
GM		 1802static int
1803qla2x00_iospace_config(struct qla_hw_data *ha)
1804{
1805 resource_size_t pio;
1806 uint16_t msix;
706f457d 1807
706f457d
GM		 1808 if (pci_request_selected_regions(ha->pdev, ha->bars,
1809 QLA2XXX_DRIVER_NAME)) {
1810 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1811 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1812 pci_name(ha->pdev));
1813 goto iospace_error_exit;
1814 }
1815 if (!(ha->bars & 1))
1816 goto skip_pio;
1817
1818 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1819 pio = pci_resource_start(ha->pdev, 0);
1820 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1821 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1822 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1823 "Invalid pci I/O region size (%s).\n",
1824 pci_name(ha->pdev));
1825 pio = 0;
1826 }
1827 } else {
1828 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1829 "Region #0 no a PIO resource (%s).\n",
1830 pci_name(ha->pdev));
1831 pio = 0;
1832 }
1833 ha->pio_address = pio;
1834 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1835 "PIO address=%llu.\n",
1836 (unsigned long long)ha->pio_address);
1837
1838skip_pio:
1839 /* Use MMIO operations for all accesses. */
1840 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1841 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1842 "Region #1 not an MMIO resource (%s), aborting.\n",
1843 pci_name(ha->pdev));
1844 goto iospace_error_exit;
1845 }
1846 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1847 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1848 "Invalid PCI mem region size (%s), aborting.\n",
1849 pci_name(ha->pdev));
1850 goto iospace_error_exit;
1851 }
1852
1853 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1854 if (!ha->iobase) {
1855 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1856 "Cannot remap MMIO (%s), aborting.\n",
1857 pci_name(ha->pdev));
1858 goto iospace_error_exit;
1859 }
1860
1861 /* Determine queue resources */
1862 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1863 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1864 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1865 goto mqiobase_exit;
1866
1867 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1868 pci_resource_len(ha->pdev, 3));
1869 if (ha->mqiobase) {
1870 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1871 "MQIO Base=%p.\n", ha->mqiobase);
1872 /* Read MSIX vector size of the board */
1873 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1874 ha->msix_count = msix + 1;
706f457d 1875 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1876 /* MB interrupt uses 1 vector */
1877 ha->max_req_queues = ha->msix_count - 1;
1878 ha->max_rsp_queues = ha->max_req_queues;
1879 /* Queue pairs is the max value minus the base queue pair */
1880 ha->max_qpairs = ha->max_rsp_queues - 1;
1881 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1882 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1883
706f457d 1884 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1885 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1886 } else
1887 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1888 "BAR 3 not enabled.\n");
1889
1890mqiobase_exit:
706f457d 1891 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1892 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1893 return (0);
1894
1895iospace_error_exit:
1896 return (-ENOMEM);
1897}
1898
1899
6246b8a1
GM		 1900static int
1901qla83xx_iospace_config(struct qla_hw_data *ha)
1902{
1903 uint16_t msix;
6246b8a1
GM		 1904
1905 if (pci_request_selected_regions(ha->pdev, ha->bars,
1906 QLA2XXX_DRIVER_NAME)) {
1907 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1908 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1909 pci_name(ha->pdev));
1910
1911 goto iospace_error_exit;
1912 }
1913
1914 /* Use MMIO operations for all accesses. */
1915 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1916 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1917 "Invalid pci I/O region size (%s).\n",
1918 pci_name(ha->pdev));
1919 goto iospace_error_exit;
1920 }
1921 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1922 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1923 "Invalid PCI mem region size (%s), aborting\n",
1924 pci_name(ha->pdev));
1925 goto iospace_error_exit;
1926 }
1927
1928 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1929 if (!ha->iobase) {
1930 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1931 "Cannot remap MMIO (%s), aborting.\n",
1932 pci_name(ha->pdev));
1933 goto iospace_error_exit;
1934 }
1935
1936 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1937 /* 83XX 26XX always use MQ type access for queues
1938 * - mbar 2, a.k.a region 4 */
1939 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1940 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 1941 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1942 pci_resource_len(ha->pdev, 4));
1943
1944 if (!ha->mqiobase) {
1945 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1946 "BAR2/region4 not enabled\n");
1947 goto mqiobase_exit;
1948 }
1949
1950 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1951 pci_resource_len(ha->pdev, 2));
1952 if (ha->msixbase) {
1953 /* Read MSIX vector size of the board */
1954 pci_read_config_word(ha->pdev,
1955 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1956 ha->msix_count = msix + 1;
093df737
QT		 1957 /*
1958 * By default, driver uses at least two msix vectors
1959 * (default & rspq)
1960 */
d7459527
MH		 1961 if (ql2xmqsupport) {
1962 /* MB interrupt uses 1 vector */
1963 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 1964
1965 /* ATIOQ needs 1 vector. That's 1 less QPair */
1966 if (QLA_TGT_MODE_ENABLED())
1967 ha->max_req_queues--;
1968
d0d2c68b
MH		 1969 ha->max_rsp_queues = ha->max_req_queues;
1970
d7459527
MH		 1971 /* Queue pairs is the max value minus
1972 * the base queue pair */
1973 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1974 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1975 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1976 }
1977 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1978 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1979 } else
1980 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1981 "BAR 1 not enabled.\n");
1982
1983mqiobase_exit:
6246b8a1 1984 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 1985 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 1986 return 0;
1987
1988iospace_error_exit:
1989 return -ENOMEM;
1990}
1991
fd34f556
AV		 1992static struct isp_operations qla2100_isp_ops = {
1993 .pci_config = qla2100_pci_config,
1994 .reset_chip = qla2x00_reset_chip,
1995 .chip_diag = qla2x00_chip_diag,
1996 .config_rings = qla2x00_config_rings,
1997 .reset_adapter = qla2x00_reset_adapter,
1998 .nvram_config = qla2x00_nvram_config,
1999 .update_fw_options = qla2x00_update_fw_options,
2000 .load_risc = qla2x00_load_risc,
2001 .pci_info_str = qla2x00_pci_info_str,
2002 .fw_version_str = qla2x00_fw_version_str,
2003 .intr_handler = qla2100_intr_handler,
2004 .enable_intrs = qla2x00_enable_intrs,
2005 .disable_intrs = qla2x00_disable_intrs,
2006 .abort_command = qla2x00_abort_command,
523ec773
AV		 2007 .target_reset = qla2x00_abort_target,
2008 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2009 .fabric_login = qla2x00_login_fabric,
2010 .fabric_logout = qla2x00_fabric_logout,
2011 .calc_req_entries = qla2x00_calc_iocbs_32,
2012 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2013 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2014 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2015 .read_nvram = qla2x00_read_nvram_data,
2016 .write_nvram = qla2x00_write_nvram_data,
2017 .fw_dump = qla2100_fw_dump,
2018 .beacon_on = NULL,
2019 .beacon_off = NULL,
2020 .beacon_blink = NULL,
2021 .read_optrom = qla2x00_read_optrom_data,
2022 .write_optrom = qla2x00_write_optrom_data,
2023 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2024 .start_scsi = qla2x00_start_scsi,
d7459527 2025 .start_scsi_mq = NULL,
a9083016 2026 .abort_isp = qla2x00_abort_isp,
706f457d 2027 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2028 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2029};
2030
2031static struct isp_operations qla2300_isp_ops = {
2032 .pci_config = qla2300_pci_config,
2033 .reset_chip = qla2x00_reset_chip,
2034 .chip_diag = qla2x00_chip_diag,
2035 .config_rings = qla2x00_config_rings,
2036 .reset_adapter = qla2x00_reset_adapter,
2037 .nvram_config = qla2x00_nvram_config,
2038 .update_fw_options = qla2x00_update_fw_options,
2039 .load_risc = qla2x00_load_risc,
2040 .pci_info_str = qla2x00_pci_info_str,
2041 .fw_version_str = qla2x00_fw_version_str,
2042 .intr_handler = qla2300_intr_handler,
2043 .enable_intrs = qla2x00_enable_intrs,
2044 .disable_intrs = qla2x00_disable_intrs,
2045 .abort_command = qla2x00_abort_command,
523ec773
AV		 2046 .target_reset = qla2x00_abort_target,
2047 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2048 .fabric_login = qla2x00_login_fabric,
2049 .fabric_logout = qla2x00_fabric_logout,
2050 .calc_req_entries = qla2x00_calc_iocbs_32,
2051 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2052 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2053 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2054 .read_nvram = qla2x00_read_nvram_data,
2055 .write_nvram = qla2x00_write_nvram_data,
2056 .fw_dump = qla2300_fw_dump,
2057 .beacon_on = qla2x00_beacon_on,
2058 .beacon_off = qla2x00_beacon_off,
2059 .beacon_blink = qla2x00_beacon_blink,
2060 .read_optrom = qla2x00_read_optrom_data,
2061 .write_optrom = qla2x00_write_optrom_data,
2062 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2063 .start_scsi = qla2x00_start_scsi,
d7459527 2064 .start_scsi_mq = NULL,
a9083016 2065 .abort_isp = qla2x00_abort_isp,
7ec0effd 2066 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2067 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2068};
2069
2070static struct isp_operations qla24xx_isp_ops = {
2071 .pci_config = qla24xx_pci_config,
2072 .reset_chip = qla24xx_reset_chip,
2073 .chip_diag = qla24xx_chip_diag,
2074 .config_rings = qla24xx_config_rings,
2075 .reset_adapter = qla24xx_reset_adapter,
2076 .nvram_config = qla24xx_nvram_config,
2077 .update_fw_options = qla24xx_update_fw_options,
2078 .load_risc = qla24xx_load_risc,
2079 .pci_info_str = qla24xx_pci_info_str,
2080 .fw_version_str = qla24xx_fw_version_str,
2081 .intr_handler = qla24xx_intr_handler,
2082 .enable_intrs = qla24xx_enable_intrs,
2083 .disable_intrs = qla24xx_disable_intrs,
2084 .abort_command = qla24xx_abort_command,
523ec773
AV		 2085 .target_reset = qla24xx_abort_target,
2086 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2087 .fabric_login = qla24xx_login_fabric,
2088 .fabric_logout = qla24xx_fabric_logout,
2089 .calc_req_entries = NULL,
2090 .build_iocbs = NULL,
2091 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2092 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2093 .read_nvram = qla24xx_read_nvram_data,
2094 .write_nvram = qla24xx_write_nvram_data,
2095 .fw_dump = qla24xx_fw_dump,
2096 .beacon_on = qla24xx_beacon_on,
2097 .beacon_off = qla24xx_beacon_off,
2098 .beacon_blink = qla24xx_beacon_blink,
2099 .read_optrom = qla24xx_read_optrom_data,
2100 .write_optrom = qla24xx_write_optrom_data,
2101 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2102 .start_scsi = qla24xx_start_scsi,
d7459527 2103 .start_scsi_mq = NULL,
a9083016 2104 .abort_isp = qla2x00_abort_isp,
7ec0effd 2105 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2106 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2107};
2108
c3a2f0df
AV		 2109static struct isp_operations qla25xx_isp_ops = {
2110 .pci_config = qla25xx_pci_config,
2111 .reset_chip = qla24xx_reset_chip,
2112 .chip_diag = qla24xx_chip_diag,
2113 .config_rings = qla24xx_config_rings,
2114 .reset_adapter = qla24xx_reset_adapter,
2115 .nvram_config = qla24xx_nvram_config,
2116 .update_fw_options = qla24xx_update_fw_options,
2117 .load_risc = qla24xx_load_risc,
2118 .pci_info_str = qla24xx_pci_info_str,
2119 .fw_version_str = qla24xx_fw_version_str,
2120 .intr_handler = qla24xx_intr_handler,
2121 .enable_intrs = qla24xx_enable_intrs,
2122 .disable_intrs = qla24xx_disable_intrs,
2123 .abort_command = qla24xx_abort_command,
523ec773
AV		 2124 .target_reset = qla24xx_abort_target,
2125 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2126 .fabric_login = qla24xx_login_fabric,
2127 .fabric_logout = qla24xx_fabric_logout,
2128 .calc_req_entries = NULL,
2129 .build_iocbs = NULL,
2130 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2131 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2132 .read_nvram = qla25xx_read_nvram_data,
2133 .write_nvram = qla25xx_write_nvram_data,
2134 .fw_dump = qla25xx_fw_dump,
2135 .beacon_on = qla24xx_beacon_on,
2136 .beacon_off = qla24xx_beacon_off,
2137 .beacon_blink = qla24xx_beacon_blink,
338c9161 2138 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2139 .write_optrom = qla24xx_write_optrom_data,
2140 .get_flash_version = qla24xx_get_flash_version,
bad75002 2141 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2142 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2143 .abort_isp = qla2x00_abort_isp,
7ec0effd 2144 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2145 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2146};
2147
3a03eb79
AV		 2148static struct isp_operations qla81xx_isp_ops = {
2149 .pci_config = qla25xx_pci_config,
2150 .reset_chip = qla24xx_reset_chip,
2151 .chip_diag = qla24xx_chip_diag,
2152 .config_rings = qla24xx_config_rings,
2153 .reset_adapter = qla24xx_reset_adapter,
2154 .nvram_config = qla81xx_nvram_config,
2155 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2156 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2157 .pci_info_str = qla24xx_pci_info_str,
2158 .fw_version_str = qla24xx_fw_version_str,
2159 .intr_handler = qla24xx_intr_handler,
2160 .enable_intrs = qla24xx_enable_intrs,
2161 .disable_intrs = qla24xx_disable_intrs,
2162 .abort_command = qla24xx_abort_command,
2163 .target_reset = qla24xx_abort_target,
2164 .lun_reset = qla24xx_lun_reset,
2165 .fabric_login = qla24xx_login_fabric,
2166 .fabric_logout = qla24xx_fabric_logout,
2167 .calc_req_entries = NULL,
2168 .build_iocbs = NULL,
2169 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2170 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2171 .read_nvram = NULL,
2172 .write_nvram = NULL,
3a03eb79
AV		 2173 .fw_dump = qla81xx_fw_dump,
2174 .beacon_on = qla24xx_beacon_on,
2175 .beacon_off = qla24xx_beacon_off,
6246b8a1 2176 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2177 .read_optrom = qla25xx_read_optrom_data,
2178 .write_optrom = qla24xx_write_optrom_data,
2179 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2180 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2181 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2182 .abort_isp = qla2x00_abort_isp,
7ec0effd 2183 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2184 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2185};
2186
2187static struct isp_operations qla82xx_isp_ops = {
2188 .pci_config = qla82xx_pci_config,
2189 .reset_chip = qla82xx_reset_chip,
2190 .chip_diag = qla24xx_chip_diag,
2191 .config_rings = qla82xx_config_rings,
2192 .reset_adapter = qla24xx_reset_adapter,
2193 .nvram_config = qla81xx_nvram_config,
2194 .update_fw_options = qla24xx_update_fw_options,
2195 .load_risc = qla82xx_load_risc,
9d55ca66 2196 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2197 .fw_version_str = qla24xx_fw_version_str,
2198 .intr_handler = qla82xx_intr_handler,
2199 .enable_intrs = qla82xx_enable_intrs,
2200 .disable_intrs = qla82xx_disable_intrs,
2201 .abort_command = qla24xx_abort_command,
2202 .target_reset = qla24xx_abort_target,
2203 .lun_reset = qla24xx_lun_reset,
2204 .fabric_login = qla24xx_login_fabric,
2205 .fabric_logout = qla24xx_fabric_logout,
2206 .calc_req_entries = NULL,
2207 .build_iocbs = NULL,
2208 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2209 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2210 .read_nvram = qla24xx_read_nvram_data,
2211 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2212 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2213 .beacon_on = qla82xx_beacon_on,
2214 .beacon_off = qla82xx_beacon_off,
2215 .beacon_blink = NULL,
a9083016
GM		 2216 .read_optrom = qla82xx_read_optrom_data,
2217 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2218 .get_flash_version = qla82xx_get_flash_version,
a9083016 2219 .start_scsi = qla82xx_start_scsi,
d7459527 2220 .start_scsi_mq = NULL,
a9083016 2221 .abort_isp = qla82xx_abort_isp,
706f457d 2222 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2223 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2224};
2225
7ec0effd
AD		 2226static struct isp_operations qla8044_isp_ops = {
2227 .pci_config = qla82xx_pci_config,
2228 .reset_chip = qla82xx_reset_chip,
2229 .chip_diag = qla24xx_chip_diag,
2230 .config_rings = qla82xx_config_rings,
2231 .reset_adapter = qla24xx_reset_adapter,
2232 .nvram_config = qla81xx_nvram_config,
2233 .update_fw_options = qla24xx_update_fw_options,
2234 .load_risc = qla82xx_load_risc,
2235 .pci_info_str = qla24xx_pci_info_str,
2236 .fw_version_str = qla24xx_fw_version_str,
2237 .intr_handler = qla8044_intr_handler,
2238 .enable_intrs = qla82xx_enable_intrs,
2239 .disable_intrs = qla82xx_disable_intrs,
2240 .abort_command = qla24xx_abort_command,
2241 .target_reset = qla24xx_abort_target,
2242 .lun_reset = qla24xx_lun_reset,
2243 .fabric_login = qla24xx_login_fabric,
2244 .fabric_logout = qla24xx_fabric_logout,
2245 .calc_req_entries = NULL,
2246 .build_iocbs = NULL,
2247 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2248 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2249 .read_nvram = NULL,
2250 .write_nvram = NULL,
a1b23c5a 2251 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2252 .beacon_on = qla82xx_beacon_on,
2253 .beacon_off = qla82xx_beacon_off,
2254 .beacon_blink = NULL,
888e639d 2255 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2256 .write_optrom = qla8044_write_optrom_data,
2257 .get_flash_version = qla82xx_get_flash_version,
2258 .start_scsi = qla82xx_start_scsi,
d7459527 2259 .start_scsi_mq = NULL,
7ec0effd
AD		 2260 .abort_isp = qla8044_abort_isp,
2261 .iospace_config = qla82xx_iospace_config,
2262 .initialize_adapter = qla2x00_initialize_adapter,
2263};
2264
6246b8a1
GM		 2265static struct isp_operations qla83xx_isp_ops = {
2266 .pci_config = qla25xx_pci_config,
2267 .reset_chip = qla24xx_reset_chip,
2268 .chip_diag = qla24xx_chip_diag,
2269 .config_rings = qla24xx_config_rings,
2270 .reset_adapter = qla24xx_reset_adapter,
2271 .nvram_config = qla81xx_nvram_config,
2272 .update_fw_options = qla81xx_update_fw_options,
2273 .load_risc = qla81xx_load_risc,
2274 .pci_info_str = qla24xx_pci_info_str,
2275 .fw_version_str = qla24xx_fw_version_str,
2276 .intr_handler = qla24xx_intr_handler,
2277 .enable_intrs = qla24xx_enable_intrs,
2278 .disable_intrs = qla24xx_disable_intrs,
2279 .abort_command = qla24xx_abort_command,
2280 .target_reset = qla24xx_abort_target,
2281 .lun_reset = qla24xx_lun_reset,
2282 .fabric_login = qla24xx_login_fabric,
2283 .fabric_logout = qla24xx_fabric_logout,
2284 .calc_req_entries = NULL,
2285 .build_iocbs = NULL,
2286 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2287 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2288 .read_nvram = NULL,
2289 .write_nvram = NULL,
2290 .fw_dump = qla83xx_fw_dump,
2291 .beacon_on = qla24xx_beacon_on,
2292 .beacon_off = qla24xx_beacon_off,
2293 .beacon_blink = qla83xx_beacon_blink,
2294 .read_optrom = qla25xx_read_optrom_data,
2295 .write_optrom = qla24xx_write_optrom_data,
2296 .get_flash_version = qla24xx_get_flash_version,
2297 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2298 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2299 .abort_isp = qla2x00_abort_isp,
2300 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2301 .initialize_adapter = qla2x00_initialize_adapter,
2302};
2303
2304static struct isp_operations qlafx00_isp_ops = {
2305 .pci_config = qlafx00_pci_config,
2306 .reset_chip = qlafx00_soft_reset,
2307 .chip_diag = qlafx00_chip_diag,
2308 .config_rings = qlafx00_config_rings,
2309 .reset_adapter = qlafx00_soft_reset,
2310 .nvram_config = NULL,
2311 .update_fw_options = NULL,
2312 .load_risc = NULL,
2313 .pci_info_str = qlafx00_pci_info_str,
2314 .fw_version_str = qlafx00_fw_version_str,
2315 .intr_handler = qlafx00_intr_handler,
2316 .enable_intrs = qlafx00_enable_intrs,
2317 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2318 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2319 .target_reset = qlafx00_abort_target,
2320 .lun_reset = qlafx00_lun_reset,
2321 .fabric_login = NULL,
2322 .fabric_logout = NULL,
2323 .calc_req_entries = NULL,
2324 .build_iocbs = NULL,
2325 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2326 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2327 .read_nvram = qla24xx_read_nvram_data,
2328 .write_nvram = qla24xx_write_nvram_data,
2329 .fw_dump = NULL,
2330 .beacon_on = qla24xx_beacon_on,
2331 .beacon_off = qla24xx_beacon_off,
2332 .beacon_blink = NULL,
2333 .read_optrom = qla24xx_read_optrom_data,
2334 .write_optrom = qla24xx_write_optrom_data,
2335 .get_flash_version = qla24xx_get_flash_version,
2336 .start_scsi = qlafx00_start_scsi,
d7459527 2337 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2338 .abort_isp = qlafx00_abort_isp,
2339 .iospace_config = qlafx00_iospace_config,
2340 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2341};
2342
f73cb695
CD		 2343static struct isp_operations qla27xx_isp_ops = {
2344 .pci_config = qla25xx_pci_config,
2345 .reset_chip = qla24xx_reset_chip,
2346 .chip_diag = qla24xx_chip_diag,
2347 .config_rings = qla24xx_config_rings,
2348 .reset_adapter = qla24xx_reset_adapter,
2349 .nvram_config = qla81xx_nvram_config,
2350 .update_fw_options = qla81xx_update_fw_options,
2351 .load_risc = qla81xx_load_risc,
2352 .pci_info_str = qla24xx_pci_info_str,
2353 .fw_version_str = qla24xx_fw_version_str,
2354 .intr_handler = qla24xx_intr_handler,
2355 .enable_intrs = qla24xx_enable_intrs,
2356 .disable_intrs = qla24xx_disable_intrs,
2357 .abort_command = qla24xx_abort_command,
2358 .target_reset = qla24xx_abort_target,
2359 .lun_reset = qla24xx_lun_reset,
2360 .fabric_login = qla24xx_login_fabric,
2361 .fabric_logout = qla24xx_fabric_logout,
2362 .calc_req_entries = NULL,
2363 .build_iocbs = NULL,
2364 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2365 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2366 .read_nvram = NULL,
2367 .write_nvram = NULL,
2368 .fw_dump = qla27xx_fwdump,
2369 .beacon_on = qla24xx_beacon_on,
2370 .beacon_off = qla24xx_beacon_off,
2371 .beacon_blink = qla83xx_beacon_blink,
2372 .read_optrom = qla25xx_read_optrom_data,
2373 .write_optrom = qla24xx_write_optrom_data,
2374 .get_flash_version = qla24xx_get_flash_version,
2375 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2376 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2377 .abort_isp = qla2x00_abort_isp,
2378 .iospace_config = qla83xx_iospace_config,
2379 .initialize_adapter = qla2x00_initialize_adapter,
2380};
2381
ea5b6382 2382static inline void
e315cd28 2383qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2384{
2385 ha->device_type = DT_EXTENDED_IDS;
2386 switch (ha->pdev->device) {
2387 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2388 ha->isp_type |= DT_ISP2100;
ea5b6382 2389 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2390 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2391 break;
2392 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2393 ha->isp_type |= DT_ISP2200;
ea5b6382 2394 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2395 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2396 break;
2397 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2398 ha->isp_type |= DT_ISP2300;
4a59f71d 2399 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2400 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2401 break;
2402 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2403 ha->isp_type |= DT_ISP2312;
4a59f71d 2404 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2405 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2406 break;
2407 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2408 ha->isp_type |= DT_ISP2322;
4a59f71d 2409 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2410 if (ha->pdev->subsystem_vendor == 0x1028 &&
2411 ha->pdev->subsystem_device == 0x0170)
2412 ha->device_type |= DT_OEM_001;
441d1072 2413 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2414 break;
2415 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2416 ha->isp_type |= DT_ISP6312;
441d1072 2417 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2418 break;
2419 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2420 ha->isp_type |= DT_ISP6322;
441d1072 2421 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2422 break;
2423 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2424 ha->isp_type |= DT_ISP2422;
4a59f71d 2425 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2426 ha->device_type |= DT_FWI2;
c76f2c01 2427 ha->device_type |= DT_IIDMA;
441d1072 2428 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2429 break;
2430 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2431 ha->isp_type |= DT_ISP2432;
4a59f71d 2432 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2433 ha->device_type |= DT_FWI2;
c76f2c01 2434 ha->device_type |= DT_IIDMA;
441d1072 2435 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2436 break;
4d4df193 2437 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2438 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2439 ha->device_type |= DT_ZIO_SUPPORTED;
2440 ha->device_type |= DT_FWI2;
2441 ha->device_type |= DT_IIDMA;
2442 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2443 break;
044cc6c8 2444 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2445 ha->isp_type |= DT_ISP5422;
e428924c 2446 ha->device_type |= DT_FWI2;
441d1072 2447 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2448 break;
044cc6c8 2449 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2450 ha->isp_type |= DT_ISP5432;
e428924c 2451 ha->device_type |= DT_FWI2;
441d1072 2452 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2453 break;
c3a2f0df 2454 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2455 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2456 ha->device_type |= DT_ZIO_SUPPORTED;
2457 ha->device_type |= DT_FWI2;
2458 ha->device_type |= DT_IIDMA;
441d1072 2459 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2460 break;
3a03eb79 2461 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2462 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2463 ha->device_type |= DT_ZIO_SUPPORTED;
2464 ha->device_type |= DT_FWI2;
2465 ha->device_type |= DT_IIDMA;
2466 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2467 break;
a9083016 2468 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2469 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2470 ha->device_type |= DT_ZIO_SUPPORTED;
2471 ha->device_type |= DT_FWI2;
2472 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2473 /* Initialize 82XX ISP flags */
2474 qla82xx_init_flags(ha);
2475 break;
7ec0effd 2476 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2477 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2478 ha->device_type |= DT_ZIO_SUPPORTED;
2479 ha->device_type |= DT_FWI2;
2480 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2481 /* Initialize 82XX ISP flags */
2482 qla82xx_init_flags(ha);
2483 break;
6246b8a1 2484 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2485 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2486 ha->device_type |= DT_ZIO_SUPPORTED;
2487 ha->device_type |= DT_FWI2;
2488 ha->device_type |= DT_IIDMA;
2489 ha->device_type |= DT_T10_PI;
2490 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2491 break;
2492 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2493 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2494 ha->device_type |= DT_ZIO_SUPPORTED;
2495 ha->device_type |= DT_FWI2;
2496 ha->device_type |= DT_IIDMA;
2497 ha->device_type |= DT_T10_PI;
2498 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2499 break;
8ae6d9c7 2500 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2501 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2502 break;
f73cb695 2503 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2504 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2505 ha->device_type |= DT_ZIO_SUPPORTED;
2506 ha->device_type |= DT_FWI2;
2507 ha->device_type |= DT_IIDMA;
8ce3f570 2508 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2509 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2510 break;
2c5bbbb2 2511 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2512 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2513 ha->device_type |= DT_ZIO_SUPPORTED;
2514 ha->device_type |= DT_FWI2;
2515 ha->device_type |= DT_IIDMA;
8ce3f570 2516 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2517 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2518 break;
2b48992f 2519 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2520 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2521 ha->device_type |= DT_ZIO_SUPPORTED;
2522 ha->device_type |= DT_FWI2;
2523 ha->device_type |= DT_IIDMA;
8ce3f570 2524 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2525 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2526 break;
ea5b6382 2527 }
e5b68a61 2528
a9083016 2529 if (IS_QLA82XX(ha))
43a9c38b 2530 ha->port_no = ha->portnum & 1;
f73cb695 2531 else {
a9083016
GM		 2532 /* Get adapter physical port no from interrupt pin register. */
2533 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2534 if (IS_QLA27XX(ha))
2535 ha->port_no--;
2536 else
2537 ha->port_no = !(ha->port_no & 1);
2538 }
a9083016 2539
7c3df132 2540 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2541 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2542 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2543}
2544
1e99e33a
AV		 2545static void
2546qla2xxx_scan_start(struct Scsi_Host *shost)
2547{
e315cd28 2548 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2549
cbc8eb67
AV		 2550 if (vha->hw->flags.running_gold_fw)
2551 return;
2552
e315cd28
AC		 2553 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2554 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2555 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2556 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2557}
2558
2559static int
2560qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2561{
e315cd28 2562 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2563
a5dd506e
BK		 2564 if (test_bit(UNLOADING, &vha->dpc_flags))
2565 return 1;
e315cd28 2566 if (!vha->host)
1e99e33a 2567 return 1;
e315cd28 2568 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2569 return 1;
2570
e315cd28 2571 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2572}
2573
ec7193e2
QT		 2574static void qla2x00_iocb_work_fn(struct work_struct *work)
2575{
2576 struct scsi_qla_host *vha = container_of(work,
2577 struct scsi_qla_host, iocb_work);
2578 int cnt = 0;
2579
2580 while (!list_empty(&vha->work_list)) {
2581 qla2x00_do_work(vha);
2582 cnt++;
2583 if (cnt > 10)
2584 break;
2585 }
2586}
2587
1da177e4
LT		 2588/*
2589 * PCI driver interface
2590 */
6f039790 2591static int
7ee61397 2592qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2593{
a1541d5a 2594 int ret = -ENODEV;
1da177e4 2595 struct Scsi_Host *host;
e315cd28
AC		 2596 scsi_qla_host_t *base_vha = NULL;
2597 struct qla_hw_data *ha;
29856e28 2598 char pci_info[30];
7d613ac6 2599 char fw_str[30], wq_name[30];
5433383e 2600 struct scsi_host_template *sht;
642ef983 2601 int bars, mem_only = 0;
e315cd28 2602 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2603 struct req_que *req = NULL;
2604 struct rsp_que *rsp = NULL;
5601236b 2605 int i;
d7459527 2606
285d0321 2607 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2608 sht = &qla2xxx_driver_template;
5433383e 2609 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2610 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2611 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2612 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2613 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2614 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2615 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2616 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2617 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2618 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2619 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2620 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2621 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2622 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2623 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2624 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2625 mem_only = 1;
7c3df132
SK		 2626 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2627 "Mem only adapter.\n");
285d0321 2628 }
7c3df132
SK		 2629 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2630 "Bars=%d.\n", bars);
285d0321 2631
09483916
BH		 2632 if (mem_only) {
2633 if (pci_enable_device_mem(pdev))
ddff7ed4 2634 return ret;
09483916
BH		 2635 } else {
2636 if (pci_enable_device(pdev))
ddff7ed4 2637 return ret;
09483916 2638 }
285d0321 2639
0927678f
JB		 2640 /* This may fail but that's ok */
2641 pci_enable_pcie_error_reporting(pdev);
285d0321 2642
e315cd28
AC		 2643 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2644 if (!ha) {
7c3df132
SK		 2645 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2646 "Unable to allocate memory for ha.\n");
ddff7ed4 2647 goto disable_device;
1da177e4 2648 }
7c3df132
SK		 2649 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2650 "Memory allocated for ha=%p.\n", ha);
e315cd28 2651 ha->pdev = pdev;
2d70c103 2652 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2653 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2654 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2655 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2656 spin_lock_init(&ha->tgt.atio_lock);
2657
1da177e4
LT		 2658
2659 /* Clear our data area */
285d0321 2660 ha->bars = bars;
09483916 2661 ha->mem_only = mem_only;
df4bf0bb 2662 spin_lock_init(&ha->hardware_lock);
339aa70e 2663 spin_lock_init(&ha->vport_slock);
a9b6f722 2664 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2665 mutex_init(&ha->optrom_mutex);
1da177e4 2666
ea5b6382
AV		 2667 /* Set ISP-type information. */
2668 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2669
2670 /* Set EEH reset type to fundamental if required by hba */
95676112 2671 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2672 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2673 pdev->needs_freset = 1;
ca79cf66 2674
cba1e47f
CD		 2675 ha->prev_topology = 0;
2676 ha->init_cb_size = sizeof(init_cb_t);
2677 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2678 ha->optrom_size = OPTROM_SIZE_2300;
2679
abbd8870 2680 /* Assign ISP specific operations. */
1da177e4 2681 if (IS_QLA2100(ha)) {
642ef983 2682 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2683 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2684 req_length = REQUEST_ENTRY_CNT_2100;
2685 rsp_length = RESPONSE_ENTRY_CNT_2100;
2686 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2687 ha->gid_list_info_size = 4;
3a03eb79
AV		 2688 ha->flash_conf_off = ~0;
2689 ha->flash_data_off = ~0;
2690 ha->nvram_conf_off = ~0;
2691 ha->nvram_data_off = ~0;
fd34f556 2692 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2693 } else if (IS_QLA2200(ha)) {
642ef983 2694 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2695 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2696 req_length = REQUEST_ENTRY_CNT_2200;
2697 rsp_length = RESPONSE_ENTRY_CNT_2100;
2698 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2699 ha->gid_list_info_size = 4;
3a03eb79
AV		 2700 ha->flash_conf_off = ~0;
2701 ha->flash_data_off = ~0;
2702 ha->nvram_conf_off = ~0;
2703 ha->nvram_data_off = ~0;
fd34f556 2704 ha->isp_ops = &qla2100_isp_ops;
fca29703 2705 } else if (IS_QLA23XX(ha)) {
642ef983 2706 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2707 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2708 req_length = REQUEST_ENTRY_CNT_2200;
2709 rsp_length = RESPONSE_ENTRY_CNT_2300;
2710 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2711 ha->gid_list_info_size = 6;
854165f4
AV		 2712 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2713 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2714 ha->flash_conf_off = ~0;
2715 ha->flash_data_off = ~0;
2716 ha->nvram_conf_off = ~0;
2717 ha->nvram_data_off = ~0;
fd34f556 2718 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2719 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2720 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2721 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2722 req_length = REQUEST_ENTRY_CNT_24XX;
2723 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2724 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2725 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2726 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2727 ha->gid_list_info_size = 8;
854165f4 2728 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2729 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2730 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2731 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2732 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2733 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2734 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2735 } else if (IS_QLA25XX(ha)) {
642ef983 2736 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2737 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2738 req_length = REQUEST_ENTRY_CNT_24XX;
2739 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2740 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2741 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2742 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2743 ha->gid_list_info_size = 8;
2744 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2745 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2746 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2747 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2748 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2749 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2750 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2751 } else if (IS_QLA81XX(ha)) {
642ef983 2752 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2753 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2754 req_length = REQUEST_ENTRY_CNT_24XX;
2755 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2756 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2757 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2758 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2759 ha->gid_list_info_size = 8;
2760 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2761 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2762 ha->isp_ops = &qla81xx_isp_ops;
2763 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2764 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2765 ha->nvram_conf_off = ~0;
2766 ha->nvram_data_off = ~0;
a9083016 2767 } else if (IS_QLA82XX(ha)) {
642ef983 2768 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2769 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2770 req_length = REQUEST_ENTRY_CNT_82XX;
2771 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2772 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2773 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2774 ha->gid_list_info_size = 8;
2775 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2776 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2777 ha->isp_ops = &qla82xx_isp_ops;
2778 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2779 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2780 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2781 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2782 } else if (IS_QLA8044(ha)) {
2783 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2784 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2785 req_length = REQUEST_ENTRY_CNT_82XX;
2786 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2787 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2788 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2789 ha->gid_list_info_size = 8;
2790 ha->optrom_size = OPTROM_SIZE_83XX;
2791 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2792 ha->isp_ops = &qla8044_isp_ops;
2793 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2794 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2795 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2796 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2797 } else if (IS_QLA83XX(ha)) {
7d613ac6 2798 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2799 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2800 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2801 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2802 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2803 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2804 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2805 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2806 ha->gid_list_info_size = 8;
2807 ha->optrom_size = OPTROM_SIZE_83XX;
2808 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2809 ha->isp_ops = &qla83xx_isp_ops;
2810 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2811 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2812 ha->nvram_conf_off = ~0;
2813 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2814 } else if (IS_QLAFX00(ha)) {
2815 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2816 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2817 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2818 req_length = REQUEST_ENTRY_CNT_FX00;
2819 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2820 ha->isp_ops = &qlafx00_isp_ops;
2821 ha->port_down_retry_count = 30; /* default value */
2822 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2823 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2824 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2825 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2826 ha->mr.host_info_resend = false;
2827 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2828 } else if (IS_QLA27XX(ha)) {
2829 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2830 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2831 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2832 req_length = REQUEST_ENTRY_CNT_83XX;
2833 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2834 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2835 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2836 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2837 ha->gid_list_info_size = 8;
2838 ha->optrom_size = OPTROM_SIZE_83XX;
2839 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2840 ha->isp_ops = &qla27xx_isp_ops;
2841 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2842 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2843 ha->nvram_conf_off = ~0;
2844 ha->nvram_data_off = ~0;
1da177e4 2845 }
6246b8a1 2846
7c3df132
SK		 2847 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2848 "mbx_count=%d, req_length=%d, "
2849 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2850 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2851 "max_fibre_devices=%d.\n",
7c3df132
SK		 2852 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2853 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2854 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2855 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2856 "isp_ops=%p, flash_conf_off=%d, "
2857 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2858 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2859 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2860
2861 /* Configure PCI I/O space */
2862 ret = ha->isp_ops->iospace_config(ha);
2863 if (ret)
0a63ad12 2864 goto iospace_config_failed;
706f457d
GM		 2865
2866 ql_log_pci(ql_log_info, pdev, 0x001d,
2867 "Found an ISP%04X irq %d iobase 0x%p.\n",
2868 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2869 mutex_init(&ha->vport_lock);
d7459527 2870 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2871 init_completion(&ha->mbx_cmd_comp);
2872 complete(&ha->mbx_cmd_comp);
2873 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2874 init_completion(&ha->dcbx_comp);
f356bef1 2875 init_completion(&ha->lb_portup_comp);
1da177e4 2876
2c3dfe3f 2877 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2878
53303c42 2879 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2880 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2881 "64 Bit addressing is %s.\n",
2882 ha->flags.enable_64bit_addressing ? "enable" :
2883 "disable");
73208dfd 2884 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2885 if (ret) {
7c3df132
SK		 2886 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2887 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2888
e315cd28
AC		 2889 goto probe_hw_failed;
2890 }
2891
73208dfd 2892 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2893 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2894 req->max_q_depth = ql2xmaxqdepth;
2895
e315cd28
AC		 2896
2897 base_vha = qla2x00_create_host(sht, ha);
2898 if (!base_vha) {
a1541d5a 2899 ret = -ENOMEM;
6e9f21f3 2900 qla2x00_mem_free(ha);
2afa19a9
AC		 2901 qla2x00_free_req_que(ha, req);
2902 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2903 goto probe_hw_failed;
1da177e4
LT		 2904 }
2905
e315cd28 2906 pci_set_drvdata(pdev, base_vha);
6b383979 2907 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2908
e315cd28 2909 host = base_vha->host;
2afa19a9 2910 base_vha->req = req;
73208dfd 2911 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2912 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2913 else
e315cd28
AC		 2914 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2915 base_vha->vp_idx;
58548cb5 2916
8ae6d9c7
GM		 2917 /* Setup fcport template structure. */
2918 ha->mr.fcport.vha = base_vha;
2919 ha->mr.fcport.port_type = FCT_UNKNOWN;
2920 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2921 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2922 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2923 ha->mr.fcport.scan_state = 1;
2924
58548cb5
GM		 2925 /* Set the SG table size based on ISP type */
2926 if (!IS_FWI2_CAPABLE(ha)) {
2927 if (IS_QLA2100(ha))
2928 host->sg_tablesize = 32;
2929 } else {
2930 if (!IS_QLA82XX(ha))
2931 host->sg_tablesize = QLA_SG_ALL;
2932 }
642ef983 2933 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2934 host->cmd_per_lun = 3;
2935 host->unique_id = host->host_no;
e02587d7 2936 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2937 host->max_cmd_len = 32;
2938 else
2939 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2940 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2941 /* Older HBAs support only 16-bit LUNs */
2942 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2943 ql2xmaxlun > 0xffff)
2944 host->max_lun = 0xffff;
2945 else
2946 host->max_lun = ql2xmaxlun;
e315cd28 2947 host->transportt = qla2xxx_transport_template;
9a069e19 2948 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2949
7c3df132
SK		 2950 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2951 "max_id=%d this_id=%d "
2952 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2953 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2954 host->this_id, host->cmd_per_lun, host->unique_id,
2955 host->max_cmd_len, host->max_channel, host->max_lun,
2956 host->transportt, sht->vendor_id);
2957
d7459527
MH		 2958 /* Set up the irqs */
2959 ret = qla2x00_request_irqs(ha, rsp);
2960 if (ret)
2961 goto probe_init_failed;
2962
9a347ff4
CD		 2963 /* Alloc arrays of request and response ring ptrs */
2964 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2965 ql_log(ql_log_fatal, base_vha, 0x003d,
2966 "Failed to allocate memory for queue pointers..."
2967 "aborting.\n");
2968 goto probe_init_failed;
2969 }
2970
5601236b
MH		 2971 if (ha->mqenable && shost_use_blk_mq(host)) {
2972 /* number of hardware queues supported by blk/scsi-mq*/
2973 host->nr_hw_queues = ha->max_qpairs;
2974
2975 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2976 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2977 } else
2978 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2979 "blk/scsi-mq disabled.\n");
2980
2d70c103 2981 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2982
90a86fc0
JC		 2983 pci_save_state(pdev);
2984
9a347ff4 2985 /* Assign back pointers */
2afa19a9
AC		 2986 rsp->req = req;
2987 req->rsp = rsp;
9a347ff4 2988
8ae6d9c7
GM		 2989 if (IS_QLAFX00(ha)) {
2990 ha->rsp_q_map[0] = rsp;
2991 ha->req_q_map[0] = req;
2992 set_bit(0, ha->req_qid_map);
2993 set_bit(0, ha->rsp_qid_map);
2994 }
2995
08029990
AV		 2996 /* FWI2-capable only. */
2997 req->req_q_in = &ha->iobase->isp24.req_q_in;
2998 req->req_q_out = &ha->iobase->isp24.req_q_out;
2999 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3000 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3001 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3002 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3003 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3004 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3005 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3006 }
3007
8ae6d9c7
GM		 3008 if (IS_QLAFX00(ha)) {
3009 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3010 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3011 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3012 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3013 }
3014
7ec0effd 3015 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3016 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3017 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3018 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3019 }
3020
7c3df132
SK		 3021 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3022 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3023 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3024 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3025 "req->req_q_in=%p req->req_q_out=%p "
3026 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3027 req->req_q_in, req->req_q_out,
3028 rsp->rsp_q_in, rsp->rsp_q_out);
3029 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3030 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3031 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3032 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3033 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3034 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3035
8ae6d9c7 3036 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3037 ql_log(ql_log_fatal, base_vha, 0x00d6,
3038 "Failed to initialize adapter - Adapter flags %x.\n",
3039 base_vha->device_flags);
1da177e4 3040
a9083016
GM		 3041 if (IS_QLA82XX(ha)) {
3042 qla82xx_idc_lock(ha);
3043 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3044 QLA8XXX_DEV_FAILED);
a9083016 3045 qla82xx_idc_unlock(ha);
7c3df132
SK		 3046 ql_log(ql_log_fatal, base_vha, 0x00d7,
3047 "HW State: FAILED.\n");
7ec0effd
AD		 3048 } else if (IS_QLA8044(ha)) {
3049 qla8044_idc_lock(ha);
3050 qla8044_wr_direct(base_vha,
3051 QLA8044_CRB_DEV_STATE_INDEX,
3052 QLA8XXX_DEV_FAILED);
3053 qla8044_idc_unlock(ha);
3054 ql_log(ql_log_fatal, base_vha, 0x0150,
3055 "HW State: FAILED.\n");
a9083016
GM		 3056 }
3057
a1541d5a 3058 ret = -ENODEV;
1da177e4
LT		 3059 goto probe_failed;
3060 }
3061
3b1bef64
CD		 3062 if (IS_QLAFX00(ha))
3063 host->can_queue = QLAFX00_MAX_CANQUEUE;
3064 else
3065 host->can_queue = req->num_outstanding_cmds - 10;
3066
3067 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3068 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3069 host->can_queue, base_vha->req,
3070 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3071
093df737 3072 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3073 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3074 /* Create start of day qpairs for Block MQ */
3075 if (shost_use_blk_mq(host)) {
3076 for (i = 0; i < ha->max_qpairs; i++)
3077 qla2xxx_create_qpair(base_vha, 5, 0);
3078 }
3079 }
68ca949c 3080
cbc8eb67
AV		 3081 if (ha->flags.running_gold_fw)
3082 goto skip_dpc;
3083
1da177e4
LT		 3084 /*
3085 * Startup the kernel thread for this host adapter
3086 */
39a11240 3087 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3088 "%s_dpc", base_vha->host_str);
39a11240 3089 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3090 ql_log(ql_log_fatal, base_vha, 0x00ed,
3091 "Failed to start DPC thread.\n");
39a11240 3092 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3093 goto probe_failed;
3094 }
7c3df132
SK		 3095 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3096 "DPC thread started successfully.\n");
1da177e4 3097
2d70c103
NB		 3098 /*
3099 * If we're not coming up in initiator mode, we might sit for
3100 * a while without waking up the dpc thread, which leads to a
3101 * stuck process warning. So just kick the dpc once here and
3102 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3103 */
3104 qla2xxx_wake_dpc(base_vha);
3105
ec7193e2 3106 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3107 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3108
81178772
SK		 3109 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3110 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3111 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3112 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3113
3114 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3115 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3116 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3117 INIT_WORK(&ha->idc_state_handler,
3118 qla83xx_idc_state_handler_work);
3119 INIT_WORK(&ha->nic_core_unrecoverable,
3120 qla83xx_nic_core_unrecoverable_work);
3121 }
3122
cbc8eb67 3123skip_dpc:
e315cd28
AC		 3124 list_add_tail(&base_vha->list, &ha->vp_list);
3125 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3126
3127 /* Initialized the timer */
e315cd28 3128 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3129 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3130 "Started qla2x00_timer with "
3131 "interval=%d.\n", WATCH_INTERVAL);
3132 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3133 "Detected hba at address=%p.\n",
3134 ha);
d19044c3 3135
e02587d7 3136 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3137 if (ha->fw_attributes & BIT_4) {
9e522cd8 3138 int prot = 0, guard;
bad75002 3139 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3140 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3141 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3142 if (ql2xenabledif == 1)
3143 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3144 scsi_host_set_prot(host,
8cb2049c 3145 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3146 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3147 | SHOST_DIF_TYPE3_PROTECTION
3148 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3149 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3150 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3151
3152 guard = SHOST_DIX_GUARD_CRC;
3153
3154 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3155 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3156 guard |= SHOST_DIX_GUARD_IP;
3157
3158 scsi_host_set_guard(host, guard);
bad75002
AE		 3159 } else
3160 base_vha->flags.difdix_supported = 0;
3161 }
3162
a9083016
GM		 3163 ha->isp_ops->enable_intrs(ha);
3164
1fe19ee4
AB		 3165 if (IS_QLAFX00(ha)) {
3166 ret = qlafx00_fx_disc(base_vha,
3167 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3168 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3169 QLA_SG_ALL : 128;
3170 }
3171
a1541d5a
AV		 3172 ret = scsi_add_host(host, &pdev->dev);
3173 if (ret)
3174 goto probe_failed;
3175
1486400f
MR		 3176 base_vha->flags.init_done = 1;
3177 base_vha->flags.online = 1;
edaa5c74 3178 ha->prev_minidump_failed = 0;
1486400f 3179
7c3df132
SK		 3180 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3181 "Init done and hba is online.\n");
3182
726b8548
QT		 3183 if (qla_ini_mode_enabled(base_vha) ||
3184 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3185 scsi_scan_host(host);
3186 else
3187 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3188 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3189
e315cd28 3190 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3191
8ae6d9c7 3192 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3193 ret = qlafx00_fx_disc(base_vha,
3194 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3195
3196 /* Register system information */
3197 ret = qlafx00_fx_disc(base_vha,
3198 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3199 }
3200
e315cd28 3201 qla2x00_init_host_attr(base_vha);
a1541d5a 3202
e315cd28 3203 qla2x00_dfs_setup(base_vha);
df613b96 3204
03eb912a
AB		 3205 ql_log(ql_log_info, base_vha, 0x00fb,
3206 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3207 ql_log(ql_log_info, base_vha, 0x00fc,
3208 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3209 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3210 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3211 base_vha->host_no,
df57caba 3212 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3213
2d70c103
NB		 3214 qlt_add_target(ha, base_vha);
3215
6b383979 3216 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3217
3218 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3219 return -ENODEV;
3220
1da177e4
LT		 3221 return 0;
3222
6e9f21f3 3223probe_init_failed:
2afa19a9 3224 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3225 ha->req_q_map[0] = NULL;
3226 clear_bit(0, ha->req_qid_map);
2afa19a9 3227 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3228 ha->rsp_q_map[0] = NULL;
3229 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3230 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3231
1da177e4 3232probe_failed:
b9978769
AV		 3233 if (base_vha->timer_active)
3234 qla2x00_stop_timer(base_vha);
3235 base_vha->flags.online = 0;
3236 if (ha->dpc_thread) {
3237 struct task_struct *t = ha->dpc_thread;
3238
3239 ha->dpc_thread = NULL;
3240 kthread_stop(t);
3241 }
3242
e315cd28 3243 qla2x00_free_device(base_vha);
1da177e4 3244
e315cd28 3245 scsi_host_put(base_vha->host);
1da177e4 3246
e315cd28 3247probe_hw_failed:
1a2fbf18
JL		 3248 qla2x00_clear_drv_active(ha);
3249
0a63ad12 3250iospace_config_failed:
7ec0effd 3251 if (IS_P3P_TYPE(ha)) {
0a63ad12 3252 if (!ha->nx_pcibase)
f73cb695 3253 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3254 if (!ql2xdbwr)
f73cb695 3255 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3256 } else {
3257 if (ha->iobase)
3258 iounmap(ha->iobase);
8ae6d9c7
GM		 3259 if (ha->cregbase)
3260 iounmap(ha->cregbase);
a9083016 3261 }
e315cd28
AC		 3262 pci_release_selected_regions(ha->pdev, ha->bars);
3263 kfree(ha);
1da177e4 3264
ddff7ed4 3265disable_device:
e315cd28 3266 pci_disable_device(pdev);
a1541d5a 3267 return ret;
1da177e4 3268}
1da177e4 3269
e30d1756
MI		 3270static void
3271qla2x00_shutdown(struct pci_dev *pdev)
3272{
3273 scsi_qla_host_t *vha;
3274 struct qla_hw_data *ha;
3275
552f3f9a
MI		 3276 if (!atomic_read(&pdev->enable_cnt))
3277 return;
3278
e30d1756
MI		 3279 vha = pci_get_drvdata(pdev);
3280 ha = vha->hw;
3281
42479343
AB		 3282 /* Notify ISPFX00 firmware */
3283 if (IS_QLAFX00(ha))
3284 qlafx00_driver_shutdown(vha, 20);
3285
e30d1756
MI		 3286 /* Turn-off FCE trace */
3287 if (ha->flags.fce_enabled) {
3288 qla2x00_disable_fce_trace(vha, NULL, NULL);
3289 ha->flags.fce_enabled = 0;
3290 }
3291
3292 /* Turn-off EFT trace */
3293 if (ha->eft)
3294 qla2x00_disable_eft_trace(vha);
3295
3296 /* Stop currently executing firmware. */
3297 qla2x00_try_to_stop_firmware(vha);
3298
3299 /* Turn adapter off line */
3300 vha->flags.online = 0;
3301
3302 /* turn-off interrupts on the card */
3303 if (ha->interrupts_on) {
3304 vha->flags.init_done = 0;
3305 ha->isp_ops->disable_intrs(ha);
3306 }
3307
3308 qla2x00_free_irqs(vha);
3309
3310 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3311
3312 pci_disable_pcie_error_reporting(pdev);
3313 pci_disable_device(pdev);
e30d1756
MI		 3314}
3315
fe1b806f 3316/* Deletes all the virtual ports for a given ha */
4c993f76 3317static void
fe1b806f 3318qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3319{
fe1b806f 3320 scsi_qla_host_t *vha;
feafb7b1 3321 unsigned long flags;
e315cd28 3322
43ebf16d
AE		 3323 mutex_lock(&ha->vport_lock);
3324 while (ha->cur_vport_count) {
43ebf16d 3325 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3326
43ebf16d
AE		 3327 BUG_ON(base_vha->list.next == &ha->vp_list);
3328 /* This assumes first entry in ha->vp_list is always base vha */
3329 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3330 scsi_host_get(vha->host);
feafb7b1 3331
43ebf16d
AE		 3332 spin_unlock_irqrestore(&ha->vport_slock, flags);
3333 mutex_unlock(&ha->vport_lock);
3334
3335 fc_vport_terminate(vha->fc_vport);
3336 scsi_host_put(vha->host);
feafb7b1 3337
43ebf16d 3338 mutex_lock(&ha->vport_lock);
e315cd28 3339 }
43ebf16d 3340 mutex_unlock(&ha->vport_lock);
fe1b806f 3341}
1da177e4 3342
fe1b806f
CD		 3343/* Stops all deferred work threads */
3344static void
3345qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3346{
7d613ac6
SV		 3347 /* Cancel all work and destroy DPC workqueues */
3348 if (ha->dpc_lp_wq) {
3349 cancel_work_sync(&ha->idc_aen);
3350 destroy_workqueue(ha->dpc_lp_wq);
3351 ha->dpc_lp_wq = NULL;
3352 }
3353
3354 if (ha->dpc_hp_wq) {
3355 cancel_work_sync(&ha->nic_core_reset);
3356 cancel_work_sync(&ha->idc_state_handler);
3357 cancel_work_sync(&ha->nic_core_unrecoverable);
3358 destroy_workqueue(ha->dpc_hp_wq);
3359 ha->dpc_hp_wq = NULL;
3360 }
3361
b9978769
AV		 3362 /* Kill the kernel thread for this host */
3363 if (ha->dpc_thread) {
3364 struct task_struct *t = ha->dpc_thread;
3365
3366 /*
3367 * qla2xxx_wake_dpc checks for ->dpc_thread
3368 * so we need to zero it out.
3369 */
3370 ha->dpc_thread = NULL;
3371 kthread_stop(t);
3372 }
fe1b806f 3373}
1da177e4 3374
fe1b806f
CD		 3375static void
3376qla2x00_unmap_iobases(struct qla_hw_data *ha)
3377{
a9083016 3378 if (IS_QLA82XX(ha)) {
b963752f 3379
f73cb695 3380 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3381 if (!ql2xdbwr)
f73cb695 3382 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3383 } else {
3384 if (ha->iobase)
3385 iounmap(ha->iobase);
1da177e4 3386
8ae6d9c7
GM		 3387 if (ha->cregbase)
3388 iounmap(ha->cregbase);
3389
a9083016
GM		 3390 if (ha->mqiobase)
3391 iounmap(ha->mqiobase);
6246b8a1 3392
f73cb695 3393 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3394 iounmap(ha->msixbase);
a9083016 3395 }
fe1b806f
CD		 3396}
3397
3398static void
db7157d4 3399qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3400{
fe1b806f
CD		 3401 if (IS_QLA8044(ha)) {
3402 qla8044_idc_lock(ha);
c41afc9a 3403 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3404 qla8044_idc_unlock(ha);
3405 } else if (IS_QLA82XX(ha)) {
3406 qla82xx_idc_lock(ha);
3407 qla82xx_clear_drv_active(ha);
3408 qla82xx_idc_unlock(ha);
3409 }
3410}
3411
3412static void
3413qla2x00_remove_one(struct pci_dev *pdev)
3414{
3415 scsi_qla_host_t *base_vha;
3416 struct qla_hw_data *ha;
3417
beb9e315
JL		 3418 base_vha = pci_get_drvdata(pdev);
3419 ha = base_vha->hw;
3420
3421 /* Indicate device removal to prevent future board_disable and wait
3422 * until any pending board_disable has completed. */
3423 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3424 cancel_work_sync(&ha->board_disable);
3425
fe1b806f 3426 /*
beb9e315
JL		 3427 * If the PCI device is disabled then there was a PCI-disconnect and
3428 * qla2x00_disable_board_on_pci_error has taken care of most of the
3429 * resources.
fe1b806f 3430 */
beb9e315 3431 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3432 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3433 base_vha->gnl.l, base_vha->gnl.ldma);
3434
beb9e315
JL		 3435 scsi_host_put(base_vha->host);
3436 kfree(ha);
3437 pci_set_drvdata(pdev, NULL);
fe1b806f 3438 return;
beb9e315 3439 }
638a1a01
SC		 3440 qla2x00_wait_for_hba_ready(base_vha);
3441
726b8548
QT		 3442 /*
3443 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3444 * where it was set first.
3445 */
3446 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3447 return;
3448
fe1b806f 3449 set_bit(UNLOADING, &base_vha->dpc_flags);
726b8548
QT		 3450 dma_free_coherent(&ha->pdev->dev,
3451 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3452
3453 if (IS_QLAFX00(ha))
3454 qlafx00_driver_shutdown(base_vha, 20);
3455
3456 qla2x00_delete_all_vps(ha, base_vha);
3457
3458 if (IS_QLA8031(ha)) {
3459 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3460 "Clearing fcoe driver presence.\n");
3461 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3462 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3463 "Error while clearing DRV-Presence.\n");
3464 }
3465
3466 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3467
3468 qla2x00_dfs_remove(base_vha);
3469
3470 qla84xx_put_chip(base_vha);
3471
2d5a4c34
HM		 3472 /* Laser should be disabled only for ISP2031 */
3473 if (IS_QLA2031(ha))
3474 qla83xx_disable_laser(base_vha);
3475
fe1b806f
CD		 3476 /* Disable timer */
3477 if (base_vha->timer_active)
3478 qla2x00_stop_timer(base_vha);
3479
3480 base_vha->flags.online = 0;
3481
b0d6cabd
HM		 3482 /* free DMA memory */
3483 if (ha->exlogin_buf)
3484 qla2x00_free_exlogin_buffer(ha);
3485
2f56a7f1
HM		 3486 /* free DMA memory */
3487 if (ha->exchoffld_buf)
3488 qla2x00_free_exchoffld_buffer(ha);
3489
fe1b806f
CD		 3490 qla2x00_destroy_deferred_work(ha);
3491
3492 qlt_remove_target(ha, base_vha);
3493
3494 qla2x00_free_sysfs_attr(base_vha, true);
3495
3496 fc_remove_host(base_vha->host);
482c9dc7 3497 qlt_remove_target_resources(ha);
fe1b806f
CD		 3498
3499 scsi_remove_host(base_vha->host);
3500
3501 qla2x00_free_device(base_vha);
3502
db7157d4 3503 qla2x00_clear_drv_active(ha);
fe1b806f 3504
d2749ffa
AE		 3505 scsi_host_put(base_vha->host);
3506
fe1b806f 3507 qla2x00_unmap_iobases(ha);
73208dfd 3508
e315cd28
AC		 3509 pci_release_selected_regions(ha->pdev, ha->bars);
3510 kfree(ha);
1da177e4 3511
90a86fc0
JC		 3512 pci_disable_pcie_error_reporting(pdev);
3513
665db93b 3514 pci_disable_device(pdev);
1da177e4 3515}
1da177e4
LT		 3516
3517static void
e315cd28 3518qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3519{
e315cd28 3520 struct qla_hw_data *ha = vha->hw;
1da177e4 3521
85880801
AV		 3522 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3523
3524 /* Disable timer */
3525 if (vha->timer_active)
3526 qla2x00_stop_timer(vha);
3527
2afa19a9 3528 qla25xx_delete_queues(vha);
fe1b806f 3529
df613b96 3530 if (ha->flags.fce_enabled)
e315cd28 3531 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3532
a7a167bf 3533 if (ha->eft)
e315cd28 3534 qla2x00_disable_eft_trace(vha);
a7a167bf 3535
f6ef3b18 3536 /* Stop currently executing firmware. */
e315cd28 3537 qla2x00_try_to_stop_firmware(vha);
1da177e4 3538
85880801
AV		 3539 vha->flags.online = 0;
3540
f6ef3b18 3541 /* turn-off interrupts on the card */
a9083016
GM		 3542 if (ha->interrupts_on) {
3543 vha->flags.init_done = 0;
fd34f556 3544 ha->isp_ops->disable_intrs(ha);
a9083016 3545 }
f6ef3b18 3546
093df737
QT		 3547 qla2x00_free_fcports(vha);
3548
e315cd28 3549 qla2x00_free_irqs(vha);
1da177e4 3550
093df737
QT		 3551 /* Flush the work queue and remove it */
3552 if (ha->wq) {
3553 flush_workqueue(ha->wq);
3554 destroy_workqueue(ha->wq);
3555 ha->wq = NULL;
3556 }
3557
8867048b 3558
e315cd28 3559 qla2x00_mem_free(ha);
73208dfd 3560
08de2844
GM		 3561 qla82xx_md_free(vha);
3562
73208dfd 3563 qla2x00_free_queues(ha);
1da177e4
LT		 3564}
3565
8867048b
CD		 3566void qla2x00_free_fcports(struct scsi_qla_host *vha)
3567{
3568 fc_port_t *fcport, *tfcport;
3569
3570 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3571 list_del(&fcport->list);
5f16b331 3572 qla2x00_clear_loop_id(fcport);
8867048b 3573 kfree(fcport);
8867048b
CD		 3574 }
3575}
3576
d97994dc 3577static inline void
e315cd28 3578qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3579 int defer)
3580{
d97994dc 3581 struct fc_rport *rport;
67becc00 3582 scsi_qla_host_t *base_vha;
044d78e1 3583 unsigned long flags;
d97994dc
AV		 3584
3585 if (!fcport->rport)
3586 return;
3587
3588 rport = fcport->rport;
3589 if (defer) {
67becc00 3590 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3591 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3592 fcport->drport = rport;
044d78e1 3593 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3594 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3595 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3596 qla2xxx_wake_dpc(base_vha);
2d70c103 3597 } else {
df673274 3598 int now;
726b8548
QT		 3599 if (rport) {
3600 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3601 "%s %8phN. rport %p roles %x \n",
3602 __func__, fcport->port_name, rport,
3603 rport->roles);
d20ed91b 3604 fc_remote_port_delete(rport);
726b8548 3605 }
df673274 3606 qlt_do_generation_tick(vha, &now);
2d70c103 3607 }
d97994dc
AV		 3608}
3609
1da177e4
LT		 3610/*
3611 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3612 *
3613 * Input: ha = adapter block pointer. fcport = port structure pointer.
3614 *
3615 * Return: None.
3616 *
3617 * Context:
3618 */
e315cd28 3619void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3620 int do_login, int defer)
1da177e4 3621{
8ae6d9c7
GM		 3622 if (IS_QLAFX00(vha->hw)) {
3623 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3624 qla2x00_schedule_rport_del(vha, fcport, defer);
3625 return;
3626 }
3627
2c3dfe3f 3628 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3629 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3630 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3631 qla2x00_schedule_rport_del(vha, fcport, defer);
3632 }
fa2a1ce5 3633 /*
1da177e4
LT		 3634 * We may need to retry the login, so don't change the state of the
3635 * port but do the retries.
3636 */
3637 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3638 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3639
3640 if (!do_login)
3641 return;
3642
a1d0285e
AE		 3643 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3644
1da177e4 3645 if (fcport->login_retry == 0) {
e315cd28 3646 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3647
7c3df132 3648 ql_dbg(ql_dbg_disc, vha, 0x2067,
726b8548 3649 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3650 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3651 }
3652}
3653
3654/*
3655 * qla2x00_mark_all_devices_lost
3656 * Updates fcport state when device goes offline.
3657 *
3658 * Input:
3659 * ha = adapter block pointer.
3660 * fcport = port structure pointer.
3661 *
3662 * Return:
3663 * None.
3664 *
3665 * Context:
3666 */
3667void
e315cd28 3668qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3669{
3670 fc_port_t *fcport;
3671
726b8548
QT		 3672 ql_dbg(ql_dbg_disc, vha, 0xffff,
3673 "Mark all dev lost\n");
3674
e315cd28 3675 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3676 fcport->scan_state = 0;
3677 qlt_schedule_sess_for_deletion_lock(fcport);
3678
c6d39e23 3679 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3680 continue;
0d6e61bc 3681
1da177e4
LT		 3682 /*
3683 * No point in marking the device as lost, if the device is
3684 * already DEAD.
3685 */
3686 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3687 continue;
e315cd28 3688 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3689 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3690 if (defer)
3691 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3692 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3693 qla2x00_schedule_rport_del(vha, fcport, defer);
3694 }
1da177e4
LT		 3695 }
3696}
3697
3698/*
3699* qla2x00_mem_alloc
3700* Allocates adapter memory.
3701*
3702* Returns:
3703* 0 = success.
e8711085 3704* !0 = failure.
1da177e4 3705*/
e8711085 3706static int
73208dfd
AC		 3707qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3708 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3709{
3710 char name[16];
1da177e4 3711
e8711085 3712 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3713 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3714 if (!ha->init_cb)
e315cd28 3715 goto fail;
e8711085 3716
2d70c103
NB		 3717 if (qlt_mem_alloc(ha) < 0)
3718 goto fail_free_init_cb;
3719
642ef983
CD		 3720 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3721 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3722 if (!ha->gid_list)
2d70c103 3723 goto fail_free_tgt_mem;
1da177e4 3724
e8711085
AV		 3725 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3726 if (!ha->srb_mempool)
e315cd28 3727 goto fail_free_gid_list;
e8711085 3728
7ec0effd 3729 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3730 /* Allocate cache for CT6 Ctx. */
3731 if (!ctx_cachep) {
3732 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3733 sizeof(struct ct6_dsd), 0,
3734 SLAB_HWCACHE_ALIGN, NULL);
3735 if (!ctx_cachep)
fc1ffd6c 3736 goto fail_free_srb_mempool;
a9083016
GM		 3737 }
3738 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3739 ctx_cachep);
3740 if (!ha->ctx_mempool)
3741 goto fail_free_srb_mempool;
7c3df132
SK		 3742 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3743 "ctx_cachep=%p ctx_mempool=%p.\n",
3744 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3745 }
3746
e8711085
AV		 3747 /* Get memory for cached NVRAM */
3748 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3749 if (!ha->nvram)
a9083016 3750 goto fail_free_ctx_mempool;
e8711085 3751
e315cd28
AC		 3752 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3753 ha->pdev->device);
3754 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3755 DMA_POOL_SIZE, 8, 0);
3756 if (!ha->s_dma_pool)
3757 goto fail_free_nvram;
3758
7c3df132
SK		 3759 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3760 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3761 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3762
7ec0effd 3763 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3764 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3765 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3766 if (!ha->dl_dma_pool) {
7c3df132
SK		 3767 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3768 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3769 goto fail_s_dma_pool;
3770 }
3771
3772 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3773 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3774 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3775 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3776 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3777 goto fail_dl_dma_pool;
3778 }
7c3df132
SK		 3779 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3780 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3781 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3782 }
3783
e8711085
AV		 3784 /* Allocate memory for SNS commands */
3785 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3786 /* Get consistent memory allocated for SNS commands */
e8711085 3787 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3788 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3789 if (!ha->sns_cmd)
e315cd28 3790 goto fail_dma_pool;
7c3df132 3791 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3792 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3793 } else {
e315cd28 3794 /* Get consistent memory allocated for MS IOCB */
e8711085 3795 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3796 &ha->ms_iocb_dma);
e8711085 3797 if (!ha->ms_iocb)
e315cd28
AC		 3798 goto fail_dma_pool;
3799 /* Get consistent memory allocated for CT SNS commands */
e8711085 3800 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3801 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3802 if (!ha->ct_sns)
3803 goto fail_free_ms_iocb;
7c3df132
SK		 3804 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3805 "ms_iocb=%p ct_sns=%p.\n",
3806 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3807 }
3808
e315cd28 3809 /* Allocate memory for request ring */
73208dfd
AC		 3810 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3811 if (!*req) {
7c3df132
SK		 3812 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3813 "Failed to allocate memory for req.\n");
e315cd28
AC		 3814 goto fail_req;
3815 }
73208dfd
AC		 3816 (*req)->length = req_len;
3817 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3818 ((*req)->length + 1) * sizeof(request_t),
3819 &(*req)->dma, GFP_KERNEL);
3820 if (!(*req)->ring) {
7c3df132
SK		 3821 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3822 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3823 goto fail_req_ring;
3824 }
3825 /* Allocate memory for response ring */
73208dfd
AC		 3826 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3827 if (!*rsp) {
7c3df132
SK		 3828 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3829 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3830 goto fail_rsp;
3831 }
73208dfd
AC		 3832 (*rsp)->hw = ha;
3833 (*rsp)->length = rsp_len;
3834 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3835 ((*rsp)->length + 1) * sizeof(response_t),
3836 &(*rsp)->dma, GFP_KERNEL);
3837 if (!(*rsp)->ring) {
7c3df132
SK		 3838 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3839 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3840 goto fail_rsp_ring;
3841 }
73208dfd
AC		 3842 (*req)->rsp = *rsp;
3843 (*rsp)->req = *req;
7c3df132
SK		 3844 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3845 "req=%p req->length=%d req->ring=%p rsp=%p "
3846 "rsp->length=%d rsp->ring=%p.\n",
3847 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3848 (*rsp)->ring);
73208dfd
AC		 3849 /* Allocate memory for NVRAM data for vports */
3850 if (ha->nvram_npiv_size) {
3851 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3852 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3853 if (!ha->npiv_info) {
7c3df132
SK		 3854 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3855 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3856 goto fail_npiv_info;
3857 }
3858 } else
3859 ha->npiv_info = NULL;
e8711085 3860
b64b0e8f 3861 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3862 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3863 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3864 &ha->ex_init_cb_dma);
3865 if (!ha->ex_init_cb)
3866 goto fail_ex_init_cb;
7c3df132
SK		 3867 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3868 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3869 }
3870
a9083016
GM		 3871 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3872
5ff1d584
AV		 3873 /* Get consistent memory allocated for Async Port-Database. */
3874 if (!IS_FWI2_CAPABLE(ha)) {
3875 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3876 &ha->async_pd_dma);
3877 if (!ha->async_pd)
3878 goto fail_async_pd;
7c3df132
SK		 3879 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3880 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3881 }
3882
e315cd28 3883 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3884
3885 /* Allocate memory for our loop_id bitmap */
3886 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3887 GFP_KERNEL);
3888 if (!ha->loop_id_map)
fc1ffd6c 3889 goto fail_loop_id_map;
5f16b331
CD		 3890 else {
3891 qla2x00_set_reserved_loop_ids(ha);
3892 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3893 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3894 }
3895
b2a72ec3 3896 return 0;
e315cd28 3897
fc1ffd6c
QT		 3898fail_loop_id_map:
3899 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3900fail_async_pd:
3901 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3902fail_ex_init_cb:
3903 kfree(ha->npiv_info);
73208dfd
AC		 3904fail_npiv_info:
3905 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3906 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3907 (*rsp)->ring = NULL;
3908 (*rsp)->dma = 0;
e315cd28 3909fail_rsp_ring:
73208dfd 3910 kfree(*rsp);
e315cd28 3911fail_rsp:
73208dfd
AC		 3912 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3913 sizeof(request_t), (*req)->ring, (*req)->dma);
3914 (*req)->ring = NULL;
3915 (*req)->dma = 0;
e315cd28 3916fail_req_ring:
73208dfd 3917 kfree(*req);
e315cd28
AC		 3918fail_req:
3919 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3920 ha->ct_sns, ha->ct_sns_dma);
3921 ha->ct_sns = NULL;
3922 ha->ct_sns_dma = 0;
e8711085
AV		 3923fail_free_ms_iocb:
3924 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3925 ha->ms_iocb = NULL;
3926 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3927
3928 if (ha->sns_cmd)
3929 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3930 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3931fail_dma_pool:
bad75002 3932 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3933 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3934 ha->fcp_cmnd_dma_pool = NULL;
3935 }
3936fail_dl_dma_pool:
bad75002 3937 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3938 dma_pool_destroy(ha->dl_dma_pool);
3939 ha->dl_dma_pool = NULL;
3940 }
3941fail_s_dma_pool:
e315cd28
AC		 3942 dma_pool_destroy(ha->s_dma_pool);
3943 ha->s_dma_pool = NULL;
e8711085
AV		 3944fail_free_nvram:
3945 kfree(ha->nvram);
3946 ha->nvram = NULL;
a9083016 3947fail_free_ctx_mempool:
fc1ffd6c
QT		 3948 if (ha->ctx_mempool)
3949 mempool_destroy(ha->ctx_mempool);
a9083016 3950 ha->ctx_mempool = NULL;
e8711085 3951fail_free_srb_mempool:
fc1ffd6c
QT		 3952 if (ha->srb_mempool)
3953 mempool_destroy(ha->srb_mempool);
e8711085 3954 ha->srb_mempool = NULL;
e8711085 3955fail_free_gid_list:
642ef983
CD		 3956 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3957 ha->gid_list,
e315cd28 3958 ha->gid_list_dma);
e8711085
AV		 3959 ha->gid_list = NULL;
3960 ha->gid_list_dma = 0;
2d70c103
NB		 3961fail_free_tgt_mem:
3962 qlt_mem_free(ha);
e315cd28
AC		 3963fail_free_init_cb:
3964 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3965 ha->init_cb_dma);
3966 ha->init_cb = NULL;
3967 ha->init_cb_dma = 0;
e8711085 3968fail:
7c3df132
SK		 3969 ql_log(ql_log_fatal, NULL, 0x0030,
3970 "Memory allocation failure.\n");
e8711085 3971 return -ENOMEM;
1da177e4
LT		 3972}
3973
b0d6cabd
HM		 3974int
3975qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3976{
3977 int rval;
3978 uint16_t size, max_cnt, temp;
3979 struct qla_hw_data *ha = vha->hw;
3980
3981 /* Return if we don't need to alloacate any extended logins */
3982 if (!ql2xexlogins)
3983 return QLA_SUCCESS;
3984
3985 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3986 max_cnt = 0;
3987 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3988 if (rval != QLA_SUCCESS) {
3989 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3990 "Failed to get exlogin status.\n");
3991 return rval;
3992 }
3993
3994 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3995 ha->exlogin_size = (size * temp);
3996 ql_log(ql_log_info, vha, 0xd024,
3997 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3998 max_cnt, size, temp);
3999
4000 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
4001 ha->exlogin_size);
4002
4003 /* Get consistent memory for extended logins */
4004 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4005 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4006 if (!ha->exlogin_buf) {
4007 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4008 "Failed to allocate memory for exlogin_buf_dma.\n");
4009 return -ENOMEM;
4010 }
4011
4012 /* Now configure the dma buffer */
4013 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4014 if (rval) {
4015 ql_log(ql_log_fatal, vha, 0x00cf,
4016 "Setup extended login buffer ****FAILED****.\n");
4017 qla2x00_free_exlogin_buffer(ha);
4018 }
4019
4020 return rval;
4021}
4022
4023/*
4024* qla2x00_free_exlogin_buffer
4025*
4026* Input:
4027* ha = adapter block pointer
4028*/
4029void
4030qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4031{
4032 if (ha->exlogin_buf) {
4033 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4034 ha->exlogin_buf, ha->exlogin_buf_dma);
4035 ha->exlogin_buf = NULL;
4036 ha->exlogin_size = 0;
4037 }
4038}
4039
2f56a7f1
HM		 4040int
4041qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4042{
4043 int rval;
4044 uint16_t size, max_cnt, temp;
4045 struct qla_hw_data *ha = vha->hw;
4046
4047 /* Return if we don't need to alloacate any extended logins */
4048 if (!ql2xexchoffld)
4049 return QLA_SUCCESS;
4050
4051 ql_log(ql_log_info, vha, 0xd014,
4052 "Exchange offload count: %d.\n", ql2xexlogins);
4053
4054 max_cnt = 0;
4055 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4056 if (rval != QLA_SUCCESS) {
4057 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4058 "Failed to get exlogin status.\n");
4059 return rval;
4060 }
4061
4062 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
4063 ha->exchoffld_size = (size * temp);
4064 ql_log(ql_log_info, vha, 0xd016,
4065 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4066 max_cnt, size, temp);
4067
4068 ql_log(ql_log_info, vha, 0xd017,
4069 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
4070
4071 /* Get consistent memory for extended logins */
4072 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4073 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4074 if (!ha->exchoffld_buf) {
4075 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4076 "Failed to allocate memory for exchoffld_buf_dma.\n");
4077 return -ENOMEM;
4078 }
4079
4080 /* Now configure the dma buffer */
4081 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4082 if (rval) {
4083 ql_log(ql_log_fatal, vha, 0xd02e,
4084 "Setup exchange offload buffer ****FAILED****.\n");
4085 qla2x00_free_exchoffld_buffer(ha);
4086 }
4087
4088 return rval;
4089}
4090
4091/*
4092* qla2x00_free_exchoffld_buffer
4093*
4094* Input:
4095* ha = adapter block pointer
4096*/
4097void
4098qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4099{
4100 if (ha->exchoffld_buf) {
4101 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4102 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4103 ha->exchoffld_buf = NULL;
4104 ha->exchoffld_size = 0;
4105 }
4106}
4107
1da177e4 4108/*
e30d1756
MI		 4109* qla2x00_free_fw_dump
4110* Frees fw dump stuff.
1da177e4
LT		 4111*
4112* Input:
7ec0effd 4113* ha = adapter block pointer
1da177e4 4114*/
a824ebb3 4115static void
e30d1756 4116qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4117{
df613b96 4118 if (ha->fce)
f73cb695
CD		 4119 dma_free_coherent(&ha->pdev->dev,
4120 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4121
f73cb695
CD		 4122 if (ha->eft)
4123 dma_free_coherent(&ha->pdev->dev,
4124 EFT_SIZE, ha->eft, ha->eft_dma);
4125
4126 if (ha->fw_dump)
a7a167bf 4127 vfree(ha->fw_dump);
f73cb695
CD		 4128 if (ha->fw_dump_template)
4129 vfree(ha->fw_dump_template);
4130
e30d1756
MI		 4131 ha->fce = NULL;
4132 ha->fce_dma = 0;
4133 ha->eft = NULL;
4134 ha->eft_dma = 0;
e30d1756 4135 ha->fw_dumped = 0;
61f098dd 4136 ha->fw_dump_cap_flags = 0;
e30d1756 4137 ha->fw_dump_reading = 0;
f73cb695
CD		 4138 ha->fw_dump = NULL;
4139 ha->fw_dump_len = 0;
4140 ha->fw_dump_template = NULL;
4141 ha->fw_dump_template_len = 0;
e30d1756
MI		 4142}
4143
4144/*
4145* qla2x00_mem_free
4146* Frees all adapter allocated memory.
4147*
4148* Input:
4149* ha = adapter block pointer.
4150*/
4151static void
4152qla2x00_mem_free(struct qla_hw_data *ha)
4153{
4154 qla2x00_free_fw_dump(ha);
4155
81178772
SK		 4156 if (ha->mctp_dump)
4157 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4158 ha->mctp_dump_dma);
4159
e30d1756
MI		 4160 if (ha->srb_mempool)
4161 mempool_destroy(ha->srb_mempool);
a7a167bf 4162
11bbc1d8
AV		 4163 if (ha->dcbx_tlv)
4164 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4165 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4166
ce0423f4
AV		 4167 if (ha->xgmac_data)
4168 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4169 ha->xgmac_data, ha->xgmac_data_dma);
4170
1da177e4
LT		 4171 if (ha->sns_cmd)
4172 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4173 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4174
4175 if (ha->ct_sns)
4176 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4177 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4178
88729e53
AV		 4179 if (ha->sfp_data)
4180 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4181
1da177e4
LT		 4182 if (ha->ms_iocb)
4183 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4184
b64b0e8f 4185 if (ha->ex_init_cb)
a9083016
GM		 4186 dma_pool_free(ha->s_dma_pool,
4187 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4188
5ff1d584
AV		 4189 if (ha->async_pd)
4190 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4191
1da177e4
LT		 4192 if (ha->s_dma_pool)
4193 dma_pool_destroy(ha->s_dma_pool);
4194
1da177e4 4195 if (ha->gid_list)
642ef983
CD		 4196 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4197 ha->gid_list, ha->gid_list_dma);
1da177e4 4198
a9083016
GM		 4199 if (IS_QLA82XX(ha)) {
4200 if (!list_empty(&ha->gbl_dsd_list)) {
4201 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4202
4203 /* clean up allocated prev pool */
4204 list_for_each_entry_safe(dsd_ptr,
4205 tdsd_ptr, &ha->gbl_dsd_list, list) {
4206 dma_pool_free(ha->dl_dma_pool,
4207 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4208 list_del(&dsd_ptr->list);
4209 kfree(dsd_ptr);
4210 }
4211 }
4212 }
4213
4214 if (ha->dl_dma_pool)
4215 dma_pool_destroy(ha->dl_dma_pool);
4216
4217 if (ha->fcp_cmnd_dma_pool)
4218 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4219
4220 if (ha->ctx_mempool)
4221 mempool_destroy(ha->ctx_mempool);
4222
2d70c103
NB		 4223 qlt_mem_free(ha);
4224
e315cd28
AC		 4225 if (ha->init_cb)
4226 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4227 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4228 vfree(ha->optrom_buffer);
4229 kfree(ha->nvram);
73208dfd 4230 kfree(ha->npiv_info);
7a67735b 4231 kfree(ha->swl);
5f16b331 4232 kfree(ha->loop_id_map);
1da177e4 4233
e8711085 4234 ha->srb_mempool = NULL;
a9083016 4235 ha->ctx_mempool = NULL;
1da177e4
LT		 4236 ha->sns_cmd = NULL;
4237 ha->sns_cmd_dma = 0;
4238 ha->ct_sns = NULL;
4239 ha->ct_sns_dma = 0;
4240 ha->ms_iocb = NULL;
4241 ha->ms_iocb_dma = 0;
1da177e4
LT		 4242 ha->init_cb = NULL;
4243 ha->init_cb_dma = 0;
b64b0e8f
AV		 4244 ha->ex_init_cb = NULL;
4245 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4246 ha->async_pd = NULL;
4247 ha->async_pd_dma = 0;
1da177e4
LT		 4248
4249 ha->s_dma_pool = NULL;
a9083016
GM		 4250 ha->dl_dma_pool = NULL;
4251 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4252
1da177e4
LT		 4253 ha->gid_list = NULL;
4254 ha->gid_list_dma = 0;
2d70c103
NB		 4255
4256 ha->tgt.atio_ring = NULL;
4257 ha->tgt.atio_dma = 0;
4258 ha->tgt.tgt_vp_map = NULL;
e315cd28 4259}
1da177e4 4260
e315cd28
AC		 4261struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4262 struct qla_hw_data *ha)
4263{
4264 struct Scsi_Host *host;
4265 struct scsi_qla_host *vha = NULL;
854165f4 4266
e315cd28 4267 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4268 if (!host) {
7c3df132
SK		 4269 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4270 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4271 return NULL;
e315cd28
AC		 4272 }
4273
4274 /* Clear our data area */
4275 vha = shost_priv(host);
4276 memset(vha, 0, sizeof(scsi_qla_host_t));
4277
4278 vha->host = host;
4279 vha->host_no = host->host_no;
4280 vha->hw = ha;
4281
4282 INIT_LIST_HEAD(&vha->vp_fcports);
4283 INIT_LIST_HEAD(&vha->work_list);
4284 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4285 INIT_LIST_HEAD(&vha->qla_cmd_list);
4286 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4287 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4288 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4289 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4290 INIT_LIST_HEAD(&vha->gnl.fcports);
e315cd28 4291
f999f4c1 4292 spin_lock_init(&vha->work_lock);
8b2f5ff3 4293 spin_lock_init(&vha->cmd_list_lock);
726b8548 4294 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4295 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4296
2fdbc65e
BVA		 4297 vha->gnl.size = sizeof(struct get_name_list_extended) *
4298 (ha->max_loop_id + 1);
41dc529a
QT		 4299 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4300 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4301 if (!vha->gnl.l) {
4302 ql_log(ql_log_fatal, vha, 0xffff,
4303 "Alloc failed for name list.\n");
4304 scsi_remove_host(vha->host);
4305 return NULL;
4306 }
f999f4c1 4307
e315cd28 4308 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4309 ql_dbg(ql_dbg_init, vha, 0x0041,
4310 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4311 vha->host, vha->hw, vha,
4312 dev_name(&(ha->pdev->dev)));
4313
e315cd28 4314 return vha;
1da177e4
LT		 4315}
4316
726b8548 4317struct qla_work_evt *
f999f4c1 4318qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4319{
4320 struct qla_work_evt *e;
feafb7b1
AE		 4321 uint8_t bail;
4322
4323 QLA_VHA_MARK_BUSY(vha, bail);
4324 if (bail)
4325 return NULL;
0971de7f 4326
f999f4c1 4327 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4328 if (!e) {
4329 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4330 return NULL;
feafb7b1 4331 }
0971de7f
AV		 4332
4333 INIT_LIST_HEAD(&e->list);
4334 e->type = type;
4335 e->flags = QLA_EVT_FLAG_FREE;
4336 return e;
4337}
4338
726b8548 4339int
f999f4c1 4340qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4341{
f999f4c1 4342 unsigned long flags;
0971de7f 4343
f999f4c1 4344 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4345 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4346 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4347
4348 if (QLA_EARLY_LINKUP(vha->hw))
4349 schedule_work(&vha->iocb_work);
4350 else
4351 qla2xxx_wake_dpc(vha);
f999f4c1 4352
0971de7f
AV		 4353 return QLA_SUCCESS;
4354}
4355
4356int
e315cd28 4357qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4358 u32 data)
4359{
4360 struct qla_work_evt *e;
4361
f999f4c1 4362 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4363 if (!e)
4364 return QLA_FUNCTION_FAILED;
4365
4366 e->u.aen.code = code;
4367 e->u.aen.data = data;
f999f4c1 4368 return qla2x00_post_work(vha, e);
0971de7f
AV		 4369}
4370
8a659571
AV		 4371int
4372qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4373{
4374 struct qla_work_evt *e;
4375
f999f4c1 4376 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4377 if (!e)
4378 return QLA_FUNCTION_FAILED;
4379
4380 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4381 return qla2x00_post_work(vha, e);
8a659571
AV		 4382}
4383
ac280b67
AV		 4384#define qla2x00_post_async_work(name, type) \
4385int qla2x00_post_async_##name##_work( \
4386 struct scsi_qla_host *vha, \
4387 fc_port_t *fcport, uint16_t *data) \
4388{ \
4389 struct qla_work_evt *e; \
4390 \
4391 e = qla2x00_alloc_work(vha, type); \
4392 if (!e) \
4393 return QLA_FUNCTION_FAILED; \
4394 \
4395 e->u.logio.fcport = fcport; \
4396 if (data) { \
4397 e->u.logio.data[0] = data[0]; \
4398 e->u.logio.data[1] = data[1]; \
4399 } \
4400 return qla2x00_post_work(vha, e); \
4401}
4402
4403qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4404qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4405qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4406qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4407qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4408
3420d36c
AV		 4409int
4410qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4411{
4412 struct qla_work_evt *e;
4413
4414 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4415 if (!e)
4416 return QLA_FUNCTION_FAILED;
4417
4418 e->u.uevent.code = code;
4419 return qla2x00_post_work(vha, e);
4420}
4421
4422static void
4423qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4424{
4425 char event_string[40];
4426 char *envp[] = { event_string, NULL };
4427
4428 switch (code) {
4429 case QLA_UEVENT_CODE_FW_DUMP:
4430 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4431 vha->host_no);
4432 break;
4433 default:
4434 /* do nothing */
4435 break;
4436 }
4437 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4438}
4439
8ae6d9c7
GM		 4440int
4441qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4442 uint32_t *data, int cnt)
4443{
4444 struct qla_work_evt *e;
4445
4446 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4447 if (!e)
4448 return QLA_FUNCTION_FAILED;
4449
4450 e->u.aenfx.evtcode = evtcode;
4451 e->u.aenfx.count = cnt;
4452 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4453 return qla2x00_post_work(vha, e);
4454}
4455
726b8548
QT		 4456int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4457{
4458 struct qla_work_evt *e;
4459
4460 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4461 if (!e)
4462 return QLA_FUNCTION_FAILED;
4463
4464 e->u.fcport.fcport = fcport;
4465 return qla2x00_post_work(vha, e);
4466}
4467
4468static
4469void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4470{
4471 unsigned long flags;
4472 fc_port_t *fcport = NULL;
4473 struct qlt_plogi_ack_t *pla =
4474 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4475
4476 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4477 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4478 if (fcport) {
4479 fcport->d_id = e->u.new_sess.id;
4480 if (pla) {
4481 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4482 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4483 /* we took an extra ref_count to prevent PLOGI ACK when
4484 * fcport/sess has not been created.
4485 */
4486 pla->ref_count--;
4487 }
4488 } else {
4489 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4490 if (fcport) {
4491 fcport->d_id = e->u.new_sess.id;
4492 fcport->scan_state = QLA_FCPORT_FOUND;
4493 fcport->flags |= FCF_FABRIC_DEVICE;
4494 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4495
4496 memcpy(fcport->port_name, e->u.new_sess.port_name,
4497 WWN_SIZE);
4498 list_add_tail(&fcport->list, &vha->vp_fcports);
4499
4500 if (pla) {
4501 qlt_plogi_ack_link(vha, pla, fcport,
4502 QLT_PLOGI_LINK_SAME_WWN);
4503 pla->ref_count--;
4504 }
4505 }
4506 }
4507 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4508
4509 if (fcport) {
4510 if (pla)
4511 qlt_plogi_ack_unref(vha, pla);
4512 else
4513 qla24xx_async_gnl(vha, fcport);
4514 }
4515}
4516
ac280b67 4517void
e315cd28 4518qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4519{
f999f4c1
AV		 4520 struct qla_work_evt *e, *tmp;
4521 unsigned long flags;
4522 LIST_HEAD(work);
0971de7f 4523
f999f4c1
AV		 4524 spin_lock_irqsave(&vha->work_lock, flags);
4525 list_splice_init(&vha->work_list, &work);
4526 spin_unlock_irqrestore(&vha->work_lock, flags);
4527
4528 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4529 list_del_init(&e->list);
0971de7f
AV		 4530
4531 switch (e->type) {
4532 case QLA_EVT_AEN:
e315cd28 4533 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4534 e->u.aen.code, e->u.aen.data);
4535 break;
8a659571
AV		 4536 case QLA_EVT_IDC_ACK:
4537 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4538 break;
ac280b67
AV		 4539 case QLA_EVT_ASYNC_LOGIN:
4540 qla2x00_async_login(vha, e->u.logio.fcport,
4541 e->u.logio.data);
4542 break;
ac280b67
AV		 4543 case QLA_EVT_ASYNC_LOGOUT:
4544 qla2x00_async_logout(vha, e->u.logio.fcport);
4545 break;
4546 case QLA_EVT_ASYNC_LOGOUT_DONE:
4547 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4548 e->u.logio.data);
4549 break;
5ff1d584
AV		 4550 case QLA_EVT_ASYNC_ADISC:
4551 qla2x00_async_adisc(vha, e->u.logio.fcport,
4552 e->u.logio.data);
4553 break;
4554 case QLA_EVT_ASYNC_ADISC_DONE:
4555 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4556 e->u.logio.data);
4557 break;
3420d36c
AV		 4558 case QLA_EVT_UEVENT:
4559 qla2x00_uevent_emit(vha, e->u.uevent.code);
4560 break;
8ae6d9c7
GM		 4561 case QLA_EVT_AENFX:
4562 qlafx00_process_aen(vha, e);
4563 break;
726b8548
QT		 4564 case QLA_EVT_GIDPN:
4565 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4566 break;
4567 case QLA_EVT_GPNID:
4568 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4569 break;
4570 case QLA_EVT_GPNID_DONE:
4571 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4572 break;
4573 case QLA_EVT_NEW_SESS:
4574 qla24xx_create_new_sess(vha, e);
4575 break;
4576 case QLA_EVT_GPDB:
4577 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4578 e->u.fcport.opt);
4579 break;
4580 case QLA_EVT_GPSC:
4581 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4582 break;
4583 case QLA_EVT_UPD_FCPORT:
4584 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4585 break;
4586 case QLA_EVT_GNL:
4587 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4588 break;
4589 case QLA_EVT_NACK:
4590 qla24xx_do_nack_work(vha, e);
4591 break;
0971de7f
AV		 4592 }
4593 if (e->flags & QLA_EVT_FLAG_FREE)
4594 kfree(e);
feafb7b1
AE		 4595
4596 /* For each work completed decrement vha ref count */
4597 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4598 }
e315cd28 4599}
f999f4c1 4600
e315cd28
AC		 4601/* Relogins all the fcports of a vport
4602 * Context: dpc thread
4603 */
4604void qla2x00_relogin(struct scsi_qla_host *vha)
4605{
4606 fc_port_t *fcport;
c6b2fca8 4607 int status;
726b8548 4608 struct event_arg ea;
e315cd28
AC		 4609
4610 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4611 /*
4612 * If the port is not ONLINE then try to login
4613 * to it if we haven't run out of retries.
4614 */
5ff1d584
AV		 4615 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4616 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4617 fcport->login_retry--;
e315cd28 4618 if (fcport->flags & FCF_FABRIC_DEVICE) {
726b8548
QT		 4619 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
4620 "%s %8phC DS %d LS %d\n", __func__,
4621 fcport->port_name, fcport->disc_state,
4622 fcport->fw_login_state);
4623 memset(&ea, 0, sizeof(ea));
4624 ea.event = FCME_RELOGIN;
4625 ea.fcport = fcport;
4626 qla2x00_fcport_event_handler(vha, &ea);
4627 } else {
e315cd28
AC		 4628 status = qla2x00_local_device_login(vha,
4629 fcport);
726b8548
QT		 4630 if (status == QLA_SUCCESS) {
4631 fcport->old_loop_id = fcport->loop_id;
4632 ql_dbg(ql_dbg_disc, vha, 0x2003,
4633 "Port login OK: logged in ID 0x%x.\n",
4634 fcport->loop_id);
4635 qla2x00_update_fcport(vha, fcport);
4636 } else if (status == 1) {
4637 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4638 /* retry the login again */
4639 ql_dbg(ql_dbg_disc, vha, 0x2007,
4640 "Retrying %d login again loop_id 0x%x.\n",
4641 fcport->login_retry,
4642 fcport->loop_id);
4643 } else {
4644 fcport->login_retry = 0;
4645 }
e315cd28 4646
726b8548
QT		 4647 if (fcport->login_retry == 0 &&
4648 status != QLA_SUCCESS)
4649 qla2x00_clear_loop_id(fcport);
e315cd28 4650 }
e315cd28
AC		 4651 }
4652 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4653 break;
0971de7f 4654 }
0971de7f
AV		 4655}
4656
7d613ac6
SV		 4657/* Schedule work on any of the dpc-workqueues */
4658void
4659qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4660{
4661 struct qla_hw_data *ha = base_vha->hw;
4662
4663 switch (work_code) {
4664 case MBA_IDC_AEN: /* 0x8200 */
4665 if (ha->dpc_lp_wq)
4666 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4667 break;
4668
4669 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4670 if (!ha->flags.nic_core_reset_hdlr_active) {
4671 if (ha->dpc_hp_wq)
4672 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4673 } else
4674 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4675 "NIC Core reset is already active. Skip "
4676 "scheduling it again.\n");
4677 break;
4678 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4679 if (ha->dpc_hp_wq)
4680 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4681 break;
4682 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4683 if (ha->dpc_hp_wq)
4684 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4685 break;
4686 default:
4687 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4688 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4689 }
4690
4691 return;
4692}
4693
4694/* Work: Perform NIC Core Unrecoverable state handling */
4695void
4696qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4697{
4698 struct qla_hw_data *ha =
2ad1b67c 4699 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4700 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4701 uint32_t dev_state = 0;
4702
4703 qla83xx_idc_lock(base_vha, 0);
4704 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4705 qla83xx_reset_ownership(base_vha);
4706 if (ha->flags.nic_core_reset_owner) {
4707 ha->flags.nic_core_reset_owner = 0;
4708 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4709 QLA8XXX_DEV_FAILED);
4710 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4711 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4712 }
4713 qla83xx_idc_unlock(base_vha, 0);
4714}
4715
4716/* Work: Execute IDC state handler */
4717void
4718qla83xx_idc_state_handler_work(struct work_struct *work)
4719{
4720 struct qla_hw_data *ha =
2ad1b67c 4721 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4722 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4723 uint32_t dev_state = 0;
4724
4725 qla83xx_idc_lock(base_vha, 0);
4726 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4727 if (dev_state == QLA8XXX_DEV_FAILED ||
4728 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4729 qla83xx_idc_state_handler(base_vha);
4730 qla83xx_idc_unlock(base_vha, 0);
4731}
4732
fa492630 4733static int
7d613ac6
SV		 4734qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4735{
4736 int rval = QLA_SUCCESS;
4737 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4738 uint32_t heart_beat_counter1, heart_beat_counter2;
4739
4740 do {
4741 if (time_after(jiffies, heart_beat_wait)) {
4742 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4743 "Nic Core f/w is not alive.\n");
4744 rval = QLA_FUNCTION_FAILED;
4745 break;
4746 }
4747
4748 qla83xx_idc_lock(base_vha, 0);
4749 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4750 &heart_beat_counter1);
4751 qla83xx_idc_unlock(base_vha, 0);
4752 msleep(100);
4753 qla83xx_idc_lock(base_vha, 0);
4754 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4755 &heart_beat_counter2);
4756 qla83xx_idc_unlock(base_vha, 0);
4757 } while (heart_beat_counter1 == heart_beat_counter2);
4758
4759 return rval;
4760}
4761
4762/* Work: Perform NIC Core Reset handling */
4763void
4764qla83xx_nic_core_reset_work(struct work_struct *work)
4765{
4766 struct qla_hw_data *ha =
4767 container_of(work, struct qla_hw_data, nic_core_reset);
4768 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4769 uint32_t dev_state = 0;
4770
81178772
SK		 4771 if (IS_QLA2031(ha)) {
4772 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4773 ql_log(ql_log_warn, base_vha, 0xb081,
4774 "Failed to dump mctp\n");
4775 return;
4776 }
4777
7d613ac6
SV		 4778 if (!ha->flags.nic_core_reset_hdlr_active) {
4779 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4780 qla83xx_idc_lock(base_vha, 0);
4781 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4782 &dev_state);
4783 qla83xx_idc_unlock(base_vha, 0);
4784 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4785 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4786 "Nic Core f/w is alive.\n");
4787 return;
4788 }
4789 }
4790
4791 ha->flags.nic_core_reset_hdlr_active = 1;
4792 if (qla83xx_nic_core_reset(base_vha)) {
4793 /* NIC Core reset failed. */
4794 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4795 "NIC Core reset failed.\n");
4796 }
4797 ha->flags.nic_core_reset_hdlr_active = 0;
4798 }
4799}
4800
4801/* Work: Handle 8200 IDC aens */
4802void
4803qla83xx_service_idc_aen(struct work_struct *work)
4804{
4805 struct qla_hw_data *ha =
4806 container_of(work, struct qla_hw_data, idc_aen);
4807 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4808 uint32_t dev_state, idc_control;
4809
4810 qla83xx_idc_lock(base_vha, 0);
4811 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4812 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4813 qla83xx_idc_unlock(base_vha, 0);
4814 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4815 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4816 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4817 "Application requested NIC Core Reset.\n");
4818 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4819 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4820 QLA_SUCCESS) {
4821 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4822 "Other protocol driver requested NIC Core Reset.\n");
4823 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4824 }
4825 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4826 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4827 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4828 }
4829}
4830
4831static void
4832qla83xx_wait_logic(void)
4833{
4834 int i;
4835
4836 /* Yield CPU */
4837 if (!in_interrupt()) {
4838 /*
4839 * Wait about 200ms before retrying again.
4840 * This controls the number of retries for single
4841 * lock operation.
4842 */
4843 msleep(100);
4844 schedule();
4845 } else {
4846 for (i = 0; i < 20; i++)
4847 cpu_relax(); /* This a nop instr on i386 */
4848 }
4849}
4850
fa492630 4851static int
7d613ac6
SV		 4852qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4853{
4854 int rval;
4855 uint32_t data;
4856 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4857 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4858 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4859 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4860 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4861
4862 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4863 if (rval)
4864 return rval;
4865
4866 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4867 return QLA_SUCCESS;
4868 } else {
4869 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4870 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4871 data);
4872 if (rval)
4873 return rval;
4874
4875 msleep(200);
4876
4877 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4878 &data);
4879 if (rval)
4880 return rval;
4881
4882 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4883 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4884 ~(idc_lck_rcvry_stage_mask));
4885 rval = qla83xx_wr_reg(base_vha,
4886 QLA83XX_IDC_LOCK_RECOVERY, data);
4887 if (rval)
4888 return rval;
4889
4890 /* Forcefully perform IDC UnLock */
4891 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4892 &data);
4893 if (rval)
4894 return rval;
4895 /* Clear lock-id by setting 0xff */
4896 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4897 0xff);
4898 if (rval)
4899 return rval;
4900 /* Clear lock-recovery by setting 0x0 */
4901 rval = qla83xx_wr_reg(base_vha,
4902 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4903 if (rval)
4904 return rval;
4905 } else
4906 return QLA_SUCCESS;
4907 }
4908
4909 return rval;
4910}
4911
fa492630 4912static int
7d613ac6
SV		 4913qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4914{
4915 int rval = QLA_SUCCESS;
4916 uint32_t o_drv_lockid, n_drv_lockid;
4917 unsigned long lock_recovery_timeout;
4918
4919 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4920retry_lockid:
4921 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4922 if (rval)
4923 goto exit;
4924
4925 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4926 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4927 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4928 return QLA_SUCCESS;
4929 else
4930 return QLA_FUNCTION_FAILED;
4931 }
4932
4933 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4934 if (rval)
4935 goto exit;
4936
4937 if (o_drv_lockid == n_drv_lockid) {
4938 qla83xx_wait_logic();
4939 goto retry_lockid;
4940 } else
4941 return QLA_SUCCESS;
4942
4943exit:
4944 return rval;
4945}
4946
4947void
4948qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4949{
4950 uint16_t options = (requester_id << 15) | BIT_6;
4951 uint32_t data;
6c315553 4952 uint32_t lock_owner;
7d613ac6
SV		 4953 struct qla_hw_data *ha = base_vha->hw;
4954
4955 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4956retry_lock:
4957 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4958 == QLA_SUCCESS) {
4959 if (data) {
4960 /* Setting lock-id to our function-number */
4961 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4962 ha->portnum);
4963 } else {
6c315553
SK		 4964 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4965 &lock_owner);
7d613ac6 4966 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4967 "Failed to acquire IDC lock, acquired by %d, "
4968 "retrying...\n", lock_owner);
7d613ac6
SV		 4969
4970 /* Retry/Perform IDC-Lock recovery */
4971 if (qla83xx_idc_lock_recovery(base_vha)
4972 == QLA_SUCCESS) {
4973 qla83xx_wait_logic();
4974 goto retry_lock;
4975 } else
4976 ql_log(ql_log_warn, base_vha, 0xb075,
4977 "IDC Lock recovery FAILED.\n");
4978 }
4979
4980 }
4981
4982 return;
4983
4984 /* XXX: IDC-lock implementation using access-control mbx */
4985retry_lock2:
4986 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4987 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4988 "Failed to acquire IDC lock. retrying...\n");
4989 /* Retry/Perform IDC-Lock recovery */
4990 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4991 qla83xx_wait_logic();
4992 goto retry_lock2;
4993 } else
4994 ql_log(ql_log_warn, base_vha, 0xb076,
4995 "IDC Lock recovery FAILED.\n");
4996 }
4997
4998 return;
4999}
5000
5001void
5002qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5003{
5897cb2f
BVA		 5004#if 0
5005 uint16_t options = (requester_id << 15) | BIT_7;
5006#endif
5007 uint16_t retry;
7d613ac6
SV		 5008 uint32_t data;
5009 struct qla_hw_data *ha = base_vha->hw;
5010
5011 /* IDC-unlock implementation using driver-unlock/lock-id
5012 * remote registers
5013 */
5014 retry = 0;
5015retry_unlock:
5016 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5017 == QLA_SUCCESS) {
5018 if (data == ha->portnum) {
5019 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5020 /* Clearing lock-id by setting 0xff */
5021 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5022 } else if (retry < 10) {
5023 /* SV: XXX: IDC unlock retrying needed here? */
5024
5025 /* Retry for IDC-unlock */
5026 qla83xx_wait_logic();
5027 retry++;
5028 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5029 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5030 goto retry_unlock;
5031 }
5032 } else if (retry < 10) {
5033 /* Retry for IDC-unlock */
5034 qla83xx_wait_logic();
5035 retry++;
5036 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5037 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5038 goto retry_unlock;
5039 }
5040
5041 return;
5042
5897cb2f 5043#if 0
7d613ac6
SV		 5044 /* XXX: IDC-unlock implementation using access-control mbx */
5045 retry = 0;
5046retry_unlock2:
5047 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5048 if (retry < 10) {
5049 /* Retry for IDC-unlock */
5050 qla83xx_wait_logic();
5051 retry++;
5052 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5053 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5054 goto retry_unlock2;
5055 }
5056 }
5057
5058 return;
5897cb2f 5059#endif
7d613ac6
SV		 5060}
5061
5062int
5063__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5064{
5065 int rval = QLA_SUCCESS;
5066 struct qla_hw_data *ha = vha->hw;
5067 uint32_t drv_presence;
5068
5069 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5070 if (rval == QLA_SUCCESS) {
5071 drv_presence |= (1 << ha->portnum);
5072 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5073 drv_presence);
5074 }
5075
5076 return rval;
5077}
5078
5079int
5080qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5081{
5082 int rval = QLA_SUCCESS;
5083
5084 qla83xx_idc_lock(vha, 0);
5085 rval = __qla83xx_set_drv_presence(vha);
5086 qla83xx_idc_unlock(vha, 0);
5087
5088 return rval;
5089}
5090
5091int
5092__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5093{
5094 int rval = QLA_SUCCESS;
5095 struct qla_hw_data *ha = vha->hw;
5096 uint32_t drv_presence;
5097
5098 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5099 if (rval == QLA_SUCCESS) {
5100 drv_presence &= ~(1 << ha->portnum);
5101 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5102 drv_presence);
5103 }
5104
5105 return rval;
5106}
5107
5108int
5109qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5110{
5111 int rval = QLA_SUCCESS;
5112
5113 qla83xx_idc_lock(vha, 0);
5114 rval = __qla83xx_clear_drv_presence(vha);
5115 qla83xx_idc_unlock(vha, 0);
5116
5117 return rval;
5118}
5119
fa492630 5120static void
7d613ac6
SV		 5121qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5122{
5123 struct qla_hw_data *ha = vha->hw;
5124 uint32_t drv_ack, drv_presence;
5125 unsigned long ack_timeout;
5126
5127 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5128 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5129 while (1) {
5130 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5131 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5132 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5133 break;
5134
5135 if (time_after_eq(jiffies, ack_timeout)) {
5136 ql_log(ql_log_warn, vha, 0xb067,
5137 "RESET ACK TIMEOUT! drv_presence=0x%x "
5138 "drv_ack=0x%x\n", drv_presence, drv_ack);
5139 /*
5140 * The function(s) which did not ack in time are forced
5141 * to withdraw any further participation in the IDC
5142 * reset.
5143 */
5144 if (drv_ack != drv_presence)
5145 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5146 drv_ack);
5147 break;
5148 }
5149
5150 qla83xx_idc_unlock(vha, 0);
5151 msleep(1000);
5152 qla83xx_idc_lock(vha, 0);
5153 }
5154
5155 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5156 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5157}
5158
fa492630 5159static int
7d613ac6
SV		 5160qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5161{
5162 int rval = QLA_SUCCESS;
5163 uint32_t idc_control;
5164
5165 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5166 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5167
5168 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5169 __qla83xx_get_idc_control(vha, &idc_control);
5170 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5171 __qla83xx_set_idc_control(vha, 0);
5172
5173 qla83xx_idc_unlock(vha, 0);
5174 rval = qla83xx_restart_nic_firmware(vha);
5175 qla83xx_idc_lock(vha, 0);
5176
5177 if (rval != QLA_SUCCESS) {
5178 ql_log(ql_log_fatal, vha, 0xb06a,
5179 "Failed to restart NIC f/w.\n");
5180 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5181 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5182 } else {
5183 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5184 "Success in restarting nic f/w.\n");
5185 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5186 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5187 }
5188
5189 return rval;
5190}
5191
5192/* Assumes idc_lock always held on entry */
5193int
5194qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5195{
5196 struct qla_hw_data *ha = base_vha->hw;
5197 int rval = QLA_SUCCESS;
5198 unsigned long dev_init_timeout;
5199 uint32_t dev_state;
5200
5201 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5202 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5203
5204 while (1) {
5205
5206 if (time_after_eq(jiffies, dev_init_timeout)) {
5207 ql_log(ql_log_warn, base_vha, 0xb06e,
5208 "Initialization TIMEOUT!\n");
5209 /* Init timeout. Disable further NIC Core
5210 * communication.
5211 */
5212 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5213 QLA8XXX_DEV_FAILED);
5214 ql_log(ql_log_info, base_vha, 0xb06f,
5215 "HW State: FAILED.\n");
5216 }
5217
5218 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5219 switch (dev_state) {
5220 case QLA8XXX_DEV_READY:
5221 if (ha->flags.nic_core_reset_owner)
5222 qla83xx_idc_audit(base_vha,
5223 IDC_AUDIT_COMPLETION);
5224 ha->flags.nic_core_reset_owner = 0;
5225 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5226 "Reset_owner reset by 0x%x.\n",
5227 ha->portnum);
5228 goto exit;
5229 case QLA8XXX_DEV_COLD:
5230 if (ha->flags.nic_core_reset_owner)
5231 rval = qla83xx_device_bootstrap(base_vha);
5232 else {
5233 /* Wait for AEN to change device-state */
5234 qla83xx_idc_unlock(base_vha, 0);
5235 msleep(1000);
5236 qla83xx_idc_lock(base_vha, 0);
5237 }
5238 break;
5239 case QLA8XXX_DEV_INITIALIZING:
5240 /* Wait for AEN to change device-state */
5241 qla83xx_idc_unlock(base_vha, 0);
5242 msleep(1000);
5243 qla83xx_idc_lock(base_vha, 0);
5244 break;
5245 case QLA8XXX_DEV_NEED_RESET:
5246 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5247 qla83xx_need_reset_handler(base_vha);
5248 else {
5249 /* Wait for AEN to change device-state */
5250 qla83xx_idc_unlock(base_vha, 0);
5251 msleep(1000);
5252 qla83xx_idc_lock(base_vha, 0);
5253 }
5254 /* reset timeout value after need reset handler */
5255 dev_init_timeout = jiffies +
5256 (ha->fcoe_dev_init_timeout * HZ);
5257 break;
5258 case QLA8XXX_DEV_NEED_QUIESCENT:
5259 /* XXX: DEBUG for now */
5260 qla83xx_idc_unlock(base_vha, 0);
5261 msleep(1000);
5262 qla83xx_idc_lock(base_vha, 0);
5263 break;
5264 case QLA8XXX_DEV_QUIESCENT:
5265 /* XXX: DEBUG for now */
5266 if (ha->flags.quiesce_owner)
5267 goto exit;
5268
5269 qla83xx_idc_unlock(base_vha, 0);
5270 msleep(1000);
5271 qla83xx_idc_lock(base_vha, 0);
5272 dev_init_timeout = jiffies +
5273 (ha->fcoe_dev_init_timeout * HZ);
5274 break;
5275 case QLA8XXX_DEV_FAILED:
5276 if (ha->flags.nic_core_reset_owner)
5277 qla83xx_idc_audit(base_vha,
5278 IDC_AUDIT_COMPLETION);
5279 ha->flags.nic_core_reset_owner = 0;
5280 __qla83xx_clear_drv_presence(base_vha);
5281 qla83xx_idc_unlock(base_vha, 0);
5282 qla8xxx_dev_failed_handler(base_vha);
5283 rval = QLA_FUNCTION_FAILED;
5284 qla83xx_idc_lock(base_vha, 0);
5285 goto exit;
5286 case QLA8XXX_BAD_VALUE:
5287 qla83xx_idc_unlock(base_vha, 0);
5288 msleep(1000);
5289 qla83xx_idc_lock(base_vha, 0);
5290 break;
5291 default:
5292 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5293 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5294 qla83xx_idc_unlock(base_vha, 0);
5295 qla8xxx_dev_failed_handler(base_vha);
5296 rval = QLA_FUNCTION_FAILED;
5297 qla83xx_idc_lock(base_vha, 0);
5298 goto exit;
5299 }
5300 }
5301
5302exit:
5303 return rval;
5304}
5305
f3ddac19
CD		 5306void
5307qla2x00_disable_board_on_pci_error(struct work_struct *work)
5308{
5309 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5310 board_disable);
5311 struct pci_dev *pdev = ha->pdev;
5312 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5313
726b8548
QT		 5314 /*
5315 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5316 * where it was set first.
5317 */
5318 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5319 return;
5320
f3ddac19
CD		 5321 ql_log(ql_log_warn, base_vha, 0x015b,
5322 "Disabling adapter.\n");
5323
726b8548
QT		 5324 qla2x00_wait_for_sess_deletion(base_vha);
5325
f3ddac19
CD		 5326 set_bit(UNLOADING, &base_vha->dpc_flags);
5327
5328 qla2x00_delete_all_vps(ha, base_vha);
5329
5330 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5331
5332 qla2x00_dfs_remove(base_vha);
5333
5334 qla84xx_put_chip(base_vha);
5335
5336 if (base_vha->timer_active)
5337 qla2x00_stop_timer(base_vha);
5338
5339 base_vha->flags.online = 0;
5340
5341 qla2x00_destroy_deferred_work(ha);
5342
5343 /*
5344 * Do not try to stop beacon blink as it will issue a mailbox
5345 * command.
5346 */
5347 qla2x00_free_sysfs_attr(base_vha, false);
5348
5349 fc_remove_host(base_vha->host);
5350
5351 scsi_remove_host(base_vha->host);
5352
5353 base_vha->flags.init_done = 0;
5354 qla25xx_delete_queues(base_vha);
f3ddac19 5355 qla2x00_free_fcports(base_vha);
093df737 5356 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5357 qla2x00_mem_free(ha);
5358 qla82xx_md_free(base_vha);
5359 qla2x00_free_queues(ha);
5360
f3ddac19
CD		 5361 qla2x00_unmap_iobases(ha);
5362
5363 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5364 pci_disable_pcie_error_reporting(pdev);
5365 pci_disable_device(pdev);
f3ddac19 5366
beb9e315
JL		 5367 /*
5368 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5369 */
f3ddac19
CD		 5370}
5371
1da177e4
LT		 5372/**************************************************************************
5373* qla2x00_do_dpc
5374* This kernel thread is a task that is schedule by the interrupt handler
5375* to perform the background processing for interrupts.
5376*
5377* Notes:
5378* This task always run in the context of a kernel thread. It
5379* is kick-off by the driver's detect code and starts up
5380* up one per adapter. It immediately goes to sleep and waits for
5381* some fibre event. When either the interrupt handler or
5382* the timer routine detects a event it will one of the task
5383* bits then wake us up.
5384**************************************************************************/
5385static int
5386qla2x00_do_dpc(void *data)
5387{
e315cd28
AC		 5388 scsi_qla_host_t *base_vha;
5389 struct qla_hw_data *ha;
d7459527
MH		 5390 uint32_t online;
5391 struct qla_qpair *qpair;
1da177e4 5392
e315cd28
AC		 5393 ha = (struct qla_hw_data *)data;
5394 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5395
8698a745 5396 set_user_nice(current, MIN_NICE);
1da177e4 5397
563585ec 5398 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5399 while (!kthread_should_stop()) {
7c3df132
SK		 5400 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5401 "DPC handler sleeping.\n");
1da177e4 5402
39a11240 5403 schedule();
1da177e4 5404
c142caf0
AV		 5405 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5406 goto end_loop;
1da177e4 5407
85880801 5408 if (ha->flags.eeh_busy) {
7c3df132
SK		 5409 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5410 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5411 goto end_loop;
85880801
AV		 5412 }
5413
1da177e4
LT		 5414 ha->dpc_active = 1;
5415
5f28d2d7
SK		 5416 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5417 "DPC handler waking up, dpc_flags=0x%lx.\n",
5418 base_vha->dpc_flags);
1da177e4 5419
a29b3dd7
JC		 5420 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5421 break;
5422
e315cd28 5423 qla2x00_do_work(base_vha);
0971de7f 5424
7ec0effd
AD		 5425 if (IS_P3P_TYPE(ha)) {
5426 if (IS_QLA8044(ha)) {
5427 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5428 &base_vha->dpc_flags)) {
5429 qla8044_idc_lock(ha);
5430 qla8044_wr_direct(base_vha,
5431 QLA8044_CRB_DEV_STATE_INDEX,
5432 QLA8XXX_DEV_FAILED);
5433 qla8044_idc_unlock(ha);
5434 ql_log(ql_log_info, base_vha, 0x4004,
5435 "HW State: FAILED.\n");
5436 qla8044_device_state_handler(base_vha);
5437 continue;
5438 }
5439
5440 } else {
5441 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5442 &base_vha->dpc_flags)) {
5443 qla82xx_idc_lock(ha);
5444 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5445 QLA8XXX_DEV_FAILED);
5446 qla82xx_idc_unlock(ha);
5447 ql_log(ql_log_info, base_vha, 0x0151,
5448 "HW State: FAILED.\n");
5449 qla82xx_device_state_handler(base_vha);
5450 continue;
5451 }
a9083016
GM		 5452 }
5453
5454 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5455 &base_vha->dpc_flags)) {
5456
7c3df132
SK		 5457 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5458 "FCoE context reset scheduled.\n");
a9083016
GM		 5459 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5460 &base_vha->dpc_flags))) {
5461 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5462 /* FCoE-ctx reset failed.
5463 * Escalate to chip-reset
5464 */
5465 set_bit(ISP_ABORT_NEEDED,
5466 &base_vha->dpc_flags);
5467 }
5468 clear_bit(ABORT_ISP_ACTIVE,
5469 &base_vha->dpc_flags);
5470 }
5471
7c3df132
SK		 5472 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5473 "FCoE context reset end.\n");
a9083016 5474 }
8ae6d9c7
GM		 5475 } else if (IS_QLAFX00(ha)) {
5476 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5477 &base_vha->dpc_flags)) {
5478 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5479 "Firmware Reset Recovery\n");
5480 if (qlafx00_reset_initialize(base_vha)) {
5481 /* Failed. Abort isp later. */
5482 if (!test_bit(UNLOADING,
f92f82d6 5483 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5484 set_bit(ISP_UNRECOVERABLE,
5485 &base_vha->dpc_flags);
5486 ql_dbg(ql_dbg_dpc, base_vha,
5487 0x4021,
5488 "Reset Recovery Failed\n");
f92f82d6 5489 }
8ae6d9c7
GM		 5490 }
5491 }
5492
5493 if (test_and_clear_bit(FX00_TARGET_SCAN,
5494 &base_vha->dpc_flags)) {
5495 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5496 "ISPFx00 Target Scan scheduled\n");
5497 if (qlafx00_rescan_isp(base_vha)) {
5498 if (!test_bit(UNLOADING,
5499 &base_vha->dpc_flags))
5500 set_bit(ISP_UNRECOVERABLE,
5501 &base_vha->dpc_flags);
5502 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5503 "ISPFx00 Target Scan Failed\n");
5504 }
5505 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5506 "ISPFx00 Target Scan End\n");
5507 }
e8f5e95d
AB		 5508 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5509 &base_vha->dpc_flags)) {
5510 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5511 "ISPFx00 Host Info resend scheduled\n");
5512 qlafx00_fx_disc(base_vha,
5513 &base_vha->hw->mr.fcport,
5514 FXDISC_REG_HOST_INFO);
5515 }
a9083016
GM		 5516 }
5517
e315cd28
AC		 5518 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5519 &base_vha->dpc_flags)) {
1da177e4 5520
7c3df132
SK		 5521 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5522 "ISP abort scheduled.\n");
1da177e4 5523 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5524 &base_vha->dpc_flags))) {
1da177e4 5525
a9083016 5526 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5527 /* failed. retry later */
5528 set_bit(ISP_ABORT_NEEDED,
e315cd28 5529 &base_vha->dpc_flags);
99363ef8 5530 }
e315cd28
AC		 5531 clear_bit(ABORT_ISP_ACTIVE,
5532 &base_vha->dpc_flags);
99363ef8
SJ		 5533 }
5534
7c3df132
SK		 5535 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5536 "ISP abort end.\n");
1da177e4
LT		 5537 }
5538
a394aac8
DJ		 5539 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5540 &base_vha->dpc_flags)) {
e315cd28 5541 qla2x00_update_fcports(base_vha);
c9c5ced9 5542 }
d97994dc 5543
8ae6d9c7
GM		 5544 if (IS_QLAFX00(ha))
5545 goto loop_resync_check;
5546
579d12b5 5547 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5548 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5549 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5550 if (IS_P3P_TYPE(ha)) {
5551 if (IS_QLA82XX(ha))
5552 qla82xx_device_state_handler(base_vha);
5553 if (IS_QLA8044(ha))
5554 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5555 clear_bit(ISP_QUIESCE_NEEDED,
5556 &base_vha->dpc_flags);
5557 if (!ha->flags.quiesce_owner) {
5558 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5559 if (IS_QLA82XX(ha)) {
5560 qla82xx_idc_lock(ha);
5561 qla82xx_clear_qsnt_ready(
5562 base_vha);
5563 qla82xx_idc_unlock(ha);
5564 } else if (IS_QLA8044(ha)) {
5565 qla8044_idc_lock(ha);
5566 qla8044_clear_qsnt_ready(
5567 base_vha);
5568 qla8044_idc_unlock(ha);
5569 }
8fcd6b8b
CD		 5570 }
5571 } else {
5572 clear_bit(ISP_QUIESCE_NEEDED,
5573 &base_vha->dpc_flags);
5574 qla2x00_quiesce_io(base_vha);
579d12b5 5575 }
7c3df132
SK		 5576 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5577 "Quiescence mode end.\n");
579d12b5
SK		 5578 }
5579
e315cd28 5580 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5581 &base_vha->dpc_flags) &&
e315cd28 5582 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5583
7c3df132
SK		 5584 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5585 "Reset marker scheduled.\n");
e315cd28
AC		 5586 qla2x00_rst_aen(base_vha);
5587 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5588 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5589 "Reset marker end.\n");
1da177e4
LT		 5590 }
5591
5592 /* Retry each device up to login retry count */
e315cd28
AC		 5593 if ((test_and_clear_bit(RELOGIN_NEEDED,
5594 &base_vha->dpc_flags)) &&
5595 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5596 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5597
7c3df132
SK		 5598 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5599 "Relogin scheduled.\n");
e315cd28 5600 qla2x00_relogin(base_vha);
7c3df132
SK		 5601 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5602 "Relogin end.\n");
1da177e4 5603 }
8ae6d9c7 5604loop_resync_check:
e315cd28 5605 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5606 &base_vha->dpc_flags)) {
1da177e4 5607
7c3df132
SK		 5608 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5609 "Loop resync scheduled.\n");
1da177e4
LT		 5610
5611 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5612 &base_vha->dpc_flags))) {
1da177e4 5613
52c82823 5614 qla2x00_loop_resync(base_vha);
1da177e4 5615
e315cd28
AC		 5616 clear_bit(LOOP_RESYNC_ACTIVE,
5617 &base_vha->dpc_flags);
1da177e4
LT		 5618 }
5619
7c3df132
SK		 5620 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5621 "Loop resync end.\n");
1da177e4
LT		 5622 }
5623
8ae6d9c7
GM		 5624 if (IS_QLAFX00(ha))
5625 goto intr_on_check;
5626
e315cd28
AC		 5627 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5628 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5629 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5630 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5631 }
5632
8ae6d9c7 5633intr_on_check:
1da177e4 5634 if (!ha->interrupts_on)
fd34f556 5635 ha->isp_ops->enable_intrs(ha);
1da177e4 5636
e315cd28 5637 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5638 &base_vha->dpc_flags)) {
5639 if (ha->beacon_blink_led == 1)
5640 ha->isp_ops->beacon_blink(base_vha);
5641 }
f6df144c 5642
d7459527
MH		 5643 /* qpair online check */
5644 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5645 &base_vha->dpc_flags)) {
5646 if (ha->flags.eeh_busy ||
5647 ha->flags.pci_channel_io_perm_failure)
5648 online = 0;
5649 else
5650 online = 1;
5651
5652 mutex_lock(&ha->mq_lock);
5653 list_for_each_entry(qpair, &base_vha->qp_list,
5654 qp_list_elem)
5655 qpair->online = online;
5656 mutex_unlock(&ha->mq_lock);
5657 }
5658
8ae6d9c7
GM		 5659 if (!IS_QLAFX00(ha))
5660 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5661
1da177e4 5662 ha->dpc_active = 0;
c142caf0 5663end_loop:
563585ec 5664 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5665 } /* End of while(1) */
563585ec 5666 __set_current_state(TASK_RUNNING);
1da177e4 5667
7c3df132
SK		 5668 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5669 "DPC handler exiting.\n");
1da177e4
LT		 5670
5671 /*
5672 * Make sure that nobody tries to wake us up again.
5673 */
1da177e4
LT		 5674 ha->dpc_active = 0;
5675
ac280b67
AV		 5676 /* Cleanup any residual CTX SRBs. */
5677 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5678
39a11240
CH		 5679 return 0;
5680}
5681
5682void
e315cd28 5683qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5684{
e315cd28 5685 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5686 struct task_struct *t = ha->dpc_thread;
5687
e315cd28 5688 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5689 wake_up_process(t);
1da177e4
LT		 5690}
5691
1da177e4
LT		 5692/*
5693* qla2x00_rst_aen
5694* Processes asynchronous reset.
5695*
5696* Input:
5697* ha = adapter block pointer.
5698*/
5699static void
e315cd28 5700qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5701{
e315cd28
AC		 5702 if (vha->flags.online && !vha->flags.reset_active &&
5703 !atomic_read(&vha->loop_down_timer) &&
5704 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5705 do {
e315cd28 5706 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5707
5708 /*
5709 * Issue marker command only when we are going to start
5710 * the I/O.
5711 */
e315cd28
AC		 5712 vha->marker_needed = 1;
5713 } while (!atomic_read(&vha->loop_down_timer) &&
5714 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5715 }
5716}
5717
1da177e4
LT		 5718/**************************************************************************
5719* qla2x00_timer
5720*
5721* Description:
5722* One second timer
5723*
5724* Context: Interrupt
5725***************************************************************************/
2c3dfe3f 5726void
e315cd28 5727qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5728{
1da177e4 5729 unsigned long cpu_flags = 0;
1da177e4
LT		 5730 int start_dpc = 0;
5731 int index;
5732 srb_t *sp;
85880801 5733 uint16_t w;
e315cd28 5734 struct qla_hw_data *ha = vha->hw;
73208dfd 5735 struct req_que *req;
85880801 5736
a5b36321 5737 if (ha->flags.eeh_busy) {
7c3df132
SK		 5738 ql_dbg(ql_dbg_timer, vha, 0x6000,
5739 "EEH = %d, restarting timer.\n",
5740 ha->flags.eeh_busy);
a5b36321
LC		 5741 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5742 return;
5743 }
5744
f3ddac19
CD		 5745 /*
5746 * Hardware read to raise pending EEH errors during mailbox waits. If
5747 * the read returns -1 then disable the board.
5748 */
5749 if (!pci_channel_offline(ha->pdev)) {
85880801 5750 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5751 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5752 }
1da177e4 5753
cefcaba6 5754 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5755 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5756 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5757 start_dpc++;
7ec0effd
AD		 5758 if (IS_QLA82XX(ha))
5759 qla82xx_watchdog(vha);
5760 else if (IS_QLA8044(ha))
5761 qla8044_watchdog(vha);
579d12b5
SK		 5762 }
5763
8ae6d9c7
GM		 5764 if (!vha->vp_idx && IS_QLAFX00(ha))
5765 qlafx00_timer_routine(vha);
5766
1da177e4 5767 /* Loop down handler. */
e315cd28 5768 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5769 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5770 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5771 && vha->flags.online) {
1da177e4 5772
e315cd28
AC		 5773 if (atomic_read(&vha->loop_down_timer) ==
5774 vha->loop_down_abort_time) {
1da177e4 5775
7c3df132
SK		 5776 ql_log(ql_log_info, vha, 0x6008,
5777 "Loop down - aborting the queues before time expires.\n");
1da177e4 5778
e315cd28
AC		 5779 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5780 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5781
f08b7251
AV		 5782 /*
5783 * Schedule an ISP abort to return any FCP2-device
5784 * commands.
5785 */
2c3dfe3f 5786 /* NPIV - scan physical port only */
e315cd28 5787 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5788 spin_lock_irqsave(&ha->hardware_lock,
5789 cpu_flags);
73208dfd 5790 req = ha->req_q_map[0];
2c3dfe3f 5791 for (index = 1;
8d93f550 5792 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5793 index++) {
5794 fc_port_t *sfcp;
5795
e315cd28 5796 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5797 if (!sp)
5798 continue;
9ba56b95 5799 if (sp->type != SRB_SCSI_CMD)
cf53b069 5800 continue;
2c3dfe3f 5801 sfcp = sp->fcport;
f08b7251 5802 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5803 continue;
bdf79621 5804
8f7daead
GM		 5805 if (IS_QLA82XX(ha))
5806 set_bit(FCOE_CTX_RESET_NEEDED,
5807 &vha->dpc_flags);
5808 else
5809 set_bit(ISP_ABORT_NEEDED,
e315cd28 5810 &vha->dpc_flags);
2c3dfe3f
SJ		 5811 break;
5812 }
5813 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5814 cpu_flags);
1da177e4 5815 }
1da177e4
LT		 5816 start_dpc++;
5817 }
5818
5819 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5820 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5821 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5822 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5823 "Loop down - aborting ISP.\n");
5824
8f7daead
GM		 5825 if (IS_QLA82XX(ha))
5826 set_bit(FCOE_CTX_RESET_NEEDED,
5827 &vha->dpc_flags);
5828 else
5829 set_bit(ISP_ABORT_NEEDED,
5830 &vha->dpc_flags);
1da177e4
LT		 5831 }
5832 }
7c3df132
SK		 5833 ql_dbg(ql_dbg_timer, vha, 0x600a,
5834 "Loop down - seconds remaining %d.\n",
5835 atomic_read(&vha->loop_down_timer));
1da177e4 5836 }
cefcaba6
SK		 5837 /* Check if beacon LED needs to be blinked for physical host only */
5838 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5839 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5840 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5841 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5842 start_dpc++;
5843 }
f6df144c
AV		 5844 }
5845
550bf57d 5846 /* Process any deferred work. */
e315cd28 5847 if (!list_empty(&vha->work_list))
550bf57d
AV		 5848 start_dpc++;
5849
1da177e4 5850 /* Schedule the DPC routine if needed */
e315cd28
AC		 5851 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5852 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5853 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5854 start_dpc ||
e315cd28
AC		 5855 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5856 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5857 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5858 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5859 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5860 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5861 ql_dbg(ql_dbg_timer, vha, 0x600b,
5862 "isp_abort_needed=%d loop_resync_needed=%d "
5863 "fcport_update_needed=%d start_dpc=%d "
5864 "reset_marker_needed=%d",
5865 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5866 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5867 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5868 start_dpc,
5869 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5870 ql_dbg(ql_dbg_timer, vha, 0x600c,
5871 "beacon_blink_needed=%d isp_unrecoverable=%d "
5872 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5873 "relogin_needed=%d.\n",
7c3df132
SK		 5874 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5875 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5876 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5877 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5878 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5879 qla2xxx_wake_dpc(vha);
7c3df132 5880 }
1da177e4 5881
e315cd28 5882 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5883}
5884
5433383e
AV		 5885/* Firmware interface routines. */
5886
f73cb695 5887#define FW_BLOBS 11
5433383e
AV		 5888#define FW_ISP21XX 0
5889#define FW_ISP22XX 1
5890#define FW_ISP2300 2
5891#define FW_ISP2322 3
48c02fde 5892#define FW_ISP24XX 4
c3a2f0df 5893#define FW_ISP25XX 5
3a03eb79 5894#define FW_ISP81XX 6
a9083016 5895#define FW_ISP82XX 7
6246b8a1
GM		 5896#define FW_ISP2031 8
5897#define FW_ISP8031 9
2c5bbbb2 5898#define FW_ISP27XX 10
5433383e 5899
bb8ee499
AV		 5900#define FW_FILE_ISP21XX "ql2100_fw.bin"
5901#define FW_FILE_ISP22XX "ql2200_fw.bin"
5902#define FW_FILE_ISP2300 "ql2300_fw.bin"
5903#define FW_FILE_ISP2322 "ql2322_fw.bin"
5904#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5905#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5906#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5907#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5908#define FW_FILE_ISP2031 "ql2600_fw.bin"
5909#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5910#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5911
bb8ee499 5912
e1e82b6f 5913static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5914
5915static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5916 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5917 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5918 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5919 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5920 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5921 { .name = FW_FILE_ISP25XX, },
3a03eb79 5922 { .name = FW_FILE_ISP81XX, },
a9083016 5923 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5924 { .name = FW_FILE_ISP2031, },
5925 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5926 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5927};
5928
5929struct fw_blob *
e315cd28 5930qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5931{
e315cd28 5932 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5933 struct fw_blob *blob;
5934
5433383e
AV		 5935 if (IS_QLA2100(ha)) {
5936 blob = &qla_fw_blobs[FW_ISP21XX];
5937 } else if (IS_QLA2200(ha)) {
5938 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5939 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5940 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5941 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5942 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5943 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5944 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5945 } else if (IS_QLA25XX(ha)) {
5946 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5947 } else if (IS_QLA81XX(ha)) {
5948 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5949 } else if (IS_QLA82XX(ha)) {
5950 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5951 } else if (IS_QLA2031(ha)) {
5952 blob = &qla_fw_blobs[FW_ISP2031];
5953 } else if (IS_QLA8031(ha)) {
5954 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5955 } else if (IS_QLA27XX(ha)) {
5956 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5957 } else {
5958 return NULL;
5433383e
AV		 5959 }
5960
e1e82b6f 5961 mutex_lock(&qla_fw_lock);
5433383e
AV		 5962 if (blob->fw)
5963 goto out;
5964
5965 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5966 ql_log(ql_log_warn, vha, 0x0063,
5967 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5968 blob->fw = NULL;
5969 blob = NULL;
5970 goto out;
5971 }
5972
5973out:
e1e82b6f 5974 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5975 return blob;
5976}
5977
5978static void
5979qla2x00_release_firmware(void)
5980{
5981 int idx;
5982
e1e82b6f 5983 mutex_lock(&qla_fw_lock);
5433383e 5984 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5985 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5986 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5987}
5988
14e660e6
SJ		 5989static pci_ers_result_t
5990qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5991{
85880801
AV		 5992 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5993 struct qla_hw_data *ha = vha->hw;
5994
7c3df132
SK		 5995 ql_dbg(ql_dbg_aer, vha, 0x9000,
5996 "PCI error detected, state %x.\n", state);
b9b12f73 5997
14e660e6
SJ		 5998 switch (state) {
5999 case pci_channel_io_normal:
85880801 6000 ha->flags.eeh_busy = 0;
d7459527
MH		 6001 if (ql2xmqsupport) {
6002 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6003 qla2xxx_wake_dpc(vha);
6004 }
14e660e6
SJ		 6005 return PCI_ERS_RESULT_CAN_RECOVER;
6006 case pci_channel_io_frozen:
85880801 6007 ha->flags.eeh_busy = 1;
a5b36321
LC		 6008 /* For ISP82XX complete any pending mailbox cmd */
6009 if (IS_QLA82XX(ha)) {
7190575f 6010 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6011 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6012 qla82xx_clear_pending_mbx(vha);
a5b36321 6013 }
90a86fc0 6014 qla2x00_free_irqs(vha);
14e660e6 6015 pci_disable_device(pdev);
bddd2d65
LC		 6016 /* Return back all IOs */
6017 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6018 if (ql2xmqsupport) {
6019 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6020 qla2xxx_wake_dpc(vha);
6021 }
14e660e6
SJ		 6022 return PCI_ERS_RESULT_NEED_RESET;
6023 case pci_channel_io_perm_failure:
85880801
AV		 6024 ha->flags.pci_channel_io_perm_failure = 1;
6025 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6026 if (ql2xmqsupport) {
6027 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6028 qla2xxx_wake_dpc(vha);
6029 }
14e660e6
SJ		 6030 return PCI_ERS_RESULT_DISCONNECT;
6031 }
6032 return PCI_ERS_RESULT_NEED_RESET;
6033}
6034
6035static pci_ers_result_t
6036qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6037{
6038 int risc_paused = 0;
6039 uint32_t stat;
6040 unsigned long flags;
e315cd28
AC		 6041 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6042 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6043 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6044 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6045
bcc5b6d3
SK		 6046 if (IS_QLA82XX(ha))
6047 return PCI_ERS_RESULT_RECOVERED;
6048
14e660e6
SJ		 6049 spin_lock_irqsave(&ha->hardware_lock, flags);
6050 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6051 stat = RD_REG_DWORD(&reg->hccr);
6052 if (stat & HCCR_RISC_PAUSE)
6053 risc_paused = 1;
6054 } else if (IS_QLA23XX(ha)) {
6055 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6056 if (stat & HSR_RISC_PAUSED)
6057 risc_paused = 1;
6058 } else if (IS_FWI2_CAPABLE(ha)) {
6059 stat = RD_REG_DWORD(&reg24->host_status);
6060 if (stat & HSRX_RISC_PAUSED)
6061 risc_paused = 1;
6062 }
6063 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6064
6065 if (risc_paused) {
7c3df132
SK		 6066 ql_log(ql_log_info, base_vha, 0x9003,
6067 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6068 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6069
6070 return PCI_ERS_RESULT_NEED_RESET;
6071 } else
6072 return PCI_ERS_RESULT_RECOVERED;
6073}
6074
fa492630
SK		 6075static uint32_t
6076qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6077{
6078 uint32_t rval = QLA_FUNCTION_FAILED;
6079 uint32_t drv_active = 0;
6080 struct qla_hw_data *ha = base_vha->hw;
6081 int fn;
6082 struct pci_dev *other_pdev = NULL;
6083
7c3df132
SK		 6084 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6085 "Entered %s.\n", __func__);
a5b36321
LC		 6086
6087 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6088
6089 if (base_vha->flags.online) {
6090 /* Abort all outstanding commands,
6091 * so as to be requeued later */
6092 qla2x00_abort_isp_cleanup(base_vha);
6093 }
6094
6095
6096 fn = PCI_FUNC(ha->pdev->devfn);
6097 while (fn > 0) {
6098 fn--;
7c3df132
SK		 6099 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6100 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6101 other_pdev =
6102 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6103 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6104 fn));
6105
6106 if (!other_pdev)
6107 continue;
6108 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6109 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6110 "Found PCI func available and enable at 0x%x.\n",
6111 fn);
a5b36321
LC		 6112 pci_dev_put(other_pdev);
6113 break;
6114 }
6115 pci_dev_put(other_pdev);
6116 }
6117
6118 if (!fn) {
6119 /* Reset owner */
7c3df132
SK		 6120 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6121 "This devfn is reset owner = 0x%x.\n",
6122 ha->pdev->devfn);
a5b36321
LC		 6123 qla82xx_idc_lock(ha);
6124
6125 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6126 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6127
6128 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6129 QLA82XX_IDC_VERSION);
6130
6131 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6132 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6133 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6134
6135 qla82xx_idc_unlock(ha);
6136 /* Reset if device is not already reset
6137 * drv_active would be 0 if a reset has already been done
6138 */
6139 if (drv_active)
6140 rval = qla82xx_start_firmware(base_vha);
6141 else
6142 rval = QLA_SUCCESS;
6143 qla82xx_idc_lock(ha);
6144
6145 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6146 ql_log(ql_log_info, base_vha, 0x900b,
6147 "HW State: FAILED.\n");
a5b36321
LC		 6148 qla82xx_clear_drv_active(ha);
6149 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6150 QLA8XXX_DEV_FAILED);
a5b36321 6151 } else {
7c3df132
SK		 6152 ql_log(ql_log_info, base_vha, 0x900c,
6153 "HW State: READY.\n");
a5b36321 6154 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6155 QLA8XXX_DEV_READY);
a5b36321 6156 qla82xx_idc_unlock(ha);
7190575f 6157 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6158 rval = qla82xx_restart_isp(base_vha);
6159 qla82xx_idc_lock(ha);
6160 /* Clear driver state register */
6161 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6162 qla82xx_set_drv_active(base_vha);
6163 }
6164 qla82xx_idc_unlock(ha);
6165 } else {
7c3df132
SK		 6166 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6167 "This devfn is not reset owner = 0x%x.\n",
6168 ha->pdev->devfn);
a5b36321 6169 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6170 QLA8XXX_DEV_READY)) {
7190575f 6171 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6172 rval = qla82xx_restart_isp(base_vha);
6173 qla82xx_idc_lock(ha);
6174 qla82xx_set_drv_active(base_vha);
6175 qla82xx_idc_unlock(ha);
6176 }
6177 }
6178 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6179
6180 return rval;
6181}
6182
14e660e6
SJ		 6183static pci_ers_result_t
6184qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6185{
6186 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6187 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6188 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6189 struct rsp_que *rsp;
6190 int rc, retries = 10;
09483916 6191
7c3df132
SK		 6192 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6193 "Slot Reset.\n");
85880801 6194
90a86fc0
JC		 6195 /* Workaround: qla2xxx driver which access hardware earlier
6196 * needs error state to be pci_channel_io_online.
6197 * Otherwise mailbox command timesout.
6198 */
6199 pdev->error_state = pci_channel_io_normal;
6200
6201 pci_restore_state(pdev);
6202
8c1496bd
RL		 6203 /* pci_restore_state() clears the saved_state flag of the device
6204 * save restored state which resets saved_state flag
6205 */
6206 pci_save_state(pdev);
6207
09483916
BH		 6208 if (ha->mem_only)
6209 rc = pci_enable_device_mem(pdev);
6210 else
6211 rc = pci_enable_device(pdev);
14e660e6 6212
09483916 6213 if (rc) {
7c3df132 6214 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6215 "Can't re-enable PCI device after reset.\n");
a5b36321 6216 goto exit_slot_reset;
14e660e6 6217 }
14e660e6 6218
90a86fc0
JC		 6219 rsp = ha->rsp_q_map[0];
6220 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6221 goto exit_slot_reset;
90a86fc0 6222
e315cd28 6223 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6224 goto exit_slot_reset;
6225
6226 if (IS_QLA82XX(ha)) {
6227 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6228 ret = PCI_ERS_RESULT_RECOVERED;
6229 goto exit_slot_reset;
6230 } else
6231 goto exit_slot_reset;
6232 }
14e660e6 6233
90a86fc0
JC		 6234 while (ha->flags.mbox_busy && retries--)
6235 msleep(1000);
85880801 6236
e315cd28 6237 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6238 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6239 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6240 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6241
90a86fc0 6242
a5b36321 6243exit_slot_reset:
7c3df132
SK		 6244 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6245 "slot_reset return %x.\n", ret);
85880801 6246
14e660e6
SJ		 6247 return ret;
6248}
6249
6250static void
6251qla2xxx_pci_resume(struct pci_dev *pdev)
6252{
e315cd28
AC		 6253 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6254 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6255 int ret;
6256
7c3df132
SK		 6257 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6258 "pci_resume.\n");
85880801 6259
e315cd28 6260 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6261 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6262 ql_log(ql_log_fatal, base_vha, 0x9002,
6263 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6264 }
85880801 6265
3e46f031
LC		 6266 pci_cleanup_aer_uncorrect_error_status(pdev);
6267
85880801 6268 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6269}
6270
2d5a4c34
HM		 6271static void
6272qla83xx_disable_laser(scsi_qla_host_t *vha)
6273{
6274 uint32_t reg, data, fn;
6275 struct qla_hw_data *ha = vha->hw;
6276 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6277
6278 /* pci func #/port # */
6279 ql_dbg(ql_dbg_init, vha, 0x004b,
6280 "Disabling Laser for hba: %p\n", vha);
6281
6282 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6283 (BIT_15|BIT_14|BIT_13|BIT_12));
6284
6285 fn = (fn >> 12);
6286
6287 if (fn & 1)
6288 reg = PORT_1_2031;
6289 else
6290 reg = PORT_0_2031;
6291
6292 data = LASER_OFF_2031;
6293
6294 qla83xx_wr_reg(vha, reg, data);
6295}
6296
5601236b
MH		 6297static int qla2xxx_map_queues(struct Scsi_Host *shost)
6298{
6299 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6300
6301 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6302}
6303
a55b2d21 6304static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6305 .error_detected = qla2xxx_pci_error_detected,
6306 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6307 .slot_reset = qla2xxx_pci_slot_reset,
6308 .resume = qla2xxx_pci_resume,
6309};
6310
5433383e 6311static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6312 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6313 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6314 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6315 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6326 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6327 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6328 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6329 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6330 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6331 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6332 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6333 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6334 { 0 },
6335};
6336MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6337
fca29703 6338static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6339 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6340 .driver = {
6341 .owner = THIS_MODULE,
6342 },
fca29703 6343 .id_table = qla2xxx_pci_tbl,
7ee61397 6344 .probe = qla2x00_probe_one,
4c993f76 6345 .remove = qla2x00_remove_one,
e30d1756 6346 .shutdown = qla2x00_shutdown,
14e660e6 6347 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6348};
6349
75ef9de1 6350static const struct file_operations apidev_fops = {
6a03b4cd 6351 .owner = THIS_MODULE,
6038f373 6352 .llseek = noop_llseek,
6a03b4cd
HZ		 6353};
6354
1da177e4
LT		 6355/**
6356 * qla2x00_module_init - Module initialization.
6357 **/
6358static int __init
6359qla2x00_module_init(void)
6360{
fca29703
AV		 6361 int ret = 0;
6362
1da177e4 6363 /* Allocate cache for SRBs. */
354d6b21 6364 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6365 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6366 if (srb_cachep == NULL) {
7c3df132
SK		 6367 ql_log(ql_log_fatal, NULL, 0x0001,
6368 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6369 return -ENOMEM;
6370 }
6371
2d70c103
NB		 6372 /* Initialize target kmem_cache and mem_pools */
6373 ret = qlt_init();
6374 if (ret < 0) {
6375 kmem_cache_destroy(srb_cachep);
6376 return ret;
6377 } else if (ret > 0) {
6378 /*
6379 * If initiator mode is explictly disabled by qlt_init(),
6380 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6381 * performing scsi_scan_target() during LOOP UP event.
6382 */
6383 qla2xxx_transport_functions.disable_target_scan = 1;
6384 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6385 }
6386
1da177e4
LT		 6387 /* Derive version string. */
6388 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6389 if (ql2xextended_error_logging)
0181944f
AV		 6390 strcat(qla2x00_version_str, "-debug");
6391
1c97a12a
AV		 6392 qla2xxx_transport_template =
6393 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6394 if (!qla2xxx_transport_template) {
6395 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6396 ql_log(ql_log_fatal, NULL, 0x0002,
6397 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6398 qlt_exit();
1da177e4 6399 return -ENODEV;
2c3dfe3f 6400 }
6a03b4cd
HZ		 6401
6402 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6403 if (apidev_major < 0) {
7c3df132
SK		 6404 ql_log(ql_log_fatal, NULL, 0x0003,
6405 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6406 }
6407
2c3dfe3f
SJ		 6408 qla2xxx_transport_vport_template =
6409 fc_attach_transport(&qla2xxx_transport_vport_functions);
6410 if (!qla2xxx_transport_vport_template) {
6411 kmem_cache_destroy(srb_cachep);
2d70c103 6412 qlt_exit();
2c3dfe3f 6413 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6414 ql_log(ql_log_fatal, NULL, 0x0004,
6415 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6416 return -ENODEV;
2c3dfe3f 6417 }
7c3df132
SK		 6418 ql_log(ql_log_info, NULL, 0x0005,
6419 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6420 qla2x00_version_str);
7ee61397 6421 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6422 if (ret) {
6423 kmem_cache_destroy(srb_cachep);
2d70c103 6424 qlt_exit();
fca29703 6425 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6426 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6427 ql_log(ql_log_fatal, NULL, 0x0006,
6428 "pci_register_driver failed...ret=%d Failing load!.\n",
6429 ret);
fca29703
AV		 6430 }
6431 return ret;
1da177e4
LT		 6432}
6433
6434/**
6435 * qla2x00_module_exit - Module cleanup.
6436 **/
6437static void __exit
6438qla2x00_module_exit(void)
6439{
6a03b4cd 6440 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6441 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6442 qla2x00_release_firmware();
354d6b21 6443 kmem_cache_destroy(srb_cachep);
2d70c103 6444 qlt_exit();
a9083016
GM		 6445 if (ctx_cachep)
6446 kmem_cache_destroy(ctx_cachep);
1da177e4 6447 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6448 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6449}
6450
6451module_init(qla2x00_module_init);
6452module_exit(qla2x00_module_exit);
6453
6454MODULE_AUTHOR("QLogic Corporation");
6455MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6456MODULE_LICENSE("GPL");
6457MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6458MODULE_FIRMWARE(FW_FILE_ISP21XX);
6459MODULE_FIRMWARE(FW_FILE_ISP22XX);
6460MODULE_FIRMWARE(FW_FILE_ISP2300);
6461MODULE_FIRMWARE(FW_FILE_ISP2322);
6462MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6463MODULE_FIRMWARE(FW_FILE_ISP25XX);
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