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[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
41dc529a
QT		 240int ql2xmvasynctoatio = 1;
241module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
242MODULE_PARM_DESC(ql2xmvasynctoatio,
243 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
244 "0 (Default). Do not move IOCBs"
245 "1 - Move IOCBs.");
246
1da177e4 247/*
fa2a1ce5 248 * SCSI host template entry points
1da177e4
LT		 249 */
250static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 251static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 252static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
253static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 254static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 255static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 256static int qla2xxx_eh_abort(struct scsi_cmnd *);
257static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 258static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 259static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
260static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 261
1a2fbf18 262static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 263static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 264static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 265static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 266
a5326f86 267struct scsi_host_template qla2xxx_driver_template = {
1da177e4 268 .module = THIS_MODULE,
cb63067a 269 .name = QLA2XXX_DRIVER_NAME,
a5326f86 270 .queuecommand = qla2xxx_queuecommand,
fca29703 271
b6a05c82 272 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 273 .eh_abort_handler = qla2xxx_eh_abort,
274 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 275 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 276 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
277 .eh_host_reset_handler = qla2xxx_eh_host_reset,
278
279 .slave_configure = qla2xxx_slave_configure,
280
281 .slave_alloc = qla2xxx_slave_alloc,
282 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 283 .scan_finished = qla2xxx_scan_finished,
284 .scan_start = qla2xxx_scan_start,
db5ed4df 285 .change_queue_depth = scsi_change_queue_depth,
5601236b 286 .map_queues = qla2xxx_map_queues,
fca29703
AV		 287 .this_id = -1,
288 .cmd_per_lun = 3,
289 .use_clustering = ENABLE_CLUSTERING,
290 .sg_tablesize = SG_ALL,
291
292 .max_sectors = 0xFFFF,
afb046e2 293 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 294
295 .supported_mode = MODE_INITIATOR,
c40ecc12 296 .track_queue_depth = 1,
fca29703
AV		 297};
298
1da177e4 299static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 300struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 301
1da177e4
LT		 302/* TODO Convert to inlines
303 *
304 * Timer routines
305 */
1da177e4 306
2c3dfe3f 307__inline__ void
e315cd28 308qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 309{
e315cd28
AC		 310 init_timer(&vha->timer);
311 vha->timer.expires = jiffies + interval * HZ;
312 vha->timer.data = (unsigned long)vha;
313 vha->timer.function = (void (*)(unsigned long))func;
314 add_timer(&vha->timer);
315 vha->timer_active = 1;
1da177e4
LT		 316}
317
318static inline void
e315cd28 319qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 320{
a9083016 321 /* Currently used for 82XX only. */
7c3df132
SK		 322 if (vha->device_flags & DFLG_DEV_FAILED) {
323 ql_dbg(ql_dbg_timer, vha, 0x600d,
324 "Device in a failed state, returning.\n");
a9083016 325 return;
7c3df132 326 }
a9083016 327
e315cd28 328 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 329}
330
a824ebb3 331static __inline__ void
e315cd28 332qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 333{
e315cd28
AC		 334 del_timer_sync(&vha->timer);
335 vha->timer_active = 0;
1da177e4
LT		 336}
337
1da177e4
LT		 338static int qla2x00_do_dpc(void *data);
339
340static void qla2x00_rst_aen(scsi_qla_host_t *);
341
73208dfd
AC		 342static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
343 struct req_que **, struct rsp_que **);
e30d1756 344static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 345static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 346int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
347 struct qla_qpair *qpair);
1da177e4 348
1da177e4 349/* -------------------------------------------------------------------------- */
9a347ff4
CD		 350static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
351 struct rsp_que *rsp)
73208dfd 352{
7c3df132 353 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 354 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 355 GFP_KERNEL);
356 if (!ha->req_q_map) {
7c3df132
SK		 357 ql_log(ql_log_fatal, vha, 0x003b,
358 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 359 goto fail_req_map;
360 }
361
2afa19a9 362 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 363 GFP_KERNEL);
364 if (!ha->rsp_q_map) {
7c3df132
SK		 365 ql_log(ql_log_fatal, vha, 0x003c,
366 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 367 goto fail_rsp_map;
368 }
d7459527
MH		 369
370 if (ql2xmqsupport && ha->max_qpairs) {
371 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
372 GFP_KERNEL);
373 if (!ha->queue_pair_map) {
374 ql_log(ql_log_fatal, vha, 0x0180,
375 "Unable to allocate memory for queue pair ptrs.\n");
376 goto fail_qpair_map;
377 }
378 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
379 if (ha->base_qpair == NULL) {
380 ql_log(ql_log_warn, vha, 0x0182,
381 "Failed to allocate base queue pair memory.\n");
382 goto fail_base_qpair;
383 }
384 ha->base_qpair->req = req;
385 ha->base_qpair->rsp = rsp;
386 }
387
9a347ff4
CD		 388 /*
389 * Make sure we record at least the request and response queue zero in
390 * case we need to free them if part of the probe fails.
391 */
392 ha->rsp_q_map[0] = rsp;
393 ha->req_q_map[0] = req;
73208dfd
AC		 394 set_bit(0, ha->rsp_qid_map);
395 set_bit(0, ha->req_qid_map);
396 return 1;
397
d7459527
MH		 398fail_base_qpair:
399 kfree(ha->queue_pair_map);
400fail_qpair_map:
401 kfree(ha->rsp_q_map);
402 ha->rsp_q_map = NULL;
73208dfd
AC		 403fail_rsp_map:
404 kfree(ha->req_q_map);
405 ha->req_q_map = NULL;
406fail_req_map:
407 return -ENOMEM;
408}
409
2afa19a9 410static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 411{
8ae6d9c7
GM		 412 if (IS_QLAFX00(ha)) {
413 if (req && req->ring_fx00)
414 dma_free_coherent(&ha->pdev->dev,
415 (req->length_fx00 + 1) * sizeof(request_t),
416 req->ring_fx00, req->dma_fx00);
417 } else if (req && req->ring)
73208dfd
AC		 418 dma_free_coherent(&ha->pdev->dev,
419 (req->length + 1) * sizeof(request_t),
420 req->ring, req->dma);
421
8d93f550
CD		 422 if (req)
423 kfree(req->outstanding_cmds);
424
73208dfd
AC		 425 kfree(req);
426 req = NULL;
427}
428
2afa19a9
AC		 429static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
430{
8ae6d9c7
GM		 431 if (IS_QLAFX00(ha)) {
432 if (rsp && rsp->ring)
433 dma_free_coherent(&ha->pdev->dev,
434 (rsp->length_fx00 + 1) * sizeof(request_t),
435 rsp->ring_fx00, rsp->dma_fx00);
436 } else if (rsp && rsp->ring) {
2afa19a9
AC		 437 dma_free_coherent(&ha->pdev->dev,
438 (rsp->length + 1) * sizeof(response_t),
439 rsp->ring, rsp->dma);
8ae6d9c7 440 }
2afa19a9
AC		 441 kfree(rsp);
442 rsp = NULL;
443}
444
73208dfd
AC		 445static void qla2x00_free_queues(struct qla_hw_data *ha)
446{
447 struct req_que *req;
448 struct rsp_que *rsp;
449 int cnt;
093df737 450 unsigned long flags;
73208dfd 451
093df737 452 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 453 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 454 if (!test_bit(cnt, ha->req_qid_map))
455 continue;
456
73208dfd 457 req = ha->req_q_map[cnt];
093df737
QT		 458 clear_bit(cnt, ha->req_qid_map);
459 ha->req_q_map[cnt] = NULL;
460
461 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 462 qla2x00_free_req_que(ha, req);
093df737 463 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 464 }
093df737
QT		 465 spin_unlock_irqrestore(&ha->hardware_lock, flags);
466
73208dfd
AC		 467 kfree(ha->req_q_map);
468 ha->req_q_map = NULL;
2afa19a9 469
093df737
QT		 470
471 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 472 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 473 if (!test_bit(cnt, ha->rsp_qid_map))
474 continue;
475
2afa19a9 476 rsp = ha->rsp_q_map[cnt];
c3c42394 477 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 478 ha->rsp_q_map[cnt] = NULL;
479 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 480 qla2x00_free_rsp_que(ha, rsp);
093df737 481 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 482 }
093df737
QT		 483 spin_unlock_irqrestore(&ha->hardware_lock, flags);
484
2afa19a9
AC		 485 kfree(ha->rsp_q_map);
486 ha->rsp_q_map = NULL;
73208dfd
AC		 487}
488
1da177e4 489static char *
e315cd28 490qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 491{
e315cd28 492 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 493 static char *pci_bus_modes[] = {
494 "33", "66", "100", "133",
495 };
496 uint16_t pci_bus;
497
498 strcpy(str, "PCI");
499 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
500 if (pci_bus) {
501 strcat(str, "-X (");
502 strcat(str, pci_bus_modes[pci_bus]);
503 } else {
504 pci_bus = (ha->pci_attr & BIT_8) >> 8;
505 strcat(str, " (");
506 strcat(str, pci_bus_modes[pci_bus]);
507 }
508 strcat(str, " MHz)");
509
510 return (str);
511}
512
fca29703 513static char *
e315cd28 514qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 515{
516 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 517 struct qla_hw_data *ha = vha->hw;
fca29703 518 uint32_t pci_bus;
fca29703 519
62a276f8 520 if (pci_is_pcie(ha->pdev)) {
fca29703 521 char lwstr[6];
62a276f8 522 uint32_t lstat, lspeed, lwidth;
fca29703 523
62a276f8
BH		 524 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
525 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
526 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 527
528 strcpy(str, "PCIe (");
49300af7
SK		 529 switch (lspeed) {
530 case 1:
c87a0d8c 531 strcat(str, "2.5GT/s ");
49300af7
SK		 532 break;
533 case 2:
c87a0d8c 534 strcat(str, "5.0GT/s ");
49300af7
SK		 535 break;
536 case 3:
537 strcat(str, "8.0GT/s ");
538 break;
539 default:
fca29703 540 strcat(str, "<unknown> ");
49300af7
SK		 541 break;
542 }
fca29703
AV		 543 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
544 strcat(str, lwstr);
545
546 return str;
547 }
548
549 strcpy(str, "PCI");
550 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
551 if (pci_bus == 0 || pci_bus == 8) {
552 strcat(str, " (");
553 strcat(str, pci_bus_modes[pci_bus >> 3]);
554 } else {
555 strcat(str, "-X ");
556 if (pci_bus & BIT_2)
557 strcat(str, "Mode 2");
558 else
559 strcat(str, "Mode 1");
560 strcat(str, " (");
561 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
562 }
563 strcat(str, " MHz)");
564
565 return str;
566}
567
e5f82ab8 568static char *
df57caba 569qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 570{
571 char un_str[10];
e315cd28 572 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 573
df57caba
HM		 574 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
575 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 576
577 if (ha->fw_attributes & BIT_9) {
578 strcat(str, "FLX");
579 return (str);
580 }
581
582 switch (ha->fw_attributes & 0xFF) {
583 case 0x7:
584 strcat(str, "EF");
585 break;
586 case 0x17:
587 strcat(str, "TP");
588 break;
589 case 0x37:
590 strcat(str, "IP");
591 break;
592 case 0x77:
593 strcat(str, "VI");
594 break;
595 default:
596 sprintf(un_str, "(%x)", ha->fw_attributes);
597 strcat(str, un_str);
598 break;
599 }
600 if (ha->fw_attributes & 0x100)
601 strcat(str, "X");
602
603 return (str);
604}
605
e5f82ab8 606static char *
df57caba 607qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 608{
e315cd28 609 struct qla_hw_data *ha = vha->hw;
f0883ac6 610
df57caba 611 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 612 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 613 return str;
fca29703
AV		 614}
615
9ba56b95 616void
25ff6af1 617qla2x00_sp_free_dma(void *ptr)
fca29703 618{
25ff6af1
JC		 619 srb_t *sp = ptr;
620 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 621 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 622 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 623
9ba56b95
GM		 624 if (sp->flags & SRB_DMA_VALID) {
625 scsi_dma_unmap(cmd);
626 sp->flags &= ~SRB_DMA_VALID;
7c3df132 627 }
fca29703 628
9ba56b95
GM		 629 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
630 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
631 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
632 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
633 }
634
635 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
636 /* List assured to be having elements */
f83adb61 637 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 638 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
639 }
640
641 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
642 dma_pool_free(ha->dl_dma_pool, ctx,
643 ((struct crc_context *)ctx)->crc_ctx_dma);
644 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
645 }
646
647 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
648 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 649
9ba56b95
GM		 650 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
651 ctx1->fcp_cmnd_dma);
652 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
653 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
654 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
655 mempool_free(ctx1, ha->ctx_mempool);
656 ctx1 = NULL;
657 }
658
659 CMD_SP(cmd) = NULL;
25ff6af1 660 qla2x00_rel_sp(sp);
9ba56b95
GM		 661}
662
d7459527 663void
25ff6af1 664qla2x00_sp_compl(void *ptr, int res)
9ba56b95 665{
25ff6af1 666 srb_t *sp = ptr;
9ba56b95
GM		 667 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
668
669 cmd->result = res;
670
671 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 672 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 673 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
674 sp, GET_CMD_SP(sp));
675 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 676 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 677 return;
678 }
679 if (!atomic_dec_and_test(&sp->ref_count))
680 return;
681
25ff6af1 682 qla2x00_sp_free_dma(sp);
9ba56b95 683 cmd->scsi_done(cmd);
fca29703
AV		 684}
685
d7459527 686void
25ff6af1 687qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 688{
689 srb_t *sp = (srb_t *)ptr;
690 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
691 struct qla_hw_data *ha = sp->fcport->vha->hw;
692 void *ctx = GET_CMD_CTX_SP(sp);
693
694 if (sp->flags & SRB_DMA_VALID) {
695 scsi_dma_unmap(cmd);
696 sp->flags &= ~SRB_DMA_VALID;
697 }
698
699 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
700 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
701 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
702 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
703 }
704
705 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
706 /* List assured to be having elements */
707 qla2x00_clean_dsd_pool(ha, sp, NULL);
708 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
709 }
710
711 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
712 dma_pool_free(ha->dl_dma_pool, ctx,
713 ((struct crc_context *)ctx)->crc_ctx_dma);
714 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
715 }
716
717 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
718 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
719
720 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
721 ctx1->fcp_cmnd_dma);
722 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
723 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
724 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
725 mempool_free(ctx1, ha->ctx_mempool);
726 }
727
728 CMD_SP(cmd) = NULL;
729 qla2xxx_rel_qpair_sp(sp->qpair, sp);
730}
731
732void
25ff6af1 733qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 734{
25ff6af1 735 srb_t *sp = ptr;
d7459527
MH		 736 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
737
738 cmd->result = res;
739
740 if (atomic_read(&sp->ref_count) == 0) {
741 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
742 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
743 sp, GET_CMD_SP(sp));
744 if (ql2xextended_error_logging & ql_dbg_io)
745 WARN_ON(atomic_read(&sp->ref_count) == 0);
746 return;
747 }
748 if (!atomic_dec_and_test(&sp->ref_count))
749 return;
750
25ff6af1 751 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 752 cmd->scsi_done(cmd);
753}
754
8ae6d9c7
GM		 755/* If we are SP1 here, we need to still take and release the host_lock as SP1
756 * does not have the changes necessary to avoid taking host->host_lock.
757 */
1da177e4 758static int
f5e3e40b 759qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 760{
134ae078 761 scsi_qla_host_t *vha = shost_priv(host);
fca29703 762 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 763 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 764 struct qla_hw_data *ha = vha->hw;
765 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 766 srb_t *sp;
767 int rval;
5601236b
MH		 768 struct qla_qpair *qpair = NULL;
769 uint32_t tag;
770 uint16_t hwq;
fca29703 771
04dfaa53
MFO		 772 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
773 cmd->result = DID_NO_CONNECT << 16;
774 goto qc24_fail_command;
775 }
776
5601236b
MH		 777 if (ha->mqenable) {
778 if (shost_use_blk_mq(vha->host)) {
779 tag = blk_mq_unique_tag(cmd->request);
780 hwq = blk_mq_unique_tag_to_hwq(tag);
781 qpair = ha->queue_pair_map[hwq];
782 } else if (vha->vp_idx && vha->qpair) {
783 qpair = vha->qpair;
784 }
785
786 if (qpair)
787 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 788 }
789
85880801 790 if (ha->flags.eeh_busy) {
7c3df132 791 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 792 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 793 "PCI Channel IO permanent failure, exiting "
794 "cmd=%p.\n", cmd);
b9b12f73 795 cmd->result = DID_NO_CONNECT << 16;
7c3df132 796 } else {
5f28d2d7 797 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 798 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 799 cmd->result = DID_REQUEUE << 16;
7c3df132 800 }
14e660e6
SJ		 801 goto qc24_fail_command;
802 }
803
19a7b4ae
JSEC		 804 rval = fc_remote_port_chkready(rport);
805 if (rval) {
806 cmd->result = rval;
5f28d2d7 807 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 808 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
809 cmd, rval);
fca29703
AV		 810 goto qc24_fail_command;
811 }
812
bad75002
AE		 813 if (!vha->flags.difdix_supported &&
814 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 815 ql_dbg(ql_dbg_io, vha, 0x3004,
816 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
817 cmd);
bad75002
AE		 818 cmd->result = DID_NO_CONNECT << 16;
819 goto qc24_fail_command;
820 }
aa651be8
CD		 821
822 if (!fcport) {
823 cmd->result = DID_NO_CONNECT << 16;
824 goto qc24_fail_command;
825 }
826
fca29703
AV		 827 if (atomic_read(&fcport->state) != FCS_ONLINE) {
828 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 829 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 830 ql_dbg(ql_dbg_io, vha, 0x3005,
831 "Returning DNC, fcport_state=%d loop_state=%d.\n",
832 atomic_read(&fcport->state),
833 atomic_read(&base_vha->loop_state));
fca29703
AV		 834 cmd->result = DID_NO_CONNECT << 16;
835 goto qc24_fail_command;
836 }
7b594131 837 goto qc24_target_busy;
fca29703
AV		 838 }
839
e05fe292
CD		 840 /*
841 * Return target busy if we've received a non-zero retry_delay_timer
842 * in a FCP_RSP.
843 */
975f7d46
BP		 844 if (fcport->retry_delay_timestamp == 0) {
845 /* retry delay not set */
846 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 847 fcport->retry_delay_timestamp = 0;
848 else
849 goto qc24_target_busy;
850
b00ee7d7 851 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 852 if (!sp)
f5e3e40b 853 goto qc24_host_busy;
fca29703 854
9ba56b95
GM		 855 sp->u.scmd.cmd = cmd;
856 sp->type = SRB_SCSI_CMD;
857 atomic_set(&sp->ref_count, 1);
858 CMD_SP(cmd) = (void *)sp;
859 sp->free = qla2x00_sp_free_dma;
860 sp->done = qla2x00_sp_compl;
861
e315cd28 862 rval = ha->isp_ops->start_scsi(sp);
7c3df132 863 if (rval != QLA_SUCCESS) {
53016ed3 864 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 865 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 866 goto qc24_host_busy_free_sp;
7c3df132 867 }
fca29703 868
fca29703
AV		 869 return 0;
870
871qc24_host_busy_free_sp:
25ff6af1 872 qla2x00_sp_free_dma(sp);
fca29703 873
f5e3e40b 874qc24_host_busy:
fca29703
AV		 875 return SCSI_MLQUEUE_HOST_BUSY;
876
7b594131
MC		 877qc24_target_busy:
878 return SCSI_MLQUEUE_TARGET_BUSY;
879
fca29703 880qc24_fail_command:
f5e3e40b 881 cmd->scsi_done(cmd);
fca29703
AV		 882
883 return 0;
884}
885
d7459527
MH		 886/* For MQ supported I/O */
887int
888qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
889 struct qla_qpair *qpair)
890{
891 scsi_qla_host_t *vha = shost_priv(host);
892 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
893 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
894 struct qla_hw_data *ha = vha->hw;
895 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
896 srb_t *sp;
897 int rval;
898
899 rval = fc_remote_port_chkready(rport);
900 if (rval) {
901 cmd->result = rval;
902 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
903 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
904 cmd, rval);
905 goto qc24_fail_command;
906 }
907
908 if (!fcport) {
909 cmd->result = DID_NO_CONNECT << 16;
910 goto qc24_fail_command;
911 }
912
913 if (atomic_read(&fcport->state) != FCS_ONLINE) {
914 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
915 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
916 ql_dbg(ql_dbg_io, vha, 0x3077,
917 "Returning DNC, fcport_state=%d loop_state=%d.\n",
918 atomic_read(&fcport->state),
919 atomic_read(&base_vha->loop_state));
920 cmd->result = DID_NO_CONNECT << 16;
921 goto qc24_fail_command;
922 }
923 goto qc24_target_busy;
924 }
925
926 /*
927 * Return target busy if we've received a non-zero retry_delay_timer
928 * in a FCP_RSP.
929 */
930 if (fcport->retry_delay_timestamp == 0) {
931 /* retry delay not set */
932 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
933 fcport->retry_delay_timestamp = 0;
934 else
935 goto qc24_target_busy;
936
937 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
938 if (!sp)
939 goto qc24_host_busy;
940
941 sp->u.scmd.cmd = cmd;
942 sp->type = SRB_SCSI_CMD;
943 atomic_set(&sp->ref_count, 1);
944 CMD_SP(cmd) = (void *)sp;
945 sp->free = qla2xxx_qpair_sp_free_dma;
946 sp->done = qla2xxx_qpair_sp_compl;
947 sp->qpair = qpair;
948
949 rval = ha->isp_ops->start_scsi_mq(sp);
950 if (rval != QLA_SUCCESS) {
951 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
952 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
953 if (rval == QLA_INTERFACE_ERROR)
954 goto qc24_fail_command;
955 goto qc24_host_busy_free_sp;
956 }
957
958 return 0;
959
960qc24_host_busy_free_sp:
25ff6af1 961 qla2xxx_qpair_sp_free_dma(sp);
d7459527
MH		 962
963qc24_host_busy:
964 return SCSI_MLQUEUE_HOST_BUSY;
965
966qc24_target_busy:
967 return SCSI_MLQUEUE_TARGET_BUSY;
968
969qc24_fail_command:
970 cmd->scsi_done(cmd);
971
972 return 0;
973}
974
1da177e4
LT		 975/*
976 * qla2x00_eh_wait_on_command
977 * Waits for the command to be returned by the Firmware for some
978 * max time.
979 *
980 * Input:
1da177e4 981 * cmd = Scsi Command to wait on.
1da177e4
LT		 982 *
983 * Return:
984 * Not Found : 0
985 * Found : 1
986 */
987static int
e315cd28 988qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 989{
fe74c71f 990#define ABORT_POLLING_PERIOD 1000
478c3b03 991#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 992 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 993 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
994 struct qla_hw_data *ha = vha->hw;
f4f051eb 995 int ret = QLA_SUCCESS;
1da177e4 996
85880801 997 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 998 ql_dbg(ql_dbg_taskm, vha, 0x8005,
999 "Return:eh_wait.\n");
85880801
AV		 1000 return ret;
1001 }
1002
d970432c 1003 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1004 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1005 }
1006 if (CMD_SP(cmd))
1007 ret = QLA_FUNCTION_FAILED;
1da177e4 1008
f4f051eb 1009 return ret;
1da177e4
LT		 1010}
1011
1012/*
1013 * qla2x00_wait_for_hba_online
fa2a1ce5 1014 * Wait till the HBA is online after going through
1da177e4
LT		 1015 * <= MAX_RETRIES_OF_ISP_ABORT or
1016 * finally HBA is disabled ie marked offline
1017 *
1018 * Input:
1019 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1020 *
1021 * Note:
1da177e4
LT		 1022 * Does context switching-Release SPIN_LOCK
1023 * (if any) before calling this routine.
1024 *
1025 * Return:
1026 * Success (Adapter is online) : 0
1027 * Failed (Adapter is offline/disabled) : 1
1028 */
854165f4 1029int
e315cd28 1030qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1031{
fca29703
AV		 1032 int return_status;
1033 unsigned long wait_online;
e315cd28
AC		 1034 struct qla_hw_data *ha = vha->hw;
1035 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1036
fa2a1ce5 1037 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1038 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1039 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1040 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1041 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1042
1043 msleep(1000);
1044 }
e315cd28 1045 if (base_vha->flags.online)
fa2a1ce5 1046 return_status = QLA_SUCCESS;
1da177e4
LT		 1047 else
1048 return_status = QLA_FUNCTION_FAILED;
1049
1da177e4
LT		 1050 return (return_status);
1051}
1052
726b8548
QT		 1053static inline int test_fcport_count(scsi_qla_host_t *vha)
1054{
1055 struct qla_hw_data *ha = vha->hw;
1056 unsigned long flags;
1057 int res;
1058
1059 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1060 ql_dbg(ql_dbg_init, vha, 0xffff,
1061 "tgt %p, fcport_count=%d\n",
1062 vha, vha->fcport_count);
1063 res = (vha->fcport_count == 0);
1064 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1065
1066 return res;
1067}
1068
1069/*
1070 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1071 * it has dependency on UNLOADING flag to stop device discovery
1072 */
1073static void
1074qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1075{
1076 qla2x00_mark_all_devices_lost(vha, 0);
1077
1078 wait_event(vha->fcport_waitQ, test_fcport_count(vha));
1079}
1080
86fbee86 1081/*
638a1a01
SC		 1082 * qla2x00_wait_for_hba_ready
1083 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1084 *
1085 * Input:
1086 * ha - pointer to host adapter structure
1087 *
1088 * Note:
1089 * Does context switching-Release SPIN_LOCK
1090 * (if any) before calling this routine.
1091 *
86fbee86 1092 */
638a1a01
SC		 1093static void
1094qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1095{
86fbee86 1096 struct qla_hw_data *ha = vha->hw;
783e0dc4 1097 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1098
1d483901
DC		 1099 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1100 ha->flags.mbox_busy) ||
1101 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1102 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1103 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1104 break;
86fbee86 1105 msleep(1000);
783e0dc4 1106 }
86fbee86
LC		 1107}
1108
2533cf67
LC		 1109int
1110qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1111{
1112 int return_status;
1113 unsigned long wait_reset;
1114 struct qla_hw_data *ha = vha->hw;
1115 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1116
1117 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1118 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1119 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1120 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1121 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1122
1123 msleep(1000);
1124
1125 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1126 ha->flags.chip_reset_done)
1127 break;
1128 }
1129 if (ha->flags.chip_reset_done)
1130 return_status = QLA_SUCCESS;
1131 else
1132 return_status = QLA_FUNCTION_FAILED;
1133
1134 return return_status;
1135}
1136
083a469d
GM		 1137static void
1138sp_get(struct srb *sp)
1139{
1140 atomic_inc(&sp->ref_count);
1141}
1142
a465537a
SC		 1143#define ISP_REG_DISCONNECT 0xffffffffU
1144/**************************************************************************
1145* qla2x00_isp_reg_stat
1146*
1147* Description:
1148* Read the host status register of ISP before aborting the command.
1149*
1150* Input:
1151* ha = pointer to host adapter structure.
1152*
1153*
1154* Returns:
1155* Either true or false.
1156*
1157* Note: Return true if there is register disconnect.
1158**************************************************************************/
1159static inline
1160uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1161{
1162 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1163
1164 return ((RD_REG_DWORD(&reg->host_status)) == ISP_REG_DISCONNECT);
1165}
1166
1da177e4
LT		 1167/**************************************************************************
1168* qla2xxx_eh_abort
1169*
1170* Description:
1171* The abort function will abort the specified command.
1172*
1173* Input:
1174* cmd = Linux SCSI command packet to be aborted.
1175*
1176* Returns:
1177* Either SUCCESS or FAILED.
1178*
1179* Note:
2ea00202 1180* Only return FAILED if command not returned by firmware.
1da177e4 1181**************************************************************************/
e5f82ab8 1182static int
1da177e4
LT		 1183qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1184{
e315cd28 1185 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1186 srb_t *sp;
4e98d3b8 1187 int ret;
9cb78c16
HR		 1188 unsigned int id;
1189 uint64_t lun;
18e144d3 1190 unsigned long flags;
f934c9d0 1191 int rval, wait = 0;
e315cd28 1192 struct qla_hw_data *ha = vha->hw;
1da177e4 1193
a465537a
SC		 1194 if (qla2x00_isp_reg_stat(ha)) {
1195 ql_log(ql_log_info, vha, 0x8042,
1196 "PCI/Register disconnect, exiting.\n");
1197 return FAILED;
1198 }
f4f051eb 1199 if (!CMD_SP(cmd))
2ea00202 1200 return SUCCESS;
1da177e4 1201
4e98d3b8
AV		 1202 ret = fc_block_scsi_eh(cmd);
1203 if (ret != 0)
1204 return ret;
1205 ret = SUCCESS;
1206
f4f051eb
AV		 1207 id = cmd->device->id;
1208 lun = cmd->device->lun;
1da177e4 1209
e315cd28 1210 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1211 sp = (srb_t *) CMD_SP(cmd);
1212 if (!sp) {
1213 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1214 return SUCCESS;
1215 }
1da177e4 1216
7c3df132 1217 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1218 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1219 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1220
170babc3
MC		 1221 /* Get a reference to the sp and drop the lock.*/
1222 sp_get(sp);
083a469d 1223
e315cd28 1224 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1225 rval = ha->isp_ops->abort_command(sp);
1226 if (rval) {
96219424 1227 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1228 ret = SUCCESS;
96219424 1229 else
f934c9d0
CD		 1230 ret = FAILED;
1231
7c3df132 1232 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1233 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1234 } else {
7c3df132 1235 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1236 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1237 wait = 1;
1238 }
75942064
SK		 1239
1240 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1241 sp->done(sp, 0);
75942064 1242 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1243
bc91ade9
CD		 1244 /* Did the command return during mailbox execution? */
1245 if (ret == FAILED && !CMD_SP(cmd))
1246 ret = SUCCESS;
1247
f4f051eb 1248 /* Wait for the command to be returned. */
2ea00202 1249 if (wait) {
e315cd28 1250 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1251 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1252 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1253 ret = FAILED;
f4f051eb 1254 }
1da177e4 1255 }
1da177e4 1256
7c3df132 1257 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1258 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1259 vha->host_no, id, lun, wait, ret);
1da177e4 1260
f4f051eb
AV		 1261 return ret;
1262}
1da177e4 1263
4d78c973 1264int
e315cd28 1265qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1266 uint64_t l, enum nexus_wait_type type)
f4f051eb 1267{
17d98630 1268 int cnt, match, status;
18e144d3 1269 unsigned long flags;
e315cd28 1270 struct qla_hw_data *ha = vha->hw;
73208dfd 1271 struct req_que *req;
4d78c973 1272 srb_t *sp;
9ba56b95 1273 struct scsi_cmnd *cmd;
1da177e4 1274
523ec773 1275 status = QLA_SUCCESS;
17d98630 1276
e315cd28 1277 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1278 req = vha->req;
17d98630 1279 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1280 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1281 sp = req->outstanding_cmds[cnt];
1282 if (!sp)
523ec773 1283 continue;
9ba56b95 1284 if (sp->type != SRB_SCSI_CMD)
cf53b069 1285 continue;
25ff6af1 1286 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1287 continue;
1288 match = 0;
9ba56b95 1289 cmd = GET_CMD_SP(sp);
17d98630
AC		 1290 switch (type) {
1291 case WAIT_HOST:
1292 match = 1;
1293 break;
1294 case WAIT_TARGET:
9ba56b95 1295 match = cmd->device->id == t;
17d98630
AC		 1296 break;
1297 case WAIT_LUN:
9ba56b95
GM		 1298 match = (cmd->device->id == t &&
1299 cmd->device->lun == l);
17d98630 1300 break;
73208dfd 1301 }
17d98630
AC		 1302 if (!match)
1303 continue;
1304
1305 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1306 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1307 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1308 }
e315cd28 1309 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1310
1311 return status;
1da177e4
LT		 1312}
1313
523ec773
AV		 1314static char *reset_errors[] = {
1315 "HBA not online",
1316 "HBA not ready",
1317 "Task management failed",
1318 "Waiting for command completions",
1319};
1da177e4 1320
e5f82ab8 1321static int
523ec773 1322__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1323 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1324{
e315cd28 1325 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1326 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1327 int err;
1da177e4 1328
7c3df132 1329 if (!fcport) {
523ec773 1330 return FAILED;
7c3df132 1331 }
1da177e4 1332
4e98d3b8
AV		 1333 err = fc_block_scsi_eh(cmd);
1334 if (err != 0)
1335 return err;
1336
7c3df132 1337 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1338 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1339 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1340
523ec773 1341 err = 0;
7c3df132
SK		 1342 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1343 ql_log(ql_log_warn, vha, 0x800a,
1344 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1345 goto eh_reset_failed;
7c3df132 1346 }
523ec773 1347 err = 2;
2afa19a9 1348 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1349 != QLA_SUCCESS) {
1350 ql_log(ql_log_warn, vha, 0x800c,
1351 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1352 goto eh_reset_failed;
7c3df132 1353 }
523ec773 1354 err = 3;
e315cd28 1355 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1356 cmd->device->lun, type) != QLA_SUCCESS) {
1357 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1358 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1359 goto eh_reset_failed;
7c3df132 1360 }
523ec773 1361
7c3df132 1362 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1363 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1364 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1365
1366 return SUCCESS;
1367
4d78c973 1368eh_reset_failed:
7c3df132 1369 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1370 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1371 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1372 cmd);
523ec773
AV		 1373 return FAILED;
1374}
1da177e4 1375
523ec773
AV		 1376static int
1377qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1378{
e315cd28
AC		 1379 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1380 struct qla_hw_data *ha = vha->hw;
1da177e4 1381
a465537a
SC		 1382 if (qla2x00_isp_reg_stat(ha)) {
1383 ql_log(ql_log_info, vha, 0x803e,
1384 "PCI/Register disconnect, exiting.\n");
1385 return FAILED;
1386 }
1387
523ec773
AV		 1388 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1389 ha->isp_ops->lun_reset);
1da177e4
LT		 1390}
1391
1da177e4 1392static int
523ec773 1393qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1394{
e315cd28
AC		 1395 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1396 struct qla_hw_data *ha = vha->hw;
1da177e4 1397
a465537a
SC		 1398 if (qla2x00_isp_reg_stat(ha)) {
1399 ql_log(ql_log_info, vha, 0x803f,
1400 "PCI/Register disconnect, exiting.\n");
1401 return FAILED;
1402 }
1403
523ec773
AV		 1404 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1405 ha->isp_ops->target_reset);
1da177e4
LT		 1406}
1407
1da177e4
LT		 1408/**************************************************************************
1409* qla2xxx_eh_bus_reset
1410*
1411* Description:
1412* The bus reset function will reset the bus and abort any executing
1413* commands.
1414*
1415* Input:
1416* cmd = Linux SCSI command packet of the command that cause the
1417* bus reset.
1418*
1419* Returns:
1420* SUCCESS/FAILURE (defined as macro in scsi.h).
1421*
1422**************************************************************************/
e5f82ab8 1423static int
1da177e4
LT		 1424qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1425{
e315cd28 1426 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1427 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1428 int ret = FAILED;
9cb78c16
HR		 1429 unsigned int id;
1430 uint64_t lun;
a465537a
SC		 1431 struct qla_hw_data *ha = vha->hw;
1432
1433 if (qla2x00_isp_reg_stat(ha)) {
1434 ql_log(ql_log_info, vha, 0x8040,
1435 "PCI/Register disconnect, exiting.\n");
1436 return FAILED;
1437 }
f4f051eb 1438
f4f051eb
AV		 1439 id = cmd->device->id;
1440 lun = cmd->device->lun;
1da177e4 1441
7c3df132 1442 if (!fcport) {
f4f051eb 1443 return ret;
7c3df132 1444 }
1da177e4 1445
4e98d3b8
AV		 1446 ret = fc_block_scsi_eh(cmd);
1447 if (ret != 0)
1448 return ret;
1449 ret = FAILED;
1450
7c3df132 1451 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1452 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1453
e315cd28 1454 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1455 ql_log(ql_log_fatal, vha, 0x8013,
1456 "Wait for hba online failed board disabled.\n");
f4f051eb 1457 goto eh_bus_reset_done;
1da177e4
LT		 1458 }
1459
ad537689
SK		 1460 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1461 ret = SUCCESS;
1462
f4f051eb
AV		 1463 if (ret == FAILED)
1464 goto eh_bus_reset_done;
1da177e4 1465
9a41a62b 1466 /* Flush outstanding commands. */
4d78c973 1467 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1468 QLA_SUCCESS) {
1469 ql_log(ql_log_warn, vha, 0x8014,
1470 "Wait for pending commands failed.\n");
9a41a62b 1471 ret = FAILED;
7c3df132 1472 }
1da177e4 1473
f4f051eb 1474eh_bus_reset_done:
7c3df132 1475 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1476 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1477 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1478
f4f051eb 1479 return ret;
1da177e4
LT		 1480}
1481
1482/**************************************************************************
1483* qla2xxx_eh_host_reset
1484*
1485* Description:
1486* The reset function will reset the Adapter.
1487*
1488* Input:
1489* cmd = Linux SCSI command packet of the command that cause the
1490* adapter reset.
1491*
1492* Returns:
1493* Either SUCCESS or FAILED.
1494*
1495* Note:
1496**************************************************************************/
e5f82ab8 1497static int
1da177e4
LT		 1498qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1499{
e315cd28 1500 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1501 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1502 int ret = FAILED;
9cb78c16
HR		 1503 unsigned int id;
1504 uint64_t lun;
e315cd28 1505 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1506
a465537a
SC		 1507 if (qla2x00_isp_reg_stat(ha)) {
1508 ql_log(ql_log_info, vha, 0x8041,
1509 "PCI/Register disconnect, exiting.\n");
1510 schedule_work(&ha->board_disable);
1511 return SUCCESS;
1512 }
1513
f4f051eb
AV		 1514 id = cmd->device->id;
1515 lun = cmd->device->lun;
f4f051eb 1516
7c3df132 1517 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1518 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1519
63ee7072
CD		 1520 /*
1521 * No point in issuing another reset if one is active. Also do not
1522 * attempt a reset if we are updating flash.
1523 */
1524 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1525 goto eh_host_reset_lock;
1da177e4 1526
e315cd28
AC		 1527 if (vha != base_vha) {
1528 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1529 goto eh_host_reset_lock;
e315cd28 1530 } else {
7ec0effd 1531 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1532 if (!qla82xx_fcoe_ctx_reset(vha)) {
1533 /* Ctx reset success */
1534 ret = SUCCESS;
1535 goto eh_host_reset_lock;
1536 }
1537 /* fall thru if ctx reset failed */
1538 }
68ca949c
AC		 1539 if (ha->wq)
1540 flush_workqueue(ha->wq);
1541
e315cd28 1542 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1543 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1544 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1545 /* failed. schedule dpc to try */
1546 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1547
7c3df132
SK		 1548 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1549 ql_log(ql_log_warn, vha, 0x802a,
1550 "wait for hba online failed.\n");
e315cd28 1551 goto eh_host_reset_lock;
7c3df132 1552 }
e315cd28
AC		 1553 }
1554 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1555 }
1da177e4 1556
e315cd28 1557 /* Waiting for command to be returned to OS.*/
4d78c973 1558 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1559 QLA_SUCCESS)
f4f051eb 1560 ret = SUCCESS;
1da177e4 1561
f4f051eb 1562eh_host_reset_lock:
cfb0919c 1563 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1564 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1565 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1566
f4f051eb
AV		 1567 return ret;
1568}
1da177e4
LT		 1569
1570/*
1571* qla2x00_loop_reset
1572* Issue loop reset.
1573*
1574* Input:
1575* ha = adapter block pointer.
1576*
1577* Returns:
1578* 0 = success
1579*/
a4722cf2 1580int
e315cd28 1581qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1582{
0c8c39af 1583 int ret;
bdf79621 1584 struct fc_port *fcport;
e315cd28 1585 struct qla_hw_data *ha = vha->hw;
1da177e4 1586
5854771e
AB		 1587 if (IS_QLAFX00(ha)) {
1588 return qlafx00_loop_reset(vha);
1589 }
1590
f4c496c1 1591 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1592 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1593 if (fcport->port_type != FCT_TARGET)
1594 continue;
1595
1596 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1597 if (ret != QLA_SUCCESS) {
7c3df132 1598 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1599 "Bus Reset failed: Reset=%d "
7c3df132 1600 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1601 }
1602 }
1603 }
1604
8ae6d9c7 1605
6246b8a1 1606 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1607 atomic_set(&vha->loop_state, LOOP_DOWN);
1608 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1609 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1610 ret = qla2x00_full_login_lip(vha);
0c8c39af 1611 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1612 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1613 "full_login_lip=%d.\n", ret);
749af3d5 1614 }
0c8c39af
AV		 1615 }
1616
0d6e61bc 1617 if (ha->flags.enable_lip_reset) {
e315cd28 1618 ret = qla2x00_lip_reset(vha);
ad537689 1619 if (ret != QLA_SUCCESS)
7c3df132
SK		 1620 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1621 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1622 }
1623
1da177e4 1624 /* Issue marker command only when we are going to start the I/O */
e315cd28 1625 vha->marker_needed = 1;
1da177e4 1626
0c8c39af 1627 return QLA_SUCCESS;
1da177e4
LT		 1628}
1629
df4bf0bb 1630void
e315cd28 1631qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1632{
73208dfd 1633 int que, cnt;
df4bf0bb
AV		 1634 unsigned long flags;
1635 srb_t *sp;
e315cd28 1636 struct qla_hw_data *ha = vha->hw;
73208dfd 1637 struct req_que *req;
df4bf0bb 1638
c0cb4496
AE		 1639 qlt_host_reset_handler(ha);
1640
df4bf0bb 1641 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1642 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1643 req = ha->req_q_map[que];
73208dfd
AC		 1644 if (!req)
1645 continue;
8d93f550
CD		 1646 if (!req->outstanding_cmds)
1647 continue;
1648 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1649 sp = req->outstanding_cmds[cnt];
e612d465 1650 if (sp) {
c733ab35
MFO		 1651 /* Don't abort commands in adapter during EEH
1652 * recovery as it's not accessible/responding.
1535aa75 1653 */
2780f3c8 1654 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy) {
c733ab35
MFO		 1655 /* Get a reference to the sp and drop the lock.
1656 * The reference ensures this sp->done() call
1657 * - and not the call in qla2xxx_eh_abort() -
1658 * ends the SCSI command (with result 'res').
1659 */
1660 sp_get(sp);
1661 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1662 qla2xxx_eh_abort(GET_CMD_SP(sp));
1663 spin_lock_irqsave(&ha->hardware_lock, flags);
1664 }
73208dfd 1665 req->outstanding_cmds[cnt] = NULL;
25ff6af1 1666 sp->done(sp, res);
73208dfd 1667 }
df4bf0bb
AV		 1668 }
1669 }
1670 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1671}
1672
f4f051eb
AV		 1673static int
1674qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1675{
bdf79621 1676 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1677
19a7b4ae 1678 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1679 return -ENXIO;
bdf79621 1680
19a7b4ae 1681 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1682
f4f051eb
AV		 1683 return 0;
1684}
1da177e4 1685
f4f051eb
AV		 1686static int
1687qla2xxx_slave_configure(struct scsi_device *sdev)
1688{
e315cd28 1689 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1690 struct req_que *req = vha->req;
8482e118 1691
9e522cd8
AE		 1692 if (IS_T10_PI_CAPABLE(vha->hw))
1693 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1694
db5ed4df 1695 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1696 return 0;
1697}
1da177e4 1698
f4f051eb
AV		 1699static void
1700qla2xxx_slave_destroy(struct scsi_device *sdev)
1701{
1702 sdev->hostdata = NULL;
1da177e4
LT		 1703}
1704
1705/**
1706 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1707 * @ha: HA context
1708 *
1709 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1710 * supported addressing method.
1711 */
1712static void
53303c42 1713qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1714{
7524f9b9 1715 /* Assume a 32bit DMA mask. */
1da177e4 1716 ha->flags.enable_64bit_addressing = 0;
1da177e4 1717
6a35528a 1718 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1719 /* Any upper-dword bits set? */
1720 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1721 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1722 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1723 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1724 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1725 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1726 return;
1da177e4 1727 }
1da177e4 1728 }
7524f9b9 1729
284901a9
YH		 1730 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1731 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1732}
1733
fd34f556 1734static void
e315cd28 1735qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1736{
1737 unsigned long flags = 0;
1738 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1739
1740 spin_lock_irqsave(&ha->hardware_lock, flags);
1741 ha->interrupts_on = 1;
1742 /* enable risc and host interrupts */
1743 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1744 RD_REG_WORD(&reg->ictrl);
1745 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1746
1747}
1748
1749static void
e315cd28 1750qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1751{
1752 unsigned long flags = 0;
1753 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1754
1755 spin_lock_irqsave(&ha->hardware_lock, flags);
1756 ha->interrupts_on = 0;
1757 /* disable risc and host interrupts */
1758 WRT_REG_WORD(&reg->ictrl, 0);
1759 RD_REG_WORD(&reg->ictrl);
1760 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1761}
1762
1763static void
e315cd28 1764qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1765{
1766 unsigned long flags = 0;
1767 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1768
1769 spin_lock_irqsave(&ha->hardware_lock, flags);
1770 ha->interrupts_on = 1;
1771 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1772 RD_REG_DWORD(&reg->ictrl);
1773 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1774}
1775
1776static void
e315cd28 1777qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1778{
1779 unsigned long flags = 0;
1780 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1781
124f85e6
AV		 1782 if (IS_NOPOLLING_TYPE(ha))
1783 return;
fd34f556
AV		 1784 spin_lock_irqsave(&ha->hardware_lock, flags);
1785 ha->interrupts_on = 0;
1786 WRT_REG_DWORD(&reg->ictrl, 0);
1787 RD_REG_DWORD(&reg->ictrl);
1788 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1789}
1790
706f457d
GM		 1791static int
1792qla2x00_iospace_config(struct qla_hw_data *ha)
1793{
1794 resource_size_t pio;
1795 uint16_t msix;
706f457d 1796
706f457d
GM		 1797 if (pci_request_selected_regions(ha->pdev, ha->bars,
1798 QLA2XXX_DRIVER_NAME)) {
1799 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1800 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1801 pci_name(ha->pdev));
1802 goto iospace_error_exit;
1803 }
1804 if (!(ha->bars & 1))
1805 goto skip_pio;
1806
1807 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1808 pio = pci_resource_start(ha->pdev, 0);
1809 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1810 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1811 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1812 "Invalid pci I/O region size (%s).\n",
1813 pci_name(ha->pdev));
1814 pio = 0;
1815 }
1816 } else {
1817 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1818 "Region #0 no a PIO resource (%s).\n",
1819 pci_name(ha->pdev));
1820 pio = 0;
1821 }
1822 ha->pio_address = pio;
1823 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1824 "PIO address=%llu.\n",
1825 (unsigned long long)ha->pio_address);
1826
1827skip_pio:
1828 /* Use MMIO operations for all accesses. */
1829 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1830 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1831 "Region #1 not an MMIO resource (%s), aborting.\n",
1832 pci_name(ha->pdev));
1833 goto iospace_error_exit;
1834 }
1835 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1836 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1837 "Invalid PCI mem region size (%s), aborting.\n",
1838 pci_name(ha->pdev));
1839 goto iospace_error_exit;
1840 }
1841
1842 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1843 if (!ha->iobase) {
1844 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1845 "Cannot remap MMIO (%s), aborting.\n",
1846 pci_name(ha->pdev));
1847 goto iospace_error_exit;
1848 }
1849
1850 /* Determine queue resources */
1851 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1852 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1853 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1854 goto mqiobase_exit;
1855
1856 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1857 pci_resource_len(ha->pdev, 3));
1858 if (ha->mqiobase) {
1859 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1860 "MQIO Base=%p.\n", ha->mqiobase);
1861 /* Read MSIX vector size of the board */
1862 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1863 ha->msix_count = msix + 1;
706f457d 1864 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1865 /* MB interrupt uses 1 vector */
1866 ha->max_req_queues = ha->msix_count - 1;
1867 ha->max_rsp_queues = ha->max_req_queues;
1868 /* Queue pairs is the max value minus the base queue pair */
1869 ha->max_qpairs = ha->max_rsp_queues - 1;
1870 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1871 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1872
706f457d 1873 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1874 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1875 } else
1876 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1877 "BAR 3 not enabled.\n");
1878
1879mqiobase_exit:
706f457d 1880 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1881 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1882 return (0);
1883
1884iospace_error_exit:
1885 return (-ENOMEM);
1886}
1887
1888
6246b8a1
GM		 1889static int
1890qla83xx_iospace_config(struct qla_hw_data *ha)
1891{
1892 uint16_t msix;
6246b8a1
GM		 1893
1894 if (pci_request_selected_regions(ha->pdev, ha->bars,
1895 QLA2XXX_DRIVER_NAME)) {
1896 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1897 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1898 pci_name(ha->pdev));
1899
1900 goto iospace_error_exit;
1901 }
1902
1903 /* Use MMIO operations for all accesses. */
1904 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1905 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1906 "Invalid pci I/O region size (%s).\n",
1907 pci_name(ha->pdev));
1908 goto iospace_error_exit;
1909 }
1910 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1911 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1912 "Invalid PCI mem region size (%s), aborting\n",
1913 pci_name(ha->pdev));
1914 goto iospace_error_exit;
1915 }
1916
1917 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1918 if (!ha->iobase) {
1919 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1920 "Cannot remap MMIO (%s), aborting.\n",
1921 pci_name(ha->pdev));
1922 goto iospace_error_exit;
1923 }
1924
1925 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1926 /* 83XX 26XX always use MQ type access for queues
1927 * - mbar 2, a.k.a region 4 */
1928 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1929 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 1930 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1931 pci_resource_len(ha->pdev, 4));
1932
1933 if (!ha->mqiobase) {
1934 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1935 "BAR2/region4 not enabled\n");
1936 goto mqiobase_exit;
1937 }
1938
1939 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1940 pci_resource_len(ha->pdev, 2));
1941 if (ha->msixbase) {
1942 /* Read MSIX vector size of the board */
1943 pci_read_config_word(ha->pdev,
1944 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1945 ha->msix_count = msix + 1;
093df737
QT		 1946 /*
1947 * By default, driver uses at least two msix vectors
1948 * (default & rspq)
1949 */
d7459527
MH		 1950 if (ql2xmqsupport) {
1951 /* MB interrupt uses 1 vector */
1952 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 1953
1954 /* ATIOQ needs 1 vector. That's 1 less QPair */
1955 if (QLA_TGT_MODE_ENABLED())
1956 ha->max_req_queues--;
1957
d0d2c68b
MH		 1958 ha->max_rsp_queues = ha->max_req_queues;
1959
d7459527
MH		 1960 /* Queue pairs is the max value minus
1961 * the base queue pair */
1962 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1963 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1964 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1965 }
1966 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1967 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1968 } else
1969 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1970 "BAR 1 not enabled.\n");
1971
1972mqiobase_exit:
6246b8a1 1973 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 1974 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 1975 return 0;
1976
1977iospace_error_exit:
1978 return -ENOMEM;
1979}
1980
fd34f556
AV		 1981static struct isp_operations qla2100_isp_ops = {
1982 .pci_config = qla2100_pci_config,
1983 .reset_chip = qla2x00_reset_chip,
1984 .chip_diag = qla2x00_chip_diag,
1985 .config_rings = qla2x00_config_rings,
1986 .reset_adapter = qla2x00_reset_adapter,
1987 .nvram_config = qla2x00_nvram_config,
1988 .update_fw_options = qla2x00_update_fw_options,
1989 .load_risc = qla2x00_load_risc,
1990 .pci_info_str = qla2x00_pci_info_str,
1991 .fw_version_str = qla2x00_fw_version_str,
1992 .intr_handler = qla2100_intr_handler,
1993 .enable_intrs = qla2x00_enable_intrs,
1994 .disable_intrs = qla2x00_disable_intrs,
1995 .abort_command = qla2x00_abort_command,
523ec773
AV		 1996 .target_reset = qla2x00_abort_target,
1997 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1998 .fabric_login = qla2x00_login_fabric,
1999 .fabric_logout = qla2x00_fabric_logout,
2000 .calc_req_entries = qla2x00_calc_iocbs_32,
2001 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2002 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2003 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2004 .read_nvram = qla2x00_read_nvram_data,
2005 .write_nvram = qla2x00_write_nvram_data,
2006 .fw_dump = qla2100_fw_dump,
2007 .beacon_on = NULL,
2008 .beacon_off = NULL,
2009 .beacon_blink = NULL,
2010 .read_optrom = qla2x00_read_optrom_data,
2011 .write_optrom = qla2x00_write_optrom_data,
2012 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2013 .start_scsi = qla2x00_start_scsi,
d7459527 2014 .start_scsi_mq = NULL,
a9083016 2015 .abort_isp = qla2x00_abort_isp,
706f457d 2016 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2017 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2018};
2019
2020static struct isp_operations qla2300_isp_ops = {
2021 .pci_config = qla2300_pci_config,
2022 .reset_chip = qla2x00_reset_chip,
2023 .chip_diag = qla2x00_chip_diag,
2024 .config_rings = qla2x00_config_rings,
2025 .reset_adapter = qla2x00_reset_adapter,
2026 .nvram_config = qla2x00_nvram_config,
2027 .update_fw_options = qla2x00_update_fw_options,
2028 .load_risc = qla2x00_load_risc,
2029 .pci_info_str = qla2x00_pci_info_str,
2030 .fw_version_str = qla2x00_fw_version_str,
2031 .intr_handler = qla2300_intr_handler,
2032 .enable_intrs = qla2x00_enable_intrs,
2033 .disable_intrs = qla2x00_disable_intrs,
2034 .abort_command = qla2x00_abort_command,
523ec773
AV		 2035 .target_reset = qla2x00_abort_target,
2036 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2037 .fabric_login = qla2x00_login_fabric,
2038 .fabric_logout = qla2x00_fabric_logout,
2039 .calc_req_entries = qla2x00_calc_iocbs_32,
2040 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2041 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2042 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2043 .read_nvram = qla2x00_read_nvram_data,
2044 .write_nvram = qla2x00_write_nvram_data,
2045 .fw_dump = qla2300_fw_dump,
2046 .beacon_on = qla2x00_beacon_on,
2047 .beacon_off = qla2x00_beacon_off,
2048 .beacon_blink = qla2x00_beacon_blink,
2049 .read_optrom = qla2x00_read_optrom_data,
2050 .write_optrom = qla2x00_write_optrom_data,
2051 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2052 .start_scsi = qla2x00_start_scsi,
d7459527 2053 .start_scsi_mq = NULL,
a9083016 2054 .abort_isp = qla2x00_abort_isp,
7ec0effd 2055 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2056 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2057};
2058
2059static struct isp_operations qla24xx_isp_ops = {
2060 .pci_config = qla24xx_pci_config,
2061 .reset_chip = qla24xx_reset_chip,
2062 .chip_diag = qla24xx_chip_diag,
2063 .config_rings = qla24xx_config_rings,
2064 .reset_adapter = qla24xx_reset_adapter,
2065 .nvram_config = qla24xx_nvram_config,
2066 .update_fw_options = qla24xx_update_fw_options,
2067 .load_risc = qla24xx_load_risc,
2068 .pci_info_str = qla24xx_pci_info_str,
2069 .fw_version_str = qla24xx_fw_version_str,
2070 .intr_handler = qla24xx_intr_handler,
2071 .enable_intrs = qla24xx_enable_intrs,
2072 .disable_intrs = qla24xx_disable_intrs,
2073 .abort_command = qla24xx_abort_command,
523ec773
AV		 2074 .target_reset = qla24xx_abort_target,
2075 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2076 .fabric_login = qla24xx_login_fabric,
2077 .fabric_logout = qla24xx_fabric_logout,
2078 .calc_req_entries = NULL,
2079 .build_iocbs = NULL,
2080 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2081 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2082 .read_nvram = qla24xx_read_nvram_data,
2083 .write_nvram = qla24xx_write_nvram_data,
2084 .fw_dump = qla24xx_fw_dump,
2085 .beacon_on = qla24xx_beacon_on,
2086 .beacon_off = qla24xx_beacon_off,
2087 .beacon_blink = qla24xx_beacon_blink,
2088 .read_optrom = qla24xx_read_optrom_data,
2089 .write_optrom = qla24xx_write_optrom_data,
2090 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2091 .start_scsi = qla24xx_start_scsi,
d7459527 2092 .start_scsi_mq = NULL,
a9083016 2093 .abort_isp = qla2x00_abort_isp,
7ec0effd 2094 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2095 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2096};
2097
c3a2f0df
AV		 2098static struct isp_operations qla25xx_isp_ops = {
2099 .pci_config = qla25xx_pci_config,
2100 .reset_chip = qla24xx_reset_chip,
2101 .chip_diag = qla24xx_chip_diag,
2102 .config_rings = qla24xx_config_rings,
2103 .reset_adapter = qla24xx_reset_adapter,
2104 .nvram_config = qla24xx_nvram_config,
2105 .update_fw_options = qla24xx_update_fw_options,
2106 .load_risc = qla24xx_load_risc,
2107 .pci_info_str = qla24xx_pci_info_str,
2108 .fw_version_str = qla24xx_fw_version_str,
2109 .intr_handler = qla24xx_intr_handler,
2110 .enable_intrs = qla24xx_enable_intrs,
2111 .disable_intrs = qla24xx_disable_intrs,
2112 .abort_command = qla24xx_abort_command,
523ec773
AV		 2113 .target_reset = qla24xx_abort_target,
2114 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2115 .fabric_login = qla24xx_login_fabric,
2116 .fabric_logout = qla24xx_fabric_logout,
2117 .calc_req_entries = NULL,
2118 .build_iocbs = NULL,
2119 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2120 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2121 .read_nvram = qla25xx_read_nvram_data,
2122 .write_nvram = qla25xx_write_nvram_data,
2123 .fw_dump = qla25xx_fw_dump,
2124 .beacon_on = qla24xx_beacon_on,
2125 .beacon_off = qla24xx_beacon_off,
2126 .beacon_blink = qla24xx_beacon_blink,
338c9161 2127 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2128 .write_optrom = qla24xx_write_optrom_data,
2129 .get_flash_version = qla24xx_get_flash_version,
bad75002 2130 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2131 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2132 .abort_isp = qla2x00_abort_isp,
7ec0effd 2133 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2134 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2135};
2136
3a03eb79
AV		 2137static struct isp_operations qla81xx_isp_ops = {
2138 .pci_config = qla25xx_pci_config,
2139 .reset_chip = qla24xx_reset_chip,
2140 .chip_diag = qla24xx_chip_diag,
2141 .config_rings = qla24xx_config_rings,
2142 .reset_adapter = qla24xx_reset_adapter,
2143 .nvram_config = qla81xx_nvram_config,
2144 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2145 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2146 .pci_info_str = qla24xx_pci_info_str,
2147 .fw_version_str = qla24xx_fw_version_str,
2148 .intr_handler = qla24xx_intr_handler,
2149 .enable_intrs = qla24xx_enable_intrs,
2150 .disable_intrs = qla24xx_disable_intrs,
2151 .abort_command = qla24xx_abort_command,
2152 .target_reset = qla24xx_abort_target,
2153 .lun_reset = qla24xx_lun_reset,
2154 .fabric_login = qla24xx_login_fabric,
2155 .fabric_logout = qla24xx_fabric_logout,
2156 .calc_req_entries = NULL,
2157 .build_iocbs = NULL,
2158 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2159 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2160 .read_nvram = NULL,
2161 .write_nvram = NULL,
3a03eb79
AV		 2162 .fw_dump = qla81xx_fw_dump,
2163 .beacon_on = qla24xx_beacon_on,
2164 .beacon_off = qla24xx_beacon_off,
6246b8a1 2165 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2166 .read_optrom = qla25xx_read_optrom_data,
2167 .write_optrom = qla24xx_write_optrom_data,
2168 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2169 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2170 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2171 .abort_isp = qla2x00_abort_isp,
7ec0effd 2172 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2173 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2174};
2175
2176static struct isp_operations qla82xx_isp_ops = {
2177 .pci_config = qla82xx_pci_config,
2178 .reset_chip = qla82xx_reset_chip,
2179 .chip_diag = qla24xx_chip_diag,
2180 .config_rings = qla82xx_config_rings,
2181 .reset_adapter = qla24xx_reset_adapter,
2182 .nvram_config = qla81xx_nvram_config,
2183 .update_fw_options = qla24xx_update_fw_options,
2184 .load_risc = qla82xx_load_risc,
9d55ca66 2185 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2186 .fw_version_str = qla24xx_fw_version_str,
2187 .intr_handler = qla82xx_intr_handler,
2188 .enable_intrs = qla82xx_enable_intrs,
2189 .disable_intrs = qla82xx_disable_intrs,
2190 .abort_command = qla24xx_abort_command,
2191 .target_reset = qla24xx_abort_target,
2192 .lun_reset = qla24xx_lun_reset,
2193 .fabric_login = qla24xx_login_fabric,
2194 .fabric_logout = qla24xx_fabric_logout,
2195 .calc_req_entries = NULL,
2196 .build_iocbs = NULL,
2197 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2198 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2199 .read_nvram = qla24xx_read_nvram_data,
2200 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2201 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2202 .beacon_on = qla82xx_beacon_on,
2203 .beacon_off = qla82xx_beacon_off,
2204 .beacon_blink = NULL,
a9083016
GM		 2205 .read_optrom = qla82xx_read_optrom_data,
2206 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2207 .get_flash_version = qla82xx_get_flash_version,
a9083016 2208 .start_scsi = qla82xx_start_scsi,
d7459527 2209 .start_scsi_mq = NULL,
a9083016 2210 .abort_isp = qla82xx_abort_isp,
706f457d 2211 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2212 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2213};
2214
7ec0effd
AD		 2215static struct isp_operations qla8044_isp_ops = {
2216 .pci_config = qla82xx_pci_config,
2217 .reset_chip = qla82xx_reset_chip,
2218 .chip_diag = qla24xx_chip_diag,
2219 .config_rings = qla82xx_config_rings,
2220 .reset_adapter = qla24xx_reset_adapter,
2221 .nvram_config = qla81xx_nvram_config,
2222 .update_fw_options = qla24xx_update_fw_options,
2223 .load_risc = qla82xx_load_risc,
2224 .pci_info_str = qla24xx_pci_info_str,
2225 .fw_version_str = qla24xx_fw_version_str,
2226 .intr_handler = qla8044_intr_handler,
2227 .enable_intrs = qla82xx_enable_intrs,
2228 .disable_intrs = qla82xx_disable_intrs,
2229 .abort_command = qla24xx_abort_command,
2230 .target_reset = qla24xx_abort_target,
2231 .lun_reset = qla24xx_lun_reset,
2232 .fabric_login = qla24xx_login_fabric,
2233 .fabric_logout = qla24xx_fabric_logout,
2234 .calc_req_entries = NULL,
2235 .build_iocbs = NULL,
2236 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2237 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2238 .read_nvram = NULL,
2239 .write_nvram = NULL,
a1b23c5a 2240 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2241 .beacon_on = qla82xx_beacon_on,
2242 .beacon_off = qla82xx_beacon_off,
2243 .beacon_blink = NULL,
888e639d 2244 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2245 .write_optrom = qla8044_write_optrom_data,
2246 .get_flash_version = qla82xx_get_flash_version,
2247 .start_scsi = qla82xx_start_scsi,
d7459527 2248 .start_scsi_mq = NULL,
7ec0effd
AD		 2249 .abort_isp = qla8044_abort_isp,
2250 .iospace_config = qla82xx_iospace_config,
2251 .initialize_adapter = qla2x00_initialize_adapter,
2252};
2253
6246b8a1
GM		 2254static struct isp_operations qla83xx_isp_ops = {
2255 .pci_config = qla25xx_pci_config,
2256 .reset_chip = qla24xx_reset_chip,
2257 .chip_diag = qla24xx_chip_diag,
2258 .config_rings = qla24xx_config_rings,
2259 .reset_adapter = qla24xx_reset_adapter,
2260 .nvram_config = qla81xx_nvram_config,
2261 .update_fw_options = qla81xx_update_fw_options,
2262 .load_risc = qla81xx_load_risc,
2263 .pci_info_str = qla24xx_pci_info_str,
2264 .fw_version_str = qla24xx_fw_version_str,
2265 .intr_handler = qla24xx_intr_handler,
2266 .enable_intrs = qla24xx_enable_intrs,
2267 .disable_intrs = qla24xx_disable_intrs,
2268 .abort_command = qla24xx_abort_command,
2269 .target_reset = qla24xx_abort_target,
2270 .lun_reset = qla24xx_lun_reset,
2271 .fabric_login = qla24xx_login_fabric,
2272 .fabric_logout = qla24xx_fabric_logout,
2273 .calc_req_entries = NULL,
2274 .build_iocbs = NULL,
2275 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2276 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2277 .read_nvram = NULL,
2278 .write_nvram = NULL,
2279 .fw_dump = qla83xx_fw_dump,
2280 .beacon_on = qla24xx_beacon_on,
2281 .beacon_off = qla24xx_beacon_off,
2282 .beacon_blink = qla83xx_beacon_blink,
2283 .read_optrom = qla25xx_read_optrom_data,
2284 .write_optrom = qla24xx_write_optrom_data,
2285 .get_flash_version = qla24xx_get_flash_version,
2286 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2287 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2288 .abort_isp = qla2x00_abort_isp,
2289 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2290 .initialize_adapter = qla2x00_initialize_adapter,
2291};
2292
2293static struct isp_operations qlafx00_isp_ops = {
2294 .pci_config = qlafx00_pci_config,
2295 .reset_chip = qlafx00_soft_reset,
2296 .chip_diag = qlafx00_chip_diag,
2297 .config_rings = qlafx00_config_rings,
2298 .reset_adapter = qlafx00_soft_reset,
2299 .nvram_config = NULL,
2300 .update_fw_options = NULL,
2301 .load_risc = NULL,
2302 .pci_info_str = qlafx00_pci_info_str,
2303 .fw_version_str = qlafx00_fw_version_str,
2304 .intr_handler = qlafx00_intr_handler,
2305 .enable_intrs = qlafx00_enable_intrs,
2306 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2307 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2308 .target_reset = qlafx00_abort_target,
2309 .lun_reset = qlafx00_lun_reset,
2310 .fabric_login = NULL,
2311 .fabric_logout = NULL,
2312 .calc_req_entries = NULL,
2313 .build_iocbs = NULL,
2314 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2315 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2316 .read_nvram = qla24xx_read_nvram_data,
2317 .write_nvram = qla24xx_write_nvram_data,
2318 .fw_dump = NULL,
2319 .beacon_on = qla24xx_beacon_on,
2320 .beacon_off = qla24xx_beacon_off,
2321 .beacon_blink = NULL,
2322 .read_optrom = qla24xx_read_optrom_data,
2323 .write_optrom = qla24xx_write_optrom_data,
2324 .get_flash_version = qla24xx_get_flash_version,
2325 .start_scsi = qlafx00_start_scsi,
d7459527 2326 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2327 .abort_isp = qlafx00_abort_isp,
2328 .iospace_config = qlafx00_iospace_config,
2329 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2330};
2331
f73cb695
CD		 2332static struct isp_operations qla27xx_isp_ops = {
2333 .pci_config = qla25xx_pci_config,
2334 .reset_chip = qla24xx_reset_chip,
2335 .chip_diag = qla24xx_chip_diag,
2336 .config_rings = qla24xx_config_rings,
2337 .reset_adapter = qla24xx_reset_adapter,
2338 .nvram_config = qla81xx_nvram_config,
2339 .update_fw_options = qla81xx_update_fw_options,
2340 .load_risc = qla81xx_load_risc,
2341 .pci_info_str = qla24xx_pci_info_str,
2342 .fw_version_str = qla24xx_fw_version_str,
2343 .intr_handler = qla24xx_intr_handler,
2344 .enable_intrs = qla24xx_enable_intrs,
2345 .disable_intrs = qla24xx_disable_intrs,
2346 .abort_command = qla24xx_abort_command,
2347 .target_reset = qla24xx_abort_target,
2348 .lun_reset = qla24xx_lun_reset,
2349 .fabric_login = qla24xx_login_fabric,
2350 .fabric_logout = qla24xx_fabric_logout,
2351 .calc_req_entries = NULL,
2352 .build_iocbs = NULL,
2353 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2354 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2355 .read_nvram = NULL,
2356 .write_nvram = NULL,
2357 .fw_dump = qla27xx_fwdump,
2358 .beacon_on = qla24xx_beacon_on,
2359 .beacon_off = qla24xx_beacon_off,
2360 .beacon_blink = qla83xx_beacon_blink,
2361 .read_optrom = qla25xx_read_optrom_data,
2362 .write_optrom = qla24xx_write_optrom_data,
2363 .get_flash_version = qla24xx_get_flash_version,
2364 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2365 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2366 .abort_isp = qla2x00_abort_isp,
2367 .iospace_config = qla83xx_iospace_config,
2368 .initialize_adapter = qla2x00_initialize_adapter,
2369};
2370
ea5b6382 2371static inline void
e315cd28 2372qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2373{
2374 ha->device_type = DT_EXTENDED_IDS;
2375 switch (ha->pdev->device) {
2376 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2377 ha->isp_type |= DT_ISP2100;
ea5b6382 2378 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2379 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2380 break;
2381 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2382 ha->isp_type |= DT_ISP2200;
ea5b6382 2383 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2384 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2385 break;
2386 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2387 ha->isp_type |= DT_ISP2300;
4a59f71d 2388 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2389 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2390 break;
2391 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2392 ha->isp_type |= DT_ISP2312;
4a59f71d 2393 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2394 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2395 break;
2396 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2397 ha->isp_type |= DT_ISP2322;
4a59f71d 2398 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2399 if (ha->pdev->subsystem_vendor == 0x1028 &&
2400 ha->pdev->subsystem_device == 0x0170)
2401 ha->device_type |= DT_OEM_001;
441d1072 2402 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2403 break;
2404 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2405 ha->isp_type |= DT_ISP6312;
441d1072 2406 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2407 break;
2408 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2409 ha->isp_type |= DT_ISP6322;
441d1072 2410 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2411 break;
2412 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2413 ha->isp_type |= DT_ISP2422;
4a59f71d 2414 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2415 ha->device_type |= DT_FWI2;
c76f2c01 2416 ha->device_type |= DT_IIDMA;
441d1072 2417 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2418 break;
2419 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2420 ha->isp_type |= DT_ISP2432;
4a59f71d 2421 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2422 ha->device_type |= DT_FWI2;
c76f2c01 2423 ha->device_type |= DT_IIDMA;
441d1072 2424 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2425 break;
4d4df193 2426 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2427 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2428 ha->device_type |= DT_ZIO_SUPPORTED;
2429 ha->device_type |= DT_FWI2;
2430 ha->device_type |= DT_IIDMA;
2431 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2432 break;
044cc6c8 2433 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2434 ha->isp_type |= DT_ISP5422;
e428924c 2435 ha->device_type |= DT_FWI2;
441d1072 2436 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2437 break;
044cc6c8 2438 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2439 ha->isp_type |= DT_ISP5432;
e428924c 2440 ha->device_type |= DT_FWI2;
441d1072 2441 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2442 break;
c3a2f0df 2443 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2444 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2445 ha->device_type |= DT_ZIO_SUPPORTED;
2446 ha->device_type |= DT_FWI2;
2447 ha->device_type |= DT_IIDMA;
441d1072 2448 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2449 break;
3a03eb79 2450 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2451 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2452 ha->device_type |= DT_ZIO_SUPPORTED;
2453 ha->device_type |= DT_FWI2;
2454 ha->device_type |= DT_IIDMA;
2455 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2456 break;
a9083016 2457 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2458 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2459 ha->device_type |= DT_ZIO_SUPPORTED;
2460 ha->device_type |= DT_FWI2;
2461 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2462 /* Initialize 82XX ISP flags */
2463 qla82xx_init_flags(ha);
2464 break;
7ec0effd 2465 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2466 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2467 ha->device_type |= DT_ZIO_SUPPORTED;
2468 ha->device_type |= DT_FWI2;
2469 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2470 /* Initialize 82XX ISP flags */
2471 qla82xx_init_flags(ha);
2472 break;
6246b8a1 2473 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2474 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2475 ha->device_type |= DT_ZIO_SUPPORTED;
2476 ha->device_type |= DT_FWI2;
2477 ha->device_type |= DT_IIDMA;
2478 ha->device_type |= DT_T10_PI;
2479 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2480 break;
2481 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2482 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2483 ha->device_type |= DT_ZIO_SUPPORTED;
2484 ha->device_type |= DT_FWI2;
2485 ha->device_type |= DT_IIDMA;
2486 ha->device_type |= DT_T10_PI;
2487 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2488 break;
8ae6d9c7 2489 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2490 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2491 break;
f73cb695 2492 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2493 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2494 ha->device_type |= DT_ZIO_SUPPORTED;
2495 ha->device_type |= DT_FWI2;
2496 ha->device_type |= DT_IIDMA;
8ce3f570 2497 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2498 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2499 break;
2c5bbbb2 2500 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2501 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2502 ha->device_type |= DT_ZIO_SUPPORTED;
2503 ha->device_type |= DT_FWI2;
2504 ha->device_type |= DT_IIDMA;
8ce3f570 2505 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2506 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2507 break;
2b48992f 2508 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2509 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2510 ha->device_type |= DT_ZIO_SUPPORTED;
2511 ha->device_type |= DT_FWI2;
2512 ha->device_type |= DT_IIDMA;
8ce3f570 2513 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2514 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2515 break;
ea5b6382 2516 }
e5b68a61 2517
a9083016 2518 if (IS_QLA82XX(ha))
43a9c38b 2519 ha->port_no = ha->portnum & 1;
f73cb695 2520 else {
a9083016
GM		 2521 /* Get adapter physical port no from interrupt pin register. */
2522 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2523 if (IS_QLA27XX(ha))
2524 ha->port_no--;
2525 else
2526 ha->port_no = !(ha->port_no & 1);
2527 }
a9083016 2528
7c3df132 2529 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2530 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2531 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2532}
2533
1e99e33a
AV		 2534static void
2535qla2xxx_scan_start(struct Scsi_Host *shost)
2536{
e315cd28 2537 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2538
cbc8eb67
AV		 2539 if (vha->hw->flags.running_gold_fw)
2540 return;
2541
e315cd28
AC		 2542 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2543 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2544 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2545 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2546}
2547
2548static int
2549qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2550{
e315cd28 2551 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2552
a5dd506e
BK		 2553 if (test_bit(UNLOADING, &vha->dpc_flags))
2554 return 1;
e315cd28 2555 if (!vha->host)
1e99e33a 2556 return 1;
e315cd28 2557 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2558 return 1;
2559
e315cd28 2560 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2561}
2562
ec7193e2
QT		 2563static void qla2x00_iocb_work_fn(struct work_struct *work)
2564{
2565 struct scsi_qla_host *vha = container_of(work,
2566 struct scsi_qla_host, iocb_work);
2567 int cnt = 0;
2568
2569 while (!list_empty(&vha->work_list)) {
2570 qla2x00_do_work(vha);
2571 cnt++;
2572 if (cnt > 10)
2573 break;
2574 }
2575}
2576
1da177e4
LT		 2577/*
2578 * PCI driver interface
2579 */
6f039790 2580static int
7ee61397 2581qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2582{
a1541d5a 2583 int ret = -ENODEV;
1da177e4 2584 struct Scsi_Host *host;
e315cd28
AC		 2585 scsi_qla_host_t *base_vha = NULL;
2586 struct qla_hw_data *ha;
29856e28 2587 char pci_info[30];
7d613ac6 2588 char fw_str[30], wq_name[30];
5433383e 2589 struct scsi_host_template *sht;
642ef983 2590 int bars, mem_only = 0;
e315cd28 2591 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2592 struct req_que *req = NULL;
2593 struct rsp_que *rsp = NULL;
5601236b 2594 int i;
d7459527 2595
285d0321 2596 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2597 sht = &qla2xxx_driver_template;
5433383e 2598 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2599 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2600 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2601 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2602 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2603 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2604 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2605 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2606 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2607 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2608 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2609 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2610 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2611 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2612 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2613 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2614 mem_only = 1;
7c3df132
SK		 2615 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2616 "Mem only adapter.\n");
285d0321 2617 }
7c3df132
SK		 2618 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2619 "Bars=%d.\n", bars);
285d0321 2620
09483916
BH		 2621 if (mem_only) {
2622 if (pci_enable_device_mem(pdev))
2623 goto probe_out;
2624 } else {
2625 if (pci_enable_device(pdev))
2626 goto probe_out;
2627 }
285d0321 2628
0927678f
JB		 2629 /* This may fail but that's ok */
2630 pci_enable_pcie_error_reporting(pdev);
285d0321 2631
e315cd28
AC		 2632 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2633 if (!ha) {
7c3df132
SK		 2634 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2635 "Unable to allocate memory for ha.\n");
e315cd28 2636 goto probe_out;
1da177e4 2637 }
7c3df132
SK		 2638 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2639 "Memory allocated for ha=%p.\n", ha);
e315cd28 2640 ha->pdev = pdev;
2d70c103 2641 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2642 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2643 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2644 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2645 spin_lock_init(&ha->tgt.atio_lock);
2646
1da177e4
LT		 2647
2648 /* Clear our data area */
285d0321 2649 ha->bars = bars;
09483916 2650 ha->mem_only = mem_only;
df4bf0bb 2651 spin_lock_init(&ha->hardware_lock);
339aa70e 2652 spin_lock_init(&ha->vport_slock);
a9b6f722 2653 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2654 mutex_init(&ha->optrom_mutex);
1da177e4 2655
ea5b6382
AV		 2656 /* Set ISP-type information. */
2657 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2658
2659 /* Set EEH reset type to fundamental if required by hba */
95676112 2660 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2661 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2662 pdev->needs_freset = 1;
ca79cf66 2663
cba1e47f
CD		 2664 ha->prev_topology = 0;
2665 ha->init_cb_size = sizeof(init_cb_t);
2666 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2667 ha->optrom_size = OPTROM_SIZE_2300;
2668
abbd8870 2669 /* Assign ISP specific operations. */
1da177e4 2670 if (IS_QLA2100(ha)) {
642ef983 2671 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2672 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2673 req_length = REQUEST_ENTRY_CNT_2100;
2674 rsp_length = RESPONSE_ENTRY_CNT_2100;
2675 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2676 ha->gid_list_info_size = 4;
3a03eb79
AV		 2677 ha->flash_conf_off = ~0;
2678 ha->flash_data_off = ~0;
2679 ha->nvram_conf_off = ~0;
2680 ha->nvram_data_off = ~0;
fd34f556 2681 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2682 } else if (IS_QLA2200(ha)) {
642ef983 2683 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2684 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2685 req_length = REQUEST_ENTRY_CNT_2200;
2686 rsp_length = RESPONSE_ENTRY_CNT_2100;
2687 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2688 ha->gid_list_info_size = 4;
3a03eb79
AV		 2689 ha->flash_conf_off = ~0;
2690 ha->flash_data_off = ~0;
2691 ha->nvram_conf_off = ~0;
2692 ha->nvram_data_off = ~0;
fd34f556 2693 ha->isp_ops = &qla2100_isp_ops;
fca29703 2694 } else if (IS_QLA23XX(ha)) {
642ef983 2695 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2696 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2697 req_length = REQUEST_ENTRY_CNT_2200;
2698 rsp_length = RESPONSE_ENTRY_CNT_2300;
2699 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2700 ha->gid_list_info_size = 6;
854165f4
AV		 2701 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2702 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2703 ha->flash_conf_off = ~0;
2704 ha->flash_data_off = ~0;
2705 ha->nvram_conf_off = ~0;
2706 ha->nvram_data_off = ~0;
fd34f556 2707 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2708 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2709 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2710 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2711 req_length = REQUEST_ENTRY_CNT_24XX;
2712 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2713 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2714 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2715 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2716 ha->gid_list_info_size = 8;
854165f4 2717 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2718 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2719 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2720 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2721 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2722 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2723 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2724 } else if (IS_QLA25XX(ha)) {
642ef983 2725 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2726 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2727 req_length = REQUEST_ENTRY_CNT_24XX;
2728 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2729 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2730 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2731 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2732 ha->gid_list_info_size = 8;
2733 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2734 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2735 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2736 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2737 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2738 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2739 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2740 } else if (IS_QLA81XX(ha)) {
642ef983 2741 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2742 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2743 req_length = REQUEST_ENTRY_CNT_24XX;
2744 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2745 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2746 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2747 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2748 ha->gid_list_info_size = 8;
2749 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2750 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2751 ha->isp_ops = &qla81xx_isp_ops;
2752 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2753 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2754 ha->nvram_conf_off = ~0;
2755 ha->nvram_data_off = ~0;
a9083016 2756 } else if (IS_QLA82XX(ha)) {
642ef983 2757 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2758 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2759 req_length = REQUEST_ENTRY_CNT_82XX;
2760 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2761 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2762 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2763 ha->gid_list_info_size = 8;
2764 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2765 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2766 ha->isp_ops = &qla82xx_isp_ops;
2767 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2768 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2769 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2770 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2771 } else if (IS_QLA8044(ha)) {
2772 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2773 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2774 req_length = REQUEST_ENTRY_CNT_82XX;
2775 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2776 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2777 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2778 ha->gid_list_info_size = 8;
2779 ha->optrom_size = OPTROM_SIZE_83XX;
2780 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2781 ha->isp_ops = &qla8044_isp_ops;
2782 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2783 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2784 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2785 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2786 } else if (IS_QLA83XX(ha)) {
7d613ac6 2787 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2788 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2789 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2790 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2791 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2792 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2793 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2794 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2795 ha->gid_list_info_size = 8;
2796 ha->optrom_size = OPTROM_SIZE_83XX;
2797 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2798 ha->isp_ops = &qla83xx_isp_ops;
2799 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2800 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2801 ha->nvram_conf_off = ~0;
2802 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2803 } else if (IS_QLAFX00(ha)) {
2804 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2805 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2806 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2807 req_length = REQUEST_ENTRY_CNT_FX00;
2808 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2809 ha->isp_ops = &qlafx00_isp_ops;
2810 ha->port_down_retry_count = 30; /* default value */
2811 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2812 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2813 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2814 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2815 ha->mr.host_info_resend = false;
2816 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2817 } else if (IS_QLA27XX(ha)) {
2818 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2819 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2820 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2821 req_length = REQUEST_ENTRY_CNT_83XX;
2822 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2823 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2824 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2825 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2826 ha->gid_list_info_size = 8;
2827 ha->optrom_size = OPTROM_SIZE_83XX;
2828 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2829 ha->isp_ops = &qla27xx_isp_ops;
2830 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2831 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2832 ha->nvram_conf_off = ~0;
2833 ha->nvram_data_off = ~0;
1da177e4 2834 }
6246b8a1 2835
7c3df132
SK		 2836 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2837 "mbx_count=%d, req_length=%d, "
2838 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2839 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2840 "max_fibre_devices=%d.\n",
7c3df132
SK		 2841 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2842 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2843 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2844 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2845 "isp_ops=%p, flash_conf_off=%d, "
2846 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2847 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2848 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2849
2850 /* Configure PCI I/O space */
2851 ret = ha->isp_ops->iospace_config(ha);
2852 if (ret)
0a63ad12 2853 goto iospace_config_failed;
706f457d
GM		 2854
2855 ql_log_pci(ql_log_info, pdev, 0x001d,
2856 "Found an ISP%04X irq %d iobase 0x%p.\n",
2857 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2858 mutex_init(&ha->vport_lock);
d7459527 2859 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2860 init_completion(&ha->mbx_cmd_comp);
2861 complete(&ha->mbx_cmd_comp);
2862 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2863 init_completion(&ha->dcbx_comp);
f356bef1 2864 init_completion(&ha->lb_portup_comp);
1da177e4 2865
2c3dfe3f 2866 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2867
53303c42 2868 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2869 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2870 "64 Bit addressing is %s.\n",
2871 ha->flags.enable_64bit_addressing ? "enable" :
2872 "disable");
73208dfd 2873 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2874 if (ret) {
7c3df132
SK		 2875 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2876 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2877
e315cd28
AC		 2878 goto probe_hw_failed;
2879 }
2880
73208dfd 2881 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2882 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2883 req->max_q_depth = ql2xmaxqdepth;
2884
e315cd28
AC		 2885
2886 base_vha = qla2x00_create_host(sht, ha);
2887 if (!base_vha) {
a1541d5a 2888 ret = -ENOMEM;
6e9f21f3 2889 qla2x00_mem_free(ha);
2afa19a9
AC		 2890 qla2x00_free_req_que(ha, req);
2891 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2892 goto probe_hw_failed;
1da177e4
LT		 2893 }
2894
e315cd28 2895 pci_set_drvdata(pdev, base_vha);
6b383979 2896 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2897
e315cd28 2898 host = base_vha->host;
2afa19a9 2899 base_vha->req = req;
73208dfd 2900 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2901 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2902 else
e315cd28
AC		 2903 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2904 base_vha->vp_idx;
58548cb5 2905
8ae6d9c7
GM		 2906 /* Setup fcport template structure. */
2907 ha->mr.fcport.vha = base_vha;
2908 ha->mr.fcport.port_type = FCT_UNKNOWN;
2909 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2910 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2911 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2912 ha->mr.fcport.scan_state = 1;
2913
58548cb5
GM		 2914 /* Set the SG table size based on ISP type */
2915 if (!IS_FWI2_CAPABLE(ha)) {
2916 if (IS_QLA2100(ha))
2917 host->sg_tablesize = 32;
2918 } else {
2919 if (!IS_QLA82XX(ha))
2920 host->sg_tablesize = QLA_SG_ALL;
2921 }
642ef983 2922 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2923 host->cmd_per_lun = 3;
2924 host->unique_id = host->host_no;
e02587d7 2925 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2926 host->max_cmd_len = 32;
2927 else
2928 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2929 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2930 /* Older HBAs support only 16-bit LUNs */
2931 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2932 ql2xmaxlun > 0xffff)
2933 host->max_lun = 0xffff;
2934 else
2935 host->max_lun = ql2xmaxlun;
e315cd28 2936 host->transportt = qla2xxx_transport_template;
9a069e19 2937 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2938
7c3df132
SK		 2939 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2940 "max_id=%d this_id=%d "
2941 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2942 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2943 host->this_id, host->cmd_per_lun, host->unique_id,
2944 host->max_cmd_len, host->max_channel, host->max_lun,
2945 host->transportt, sht->vendor_id);
2946
d7459527
MH		 2947 /* Set up the irqs */
2948 ret = qla2x00_request_irqs(ha, rsp);
2949 if (ret)
2950 goto probe_init_failed;
2951
9a347ff4
CD		 2952 /* Alloc arrays of request and response ring ptrs */
2953 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2954 ql_log(ql_log_fatal, base_vha, 0x003d,
2955 "Failed to allocate memory for queue pointers..."
2956 "aborting.\n");
2957 goto probe_init_failed;
2958 }
2959
5601236b
MH		 2960 if (ha->mqenable && shost_use_blk_mq(host)) {
2961 /* number of hardware queues supported by blk/scsi-mq*/
2962 host->nr_hw_queues = ha->max_qpairs;
2963
2964 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2965 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2966 } else
2967 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2968 "blk/scsi-mq disabled.\n");
2969
2d70c103 2970 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2971
90a86fc0
JC		 2972 pci_save_state(pdev);
2973
9a347ff4 2974 /* Assign back pointers */
2afa19a9
AC		 2975 rsp->req = req;
2976 req->rsp = rsp;
9a347ff4 2977
8ae6d9c7
GM		 2978 if (IS_QLAFX00(ha)) {
2979 ha->rsp_q_map[0] = rsp;
2980 ha->req_q_map[0] = req;
2981 set_bit(0, ha->req_qid_map);
2982 set_bit(0, ha->rsp_qid_map);
2983 }
2984
08029990
AV		 2985 /* FWI2-capable only. */
2986 req->req_q_in = &ha->iobase->isp24.req_q_in;
2987 req->req_q_out = &ha->iobase->isp24.req_q_out;
2988 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2989 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2990 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2991 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2992 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2993 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2994 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2995 }
2996
8ae6d9c7
GM		 2997 if (IS_QLAFX00(ha)) {
2998 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2999 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3000 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3001 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3002 }
3003
7ec0effd 3004 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3005 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3006 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3007 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3008 }
3009
7c3df132
SK		 3010 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3011 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3012 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3013 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3014 "req->req_q_in=%p req->req_q_out=%p "
3015 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3016 req->req_q_in, req->req_q_out,
3017 rsp->rsp_q_in, rsp->rsp_q_out);
3018 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3019 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3020 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3021 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3022 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3023 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3024
8ae6d9c7 3025 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3026 ql_log(ql_log_fatal, base_vha, 0x00d6,
3027 "Failed to initialize adapter - Adapter flags %x.\n",
3028 base_vha->device_flags);
1da177e4 3029
a9083016
GM		 3030 if (IS_QLA82XX(ha)) {
3031 qla82xx_idc_lock(ha);
3032 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3033 QLA8XXX_DEV_FAILED);
a9083016 3034 qla82xx_idc_unlock(ha);
7c3df132
SK		 3035 ql_log(ql_log_fatal, base_vha, 0x00d7,
3036 "HW State: FAILED.\n");
7ec0effd
AD		 3037 } else if (IS_QLA8044(ha)) {
3038 qla8044_idc_lock(ha);
3039 qla8044_wr_direct(base_vha,
3040 QLA8044_CRB_DEV_STATE_INDEX,
3041 QLA8XXX_DEV_FAILED);
3042 qla8044_idc_unlock(ha);
3043 ql_log(ql_log_fatal, base_vha, 0x0150,
3044 "HW State: FAILED.\n");
a9083016
GM		 3045 }
3046
a1541d5a 3047 ret = -ENODEV;
1da177e4
LT		 3048 goto probe_failed;
3049 }
3050
3b1bef64
CD		 3051 if (IS_QLAFX00(ha))
3052 host->can_queue = QLAFX00_MAX_CANQUEUE;
3053 else
3054 host->can_queue = req->num_outstanding_cmds - 10;
3055
3056 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3057 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3058 host->can_queue, base_vha->req,
3059 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3060
093df737 3061 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3062 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3063 /* Create start of day qpairs for Block MQ */
3064 if (shost_use_blk_mq(host)) {
3065 for (i = 0; i < ha->max_qpairs; i++)
3066 qla2xxx_create_qpair(base_vha, 5, 0);
3067 }
3068 }
68ca949c 3069
cbc8eb67
AV		 3070 if (ha->flags.running_gold_fw)
3071 goto skip_dpc;
3072
1da177e4
LT		 3073 /*
3074 * Startup the kernel thread for this host adapter
3075 */
39a11240 3076 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3077 "%s_dpc", base_vha->host_str);
39a11240 3078 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3079 ql_log(ql_log_fatal, base_vha, 0x00ed,
3080 "Failed to start DPC thread.\n");
39a11240 3081 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3082 goto probe_failed;
3083 }
7c3df132
SK		 3084 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3085 "DPC thread started successfully.\n");
1da177e4 3086
2d70c103
NB		 3087 /*
3088 * If we're not coming up in initiator mode, we might sit for
3089 * a while without waking up the dpc thread, which leads to a
3090 * stuck process warning. So just kick the dpc once here and
3091 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3092 */
3093 qla2xxx_wake_dpc(base_vha);
3094
ec7193e2 3095 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3096 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3097
81178772
SK		 3098 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3099 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3100 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3101 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3102
3103 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3104 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3105 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3106 INIT_WORK(&ha->idc_state_handler,
3107 qla83xx_idc_state_handler_work);
3108 INIT_WORK(&ha->nic_core_unrecoverable,
3109 qla83xx_nic_core_unrecoverable_work);
3110 }
3111
cbc8eb67 3112skip_dpc:
e315cd28
AC		 3113 list_add_tail(&base_vha->list, &ha->vp_list);
3114 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3115
3116 /* Initialized the timer */
e315cd28 3117 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3118 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3119 "Started qla2x00_timer with "
3120 "interval=%d.\n", WATCH_INTERVAL);
3121 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3122 "Detected hba at address=%p.\n",
3123 ha);
d19044c3 3124
e02587d7 3125 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3126 if (ha->fw_attributes & BIT_4) {
9e522cd8 3127 int prot = 0, guard;
bad75002 3128 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3129 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3130 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3131 if (ql2xenabledif == 1)
3132 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3133 scsi_host_set_prot(host,
8cb2049c 3134 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3135 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3136 | SHOST_DIF_TYPE3_PROTECTION
3137 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3138 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3139 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3140
3141 guard = SHOST_DIX_GUARD_CRC;
3142
3143 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3144 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3145 guard |= SHOST_DIX_GUARD_IP;
3146
3147 scsi_host_set_guard(host, guard);
bad75002
AE		 3148 } else
3149 base_vha->flags.difdix_supported = 0;
3150 }
3151
a9083016
GM		 3152 ha->isp_ops->enable_intrs(ha);
3153
1fe19ee4
AB		 3154 if (IS_QLAFX00(ha)) {
3155 ret = qlafx00_fx_disc(base_vha,
3156 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3157 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3158 QLA_SG_ALL : 128;
3159 }
3160
a1541d5a
AV		 3161 ret = scsi_add_host(host, &pdev->dev);
3162 if (ret)
3163 goto probe_failed;
3164
1486400f
MR		 3165 base_vha->flags.init_done = 1;
3166 base_vha->flags.online = 1;
edaa5c74 3167 ha->prev_minidump_failed = 0;
1486400f 3168
7c3df132
SK		 3169 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3170 "Init done and hba is online.\n");
3171
726b8548
QT		 3172 if (qla_ini_mode_enabled(base_vha) ||
3173 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3174 scsi_scan_host(host);
3175 else
3176 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3177 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3178
e315cd28 3179 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3180
8ae6d9c7 3181 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3182 ret = qlafx00_fx_disc(base_vha,
3183 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3184
3185 /* Register system information */
3186 ret = qlafx00_fx_disc(base_vha,
3187 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3188 }
3189
e315cd28 3190 qla2x00_init_host_attr(base_vha);
a1541d5a 3191
e315cd28 3192 qla2x00_dfs_setup(base_vha);
df613b96 3193
03eb912a
AB		 3194 ql_log(ql_log_info, base_vha, 0x00fb,
3195 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3196 ql_log(ql_log_info, base_vha, 0x00fc,
3197 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3198 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3199 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3200 base_vha->host_no,
df57caba 3201 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3202
2d70c103
NB		 3203 qlt_add_target(ha, base_vha);
3204
6b383979 3205 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3206
3207 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3208 return -ENODEV;
3209
1da177e4
LT		 3210 return 0;
3211
6e9f21f3 3212probe_init_failed:
2afa19a9 3213 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3214 ha->req_q_map[0] = NULL;
3215 clear_bit(0, ha->req_qid_map);
2afa19a9 3216 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3217 ha->rsp_q_map[0] = NULL;
3218 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3219 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3220
1da177e4 3221probe_failed:
b9978769
AV		 3222 if (base_vha->timer_active)
3223 qla2x00_stop_timer(base_vha);
3224 base_vha->flags.online = 0;
3225 if (ha->dpc_thread) {
3226 struct task_struct *t = ha->dpc_thread;
3227
3228 ha->dpc_thread = NULL;
3229 kthread_stop(t);
3230 }
3231
e315cd28 3232 qla2x00_free_device(base_vha);
1da177e4 3233
e315cd28 3234 scsi_host_put(base_vha->host);
1da177e4 3235
e315cd28 3236probe_hw_failed:
1a2fbf18
JL		 3237 qla2x00_clear_drv_active(ha);
3238
0a63ad12 3239iospace_config_failed:
7ec0effd 3240 if (IS_P3P_TYPE(ha)) {
0a63ad12 3241 if (!ha->nx_pcibase)
f73cb695 3242 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3243 if (!ql2xdbwr)
f73cb695 3244 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3245 } else {
3246 if (ha->iobase)
3247 iounmap(ha->iobase);
8ae6d9c7
GM		 3248 if (ha->cregbase)
3249 iounmap(ha->cregbase);
a9083016 3250 }
e315cd28
AC		 3251 pci_release_selected_regions(ha->pdev, ha->bars);
3252 kfree(ha);
3253 ha = NULL;
1da177e4 3254
a1541d5a 3255probe_out:
e315cd28 3256 pci_disable_device(pdev);
a1541d5a 3257 return ret;
1da177e4 3258}
1da177e4 3259
e30d1756
MI		 3260static void
3261qla2x00_shutdown(struct pci_dev *pdev)
3262{
3263 scsi_qla_host_t *vha;
3264 struct qla_hw_data *ha;
3265
552f3f9a
MI		 3266 if (!atomic_read(&pdev->enable_cnt))
3267 return;
3268
e30d1756
MI		 3269 vha = pci_get_drvdata(pdev);
3270 ha = vha->hw;
3271
42479343
AB		 3272 /* Notify ISPFX00 firmware */
3273 if (IS_QLAFX00(ha))
3274 qlafx00_driver_shutdown(vha, 20);
3275
e30d1756
MI		 3276 /* Turn-off FCE trace */
3277 if (ha->flags.fce_enabled) {
3278 qla2x00_disable_fce_trace(vha, NULL, NULL);
3279 ha->flags.fce_enabled = 0;
3280 }
3281
3282 /* Turn-off EFT trace */
3283 if (ha->eft)
3284 qla2x00_disable_eft_trace(vha);
3285
3286 /* Stop currently executing firmware. */
3287 qla2x00_try_to_stop_firmware(vha);
3288
3289 /* Turn adapter off line */
3290 vha->flags.online = 0;
3291
3292 /* turn-off interrupts on the card */
3293 if (ha->interrupts_on) {
3294 vha->flags.init_done = 0;
3295 ha->isp_ops->disable_intrs(ha);
3296 }
3297
3298 qla2x00_free_irqs(vha);
3299
3300 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3301
3302 pci_disable_pcie_error_reporting(pdev);
3303 pci_disable_device(pdev);
e30d1756
MI		 3304}
3305
fe1b806f 3306/* Deletes all the virtual ports for a given ha */
4c993f76 3307static void
fe1b806f 3308qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3309{
fe1b806f 3310 scsi_qla_host_t *vha;
feafb7b1 3311 unsigned long flags;
e315cd28 3312
43ebf16d
AE		 3313 mutex_lock(&ha->vport_lock);
3314 while (ha->cur_vport_count) {
43ebf16d 3315 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3316
43ebf16d
AE		 3317 BUG_ON(base_vha->list.next == &ha->vp_list);
3318 /* This assumes first entry in ha->vp_list is always base vha */
3319 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3320 scsi_host_get(vha->host);
feafb7b1 3321
43ebf16d
AE		 3322 spin_unlock_irqrestore(&ha->vport_slock, flags);
3323 mutex_unlock(&ha->vport_lock);
3324
3325 fc_vport_terminate(vha->fc_vport);
3326 scsi_host_put(vha->host);
feafb7b1 3327
43ebf16d 3328 mutex_lock(&ha->vport_lock);
e315cd28 3329 }
43ebf16d 3330 mutex_unlock(&ha->vport_lock);
fe1b806f 3331}
1da177e4 3332
fe1b806f
CD		 3333/* Stops all deferred work threads */
3334static void
3335qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3336{
7d613ac6
SV		 3337 /* Cancel all work and destroy DPC workqueues */
3338 if (ha->dpc_lp_wq) {
3339 cancel_work_sync(&ha->idc_aen);
3340 destroy_workqueue(ha->dpc_lp_wq);
3341 ha->dpc_lp_wq = NULL;
3342 }
3343
3344 if (ha->dpc_hp_wq) {
3345 cancel_work_sync(&ha->nic_core_reset);
3346 cancel_work_sync(&ha->idc_state_handler);
3347 cancel_work_sync(&ha->nic_core_unrecoverable);
3348 destroy_workqueue(ha->dpc_hp_wq);
3349 ha->dpc_hp_wq = NULL;
3350 }
3351
b9978769
AV		 3352 /* Kill the kernel thread for this host */
3353 if (ha->dpc_thread) {
3354 struct task_struct *t = ha->dpc_thread;
3355
3356 /*
3357 * qla2xxx_wake_dpc checks for ->dpc_thread
3358 * so we need to zero it out.
3359 */
3360 ha->dpc_thread = NULL;
3361 kthread_stop(t);
3362 }
fe1b806f 3363}
1da177e4 3364
fe1b806f
CD		 3365static void
3366qla2x00_unmap_iobases(struct qla_hw_data *ha)
3367{
a9083016 3368 if (IS_QLA82XX(ha)) {
b963752f 3369
f73cb695 3370 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3371 if (!ql2xdbwr)
f73cb695 3372 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3373 } else {
3374 if (ha->iobase)
3375 iounmap(ha->iobase);
1da177e4 3376
8ae6d9c7
GM		 3377 if (ha->cregbase)
3378 iounmap(ha->cregbase);
3379
a9083016
GM		 3380 if (ha->mqiobase)
3381 iounmap(ha->mqiobase);
6246b8a1 3382
f73cb695 3383 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3384 iounmap(ha->msixbase);
a9083016 3385 }
fe1b806f
CD		 3386}
3387
3388static void
db7157d4 3389qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3390{
fe1b806f
CD		 3391 if (IS_QLA8044(ha)) {
3392 qla8044_idc_lock(ha);
c41afc9a 3393 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3394 qla8044_idc_unlock(ha);
3395 } else if (IS_QLA82XX(ha)) {
3396 qla82xx_idc_lock(ha);
3397 qla82xx_clear_drv_active(ha);
3398 qla82xx_idc_unlock(ha);
3399 }
3400}
3401
3402static void
3403qla2x00_remove_one(struct pci_dev *pdev)
3404{
3405 scsi_qla_host_t *base_vha;
3406 struct qla_hw_data *ha;
3407
beb9e315
JL		 3408 base_vha = pci_get_drvdata(pdev);
3409 ha = base_vha->hw;
3410
3411 /* Indicate device removal to prevent future board_disable and wait
3412 * until any pending board_disable has completed. */
3413 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3414 cancel_work_sync(&ha->board_disable);
3415
fe1b806f 3416 /*
beb9e315
JL		 3417 * If the PCI device is disabled then there was a PCI-disconnect and
3418 * qla2x00_disable_board_on_pci_error has taken care of most of the
3419 * resources.
fe1b806f 3420 */
beb9e315 3421 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3422 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3423 base_vha->gnl.l, base_vha->gnl.ldma);
3424
beb9e315
JL		 3425 scsi_host_put(base_vha->host);
3426 kfree(ha);
3427 pci_set_drvdata(pdev, NULL);
fe1b806f 3428 return;
beb9e315 3429 }
638a1a01
SC		 3430 qla2x00_wait_for_hba_ready(base_vha);
3431
726b8548
QT		 3432 /*
3433 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3434 * where it was set first.
3435 */
3436 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3437 return;
3438
fe1b806f 3439 set_bit(UNLOADING, &base_vha->dpc_flags);
726b8548
QT		 3440 dma_free_coherent(&ha->pdev->dev,
3441 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3442
3443 if (IS_QLAFX00(ha))
3444 qlafx00_driver_shutdown(base_vha, 20);
3445
3446 qla2x00_delete_all_vps(ha, base_vha);
3447
3448 if (IS_QLA8031(ha)) {
3449 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3450 "Clearing fcoe driver presence.\n");
3451 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3452 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3453 "Error while clearing DRV-Presence.\n");
3454 }
3455
3456 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3457
3458 qla2x00_dfs_remove(base_vha);
3459
3460 qla84xx_put_chip(base_vha);
3461
2d5a4c34
HM		 3462 /* Laser should be disabled only for ISP2031 */
3463 if (IS_QLA2031(ha))
3464 qla83xx_disable_laser(base_vha);
3465
fe1b806f
CD		 3466 /* Disable timer */
3467 if (base_vha->timer_active)
3468 qla2x00_stop_timer(base_vha);
3469
3470 base_vha->flags.online = 0;
3471
b0d6cabd
HM		 3472 /* free DMA memory */
3473 if (ha->exlogin_buf)
3474 qla2x00_free_exlogin_buffer(ha);
3475
2f56a7f1
HM		 3476 /* free DMA memory */
3477 if (ha->exchoffld_buf)
3478 qla2x00_free_exchoffld_buffer(ha);
3479
fe1b806f
CD		 3480 qla2x00_destroy_deferred_work(ha);
3481
3482 qlt_remove_target(ha, base_vha);
3483
3484 qla2x00_free_sysfs_attr(base_vha, true);
3485
3486 fc_remove_host(base_vha->host);
482c9dc7 3487 qlt_remove_target_resources(ha);
fe1b806f
CD		 3488
3489 scsi_remove_host(base_vha->host);
3490
3491 qla2x00_free_device(base_vha);
3492
db7157d4 3493 qla2x00_clear_drv_active(ha);
fe1b806f 3494
d2749ffa
AE		 3495 scsi_host_put(base_vha->host);
3496
fe1b806f 3497 qla2x00_unmap_iobases(ha);
73208dfd 3498
e315cd28
AC		 3499 pci_release_selected_regions(ha->pdev, ha->bars);
3500 kfree(ha);
3501 ha = NULL;
1da177e4 3502
90a86fc0
JC		 3503 pci_disable_pcie_error_reporting(pdev);
3504
665db93b 3505 pci_disable_device(pdev);
1da177e4 3506}
1da177e4
LT		 3507
3508static void
e315cd28 3509qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3510{
e315cd28 3511 struct qla_hw_data *ha = vha->hw;
1da177e4 3512
85880801
AV		 3513 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3514
3515 /* Disable timer */
3516 if (vha->timer_active)
3517 qla2x00_stop_timer(vha);
3518
2afa19a9 3519 qla25xx_delete_queues(vha);
fe1b806f 3520
df613b96 3521 if (ha->flags.fce_enabled)
e315cd28 3522 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3523
a7a167bf 3524 if (ha->eft)
e315cd28 3525 qla2x00_disable_eft_trace(vha);
a7a167bf 3526
f6ef3b18 3527 /* Stop currently executing firmware. */
e315cd28 3528 qla2x00_try_to_stop_firmware(vha);
1da177e4 3529
85880801
AV		 3530 vha->flags.online = 0;
3531
f6ef3b18 3532 /* turn-off interrupts on the card */
a9083016
GM		 3533 if (ha->interrupts_on) {
3534 vha->flags.init_done = 0;
fd34f556 3535 ha->isp_ops->disable_intrs(ha);
a9083016 3536 }
f6ef3b18 3537
093df737
QT		 3538 qla2x00_free_fcports(vha);
3539
e315cd28 3540 qla2x00_free_irqs(vha);
1da177e4 3541
093df737
QT		 3542 /* Flush the work queue and remove it */
3543 if (ha->wq) {
3544 flush_workqueue(ha->wq);
3545 destroy_workqueue(ha->wq);
3546 ha->wq = NULL;
3547 }
3548
8867048b 3549
e315cd28 3550 qla2x00_mem_free(ha);
73208dfd 3551
08de2844
GM		 3552 qla82xx_md_free(vha);
3553
73208dfd 3554 qla2x00_free_queues(ha);
1da177e4
LT		 3555}
3556
8867048b
CD		 3557void qla2x00_free_fcports(struct scsi_qla_host *vha)
3558{
3559 fc_port_t *fcport, *tfcport;
3560
3561 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3562 list_del(&fcport->list);
5f16b331 3563 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3564 kfree(fcport);
3565 fcport = NULL;
3566 }
3567}
3568
d97994dc 3569static inline void
e315cd28 3570qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3571 int defer)
3572{
d97994dc 3573 struct fc_rport *rport;
67becc00 3574 scsi_qla_host_t *base_vha;
044d78e1 3575 unsigned long flags;
d97994dc
AV		 3576
3577 if (!fcport->rport)
3578 return;
3579
3580 rport = fcport->rport;
3581 if (defer) {
67becc00 3582 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3583 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3584 fcport->drport = rport;
044d78e1 3585 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3586 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3587 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3588 qla2xxx_wake_dpc(base_vha);
2d70c103 3589 } else {
df673274 3590 int now;
726b8548
QT		 3591 if (rport) {
3592 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
3593 "%s %8phN. rport %p roles %x \n",
3594 __func__, fcport->port_name, rport,
3595 rport->roles);
d20ed91b 3596 fc_remote_port_delete(rport);
726b8548 3597 }
df673274 3598 qlt_do_generation_tick(vha, &now);
2d70c103 3599 }
d97994dc
AV		 3600}
3601
1da177e4
LT		 3602/*
3603 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3604 *
3605 * Input: ha = adapter block pointer. fcport = port structure pointer.
3606 *
3607 * Return: None.
3608 *
3609 * Context:
3610 */
e315cd28 3611void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3612 int do_login, int defer)
1da177e4 3613{
8ae6d9c7
GM		 3614 if (IS_QLAFX00(vha->hw)) {
3615 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3616 qla2x00_schedule_rport_del(vha, fcport, defer);
3617 return;
3618 }
3619
2c3dfe3f 3620 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3621 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3622 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3623 qla2x00_schedule_rport_del(vha, fcport, defer);
3624 }
fa2a1ce5 3625 /*
1da177e4
LT		 3626 * We may need to retry the login, so don't change the state of the
3627 * port but do the retries.
3628 */
3629 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3630 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3631
3632 if (!do_login)
3633 return;
3634
a1d0285e
AE		 3635 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3636
1da177e4 3637 if (fcport->login_retry == 0) {
e315cd28 3638 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3639
7c3df132 3640 ql_dbg(ql_dbg_disc, vha, 0x2067,
726b8548 3641 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3642 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3643 }
3644}
3645
3646/*
3647 * qla2x00_mark_all_devices_lost
3648 * Updates fcport state when device goes offline.
3649 *
3650 * Input:
3651 * ha = adapter block pointer.
3652 * fcport = port structure pointer.
3653 *
3654 * Return:
3655 * None.
3656 *
3657 * Context:
3658 */
3659void
e315cd28 3660qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3661{
3662 fc_port_t *fcport;
3663
726b8548
QT		 3664 ql_dbg(ql_dbg_disc, vha, 0xffff,
3665 "Mark all dev lost\n");
3666
e315cd28 3667 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3668 fcport->scan_state = 0;
3669 qlt_schedule_sess_for_deletion_lock(fcport);
3670
c6d39e23 3671 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3672 continue;
0d6e61bc 3673
1da177e4
LT		 3674 /*
3675 * No point in marking the device as lost, if the device is
3676 * already DEAD.
3677 */
3678 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3679 continue;
e315cd28 3680 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3681 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3682 if (defer)
3683 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3684 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3685 qla2x00_schedule_rport_del(vha, fcport, defer);
3686 }
1da177e4
LT		 3687 }
3688}
3689
3690/*
3691* qla2x00_mem_alloc
3692* Allocates adapter memory.
3693*
3694* Returns:
3695* 0 = success.
e8711085 3696* !0 = failure.
1da177e4 3697*/
e8711085 3698static int
73208dfd
AC		 3699qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3700 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3701{
3702 char name[16];
1da177e4 3703
e8711085 3704 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3705 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3706 if (!ha->init_cb)
e315cd28 3707 goto fail;
e8711085 3708
2d70c103
NB		 3709 if (qlt_mem_alloc(ha) < 0)
3710 goto fail_free_init_cb;
3711
642ef983
CD		 3712 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3713 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3714 if (!ha->gid_list)
2d70c103 3715 goto fail_free_tgt_mem;
1da177e4 3716
e8711085
AV		 3717 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3718 if (!ha->srb_mempool)
e315cd28 3719 goto fail_free_gid_list;
e8711085 3720
7ec0effd 3721 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3722 /* Allocate cache for CT6 Ctx. */
3723 if (!ctx_cachep) {
3724 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3725 sizeof(struct ct6_dsd), 0,
3726 SLAB_HWCACHE_ALIGN, NULL);
3727 if (!ctx_cachep)
fc1ffd6c 3728 goto fail_free_srb_mempool;
a9083016
GM		 3729 }
3730 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3731 ctx_cachep);
3732 if (!ha->ctx_mempool)
3733 goto fail_free_srb_mempool;
7c3df132
SK		 3734 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3735 "ctx_cachep=%p ctx_mempool=%p.\n",
3736 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3737 }
3738
e8711085
AV		 3739 /* Get memory for cached NVRAM */
3740 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3741 if (!ha->nvram)
a9083016 3742 goto fail_free_ctx_mempool;
e8711085 3743
e315cd28
AC		 3744 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3745 ha->pdev->device);
3746 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3747 DMA_POOL_SIZE, 8, 0);
3748 if (!ha->s_dma_pool)
3749 goto fail_free_nvram;
3750
7c3df132
SK		 3751 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3752 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3753 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3754
7ec0effd 3755 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3756 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3757 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3758 if (!ha->dl_dma_pool) {
7c3df132
SK		 3759 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3760 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3761 goto fail_s_dma_pool;
3762 }
3763
3764 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3765 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3766 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3767 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3768 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3769 goto fail_dl_dma_pool;
3770 }
7c3df132
SK		 3771 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3772 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3773 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3774 }
3775
e8711085
AV		 3776 /* Allocate memory for SNS commands */
3777 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3778 /* Get consistent memory allocated for SNS commands */
e8711085 3779 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3780 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3781 if (!ha->sns_cmd)
e315cd28 3782 goto fail_dma_pool;
7c3df132 3783 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3784 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3785 } else {
e315cd28 3786 /* Get consistent memory allocated for MS IOCB */
e8711085 3787 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3788 &ha->ms_iocb_dma);
e8711085 3789 if (!ha->ms_iocb)
e315cd28
AC		 3790 goto fail_dma_pool;
3791 /* Get consistent memory allocated for CT SNS commands */
e8711085 3792 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3793 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3794 if (!ha->ct_sns)
3795 goto fail_free_ms_iocb;
7c3df132
SK		 3796 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3797 "ms_iocb=%p ct_sns=%p.\n",
3798 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3799 }
3800
e315cd28 3801 /* Allocate memory for request ring */
73208dfd
AC		 3802 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3803 if (!*req) {
7c3df132
SK		 3804 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3805 "Failed to allocate memory for req.\n");
e315cd28
AC		 3806 goto fail_req;
3807 }
73208dfd
AC		 3808 (*req)->length = req_len;
3809 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3810 ((*req)->length + 1) * sizeof(request_t),
3811 &(*req)->dma, GFP_KERNEL);
3812 if (!(*req)->ring) {
7c3df132
SK		 3813 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3814 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3815 goto fail_req_ring;
3816 }
3817 /* Allocate memory for response ring */
73208dfd
AC		 3818 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3819 if (!*rsp) {
7c3df132
SK		 3820 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3821 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3822 goto fail_rsp;
3823 }
73208dfd
AC		 3824 (*rsp)->hw = ha;
3825 (*rsp)->length = rsp_len;
3826 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3827 ((*rsp)->length + 1) * sizeof(response_t),
3828 &(*rsp)->dma, GFP_KERNEL);
3829 if (!(*rsp)->ring) {
7c3df132
SK		 3830 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3831 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3832 goto fail_rsp_ring;
3833 }
73208dfd
AC		 3834 (*req)->rsp = *rsp;
3835 (*rsp)->req = *req;
7c3df132
SK		 3836 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3837 "req=%p req->length=%d req->ring=%p rsp=%p "
3838 "rsp->length=%d rsp->ring=%p.\n",
3839 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3840 (*rsp)->ring);
73208dfd
AC		 3841 /* Allocate memory for NVRAM data for vports */
3842 if (ha->nvram_npiv_size) {
3843 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3844 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3845 if (!ha->npiv_info) {
7c3df132
SK		 3846 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3847 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3848 goto fail_npiv_info;
3849 }
3850 } else
3851 ha->npiv_info = NULL;
e8711085 3852
b64b0e8f 3853 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3854 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3855 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3856 &ha->ex_init_cb_dma);
3857 if (!ha->ex_init_cb)
3858 goto fail_ex_init_cb;
7c3df132
SK		 3859 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3860 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3861 }
3862
a9083016
GM		 3863 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3864
5ff1d584
AV		 3865 /* Get consistent memory allocated for Async Port-Database. */
3866 if (!IS_FWI2_CAPABLE(ha)) {
3867 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3868 &ha->async_pd_dma);
3869 if (!ha->async_pd)
3870 goto fail_async_pd;
7c3df132
SK		 3871 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3872 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3873 }
3874
e315cd28 3875 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3876
3877 /* Allocate memory for our loop_id bitmap */
3878 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3879 GFP_KERNEL);
3880 if (!ha->loop_id_map)
fc1ffd6c 3881 goto fail_loop_id_map;
5f16b331
CD		 3882 else {
3883 qla2x00_set_reserved_loop_ids(ha);
3884 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3885 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3886 }
3887
b2a72ec3 3888 return 0;
e315cd28 3889
fc1ffd6c
QT		 3890fail_loop_id_map:
3891 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3892fail_async_pd:
3893 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3894fail_ex_init_cb:
3895 kfree(ha->npiv_info);
73208dfd
AC		 3896fail_npiv_info:
3897 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3898 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3899 (*rsp)->ring = NULL;
3900 (*rsp)->dma = 0;
e315cd28 3901fail_rsp_ring:
73208dfd 3902 kfree(*rsp);
e315cd28 3903fail_rsp:
73208dfd
AC		 3904 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3905 sizeof(request_t), (*req)->ring, (*req)->dma);
3906 (*req)->ring = NULL;
3907 (*req)->dma = 0;
e315cd28 3908fail_req_ring:
73208dfd 3909 kfree(*req);
e315cd28
AC		 3910fail_req:
3911 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3912 ha->ct_sns, ha->ct_sns_dma);
3913 ha->ct_sns = NULL;
3914 ha->ct_sns_dma = 0;
e8711085
AV		 3915fail_free_ms_iocb:
3916 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3917 ha->ms_iocb = NULL;
3918 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3919
3920 if (ha->sns_cmd)
3921 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3922 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3923fail_dma_pool:
bad75002 3924 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3925 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3926 ha->fcp_cmnd_dma_pool = NULL;
3927 }
3928fail_dl_dma_pool:
bad75002 3929 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3930 dma_pool_destroy(ha->dl_dma_pool);
3931 ha->dl_dma_pool = NULL;
3932 }
3933fail_s_dma_pool:
e315cd28
AC		 3934 dma_pool_destroy(ha->s_dma_pool);
3935 ha->s_dma_pool = NULL;
e8711085
AV		 3936fail_free_nvram:
3937 kfree(ha->nvram);
3938 ha->nvram = NULL;
a9083016 3939fail_free_ctx_mempool:
fc1ffd6c
QT		 3940 if (ha->ctx_mempool)
3941 mempool_destroy(ha->ctx_mempool);
a9083016 3942 ha->ctx_mempool = NULL;
e8711085 3943fail_free_srb_mempool:
fc1ffd6c
QT		 3944 if (ha->srb_mempool)
3945 mempool_destroy(ha->srb_mempool);
e8711085 3946 ha->srb_mempool = NULL;
e8711085 3947fail_free_gid_list:
642ef983
CD		 3948 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3949 ha->gid_list,
e315cd28 3950 ha->gid_list_dma);
e8711085
AV		 3951 ha->gid_list = NULL;
3952 ha->gid_list_dma = 0;
2d70c103
NB		 3953fail_free_tgt_mem:
3954 qlt_mem_free(ha);
e315cd28
AC		 3955fail_free_init_cb:
3956 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3957 ha->init_cb_dma);
3958 ha->init_cb = NULL;
3959 ha->init_cb_dma = 0;
e8711085 3960fail:
7c3df132
SK		 3961 ql_log(ql_log_fatal, NULL, 0x0030,
3962 "Memory allocation failure.\n");
e8711085 3963 return -ENOMEM;
1da177e4
LT		 3964}
3965
b0d6cabd
HM		 3966int
3967qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3968{
3969 int rval;
3970 uint16_t size, max_cnt, temp;
3971 struct qla_hw_data *ha = vha->hw;
3972
3973 /* Return if we don't need to alloacate any extended logins */
3974 if (!ql2xexlogins)
3975 return QLA_SUCCESS;
3976
3977 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3978 max_cnt = 0;
3979 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3980 if (rval != QLA_SUCCESS) {
3981 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3982 "Failed to get exlogin status.\n");
3983 return rval;
3984 }
3985
3986 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3987 ha->exlogin_size = (size * temp);
3988 ql_log(ql_log_info, vha, 0xd024,
3989 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3990 max_cnt, size, temp);
3991
3992 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3993 ha->exlogin_size);
3994
3995 /* Get consistent memory for extended logins */
3996 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3997 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3998 if (!ha->exlogin_buf) {
3999 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4000 "Failed to allocate memory for exlogin_buf_dma.\n");
4001 return -ENOMEM;
4002 }
4003
4004 /* Now configure the dma buffer */
4005 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4006 if (rval) {
4007 ql_log(ql_log_fatal, vha, 0x00cf,
4008 "Setup extended login buffer ****FAILED****.\n");
4009 qla2x00_free_exlogin_buffer(ha);
4010 }
4011
4012 return rval;
4013}
4014
4015/*
4016* qla2x00_free_exlogin_buffer
4017*
4018* Input:
4019* ha = adapter block pointer
4020*/
4021void
4022qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4023{
4024 if (ha->exlogin_buf) {
4025 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4026 ha->exlogin_buf, ha->exlogin_buf_dma);
4027 ha->exlogin_buf = NULL;
4028 ha->exlogin_size = 0;
4029 }
4030}
4031
2f56a7f1
HM		 4032int
4033qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4034{
4035 int rval;
4036 uint16_t size, max_cnt, temp;
4037 struct qla_hw_data *ha = vha->hw;
4038
4039 /* Return if we don't need to alloacate any extended logins */
4040 if (!ql2xexchoffld)
4041 return QLA_SUCCESS;
4042
4043 ql_log(ql_log_info, vha, 0xd014,
4044 "Exchange offload count: %d.\n", ql2xexlogins);
4045
4046 max_cnt = 0;
4047 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4048 if (rval != QLA_SUCCESS) {
4049 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4050 "Failed to get exlogin status.\n");
4051 return rval;
4052 }
4053
4054 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
4055 ha->exchoffld_size = (size * temp);
4056 ql_log(ql_log_info, vha, 0xd016,
4057 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4058 max_cnt, size, temp);
4059
4060 ql_log(ql_log_info, vha, 0xd017,
4061 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
4062
4063 /* Get consistent memory for extended logins */
4064 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4065 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4066 if (!ha->exchoffld_buf) {
4067 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4068 "Failed to allocate memory for exchoffld_buf_dma.\n");
4069 return -ENOMEM;
4070 }
4071
4072 /* Now configure the dma buffer */
4073 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4074 if (rval) {
4075 ql_log(ql_log_fatal, vha, 0xd02e,
4076 "Setup exchange offload buffer ****FAILED****.\n");
4077 qla2x00_free_exchoffld_buffer(ha);
4078 }
4079
4080 return rval;
4081}
4082
4083/*
4084* qla2x00_free_exchoffld_buffer
4085*
4086* Input:
4087* ha = adapter block pointer
4088*/
4089void
4090qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4091{
4092 if (ha->exchoffld_buf) {
4093 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4094 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4095 ha->exchoffld_buf = NULL;
4096 ha->exchoffld_size = 0;
4097 }
4098}
4099
1da177e4 4100/*
e30d1756
MI		 4101* qla2x00_free_fw_dump
4102* Frees fw dump stuff.
1da177e4
LT		 4103*
4104* Input:
7ec0effd 4105* ha = adapter block pointer
1da177e4 4106*/
a824ebb3 4107static void
e30d1756 4108qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4109{
df613b96 4110 if (ha->fce)
f73cb695
CD		 4111 dma_free_coherent(&ha->pdev->dev,
4112 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4113
f73cb695
CD		 4114 if (ha->eft)
4115 dma_free_coherent(&ha->pdev->dev,
4116 EFT_SIZE, ha->eft, ha->eft_dma);
4117
4118 if (ha->fw_dump)
a7a167bf 4119 vfree(ha->fw_dump);
f73cb695
CD		 4120 if (ha->fw_dump_template)
4121 vfree(ha->fw_dump_template);
4122
e30d1756
MI		 4123 ha->fce = NULL;
4124 ha->fce_dma = 0;
4125 ha->eft = NULL;
4126 ha->eft_dma = 0;
e30d1756 4127 ha->fw_dumped = 0;
61f098dd 4128 ha->fw_dump_cap_flags = 0;
e30d1756 4129 ha->fw_dump_reading = 0;
f73cb695
CD		 4130 ha->fw_dump = NULL;
4131 ha->fw_dump_len = 0;
4132 ha->fw_dump_template = NULL;
4133 ha->fw_dump_template_len = 0;
e30d1756
MI		 4134}
4135
4136/*
4137* qla2x00_mem_free
4138* Frees all adapter allocated memory.
4139*
4140* Input:
4141* ha = adapter block pointer.
4142*/
4143static void
4144qla2x00_mem_free(struct qla_hw_data *ha)
4145{
4146 qla2x00_free_fw_dump(ha);
4147
81178772
SK		 4148 if (ha->mctp_dump)
4149 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4150 ha->mctp_dump_dma);
4151
e30d1756
MI		 4152 if (ha->srb_mempool)
4153 mempool_destroy(ha->srb_mempool);
a7a167bf 4154
11bbc1d8
AV		 4155 if (ha->dcbx_tlv)
4156 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4157 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4158
ce0423f4
AV		 4159 if (ha->xgmac_data)
4160 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4161 ha->xgmac_data, ha->xgmac_data_dma);
4162
1da177e4
LT		 4163 if (ha->sns_cmd)
4164 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4165 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4166
4167 if (ha->ct_sns)
4168 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4169 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4170
88729e53
AV		 4171 if (ha->sfp_data)
4172 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4173
1da177e4
LT		 4174 if (ha->ms_iocb)
4175 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4176
b64b0e8f 4177 if (ha->ex_init_cb)
a9083016
GM		 4178 dma_pool_free(ha->s_dma_pool,
4179 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4180
5ff1d584
AV		 4181 if (ha->async_pd)
4182 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4183
1da177e4
LT		 4184 if (ha->s_dma_pool)
4185 dma_pool_destroy(ha->s_dma_pool);
4186
1da177e4 4187 if (ha->gid_list)
642ef983
CD		 4188 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4189 ha->gid_list, ha->gid_list_dma);
1da177e4 4190
a9083016
GM		 4191 if (IS_QLA82XX(ha)) {
4192 if (!list_empty(&ha->gbl_dsd_list)) {
4193 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4194
4195 /* clean up allocated prev pool */
4196 list_for_each_entry_safe(dsd_ptr,
4197 tdsd_ptr, &ha->gbl_dsd_list, list) {
4198 dma_pool_free(ha->dl_dma_pool,
4199 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4200 list_del(&dsd_ptr->list);
4201 kfree(dsd_ptr);
4202 }
4203 }
4204 }
4205
4206 if (ha->dl_dma_pool)
4207 dma_pool_destroy(ha->dl_dma_pool);
4208
4209 if (ha->fcp_cmnd_dma_pool)
4210 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4211
4212 if (ha->ctx_mempool)
4213 mempool_destroy(ha->ctx_mempool);
4214
2d70c103
NB		 4215 qlt_mem_free(ha);
4216
e315cd28
AC		 4217 if (ha->init_cb)
4218 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4219 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4220 vfree(ha->optrom_buffer);
4221 kfree(ha->nvram);
73208dfd 4222 kfree(ha->npiv_info);
7a67735b 4223 kfree(ha->swl);
5f16b331 4224 kfree(ha->loop_id_map);
1da177e4 4225
e8711085 4226 ha->srb_mempool = NULL;
a9083016 4227 ha->ctx_mempool = NULL;
1da177e4
LT		 4228 ha->sns_cmd = NULL;
4229 ha->sns_cmd_dma = 0;
4230 ha->ct_sns = NULL;
4231 ha->ct_sns_dma = 0;
4232 ha->ms_iocb = NULL;
4233 ha->ms_iocb_dma = 0;
1da177e4
LT		 4234 ha->init_cb = NULL;
4235 ha->init_cb_dma = 0;
b64b0e8f
AV		 4236 ha->ex_init_cb = NULL;
4237 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4238 ha->async_pd = NULL;
4239 ha->async_pd_dma = 0;
1da177e4
LT		 4240
4241 ha->s_dma_pool = NULL;
a9083016
GM		 4242 ha->dl_dma_pool = NULL;
4243 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4244
1da177e4
LT		 4245 ha->gid_list = NULL;
4246 ha->gid_list_dma = 0;
2d70c103
NB		 4247
4248 ha->tgt.atio_ring = NULL;
4249 ha->tgt.atio_dma = 0;
4250 ha->tgt.tgt_vp_map = NULL;
e315cd28 4251}
1da177e4 4252
e315cd28
AC		 4253struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4254 struct qla_hw_data *ha)
4255{
4256 struct Scsi_Host *host;
4257 struct scsi_qla_host *vha = NULL;
854165f4 4258
e315cd28 4259 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4260 if (!host) {
7c3df132
SK		 4261 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4262 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4263 return NULL;
e315cd28
AC		 4264 }
4265
4266 /* Clear our data area */
4267 vha = shost_priv(host);
4268 memset(vha, 0, sizeof(scsi_qla_host_t));
4269
4270 vha->host = host;
4271 vha->host_no = host->host_no;
4272 vha->hw = ha;
4273
4274 INIT_LIST_HEAD(&vha->vp_fcports);
4275 INIT_LIST_HEAD(&vha->work_list);
4276 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4277 INIT_LIST_HEAD(&vha->qla_cmd_list);
4278 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4279 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4280 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4281 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4282 INIT_LIST_HEAD(&vha->gnl.fcports);
e315cd28 4283
f999f4c1 4284 spin_lock_init(&vha->work_lock);
8b2f5ff3 4285 spin_lock_init(&vha->cmd_list_lock);
726b8548 4286 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4287 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4288
2fdbc65e
BVA		 4289 vha->gnl.size = sizeof(struct get_name_list_extended) *
4290 (ha->max_loop_id + 1);
41dc529a
QT		 4291 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4292 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4293 if (!vha->gnl.l) {
4294 ql_log(ql_log_fatal, vha, 0xffff,
4295 "Alloc failed for name list.\n");
4296 scsi_remove_host(vha->host);
4297 return NULL;
4298 }
f999f4c1 4299
e315cd28 4300 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4301 ql_dbg(ql_dbg_init, vha, 0x0041,
4302 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4303 vha->host, vha->hw, vha,
4304 dev_name(&(ha->pdev->dev)));
4305
e315cd28 4306 return vha;
1da177e4
LT		 4307}
4308
726b8548 4309struct qla_work_evt *
f999f4c1 4310qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4311{
4312 struct qla_work_evt *e;
feafb7b1
AE		 4313 uint8_t bail;
4314
4315 QLA_VHA_MARK_BUSY(vha, bail);
4316 if (bail)
4317 return NULL;
0971de7f 4318
f999f4c1 4319 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4320 if (!e) {
4321 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4322 return NULL;
feafb7b1 4323 }
0971de7f
AV		 4324
4325 INIT_LIST_HEAD(&e->list);
4326 e->type = type;
4327 e->flags = QLA_EVT_FLAG_FREE;
4328 return e;
4329}
4330
726b8548 4331int
f999f4c1 4332qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4333{
f999f4c1 4334 unsigned long flags;
0971de7f 4335
f999f4c1 4336 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4337 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4338 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4339
4340 if (QLA_EARLY_LINKUP(vha->hw))
4341 schedule_work(&vha->iocb_work);
4342 else
4343 qla2xxx_wake_dpc(vha);
f999f4c1 4344
0971de7f
AV		 4345 return QLA_SUCCESS;
4346}
4347
4348int
e315cd28 4349qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4350 u32 data)
4351{
4352 struct qla_work_evt *e;
4353
f999f4c1 4354 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4355 if (!e)
4356 return QLA_FUNCTION_FAILED;
4357
4358 e->u.aen.code = code;
4359 e->u.aen.data = data;
f999f4c1 4360 return qla2x00_post_work(vha, e);
0971de7f
AV		 4361}
4362
8a659571
AV		 4363int
4364qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4365{
4366 struct qla_work_evt *e;
4367
f999f4c1 4368 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4369 if (!e)
4370 return QLA_FUNCTION_FAILED;
4371
4372 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4373 return qla2x00_post_work(vha, e);
8a659571
AV		 4374}
4375
ac280b67
AV		 4376#define qla2x00_post_async_work(name, type) \
4377int qla2x00_post_async_##name##_work( \
4378 struct scsi_qla_host *vha, \
4379 fc_port_t *fcport, uint16_t *data) \
4380{ \
4381 struct qla_work_evt *e; \
4382 \
4383 e = qla2x00_alloc_work(vha, type); \
4384 if (!e) \
4385 return QLA_FUNCTION_FAILED; \
4386 \
4387 e->u.logio.fcport = fcport; \
4388 if (data) { \
4389 e->u.logio.data[0] = data[0]; \
4390 e->u.logio.data[1] = data[1]; \
4391 } \
4392 return qla2x00_post_work(vha, e); \
4393}
4394
4395qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4396qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4397qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4398qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4399qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4400
3420d36c
AV		 4401int
4402qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4403{
4404 struct qla_work_evt *e;
4405
4406 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4407 if (!e)
4408 return QLA_FUNCTION_FAILED;
4409
4410 e->u.uevent.code = code;
4411 return qla2x00_post_work(vha, e);
4412}
4413
4414static void
4415qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4416{
4417 char event_string[40];
4418 char *envp[] = { event_string, NULL };
4419
4420 switch (code) {
4421 case QLA_UEVENT_CODE_FW_DUMP:
4422 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4423 vha->host_no);
4424 break;
4425 default:
4426 /* do nothing */
4427 break;
4428 }
4429 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4430}
4431
8ae6d9c7
GM		 4432int
4433qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4434 uint32_t *data, int cnt)
4435{
4436 struct qla_work_evt *e;
4437
4438 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4439 if (!e)
4440 return QLA_FUNCTION_FAILED;
4441
4442 e->u.aenfx.evtcode = evtcode;
4443 e->u.aenfx.count = cnt;
4444 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4445 return qla2x00_post_work(vha, e);
4446}
4447
726b8548
QT		 4448int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4449{
4450 struct qla_work_evt *e;
4451
4452 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4453 if (!e)
4454 return QLA_FUNCTION_FAILED;
4455
4456 e->u.fcport.fcport = fcport;
4457 return qla2x00_post_work(vha, e);
4458}
4459
4460static
4461void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4462{
4463 unsigned long flags;
4464 fc_port_t *fcport = NULL;
4465 struct qlt_plogi_ack_t *pla =
4466 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4467
4468 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4469 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4470 if (fcport) {
4471 fcport->d_id = e->u.new_sess.id;
4472 if (pla) {
4473 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4474 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4475 /* we took an extra ref_count to prevent PLOGI ACK when
4476 * fcport/sess has not been created.
4477 */
4478 pla->ref_count--;
4479 }
4480 } else {
4481 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4482 if (fcport) {
4483 fcport->d_id = e->u.new_sess.id;
4484 fcport->scan_state = QLA_FCPORT_FOUND;
4485 fcport->flags |= FCF_FABRIC_DEVICE;
4486 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4487
4488 memcpy(fcport->port_name, e->u.new_sess.port_name,
4489 WWN_SIZE);
4490 list_add_tail(&fcport->list, &vha->vp_fcports);
4491
4492 if (pla) {
4493 qlt_plogi_ack_link(vha, pla, fcport,
4494 QLT_PLOGI_LINK_SAME_WWN);
4495 pla->ref_count--;
4496 }
4497 }
4498 }
4499 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4500
4501 if (fcport) {
4502 if (pla)
4503 qlt_plogi_ack_unref(vha, pla);
4504 else
4505 qla24xx_async_gnl(vha, fcport);
4506 }
4507}
4508
ac280b67 4509void
e315cd28 4510qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4511{
f999f4c1
AV		 4512 struct qla_work_evt *e, *tmp;
4513 unsigned long flags;
4514 LIST_HEAD(work);
0971de7f 4515
f999f4c1
AV		 4516 spin_lock_irqsave(&vha->work_lock, flags);
4517 list_splice_init(&vha->work_list, &work);
4518 spin_unlock_irqrestore(&vha->work_lock, flags);
4519
4520 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4521 list_del_init(&e->list);
0971de7f
AV		 4522
4523 switch (e->type) {
4524 case QLA_EVT_AEN:
e315cd28 4525 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4526 e->u.aen.code, e->u.aen.data);
4527 break;
8a659571
AV		 4528 case QLA_EVT_IDC_ACK:
4529 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4530 break;
ac280b67
AV		 4531 case QLA_EVT_ASYNC_LOGIN:
4532 qla2x00_async_login(vha, e->u.logio.fcport,
4533 e->u.logio.data);
4534 break;
ac280b67
AV		 4535 case QLA_EVT_ASYNC_LOGOUT:
4536 qla2x00_async_logout(vha, e->u.logio.fcport);
4537 break;
4538 case QLA_EVT_ASYNC_LOGOUT_DONE:
4539 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4540 e->u.logio.data);
4541 break;
5ff1d584
AV		 4542 case QLA_EVT_ASYNC_ADISC:
4543 qla2x00_async_adisc(vha, e->u.logio.fcport,
4544 e->u.logio.data);
4545 break;
4546 case QLA_EVT_ASYNC_ADISC_DONE:
4547 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4548 e->u.logio.data);
4549 break;
3420d36c
AV		 4550 case QLA_EVT_UEVENT:
4551 qla2x00_uevent_emit(vha, e->u.uevent.code);
4552 break;
8ae6d9c7
GM		 4553 case QLA_EVT_AENFX:
4554 qlafx00_process_aen(vha, e);
4555 break;
726b8548
QT		 4556 case QLA_EVT_GIDPN:
4557 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4558 break;
4559 case QLA_EVT_GPNID:
4560 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4561 break;
4562 case QLA_EVT_GPNID_DONE:
4563 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4564 break;
4565 case QLA_EVT_NEW_SESS:
4566 qla24xx_create_new_sess(vha, e);
4567 break;
4568 case QLA_EVT_GPDB:
4569 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4570 e->u.fcport.opt);
4571 break;
4572 case QLA_EVT_GPSC:
4573 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4574 break;
4575 case QLA_EVT_UPD_FCPORT:
4576 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4577 break;
4578 case QLA_EVT_GNL:
4579 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4580 break;
4581 case QLA_EVT_NACK:
4582 qla24xx_do_nack_work(vha, e);
4583 break;
0971de7f
AV		 4584 }
4585 if (e->flags & QLA_EVT_FLAG_FREE)
4586 kfree(e);
feafb7b1
AE		 4587
4588 /* For each work completed decrement vha ref count */
4589 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4590 }
e315cd28 4591}
f999f4c1 4592
e315cd28
AC		 4593/* Relogins all the fcports of a vport
4594 * Context: dpc thread
4595 */
4596void qla2x00_relogin(struct scsi_qla_host *vha)
4597{
4598 fc_port_t *fcport;
c6b2fca8 4599 int status;
726b8548 4600 struct event_arg ea;
e315cd28
AC		 4601
4602 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4603 /*
4604 * If the port is not ONLINE then try to login
4605 * to it if we haven't run out of retries.
4606 */
5ff1d584
AV		 4607 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4608 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4609 fcport->login_retry--;
e315cd28 4610 if (fcport->flags & FCF_FABRIC_DEVICE) {
726b8548
QT		 4611 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
4612 "%s %8phC DS %d LS %d\n", __func__,
4613 fcport->port_name, fcport->disc_state,
4614 fcport->fw_login_state);
4615 memset(&ea, 0, sizeof(ea));
4616 ea.event = FCME_RELOGIN;
4617 ea.fcport = fcport;
4618 qla2x00_fcport_event_handler(vha, &ea);
4619 } else {
e315cd28
AC		 4620 status = qla2x00_local_device_login(vha,
4621 fcport);
726b8548
QT		 4622 if (status == QLA_SUCCESS) {
4623 fcport->old_loop_id = fcport->loop_id;
4624 ql_dbg(ql_dbg_disc, vha, 0x2003,
4625 "Port login OK: logged in ID 0x%x.\n",
4626 fcport->loop_id);
4627 qla2x00_update_fcport(vha, fcport);
4628 } else if (status == 1) {
4629 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4630 /* retry the login again */
4631 ql_dbg(ql_dbg_disc, vha, 0x2007,
4632 "Retrying %d login again loop_id 0x%x.\n",
4633 fcport->login_retry,
4634 fcport->loop_id);
4635 } else {
4636 fcport->login_retry = 0;
4637 }
e315cd28 4638
726b8548
QT		 4639 if (fcport->login_retry == 0 &&
4640 status != QLA_SUCCESS)
4641 qla2x00_clear_loop_id(fcport);
e315cd28 4642 }
e315cd28
AC		 4643 }
4644 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4645 break;
0971de7f 4646 }
0971de7f
AV		 4647}
4648
7d613ac6
SV		 4649/* Schedule work on any of the dpc-workqueues */
4650void
4651qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4652{
4653 struct qla_hw_data *ha = base_vha->hw;
4654
4655 switch (work_code) {
4656 case MBA_IDC_AEN: /* 0x8200 */
4657 if (ha->dpc_lp_wq)
4658 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4659 break;
4660
4661 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4662 if (!ha->flags.nic_core_reset_hdlr_active) {
4663 if (ha->dpc_hp_wq)
4664 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4665 } else
4666 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4667 "NIC Core reset is already active. Skip "
4668 "scheduling it again.\n");
4669 break;
4670 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4671 if (ha->dpc_hp_wq)
4672 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4673 break;
4674 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4675 if (ha->dpc_hp_wq)
4676 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4677 break;
4678 default:
4679 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4680 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4681 }
4682
4683 return;
4684}
4685
4686/* Work: Perform NIC Core Unrecoverable state handling */
4687void
4688qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4689{
4690 struct qla_hw_data *ha =
2ad1b67c 4691 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4692 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4693 uint32_t dev_state = 0;
4694
4695 qla83xx_idc_lock(base_vha, 0);
4696 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4697 qla83xx_reset_ownership(base_vha);
4698 if (ha->flags.nic_core_reset_owner) {
4699 ha->flags.nic_core_reset_owner = 0;
4700 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4701 QLA8XXX_DEV_FAILED);
4702 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4703 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4704 }
4705 qla83xx_idc_unlock(base_vha, 0);
4706}
4707
4708/* Work: Execute IDC state handler */
4709void
4710qla83xx_idc_state_handler_work(struct work_struct *work)
4711{
4712 struct qla_hw_data *ha =
2ad1b67c 4713 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4714 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4715 uint32_t dev_state = 0;
4716
4717 qla83xx_idc_lock(base_vha, 0);
4718 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4719 if (dev_state == QLA8XXX_DEV_FAILED ||
4720 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4721 qla83xx_idc_state_handler(base_vha);
4722 qla83xx_idc_unlock(base_vha, 0);
4723}
4724
fa492630 4725static int
7d613ac6
SV		 4726qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4727{
4728 int rval = QLA_SUCCESS;
4729 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4730 uint32_t heart_beat_counter1, heart_beat_counter2;
4731
4732 do {
4733 if (time_after(jiffies, heart_beat_wait)) {
4734 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4735 "Nic Core f/w is not alive.\n");
4736 rval = QLA_FUNCTION_FAILED;
4737 break;
4738 }
4739
4740 qla83xx_idc_lock(base_vha, 0);
4741 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4742 &heart_beat_counter1);
4743 qla83xx_idc_unlock(base_vha, 0);
4744 msleep(100);
4745 qla83xx_idc_lock(base_vha, 0);
4746 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4747 &heart_beat_counter2);
4748 qla83xx_idc_unlock(base_vha, 0);
4749 } while (heart_beat_counter1 == heart_beat_counter2);
4750
4751 return rval;
4752}
4753
4754/* Work: Perform NIC Core Reset handling */
4755void
4756qla83xx_nic_core_reset_work(struct work_struct *work)
4757{
4758 struct qla_hw_data *ha =
4759 container_of(work, struct qla_hw_data, nic_core_reset);
4760 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4761 uint32_t dev_state = 0;
4762
81178772
SK		 4763 if (IS_QLA2031(ha)) {
4764 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4765 ql_log(ql_log_warn, base_vha, 0xb081,
4766 "Failed to dump mctp\n");
4767 return;
4768 }
4769
7d613ac6
SV		 4770 if (!ha->flags.nic_core_reset_hdlr_active) {
4771 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4772 qla83xx_idc_lock(base_vha, 0);
4773 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4774 &dev_state);
4775 qla83xx_idc_unlock(base_vha, 0);
4776 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4777 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4778 "Nic Core f/w is alive.\n");
4779 return;
4780 }
4781 }
4782
4783 ha->flags.nic_core_reset_hdlr_active = 1;
4784 if (qla83xx_nic_core_reset(base_vha)) {
4785 /* NIC Core reset failed. */
4786 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4787 "NIC Core reset failed.\n");
4788 }
4789 ha->flags.nic_core_reset_hdlr_active = 0;
4790 }
4791}
4792
4793/* Work: Handle 8200 IDC aens */
4794void
4795qla83xx_service_idc_aen(struct work_struct *work)
4796{
4797 struct qla_hw_data *ha =
4798 container_of(work, struct qla_hw_data, idc_aen);
4799 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4800 uint32_t dev_state, idc_control;
4801
4802 qla83xx_idc_lock(base_vha, 0);
4803 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4804 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4805 qla83xx_idc_unlock(base_vha, 0);
4806 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4807 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4808 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4809 "Application requested NIC Core Reset.\n");
4810 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4811 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4812 QLA_SUCCESS) {
4813 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4814 "Other protocol driver requested NIC Core Reset.\n");
4815 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4816 }
4817 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4818 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4819 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4820 }
4821}
4822
4823static void
4824qla83xx_wait_logic(void)
4825{
4826 int i;
4827
4828 /* Yield CPU */
4829 if (!in_interrupt()) {
4830 /*
4831 * Wait about 200ms before retrying again.
4832 * This controls the number of retries for single
4833 * lock operation.
4834 */
4835 msleep(100);
4836 schedule();
4837 } else {
4838 for (i = 0; i < 20; i++)
4839 cpu_relax(); /* This a nop instr on i386 */
4840 }
4841}
4842
fa492630 4843static int
7d613ac6
SV		 4844qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4845{
4846 int rval;
4847 uint32_t data;
4848 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4849 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4850 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4851 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4852 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4853
4854 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4855 if (rval)
4856 return rval;
4857
4858 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4859 return QLA_SUCCESS;
4860 } else {
4861 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4862 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4863 data);
4864 if (rval)
4865 return rval;
4866
4867 msleep(200);
4868
4869 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4870 &data);
4871 if (rval)
4872 return rval;
4873
4874 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4875 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4876 ~(idc_lck_rcvry_stage_mask));
4877 rval = qla83xx_wr_reg(base_vha,
4878 QLA83XX_IDC_LOCK_RECOVERY, data);
4879 if (rval)
4880 return rval;
4881
4882 /* Forcefully perform IDC UnLock */
4883 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4884 &data);
4885 if (rval)
4886 return rval;
4887 /* Clear lock-id by setting 0xff */
4888 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4889 0xff);
4890 if (rval)
4891 return rval;
4892 /* Clear lock-recovery by setting 0x0 */
4893 rval = qla83xx_wr_reg(base_vha,
4894 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4895 if (rval)
4896 return rval;
4897 } else
4898 return QLA_SUCCESS;
4899 }
4900
4901 return rval;
4902}
4903
fa492630 4904static int
7d613ac6
SV		 4905qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4906{
4907 int rval = QLA_SUCCESS;
4908 uint32_t o_drv_lockid, n_drv_lockid;
4909 unsigned long lock_recovery_timeout;
4910
4911 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4912retry_lockid:
4913 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4914 if (rval)
4915 goto exit;
4916
4917 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4918 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4919 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4920 return QLA_SUCCESS;
4921 else
4922 return QLA_FUNCTION_FAILED;
4923 }
4924
4925 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4926 if (rval)
4927 goto exit;
4928
4929 if (o_drv_lockid == n_drv_lockid) {
4930 qla83xx_wait_logic();
4931 goto retry_lockid;
4932 } else
4933 return QLA_SUCCESS;
4934
4935exit:
4936 return rval;
4937}
4938
4939void
4940qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4941{
4942 uint16_t options = (requester_id << 15) | BIT_6;
4943 uint32_t data;
6c315553 4944 uint32_t lock_owner;
7d613ac6
SV		 4945 struct qla_hw_data *ha = base_vha->hw;
4946
4947 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4948retry_lock:
4949 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4950 == QLA_SUCCESS) {
4951 if (data) {
4952 /* Setting lock-id to our function-number */
4953 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4954 ha->portnum);
4955 } else {
6c315553
SK		 4956 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4957 &lock_owner);
7d613ac6 4958 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4959 "Failed to acquire IDC lock, acquired by %d, "
4960 "retrying...\n", lock_owner);
7d613ac6
SV		 4961
4962 /* Retry/Perform IDC-Lock recovery */
4963 if (qla83xx_idc_lock_recovery(base_vha)
4964 == QLA_SUCCESS) {
4965 qla83xx_wait_logic();
4966 goto retry_lock;
4967 } else
4968 ql_log(ql_log_warn, base_vha, 0xb075,
4969 "IDC Lock recovery FAILED.\n");
4970 }
4971
4972 }
4973
4974 return;
4975
4976 /* XXX: IDC-lock implementation using access-control mbx */
4977retry_lock2:
4978 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4979 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4980 "Failed to acquire IDC lock. retrying...\n");
4981 /* Retry/Perform IDC-Lock recovery */
4982 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4983 qla83xx_wait_logic();
4984 goto retry_lock2;
4985 } else
4986 ql_log(ql_log_warn, base_vha, 0xb076,
4987 "IDC Lock recovery FAILED.\n");
4988 }
4989
4990 return;
4991}
4992
4993void
4994qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4995{
5897cb2f
BVA		 4996#if 0
4997 uint16_t options = (requester_id << 15) | BIT_7;
4998#endif
4999 uint16_t retry;
7d613ac6
SV		 5000 uint32_t data;
5001 struct qla_hw_data *ha = base_vha->hw;
5002
5003 /* IDC-unlock implementation using driver-unlock/lock-id
5004 * remote registers
5005 */
5006 retry = 0;
5007retry_unlock:
5008 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5009 == QLA_SUCCESS) {
5010 if (data == ha->portnum) {
5011 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5012 /* Clearing lock-id by setting 0xff */
5013 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5014 } else if (retry < 10) {
5015 /* SV: XXX: IDC unlock retrying needed here? */
5016
5017 /* Retry for IDC-unlock */
5018 qla83xx_wait_logic();
5019 retry++;
5020 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5021 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5022 goto retry_unlock;
5023 }
5024 } else if (retry < 10) {
5025 /* Retry for IDC-unlock */
5026 qla83xx_wait_logic();
5027 retry++;
5028 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5029 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5030 goto retry_unlock;
5031 }
5032
5033 return;
5034
5897cb2f 5035#if 0
7d613ac6
SV		 5036 /* XXX: IDC-unlock implementation using access-control mbx */
5037 retry = 0;
5038retry_unlock2:
5039 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5040 if (retry < 10) {
5041 /* Retry for IDC-unlock */
5042 qla83xx_wait_logic();
5043 retry++;
5044 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5045 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5046 goto retry_unlock2;
5047 }
5048 }
5049
5050 return;
5897cb2f 5051#endif
7d613ac6
SV		 5052}
5053
5054int
5055__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5056{
5057 int rval = QLA_SUCCESS;
5058 struct qla_hw_data *ha = vha->hw;
5059 uint32_t drv_presence;
5060
5061 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5062 if (rval == QLA_SUCCESS) {
5063 drv_presence |= (1 << ha->portnum);
5064 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5065 drv_presence);
5066 }
5067
5068 return rval;
5069}
5070
5071int
5072qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5073{
5074 int rval = QLA_SUCCESS;
5075
5076 qla83xx_idc_lock(vha, 0);
5077 rval = __qla83xx_set_drv_presence(vha);
5078 qla83xx_idc_unlock(vha, 0);
5079
5080 return rval;
5081}
5082
5083int
5084__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5085{
5086 int rval = QLA_SUCCESS;
5087 struct qla_hw_data *ha = vha->hw;
5088 uint32_t drv_presence;
5089
5090 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5091 if (rval == QLA_SUCCESS) {
5092 drv_presence &= ~(1 << ha->portnum);
5093 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5094 drv_presence);
5095 }
5096
5097 return rval;
5098}
5099
5100int
5101qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5102{
5103 int rval = QLA_SUCCESS;
5104
5105 qla83xx_idc_lock(vha, 0);
5106 rval = __qla83xx_clear_drv_presence(vha);
5107 qla83xx_idc_unlock(vha, 0);
5108
5109 return rval;
5110}
5111
fa492630 5112static void
7d613ac6
SV		 5113qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5114{
5115 struct qla_hw_data *ha = vha->hw;
5116 uint32_t drv_ack, drv_presence;
5117 unsigned long ack_timeout;
5118
5119 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5120 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5121 while (1) {
5122 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5123 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5124 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5125 break;
5126
5127 if (time_after_eq(jiffies, ack_timeout)) {
5128 ql_log(ql_log_warn, vha, 0xb067,
5129 "RESET ACK TIMEOUT! drv_presence=0x%x "
5130 "drv_ack=0x%x\n", drv_presence, drv_ack);
5131 /*
5132 * The function(s) which did not ack in time are forced
5133 * to withdraw any further participation in the IDC
5134 * reset.
5135 */
5136 if (drv_ack != drv_presence)
5137 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5138 drv_ack);
5139 break;
5140 }
5141
5142 qla83xx_idc_unlock(vha, 0);
5143 msleep(1000);
5144 qla83xx_idc_lock(vha, 0);
5145 }
5146
5147 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5148 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5149}
5150
fa492630 5151static int
7d613ac6
SV		 5152qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5153{
5154 int rval = QLA_SUCCESS;
5155 uint32_t idc_control;
5156
5157 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5158 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5159
5160 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5161 __qla83xx_get_idc_control(vha, &idc_control);
5162 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5163 __qla83xx_set_idc_control(vha, 0);
5164
5165 qla83xx_idc_unlock(vha, 0);
5166 rval = qla83xx_restart_nic_firmware(vha);
5167 qla83xx_idc_lock(vha, 0);
5168
5169 if (rval != QLA_SUCCESS) {
5170 ql_log(ql_log_fatal, vha, 0xb06a,
5171 "Failed to restart NIC f/w.\n");
5172 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5173 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5174 } else {
5175 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5176 "Success in restarting nic f/w.\n");
5177 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5178 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5179 }
5180
5181 return rval;
5182}
5183
5184/* Assumes idc_lock always held on entry */
5185int
5186qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5187{
5188 struct qla_hw_data *ha = base_vha->hw;
5189 int rval = QLA_SUCCESS;
5190 unsigned long dev_init_timeout;
5191 uint32_t dev_state;
5192
5193 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5194 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5195
5196 while (1) {
5197
5198 if (time_after_eq(jiffies, dev_init_timeout)) {
5199 ql_log(ql_log_warn, base_vha, 0xb06e,
5200 "Initialization TIMEOUT!\n");
5201 /* Init timeout. Disable further NIC Core
5202 * communication.
5203 */
5204 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5205 QLA8XXX_DEV_FAILED);
5206 ql_log(ql_log_info, base_vha, 0xb06f,
5207 "HW State: FAILED.\n");
5208 }
5209
5210 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5211 switch (dev_state) {
5212 case QLA8XXX_DEV_READY:
5213 if (ha->flags.nic_core_reset_owner)
5214 qla83xx_idc_audit(base_vha,
5215 IDC_AUDIT_COMPLETION);
5216 ha->flags.nic_core_reset_owner = 0;
5217 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5218 "Reset_owner reset by 0x%x.\n",
5219 ha->portnum);
5220 goto exit;
5221 case QLA8XXX_DEV_COLD:
5222 if (ha->flags.nic_core_reset_owner)
5223 rval = qla83xx_device_bootstrap(base_vha);
5224 else {
5225 /* Wait for AEN to change device-state */
5226 qla83xx_idc_unlock(base_vha, 0);
5227 msleep(1000);
5228 qla83xx_idc_lock(base_vha, 0);
5229 }
5230 break;
5231 case QLA8XXX_DEV_INITIALIZING:
5232 /* Wait for AEN to change device-state */
5233 qla83xx_idc_unlock(base_vha, 0);
5234 msleep(1000);
5235 qla83xx_idc_lock(base_vha, 0);
5236 break;
5237 case QLA8XXX_DEV_NEED_RESET:
5238 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5239 qla83xx_need_reset_handler(base_vha);
5240 else {
5241 /* Wait for AEN to change device-state */
5242 qla83xx_idc_unlock(base_vha, 0);
5243 msleep(1000);
5244 qla83xx_idc_lock(base_vha, 0);
5245 }
5246 /* reset timeout value after need reset handler */
5247 dev_init_timeout = jiffies +
5248 (ha->fcoe_dev_init_timeout * HZ);
5249 break;
5250 case QLA8XXX_DEV_NEED_QUIESCENT:
5251 /* XXX: DEBUG for now */
5252 qla83xx_idc_unlock(base_vha, 0);
5253 msleep(1000);
5254 qla83xx_idc_lock(base_vha, 0);
5255 break;
5256 case QLA8XXX_DEV_QUIESCENT:
5257 /* XXX: DEBUG for now */
5258 if (ha->flags.quiesce_owner)
5259 goto exit;
5260
5261 qla83xx_idc_unlock(base_vha, 0);
5262 msleep(1000);
5263 qla83xx_idc_lock(base_vha, 0);
5264 dev_init_timeout = jiffies +
5265 (ha->fcoe_dev_init_timeout * HZ);
5266 break;
5267 case QLA8XXX_DEV_FAILED:
5268 if (ha->flags.nic_core_reset_owner)
5269 qla83xx_idc_audit(base_vha,
5270 IDC_AUDIT_COMPLETION);
5271 ha->flags.nic_core_reset_owner = 0;
5272 __qla83xx_clear_drv_presence(base_vha);
5273 qla83xx_idc_unlock(base_vha, 0);
5274 qla8xxx_dev_failed_handler(base_vha);
5275 rval = QLA_FUNCTION_FAILED;
5276 qla83xx_idc_lock(base_vha, 0);
5277 goto exit;
5278 case QLA8XXX_BAD_VALUE:
5279 qla83xx_idc_unlock(base_vha, 0);
5280 msleep(1000);
5281 qla83xx_idc_lock(base_vha, 0);
5282 break;
5283 default:
5284 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5285 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5286 qla83xx_idc_unlock(base_vha, 0);
5287 qla8xxx_dev_failed_handler(base_vha);
5288 rval = QLA_FUNCTION_FAILED;
5289 qla83xx_idc_lock(base_vha, 0);
5290 goto exit;
5291 }
5292 }
5293
5294exit:
5295 return rval;
5296}
5297
f3ddac19
CD		 5298void
5299qla2x00_disable_board_on_pci_error(struct work_struct *work)
5300{
5301 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5302 board_disable);
5303 struct pci_dev *pdev = ha->pdev;
5304 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5305
726b8548
QT		 5306 /*
5307 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5308 * where it was set first.
5309 */
5310 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5311 return;
5312
f3ddac19
CD		 5313 ql_log(ql_log_warn, base_vha, 0x015b,
5314 "Disabling adapter.\n");
5315
726b8548
QT		 5316 qla2x00_wait_for_sess_deletion(base_vha);
5317
f3ddac19
CD		 5318 set_bit(UNLOADING, &base_vha->dpc_flags);
5319
5320 qla2x00_delete_all_vps(ha, base_vha);
5321
5322 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5323
5324 qla2x00_dfs_remove(base_vha);
5325
5326 qla84xx_put_chip(base_vha);
5327
5328 if (base_vha->timer_active)
5329 qla2x00_stop_timer(base_vha);
5330
5331 base_vha->flags.online = 0;
5332
5333 qla2x00_destroy_deferred_work(ha);
5334
5335 /*
5336 * Do not try to stop beacon blink as it will issue a mailbox
5337 * command.
5338 */
5339 qla2x00_free_sysfs_attr(base_vha, false);
5340
5341 fc_remove_host(base_vha->host);
5342
5343 scsi_remove_host(base_vha->host);
5344
5345 base_vha->flags.init_done = 0;
5346 qla25xx_delete_queues(base_vha);
f3ddac19 5347 qla2x00_free_fcports(base_vha);
093df737 5348 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5349 qla2x00_mem_free(ha);
5350 qla82xx_md_free(base_vha);
5351 qla2x00_free_queues(ha);
5352
f3ddac19
CD		 5353 qla2x00_unmap_iobases(ha);
5354
5355 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5356 pci_disable_pcie_error_reporting(pdev);
5357 pci_disable_device(pdev);
f3ddac19 5358
beb9e315
JL		 5359 /*
5360 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5361 */
f3ddac19
CD		 5362}
5363
1da177e4
LT		 5364/**************************************************************************
5365* qla2x00_do_dpc
5366* This kernel thread is a task that is schedule by the interrupt handler
5367* to perform the background processing for interrupts.
5368*
5369* Notes:
5370* This task always run in the context of a kernel thread. It
5371* is kick-off by the driver's detect code and starts up
5372* up one per adapter. It immediately goes to sleep and waits for
5373* some fibre event. When either the interrupt handler or
5374* the timer routine detects a event it will one of the task
5375* bits then wake us up.
5376**************************************************************************/
5377static int
5378qla2x00_do_dpc(void *data)
5379{
e315cd28
AC		 5380 scsi_qla_host_t *base_vha;
5381 struct qla_hw_data *ha;
d7459527
MH		 5382 uint32_t online;
5383 struct qla_qpair *qpair;
1da177e4 5384
e315cd28
AC		 5385 ha = (struct qla_hw_data *)data;
5386 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5387
8698a745 5388 set_user_nice(current, MIN_NICE);
1da177e4 5389
563585ec 5390 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5391 while (!kthread_should_stop()) {
7c3df132
SK		 5392 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5393 "DPC handler sleeping.\n");
1da177e4 5394
39a11240 5395 schedule();
1da177e4 5396
c142caf0
AV		 5397 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5398 goto end_loop;
1da177e4 5399
85880801 5400 if (ha->flags.eeh_busy) {
7c3df132
SK		 5401 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5402 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5403 goto end_loop;
85880801
AV		 5404 }
5405
1da177e4
LT		 5406 ha->dpc_active = 1;
5407
5f28d2d7
SK		 5408 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5409 "DPC handler waking up, dpc_flags=0x%lx.\n",
5410 base_vha->dpc_flags);
1da177e4 5411
a29b3dd7
JC		 5412 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5413 break;
5414
e315cd28 5415 qla2x00_do_work(base_vha);
0971de7f 5416
7ec0effd
AD		 5417 if (IS_P3P_TYPE(ha)) {
5418 if (IS_QLA8044(ha)) {
5419 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5420 &base_vha->dpc_flags)) {
5421 qla8044_idc_lock(ha);
5422 qla8044_wr_direct(base_vha,
5423 QLA8044_CRB_DEV_STATE_INDEX,
5424 QLA8XXX_DEV_FAILED);
5425 qla8044_idc_unlock(ha);
5426 ql_log(ql_log_info, base_vha, 0x4004,
5427 "HW State: FAILED.\n");
5428 qla8044_device_state_handler(base_vha);
5429 continue;
5430 }
5431
5432 } else {
5433 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5434 &base_vha->dpc_flags)) {
5435 qla82xx_idc_lock(ha);
5436 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5437 QLA8XXX_DEV_FAILED);
5438 qla82xx_idc_unlock(ha);
5439 ql_log(ql_log_info, base_vha, 0x0151,
5440 "HW State: FAILED.\n");
5441 qla82xx_device_state_handler(base_vha);
5442 continue;
5443 }
a9083016
GM		 5444 }
5445
5446 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5447 &base_vha->dpc_flags)) {
5448
7c3df132
SK		 5449 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5450 "FCoE context reset scheduled.\n");
a9083016
GM		 5451 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5452 &base_vha->dpc_flags))) {
5453 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5454 /* FCoE-ctx reset failed.
5455 * Escalate to chip-reset
5456 */
5457 set_bit(ISP_ABORT_NEEDED,
5458 &base_vha->dpc_flags);
5459 }
5460 clear_bit(ABORT_ISP_ACTIVE,
5461 &base_vha->dpc_flags);
5462 }
5463
7c3df132
SK		 5464 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5465 "FCoE context reset end.\n");
a9083016 5466 }
8ae6d9c7
GM		 5467 } else if (IS_QLAFX00(ha)) {
5468 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5469 &base_vha->dpc_flags)) {
5470 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5471 "Firmware Reset Recovery\n");
5472 if (qlafx00_reset_initialize(base_vha)) {
5473 /* Failed. Abort isp later. */
5474 if (!test_bit(UNLOADING,
f92f82d6 5475 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5476 set_bit(ISP_UNRECOVERABLE,
5477 &base_vha->dpc_flags);
5478 ql_dbg(ql_dbg_dpc, base_vha,
5479 0x4021,
5480 "Reset Recovery Failed\n");
f92f82d6 5481 }
8ae6d9c7
GM		 5482 }
5483 }
5484
5485 if (test_and_clear_bit(FX00_TARGET_SCAN,
5486 &base_vha->dpc_flags)) {
5487 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5488 "ISPFx00 Target Scan scheduled\n");
5489 if (qlafx00_rescan_isp(base_vha)) {
5490 if (!test_bit(UNLOADING,
5491 &base_vha->dpc_flags))
5492 set_bit(ISP_UNRECOVERABLE,
5493 &base_vha->dpc_flags);
5494 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5495 "ISPFx00 Target Scan Failed\n");
5496 }
5497 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5498 "ISPFx00 Target Scan End\n");
5499 }
e8f5e95d
AB		 5500 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5501 &base_vha->dpc_flags)) {
5502 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5503 "ISPFx00 Host Info resend scheduled\n");
5504 qlafx00_fx_disc(base_vha,
5505 &base_vha->hw->mr.fcport,
5506 FXDISC_REG_HOST_INFO);
5507 }
a9083016
GM		 5508 }
5509
e315cd28
AC		 5510 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5511 &base_vha->dpc_flags)) {
1da177e4 5512
7c3df132
SK		 5513 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5514 "ISP abort scheduled.\n");
1da177e4 5515 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5516 &base_vha->dpc_flags))) {
1da177e4 5517
a9083016 5518 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5519 /* failed. retry later */
5520 set_bit(ISP_ABORT_NEEDED,
e315cd28 5521 &base_vha->dpc_flags);
99363ef8 5522 }
e315cd28
AC		 5523 clear_bit(ABORT_ISP_ACTIVE,
5524 &base_vha->dpc_flags);
99363ef8
SJ		 5525 }
5526
7c3df132
SK		 5527 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5528 "ISP abort end.\n");
1da177e4
LT		 5529 }
5530
a394aac8
DJ		 5531 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5532 &base_vha->dpc_flags)) {
e315cd28 5533 qla2x00_update_fcports(base_vha);
c9c5ced9 5534 }
d97994dc 5535
8ae6d9c7
GM		 5536 if (IS_QLAFX00(ha))
5537 goto loop_resync_check;
5538
579d12b5 5539 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5540 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5541 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5542 if (IS_P3P_TYPE(ha)) {
5543 if (IS_QLA82XX(ha))
5544 qla82xx_device_state_handler(base_vha);
5545 if (IS_QLA8044(ha))
5546 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5547 clear_bit(ISP_QUIESCE_NEEDED,
5548 &base_vha->dpc_flags);
5549 if (!ha->flags.quiesce_owner) {
5550 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5551 if (IS_QLA82XX(ha)) {
5552 qla82xx_idc_lock(ha);
5553 qla82xx_clear_qsnt_ready(
5554 base_vha);
5555 qla82xx_idc_unlock(ha);
5556 } else if (IS_QLA8044(ha)) {
5557 qla8044_idc_lock(ha);
5558 qla8044_clear_qsnt_ready(
5559 base_vha);
5560 qla8044_idc_unlock(ha);
5561 }
8fcd6b8b
CD		 5562 }
5563 } else {
5564 clear_bit(ISP_QUIESCE_NEEDED,
5565 &base_vha->dpc_flags);
5566 qla2x00_quiesce_io(base_vha);
579d12b5 5567 }
7c3df132
SK		 5568 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5569 "Quiescence mode end.\n");
579d12b5
SK		 5570 }
5571
e315cd28 5572 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5573 &base_vha->dpc_flags) &&
e315cd28 5574 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5575
7c3df132
SK		 5576 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5577 "Reset marker scheduled.\n");
e315cd28
AC		 5578 qla2x00_rst_aen(base_vha);
5579 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5580 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5581 "Reset marker end.\n");
1da177e4
LT		 5582 }
5583
5584 /* Retry each device up to login retry count */
e315cd28
AC		 5585 if ((test_and_clear_bit(RELOGIN_NEEDED,
5586 &base_vha->dpc_flags)) &&
5587 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5588 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5589
7c3df132
SK		 5590 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5591 "Relogin scheduled.\n");
e315cd28 5592 qla2x00_relogin(base_vha);
7c3df132
SK		 5593 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5594 "Relogin end.\n");
1da177e4 5595 }
8ae6d9c7 5596loop_resync_check:
e315cd28 5597 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5598 &base_vha->dpc_flags)) {
1da177e4 5599
7c3df132
SK		 5600 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5601 "Loop resync scheduled.\n");
1da177e4
LT		 5602
5603 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5604 &base_vha->dpc_flags))) {
1da177e4 5605
52c82823 5606 qla2x00_loop_resync(base_vha);
1da177e4 5607
e315cd28
AC		 5608 clear_bit(LOOP_RESYNC_ACTIVE,
5609 &base_vha->dpc_flags);
1da177e4
LT		 5610 }
5611
7c3df132
SK		 5612 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5613 "Loop resync end.\n");
1da177e4
LT		 5614 }
5615
8ae6d9c7
GM		 5616 if (IS_QLAFX00(ha))
5617 goto intr_on_check;
5618
e315cd28
AC		 5619 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5620 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5621 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5622 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5623 }
5624
8ae6d9c7 5625intr_on_check:
1da177e4 5626 if (!ha->interrupts_on)
fd34f556 5627 ha->isp_ops->enable_intrs(ha);
1da177e4 5628
e315cd28 5629 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5630 &base_vha->dpc_flags)) {
5631 if (ha->beacon_blink_led == 1)
5632 ha->isp_ops->beacon_blink(base_vha);
5633 }
f6df144c 5634
d7459527
MH		 5635 /* qpair online check */
5636 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5637 &base_vha->dpc_flags)) {
5638 if (ha->flags.eeh_busy ||
5639 ha->flags.pci_channel_io_perm_failure)
5640 online = 0;
5641 else
5642 online = 1;
5643
5644 mutex_lock(&ha->mq_lock);
5645 list_for_each_entry(qpair, &base_vha->qp_list,
5646 qp_list_elem)
5647 qpair->online = online;
5648 mutex_unlock(&ha->mq_lock);
5649 }
5650
8ae6d9c7
GM		 5651 if (!IS_QLAFX00(ha))
5652 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5653
1da177e4 5654 ha->dpc_active = 0;
c142caf0 5655end_loop:
563585ec 5656 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5657 } /* End of while(1) */
563585ec 5658 __set_current_state(TASK_RUNNING);
1da177e4 5659
7c3df132
SK		 5660 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5661 "DPC handler exiting.\n");
1da177e4
LT		 5662
5663 /*
5664 * Make sure that nobody tries to wake us up again.
5665 */
1da177e4
LT		 5666 ha->dpc_active = 0;
5667
ac280b67
AV		 5668 /* Cleanup any residual CTX SRBs. */
5669 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5670
39a11240
CH		 5671 return 0;
5672}
5673
5674void
e315cd28 5675qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5676{
e315cd28 5677 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5678 struct task_struct *t = ha->dpc_thread;
5679
e315cd28 5680 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5681 wake_up_process(t);
1da177e4
LT		 5682}
5683
1da177e4
LT		 5684/*
5685* qla2x00_rst_aen
5686* Processes asynchronous reset.
5687*
5688* Input:
5689* ha = adapter block pointer.
5690*/
5691static void
e315cd28 5692qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5693{
e315cd28
AC		 5694 if (vha->flags.online && !vha->flags.reset_active &&
5695 !atomic_read(&vha->loop_down_timer) &&
5696 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5697 do {
e315cd28 5698 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5699
5700 /*
5701 * Issue marker command only when we are going to start
5702 * the I/O.
5703 */
e315cd28
AC		 5704 vha->marker_needed = 1;
5705 } while (!atomic_read(&vha->loop_down_timer) &&
5706 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5707 }
5708}
5709
1da177e4
LT		 5710/**************************************************************************
5711* qla2x00_timer
5712*
5713* Description:
5714* One second timer
5715*
5716* Context: Interrupt
5717***************************************************************************/
2c3dfe3f 5718void
e315cd28 5719qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5720{
1da177e4 5721 unsigned long cpu_flags = 0;
1da177e4
LT		 5722 int start_dpc = 0;
5723 int index;
5724 srb_t *sp;
85880801 5725 uint16_t w;
e315cd28 5726 struct qla_hw_data *ha = vha->hw;
73208dfd 5727 struct req_que *req;
85880801 5728
a5b36321 5729 if (ha->flags.eeh_busy) {
7c3df132
SK		 5730 ql_dbg(ql_dbg_timer, vha, 0x6000,
5731 "EEH = %d, restarting timer.\n",
5732 ha->flags.eeh_busy);
a5b36321
LC		 5733 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5734 return;
5735 }
5736
f3ddac19
CD		 5737 /*
5738 * Hardware read to raise pending EEH errors during mailbox waits. If
5739 * the read returns -1 then disable the board.
5740 */
5741 if (!pci_channel_offline(ha->pdev)) {
85880801 5742 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5743 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5744 }
1da177e4 5745
cefcaba6 5746 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5747 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5748 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5749 start_dpc++;
7ec0effd
AD		 5750 if (IS_QLA82XX(ha))
5751 qla82xx_watchdog(vha);
5752 else if (IS_QLA8044(ha))
5753 qla8044_watchdog(vha);
579d12b5
SK		 5754 }
5755
8ae6d9c7
GM		 5756 if (!vha->vp_idx && IS_QLAFX00(ha))
5757 qlafx00_timer_routine(vha);
5758
1da177e4 5759 /* Loop down handler. */
e315cd28 5760 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5761 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5762 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5763 && vha->flags.online) {
1da177e4 5764
e315cd28
AC		 5765 if (atomic_read(&vha->loop_down_timer) ==
5766 vha->loop_down_abort_time) {
1da177e4 5767
7c3df132
SK		 5768 ql_log(ql_log_info, vha, 0x6008,
5769 "Loop down - aborting the queues before time expires.\n");
1da177e4 5770
e315cd28
AC		 5771 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5772 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5773
f08b7251
AV		 5774 /*
5775 * Schedule an ISP abort to return any FCP2-device
5776 * commands.
5777 */
2c3dfe3f 5778 /* NPIV - scan physical port only */
e315cd28 5779 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5780 spin_lock_irqsave(&ha->hardware_lock,
5781 cpu_flags);
73208dfd 5782 req = ha->req_q_map[0];
2c3dfe3f 5783 for (index = 1;
8d93f550 5784 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5785 index++) {
5786 fc_port_t *sfcp;
5787
e315cd28 5788 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5789 if (!sp)
5790 continue;
9ba56b95 5791 if (sp->type != SRB_SCSI_CMD)
cf53b069 5792 continue;
2c3dfe3f 5793 sfcp = sp->fcport;
f08b7251 5794 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5795 continue;
bdf79621 5796
8f7daead
GM		 5797 if (IS_QLA82XX(ha))
5798 set_bit(FCOE_CTX_RESET_NEEDED,
5799 &vha->dpc_flags);
5800 else
5801 set_bit(ISP_ABORT_NEEDED,
e315cd28 5802 &vha->dpc_flags);
2c3dfe3f
SJ		 5803 break;
5804 }
5805 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5806 cpu_flags);
1da177e4 5807 }
1da177e4
LT		 5808 start_dpc++;
5809 }
5810
5811 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5812 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5813 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5814 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5815 "Loop down - aborting ISP.\n");
5816
8f7daead
GM		 5817 if (IS_QLA82XX(ha))
5818 set_bit(FCOE_CTX_RESET_NEEDED,
5819 &vha->dpc_flags);
5820 else
5821 set_bit(ISP_ABORT_NEEDED,
5822 &vha->dpc_flags);
1da177e4
LT		 5823 }
5824 }
7c3df132
SK		 5825 ql_dbg(ql_dbg_timer, vha, 0x600a,
5826 "Loop down - seconds remaining %d.\n",
5827 atomic_read(&vha->loop_down_timer));
1da177e4 5828 }
cefcaba6
SK		 5829 /* Check if beacon LED needs to be blinked for physical host only */
5830 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5831 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5832 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5833 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5834 start_dpc++;
5835 }
f6df144c
AV		 5836 }
5837
550bf57d 5838 /* Process any deferred work. */
e315cd28 5839 if (!list_empty(&vha->work_list))
550bf57d
AV		 5840 start_dpc++;
5841
1da177e4 5842 /* Schedule the DPC routine if needed */
e315cd28
AC		 5843 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5844 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5845 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5846 start_dpc ||
e315cd28
AC		 5847 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5848 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5849 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5850 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5851 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5852 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5853 ql_dbg(ql_dbg_timer, vha, 0x600b,
5854 "isp_abort_needed=%d loop_resync_needed=%d "
5855 "fcport_update_needed=%d start_dpc=%d "
5856 "reset_marker_needed=%d",
5857 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5858 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5859 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5860 start_dpc,
5861 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5862 ql_dbg(ql_dbg_timer, vha, 0x600c,
5863 "beacon_blink_needed=%d isp_unrecoverable=%d "
5864 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5865 "relogin_needed=%d.\n",
7c3df132
SK		 5866 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5867 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5868 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5869 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5870 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5871 qla2xxx_wake_dpc(vha);
7c3df132 5872 }
1da177e4 5873
e315cd28 5874 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5875}
5876
5433383e
AV		 5877/* Firmware interface routines. */
5878
f73cb695 5879#define FW_BLOBS 11
5433383e
AV		 5880#define FW_ISP21XX 0
5881#define FW_ISP22XX 1
5882#define FW_ISP2300 2
5883#define FW_ISP2322 3
48c02fde 5884#define FW_ISP24XX 4
c3a2f0df 5885#define FW_ISP25XX 5
3a03eb79 5886#define FW_ISP81XX 6
a9083016 5887#define FW_ISP82XX 7
6246b8a1
GM		 5888#define FW_ISP2031 8
5889#define FW_ISP8031 9
2c5bbbb2 5890#define FW_ISP27XX 10
5433383e 5891
bb8ee499
AV		 5892#define FW_FILE_ISP21XX "ql2100_fw.bin"
5893#define FW_FILE_ISP22XX "ql2200_fw.bin"
5894#define FW_FILE_ISP2300 "ql2300_fw.bin"
5895#define FW_FILE_ISP2322 "ql2322_fw.bin"
5896#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5897#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5898#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5899#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5900#define FW_FILE_ISP2031 "ql2600_fw.bin"
5901#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5902#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5903
bb8ee499 5904
e1e82b6f 5905static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5906
5907static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5908 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5909 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5910 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5911 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5912 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5913 { .name = FW_FILE_ISP25XX, },
3a03eb79 5914 { .name = FW_FILE_ISP81XX, },
a9083016 5915 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5916 { .name = FW_FILE_ISP2031, },
5917 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5918 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5919};
5920
5921struct fw_blob *
e315cd28 5922qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5923{
e315cd28 5924 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5925 struct fw_blob *blob;
5926
5433383e
AV		 5927 if (IS_QLA2100(ha)) {
5928 blob = &qla_fw_blobs[FW_ISP21XX];
5929 } else if (IS_QLA2200(ha)) {
5930 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5931 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5932 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5933 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5934 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5935 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5936 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5937 } else if (IS_QLA25XX(ha)) {
5938 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5939 } else if (IS_QLA81XX(ha)) {
5940 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5941 } else if (IS_QLA82XX(ha)) {
5942 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5943 } else if (IS_QLA2031(ha)) {
5944 blob = &qla_fw_blobs[FW_ISP2031];
5945 } else if (IS_QLA8031(ha)) {
5946 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5947 } else if (IS_QLA27XX(ha)) {
5948 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5949 } else {
5950 return NULL;
5433383e
AV		 5951 }
5952
e1e82b6f 5953 mutex_lock(&qla_fw_lock);
5433383e
AV		 5954 if (blob->fw)
5955 goto out;
5956
5957 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5958 ql_log(ql_log_warn, vha, 0x0063,
5959 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5960 blob->fw = NULL;
5961 blob = NULL;
5962 goto out;
5963 }
5964
5965out:
e1e82b6f 5966 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5967 return blob;
5968}
5969
5970static void
5971qla2x00_release_firmware(void)
5972{
5973 int idx;
5974
e1e82b6f 5975 mutex_lock(&qla_fw_lock);
5433383e 5976 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5977 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5978 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5979}
5980
14e660e6
SJ		 5981static pci_ers_result_t
5982qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5983{
85880801
AV		 5984 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5985 struct qla_hw_data *ha = vha->hw;
5986
7c3df132
SK		 5987 ql_dbg(ql_dbg_aer, vha, 0x9000,
5988 "PCI error detected, state %x.\n", state);
b9b12f73 5989
14e660e6
SJ		 5990 switch (state) {
5991 case pci_channel_io_normal:
85880801 5992 ha->flags.eeh_busy = 0;
d7459527
MH		 5993 if (ql2xmqsupport) {
5994 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5995 qla2xxx_wake_dpc(vha);
5996 }
14e660e6
SJ		 5997 return PCI_ERS_RESULT_CAN_RECOVER;
5998 case pci_channel_io_frozen:
85880801 5999 ha->flags.eeh_busy = 1;
a5b36321
LC		 6000 /* For ISP82XX complete any pending mailbox cmd */
6001 if (IS_QLA82XX(ha)) {
7190575f 6002 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6003 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6004 qla82xx_clear_pending_mbx(vha);
a5b36321 6005 }
90a86fc0 6006 qla2x00_free_irqs(vha);
14e660e6 6007 pci_disable_device(pdev);
bddd2d65
LC		 6008 /* Return back all IOs */
6009 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6010 if (ql2xmqsupport) {
6011 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6012 qla2xxx_wake_dpc(vha);
6013 }
14e660e6
SJ		 6014 return PCI_ERS_RESULT_NEED_RESET;
6015 case pci_channel_io_perm_failure:
85880801
AV		 6016 ha->flags.pci_channel_io_perm_failure = 1;
6017 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6018 if (ql2xmqsupport) {
6019 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6020 qla2xxx_wake_dpc(vha);
6021 }
14e660e6
SJ		 6022 return PCI_ERS_RESULT_DISCONNECT;
6023 }
6024 return PCI_ERS_RESULT_NEED_RESET;
6025}
6026
6027static pci_ers_result_t
6028qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6029{
6030 int risc_paused = 0;
6031 uint32_t stat;
6032 unsigned long flags;
e315cd28
AC		 6033 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6034 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6035 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6036 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6037
bcc5b6d3
SK		 6038 if (IS_QLA82XX(ha))
6039 return PCI_ERS_RESULT_RECOVERED;
6040
14e660e6
SJ		 6041 spin_lock_irqsave(&ha->hardware_lock, flags);
6042 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6043 stat = RD_REG_DWORD(&reg->hccr);
6044 if (stat & HCCR_RISC_PAUSE)
6045 risc_paused = 1;
6046 } else if (IS_QLA23XX(ha)) {
6047 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6048 if (stat & HSR_RISC_PAUSED)
6049 risc_paused = 1;
6050 } else if (IS_FWI2_CAPABLE(ha)) {
6051 stat = RD_REG_DWORD(&reg24->host_status);
6052 if (stat & HSRX_RISC_PAUSED)
6053 risc_paused = 1;
6054 }
6055 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6056
6057 if (risc_paused) {
7c3df132
SK		 6058 ql_log(ql_log_info, base_vha, 0x9003,
6059 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6060 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6061
6062 return PCI_ERS_RESULT_NEED_RESET;
6063 } else
6064 return PCI_ERS_RESULT_RECOVERED;
6065}
6066
fa492630
SK		 6067static uint32_t
6068qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6069{
6070 uint32_t rval = QLA_FUNCTION_FAILED;
6071 uint32_t drv_active = 0;
6072 struct qla_hw_data *ha = base_vha->hw;
6073 int fn;
6074 struct pci_dev *other_pdev = NULL;
6075
7c3df132
SK		 6076 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6077 "Entered %s.\n", __func__);
a5b36321
LC		 6078
6079 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6080
6081 if (base_vha->flags.online) {
6082 /* Abort all outstanding commands,
6083 * so as to be requeued later */
6084 qla2x00_abort_isp_cleanup(base_vha);
6085 }
6086
6087
6088 fn = PCI_FUNC(ha->pdev->devfn);
6089 while (fn > 0) {
6090 fn--;
7c3df132
SK		 6091 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6092 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6093 other_pdev =
6094 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6095 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6096 fn));
6097
6098 if (!other_pdev)
6099 continue;
6100 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6101 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6102 "Found PCI func available and enable at 0x%x.\n",
6103 fn);
a5b36321
LC		 6104 pci_dev_put(other_pdev);
6105 break;
6106 }
6107 pci_dev_put(other_pdev);
6108 }
6109
6110 if (!fn) {
6111 /* Reset owner */
7c3df132
SK		 6112 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6113 "This devfn is reset owner = 0x%x.\n",
6114 ha->pdev->devfn);
a5b36321
LC		 6115 qla82xx_idc_lock(ha);
6116
6117 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6118 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6119
6120 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6121 QLA82XX_IDC_VERSION);
6122
6123 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6124 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6125 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6126
6127 qla82xx_idc_unlock(ha);
6128 /* Reset if device is not already reset
6129 * drv_active would be 0 if a reset has already been done
6130 */
6131 if (drv_active)
6132 rval = qla82xx_start_firmware(base_vha);
6133 else
6134 rval = QLA_SUCCESS;
6135 qla82xx_idc_lock(ha);
6136
6137 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6138 ql_log(ql_log_info, base_vha, 0x900b,
6139 "HW State: FAILED.\n");
a5b36321
LC		 6140 qla82xx_clear_drv_active(ha);
6141 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6142 QLA8XXX_DEV_FAILED);
a5b36321 6143 } else {
7c3df132
SK		 6144 ql_log(ql_log_info, base_vha, 0x900c,
6145 "HW State: READY.\n");
a5b36321 6146 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6147 QLA8XXX_DEV_READY);
a5b36321 6148 qla82xx_idc_unlock(ha);
7190575f 6149 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6150 rval = qla82xx_restart_isp(base_vha);
6151 qla82xx_idc_lock(ha);
6152 /* Clear driver state register */
6153 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6154 qla82xx_set_drv_active(base_vha);
6155 }
6156 qla82xx_idc_unlock(ha);
6157 } else {
7c3df132
SK		 6158 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6159 "This devfn is not reset owner = 0x%x.\n",
6160 ha->pdev->devfn);
a5b36321 6161 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6162 QLA8XXX_DEV_READY)) {
7190575f 6163 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6164 rval = qla82xx_restart_isp(base_vha);
6165 qla82xx_idc_lock(ha);
6166 qla82xx_set_drv_active(base_vha);
6167 qla82xx_idc_unlock(ha);
6168 }
6169 }
6170 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6171
6172 return rval;
6173}
6174
14e660e6
SJ		 6175static pci_ers_result_t
6176qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6177{
6178 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6179 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6180 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6181 struct rsp_que *rsp;
6182 int rc, retries = 10;
09483916 6183
7c3df132
SK		 6184 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6185 "Slot Reset.\n");
85880801 6186
90a86fc0
JC		 6187 /* Workaround: qla2xxx driver which access hardware earlier
6188 * needs error state to be pci_channel_io_online.
6189 * Otherwise mailbox command timesout.
6190 */
6191 pdev->error_state = pci_channel_io_normal;
6192
6193 pci_restore_state(pdev);
6194
8c1496bd
RL		 6195 /* pci_restore_state() clears the saved_state flag of the device
6196 * save restored state which resets saved_state flag
6197 */
6198 pci_save_state(pdev);
6199
09483916
BH		 6200 if (ha->mem_only)
6201 rc = pci_enable_device_mem(pdev);
6202 else
6203 rc = pci_enable_device(pdev);
14e660e6 6204
09483916 6205 if (rc) {
7c3df132 6206 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6207 "Can't re-enable PCI device after reset.\n");
a5b36321 6208 goto exit_slot_reset;
14e660e6 6209 }
14e660e6 6210
90a86fc0
JC		 6211 rsp = ha->rsp_q_map[0];
6212 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6213 goto exit_slot_reset;
90a86fc0 6214
e315cd28 6215 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6216 goto exit_slot_reset;
6217
6218 if (IS_QLA82XX(ha)) {
6219 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6220 ret = PCI_ERS_RESULT_RECOVERED;
6221 goto exit_slot_reset;
6222 } else
6223 goto exit_slot_reset;
6224 }
14e660e6 6225
90a86fc0
JC		 6226 while (ha->flags.mbox_busy && retries--)
6227 msleep(1000);
85880801 6228
e315cd28 6229 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6230 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6231 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6232 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6233
90a86fc0 6234
a5b36321 6235exit_slot_reset:
7c3df132
SK		 6236 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6237 "slot_reset return %x.\n", ret);
85880801 6238
14e660e6
SJ		 6239 return ret;
6240}
6241
6242static void
6243qla2xxx_pci_resume(struct pci_dev *pdev)
6244{
e315cd28
AC		 6245 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6246 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6247 int ret;
6248
7c3df132
SK		 6249 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6250 "pci_resume.\n");
85880801 6251
e315cd28 6252 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6253 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6254 ql_log(ql_log_fatal, base_vha, 0x9002,
6255 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6256 }
85880801 6257
3e46f031
LC		 6258 pci_cleanup_aer_uncorrect_error_status(pdev);
6259
85880801 6260 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6261}
6262
2d5a4c34
HM		 6263static void
6264qla83xx_disable_laser(scsi_qla_host_t *vha)
6265{
6266 uint32_t reg, data, fn;
6267 struct qla_hw_data *ha = vha->hw;
6268 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6269
6270 /* pci func #/port # */
6271 ql_dbg(ql_dbg_init, vha, 0x004b,
6272 "Disabling Laser for hba: %p\n", vha);
6273
6274 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6275 (BIT_15|BIT_14|BIT_13|BIT_12));
6276
6277 fn = (fn >> 12);
6278
6279 if (fn & 1)
6280 reg = PORT_1_2031;
6281 else
6282 reg = PORT_0_2031;
6283
6284 data = LASER_OFF_2031;
6285
6286 qla83xx_wr_reg(vha, reg, data);
6287}
6288
5601236b
MH		 6289static int qla2xxx_map_queues(struct Scsi_Host *shost)
6290{
6291 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6292
6293 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6294}
6295
a55b2d21 6296static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6297 .error_detected = qla2xxx_pci_error_detected,
6298 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6299 .slot_reset = qla2xxx_pci_slot_reset,
6300 .resume = qla2xxx_pci_resume,
6301};
6302
5433383e 6303static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6304 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6305 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6306 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6307 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6308 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6309 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6310 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6311 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6312 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6313 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6314 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6315 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6316 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6317 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6318 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6319 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6320 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6321 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6322 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6323 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6324 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6325 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6326 { 0 },
6327};
6328MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6329
fca29703 6330static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6331 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6332 .driver = {
6333 .owner = THIS_MODULE,
6334 },
fca29703 6335 .id_table = qla2xxx_pci_tbl,
7ee61397 6336 .probe = qla2x00_probe_one,
4c993f76 6337 .remove = qla2x00_remove_one,
e30d1756 6338 .shutdown = qla2x00_shutdown,
14e660e6 6339 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6340};
6341
75ef9de1 6342static const struct file_operations apidev_fops = {
6a03b4cd 6343 .owner = THIS_MODULE,
6038f373 6344 .llseek = noop_llseek,
6a03b4cd
HZ		 6345};
6346
1da177e4
LT		 6347/**
6348 * qla2x00_module_init - Module initialization.
6349 **/
6350static int __init
6351qla2x00_module_init(void)
6352{
fca29703
AV		 6353 int ret = 0;
6354
1da177e4 6355 /* Allocate cache for SRBs. */
354d6b21 6356 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6357 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6358 if (srb_cachep == NULL) {
7c3df132
SK		 6359 ql_log(ql_log_fatal, NULL, 0x0001,
6360 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6361 return -ENOMEM;
6362 }
6363
2d70c103
NB		 6364 /* Initialize target kmem_cache and mem_pools */
6365 ret = qlt_init();
6366 if (ret < 0) {
6367 kmem_cache_destroy(srb_cachep);
6368 return ret;
6369 } else if (ret > 0) {
6370 /*
6371 * If initiator mode is explictly disabled by qlt_init(),
6372 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6373 * performing scsi_scan_target() during LOOP UP event.
6374 */
6375 qla2xxx_transport_functions.disable_target_scan = 1;
6376 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6377 }
6378
1da177e4
LT		 6379 /* Derive version string. */
6380 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6381 if (ql2xextended_error_logging)
0181944f
AV		 6382 strcat(qla2x00_version_str, "-debug");
6383
1c97a12a
AV		 6384 qla2xxx_transport_template =
6385 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6386 if (!qla2xxx_transport_template) {
6387 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6388 ql_log(ql_log_fatal, NULL, 0x0002,
6389 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6390 qlt_exit();
1da177e4 6391 return -ENODEV;
2c3dfe3f 6392 }
6a03b4cd
HZ		 6393
6394 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6395 if (apidev_major < 0) {
7c3df132
SK		 6396 ql_log(ql_log_fatal, NULL, 0x0003,
6397 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6398 }
6399
2c3dfe3f
SJ		 6400 qla2xxx_transport_vport_template =
6401 fc_attach_transport(&qla2xxx_transport_vport_functions);
6402 if (!qla2xxx_transport_vport_template) {
6403 kmem_cache_destroy(srb_cachep);
2d70c103 6404 qlt_exit();
2c3dfe3f 6405 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6406 ql_log(ql_log_fatal, NULL, 0x0004,
6407 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6408 return -ENODEV;
2c3dfe3f 6409 }
7c3df132
SK		 6410 ql_log(ql_log_info, NULL, 0x0005,
6411 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6412 qla2x00_version_str);
7ee61397 6413 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6414 if (ret) {
6415 kmem_cache_destroy(srb_cachep);
2d70c103 6416 qlt_exit();
fca29703 6417 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6418 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6419 ql_log(ql_log_fatal, NULL, 0x0006,
6420 "pci_register_driver failed...ret=%d Failing load!.\n",
6421 ret);
fca29703
AV		 6422 }
6423 return ret;
1da177e4
LT		 6424}
6425
6426/**
6427 * qla2x00_module_exit - Module cleanup.
6428 **/
6429static void __exit
6430qla2x00_module_exit(void)
6431{
6a03b4cd 6432 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6433 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6434 qla2x00_release_firmware();
354d6b21 6435 kmem_cache_destroy(srb_cachep);
2d70c103 6436 qlt_exit();
a9083016
GM		 6437 if (ctx_cachep)
6438 kmem_cache_destroy(ctx_cachep);
1da177e4 6439 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6440 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6441}
6442
6443module_init(qla2x00_module_init);
6444module_exit(qla2x00_module_exit);
6445
6446MODULE_AUTHOR("QLogic Corporation");
6447MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6448MODULE_LICENSE("GPL");
6449MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6450MODULE_FIRMWARE(FW_FILE_ISP21XX);
6451MODULE_FIRMWARE(FW_FILE_ISP22XX);
6452MODULE_FIRMWARE(FW_FILE_ISP2300);
6453MODULE_FIRMWARE(FW_FILE_ISP2322);
6454MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6455MODULE_FIRMWARE(FW_FILE_ISP25XX);
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