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scsi: qla2xxx: Cleaned up queue configuration code.
[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
50280c01
CD		 116#define MAX_Q_DEPTH 32
117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f
CD		 120 "Maximum queue depth to set for each LUN. "
121 "Default is 32.");
df7baa50 122
9e522cd8
AE		 123int ql2xenabledif = 2;
124module_param(ql2xenabledif, int, S_IRUGO);
bad75002 125MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 126 " Enable T10-CRC-DIF:\n"
127 " Default is 2.\n"
128 " 0 -- No DIF Support\n"
129 " 1 -- Enable DIF for all types\n"
130 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 131
8cb2049c 132int ql2xenablehba_err_chk = 2;
bad75002
AE		 133module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
134MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 135 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 136 " Default is 2.\n"
8cb2049c
AE		 137 " 0 -- Error isolation disabled\n"
138 " 1 -- Error isolation enabled only for DIX Type 0\n"
139 " 2 -- Error isolation enabled for all Types\n");
bad75002 140
e5896bd5 141int ql2xiidmaenable=1;
f2019cb1 142module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 143MODULE_PARM_DESC(ql2xiidmaenable,
144 "Enables iIDMA settings "
145 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
146
d7459527
MH		 147int ql2xmqsupport = 1;
148module_param(ql2xmqsupport, int, S_IRUGO);
149MODULE_PARM_DESC(ql2xmqsupport,
150 "Enable on demand multiple queue pairs support "
151 "Default is 1 for supported. "
152 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 153
154int ql2xfwloadbin;
86e45bf6 155module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 156module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 157MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 158 "Option to specify location from which to load ISP firmware:.\n"
159 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 160 " interface.\n"
161 " 1 -- load firmware from flash.\n"
162 " 0 -- use default semantics.\n");
163
ae97c91e 164int ql2xetsenable;
f2019cb1 165module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 166MODULE_PARM_DESC(ql2xetsenable,
167 "Enables firmware ETS burst."
168 "Default is 0 - skip ETS enablement.");
169
6907869d 170int ql2xdbwr = 1;
86e45bf6 171module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 172MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 173 "Option to specify scheme for request queue posting.\n"
174 " 0 -- Regular doorbell.\n"
175 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 176
f4c496c1 177int ql2xtargetreset = 1;
f2019cb1 178module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 179MODULE_PARM_DESC(ql2xtargetreset,
180 "Enable target reset."
181 "Default is 1 - use hw defaults.");
182
4da26e16 183int ql2xgffidenable;
f2019cb1 184module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 185MODULE_PARM_DESC(ql2xgffidenable,
186 "Enables GFF_ID checks of port type. "
187 "Default is 0 - Do not use GFF_ID information.");
a9083016 188
3822263e 189int ql2xasynctmfenable;
f2019cb1 190module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 191MODULE_PARM_DESC(ql2xasynctmfenable,
192 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
193 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 194
195int ql2xdontresethba;
86e45bf6 196module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 197MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 198 "Option to specify reset behaviour.\n"
199 " 0 (Default) -- Reset on failure.\n"
200 " 1 -- Do not reset on failure.\n");
ed0de87c 201
1abf635d
HR		 202uint64_t ql2xmaxlun = MAX_LUNS;
203module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 204MODULE_PARM_DESC(ql2xmaxlun,
205 "Defines the maximum LU number to register with the SCSI "
206 "midlayer. Default is 65535.");
207
08de2844
GM		 208int ql2xmdcapmask = 0x1F;
209module_param(ql2xmdcapmask, int, S_IRUGO);
210MODULE_PARM_DESC(ql2xmdcapmask,
211 "Set the Minidump driver capture mask level. "
6e96fa7b 212 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 213
3aadff35 214int ql2xmdenable = 1;
08de2844
GM		 215module_param(ql2xmdenable, int, S_IRUGO);
216MODULE_PARM_DESC(ql2xmdenable,
217 "Enable/disable MiniDump. "
3aadff35
GM		 218 "0 - MiniDump disabled. "
219 "1 (Default) - MiniDump enabled.");
08de2844 220
b0d6cabd
HM		 221int ql2xexlogins = 0;
222module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
223MODULE_PARM_DESC(ql2xexlogins,
224 "Number of extended Logins. "
225 "0 (Default)- Disabled.");
226
2f56a7f1
HM		 227int ql2xexchoffld = 0;
228module_param(ql2xexchoffld, uint, S_IRUGO|S_IWUSR);
229MODULE_PARM_DESC(ql2xexchoffld,
230 "Number of exchanges to offload. "
231 "0 (Default)- Disabled.");
232
f198cafa
HM		 233int ql2xfwholdabts = 0;
234module_param(ql2xfwholdabts, int, S_IRUGO);
235MODULE_PARM_DESC(ql2xfwholdabts,
236 "Allow FW to hold status IOCB until ABTS rsp received. "
237 "0 (Default) Do not set fw option. "
238 "1 - Set fw option to hold ABTS.");
239
1da177e4 240/*
fa2a1ce5 241 * SCSI host template entry points
1da177e4
LT		 242 */
243static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 244static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 245static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
246static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 247static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 248static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 249static int qla2xxx_eh_abort(struct scsi_cmnd *);
250static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 251static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 252static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
253static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 254
1a2fbf18 255static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 256static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 257static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 258static int qla2xxx_map_queues(struct Scsi_Host *shost);
ce7e4af7 259
a5326f86 260struct scsi_host_template qla2xxx_driver_template = {
1da177e4 261 .module = THIS_MODULE,
cb63067a 262 .name = QLA2XXX_DRIVER_NAME,
a5326f86 263 .queuecommand = qla2xxx_queuecommand,
fca29703 264
b6a05c82 265 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 266 .eh_abort_handler = qla2xxx_eh_abort,
267 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 268 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 269 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
270 .eh_host_reset_handler = qla2xxx_eh_host_reset,
271
272 .slave_configure = qla2xxx_slave_configure,
273
274 .slave_alloc = qla2xxx_slave_alloc,
275 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 276 .scan_finished = qla2xxx_scan_finished,
277 .scan_start = qla2xxx_scan_start,
db5ed4df 278 .change_queue_depth = scsi_change_queue_depth,
5601236b 279 .map_queues = qla2xxx_map_queues,
fca29703
AV		 280 .this_id = -1,
281 .cmd_per_lun = 3,
282 .use_clustering = ENABLE_CLUSTERING,
283 .sg_tablesize = SG_ALL,
284
285 .max_sectors = 0xFFFF,
afb046e2 286 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 287
288 .supported_mode = MODE_INITIATOR,
c40ecc12 289 .track_queue_depth = 1,
fca29703
AV		 290};
291
1da177e4 292static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 293struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 294
1da177e4
LT		 295/* TODO Convert to inlines
296 *
297 * Timer routines
298 */
1da177e4 299
2c3dfe3f 300__inline__ void
e315cd28 301qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval)
1da177e4 302{
e315cd28
AC		 303 init_timer(&vha->timer);
304 vha->timer.expires = jiffies + interval * HZ;
305 vha->timer.data = (unsigned long)vha;
306 vha->timer.function = (void (*)(unsigned long))func;
307 add_timer(&vha->timer);
308 vha->timer_active = 1;
1da177e4
LT		 309}
310
311static inline void
e315cd28 312qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 313{
a9083016 314 /* Currently used for 82XX only. */
7c3df132
SK		 315 if (vha->device_flags & DFLG_DEV_FAILED) {
316 ql_dbg(ql_dbg_timer, vha, 0x600d,
317 "Device in a failed state, returning.\n");
a9083016 318 return;
7c3df132 319 }
a9083016 320
e315cd28 321 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 322}
323
a824ebb3 324static __inline__ void
e315cd28 325qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 326{
e315cd28
AC		 327 del_timer_sync(&vha->timer);
328 vha->timer_active = 0;
1da177e4
LT		 329}
330
1da177e4
LT		 331static int qla2x00_do_dpc(void *data);
332
333static void qla2x00_rst_aen(scsi_qla_host_t *);
334
73208dfd
AC		 335static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
336 struct req_que **, struct rsp_que **);
e30d1756 337static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 338static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 339int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
340 struct qla_qpair *qpair);
1da177e4 341
1da177e4 342/* -------------------------------------------------------------------------- */
9a347ff4
CD		 343static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
344 struct rsp_que *rsp)
73208dfd 345{
7c3df132 346 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 347 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 348 GFP_KERNEL);
349 if (!ha->req_q_map) {
7c3df132
SK		 350 ql_log(ql_log_fatal, vha, 0x003b,
351 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 352 goto fail_req_map;
353 }
354
2afa19a9 355 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 356 GFP_KERNEL);
357 if (!ha->rsp_q_map) {
7c3df132
SK		 358 ql_log(ql_log_fatal, vha, 0x003c,
359 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 360 goto fail_rsp_map;
361 }
d7459527
MH		 362
363 if (ql2xmqsupport && ha->max_qpairs) {
364 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
365 GFP_KERNEL);
366 if (!ha->queue_pair_map) {
367 ql_log(ql_log_fatal, vha, 0x0180,
368 "Unable to allocate memory for queue pair ptrs.\n");
369 goto fail_qpair_map;
370 }
371 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
372 if (ha->base_qpair == NULL) {
373 ql_log(ql_log_warn, vha, 0x0182,
374 "Failed to allocate base queue pair memory.\n");
375 goto fail_base_qpair;
376 }
377 ha->base_qpair->req = req;
378 ha->base_qpair->rsp = rsp;
379 }
380
9a347ff4
CD		 381 /*
382 * Make sure we record at least the request and response queue zero in
383 * case we need to free them if part of the probe fails.
384 */
385 ha->rsp_q_map[0] = rsp;
386 ha->req_q_map[0] = req;
73208dfd
AC		 387 set_bit(0, ha->rsp_qid_map);
388 set_bit(0, ha->req_qid_map);
389 return 1;
390
d7459527
MH		 391fail_base_qpair:
392 kfree(ha->queue_pair_map);
393fail_qpair_map:
394 kfree(ha->rsp_q_map);
395 ha->rsp_q_map = NULL;
73208dfd
AC		 396fail_rsp_map:
397 kfree(ha->req_q_map);
398 ha->req_q_map = NULL;
399fail_req_map:
400 return -ENOMEM;
401}
402
2afa19a9 403static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 404{
8ae6d9c7
GM		 405 if (IS_QLAFX00(ha)) {
406 if (req && req->ring_fx00)
407 dma_free_coherent(&ha->pdev->dev,
408 (req->length_fx00 + 1) * sizeof(request_t),
409 req->ring_fx00, req->dma_fx00);
410 } else if (req && req->ring)
73208dfd
AC		 411 dma_free_coherent(&ha->pdev->dev,
412 (req->length + 1) * sizeof(request_t),
413 req->ring, req->dma);
414
8d93f550
CD		 415 if (req)
416 kfree(req->outstanding_cmds);
417
73208dfd
AC		 418 kfree(req);
419 req = NULL;
420}
421
2afa19a9
AC		 422static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
423{
8ae6d9c7
GM		 424 if (IS_QLAFX00(ha)) {
425 if (rsp && rsp->ring)
426 dma_free_coherent(&ha->pdev->dev,
427 (rsp->length_fx00 + 1) * sizeof(request_t),
428 rsp->ring_fx00, rsp->dma_fx00);
429 } else if (rsp && rsp->ring) {
2afa19a9
AC		 430 dma_free_coherent(&ha->pdev->dev,
431 (rsp->length + 1) * sizeof(response_t),
432 rsp->ring, rsp->dma);
8ae6d9c7 433 }
2afa19a9
AC		 434 kfree(rsp);
435 rsp = NULL;
436}
437
73208dfd
AC		 438static void qla2x00_free_queues(struct qla_hw_data *ha)
439{
440 struct req_que *req;
441 struct rsp_que *rsp;
442 int cnt;
093df737 443 unsigned long flags;
73208dfd 444
093df737 445 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 446 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 447 if (!test_bit(cnt, ha->req_qid_map))
448 continue;
449
73208dfd 450 req = ha->req_q_map[cnt];
093df737
QT		 451 clear_bit(cnt, ha->req_qid_map);
452 ha->req_q_map[cnt] = NULL;
453
454 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 455 qla2x00_free_req_que(ha, req);
093df737 456 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 457 }
093df737
QT		 458 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459
73208dfd
AC		 460 kfree(ha->req_q_map);
461 ha->req_q_map = NULL;
2afa19a9 462
093df737
QT		 463
464 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 465 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 466 if (!test_bit(cnt, ha->rsp_qid_map))
467 continue;
468
2afa19a9 469 rsp = ha->rsp_q_map[cnt];
c3c42394 470 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 471 ha->rsp_q_map[cnt] = NULL;
472 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 473 qla2x00_free_rsp_que(ha, rsp);
093df737 474 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 475 }
093df737
QT		 476 spin_unlock_irqrestore(&ha->hardware_lock, flags);
477
2afa19a9
AC		 478 kfree(ha->rsp_q_map);
479 ha->rsp_q_map = NULL;
73208dfd
AC		 480}
481
1da177e4 482static char *
e315cd28 483qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 484{
e315cd28 485 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 486 static char *pci_bus_modes[] = {
487 "33", "66", "100", "133",
488 };
489 uint16_t pci_bus;
490
491 strcpy(str, "PCI");
492 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
493 if (pci_bus) {
494 strcat(str, "-X (");
495 strcat(str, pci_bus_modes[pci_bus]);
496 } else {
497 pci_bus = (ha->pci_attr & BIT_8) >> 8;
498 strcat(str, " (");
499 strcat(str, pci_bus_modes[pci_bus]);
500 }
501 strcat(str, " MHz)");
502
503 return (str);
504}
505
fca29703 506static char *
e315cd28 507qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 508{
509 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 510 struct qla_hw_data *ha = vha->hw;
fca29703 511 uint32_t pci_bus;
fca29703 512
62a276f8 513 if (pci_is_pcie(ha->pdev)) {
fca29703 514 char lwstr[6];
62a276f8 515 uint32_t lstat, lspeed, lwidth;
fca29703 516
62a276f8
BH		 517 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
518 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
519 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 520
521 strcpy(str, "PCIe (");
49300af7
SK		 522 switch (lspeed) {
523 case 1:
c87a0d8c 524 strcat(str, "2.5GT/s ");
49300af7
SK		 525 break;
526 case 2:
c87a0d8c 527 strcat(str, "5.0GT/s ");
49300af7
SK		 528 break;
529 case 3:
530 strcat(str, "8.0GT/s ");
531 break;
532 default:
fca29703 533 strcat(str, "<unknown> ");
49300af7
SK		 534 break;
535 }
fca29703
AV		 536 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
537 strcat(str, lwstr);
538
539 return str;
540 }
541
542 strcpy(str, "PCI");
543 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
544 if (pci_bus == 0 || pci_bus == 8) {
545 strcat(str, " (");
546 strcat(str, pci_bus_modes[pci_bus >> 3]);
547 } else {
548 strcat(str, "-X ");
549 if (pci_bus & BIT_2)
550 strcat(str, "Mode 2");
551 else
552 strcat(str, "Mode 1");
553 strcat(str, " (");
554 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
555 }
556 strcat(str, " MHz)");
557
558 return str;
559}
560
e5f82ab8 561static char *
df57caba 562qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 563{
564 char un_str[10];
e315cd28 565 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 566
df57caba
HM		 567 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
568 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 569
570 if (ha->fw_attributes & BIT_9) {
571 strcat(str, "FLX");
572 return (str);
573 }
574
575 switch (ha->fw_attributes & 0xFF) {
576 case 0x7:
577 strcat(str, "EF");
578 break;
579 case 0x17:
580 strcat(str, "TP");
581 break;
582 case 0x37:
583 strcat(str, "IP");
584 break;
585 case 0x77:
586 strcat(str, "VI");
587 break;
588 default:
589 sprintf(un_str, "(%x)", ha->fw_attributes);
590 strcat(str, un_str);
591 break;
592 }
593 if (ha->fw_attributes & 0x100)
594 strcat(str, "X");
595
596 return (str);
597}
598
e5f82ab8 599static char *
df57caba 600qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 601{
e315cd28 602 struct qla_hw_data *ha = vha->hw;
f0883ac6 603
df57caba 604 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 605 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 606 return str;
fca29703
AV		 607}
608
9ba56b95
GM		 609void
610qla2x00_sp_free_dma(void *vha, void *ptr)
fca29703 611{
9ba56b95
GM		 612 srb_t *sp = (srb_t *)ptr;
613 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
614 struct qla_hw_data *ha = sp->fcport->vha->hw;
615 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 616
9ba56b95
GM		 617 if (sp->flags & SRB_DMA_VALID) {
618 scsi_dma_unmap(cmd);
619 sp->flags &= ~SRB_DMA_VALID;
7c3df132 620 }
fca29703 621
9ba56b95
GM		 622 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
623 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
624 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
625 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
626 }
627
628 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
629 /* List assured to be having elements */
f83adb61 630 qla2x00_clean_dsd_pool(ha, sp, NULL);
9ba56b95
GM		 631 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
632 }
633
634 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
635 dma_pool_free(ha->dl_dma_pool, ctx,
636 ((struct crc_context *)ctx)->crc_ctx_dma);
637 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
638 }
639
640 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
641 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
fca29703 642
9ba56b95
GM		 643 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
644 ctx1->fcp_cmnd_dma);
645 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
646 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
647 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
648 mempool_free(ctx1, ha->ctx_mempool);
649 ctx1 = NULL;
650 }
651
652 CMD_SP(cmd) = NULL;
b00ee7d7 653 qla2x00_rel_sp(sp->fcport->vha, sp);
9ba56b95
GM		 654}
655
d7459527 656void
9ba56b95
GM		 657qla2x00_sp_compl(void *data, void *ptr, int res)
658{
659 struct qla_hw_data *ha = (struct qla_hw_data *)data;
660 srb_t *sp = (srb_t *)ptr;
661 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
662
663 cmd->result = res;
664
665 if (atomic_read(&sp->ref_count) == 0) {
666 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3015,
667 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
668 sp, GET_CMD_SP(sp));
669 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 670 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 671 return;
672 }
673 if (!atomic_dec_and_test(&sp->ref_count))
674 return;
675
676 qla2x00_sp_free_dma(ha, sp);
677 cmd->scsi_done(cmd);
fca29703
AV		 678}
679
d7459527
MH		 680void
681qla2xxx_qpair_sp_free_dma(void *vha, void *ptr)
682{
683 srb_t *sp = (srb_t *)ptr;
684 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
685 struct qla_hw_data *ha = sp->fcport->vha->hw;
686 void *ctx = GET_CMD_CTX_SP(sp);
687
688 if (sp->flags & SRB_DMA_VALID) {
689 scsi_dma_unmap(cmd);
690 sp->flags &= ~SRB_DMA_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
694 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
695 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
696 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
697 }
698
699 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
700 /* List assured to be having elements */
701 qla2x00_clean_dsd_pool(ha, sp, NULL);
702 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
703 }
704
705 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
706 dma_pool_free(ha->dl_dma_pool, ctx,
707 ((struct crc_context *)ctx)->crc_ctx_dma);
708 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
709 }
710
711 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
712 struct ct6_dsd *ctx1 = (struct ct6_dsd *)ctx;
713
714 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
715 ctx1->fcp_cmnd_dma);
716 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
717 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
718 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
719 mempool_free(ctx1, ha->ctx_mempool);
720 }
721
722 CMD_SP(cmd) = NULL;
723 qla2xxx_rel_qpair_sp(sp->qpair, sp);
724}
725
726void
727qla2xxx_qpair_sp_compl(void *data, void *ptr, int res)
728{
729 srb_t *sp = (srb_t *)ptr;
730 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
731
732 cmd->result = res;
733
734 if (atomic_read(&sp->ref_count) == 0) {
735 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
736 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
737 sp, GET_CMD_SP(sp));
738 if (ql2xextended_error_logging & ql_dbg_io)
739 WARN_ON(atomic_read(&sp->ref_count) == 0);
740 return;
741 }
742 if (!atomic_dec_and_test(&sp->ref_count))
743 return;
744
745 qla2xxx_qpair_sp_free_dma(sp->fcport->vha, sp);
746 cmd->scsi_done(cmd);
747}
748
8ae6d9c7
GM		 749/* If we are SP1 here, we need to still take and release the host_lock as SP1
750 * does not have the changes necessary to avoid taking host->host_lock.
751 */
1da177e4 752static int
f5e3e40b 753qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 754{
134ae078 755 scsi_qla_host_t *vha = shost_priv(host);
fca29703 756 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 757 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 758 struct qla_hw_data *ha = vha->hw;
759 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 760 srb_t *sp;
761 int rval;
5601236b
MH		 762 struct qla_qpair *qpair = NULL;
763 uint32_t tag;
764 uint16_t hwq;
fca29703 765
04dfaa53
MFO		 766 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
767 cmd->result = DID_NO_CONNECT << 16;
768 goto qc24_fail_command;
769 }
770
5601236b
MH		 771 if (ha->mqenable) {
772 if (shost_use_blk_mq(vha->host)) {
773 tag = blk_mq_unique_tag(cmd->request);
774 hwq = blk_mq_unique_tag_to_hwq(tag);
775 qpair = ha->queue_pair_map[hwq];
776 } else if (vha->vp_idx && vha->qpair) {
777 qpair = vha->qpair;
778 }
779
780 if (qpair)
781 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 782 }
783
85880801 784 if (ha->flags.eeh_busy) {
7c3df132 785 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 786 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 787 "PCI Channel IO permanent failure, exiting "
788 "cmd=%p.\n", cmd);
b9b12f73 789 cmd->result = DID_NO_CONNECT << 16;
7c3df132 790 } else {
5f28d2d7 791 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 792 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 793 cmd->result = DID_REQUEUE << 16;
7c3df132 794 }
14e660e6
SJ		 795 goto qc24_fail_command;
796 }
797
19a7b4ae
JSEC		 798 rval = fc_remote_port_chkready(rport);
799 if (rval) {
800 cmd->result = rval;
5f28d2d7 801 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 802 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
803 cmd, rval);
fca29703
AV		 804 goto qc24_fail_command;
805 }
806
bad75002
AE		 807 if (!vha->flags.difdix_supported &&
808 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 809 ql_dbg(ql_dbg_io, vha, 0x3004,
810 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
811 cmd);
bad75002
AE		 812 cmd->result = DID_NO_CONNECT << 16;
813 goto qc24_fail_command;
814 }
aa651be8
CD		 815
816 if (!fcport) {
817 cmd->result = DID_NO_CONNECT << 16;
818 goto qc24_fail_command;
819 }
820
fca29703
AV		 821 if (atomic_read(&fcport->state) != FCS_ONLINE) {
822 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 823 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 824 ql_dbg(ql_dbg_io, vha, 0x3005,
825 "Returning DNC, fcport_state=%d loop_state=%d.\n",
826 atomic_read(&fcport->state),
827 atomic_read(&base_vha->loop_state));
fca29703
AV		 828 cmd->result = DID_NO_CONNECT << 16;
829 goto qc24_fail_command;
830 }
7b594131 831 goto qc24_target_busy;
fca29703
AV		 832 }
833
e05fe292
CD		 834 /*
835 * Return target busy if we've received a non-zero retry_delay_timer
836 * in a FCP_RSP.
837 */
975f7d46
BP		 838 if (fcport->retry_delay_timestamp == 0) {
839 /* retry delay not set */
840 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 841 fcport->retry_delay_timestamp = 0;
842 else
843 goto qc24_target_busy;
844
b00ee7d7 845 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 846 if (!sp)
f5e3e40b 847 goto qc24_host_busy;
fca29703 848
9ba56b95
GM		 849 sp->u.scmd.cmd = cmd;
850 sp->type = SRB_SCSI_CMD;
851 atomic_set(&sp->ref_count, 1);
852 CMD_SP(cmd) = (void *)sp;
853 sp->free = qla2x00_sp_free_dma;
854 sp->done = qla2x00_sp_compl;
855
e315cd28 856 rval = ha->isp_ops->start_scsi(sp);
7c3df132 857 if (rval != QLA_SUCCESS) {
53016ed3 858 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 859 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 860 goto qc24_host_busy_free_sp;
7c3df132 861 }
fca29703 862
fca29703
AV		 863 return 0;
864
865qc24_host_busy_free_sp:
9ba56b95 866 qla2x00_sp_free_dma(ha, sp);
fca29703 867
f5e3e40b 868qc24_host_busy:
fca29703
AV		 869 return SCSI_MLQUEUE_HOST_BUSY;
870
7b594131
MC		 871qc24_target_busy:
872 return SCSI_MLQUEUE_TARGET_BUSY;
873
fca29703 874qc24_fail_command:
f5e3e40b 875 cmd->scsi_done(cmd);
fca29703
AV		 876
877 return 0;
878}
879
d7459527
MH		 880/* For MQ supported I/O */
881int
882qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
883 struct qla_qpair *qpair)
884{
885 scsi_qla_host_t *vha = shost_priv(host);
886 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
887 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
888 struct qla_hw_data *ha = vha->hw;
889 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
890 srb_t *sp;
891 int rval;
892
893 rval = fc_remote_port_chkready(rport);
894 if (rval) {
895 cmd->result = rval;
896 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
897 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
898 cmd, rval);
899 goto qc24_fail_command;
900 }
901
902 if (!fcport) {
903 cmd->result = DID_NO_CONNECT << 16;
904 goto qc24_fail_command;
905 }
906
907 if (atomic_read(&fcport->state) != FCS_ONLINE) {
908 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
909 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
910 ql_dbg(ql_dbg_io, vha, 0x3077,
911 "Returning DNC, fcport_state=%d loop_state=%d.\n",
912 atomic_read(&fcport->state),
913 atomic_read(&base_vha->loop_state));
914 cmd->result = DID_NO_CONNECT << 16;
915 goto qc24_fail_command;
916 }
917 goto qc24_target_busy;
918 }
919
920 /*
921 * Return target busy if we've received a non-zero retry_delay_timer
922 * in a FCP_RSP.
923 */
924 if (fcport->retry_delay_timestamp == 0) {
925 /* retry delay not set */
926 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
927 fcport->retry_delay_timestamp = 0;
928 else
929 goto qc24_target_busy;
930
931 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
932 if (!sp)
933 goto qc24_host_busy;
934
935 sp->u.scmd.cmd = cmd;
936 sp->type = SRB_SCSI_CMD;
937 atomic_set(&sp->ref_count, 1);
938 CMD_SP(cmd) = (void *)sp;
939 sp->free = qla2xxx_qpair_sp_free_dma;
940 sp->done = qla2xxx_qpair_sp_compl;
941 sp->qpair = qpair;
942
943 rval = ha->isp_ops->start_scsi_mq(sp);
944 if (rval != QLA_SUCCESS) {
945 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
946 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
947 if (rval == QLA_INTERFACE_ERROR)
948 goto qc24_fail_command;
949 goto qc24_host_busy_free_sp;
950 }
951
952 return 0;
953
954qc24_host_busy_free_sp:
955 qla2xxx_qpair_sp_free_dma(vha, sp);
956
957qc24_host_busy:
958 return SCSI_MLQUEUE_HOST_BUSY;
959
960qc24_target_busy:
961 return SCSI_MLQUEUE_TARGET_BUSY;
962
963qc24_fail_command:
964 cmd->scsi_done(cmd);
965
966 return 0;
967}
968
1da177e4
LT		 969/*
970 * qla2x00_eh_wait_on_command
971 * Waits for the command to be returned by the Firmware for some
972 * max time.
973 *
974 * Input:
1da177e4 975 * cmd = Scsi Command to wait on.
1da177e4
LT		 976 *
977 * Return:
978 * Not Found : 0
979 * Found : 1
980 */
981static int
e315cd28 982qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 983{
fe74c71f 984#define ABORT_POLLING_PERIOD 1000
478c3b03 985#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 986 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 987 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
988 struct qla_hw_data *ha = vha->hw;
f4f051eb 989 int ret = QLA_SUCCESS;
1da177e4 990
85880801 991 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 992 ql_dbg(ql_dbg_taskm, vha, 0x8005,
993 "Return:eh_wait.\n");
85880801
AV		 994 return ret;
995 }
996
d970432c 997 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 998 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 999 }
1000 if (CMD_SP(cmd))
1001 ret = QLA_FUNCTION_FAILED;
1da177e4 1002
f4f051eb 1003 return ret;
1da177e4
LT		 1004}
1005
1006/*
1007 * qla2x00_wait_for_hba_online
fa2a1ce5 1008 * Wait till the HBA is online after going through
1da177e4
LT		 1009 * <= MAX_RETRIES_OF_ISP_ABORT or
1010 * finally HBA is disabled ie marked offline
1011 *
1012 * Input:
1013 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1014 *
1015 * Note:
1da177e4
LT		 1016 * Does context switching-Release SPIN_LOCK
1017 * (if any) before calling this routine.
1018 *
1019 * Return:
1020 * Success (Adapter is online) : 0
1021 * Failed (Adapter is offline/disabled) : 1
1022 */
854165f4 1023int
e315cd28 1024qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1025{
fca29703
AV		 1026 int return_status;
1027 unsigned long wait_online;
e315cd28
AC		 1028 struct qla_hw_data *ha = vha->hw;
1029 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1030
fa2a1ce5 1031 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1032 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1033 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1034 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1035 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1036
1037 msleep(1000);
1038 }
e315cd28 1039 if (base_vha->flags.online)
fa2a1ce5 1040 return_status = QLA_SUCCESS;
1da177e4
LT		 1041 else
1042 return_status = QLA_FUNCTION_FAILED;
1043
1da177e4
LT		 1044 return (return_status);
1045}
1046
86fbee86 1047/*
638a1a01
SC		 1048 * qla2x00_wait_for_hba_ready
1049 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1050 *
1051 * Input:
1052 * ha - pointer to host adapter structure
1053 *
1054 * Note:
1055 * Does context switching-Release SPIN_LOCK
1056 * (if any) before calling this routine.
1057 *
86fbee86 1058 */
638a1a01
SC		 1059static void
1060qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1061{
86fbee86 1062 struct qla_hw_data *ha = vha->hw;
783e0dc4 1063 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1064
1d483901
DC		 1065 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1066 ha->flags.mbox_busy) ||
1067 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1068 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1069 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1070 break;
86fbee86 1071 msleep(1000);
783e0dc4 1072 }
86fbee86
LC		 1073}
1074
2533cf67
LC		 1075int
1076qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1077{
1078 int return_status;
1079 unsigned long wait_reset;
1080 struct qla_hw_data *ha = vha->hw;
1081 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1082
1083 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1084 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1085 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1086 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1087 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1088
1089 msleep(1000);
1090
1091 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1092 ha->flags.chip_reset_done)
1093 break;
1094 }
1095 if (ha->flags.chip_reset_done)
1096 return_status = QLA_SUCCESS;
1097 else
1098 return_status = QLA_FUNCTION_FAILED;
1099
1100 return return_status;
1101}
1102
083a469d
GM		 1103static void
1104sp_get(struct srb *sp)
1105{
1106 atomic_inc(&sp->ref_count);
1107}
1108
a465537a
SC		 1109#define ISP_REG_DISCONNECT 0xffffffffU
1110/**************************************************************************
1111* qla2x00_isp_reg_stat
1112*
1113* Description:
1114* Read the host status register of ISP before aborting the command.
1115*
1116* Input:
1117* ha = pointer to host adapter structure.
1118*
1119*
1120* Returns:
1121* Either true or false.
1122*
1123* Note: Return true if there is register disconnect.
1124**************************************************************************/
1125static inline
1126uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1127{
1128 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1129
1130 return ((RD_REG_DWORD(&reg->host_status)) == ISP_REG_DISCONNECT);
1131}
1132
1da177e4
LT		 1133/**************************************************************************
1134* qla2xxx_eh_abort
1135*
1136* Description:
1137* The abort function will abort the specified command.
1138*
1139* Input:
1140* cmd = Linux SCSI command packet to be aborted.
1141*
1142* Returns:
1143* Either SUCCESS or FAILED.
1144*
1145* Note:
2ea00202 1146* Only return FAILED if command not returned by firmware.
1da177e4 1147**************************************************************************/
e5f82ab8 1148static int
1da177e4
LT		 1149qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1150{
e315cd28 1151 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1152 srb_t *sp;
4e98d3b8 1153 int ret;
9cb78c16
HR		 1154 unsigned int id;
1155 uint64_t lun;
18e144d3 1156 unsigned long flags;
f934c9d0 1157 int rval, wait = 0;
e315cd28 1158 struct qla_hw_data *ha = vha->hw;
1da177e4 1159
a465537a
SC		 1160 if (qla2x00_isp_reg_stat(ha)) {
1161 ql_log(ql_log_info, vha, 0x8042,
1162 "PCI/Register disconnect, exiting.\n");
1163 return FAILED;
1164 }
f4f051eb 1165 if (!CMD_SP(cmd))
2ea00202 1166 return SUCCESS;
1da177e4 1167
4e98d3b8
AV		 1168 ret = fc_block_scsi_eh(cmd);
1169 if (ret != 0)
1170 return ret;
1171 ret = SUCCESS;
1172
f4f051eb
AV		 1173 id = cmd->device->id;
1174 lun = cmd->device->lun;
1da177e4 1175
e315cd28 1176 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1177 sp = (srb_t *) CMD_SP(cmd);
1178 if (!sp) {
1179 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1180 return SUCCESS;
1181 }
1da177e4 1182
7c3df132 1183 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1184 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1185 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1186
170babc3
MC		 1187 /* Get a reference to the sp and drop the lock.*/
1188 sp_get(sp);
083a469d 1189
e315cd28 1190 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1191 rval = ha->isp_ops->abort_command(sp);
1192 if (rval) {
96219424 1193 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1194 ret = SUCCESS;
96219424 1195 else
f934c9d0
CD		 1196 ret = FAILED;
1197
7c3df132 1198 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1199 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1200 } else {
7c3df132 1201 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1202 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1203 wait = 1;
1204 }
75942064
SK		 1205
1206 spin_lock_irqsave(&ha->hardware_lock, flags);
9ba56b95 1207 sp->done(ha, sp, 0);
75942064 1208 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1209
bc91ade9
CD		 1210 /* Did the command return during mailbox execution? */
1211 if (ret == FAILED && !CMD_SP(cmd))
1212 ret = SUCCESS;
1213
f4f051eb 1214 /* Wait for the command to be returned. */
2ea00202 1215 if (wait) {
e315cd28 1216 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1217 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1218 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1219 ret = FAILED;
f4f051eb 1220 }
1da177e4 1221 }
1da177e4 1222
7c3df132 1223 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1224 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1225 vha->host_no, id, lun, wait, ret);
1da177e4 1226
f4f051eb
AV		 1227 return ret;
1228}
1da177e4 1229
4d78c973 1230int
e315cd28 1231qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1232 uint64_t l, enum nexus_wait_type type)
f4f051eb 1233{
17d98630 1234 int cnt, match, status;
18e144d3 1235 unsigned long flags;
e315cd28 1236 struct qla_hw_data *ha = vha->hw;
73208dfd 1237 struct req_que *req;
4d78c973 1238 srb_t *sp;
9ba56b95 1239 struct scsi_cmnd *cmd;
1da177e4 1240
523ec773 1241 status = QLA_SUCCESS;
17d98630 1242
e315cd28 1243 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1244 req = vha->req;
17d98630 1245 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1246 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1247 sp = req->outstanding_cmds[cnt];
1248 if (!sp)
523ec773 1249 continue;
9ba56b95 1250 if (sp->type != SRB_SCSI_CMD)
cf53b069 1251 continue;
17d98630
AC		 1252 if (vha->vp_idx != sp->fcport->vha->vp_idx)
1253 continue;
1254 match = 0;
9ba56b95 1255 cmd = GET_CMD_SP(sp);
17d98630
AC		 1256 switch (type) {
1257 case WAIT_HOST:
1258 match = 1;
1259 break;
1260 case WAIT_TARGET:
9ba56b95 1261 match = cmd->device->id == t;
17d98630
AC		 1262 break;
1263 case WAIT_LUN:
9ba56b95
GM		 1264 match = (cmd->device->id == t &&
1265 cmd->device->lun == l);
17d98630 1266 break;
73208dfd 1267 }
17d98630
AC		 1268 if (!match)
1269 continue;
1270
1271 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1272 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1273 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1274 }
e315cd28 1275 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1276
1277 return status;
1da177e4
LT		 1278}
1279
523ec773
AV		 1280static char *reset_errors[] = {
1281 "HBA not online",
1282 "HBA not ready",
1283 "Task management failed",
1284 "Waiting for command completions",
1285};
1da177e4 1286
e5f82ab8 1287static int
523ec773 1288__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1289 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1290{
e315cd28 1291 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1292 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1293 int err;
1da177e4 1294
7c3df132 1295 if (!fcport) {
523ec773 1296 return FAILED;
7c3df132 1297 }
1da177e4 1298
4e98d3b8
AV		 1299 err = fc_block_scsi_eh(cmd);
1300 if (err != 0)
1301 return err;
1302
7c3df132 1303 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1304 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1305 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1306
523ec773 1307 err = 0;
7c3df132
SK		 1308 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1309 ql_log(ql_log_warn, vha, 0x800a,
1310 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1311 goto eh_reset_failed;
7c3df132 1312 }
523ec773 1313 err = 2;
2afa19a9 1314 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1315 != QLA_SUCCESS) {
1316 ql_log(ql_log_warn, vha, 0x800c,
1317 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1318 goto eh_reset_failed;
7c3df132 1319 }
523ec773 1320 err = 3;
e315cd28 1321 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1322 cmd->device->lun, type) != QLA_SUCCESS) {
1323 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1324 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1325 goto eh_reset_failed;
7c3df132 1326 }
523ec773 1327
7c3df132 1328 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1329 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1330 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1331
1332 return SUCCESS;
1333
4d78c973 1334eh_reset_failed:
7c3df132 1335 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1336 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1337 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1338 cmd);
523ec773
AV		 1339 return FAILED;
1340}
1da177e4 1341
523ec773
AV		 1342static int
1343qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1344{
e315cd28
AC		 1345 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1346 struct qla_hw_data *ha = vha->hw;
1da177e4 1347
a465537a
SC		 1348 if (qla2x00_isp_reg_stat(ha)) {
1349 ql_log(ql_log_info, vha, 0x803e,
1350 "PCI/Register disconnect, exiting.\n");
1351 return FAILED;
1352 }
1353
523ec773
AV		 1354 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1355 ha->isp_ops->lun_reset);
1da177e4
LT		 1356}
1357
1da177e4 1358static int
523ec773 1359qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1360{
e315cd28
AC		 1361 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1362 struct qla_hw_data *ha = vha->hw;
1da177e4 1363
a465537a
SC		 1364 if (qla2x00_isp_reg_stat(ha)) {
1365 ql_log(ql_log_info, vha, 0x803f,
1366 "PCI/Register disconnect, exiting.\n");
1367 return FAILED;
1368 }
1369
523ec773
AV		 1370 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1371 ha->isp_ops->target_reset);
1da177e4
LT		 1372}
1373
1da177e4
LT		 1374/**************************************************************************
1375* qla2xxx_eh_bus_reset
1376*
1377* Description:
1378* The bus reset function will reset the bus and abort any executing
1379* commands.
1380*
1381* Input:
1382* cmd = Linux SCSI command packet of the command that cause the
1383* bus reset.
1384*
1385* Returns:
1386* SUCCESS/FAILURE (defined as macro in scsi.h).
1387*
1388**************************************************************************/
e5f82ab8 1389static int
1da177e4
LT		 1390qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1391{
e315cd28 1392 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1393 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1394 int ret = FAILED;
9cb78c16
HR		 1395 unsigned int id;
1396 uint64_t lun;
a465537a
SC		 1397 struct qla_hw_data *ha = vha->hw;
1398
1399 if (qla2x00_isp_reg_stat(ha)) {
1400 ql_log(ql_log_info, vha, 0x8040,
1401 "PCI/Register disconnect, exiting.\n");
1402 return FAILED;
1403 }
f4f051eb 1404
f4f051eb
AV		 1405 id = cmd->device->id;
1406 lun = cmd->device->lun;
1da177e4 1407
7c3df132 1408 if (!fcport) {
f4f051eb 1409 return ret;
7c3df132 1410 }
1da177e4 1411
4e98d3b8
AV		 1412 ret = fc_block_scsi_eh(cmd);
1413 if (ret != 0)
1414 return ret;
1415 ret = FAILED;
1416
7c3df132 1417 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1418 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1419
e315cd28 1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1421 ql_log(ql_log_fatal, vha, 0x8013,
1422 "Wait for hba online failed board disabled.\n");
f4f051eb 1423 goto eh_bus_reset_done;
1da177e4
LT		 1424 }
1425
ad537689
SK		 1426 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1427 ret = SUCCESS;
1428
f4f051eb
AV		 1429 if (ret == FAILED)
1430 goto eh_bus_reset_done;
1da177e4 1431
9a41a62b 1432 /* Flush outstanding commands. */
4d78c973 1433 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1434 QLA_SUCCESS) {
1435 ql_log(ql_log_warn, vha, 0x8014,
1436 "Wait for pending commands failed.\n");
9a41a62b 1437 ret = FAILED;
7c3df132 1438 }
1da177e4 1439
f4f051eb 1440eh_bus_reset_done:
7c3df132 1441 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1442 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1443 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1444
f4f051eb 1445 return ret;
1da177e4
LT		 1446}
1447
1448/**************************************************************************
1449* qla2xxx_eh_host_reset
1450*
1451* Description:
1452* The reset function will reset the Adapter.
1453*
1454* Input:
1455* cmd = Linux SCSI command packet of the command that cause the
1456* adapter reset.
1457*
1458* Returns:
1459* Either SUCCESS or FAILED.
1460*
1461* Note:
1462**************************************************************************/
e5f82ab8 1463static int
1da177e4
LT		 1464qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1465{
e315cd28 1466 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1467 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1468 int ret = FAILED;
9cb78c16
HR		 1469 unsigned int id;
1470 uint64_t lun;
e315cd28 1471 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1472
a465537a
SC		 1473 if (qla2x00_isp_reg_stat(ha)) {
1474 ql_log(ql_log_info, vha, 0x8041,
1475 "PCI/Register disconnect, exiting.\n");
1476 schedule_work(&ha->board_disable);
1477 return SUCCESS;
1478 }
1479
f4f051eb
AV		 1480 id = cmd->device->id;
1481 lun = cmd->device->lun;
f4f051eb 1482
7c3df132 1483 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1484 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1485
63ee7072
CD		 1486 /*
1487 * No point in issuing another reset if one is active. Also do not
1488 * attempt a reset if we are updating flash.
1489 */
1490 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1491 goto eh_host_reset_lock;
1da177e4 1492
e315cd28
AC		 1493 if (vha != base_vha) {
1494 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1495 goto eh_host_reset_lock;
e315cd28 1496 } else {
7ec0effd 1497 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1498 if (!qla82xx_fcoe_ctx_reset(vha)) {
1499 /* Ctx reset success */
1500 ret = SUCCESS;
1501 goto eh_host_reset_lock;
1502 }
1503 /* fall thru if ctx reset failed */
1504 }
68ca949c
AC		 1505 if (ha->wq)
1506 flush_workqueue(ha->wq);
1507
e315cd28 1508 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1509 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1510 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1511 /* failed. schedule dpc to try */
1512 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1513
7c3df132
SK		 1514 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1515 ql_log(ql_log_warn, vha, 0x802a,
1516 "wait for hba online failed.\n");
e315cd28 1517 goto eh_host_reset_lock;
7c3df132 1518 }
e315cd28
AC		 1519 }
1520 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1521 }
1da177e4 1522
e315cd28 1523 /* Waiting for command to be returned to OS.*/
4d78c973 1524 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1525 QLA_SUCCESS)
f4f051eb 1526 ret = SUCCESS;
1da177e4 1527
f4f051eb 1528eh_host_reset_lock:
cfb0919c 1529 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1530 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1531 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1532
f4f051eb
AV		 1533 return ret;
1534}
1da177e4
LT		 1535
1536/*
1537* qla2x00_loop_reset
1538* Issue loop reset.
1539*
1540* Input:
1541* ha = adapter block pointer.
1542*
1543* Returns:
1544* 0 = success
1545*/
a4722cf2 1546int
e315cd28 1547qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1548{
0c8c39af 1549 int ret;
bdf79621 1550 struct fc_port *fcport;
e315cd28 1551 struct qla_hw_data *ha = vha->hw;
1da177e4 1552
5854771e
AB		 1553 if (IS_QLAFX00(ha)) {
1554 return qlafx00_loop_reset(vha);
1555 }
1556
f4c496c1 1557 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1558 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1559 if (fcport->port_type != FCT_TARGET)
1560 continue;
1561
1562 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1563 if (ret != QLA_SUCCESS) {
7c3df132 1564 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1565 "Bus Reset failed: Reset=%d "
7c3df132 1566 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1567 }
1568 }
1569 }
1570
8ae6d9c7 1571
6246b8a1 1572 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1573 atomic_set(&vha->loop_state, LOOP_DOWN);
1574 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1575 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1576 ret = qla2x00_full_login_lip(vha);
0c8c39af 1577 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1578 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1579 "full_login_lip=%d.\n", ret);
749af3d5 1580 }
0c8c39af
AV		 1581 }
1582
0d6e61bc 1583 if (ha->flags.enable_lip_reset) {
e315cd28 1584 ret = qla2x00_lip_reset(vha);
ad537689 1585 if (ret != QLA_SUCCESS)
7c3df132
SK		 1586 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1587 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1588 }
1589
1da177e4 1590 /* Issue marker command only when we are going to start the I/O */
e315cd28 1591 vha->marker_needed = 1;
1da177e4 1592
0c8c39af 1593 return QLA_SUCCESS;
1da177e4
LT		 1594}
1595
df4bf0bb 1596void
e315cd28 1597qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1598{
73208dfd 1599 int que, cnt;
df4bf0bb
AV		 1600 unsigned long flags;
1601 srb_t *sp;
e315cd28 1602 struct qla_hw_data *ha = vha->hw;
73208dfd 1603 struct req_que *req;
df4bf0bb 1604
c0cb4496
AE		 1605 qlt_host_reset_handler(ha);
1606
df4bf0bb 1607 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1608 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1609 req = ha->req_q_map[que];
73208dfd
AC		 1610 if (!req)
1611 continue;
8d93f550
CD		 1612 if (!req->outstanding_cmds)
1613 continue;
1614 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1615 sp = req->outstanding_cmds[cnt];
e612d465 1616 if (sp) {
c733ab35
MFO		 1617 /* Don't abort commands in adapter during EEH
1618 * recovery as it's not accessible/responding.
1535aa75 1619 */
2780f3c8 1620 if (GET_CMD_SP(sp) && !ha->flags.eeh_busy) {
c733ab35
MFO		 1621 /* Get a reference to the sp and drop the lock.
1622 * The reference ensures this sp->done() call
1623 * - and not the call in qla2xxx_eh_abort() -
1624 * ends the SCSI command (with result 'res').
1625 */
1626 sp_get(sp);
1627 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1628 qla2xxx_eh_abort(GET_CMD_SP(sp));
1629 spin_lock_irqsave(&ha->hardware_lock, flags);
1630 }
73208dfd 1631 req->outstanding_cmds[cnt] = NULL;
9ba56b95 1632 sp->done(vha, sp, res);
73208dfd 1633 }
df4bf0bb
AV		 1634 }
1635 }
1636 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1637}
1638
f4f051eb
AV		 1639static int
1640qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1641{
bdf79621 1642 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1643
19a7b4ae 1644 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1645 return -ENXIO;
bdf79621 1646
19a7b4ae 1647 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1648
f4f051eb
AV		 1649 return 0;
1650}
1da177e4 1651
f4f051eb
AV		 1652static int
1653qla2xxx_slave_configure(struct scsi_device *sdev)
1654{
e315cd28 1655 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1656 struct req_que *req = vha->req;
8482e118 1657
9e522cd8
AE		 1658 if (IS_T10_PI_CAPABLE(vha->hw))
1659 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1660
db5ed4df 1661 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1662 return 0;
1663}
1da177e4 1664
f4f051eb
AV		 1665static void
1666qla2xxx_slave_destroy(struct scsi_device *sdev)
1667{
1668 sdev->hostdata = NULL;
1da177e4
LT		 1669}
1670
1671/**
1672 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1673 * @ha: HA context
1674 *
1675 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1676 * supported addressing method.
1677 */
1678static void
53303c42 1679qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1680{
7524f9b9 1681 /* Assume a 32bit DMA mask. */
1da177e4 1682 ha->flags.enable_64bit_addressing = 0;
1da177e4 1683
6a35528a 1684 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1685 /* Any upper-dword bits set? */
1686 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1687 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1688 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1689 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1690 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1691 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1692 return;
1da177e4 1693 }
1da177e4 1694 }
7524f9b9 1695
284901a9
YH		 1696 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1697 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1698}
1699
fd34f556 1700static void
e315cd28 1701qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1702{
1703 unsigned long flags = 0;
1704 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1705
1706 spin_lock_irqsave(&ha->hardware_lock, flags);
1707 ha->interrupts_on = 1;
1708 /* enable risc and host interrupts */
1709 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1710 RD_REG_WORD(&reg->ictrl);
1711 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1712
1713}
1714
1715static void
e315cd28 1716qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1717{
1718 unsigned long flags = 0;
1719 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1720
1721 spin_lock_irqsave(&ha->hardware_lock, flags);
1722 ha->interrupts_on = 0;
1723 /* disable risc and host interrupts */
1724 WRT_REG_WORD(&reg->ictrl, 0);
1725 RD_REG_WORD(&reg->ictrl);
1726 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1727}
1728
1729static void
e315cd28 1730qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1731{
1732 unsigned long flags = 0;
1733 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1734
1735 spin_lock_irqsave(&ha->hardware_lock, flags);
1736 ha->interrupts_on = 1;
1737 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1738 RD_REG_DWORD(&reg->ictrl);
1739 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1740}
1741
1742static void
e315cd28 1743qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1744{
1745 unsigned long flags = 0;
1746 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1747
124f85e6
AV		 1748 if (IS_NOPOLLING_TYPE(ha))
1749 return;
fd34f556
AV		 1750 spin_lock_irqsave(&ha->hardware_lock, flags);
1751 ha->interrupts_on = 0;
1752 WRT_REG_DWORD(&reg->ictrl, 0);
1753 RD_REG_DWORD(&reg->ictrl);
1754 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1755}
1756
706f457d
GM		 1757static int
1758qla2x00_iospace_config(struct qla_hw_data *ha)
1759{
1760 resource_size_t pio;
1761 uint16_t msix;
706f457d 1762
706f457d
GM		 1763 if (pci_request_selected_regions(ha->pdev, ha->bars,
1764 QLA2XXX_DRIVER_NAME)) {
1765 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1766 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1767 pci_name(ha->pdev));
1768 goto iospace_error_exit;
1769 }
1770 if (!(ha->bars & 1))
1771 goto skip_pio;
1772
1773 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1774 pio = pci_resource_start(ha->pdev, 0);
1775 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1776 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1777 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1778 "Invalid pci I/O region size (%s).\n",
1779 pci_name(ha->pdev));
1780 pio = 0;
1781 }
1782 } else {
1783 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1784 "Region #0 no a PIO resource (%s).\n",
1785 pci_name(ha->pdev));
1786 pio = 0;
1787 }
1788 ha->pio_address = pio;
1789 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1790 "PIO address=%llu.\n",
1791 (unsigned long long)ha->pio_address);
1792
1793skip_pio:
1794 /* Use MMIO operations for all accesses. */
1795 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1796 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1797 "Region #1 not an MMIO resource (%s), aborting.\n",
1798 pci_name(ha->pdev));
1799 goto iospace_error_exit;
1800 }
1801 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1802 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1803 "Invalid PCI mem region size (%s), aborting.\n",
1804 pci_name(ha->pdev));
1805 goto iospace_error_exit;
1806 }
1807
1808 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1809 if (!ha->iobase) {
1810 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1811 "Cannot remap MMIO (%s), aborting.\n",
1812 pci_name(ha->pdev));
1813 goto iospace_error_exit;
1814 }
1815
1816 /* Determine queue resources */
1817 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1818 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1819 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1820 goto mqiobase_exit;
1821
1822 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1823 pci_resource_len(ha->pdev, 3));
1824 if (ha->mqiobase) {
1825 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1826 "MQIO Base=%p.\n", ha->mqiobase);
1827 /* Read MSIX vector size of the board */
1828 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1829 ha->msix_count = msix + 1;
706f457d 1830 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1831 /* MB interrupt uses 1 vector */
1832 ha->max_req_queues = ha->msix_count - 1;
1833 ha->max_rsp_queues = ha->max_req_queues;
1834 /* Queue pairs is the max value minus the base queue pair */
1835 ha->max_qpairs = ha->max_rsp_queues - 1;
1836 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1837 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1838
706f457d 1839 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1840 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1841 } else
1842 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1843 "BAR 3 not enabled.\n");
1844
1845mqiobase_exit:
706f457d 1846 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1847 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1848 return (0);
1849
1850iospace_error_exit:
1851 return (-ENOMEM);
1852}
1853
1854
6246b8a1
GM		 1855static int
1856qla83xx_iospace_config(struct qla_hw_data *ha)
1857{
1858 uint16_t msix;
6246b8a1
GM		 1859
1860 if (pci_request_selected_regions(ha->pdev, ha->bars,
1861 QLA2XXX_DRIVER_NAME)) {
1862 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
1863 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1864 pci_name(ha->pdev));
1865
1866 goto iospace_error_exit;
1867 }
1868
1869 /* Use MMIO operations for all accesses. */
1870 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1871 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
1872 "Invalid pci I/O region size (%s).\n",
1873 pci_name(ha->pdev));
1874 goto iospace_error_exit;
1875 }
1876 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1877 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
1878 "Invalid PCI mem region size (%s), aborting\n",
1879 pci_name(ha->pdev));
1880 goto iospace_error_exit;
1881 }
1882
1883 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
1884 if (!ha->iobase) {
1885 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
1886 "Cannot remap MMIO (%s), aborting.\n",
1887 pci_name(ha->pdev));
1888 goto iospace_error_exit;
1889 }
1890
1891 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
1892 /* 83XX 26XX always use MQ type access for queues
1893 * - mbar 2, a.k.a region 4 */
1894 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1895 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 1896 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
1897 pci_resource_len(ha->pdev, 4));
1898
1899 if (!ha->mqiobase) {
1900 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
1901 "BAR2/region4 not enabled\n");
1902 goto mqiobase_exit;
1903 }
1904
1905 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
1906 pci_resource_len(ha->pdev, 2));
1907 if (ha->msixbase) {
1908 /* Read MSIX vector size of the board */
1909 pci_read_config_word(ha->pdev,
1910 QLA_83XX_PCI_MSIX_CONTROL, &msix);
d7459527 1911 ha->msix_count = msix + 1;
093df737
QT		 1912 /*
1913 * By default, driver uses at least two msix vectors
1914 * (default & rspq)
1915 */
d7459527
MH		 1916 if (ql2xmqsupport) {
1917 /* MB interrupt uses 1 vector */
1918 ha->max_req_queues = ha->msix_count - 1;
1919 ha->max_rsp_queues = ha->max_req_queues;
093df737
QT		 1920
1921 /* ATIOQ needs 1 vector. That's 1 less QPair */
1922 if (QLA_TGT_MODE_ENABLED())
1923 ha->max_req_queues--;
1924
d7459527
MH		 1925 /* Queue pairs is the max value minus
1926 * the base queue pair */
1927 ha->max_qpairs = ha->max_req_queues - 1;
d7459527
MH		 1928 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0190,
1929 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 1930 }
1931 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 1932 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 1933 } else
1934 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
1935 "BAR 1 not enabled.\n");
1936
1937mqiobase_exit:
6246b8a1 1938 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 1939 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 1940 return 0;
1941
1942iospace_error_exit:
1943 return -ENOMEM;
1944}
1945
fd34f556
AV		 1946static struct isp_operations qla2100_isp_ops = {
1947 .pci_config = qla2100_pci_config,
1948 .reset_chip = qla2x00_reset_chip,
1949 .chip_diag = qla2x00_chip_diag,
1950 .config_rings = qla2x00_config_rings,
1951 .reset_adapter = qla2x00_reset_adapter,
1952 .nvram_config = qla2x00_nvram_config,
1953 .update_fw_options = qla2x00_update_fw_options,
1954 .load_risc = qla2x00_load_risc,
1955 .pci_info_str = qla2x00_pci_info_str,
1956 .fw_version_str = qla2x00_fw_version_str,
1957 .intr_handler = qla2100_intr_handler,
1958 .enable_intrs = qla2x00_enable_intrs,
1959 .disable_intrs = qla2x00_disable_intrs,
1960 .abort_command = qla2x00_abort_command,
523ec773
AV		 1961 .target_reset = qla2x00_abort_target,
1962 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 1963 .fabric_login = qla2x00_login_fabric,
1964 .fabric_logout = qla2x00_fabric_logout,
1965 .calc_req_entries = qla2x00_calc_iocbs_32,
1966 .build_iocbs = qla2x00_build_scsi_iocbs_32,
1967 .prep_ms_iocb = qla2x00_prep_ms_iocb,
1968 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
1969 .read_nvram = qla2x00_read_nvram_data,
1970 .write_nvram = qla2x00_write_nvram_data,
1971 .fw_dump = qla2100_fw_dump,
1972 .beacon_on = NULL,
1973 .beacon_off = NULL,
1974 .beacon_blink = NULL,
1975 .read_optrom = qla2x00_read_optrom_data,
1976 .write_optrom = qla2x00_write_optrom_data,
1977 .get_flash_version = qla2x00_get_flash_version,
e315cd28 1978 .start_scsi = qla2x00_start_scsi,
d7459527 1979 .start_scsi_mq = NULL,
a9083016 1980 .abort_isp = qla2x00_abort_isp,
706f457d 1981 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 1982 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 1983};
1984
1985static struct isp_operations qla2300_isp_ops = {
1986 .pci_config = qla2300_pci_config,
1987 .reset_chip = qla2x00_reset_chip,
1988 .chip_diag = qla2x00_chip_diag,
1989 .config_rings = qla2x00_config_rings,
1990 .reset_adapter = qla2x00_reset_adapter,
1991 .nvram_config = qla2x00_nvram_config,
1992 .update_fw_options = qla2x00_update_fw_options,
1993 .load_risc = qla2x00_load_risc,
1994 .pci_info_str = qla2x00_pci_info_str,
1995 .fw_version_str = qla2x00_fw_version_str,
1996 .intr_handler = qla2300_intr_handler,
1997 .enable_intrs = qla2x00_enable_intrs,
1998 .disable_intrs = qla2x00_disable_intrs,
1999 .abort_command = qla2x00_abort_command,
523ec773
AV		 2000 .target_reset = qla2x00_abort_target,
2001 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2002 .fabric_login = qla2x00_login_fabric,
2003 .fabric_logout = qla2x00_fabric_logout,
2004 .calc_req_entries = qla2x00_calc_iocbs_32,
2005 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2006 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2007 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2008 .read_nvram = qla2x00_read_nvram_data,
2009 .write_nvram = qla2x00_write_nvram_data,
2010 .fw_dump = qla2300_fw_dump,
2011 .beacon_on = qla2x00_beacon_on,
2012 .beacon_off = qla2x00_beacon_off,
2013 .beacon_blink = qla2x00_beacon_blink,
2014 .read_optrom = qla2x00_read_optrom_data,
2015 .write_optrom = qla2x00_write_optrom_data,
2016 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2017 .start_scsi = qla2x00_start_scsi,
d7459527 2018 .start_scsi_mq = NULL,
a9083016 2019 .abort_isp = qla2x00_abort_isp,
7ec0effd 2020 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2021 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2022};
2023
2024static struct isp_operations qla24xx_isp_ops = {
2025 .pci_config = qla24xx_pci_config,
2026 .reset_chip = qla24xx_reset_chip,
2027 .chip_diag = qla24xx_chip_diag,
2028 .config_rings = qla24xx_config_rings,
2029 .reset_adapter = qla24xx_reset_adapter,
2030 .nvram_config = qla24xx_nvram_config,
2031 .update_fw_options = qla24xx_update_fw_options,
2032 .load_risc = qla24xx_load_risc,
2033 .pci_info_str = qla24xx_pci_info_str,
2034 .fw_version_str = qla24xx_fw_version_str,
2035 .intr_handler = qla24xx_intr_handler,
2036 .enable_intrs = qla24xx_enable_intrs,
2037 .disable_intrs = qla24xx_disable_intrs,
2038 .abort_command = qla24xx_abort_command,
523ec773
AV		 2039 .target_reset = qla24xx_abort_target,
2040 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2041 .fabric_login = qla24xx_login_fabric,
2042 .fabric_logout = qla24xx_fabric_logout,
2043 .calc_req_entries = NULL,
2044 .build_iocbs = NULL,
2045 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2046 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2047 .read_nvram = qla24xx_read_nvram_data,
2048 .write_nvram = qla24xx_write_nvram_data,
2049 .fw_dump = qla24xx_fw_dump,
2050 .beacon_on = qla24xx_beacon_on,
2051 .beacon_off = qla24xx_beacon_off,
2052 .beacon_blink = qla24xx_beacon_blink,
2053 .read_optrom = qla24xx_read_optrom_data,
2054 .write_optrom = qla24xx_write_optrom_data,
2055 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2056 .start_scsi = qla24xx_start_scsi,
d7459527 2057 .start_scsi_mq = NULL,
a9083016 2058 .abort_isp = qla2x00_abort_isp,
7ec0effd 2059 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2060 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2061};
2062
c3a2f0df
AV		 2063static struct isp_operations qla25xx_isp_ops = {
2064 .pci_config = qla25xx_pci_config,
2065 .reset_chip = qla24xx_reset_chip,
2066 .chip_diag = qla24xx_chip_diag,
2067 .config_rings = qla24xx_config_rings,
2068 .reset_adapter = qla24xx_reset_adapter,
2069 .nvram_config = qla24xx_nvram_config,
2070 .update_fw_options = qla24xx_update_fw_options,
2071 .load_risc = qla24xx_load_risc,
2072 .pci_info_str = qla24xx_pci_info_str,
2073 .fw_version_str = qla24xx_fw_version_str,
2074 .intr_handler = qla24xx_intr_handler,
2075 .enable_intrs = qla24xx_enable_intrs,
2076 .disable_intrs = qla24xx_disable_intrs,
2077 .abort_command = qla24xx_abort_command,
523ec773
AV		 2078 .target_reset = qla24xx_abort_target,
2079 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2080 .fabric_login = qla24xx_login_fabric,
2081 .fabric_logout = qla24xx_fabric_logout,
2082 .calc_req_entries = NULL,
2083 .build_iocbs = NULL,
2084 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2085 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2086 .read_nvram = qla25xx_read_nvram_data,
2087 .write_nvram = qla25xx_write_nvram_data,
2088 .fw_dump = qla25xx_fw_dump,
2089 .beacon_on = qla24xx_beacon_on,
2090 .beacon_off = qla24xx_beacon_off,
2091 .beacon_blink = qla24xx_beacon_blink,
338c9161 2092 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2093 .write_optrom = qla24xx_write_optrom_data,
2094 .get_flash_version = qla24xx_get_flash_version,
bad75002 2095 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2096 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2097 .abort_isp = qla2x00_abort_isp,
7ec0effd 2098 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2099 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2100};
2101
3a03eb79
AV		 2102static struct isp_operations qla81xx_isp_ops = {
2103 .pci_config = qla25xx_pci_config,
2104 .reset_chip = qla24xx_reset_chip,
2105 .chip_diag = qla24xx_chip_diag,
2106 .config_rings = qla24xx_config_rings,
2107 .reset_adapter = qla24xx_reset_adapter,
2108 .nvram_config = qla81xx_nvram_config,
2109 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2110 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2111 .pci_info_str = qla24xx_pci_info_str,
2112 .fw_version_str = qla24xx_fw_version_str,
2113 .intr_handler = qla24xx_intr_handler,
2114 .enable_intrs = qla24xx_enable_intrs,
2115 .disable_intrs = qla24xx_disable_intrs,
2116 .abort_command = qla24xx_abort_command,
2117 .target_reset = qla24xx_abort_target,
2118 .lun_reset = qla24xx_lun_reset,
2119 .fabric_login = qla24xx_login_fabric,
2120 .fabric_logout = qla24xx_fabric_logout,
2121 .calc_req_entries = NULL,
2122 .build_iocbs = NULL,
2123 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2124 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2125 .read_nvram = NULL,
2126 .write_nvram = NULL,
3a03eb79
AV		 2127 .fw_dump = qla81xx_fw_dump,
2128 .beacon_on = qla24xx_beacon_on,
2129 .beacon_off = qla24xx_beacon_off,
6246b8a1 2130 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2131 .read_optrom = qla25xx_read_optrom_data,
2132 .write_optrom = qla24xx_write_optrom_data,
2133 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2134 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2135 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2136 .abort_isp = qla2x00_abort_isp,
7ec0effd 2137 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2138 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2139};
2140
2141static struct isp_operations qla82xx_isp_ops = {
2142 .pci_config = qla82xx_pci_config,
2143 .reset_chip = qla82xx_reset_chip,
2144 .chip_diag = qla24xx_chip_diag,
2145 .config_rings = qla82xx_config_rings,
2146 .reset_adapter = qla24xx_reset_adapter,
2147 .nvram_config = qla81xx_nvram_config,
2148 .update_fw_options = qla24xx_update_fw_options,
2149 .load_risc = qla82xx_load_risc,
9d55ca66 2150 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2151 .fw_version_str = qla24xx_fw_version_str,
2152 .intr_handler = qla82xx_intr_handler,
2153 .enable_intrs = qla82xx_enable_intrs,
2154 .disable_intrs = qla82xx_disable_intrs,
2155 .abort_command = qla24xx_abort_command,
2156 .target_reset = qla24xx_abort_target,
2157 .lun_reset = qla24xx_lun_reset,
2158 .fabric_login = qla24xx_login_fabric,
2159 .fabric_logout = qla24xx_fabric_logout,
2160 .calc_req_entries = NULL,
2161 .build_iocbs = NULL,
2162 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2163 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2164 .read_nvram = qla24xx_read_nvram_data,
2165 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2166 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2167 .beacon_on = qla82xx_beacon_on,
2168 .beacon_off = qla82xx_beacon_off,
2169 .beacon_blink = NULL,
a9083016
GM		 2170 .read_optrom = qla82xx_read_optrom_data,
2171 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2172 .get_flash_version = qla82xx_get_flash_version,
a9083016 2173 .start_scsi = qla82xx_start_scsi,
d7459527 2174 .start_scsi_mq = NULL,
a9083016 2175 .abort_isp = qla82xx_abort_isp,
706f457d 2176 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2177 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2178};
2179
7ec0effd
AD		 2180static struct isp_operations qla8044_isp_ops = {
2181 .pci_config = qla82xx_pci_config,
2182 .reset_chip = qla82xx_reset_chip,
2183 .chip_diag = qla24xx_chip_diag,
2184 .config_rings = qla82xx_config_rings,
2185 .reset_adapter = qla24xx_reset_adapter,
2186 .nvram_config = qla81xx_nvram_config,
2187 .update_fw_options = qla24xx_update_fw_options,
2188 .load_risc = qla82xx_load_risc,
2189 .pci_info_str = qla24xx_pci_info_str,
2190 .fw_version_str = qla24xx_fw_version_str,
2191 .intr_handler = qla8044_intr_handler,
2192 .enable_intrs = qla82xx_enable_intrs,
2193 .disable_intrs = qla82xx_disable_intrs,
2194 .abort_command = qla24xx_abort_command,
2195 .target_reset = qla24xx_abort_target,
2196 .lun_reset = qla24xx_lun_reset,
2197 .fabric_login = qla24xx_login_fabric,
2198 .fabric_logout = qla24xx_fabric_logout,
2199 .calc_req_entries = NULL,
2200 .build_iocbs = NULL,
2201 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2202 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2203 .read_nvram = NULL,
2204 .write_nvram = NULL,
a1b23c5a 2205 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2206 .beacon_on = qla82xx_beacon_on,
2207 .beacon_off = qla82xx_beacon_off,
2208 .beacon_blink = NULL,
888e639d 2209 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2210 .write_optrom = qla8044_write_optrom_data,
2211 .get_flash_version = qla82xx_get_flash_version,
2212 .start_scsi = qla82xx_start_scsi,
d7459527 2213 .start_scsi_mq = NULL,
7ec0effd
AD		 2214 .abort_isp = qla8044_abort_isp,
2215 .iospace_config = qla82xx_iospace_config,
2216 .initialize_adapter = qla2x00_initialize_adapter,
2217};
2218
6246b8a1
GM		 2219static struct isp_operations qla83xx_isp_ops = {
2220 .pci_config = qla25xx_pci_config,
2221 .reset_chip = qla24xx_reset_chip,
2222 .chip_diag = qla24xx_chip_diag,
2223 .config_rings = qla24xx_config_rings,
2224 .reset_adapter = qla24xx_reset_adapter,
2225 .nvram_config = qla81xx_nvram_config,
2226 .update_fw_options = qla81xx_update_fw_options,
2227 .load_risc = qla81xx_load_risc,
2228 .pci_info_str = qla24xx_pci_info_str,
2229 .fw_version_str = qla24xx_fw_version_str,
2230 .intr_handler = qla24xx_intr_handler,
2231 .enable_intrs = qla24xx_enable_intrs,
2232 .disable_intrs = qla24xx_disable_intrs,
2233 .abort_command = qla24xx_abort_command,
2234 .target_reset = qla24xx_abort_target,
2235 .lun_reset = qla24xx_lun_reset,
2236 .fabric_login = qla24xx_login_fabric,
2237 .fabric_logout = qla24xx_fabric_logout,
2238 .calc_req_entries = NULL,
2239 .build_iocbs = NULL,
2240 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2241 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2242 .read_nvram = NULL,
2243 .write_nvram = NULL,
2244 .fw_dump = qla83xx_fw_dump,
2245 .beacon_on = qla24xx_beacon_on,
2246 .beacon_off = qla24xx_beacon_off,
2247 .beacon_blink = qla83xx_beacon_blink,
2248 .read_optrom = qla25xx_read_optrom_data,
2249 .write_optrom = qla24xx_write_optrom_data,
2250 .get_flash_version = qla24xx_get_flash_version,
2251 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2252 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2253 .abort_isp = qla2x00_abort_isp,
2254 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2255 .initialize_adapter = qla2x00_initialize_adapter,
2256};
2257
2258static struct isp_operations qlafx00_isp_ops = {
2259 .pci_config = qlafx00_pci_config,
2260 .reset_chip = qlafx00_soft_reset,
2261 .chip_diag = qlafx00_chip_diag,
2262 .config_rings = qlafx00_config_rings,
2263 .reset_adapter = qlafx00_soft_reset,
2264 .nvram_config = NULL,
2265 .update_fw_options = NULL,
2266 .load_risc = NULL,
2267 .pci_info_str = qlafx00_pci_info_str,
2268 .fw_version_str = qlafx00_fw_version_str,
2269 .intr_handler = qlafx00_intr_handler,
2270 .enable_intrs = qlafx00_enable_intrs,
2271 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2272 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2273 .target_reset = qlafx00_abort_target,
2274 .lun_reset = qlafx00_lun_reset,
2275 .fabric_login = NULL,
2276 .fabric_logout = NULL,
2277 .calc_req_entries = NULL,
2278 .build_iocbs = NULL,
2279 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2280 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2281 .read_nvram = qla24xx_read_nvram_data,
2282 .write_nvram = qla24xx_write_nvram_data,
2283 .fw_dump = NULL,
2284 .beacon_on = qla24xx_beacon_on,
2285 .beacon_off = qla24xx_beacon_off,
2286 .beacon_blink = NULL,
2287 .read_optrom = qla24xx_read_optrom_data,
2288 .write_optrom = qla24xx_write_optrom_data,
2289 .get_flash_version = qla24xx_get_flash_version,
2290 .start_scsi = qlafx00_start_scsi,
d7459527 2291 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2292 .abort_isp = qlafx00_abort_isp,
2293 .iospace_config = qlafx00_iospace_config,
2294 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2295};
2296
f73cb695
CD		 2297static struct isp_operations qla27xx_isp_ops = {
2298 .pci_config = qla25xx_pci_config,
2299 .reset_chip = qla24xx_reset_chip,
2300 .chip_diag = qla24xx_chip_diag,
2301 .config_rings = qla24xx_config_rings,
2302 .reset_adapter = qla24xx_reset_adapter,
2303 .nvram_config = qla81xx_nvram_config,
2304 .update_fw_options = qla81xx_update_fw_options,
2305 .load_risc = qla81xx_load_risc,
2306 .pci_info_str = qla24xx_pci_info_str,
2307 .fw_version_str = qla24xx_fw_version_str,
2308 .intr_handler = qla24xx_intr_handler,
2309 .enable_intrs = qla24xx_enable_intrs,
2310 .disable_intrs = qla24xx_disable_intrs,
2311 .abort_command = qla24xx_abort_command,
2312 .target_reset = qla24xx_abort_target,
2313 .lun_reset = qla24xx_lun_reset,
2314 .fabric_login = qla24xx_login_fabric,
2315 .fabric_logout = qla24xx_fabric_logout,
2316 .calc_req_entries = NULL,
2317 .build_iocbs = NULL,
2318 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2319 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2320 .read_nvram = NULL,
2321 .write_nvram = NULL,
2322 .fw_dump = qla27xx_fwdump,
2323 .beacon_on = qla24xx_beacon_on,
2324 .beacon_off = qla24xx_beacon_off,
2325 .beacon_blink = qla83xx_beacon_blink,
2326 .read_optrom = qla25xx_read_optrom_data,
2327 .write_optrom = qla24xx_write_optrom_data,
2328 .get_flash_version = qla24xx_get_flash_version,
2329 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2330 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2331 .abort_isp = qla2x00_abort_isp,
2332 .iospace_config = qla83xx_iospace_config,
2333 .initialize_adapter = qla2x00_initialize_adapter,
2334};
2335
ea5b6382 2336static inline void
e315cd28 2337qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2338{
2339 ha->device_type = DT_EXTENDED_IDS;
2340 switch (ha->pdev->device) {
2341 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2342 ha->isp_type |= DT_ISP2100;
ea5b6382 2343 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2344 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2345 break;
2346 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2347 ha->isp_type |= DT_ISP2200;
ea5b6382 2348 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2349 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2350 break;
2351 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2352 ha->isp_type |= DT_ISP2300;
4a59f71d 2353 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2354 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2355 break;
2356 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2357 ha->isp_type |= DT_ISP2312;
4a59f71d 2358 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2359 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2360 break;
2361 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2362 ha->isp_type |= DT_ISP2322;
4a59f71d 2363 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2364 if (ha->pdev->subsystem_vendor == 0x1028 &&
2365 ha->pdev->subsystem_device == 0x0170)
2366 ha->device_type |= DT_OEM_001;
441d1072 2367 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2368 break;
2369 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2370 ha->isp_type |= DT_ISP6312;
441d1072 2371 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2372 break;
2373 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2374 ha->isp_type |= DT_ISP6322;
441d1072 2375 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2376 break;
2377 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2378 ha->isp_type |= DT_ISP2422;
4a59f71d 2379 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2380 ha->device_type |= DT_FWI2;
c76f2c01 2381 ha->device_type |= DT_IIDMA;
441d1072 2382 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2383 break;
2384 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2385 ha->isp_type |= DT_ISP2432;
4a59f71d 2386 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2387 ha->device_type |= DT_FWI2;
c76f2c01 2388 ha->device_type |= DT_IIDMA;
441d1072 2389 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2390 break;
4d4df193 2391 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2392 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2393 ha->device_type |= DT_ZIO_SUPPORTED;
2394 ha->device_type |= DT_FWI2;
2395 ha->device_type |= DT_IIDMA;
2396 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2397 break;
044cc6c8 2398 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2399 ha->isp_type |= DT_ISP5422;
e428924c 2400 ha->device_type |= DT_FWI2;
441d1072 2401 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2402 break;
044cc6c8 2403 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2404 ha->isp_type |= DT_ISP5432;
e428924c 2405 ha->device_type |= DT_FWI2;
441d1072 2406 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2407 break;
c3a2f0df 2408 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2409 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2410 ha->device_type |= DT_ZIO_SUPPORTED;
2411 ha->device_type |= DT_FWI2;
2412 ha->device_type |= DT_IIDMA;
441d1072 2413 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2414 break;
3a03eb79 2415 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2416 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2417 ha->device_type |= DT_ZIO_SUPPORTED;
2418 ha->device_type |= DT_FWI2;
2419 ha->device_type |= DT_IIDMA;
2420 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2421 break;
a9083016 2422 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2423 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2424 ha->device_type |= DT_ZIO_SUPPORTED;
2425 ha->device_type |= DT_FWI2;
2426 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2427 /* Initialize 82XX ISP flags */
2428 qla82xx_init_flags(ha);
2429 break;
7ec0effd 2430 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2431 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2432 ha->device_type |= DT_ZIO_SUPPORTED;
2433 ha->device_type |= DT_FWI2;
2434 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2435 /* Initialize 82XX ISP flags */
2436 qla82xx_init_flags(ha);
2437 break;
6246b8a1 2438 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2439 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2440 ha->device_type |= DT_ZIO_SUPPORTED;
2441 ha->device_type |= DT_FWI2;
2442 ha->device_type |= DT_IIDMA;
2443 ha->device_type |= DT_T10_PI;
2444 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2445 break;
2446 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2447 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2448 ha->device_type |= DT_ZIO_SUPPORTED;
2449 ha->device_type |= DT_FWI2;
2450 ha->device_type |= DT_IIDMA;
2451 ha->device_type |= DT_T10_PI;
2452 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2453 break;
8ae6d9c7 2454 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2455 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2456 break;
f73cb695 2457 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2458 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2459 ha->device_type |= DT_ZIO_SUPPORTED;
2460 ha->device_type |= DT_FWI2;
2461 ha->device_type |= DT_IIDMA;
8ce3f570 2462 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2463 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2464 break;
2c5bbbb2 2465 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2466 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2467 ha->device_type |= DT_ZIO_SUPPORTED;
2468 ha->device_type |= DT_FWI2;
2469 ha->device_type |= DT_IIDMA;
8ce3f570 2470 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2471 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2472 break;
2b48992f 2473 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2474 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2475 ha->device_type |= DT_ZIO_SUPPORTED;
2476 ha->device_type |= DT_FWI2;
2477 ha->device_type |= DT_IIDMA;
8ce3f570 2478 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2479 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2480 break;
ea5b6382 2481 }
e5b68a61 2482
a9083016 2483 if (IS_QLA82XX(ha))
43a9c38b 2484 ha->port_no = ha->portnum & 1;
f73cb695 2485 else {
a9083016
GM		 2486 /* Get adapter physical port no from interrupt pin register. */
2487 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2488 if (IS_QLA27XX(ha))
2489 ha->port_no--;
2490 else
2491 ha->port_no = !(ha->port_no & 1);
2492 }
a9083016 2493
7c3df132 2494 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2495 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2496 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2497}
2498
1e99e33a
AV		 2499static void
2500qla2xxx_scan_start(struct Scsi_Host *shost)
2501{
e315cd28 2502 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2503
cbc8eb67
AV		 2504 if (vha->hw->flags.running_gold_fw)
2505 return;
2506
e315cd28
AC		 2507 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2508 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2509 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2510 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2511}
2512
2513static int
2514qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2515{
e315cd28 2516 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2517
a5dd506e
BK		 2518 if (test_bit(UNLOADING, &vha->dpc_flags))
2519 return 1;
e315cd28 2520 if (!vha->host)
1e99e33a 2521 return 1;
e315cd28 2522 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2523 return 1;
2524
e315cd28 2525 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2526}
2527
1da177e4
LT		 2528/*
2529 * PCI driver interface
2530 */
6f039790 2531static int
7ee61397 2532qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2533{
a1541d5a 2534 int ret = -ENODEV;
1da177e4 2535 struct Scsi_Host *host;
e315cd28
AC		 2536 scsi_qla_host_t *base_vha = NULL;
2537 struct qla_hw_data *ha;
29856e28 2538 char pci_info[30];
7d613ac6 2539 char fw_str[30], wq_name[30];
5433383e 2540 struct scsi_host_template *sht;
642ef983 2541 int bars, mem_only = 0;
e315cd28 2542 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2543 struct req_que *req = NULL;
2544 struct rsp_que *rsp = NULL;
5601236b 2545 int i;
d7459527 2546
285d0321 2547 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2548 sht = &qla2xxx_driver_template;
5433383e 2549 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2550 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2551 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2552 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2553 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2554 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2555 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2556 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2557 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2558 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2559 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2560 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2561 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2562 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2563 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2564 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2565 mem_only = 1;
7c3df132
SK		 2566 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2567 "Mem only adapter.\n");
285d0321 2568 }
7c3df132
SK		 2569 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2570 "Bars=%d.\n", bars);
285d0321 2571
09483916
BH		 2572 if (mem_only) {
2573 if (pci_enable_device_mem(pdev))
2574 goto probe_out;
2575 } else {
2576 if (pci_enable_device(pdev))
2577 goto probe_out;
2578 }
285d0321 2579
0927678f
JB		 2580 /* This may fail but that's ok */
2581 pci_enable_pcie_error_reporting(pdev);
285d0321 2582
e315cd28
AC		 2583 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2584 if (!ha) {
7c3df132
SK		 2585 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2586 "Unable to allocate memory for ha.\n");
e315cd28 2587 goto probe_out;
1da177e4 2588 }
7c3df132
SK		 2589 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2590 "Memory allocated for ha=%p.\n", ha);
e315cd28 2591 ha->pdev = pdev;
2d70c103 2592 ha->tgt.enable_class_2 = ql2xenableclass2;
33e79977
QT		 2593 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2594 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2595 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2596 spin_lock_init(&ha->tgt.atio_lock);
2597
1da177e4
LT		 2598
2599 /* Clear our data area */
285d0321 2600 ha->bars = bars;
09483916 2601 ha->mem_only = mem_only;
df4bf0bb 2602 spin_lock_init(&ha->hardware_lock);
339aa70e 2603 spin_lock_init(&ha->vport_slock);
a9b6f722 2604 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2605 mutex_init(&ha->optrom_mutex);
1da177e4 2606
ea5b6382
AV		 2607 /* Set ISP-type information. */
2608 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2609
2610 /* Set EEH reset type to fundamental if required by hba */
95676112 2611 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2612 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2613 pdev->needs_freset = 1;
ca79cf66 2614
cba1e47f
CD		 2615 ha->prev_topology = 0;
2616 ha->init_cb_size = sizeof(init_cb_t);
2617 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2618 ha->optrom_size = OPTROM_SIZE_2300;
2619
abbd8870 2620 /* Assign ISP specific operations. */
1da177e4 2621 if (IS_QLA2100(ha)) {
642ef983 2622 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2623 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2624 req_length = REQUEST_ENTRY_CNT_2100;
2625 rsp_length = RESPONSE_ENTRY_CNT_2100;
2626 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2627 ha->gid_list_info_size = 4;
3a03eb79
AV		 2628 ha->flash_conf_off = ~0;
2629 ha->flash_data_off = ~0;
2630 ha->nvram_conf_off = ~0;
2631 ha->nvram_data_off = ~0;
fd34f556 2632 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2633 } else if (IS_QLA2200(ha)) {
642ef983 2634 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2635 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2636 req_length = REQUEST_ENTRY_CNT_2200;
2637 rsp_length = RESPONSE_ENTRY_CNT_2100;
2638 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2639 ha->gid_list_info_size = 4;
3a03eb79
AV		 2640 ha->flash_conf_off = ~0;
2641 ha->flash_data_off = ~0;
2642 ha->nvram_conf_off = ~0;
2643 ha->nvram_data_off = ~0;
fd34f556 2644 ha->isp_ops = &qla2100_isp_ops;
fca29703 2645 } else if (IS_QLA23XX(ha)) {
642ef983 2646 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2647 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2648 req_length = REQUEST_ENTRY_CNT_2200;
2649 rsp_length = RESPONSE_ENTRY_CNT_2300;
2650 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2651 ha->gid_list_info_size = 6;
854165f4
AV		 2652 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2653 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2654 ha->flash_conf_off = ~0;
2655 ha->flash_data_off = ~0;
2656 ha->nvram_conf_off = ~0;
2657 ha->nvram_data_off = ~0;
fd34f556 2658 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2659 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2660 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2661 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2662 req_length = REQUEST_ENTRY_CNT_24XX;
2663 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2664 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2665 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2666 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2667 ha->gid_list_info_size = 8;
854165f4 2668 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2669 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2670 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2671 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2672 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2673 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2674 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2675 } else if (IS_QLA25XX(ha)) {
642ef983 2676 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2677 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2678 req_length = REQUEST_ENTRY_CNT_24XX;
2679 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2680 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2681 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2682 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2683 ha->gid_list_info_size = 8;
2684 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2685 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2686 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2687 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2688 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2689 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2690 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2691 } else if (IS_QLA81XX(ha)) {
642ef983 2692 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2693 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2694 req_length = REQUEST_ENTRY_CNT_24XX;
2695 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2696 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2697 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2698 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2699 ha->gid_list_info_size = 8;
2700 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2701 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2702 ha->isp_ops = &qla81xx_isp_ops;
2703 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2704 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2705 ha->nvram_conf_off = ~0;
2706 ha->nvram_data_off = ~0;
a9083016 2707 } else if (IS_QLA82XX(ha)) {
642ef983 2708 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2709 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2710 req_length = REQUEST_ENTRY_CNT_82XX;
2711 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2712 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2713 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2714 ha->gid_list_info_size = 8;
2715 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2716 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2717 ha->isp_ops = &qla82xx_isp_ops;
2718 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2719 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2720 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2721 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2722 } else if (IS_QLA8044(ha)) {
2723 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2724 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2725 req_length = REQUEST_ENTRY_CNT_82XX;
2726 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2727 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2728 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2729 ha->gid_list_info_size = 8;
2730 ha->optrom_size = OPTROM_SIZE_83XX;
2731 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2732 ha->isp_ops = &qla8044_isp_ops;
2733 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2734 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2735 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2736 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2737 } else if (IS_QLA83XX(ha)) {
7d613ac6 2738 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2739 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2740 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2741 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2742 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2743 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2744 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2745 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2746 ha->gid_list_info_size = 8;
2747 ha->optrom_size = OPTROM_SIZE_83XX;
2748 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2749 ha->isp_ops = &qla83xx_isp_ops;
2750 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2751 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2752 ha->nvram_conf_off = ~0;
2753 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2754 } else if (IS_QLAFX00(ha)) {
2755 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2756 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2757 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2758 req_length = REQUEST_ENTRY_CNT_FX00;
2759 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2760 ha->isp_ops = &qlafx00_isp_ops;
2761 ha->port_down_retry_count = 30; /* default value */
2762 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2763 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2764 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2765 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2766 ha->mr.host_info_resend = false;
2767 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2768 } else if (IS_QLA27XX(ha)) {
2769 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2770 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2771 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2772 req_length = REQUEST_ENTRY_CNT_83XX;
2773 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2774 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2775 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2776 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2777 ha->gid_list_info_size = 8;
2778 ha->optrom_size = OPTROM_SIZE_83XX;
2779 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2780 ha->isp_ops = &qla27xx_isp_ops;
2781 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2782 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2783 ha->nvram_conf_off = ~0;
2784 ha->nvram_data_off = ~0;
1da177e4 2785 }
6246b8a1 2786
7c3df132
SK		 2787 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2788 "mbx_count=%d, req_length=%d, "
2789 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2790 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2791 "max_fibre_devices=%d.\n",
7c3df132
SK		 2792 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2793 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2794 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2795 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2796 "isp_ops=%p, flash_conf_off=%d, "
2797 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2798 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2799 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2800
2801 /* Configure PCI I/O space */
2802 ret = ha->isp_ops->iospace_config(ha);
2803 if (ret)
0a63ad12 2804 goto iospace_config_failed;
706f457d
GM		 2805
2806 ql_log_pci(ql_log_info, pdev, 0x001d,
2807 "Found an ISP%04X irq %d iobase 0x%p.\n",
2808 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2809 mutex_init(&ha->vport_lock);
d7459527 2810 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2811 init_completion(&ha->mbx_cmd_comp);
2812 complete(&ha->mbx_cmd_comp);
2813 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2814 init_completion(&ha->dcbx_comp);
f356bef1 2815 init_completion(&ha->lb_portup_comp);
1da177e4 2816
2c3dfe3f 2817 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2818
53303c42 2819 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2820 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2821 "64 Bit addressing is %s.\n",
2822 ha->flags.enable_64bit_addressing ? "enable" :
2823 "disable");
73208dfd 2824 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2825 if (ret) {
7c3df132
SK		 2826 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2827 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2828
e315cd28
AC		 2829 goto probe_hw_failed;
2830 }
2831
73208dfd 2832 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2833 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2834 req->max_q_depth = ql2xmaxqdepth;
2835
e315cd28
AC		 2836
2837 base_vha = qla2x00_create_host(sht, ha);
2838 if (!base_vha) {
a1541d5a 2839 ret = -ENOMEM;
6e9f21f3 2840 qla2x00_mem_free(ha);
2afa19a9
AC		 2841 qla2x00_free_req_que(ha, req);
2842 qla2x00_free_rsp_que(ha, rsp);
e315cd28 2843 goto probe_hw_failed;
1da177e4
LT		 2844 }
2845
e315cd28 2846 pci_set_drvdata(pdev, base_vha);
6b383979 2847 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 2848
e315cd28 2849 host = base_vha->host;
2afa19a9 2850 base_vha->req = req;
73208dfd 2851 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 2852 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 2853 else
e315cd28
AC		 2854 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
2855 base_vha->vp_idx;
58548cb5 2856
8ae6d9c7
GM		 2857 /* Setup fcport template structure. */
2858 ha->mr.fcport.vha = base_vha;
2859 ha->mr.fcport.port_type = FCT_UNKNOWN;
2860 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
2861 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
2862 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
2863 ha->mr.fcport.scan_state = 1;
2864
58548cb5
GM		 2865 /* Set the SG table size based on ISP type */
2866 if (!IS_FWI2_CAPABLE(ha)) {
2867 if (IS_QLA2100(ha))
2868 host->sg_tablesize = 32;
2869 } else {
2870 if (!IS_QLA82XX(ha))
2871 host->sg_tablesize = QLA_SG_ALL;
2872 }
642ef983 2873 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 2874 host->cmd_per_lun = 3;
2875 host->unique_id = host->host_no;
e02587d7 2876 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 2877 host->max_cmd_len = 32;
2878 else
2879 host->max_cmd_len = MAX_CMDSZ;
e315cd28 2880 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 2881 /* Older HBAs support only 16-bit LUNs */
2882 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
2883 ql2xmaxlun > 0xffff)
2884 host->max_lun = 0xffff;
2885 else
2886 host->max_lun = ql2xmaxlun;
e315cd28 2887 host->transportt = qla2xxx_transport_template;
9a069e19 2888 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 2889
7c3df132
SK		 2890 ql_dbg(ql_dbg_init, base_vha, 0x0033,
2891 "max_id=%d this_id=%d "
2892 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 2893 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 2894 host->this_id, host->cmd_per_lun, host->unique_id,
2895 host->max_cmd_len, host->max_channel, host->max_lun,
2896 host->transportt, sht->vendor_id);
2897
d7459527
MH		 2898 /* Set up the irqs */
2899 ret = qla2x00_request_irqs(ha, rsp);
2900 if (ret)
2901 goto probe_init_failed;
2902
9a347ff4
CD		 2903 /* Alloc arrays of request and response ring ptrs */
2904 if (!qla2x00_alloc_queues(ha, req, rsp)) {
2905 ql_log(ql_log_fatal, base_vha, 0x003d,
2906 "Failed to allocate memory for queue pointers..."
2907 "aborting.\n");
2908 goto probe_init_failed;
2909 }
2910
5601236b
MH		 2911 if (ha->mqenable && shost_use_blk_mq(host)) {
2912 /* number of hardware queues supported by blk/scsi-mq*/
2913 host->nr_hw_queues = ha->max_qpairs;
2914
2915 ql_dbg(ql_dbg_init, base_vha, 0x0192,
2916 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
2917 } else
2918 ql_dbg(ql_dbg_init, base_vha, 0x0193,
2919 "blk/scsi-mq disabled.\n");
2920
2d70c103 2921 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 2922
90a86fc0
JC		 2923 pci_save_state(pdev);
2924
9a347ff4 2925 /* Assign back pointers */
2afa19a9
AC		 2926 rsp->req = req;
2927 req->rsp = rsp;
9a347ff4 2928
8ae6d9c7
GM		 2929 if (IS_QLAFX00(ha)) {
2930 ha->rsp_q_map[0] = rsp;
2931 ha->req_q_map[0] = req;
2932 set_bit(0, ha->req_qid_map);
2933 set_bit(0, ha->rsp_qid_map);
2934 }
2935
08029990
AV		 2936 /* FWI2-capable only. */
2937 req->req_q_in = &ha->iobase->isp24.req_q_in;
2938 req->req_q_out = &ha->iobase->isp24.req_q_out;
2939 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
2940 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 2941 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 2942 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
2943 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
2944 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
2945 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 2946 }
2947
8ae6d9c7
GM		 2948 if (IS_QLAFX00(ha)) {
2949 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
2950 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
2951 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
2952 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
2953 }
2954
7ec0effd 2955 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 2956 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
2957 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
2958 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
2959 }
2960
7c3df132
SK		 2961 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
2962 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2963 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2964 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
2965 "req->req_q_in=%p req->req_q_out=%p "
2966 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2967 req->req_q_in, req->req_q_out,
2968 rsp->rsp_q_in, rsp->rsp_q_out);
2969 ql_dbg(ql_dbg_init, base_vha, 0x003e,
2970 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
2971 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
2972 ql_dbg(ql_dbg_init, base_vha, 0x003f,
2973 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
2974 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 2975
8ae6d9c7 2976 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 2977 ql_log(ql_log_fatal, base_vha, 0x00d6,
2978 "Failed to initialize adapter - Adapter flags %x.\n",
2979 base_vha->device_flags);
1da177e4 2980
a9083016
GM		 2981 if (IS_QLA82XX(ha)) {
2982 qla82xx_idc_lock(ha);
2983 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 2984 QLA8XXX_DEV_FAILED);
a9083016 2985 qla82xx_idc_unlock(ha);
7c3df132
SK		 2986 ql_log(ql_log_fatal, base_vha, 0x00d7,
2987 "HW State: FAILED.\n");
7ec0effd
AD		 2988 } else if (IS_QLA8044(ha)) {
2989 qla8044_idc_lock(ha);
2990 qla8044_wr_direct(base_vha,
2991 QLA8044_CRB_DEV_STATE_INDEX,
2992 QLA8XXX_DEV_FAILED);
2993 qla8044_idc_unlock(ha);
2994 ql_log(ql_log_fatal, base_vha, 0x0150,
2995 "HW State: FAILED.\n");
a9083016
GM		 2996 }
2997
a1541d5a 2998 ret = -ENODEV;
1da177e4
LT		 2999 goto probe_failed;
3000 }
3001
3b1bef64
CD		 3002 if (IS_QLAFX00(ha))
3003 host->can_queue = QLAFX00_MAX_CANQUEUE;
3004 else
3005 host->can_queue = req->num_outstanding_cmds - 10;
3006
3007 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3008 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3009 host->can_queue, base_vha->req,
3010 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3011
093df737 3012 if (ha->mqenable && qla_ini_mode_enabled(base_vha)) {
d7459527 3013 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 1);
5601236b
MH		 3014 /* Create start of day qpairs for Block MQ */
3015 if (shost_use_blk_mq(host)) {
3016 for (i = 0; i < ha->max_qpairs; i++)
3017 qla2xxx_create_qpair(base_vha, 5, 0);
3018 }
3019 }
68ca949c 3020
cbc8eb67
AV		 3021 if (ha->flags.running_gold_fw)
3022 goto skip_dpc;
3023
1da177e4
LT		 3024 /*
3025 * Startup the kernel thread for this host adapter
3026 */
39a11240 3027 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3028 "%s_dpc", base_vha->host_str);
39a11240 3029 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3030 ql_log(ql_log_fatal, base_vha, 0x00ed,
3031 "Failed to start DPC thread.\n");
39a11240 3032 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3033 goto probe_failed;
3034 }
7c3df132
SK		 3035 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3036 "DPC thread started successfully.\n");
1da177e4 3037
2d70c103
NB		 3038 /*
3039 * If we're not coming up in initiator mode, we might sit for
3040 * a while without waking up the dpc thread, which leads to a
3041 * stuck process warning. So just kick the dpc once here and
3042 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3043 */
3044 qla2xxx_wake_dpc(base_vha);
3045
f3ddac19
CD		 3046 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3047
81178772
SK		 3048 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3049 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3050 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3051 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3052
3053 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3054 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3055 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3056 INIT_WORK(&ha->idc_state_handler,
3057 qla83xx_idc_state_handler_work);
3058 INIT_WORK(&ha->nic_core_unrecoverable,
3059 qla83xx_nic_core_unrecoverable_work);
3060 }
3061
cbc8eb67 3062skip_dpc:
e315cd28
AC		 3063 list_add_tail(&base_vha->list, &ha->vp_list);
3064 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3065
3066 /* Initialized the timer */
e315cd28 3067 qla2x00_start_timer(base_vha, qla2x00_timer, WATCH_INTERVAL);
7c3df132
SK		 3068 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3069 "Started qla2x00_timer with "
3070 "interval=%d.\n", WATCH_INTERVAL);
3071 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3072 "Detected hba at address=%p.\n",
3073 ha);
d19044c3 3074
e02587d7 3075 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3076 if (ha->fw_attributes & BIT_4) {
9e522cd8 3077 int prot = 0, guard;
bad75002 3078 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3079 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3080 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3081 if (ql2xenabledif == 1)
3082 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3083 scsi_host_set_prot(host,
8cb2049c 3084 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3085 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3086 | SHOST_DIF_TYPE3_PROTECTION
3087 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3088 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3089 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3090
3091 guard = SHOST_DIX_GUARD_CRC;
3092
3093 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3094 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3095 guard |= SHOST_DIX_GUARD_IP;
3096
3097 scsi_host_set_guard(host, guard);
bad75002
AE		 3098 } else
3099 base_vha->flags.difdix_supported = 0;
3100 }
3101
a9083016
GM		 3102 ha->isp_ops->enable_intrs(ha);
3103
1fe19ee4
AB		 3104 if (IS_QLAFX00(ha)) {
3105 ret = qlafx00_fx_disc(base_vha,
3106 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3107 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3108 QLA_SG_ALL : 128;
3109 }
3110
a1541d5a
AV		 3111 ret = scsi_add_host(host, &pdev->dev);
3112 if (ret)
3113 goto probe_failed;
3114
1486400f
MR		 3115 base_vha->flags.init_done = 1;
3116 base_vha->flags.online = 1;
edaa5c74 3117 ha->prev_minidump_failed = 0;
1486400f 3118
7c3df132
SK		 3119 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3120 "Init done and hba is online.\n");
3121
2d70c103
NB		 3122 if (qla_ini_mode_enabled(base_vha))
3123 scsi_scan_host(host);
3124 else
3125 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3126 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3127
e315cd28 3128 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3129
8ae6d9c7 3130 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3131 ret = qlafx00_fx_disc(base_vha,
3132 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3133
3134 /* Register system information */
3135 ret = qlafx00_fx_disc(base_vha,
3136 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3137 }
3138
e315cd28 3139 qla2x00_init_host_attr(base_vha);
a1541d5a 3140
e315cd28 3141 qla2x00_dfs_setup(base_vha);
df613b96 3142
03eb912a
AB		 3143 ql_log(ql_log_info, base_vha, 0x00fb,
3144 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3145 ql_log(ql_log_info, base_vha, 0x00fc,
3146 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3147 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3148 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3149 base_vha->host_no,
df57caba 3150 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3151
2d70c103
NB		 3152 qlt_add_target(ha, base_vha);
3153
6b383979 3154 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3155
3156 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3157 return -ENODEV;
3158
1da177e4
LT		 3159 return 0;
3160
6e9f21f3 3161probe_init_failed:
2afa19a9 3162 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3163 ha->req_q_map[0] = NULL;
3164 clear_bit(0, ha->req_qid_map);
2afa19a9 3165 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3166 ha->rsp_q_map[0] = NULL;
3167 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3168 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3169
1da177e4 3170probe_failed:
b9978769
AV		 3171 if (base_vha->timer_active)
3172 qla2x00_stop_timer(base_vha);
3173 base_vha->flags.online = 0;
3174 if (ha->dpc_thread) {
3175 struct task_struct *t = ha->dpc_thread;
3176
3177 ha->dpc_thread = NULL;
3178 kthread_stop(t);
3179 }
3180
e315cd28 3181 qla2x00_free_device(base_vha);
1da177e4 3182
e315cd28 3183 scsi_host_put(base_vha->host);
1da177e4 3184
e315cd28 3185probe_hw_failed:
1a2fbf18
JL		 3186 qla2x00_clear_drv_active(ha);
3187
0a63ad12 3188iospace_config_failed:
7ec0effd 3189 if (IS_P3P_TYPE(ha)) {
0a63ad12 3190 if (!ha->nx_pcibase)
f73cb695 3191 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3192 if (!ql2xdbwr)
f73cb695 3193 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3194 } else {
3195 if (ha->iobase)
3196 iounmap(ha->iobase);
8ae6d9c7
GM		 3197 if (ha->cregbase)
3198 iounmap(ha->cregbase);
a9083016 3199 }
e315cd28
AC		 3200 pci_release_selected_regions(ha->pdev, ha->bars);
3201 kfree(ha);
3202 ha = NULL;
1da177e4 3203
a1541d5a 3204probe_out:
e315cd28 3205 pci_disable_device(pdev);
a1541d5a 3206 return ret;
1da177e4 3207}
1da177e4 3208
e30d1756
MI		 3209static void
3210qla2x00_shutdown(struct pci_dev *pdev)
3211{
3212 scsi_qla_host_t *vha;
3213 struct qla_hw_data *ha;
3214
552f3f9a
MI		 3215 if (!atomic_read(&pdev->enable_cnt))
3216 return;
3217
e30d1756
MI		 3218 vha = pci_get_drvdata(pdev);
3219 ha = vha->hw;
3220
42479343
AB		 3221 /* Notify ISPFX00 firmware */
3222 if (IS_QLAFX00(ha))
3223 qlafx00_driver_shutdown(vha, 20);
3224
e30d1756
MI		 3225 /* Turn-off FCE trace */
3226 if (ha->flags.fce_enabled) {
3227 qla2x00_disable_fce_trace(vha, NULL, NULL);
3228 ha->flags.fce_enabled = 0;
3229 }
3230
3231 /* Turn-off EFT trace */
3232 if (ha->eft)
3233 qla2x00_disable_eft_trace(vha);
3234
3235 /* Stop currently executing firmware. */
3236 qla2x00_try_to_stop_firmware(vha);
3237
3238 /* Turn adapter off line */
3239 vha->flags.online = 0;
3240
3241 /* turn-off interrupts on the card */
3242 if (ha->interrupts_on) {
3243 vha->flags.init_done = 0;
3244 ha->isp_ops->disable_intrs(ha);
3245 }
3246
3247 qla2x00_free_irqs(vha);
3248
3249 qla2x00_free_fw_dump(ha);
61d41f61
CD		 3250
3251 pci_disable_pcie_error_reporting(pdev);
3252 pci_disable_device(pdev);
e30d1756
MI		 3253}
3254
fe1b806f 3255/* Deletes all the virtual ports for a given ha */
4c993f76 3256static void
fe1b806f 3257qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3258{
fe1b806f 3259 scsi_qla_host_t *vha;
feafb7b1 3260 unsigned long flags;
e315cd28 3261
43ebf16d
AE		 3262 mutex_lock(&ha->vport_lock);
3263 while (ha->cur_vport_count) {
43ebf16d 3264 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3265
43ebf16d
AE		 3266 BUG_ON(base_vha->list.next == &ha->vp_list);
3267 /* This assumes first entry in ha->vp_list is always base vha */
3268 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3269 scsi_host_get(vha->host);
feafb7b1 3270
43ebf16d
AE		 3271 spin_unlock_irqrestore(&ha->vport_slock, flags);
3272 mutex_unlock(&ha->vport_lock);
3273
3274 fc_vport_terminate(vha->fc_vport);
3275 scsi_host_put(vha->host);
feafb7b1 3276
43ebf16d 3277 mutex_lock(&ha->vport_lock);
e315cd28 3278 }
43ebf16d 3279 mutex_unlock(&ha->vport_lock);
fe1b806f 3280}
1da177e4 3281
fe1b806f
CD		 3282/* Stops all deferred work threads */
3283static void
3284qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3285{
7d613ac6
SV		 3286 /* Cancel all work and destroy DPC workqueues */
3287 if (ha->dpc_lp_wq) {
3288 cancel_work_sync(&ha->idc_aen);
3289 destroy_workqueue(ha->dpc_lp_wq);
3290 ha->dpc_lp_wq = NULL;
3291 }
3292
3293 if (ha->dpc_hp_wq) {
3294 cancel_work_sync(&ha->nic_core_reset);
3295 cancel_work_sync(&ha->idc_state_handler);
3296 cancel_work_sync(&ha->nic_core_unrecoverable);
3297 destroy_workqueue(ha->dpc_hp_wq);
3298 ha->dpc_hp_wq = NULL;
3299 }
3300
b9978769
AV		 3301 /* Kill the kernel thread for this host */
3302 if (ha->dpc_thread) {
3303 struct task_struct *t = ha->dpc_thread;
3304
3305 /*
3306 * qla2xxx_wake_dpc checks for ->dpc_thread
3307 * so we need to zero it out.
3308 */
3309 ha->dpc_thread = NULL;
3310 kthread_stop(t);
3311 }
fe1b806f 3312}
1da177e4 3313
fe1b806f
CD		 3314static void
3315qla2x00_unmap_iobases(struct qla_hw_data *ha)
3316{
a9083016 3317 if (IS_QLA82XX(ha)) {
b963752f 3318
f73cb695 3319 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3320 if (!ql2xdbwr)
f73cb695 3321 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3322 } else {
3323 if (ha->iobase)
3324 iounmap(ha->iobase);
1da177e4 3325
8ae6d9c7
GM		 3326 if (ha->cregbase)
3327 iounmap(ha->cregbase);
3328
a9083016
GM		 3329 if (ha->mqiobase)
3330 iounmap(ha->mqiobase);
6246b8a1 3331
f73cb695 3332 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3333 iounmap(ha->msixbase);
a9083016 3334 }
fe1b806f
CD		 3335}
3336
3337static void
db7157d4 3338qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3339{
fe1b806f
CD		 3340 if (IS_QLA8044(ha)) {
3341 qla8044_idc_lock(ha);
c41afc9a 3342 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3343 qla8044_idc_unlock(ha);
3344 } else if (IS_QLA82XX(ha)) {
3345 qla82xx_idc_lock(ha);
3346 qla82xx_clear_drv_active(ha);
3347 qla82xx_idc_unlock(ha);
3348 }
3349}
3350
3351static void
3352qla2x00_remove_one(struct pci_dev *pdev)
3353{
3354 scsi_qla_host_t *base_vha;
3355 struct qla_hw_data *ha;
3356
beb9e315
JL		 3357 base_vha = pci_get_drvdata(pdev);
3358 ha = base_vha->hw;
3359
3360 /* Indicate device removal to prevent future board_disable and wait
3361 * until any pending board_disable has completed. */
3362 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3363 cancel_work_sync(&ha->board_disable);
3364
fe1b806f 3365 /*
beb9e315
JL		 3366 * If the PCI device is disabled then there was a PCI-disconnect and
3367 * qla2x00_disable_board_on_pci_error has taken care of most of the
3368 * resources.
fe1b806f 3369 */
beb9e315
JL		 3370 if (!atomic_read(&pdev->enable_cnt)) {
3371 scsi_host_put(base_vha->host);
3372 kfree(ha);
3373 pci_set_drvdata(pdev, NULL);
fe1b806f 3374 return;
beb9e315 3375 }
fe1b806f 3376
638a1a01
SC		 3377 qla2x00_wait_for_hba_ready(base_vha);
3378
783e0dc4
SC		 3379 /* if UNLOAD flag is already set, then continue unload,
3380 * where it was set first.
3381 */
3382 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3383 return;
3384
fe1b806f
CD		 3385 set_bit(UNLOADING, &base_vha->dpc_flags);
3386
3387 if (IS_QLAFX00(ha))
3388 qlafx00_driver_shutdown(base_vha, 20);
3389
3390 qla2x00_delete_all_vps(ha, base_vha);
3391
3392 if (IS_QLA8031(ha)) {
3393 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3394 "Clearing fcoe driver presence.\n");
3395 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3396 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3397 "Error while clearing DRV-Presence.\n");
3398 }
3399
3400 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3401
3402 qla2x00_dfs_remove(base_vha);
3403
3404 qla84xx_put_chip(base_vha);
3405
2d5a4c34
HM		 3406 /* Laser should be disabled only for ISP2031 */
3407 if (IS_QLA2031(ha))
3408 qla83xx_disable_laser(base_vha);
3409
fe1b806f
CD		 3410 /* Disable timer */
3411 if (base_vha->timer_active)
3412 qla2x00_stop_timer(base_vha);
3413
3414 base_vha->flags.online = 0;
3415
b0d6cabd
HM		 3416 /* free DMA memory */
3417 if (ha->exlogin_buf)
3418 qla2x00_free_exlogin_buffer(ha);
3419
2f56a7f1
HM		 3420 /* free DMA memory */
3421 if (ha->exchoffld_buf)
3422 qla2x00_free_exchoffld_buffer(ha);
3423
fe1b806f
CD		 3424 qla2x00_destroy_deferred_work(ha);
3425
3426 qlt_remove_target(ha, base_vha);
3427
3428 qla2x00_free_sysfs_attr(base_vha, true);
3429
3430 fc_remove_host(base_vha->host);
3431
3432 scsi_remove_host(base_vha->host);
3433
3434 qla2x00_free_device(base_vha);
3435
db7157d4 3436 qla2x00_clear_drv_active(ha);
fe1b806f 3437
d2749ffa
AE		 3438 scsi_host_put(base_vha->host);
3439
fe1b806f 3440 qla2x00_unmap_iobases(ha);
73208dfd 3441
e315cd28
AC		 3442 pci_release_selected_regions(ha->pdev, ha->bars);
3443 kfree(ha);
3444 ha = NULL;
1da177e4 3445
90a86fc0
JC		 3446 pci_disable_pcie_error_reporting(pdev);
3447
665db93b 3448 pci_disable_device(pdev);
1da177e4 3449}
1da177e4
LT		 3450
3451static void
e315cd28 3452qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3453{
e315cd28 3454 struct qla_hw_data *ha = vha->hw;
1da177e4 3455
85880801
AV		 3456 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3457
3458 /* Disable timer */
3459 if (vha->timer_active)
3460 qla2x00_stop_timer(vha);
3461
2afa19a9 3462 qla25xx_delete_queues(vha);
fe1b806f 3463
df613b96 3464 if (ha->flags.fce_enabled)
e315cd28 3465 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3466
a7a167bf 3467 if (ha->eft)
e315cd28 3468 qla2x00_disable_eft_trace(vha);
a7a167bf 3469
f6ef3b18 3470 /* Stop currently executing firmware. */
e315cd28 3471 qla2x00_try_to_stop_firmware(vha);
1da177e4 3472
85880801
AV		 3473 vha->flags.online = 0;
3474
f6ef3b18 3475 /* turn-off interrupts on the card */
a9083016
GM		 3476 if (ha->interrupts_on) {
3477 vha->flags.init_done = 0;
fd34f556 3478 ha->isp_ops->disable_intrs(ha);
a9083016 3479 }
f6ef3b18 3480
093df737
QT		 3481 qla2x00_free_fcports(vha);
3482
e315cd28 3483 qla2x00_free_irqs(vha);
1da177e4 3484
093df737
QT		 3485 /* Flush the work queue and remove it */
3486 if (ha->wq) {
3487 flush_workqueue(ha->wq);
3488 destroy_workqueue(ha->wq);
3489 ha->wq = NULL;
3490 }
3491
8867048b 3492
e315cd28 3493 qla2x00_mem_free(ha);
73208dfd 3494
08de2844
GM		 3495 qla82xx_md_free(vha);
3496
73208dfd 3497 qla2x00_free_queues(ha);
1da177e4
LT		 3498}
3499
8867048b
CD		 3500void qla2x00_free_fcports(struct scsi_qla_host *vha)
3501{
3502 fc_port_t *fcport, *tfcport;
3503
3504 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3505 list_del(&fcport->list);
5f16b331 3506 qla2x00_clear_loop_id(fcport);
8867048b
CD		 3507 kfree(fcport);
3508 fcport = NULL;
3509 }
3510}
3511
d97994dc 3512static inline void
e315cd28 3513qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3514 int defer)
3515{
d97994dc 3516 struct fc_rport *rport;
67becc00 3517 scsi_qla_host_t *base_vha;
044d78e1 3518 unsigned long flags;
d97994dc
AV		 3519
3520 if (!fcport->rport)
3521 return;
3522
3523 rport = fcport->rport;
3524 if (defer) {
67becc00 3525 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3526 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3527 fcport->drport = rport;
044d78e1 3528 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3529 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3530 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3531 qla2xxx_wake_dpc(base_vha);
2d70c103 3532 } else {
df673274 3533 int now;
d20ed91b
AP		 3534 if (rport)
3535 fc_remote_port_delete(rport);
df673274
AP		 3536 qlt_do_generation_tick(vha, &now);
3537 qlt_fc_port_deleted(vha, fcport, now);
2d70c103 3538 }
d97994dc
AV		 3539}
3540
1da177e4
LT		 3541/*
3542 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3543 *
3544 * Input: ha = adapter block pointer. fcport = port structure pointer.
3545 *
3546 * Return: None.
3547 *
3548 * Context:
3549 */
e315cd28 3550void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3551 int do_login, int defer)
1da177e4 3552{
8ae6d9c7
GM		 3553 if (IS_QLAFX00(vha->hw)) {
3554 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3555 qla2x00_schedule_rport_del(vha, fcport, defer);
3556 return;
3557 }
3558
2c3dfe3f 3559 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3560 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3561 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3562 qla2x00_schedule_rport_del(vha, fcport, defer);
3563 }
fa2a1ce5 3564 /*
1da177e4
LT		 3565 * We may need to retry the login, so don't change the state of the
3566 * port but do the retries.
3567 */
3568 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3569 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3570
3571 if (!do_login)
3572 return;
3573
a1d0285e
AE		 3574 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3575
1da177e4 3576 if (fcport->login_retry == 0) {
e315cd28 3577 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3578
7c3df132 3579 ql_dbg(ql_dbg_disc, vha, 0x2067,
7b833558
OK		 3580 "Port login retry %8phN, id = 0x%04x retry cnt=%d.\n",
3581 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3582 }
3583}
3584
3585/*
3586 * qla2x00_mark_all_devices_lost
3587 * Updates fcport state when device goes offline.
3588 *
3589 * Input:
3590 * ha = adapter block pointer.
3591 * fcport = port structure pointer.
3592 *
3593 * Return:
3594 * None.
3595 *
3596 * Context:
3597 */
3598void
e315cd28 3599qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3600{
3601 fc_port_t *fcport;
3602
e315cd28 3603 list_for_each_entry(fcport, &vha->vp_fcports, list) {
c6d39e23 3604 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3605 continue;
0d6e61bc 3606
1da177e4
LT		 3607 /*
3608 * No point in marking the device as lost, if the device is
3609 * already DEAD.
3610 */
3611 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3612 continue;
e315cd28 3613 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3614 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3615 if (defer)
3616 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3617 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3618 qla2x00_schedule_rport_del(vha, fcport, defer);
3619 }
1da177e4
LT		 3620 }
3621}
3622
3623/*
3624* qla2x00_mem_alloc
3625* Allocates adapter memory.
3626*
3627* Returns:
3628* 0 = success.
e8711085 3629* !0 = failure.
1da177e4 3630*/
e8711085 3631static int
73208dfd
AC		 3632qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3633 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3634{
3635 char name[16];
1da177e4 3636
e8711085 3637 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3638 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3639 if (!ha->init_cb)
e315cd28 3640 goto fail;
e8711085 3641
2d70c103
NB		 3642 if (qlt_mem_alloc(ha) < 0)
3643 goto fail_free_init_cb;
3644
642ef983
CD		 3645 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3646 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3647 if (!ha->gid_list)
2d70c103 3648 goto fail_free_tgt_mem;
1da177e4 3649
e8711085
AV		 3650 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3651 if (!ha->srb_mempool)
e315cd28 3652 goto fail_free_gid_list;
e8711085 3653
7ec0effd 3654 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3655 /* Allocate cache for CT6 Ctx. */
3656 if (!ctx_cachep) {
3657 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3658 sizeof(struct ct6_dsd), 0,
3659 SLAB_HWCACHE_ALIGN, NULL);
3660 if (!ctx_cachep)
fc1ffd6c 3661 goto fail_free_srb_mempool;
a9083016
GM		 3662 }
3663 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3664 ctx_cachep);
3665 if (!ha->ctx_mempool)
3666 goto fail_free_srb_mempool;
7c3df132
SK		 3667 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3668 "ctx_cachep=%p ctx_mempool=%p.\n",
3669 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3670 }
3671
e8711085
AV		 3672 /* Get memory for cached NVRAM */
3673 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3674 if (!ha->nvram)
a9083016 3675 goto fail_free_ctx_mempool;
e8711085 3676
e315cd28
AC		 3677 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3678 ha->pdev->device);
3679 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3680 DMA_POOL_SIZE, 8, 0);
3681 if (!ha->s_dma_pool)
3682 goto fail_free_nvram;
3683
7c3df132
SK		 3684 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3685 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3686 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3687
7ec0effd 3688 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3689 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3690 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3691 if (!ha->dl_dma_pool) {
7c3df132
SK		 3692 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3693 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3694 goto fail_s_dma_pool;
3695 }
3696
3697 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3698 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3699 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3700 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3701 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3702 goto fail_dl_dma_pool;
3703 }
7c3df132
SK		 3704 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3705 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3706 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3707 }
3708
e8711085
AV		 3709 /* Allocate memory for SNS commands */
3710 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3711 /* Get consistent memory allocated for SNS commands */
e8711085 3712 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3713 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3714 if (!ha->sns_cmd)
e315cd28 3715 goto fail_dma_pool;
7c3df132 3716 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3717 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3718 } else {
e315cd28 3719 /* Get consistent memory allocated for MS IOCB */
e8711085 3720 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3721 &ha->ms_iocb_dma);
e8711085 3722 if (!ha->ms_iocb)
e315cd28
AC		 3723 goto fail_dma_pool;
3724 /* Get consistent memory allocated for CT SNS commands */
e8711085 3725 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3726 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3727 if (!ha->ct_sns)
3728 goto fail_free_ms_iocb;
7c3df132
SK		 3729 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3730 "ms_iocb=%p ct_sns=%p.\n",
3731 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3732 }
3733
e315cd28 3734 /* Allocate memory for request ring */
73208dfd
AC		 3735 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3736 if (!*req) {
7c3df132
SK		 3737 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3738 "Failed to allocate memory for req.\n");
e315cd28
AC		 3739 goto fail_req;
3740 }
73208dfd
AC		 3741 (*req)->length = req_len;
3742 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3743 ((*req)->length + 1) * sizeof(request_t),
3744 &(*req)->dma, GFP_KERNEL);
3745 if (!(*req)->ring) {
7c3df132
SK		 3746 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3747 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3748 goto fail_req_ring;
3749 }
3750 /* Allocate memory for response ring */
73208dfd
AC		 3751 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3752 if (!*rsp) {
7c3df132
SK		 3753 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3754 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3755 goto fail_rsp;
3756 }
73208dfd
AC		 3757 (*rsp)->hw = ha;
3758 (*rsp)->length = rsp_len;
3759 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3760 ((*rsp)->length + 1) * sizeof(response_t),
3761 &(*rsp)->dma, GFP_KERNEL);
3762 if (!(*rsp)->ring) {
7c3df132
SK		 3763 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3764 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3765 goto fail_rsp_ring;
3766 }
73208dfd
AC		 3767 (*req)->rsp = *rsp;
3768 (*rsp)->req = *req;
7c3df132
SK		 3769 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3770 "req=%p req->length=%d req->ring=%p rsp=%p "
3771 "rsp->length=%d rsp->ring=%p.\n",
3772 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3773 (*rsp)->ring);
73208dfd
AC		 3774 /* Allocate memory for NVRAM data for vports */
3775 if (ha->nvram_npiv_size) {
3776 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3777 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3778 if (!ha->npiv_info) {
7c3df132
SK		 3779 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3780 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3781 goto fail_npiv_info;
3782 }
3783 } else
3784 ha->npiv_info = NULL;
e8711085 3785
b64b0e8f 3786 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 3787 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 3788 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3789 &ha->ex_init_cb_dma);
3790 if (!ha->ex_init_cb)
3791 goto fail_ex_init_cb;
7c3df132
SK		 3792 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
3793 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 3794 }
3795
a9083016
GM		 3796 INIT_LIST_HEAD(&ha->gbl_dsd_list);
3797
5ff1d584
AV		 3798 /* Get consistent memory allocated for Async Port-Database. */
3799 if (!IS_FWI2_CAPABLE(ha)) {
3800 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
3801 &ha->async_pd_dma);
3802 if (!ha->async_pd)
3803 goto fail_async_pd;
7c3df132
SK		 3804 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
3805 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 3806 }
3807
e315cd28 3808 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 3809
3810 /* Allocate memory for our loop_id bitmap */
3811 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
3812 GFP_KERNEL);
3813 if (!ha->loop_id_map)
fc1ffd6c 3814 goto fail_loop_id_map;
5f16b331
CD		 3815 else {
3816 qla2x00_set_reserved_loop_ids(ha);
3817 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 3818 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 3819 }
3820
b2a72ec3 3821 return 0;
e315cd28 3822
fc1ffd6c
QT		 3823fail_loop_id_map:
3824 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 3825fail_async_pd:
3826 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 3827fail_ex_init_cb:
3828 kfree(ha->npiv_info);
73208dfd
AC		 3829fail_npiv_info:
3830 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
3831 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
3832 (*rsp)->ring = NULL;
3833 (*rsp)->dma = 0;
e315cd28 3834fail_rsp_ring:
73208dfd 3835 kfree(*rsp);
e315cd28 3836fail_rsp:
73208dfd
AC		 3837 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
3838 sizeof(request_t), (*req)->ring, (*req)->dma);
3839 (*req)->ring = NULL;
3840 (*req)->dma = 0;
e315cd28 3841fail_req_ring:
73208dfd 3842 kfree(*req);
e315cd28
AC		 3843fail_req:
3844 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
3845 ha->ct_sns, ha->ct_sns_dma);
3846 ha->ct_sns = NULL;
3847 ha->ct_sns_dma = 0;
e8711085
AV		 3848fail_free_ms_iocb:
3849 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
3850 ha->ms_iocb = NULL;
3851 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 3852
3853 if (ha->sns_cmd)
3854 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
3855 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 3856fail_dma_pool:
bad75002 3857 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3858 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
3859 ha->fcp_cmnd_dma_pool = NULL;
3860 }
3861fail_dl_dma_pool:
bad75002 3862 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 3863 dma_pool_destroy(ha->dl_dma_pool);
3864 ha->dl_dma_pool = NULL;
3865 }
3866fail_s_dma_pool:
e315cd28
AC		 3867 dma_pool_destroy(ha->s_dma_pool);
3868 ha->s_dma_pool = NULL;
e8711085
AV		 3869fail_free_nvram:
3870 kfree(ha->nvram);
3871 ha->nvram = NULL;
a9083016 3872fail_free_ctx_mempool:
fc1ffd6c
QT		 3873 if (ha->ctx_mempool)
3874 mempool_destroy(ha->ctx_mempool);
a9083016 3875 ha->ctx_mempool = NULL;
e8711085 3876fail_free_srb_mempool:
fc1ffd6c
QT		 3877 if (ha->srb_mempool)
3878 mempool_destroy(ha->srb_mempool);
e8711085 3879 ha->srb_mempool = NULL;
e8711085 3880fail_free_gid_list:
642ef983
CD		 3881 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
3882 ha->gid_list,
e315cd28 3883 ha->gid_list_dma);
e8711085
AV		 3884 ha->gid_list = NULL;
3885 ha->gid_list_dma = 0;
2d70c103
NB		 3886fail_free_tgt_mem:
3887 qlt_mem_free(ha);
e315cd28
AC		 3888fail_free_init_cb:
3889 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
3890 ha->init_cb_dma);
3891 ha->init_cb = NULL;
3892 ha->init_cb_dma = 0;
e8711085 3893fail:
7c3df132
SK		 3894 ql_log(ql_log_fatal, NULL, 0x0030,
3895 "Memory allocation failure.\n");
e8711085 3896 return -ENOMEM;
1da177e4
LT		 3897}
3898
b0d6cabd
HM		 3899int
3900qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
3901{
3902 int rval;
3903 uint16_t size, max_cnt, temp;
3904 struct qla_hw_data *ha = vha->hw;
3905
3906 /* Return if we don't need to alloacate any extended logins */
3907 if (!ql2xexlogins)
3908 return QLA_SUCCESS;
3909
3910 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
3911 max_cnt = 0;
3912 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
3913 if (rval != QLA_SUCCESS) {
3914 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
3915 "Failed to get exlogin status.\n");
3916 return rval;
3917 }
3918
3919 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
3920 ha->exlogin_size = (size * temp);
3921 ql_log(ql_log_info, vha, 0xd024,
3922 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
3923 max_cnt, size, temp);
3924
3925 ql_log(ql_log_info, vha, 0xd025, "EXLOGIN: requested size=0x%x\n",
3926 ha->exlogin_size);
3927
3928 /* Get consistent memory for extended logins */
3929 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
3930 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
3931 if (!ha->exlogin_buf) {
3932 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
3933 "Failed to allocate memory for exlogin_buf_dma.\n");
3934 return -ENOMEM;
3935 }
3936
3937 /* Now configure the dma buffer */
3938 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
3939 if (rval) {
3940 ql_log(ql_log_fatal, vha, 0x00cf,
3941 "Setup extended login buffer ****FAILED****.\n");
3942 qla2x00_free_exlogin_buffer(ha);
3943 }
3944
3945 return rval;
3946}
3947
3948/*
3949* qla2x00_free_exlogin_buffer
3950*
3951* Input:
3952* ha = adapter block pointer
3953*/
3954void
3955qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
3956{
3957 if (ha->exlogin_buf) {
3958 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
3959 ha->exlogin_buf, ha->exlogin_buf_dma);
3960 ha->exlogin_buf = NULL;
3961 ha->exlogin_size = 0;
3962 }
3963}
3964
2f56a7f1
HM		 3965int
3966qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
3967{
3968 int rval;
3969 uint16_t size, max_cnt, temp;
3970 struct qla_hw_data *ha = vha->hw;
3971
3972 /* Return if we don't need to alloacate any extended logins */
3973 if (!ql2xexchoffld)
3974 return QLA_SUCCESS;
3975
3976 ql_log(ql_log_info, vha, 0xd014,
3977 "Exchange offload count: %d.\n", ql2xexlogins);
3978
3979 max_cnt = 0;
3980 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
3981 if (rval != QLA_SUCCESS) {
3982 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
3983 "Failed to get exlogin status.\n");
3984 return rval;
3985 }
3986
3987 temp = (ql2xexchoffld > max_cnt) ? max_cnt : ql2xexchoffld;
3988 ha->exchoffld_size = (size * temp);
3989 ql_log(ql_log_info, vha, 0xd016,
3990 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
3991 max_cnt, size, temp);
3992
3993 ql_log(ql_log_info, vha, 0xd017,
3994 "Exchange Buffers requested size = 0x%x\n", ha->exchoffld_size);
3995
3996 /* Get consistent memory for extended logins */
3997 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
3998 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
3999 if (!ha->exchoffld_buf) {
4000 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4001 "Failed to allocate memory for exchoffld_buf_dma.\n");
4002 return -ENOMEM;
4003 }
4004
4005 /* Now configure the dma buffer */
4006 rval = qla_set_exchoffld_mem_cfg(vha, ha->exchoffld_buf_dma);
4007 if (rval) {
4008 ql_log(ql_log_fatal, vha, 0xd02e,
4009 "Setup exchange offload buffer ****FAILED****.\n");
4010 qla2x00_free_exchoffld_buffer(ha);
4011 }
4012
4013 return rval;
4014}
4015
4016/*
4017* qla2x00_free_exchoffld_buffer
4018*
4019* Input:
4020* ha = adapter block pointer
4021*/
4022void
4023qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4024{
4025 if (ha->exchoffld_buf) {
4026 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4027 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4028 ha->exchoffld_buf = NULL;
4029 ha->exchoffld_size = 0;
4030 }
4031}
4032
1da177e4 4033/*
e30d1756
MI		 4034* qla2x00_free_fw_dump
4035* Frees fw dump stuff.
1da177e4
LT		 4036*
4037* Input:
7ec0effd 4038* ha = adapter block pointer
1da177e4 4039*/
a824ebb3 4040static void
e30d1756 4041qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4042{
df613b96 4043 if (ha->fce)
f73cb695
CD		 4044 dma_free_coherent(&ha->pdev->dev,
4045 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4046
f73cb695
CD		 4047 if (ha->eft)
4048 dma_free_coherent(&ha->pdev->dev,
4049 EFT_SIZE, ha->eft, ha->eft_dma);
4050
4051 if (ha->fw_dump)
a7a167bf 4052 vfree(ha->fw_dump);
f73cb695
CD		 4053 if (ha->fw_dump_template)
4054 vfree(ha->fw_dump_template);
4055
e30d1756
MI		 4056 ha->fce = NULL;
4057 ha->fce_dma = 0;
4058 ha->eft = NULL;
4059 ha->eft_dma = 0;
e30d1756 4060 ha->fw_dumped = 0;
61f098dd 4061 ha->fw_dump_cap_flags = 0;
e30d1756 4062 ha->fw_dump_reading = 0;
f73cb695
CD		 4063 ha->fw_dump = NULL;
4064 ha->fw_dump_len = 0;
4065 ha->fw_dump_template = NULL;
4066 ha->fw_dump_template_len = 0;
e30d1756
MI		 4067}
4068
4069/*
4070* qla2x00_mem_free
4071* Frees all adapter allocated memory.
4072*
4073* Input:
4074* ha = adapter block pointer.
4075*/
4076static void
4077qla2x00_mem_free(struct qla_hw_data *ha)
4078{
4079 qla2x00_free_fw_dump(ha);
4080
81178772
SK		 4081 if (ha->mctp_dump)
4082 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4083 ha->mctp_dump_dma);
4084
e30d1756
MI		 4085 if (ha->srb_mempool)
4086 mempool_destroy(ha->srb_mempool);
a7a167bf 4087
11bbc1d8
AV		 4088 if (ha->dcbx_tlv)
4089 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4090 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4091
ce0423f4
AV		 4092 if (ha->xgmac_data)
4093 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4094 ha->xgmac_data, ha->xgmac_data_dma);
4095
1da177e4
LT		 4096 if (ha->sns_cmd)
4097 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4098 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4099
4100 if (ha->ct_sns)
4101 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4102 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4103
88729e53
AV		 4104 if (ha->sfp_data)
4105 dma_pool_free(ha->s_dma_pool, ha->sfp_data, ha->sfp_data_dma);
4106
1da177e4
LT		 4107 if (ha->ms_iocb)
4108 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4109
b64b0e8f 4110 if (ha->ex_init_cb)
a9083016
GM		 4111 dma_pool_free(ha->s_dma_pool,
4112 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4113
5ff1d584
AV		 4114 if (ha->async_pd)
4115 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4116
1da177e4
LT		 4117 if (ha->s_dma_pool)
4118 dma_pool_destroy(ha->s_dma_pool);
4119
1da177e4 4120 if (ha->gid_list)
642ef983
CD		 4121 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4122 ha->gid_list, ha->gid_list_dma);
1da177e4 4123
a9083016
GM		 4124 if (IS_QLA82XX(ha)) {
4125 if (!list_empty(&ha->gbl_dsd_list)) {
4126 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4127
4128 /* clean up allocated prev pool */
4129 list_for_each_entry_safe(dsd_ptr,
4130 tdsd_ptr, &ha->gbl_dsd_list, list) {
4131 dma_pool_free(ha->dl_dma_pool,
4132 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4133 list_del(&dsd_ptr->list);
4134 kfree(dsd_ptr);
4135 }
4136 }
4137 }
4138
4139 if (ha->dl_dma_pool)
4140 dma_pool_destroy(ha->dl_dma_pool);
4141
4142 if (ha->fcp_cmnd_dma_pool)
4143 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4144
4145 if (ha->ctx_mempool)
4146 mempool_destroy(ha->ctx_mempool);
4147
2d70c103
NB		 4148 qlt_mem_free(ha);
4149
e315cd28
AC		 4150 if (ha->init_cb)
4151 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4152 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4153 vfree(ha->optrom_buffer);
4154 kfree(ha->nvram);
73208dfd 4155 kfree(ha->npiv_info);
7a67735b 4156 kfree(ha->swl);
5f16b331 4157 kfree(ha->loop_id_map);
1da177e4 4158
e8711085 4159 ha->srb_mempool = NULL;
a9083016 4160 ha->ctx_mempool = NULL;
1da177e4
LT		 4161 ha->sns_cmd = NULL;
4162 ha->sns_cmd_dma = 0;
4163 ha->ct_sns = NULL;
4164 ha->ct_sns_dma = 0;
4165 ha->ms_iocb = NULL;
4166 ha->ms_iocb_dma = 0;
1da177e4
LT		 4167 ha->init_cb = NULL;
4168 ha->init_cb_dma = 0;
b64b0e8f
AV		 4169 ha->ex_init_cb = NULL;
4170 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4171 ha->async_pd = NULL;
4172 ha->async_pd_dma = 0;
1da177e4
LT		 4173
4174 ha->s_dma_pool = NULL;
a9083016
GM		 4175 ha->dl_dma_pool = NULL;
4176 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4177
1da177e4
LT		 4178 ha->gid_list = NULL;
4179 ha->gid_list_dma = 0;
2d70c103
NB		 4180
4181 ha->tgt.atio_ring = NULL;
4182 ha->tgt.atio_dma = 0;
4183 ha->tgt.tgt_vp_map = NULL;
e315cd28 4184}
1da177e4 4185
e315cd28
AC		 4186struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4187 struct qla_hw_data *ha)
4188{
4189 struct Scsi_Host *host;
4190 struct scsi_qla_host *vha = NULL;
854165f4 4191
e315cd28
AC		 4192 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4193 if (host == NULL) {
7c3df132
SK		 4194 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4195 "Failed to allocate host from the scsi layer, aborting.\n");
e315cd28
AC		 4196 goto fail;
4197 }
4198
4199 /* Clear our data area */
4200 vha = shost_priv(host);
4201 memset(vha, 0, sizeof(scsi_qla_host_t));
4202
4203 vha->host = host;
4204 vha->host_no = host->host_no;
4205 vha->hw = ha;
4206
4207 INIT_LIST_HEAD(&vha->vp_fcports);
4208 INIT_LIST_HEAD(&vha->work_list);
4209 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4210 INIT_LIST_HEAD(&vha->qla_cmd_list);
4211 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4212 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4213 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4214 INIT_LIST_HEAD(&vha->qp_list);
e315cd28 4215
f999f4c1 4216 spin_lock_init(&vha->work_lock);
8b2f5ff3 4217 spin_lock_init(&vha->cmd_list_lock);
f999f4c1 4218
e315cd28 4219 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4220 ql_dbg(ql_dbg_init, vha, 0x0041,
4221 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4222 vha->host, vha->hw, vha,
4223 dev_name(&(ha->pdev->dev)));
4224
e315cd28
AC		 4225 return vha;
4226
4227fail:
4228 return vha;
1da177e4
LT		 4229}
4230
01ef66bb 4231static struct qla_work_evt *
f999f4c1 4232qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4233{
4234 struct qla_work_evt *e;
feafb7b1
AE		 4235 uint8_t bail;
4236
4237 QLA_VHA_MARK_BUSY(vha, bail);
4238 if (bail)
4239 return NULL;
0971de7f 4240
f999f4c1 4241 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4242 if (!e) {
4243 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4244 return NULL;
feafb7b1 4245 }
0971de7f
AV		 4246
4247 INIT_LIST_HEAD(&e->list);
4248 e->type = type;
4249 e->flags = QLA_EVT_FLAG_FREE;
4250 return e;
4251}
4252
01ef66bb 4253static int
f999f4c1 4254qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4255{
f999f4c1 4256 unsigned long flags;
0971de7f 4257
f999f4c1 4258 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4259 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4260 spin_unlock_irqrestore(&vha->work_lock, flags);
e315cd28 4261 qla2xxx_wake_dpc(vha);
f999f4c1 4262
0971de7f
AV		 4263 return QLA_SUCCESS;
4264}
4265
4266int
e315cd28 4267qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4268 u32 data)
4269{
4270 struct qla_work_evt *e;
4271
f999f4c1 4272 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4273 if (!e)
4274 return QLA_FUNCTION_FAILED;
4275
4276 e->u.aen.code = code;
4277 e->u.aen.data = data;
f999f4c1 4278 return qla2x00_post_work(vha, e);
0971de7f
AV		 4279}
4280
8a659571
AV		 4281int
4282qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4283{
4284 struct qla_work_evt *e;
4285
f999f4c1 4286 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4287 if (!e)
4288 return QLA_FUNCTION_FAILED;
4289
4290 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4291 return qla2x00_post_work(vha, e);
8a659571
AV		 4292}
4293
ac280b67
AV		 4294#define qla2x00_post_async_work(name, type) \
4295int qla2x00_post_async_##name##_work( \
4296 struct scsi_qla_host *vha, \
4297 fc_port_t *fcport, uint16_t *data) \
4298{ \
4299 struct qla_work_evt *e; \
4300 \
4301 e = qla2x00_alloc_work(vha, type); \
4302 if (!e) \
4303 return QLA_FUNCTION_FAILED; \
4304 \
4305 e->u.logio.fcport = fcport; \
4306 if (data) { \
4307 e->u.logio.data[0] = data[0]; \
4308 e->u.logio.data[1] = data[1]; \
4309 } \
4310 return qla2x00_post_work(vha, e); \
4311}
4312
4313qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4314qla2x00_post_async_work(login_done, QLA_EVT_ASYNC_LOGIN_DONE);
4315qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4316qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4317qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4318qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4319
3420d36c
AV		 4320int
4321qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4322{
4323 struct qla_work_evt *e;
4324
4325 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4326 if (!e)
4327 return QLA_FUNCTION_FAILED;
4328
4329 e->u.uevent.code = code;
4330 return qla2x00_post_work(vha, e);
4331}
4332
4333static void
4334qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4335{
4336 char event_string[40];
4337 char *envp[] = { event_string, NULL };
4338
4339 switch (code) {
4340 case QLA_UEVENT_CODE_FW_DUMP:
4341 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4342 vha->host_no);
4343 break;
4344 default:
4345 /* do nothing */
4346 break;
4347 }
4348 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4349}
4350
8ae6d9c7
GM		 4351int
4352qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4353 uint32_t *data, int cnt)
4354{
4355 struct qla_work_evt *e;
4356
4357 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4358 if (!e)
4359 return QLA_FUNCTION_FAILED;
4360
4361 e->u.aenfx.evtcode = evtcode;
4362 e->u.aenfx.count = cnt;
4363 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4364 return qla2x00_post_work(vha, e);
4365}
4366
ac280b67 4367void
e315cd28 4368qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4369{
f999f4c1
AV		 4370 struct qla_work_evt *e, *tmp;
4371 unsigned long flags;
4372 LIST_HEAD(work);
0971de7f 4373
f999f4c1
AV		 4374 spin_lock_irqsave(&vha->work_lock, flags);
4375 list_splice_init(&vha->work_list, &work);
4376 spin_unlock_irqrestore(&vha->work_lock, flags);
4377
4378 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4379 list_del_init(&e->list);
0971de7f
AV		 4380
4381 switch (e->type) {
4382 case QLA_EVT_AEN:
e315cd28 4383 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4384 e->u.aen.code, e->u.aen.data);
4385 break;
8a659571
AV		 4386 case QLA_EVT_IDC_ACK:
4387 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4388 break;
ac280b67
AV		 4389 case QLA_EVT_ASYNC_LOGIN:
4390 qla2x00_async_login(vha, e->u.logio.fcport,
4391 e->u.logio.data);
4392 break;
4393 case QLA_EVT_ASYNC_LOGIN_DONE:
4394 qla2x00_async_login_done(vha, e->u.logio.fcport,
4395 e->u.logio.data);
4396 break;
4397 case QLA_EVT_ASYNC_LOGOUT:
4398 qla2x00_async_logout(vha, e->u.logio.fcport);
4399 break;
4400 case QLA_EVT_ASYNC_LOGOUT_DONE:
4401 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4402 e->u.logio.data);
4403 break;
5ff1d584
AV		 4404 case QLA_EVT_ASYNC_ADISC:
4405 qla2x00_async_adisc(vha, e->u.logio.fcport,
4406 e->u.logio.data);
4407 break;
4408 case QLA_EVT_ASYNC_ADISC_DONE:
4409 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4410 e->u.logio.data);
4411 break;
3420d36c
AV		 4412 case QLA_EVT_UEVENT:
4413 qla2x00_uevent_emit(vha, e->u.uevent.code);
4414 break;
8ae6d9c7
GM		 4415 case QLA_EVT_AENFX:
4416 qlafx00_process_aen(vha, e);
4417 break;
0971de7f
AV		 4418 }
4419 if (e->flags & QLA_EVT_FLAG_FREE)
4420 kfree(e);
feafb7b1
AE		 4421
4422 /* For each work completed decrement vha ref count */
4423 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4424 }
e315cd28 4425}
f999f4c1 4426
e315cd28
AC		 4427/* Relogins all the fcports of a vport
4428 * Context: dpc thread
4429 */
4430void qla2x00_relogin(struct scsi_qla_host *vha)
4431{
4432 fc_port_t *fcport;
c6b2fca8 4433 int status;
e315cd28
AC		 4434 uint16_t next_loopid = 0;
4435 struct qla_hw_data *ha = vha->hw;
ac280b67 4436 uint16_t data[2];
e315cd28
AC		 4437
4438 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4439 /*
4440 * If the port is not ONLINE then try to login
4441 * to it if we haven't run out of retries.
4442 */
5ff1d584
AV		 4443 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4444 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4445 fcport->login_retry--;
e315cd28 4446 if (fcport->flags & FCF_FABRIC_DEVICE) {
f08b7251 4447 if (fcport->flags & FCF_FCP2_DEVICE)
e315cd28
AC		 4448 ha->isp_ops->fabric_logout(vha,
4449 fcport->loop_id,
4450 fcport->d_id.b.domain,
4451 fcport->d_id.b.area,
4452 fcport->d_id.b.al_pa);
4453
03bcfb57
JC		 4454 if (fcport->loop_id == FC_NO_LOOP_ID) {
4455 fcport->loop_id = next_loopid =
4456 ha->min_external_loopid;
4457 status = qla2x00_find_new_loop_id(
4458 vha, fcport);
4459 if (status != QLA_SUCCESS) {
4460 /* Ran out of IDs to use */
4461 break;
4462 }
4463 }
4464
ac280b67 4465 if (IS_ALOGIO_CAPABLE(ha)) {
5ff1d584 4466 fcport->flags |= FCF_ASYNC_SENT;
ac280b67
AV		 4467 data[0] = 0;
4468 data[1] = QLA_LOGIO_LOGIN_RETRIED;
4469 status = qla2x00_post_async_login_work(
4470 vha, fcport, data);
4471 if (status == QLA_SUCCESS)
4472 continue;
4473 /* Attempt a retry. */
4474 status = 1;
aaf4d3e2 4475 } else {
ac280b67
AV		 4476 status = qla2x00_fabric_login(vha,
4477 fcport, &next_loopid);
aaf4d3e2
SK		 4478 if (status == QLA_SUCCESS) {
4479 int status2;
4480 uint8_t opts;
4481
4482 opts = 0;
4483 if (fcport->flags &
4484 FCF_FCP2_DEVICE)
4485 opts |= BIT_1;
03003960
SK		 4486 status2 =
4487 qla2x00_get_port_database(
4488 vha, fcport, opts);
aaf4d3e2
SK		 4489 if (status2 != QLA_SUCCESS)
4490 status = 1;
4491 }
4492 }
e315cd28
AC		 4493 } else
4494 status = qla2x00_local_device_login(vha,
4495 fcport);
4496
e315cd28
AC		 4497 if (status == QLA_SUCCESS) {
4498 fcport->old_loop_id = fcport->loop_id;
4499
7c3df132
SK		 4500 ql_dbg(ql_dbg_disc, vha, 0x2003,
4501 "Port login OK: logged in ID 0x%x.\n",
4502 fcport->loop_id);
e315cd28
AC		 4503
4504 qla2x00_update_fcport(vha, fcport);
4505
4506 } else if (status == 1) {
4507 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4508 /* retry the login again */
7c3df132
SK		 4509 ql_dbg(ql_dbg_disc, vha, 0x2007,
4510 "Retrying %d login again loop_id 0x%x.\n",
4511 fcport->login_retry, fcport->loop_id);
e315cd28
AC		 4512 } else {
4513 fcport->login_retry = 0;
4514 }
4515
4516 if (fcport->login_retry == 0 && status != QLA_SUCCESS)
5f16b331 4517 qla2x00_clear_loop_id(fcport);
e315cd28
AC		 4518 }
4519 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4520 break;
0971de7f 4521 }
0971de7f
AV		 4522}
4523
7d613ac6
SV		 4524/* Schedule work on any of the dpc-workqueues */
4525void
4526qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4527{
4528 struct qla_hw_data *ha = base_vha->hw;
4529
4530 switch (work_code) {
4531 case MBA_IDC_AEN: /* 0x8200 */
4532 if (ha->dpc_lp_wq)
4533 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4534 break;
4535
4536 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4537 if (!ha->flags.nic_core_reset_hdlr_active) {
4538 if (ha->dpc_hp_wq)
4539 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4540 } else
4541 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4542 "NIC Core reset is already active. Skip "
4543 "scheduling it again.\n");
4544 break;
4545 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4546 if (ha->dpc_hp_wq)
4547 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4548 break;
4549 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4550 if (ha->dpc_hp_wq)
4551 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4552 break;
4553 default:
4554 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4555 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4556 }
4557
4558 return;
4559}
4560
4561/* Work: Perform NIC Core Unrecoverable state handling */
4562void
4563qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4564{
4565 struct qla_hw_data *ha =
2ad1b67c 4566 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4567 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4568 uint32_t dev_state = 0;
4569
4570 qla83xx_idc_lock(base_vha, 0);
4571 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4572 qla83xx_reset_ownership(base_vha);
4573 if (ha->flags.nic_core_reset_owner) {
4574 ha->flags.nic_core_reset_owner = 0;
4575 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4576 QLA8XXX_DEV_FAILED);
4577 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4578 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4579 }
4580 qla83xx_idc_unlock(base_vha, 0);
4581}
4582
4583/* Work: Execute IDC state handler */
4584void
4585qla83xx_idc_state_handler_work(struct work_struct *work)
4586{
4587 struct qla_hw_data *ha =
2ad1b67c 4588 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4589 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4590 uint32_t dev_state = 0;
4591
4592 qla83xx_idc_lock(base_vha, 0);
4593 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4594 if (dev_state == QLA8XXX_DEV_FAILED ||
4595 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4596 qla83xx_idc_state_handler(base_vha);
4597 qla83xx_idc_unlock(base_vha, 0);
4598}
4599
fa492630 4600static int
7d613ac6
SV		 4601qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4602{
4603 int rval = QLA_SUCCESS;
4604 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4605 uint32_t heart_beat_counter1, heart_beat_counter2;
4606
4607 do {
4608 if (time_after(jiffies, heart_beat_wait)) {
4609 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4610 "Nic Core f/w is not alive.\n");
4611 rval = QLA_FUNCTION_FAILED;
4612 break;
4613 }
4614
4615 qla83xx_idc_lock(base_vha, 0);
4616 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4617 &heart_beat_counter1);
4618 qla83xx_idc_unlock(base_vha, 0);
4619 msleep(100);
4620 qla83xx_idc_lock(base_vha, 0);
4621 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4622 &heart_beat_counter2);
4623 qla83xx_idc_unlock(base_vha, 0);
4624 } while (heart_beat_counter1 == heart_beat_counter2);
4625
4626 return rval;
4627}
4628
4629/* Work: Perform NIC Core Reset handling */
4630void
4631qla83xx_nic_core_reset_work(struct work_struct *work)
4632{
4633 struct qla_hw_data *ha =
4634 container_of(work, struct qla_hw_data, nic_core_reset);
4635 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4636 uint32_t dev_state = 0;
4637
81178772
SK		 4638 if (IS_QLA2031(ha)) {
4639 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
4640 ql_log(ql_log_warn, base_vha, 0xb081,
4641 "Failed to dump mctp\n");
4642 return;
4643 }
4644
7d613ac6
SV		 4645 if (!ha->flags.nic_core_reset_hdlr_active) {
4646 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
4647 qla83xx_idc_lock(base_vha, 0);
4648 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4649 &dev_state);
4650 qla83xx_idc_unlock(base_vha, 0);
4651 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
4652 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
4653 "Nic Core f/w is alive.\n");
4654 return;
4655 }
4656 }
4657
4658 ha->flags.nic_core_reset_hdlr_active = 1;
4659 if (qla83xx_nic_core_reset(base_vha)) {
4660 /* NIC Core reset failed. */
4661 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
4662 "NIC Core reset failed.\n");
4663 }
4664 ha->flags.nic_core_reset_hdlr_active = 0;
4665 }
4666}
4667
4668/* Work: Handle 8200 IDC aens */
4669void
4670qla83xx_service_idc_aen(struct work_struct *work)
4671{
4672 struct qla_hw_data *ha =
4673 container_of(work, struct qla_hw_data, idc_aen);
4674 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4675 uint32_t dev_state, idc_control;
4676
4677 qla83xx_idc_lock(base_vha, 0);
4678 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4679 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
4680 qla83xx_idc_unlock(base_vha, 0);
4681 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
4682 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
4683 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
4684 "Application requested NIC Core Reset.\n");
4685 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4686 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
4687 QLA_SUCCESS) {
4688 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
4689 "Other protocol driver requested NIC Core Reset.\n");
4690 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
4691 }
4692 } else if (dev_state == QLA8XXX_DEV_FAILED ||
4693 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
4694 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4695 }
4696}
4697
4698static void
4699qla83xx_wait_logic(void)
4700{
4701 int i;
4702
4703 /* Yield CPU */
4704 if (!in_interrupt()) {
4705 /*
4706 * Wait about 200ms before retrying again.
4707 * This controls the number of retries for single
4708 * lock operation.
4709 */
4710 msleep(100);
4711 schedule();
4712 } else {
4713 for (i = 0; i < 20; i++)
4714 cpu_relax(); /* This a nop instr on i386 */
4715 }
4716}
4717
fa492630 4718static int
7d613ac6
SV		 4719qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
4720{
4721 int rval;
4722 uint32_t data;
4723 uint32_t idc_lck_rcvry_stage_mask = 0x3;
4724 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
4725 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 4726 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
4727 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 4728
4729 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
4730 if (rval)
4731 return rval;
4732
4733 if ((data & idc_lck_rcvry_stage_mask) > 0) {
4734 return QLA_SUCCESS;
4735 } else {
4736 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
4737 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4738 data);
4739 if (rval)
4740 return rval;
4741
4742 msleep(200);
4743
4744 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
4745 &data);
4746 if (rval)
4747 return rval;
4748
4749 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
4750 data &= (IDC_LOCK_RECOVERY_STAGE2 |
4751 ~(idc_lck_rcvry_stage_mask));
4752 rval = qla83xx_wr_reg(base_vha,
4753 QLA83XX_IDC_LOCK_RECOVERY, data);
4754 if (rval)
4755 return rval;
4756
4757 /* Forcefully perform IDC UnLock */
4758 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
4759 &data);
4760 if (rval)
4761 return rval;
4762 /* Clear lock-id by setting 0xff */
4763 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4764 0xff);
4765 if (rval)
4766 return rval;
4767 /* Clear lock-recovery by setting 0x0 */
4768 rval = qla83xx_wr_reg(base_vha,
4769 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
4770 if (rval)
4771 return rval;
4772 } else
4773 return QLA_SUCCESS;
4774 }
4775
4776 return rval;
4777}
4778
fa492630 4779static int
7d613ac6
SV		 4780qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
4781{
4782 int rval = QLA_SUCCESS;
4783 uint32_t o_drv_lockid, n_drv_lockid;
4784 unsigned long lock_recovery_timeout;
4785
4786 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
4787retry_lockid:
4788 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
4789 if (rval)
4790 goto exit;
4791
4792 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
4793 if (time_after_eq(jiffies, lock_recovery_timeout)) {
4794 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
4795 return QLA_SUCCESS;
4796 else
4797 return QLA_FUNCTION_FAILED;
4798 }
4799
4800 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
4801 if (rval)
4802 goto exit;
4803
4804 if (o_drv_lockid == n_drv_lockid) {
4805 qla83xx_wait_logic();
4806 goto retry_lockid;
4807 } else
4808 return QLA_SUCCESS;
4809
4810exit:
4811 return rval;
4812}
4813
4814void
4815qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4816{
4817 uint16_t options = (requester_id << 15) | BIT_6;
4818 uint32_t data;
6c315553 4819 uint32_t lock_owner;
7d613ac6
SV		 4820 struct qla_hw_data *ha = base_vha->hw;
4821
4822 /* IDC-lock implementation using driver-lock/lock-id remote registers */
4823retry_lock:
4824 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
4825 == QLA_SUCCESS) {
4826 if (data) {
4827 /* Setting lock-id to our function-number */
4828 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4829 ha->portnum);
4830 } else {
6c315553
SK		 4831 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
4832 &lock_owner);
7d613ac6 4833 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 4834 "Failed to acquire IDC lock, acquired by %d, "
4835 "retrying...\n", lock_owner);
7d613ac6
SV		 4836
4837 /* Retry/Perform IDC-Lock recovery */
4838 if (qla83xx_idc_lock_recovery(base_vha)
4839 == QLA_SUCCESS) {
4840 qla83xx_wait_logic();
4841 goto retry_lock;
4842 } else
4843 ql_log(ql_log_warn, base_vha, 0xb075,
4844 "IDC Lock recovery FAILED.\n");
4845 }
4846
4847 }
4848
4849 return;
4850
4851 /* XXX: IDC-lock implementation using access-control mbx */
4852retry_lock2:
4853 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4854 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
4855 "Failed to acquire IDC lock. retrying...\n");
4856 /* Retry/Perform IDC-Lock recovery */
4857 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
4858 qla83xx_wait_logic();
4859 goto retry_lock2;
4860 } else
4861 ql_log(ql_log_warn, base_vha, 0xb076,
4862 "IDC Lock recovery FAILED.\n");
4863 }
4864
4865 return;
4866}
4867
4868void
4869qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
4870{
5897cb2f
BVA		 4871#if 0
4872 uint16_t options = (requester_id << 15) | BIT_7;
4873#endif
4874 uint16_t retry;
7d613ac6
SV		 4875 uint32_t data;
4876 struct qla_hw_data *ha = base_vha->hw;
4877
4878 /* IDC-unlock implementation using driver-unlock/lock-id
4879 * remote registers
4880 */
4881 retry = 0;
4882retry_unlock:
4883 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
4884 == QLA_SUCCESS) {
4885 if (data == ha->portnum) {
4886 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
4887 /* Clearing lock-id by setting 0xff */
4888 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
4889 } else if (retry < 10) {
4890 /* SV: XXX: IDC unlock retrying needed here? */
4891
4892 /* Retry for IDC-unlock */
4893 qla83xx_wait_logic();
4894 retry++;
4895 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 4896 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4897 goto retry_unlock;
4898 }
4899 } else if (retry < 10) {
4900 /* Retry for IDC-unlock */
4901 qla83xx_wait_logic();
4902 retry++;
4903 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 4904 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 4905 goto retry_unlock;
4906 }
4907
4908 return;
4909
5897cb2f 4910#if 0
7d613ac6
SV		 4911 /* XXX: IDC-unlock implementation using access-control mbx */
4912 retry = 0;
4913retry_unlock2:
4914 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
4915 if (retry < 10) {
4916 /* Retry for IDC-unlock */
4917 qla83xx_wait_logic();
4918 retry++;
4919 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 4920 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 4921 goto retry_unlock2;
4922 }
4923 }
4924
4925 return;
5897cb2f 4926#endif
7d613ac6
SV		 4927}
4928
4929int
4930__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4931{
4932 int rval = QLA_SUCCESS;
4933 struct qla_hw_data *ha = vha->hw;
4934 uint32_t drv_presence;
4935
4936 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4937 if (rval == QLA_SUCCESS) {
4938 drv_presence |= (1 << ha->portnum);
4939 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4940 drv_presence);
4941 }
4942
4943 return rval;
4944}
4945
4946int
4947qla83xx_set_drv_presence(scsi_qla_host_t *vha)
4948{
4949 int rval = QLA_SUCCESS;
4950
4951 qla83xx_idc_lock(vha, 0);
4952 rval = __qla83xx_set_drv_presence(vha);
4953 qla83xx_idc_unlock(vha, 0);
4954
4955 return rval;
4956}
4957
4958int
4959__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4960{
4961 int rval = QLA_SUCCESS;
4962 struct qla_hw_data *ha = vha->hw;
4963 uint32_t drv_presence;
4964
4965 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
4966 if (rval == QLA_SUCCESS) {
4967 drv_presence &= ~(1 << ha->portnum);
4968 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
4969 drv_presence);
4970 }
4971
4972 return rval;
4973}
4974
4975int
4976qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
4977{
4978 int rval = QLA_SUCCESS;
4979
4980 qla83xx_idc_lock(vha, 0);
4981 rval = __qla83xx_clear_drv_presence(vha);
4982 qla83xx_idc_unlock(vha, 0);
4983
4984 return rval;
4985}
4986
fa492630 4987static void
7d613ac6
SV		 4988qla83xx_need_reset_handler(scsi_qla_host_t *vha)
4989{
4990 struct qla_hw_data *ha = vha->hw;
4991 uint32_t drv_ack, drv_presence;
4992 unsigned long ack_timeout;
4993
4994 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
4995 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
4996 while (1) {
4997 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
4998 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 4999 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5000 break;
5001
5002 if (time_after_eq(jiffies, ack_timeout)) {
5003 ql_log(ql_log_warn, vha, 0xb067,
5004 "RESET ACK TIMEOUT! drv_presence=0x%x "
5005 "drv_ack=0x%x\n", drv_presence, drv_ack);
5006 /*
5007 * The function(s) which did not ack in time are forced
5008 * to withdraw any further participation in the IDC
5009 * reset.
5010 */
5011 if (drv_ack != drv_presence)
5012 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5013 drv_ack);
5014 break;
5015 }
5016
5017 qla83xx_idc_unlock(vha, 0);
5018 msleep(1000);
5019 qla83xx_idc_lock(vha, 0);
5020 }
5021
5022 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5023 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5024}
5025
fa492630 5026static int
7d613ac6
SV		 5027qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5028{
5029 int rval = QLA_SUCCESS;
5030 uint32_t idc_control;
5031
5032 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5033 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5034
5035 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5036 __qla83xx_get_idc_control(vha, &idc_control);
5037 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5038 __qla83xx_set_idc_control(vha, 0);
5039
5040 qla83xx_idc_unlock(vha, 0);
5041 rval = qla83xx_restart_nic_firmware(vha);
5042 qla83xx_idc_lock(vha, 0);
5043
5044 if (rval != QLA_SUCCESS) {
5045 ql_log(ql_log_fatal, vha, 0xb06a,
5046 "Failed to restart NIC f/w.\n");
5047 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5048 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5049 } else {
5050 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5051 "Success in restarting nic f/w.\n");
5052 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5053 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5054 }
5055
5056 return rval;
5057}
5058
5059/* Assumes idc_lock always held on entry */
5060int
5061qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5062{
5063 struct qla_hw_data *ha = base_vha->hw;
5064 int rval = QLA_SUCCESS;
5065 unsigned long dev_init_timeout;
5066 uint32_t dev_state;
5067
5068 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5069 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5070
5071 while (1) {
5072
5073 if (time_after_eq(jiffies, dev_init_timeout)) {
5074 ql_log(ql_log_warn, base_vha, 0xb06e,
5075 "Initialization TIMEOUT!\n");
5076 /* Init timeout. Disable further NIC Core
5077 * communication.
5078 */
5079 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5080 QLA8XXX_DEV_FAILED);
5081 ql_log(ql_log_info, base_vha, 0xb06f,
5082 "HW State: FAILED.\n");
5083 }
5084
5085 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5086 switch (dev_state) {
5087 case QLA8XXX_DEV_READY:
5088 if (ha->flags.nic_core_reset_owner)
5089 qla83xx_idc_audit(base_vha,
5090 IDC_AUDIT_COMPLETION);
5091 ha->flags.nic_core_reset_owner = 0;
5092 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5093 "Reset_owner reset by 0x%x.\n",
5094 ha->portnum);
5095 goto exit;
5096 case QLA8XXX_DEV_COLD:
5097 if (ha->flags.nic_core_reset_owner)
5098 rval = qla83xx_device_bootstrap(base_vha);
5099 else {
5100 /* Wait for AEN to change device-state */
5101 qla83xx_idc_unlock(base_vha, 0);
5102 msleep(1000);
5103 qla83xx_idc_lock(base_vha, 0);
5104 }
5105 break;
5106 case QLA8XXX_DEV_INITIALIZING:
5107 /* Wait for AEN to change device-state */
5108 qla83xx_idc_unlock(base_vha, 0);
5109 msleep(1000);
5110 qla83xx_idc_lock(base_vha, 0);
5111 break;
5112 case QLA8XXX_DEV_NEED_RESET:
5113 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5114 qla83xx_need_reset_handler(base_vha);
5115 else {
5116 /* Wait for AEN to change device-state */
5117 qla83xx_idc_unlock(base_vha, 0);
5118 msleep(1000);
5119 qla83xx_idc_lock(base_vha, 0);
5120 }
5121 /* reset timeout value after need reset handler */
5122 dev_init_timeout = jiffies +
5123 (ha->fcoe_dev_init_timeout * HZ);
5124 break;
5125 case QLA8XXX_DEV_NEED_QUIESCENT:
5126 /* XXX: DEBUG for now */
5127 qla83xx_idc_unlock(base_vha, 0);
5128 msleep(1000);
5129 qla83xx_idc_lock(base_vha, 0);
5130 break;
5131 case QLA8XXX_DEV_QUIESCENT:
5132 /* XXX: DEBUG for now */
5133 if (ha->flags.quiesce_owner)
5134 goto exit;
5135
5136 qla83xx_idc_unlock(base_vha, 0);
5137 msleep(1000);
5138 qla83xx_idc_lock(base_vha, 0);
5139 dev_init_timeout = jiffies +
5140 (ha->fcoe_dev_init_timeout * HZ);
5141 break;
5142 case QLA8XXX_DEV_FAILED:
5143 if (ha->flags.nic_core_reset_owner)
5144 qla83xx_idc_audit(base_vha,
5145 IDC_AUDIT_COMPLETION);
5146 ha->flags.nic_core_reset_owner = 0;
5147 __qla83xx_clear_drv_presence(base_vha);
5148 qla83xx_idc_unlock(base_vha, 0);
5149 qla8xxx_dev_failed_handler(base_vha);
5150 rval = QLA_FUNCTION_FAILED;
5151 qla83xx_idc_lock(base_vha, 0);
5152 goto exit;
5153 case QLA8XXX_BAD_VALUE:
5154 qla83xx_idc_unlock(base_vha, 0);
5155 msleep(1000);
5156 qla83xx_idc_lock(base_vha, 0);
5157 break;
5158 default:
5159 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5160 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5161 qla83xx_idc_unlock(base_vha, 0);
5162 qla8xxx_dev_failed_handler(base_vha);
5163 rval = QLA_FUNCTION_FAILED;
5164 qla83xx_idc_lock(base_vha, 0);
5165 goto exit;
5166 }
5167 }
5168
5169exit:
5170 return rval;
5171}
5172
f3ddac19
CD		 5173void
5174qla2x00_disable_board_on_pci_error(struct work_struct *work)
5175{
5176 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5177 board_disable);
5178 struct pci_dev *pdev = ha->pdev;
5179 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5180
783e0dc4
SC		 5181 /* if UNLOAD flag is already set, then continue unload,
5182 * where it was set first.
5183 */
5184 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5185 return;
5186
f3ddac19
CD		 5187 ql_log(ql_log_warn, base_vha, 0x015b,
5188 "Disabling adapter.\n");
5189
5190 set_bit(UNLOADING, &base_vha->dpc_flags);
5191
5192 qla2x00_delete_all_vps(ha, base_vha);
5193
5194 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5195
5196 qla2x00_dfs_remove(base_vha);
5197
5198 qla84xx_put_chip(base_vha);
5199
5200 if (base_vha->timer_active)
5201 qla2x00_stop_timer(base_vha);
5202
5203 base_vha->flags.online = 0;
5204
5205 qla2x00_destroy_deferred_work(ha);
5206
5207 /*
5208 * Do not try to stop beacon blink as it will issue a mailbox
5209 * command.
5210 */
5211 qla2x00_free_sysfs_attr(base_vha, false);
5212
5213 fc_remove_host(base_vha->host);
5214
5215 scsi_remove_host(base_vha->host);
5216
5217 base_vha->flags.init_done = 0;
5218 qla25xx_delete_queues(base_vha);
f3ddac19 5219 qla2x00_free_fcports(base_vha);
093df737 5220 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5221 qla2x00_mem_free(ha);
5222 qla82xx_md_free(base_vha);
5223 qla2x00_free_queues(ha);
5224
f3ddac19
CD		 5225 qla2x00_unmap_iobases(ha);
5226
5227 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5228 pci_disable_pcie_error_reporting(pdev);
5229 pci_disable_device(pdev);
f3ddac19 5230
beb9e315
JL		 5231 /*
5232 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5233 */
f3ddac19
CD		 5234}
5235
1da177e4
LT		 5236/**************************************************************************
5237* qla2x00_do_dpc
5238* This kernel thread is a task that is schedule by the interrupt handler
5239* to perform the background processing for interrupts.
5240*
5241* Notes:
5242* This task always run in the context of a kernel thread. It
5243* is kick-off by the driver's detect code and starts up
5244* up one per adapter. It immediately goes to sleep and waits for
5245* some fibre event. When either the interrupt handler or
5246* the timer routine detects a event it will one of the task
5247* bits then wake us up.
5248**************************************************************************/
5249static int
5250qla2x00_do_dpc(void *data)
5251{
e315cd28
AC		 5252 scsi_qla_host_t *base_vha;
5253 struct qla_hw_data *ha;
d7459527
MH		 5254 uint32_t online;
5255 struct qla_qpair *qpair;
1da177e4 5256
e315cd28
AC		 5257 ha = (struct qla_hw_data *)data;
5258 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5259
8698a745 5260 set_user_nice(current, MIN_NICE);
1da177e4 5261
563585ec 5262 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5263 while (!kthread_should_stop()) {
7c3df132
SK		 5264 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5265 "DPC handler sleeping.\n");
1da177e4 5266
39a11240 5267 schedule();
1da177e4 5268
c142caf0
AV		 5269 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5270 goto end_loop;
1da177e4 5271
85880801 5272 if (ha->flags.eeh_busy) {
7c3df132
SK		 5273 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5274 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5275 goto end_loop;
85880801
AV		 5276 }
5277
1da177e4
LT		 5278 ha->dpc_active = 1;
5279
5f28d2d7
SK		 5280 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5281 "DPC handler waking up, dpc_flags=0x%lx.\n",
5282 base_vha->dpc_flags);
1da177e4 5283
a29b3dd7
JC		 5284 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5285 break;
5286
e315cd28 5287 qla2x00_do_work(base_vha);
0971de7f 5288
7ec0effd
AD		 5289 if (IS_P3P_TYPE(ha)) {
5290 if (IS_QLA8044(ha)) {
5291 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5292 &base_vha->dpc_flags)) {
5293 qla8044_idc_lock(ha);
5294 qla8044_wr_direct(base_vha,
5295 QLA8044_CRB_DEV_STATE_INDEX,
5296 QLA8XXX_DEV_FAILED);
5297 qla8044_idc_unlock(ha);
5298 ql_log(ql_log_info, base_vha, 0x4004,
5299 "HW State: FAILED.\n");
5300 qla8044_device_state_handler(base_vha);
5301 continue;
5302 }
5303
5304 } else {
5305 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5306 &base_vha->dpc_flags)) {
5307 qla82xx_idc_lock(ha);
5308 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5309 QLA8XXX_DEV_FAILED);
5310 qla82xx_idc_unlock(ha);
5311 ql_log(ql_log_info, base_vha, 0x0151,
5312 "HW State: FAILED.\n");
5313 qla82xx_device_state_handler(base_vha);
5314 continue;
5315 }
a9083016
GM		 5316 }
5317
5318 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5319 &base_vha->dpc_flags)) {
5320
7c3df132
SK		 5321 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5322 "FCoE context reset scheduled.\n");
a9083016
GM		 5323 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5324 &base_vha->dpc_flags))) {
5325 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5326 /* FCoE-ctx reset failed.
5327 * Escalate to chip-reset
5328 */
5329 set_bit(ISP_ABORT_NEEDED,
5330 &base_vha->dpc_flags);
5331 }
5332 clear_bit(ABORT_ISP_ACTIVE,
5333 &base_vha->dpc_flags);
5334 }
5335
7c3df132
SK		 5336 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5337 "FCoE context reset end.\n");
a9083016 5338 }
8ae6d9c7
GM		 5339 } else if (IS_QLAFX00(ha)) {
5340 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5341 &base_vha->dpc_flags)) {
5342 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5343 "Firmware Reset Recovery\n");
5344 if (qlafx00_reset_initialize(base_vha)) {
5345 /* Failed. Abort isp later. */
5346 if (!test_bit(UNLOADING,
f92f82d6 5347 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5348 set_bit(ISP_UNRECOVERABLE,
5349 &base_vha->dpc_flags);
5350 ql_dbg(ql_dbg_dpc, base_vha,
5351 0x4021,
5352 "Reset Recovery Failed\n");
f92f82d6 5353 }
8ae6d9c7
GM		 5354 }
5355 }
5356
5357 if (test_and_clear_bit(FX00_TARGET_SCAN,
5358 &base_vha->dpc_flags)) {
5359 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5360 "ISPFx00 Target Scan scheduled\n");
5361 if (qlafx00_rescan_isp(base_vha)) {
5362 if (!test_bit(UNLOADING,
5363 &base_vha->dpc_flags))
5364 set_bit(ISP_UNRECOVERABLE,
5365 &base_vha->dpc_flags);
5366 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5367 "ISPFx00 Target Scan Failed\n");
5368 }
5369 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5370 "ISPFx00 Target Scan End\n");
5371 }
e8f5e95d
AB		 5372 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5373 &base_vha->dpc_flags)) {
5374 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5375 "ISPFx00 Host Info resend scheduled\n");
5376 qlafx00_fx_disc(base_vha,
5377 &base_vha->hw->mr.fcport,
5378 FXDISC_REG_HOST_INFO);
5379 }
a9083016
GM		 5380 }
5381
e315cd28
AC		 5382 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5383 &base_vha->dpc_flags)) {
1da177e4 5384
7c3df132
SK		 5385 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5386 "ISP abort scheduled.\n");
1da177e4 5387 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5388 &base_vha->dpc_flags))) {
1da177e4 5389
a9083016 5390 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5391 /* failed. retry later */
5392 set_bit(ISP_ABORT_NEEDED,
e315cd28 5393 &base_vha->dpc_flags);
99363ef8 5394 }
e315cd28
AC		 5395 clear_bit(ABORT_ISP_ACTIVE,
5396 &base_vha->dpc_flags);
99363ef8
SJ		 5397 }
5398
7c3df132
SK		 5399 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5400 "ISP abort end.\n");
1da177e4
LT		 5401 }
5402
a394aac8
DJ		 5403 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5404 &base_vha->dpc_flags)) {
e315cd28 5405 qla2x00_update_fcports(base_vha);
c9c5ced9 5406 }
d97994dc 5407
2d70c103
NB		 5408 if (test_bit(SCR_PENDING, &base_vha->dpc_flags)) {
5409 int ret;
5410 ret = qla2x00_send_change_request(base_vha, 0x3, 0);
5411 if (ret != QLA_SUCCESS)
5412 ql_log(ql_log_warn, base_vha, 0x121,
5413 "Failed to enable receiving of RSCN "
5414 "requests: 0x%x.\n", ret);
5415 clear_bit(SCR_PENDING, &base_vha->dpc_flags);
5416 }
5417
8ae6d9c7
GM		 5418 if (IS_QLAFX00(ha))
5419 goto loop_resync_check;
5420
579d12b5 5421 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5422 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5423 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5424 if (IS_P3P_TYPE(ha)) {
5425 if (IS_QLA82XX(ha))
5426 qla82xx_device_state_handler(base_vha);
5427 if (IS_QLA8044(ha))
5428 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5429 clear_bit(ISP_QUIESCE_NEEDED,
5430 &base_vha->dpc_flags);
5431 if (!ha->flags.quiesce_owner) {
5432 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5433 if (IS_QLA82XX(ha)) {
5434 qla82xx_idc_lock(ha);
5435 qla82xx_clear_qsnt_ready(
5436 base_vha);
5437 qla82xx_idc_unlock(ha);
5438 } else if (IS_QLA8044(ha)) {
5439 qla8044_idc_lock(ha);
5440 qla8044_clear_qsnt_ready(
5441 base_vha);
5442 qla8044_idc_unlock(ha);
5443 }
8fcd6b8b
CD		 5444 }
5445 } else {
5446 clear_bit(ISP_QUIESCE_NEEDED,
5447 &base_vha->dpc_flags);
5448 qla2x00_quiesce_io(base_vha);
579d12b5 5449 }
7c3df132
SK		 5450 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5451 "Quiescence mode end.\n");
579d12b5
SK		 5452 }
5453
e315cd28 5454 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5455 &base_vha->dpc_flags) &&
e315cd28 5456 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5457
7c3df132
SK		 5458 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5459 "Reset marker scheduled.\n");
e315cd28
AC		 5460 qla2x00_rst_aen(base_vha);
5461 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5462 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5463 "Reset marker end.\n");
1da177e4
LT		 5464 }
5465
5466 /* Retry each device up to login retry count */
e315cd28
AC		 5467 if ((test_and_clear_bit(RELOGIN_NEEDED,
5468 &base_vha->dpc_flags)) &&
5469 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5470 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5471
7c3df132
SK		 5472 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5473 "Relogin scheduled.\n");
e315cd28 5474 qla2x00_relogin(base_vha);
7c3df132
SK		 5475 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5476 "Relogin end.\n");
1da177e4 5477 }
8ae6d9c7 5478loop_resync_check:
e315cd28 5479 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5480 &base_vha->dpc_flags)) {
1da177e4 5481
7c3df132
SK		 5482 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5483 "Loop resync scheduled.\n");
1da177e4
LT		 5484
5485 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5486 &base_vha->dpc_flags))) {
1da177e4 5487
52c82823 5488 qla2x00_loop_resync(base_vha);
1da177e4 5489
e315cd28
AC		 5490 clear_bit(LOOP_RESYNC_ACTIVE,
5491 &base_vha->dpc_flags);
1da177e4
LT		 5492 }
5493
7c3df132
SK		 5494 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5495 "Loop resync end.\n");
1da177e4
LT		 5496 }
5497
8ae6d9c7
GM		 5498 if (IS_QLAFX00(ha))
5499 goto intr_on_check;
5500
e315cd28
AC		 5501 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5502 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5503 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5504 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5505 }
5506
8ae6d9c7 5507intr_on_check:
1da177e4 5508 if (!ha->interrupts_on)
fd34f556 5509 ha->isp_ops->enable_intrs(ha);
1da177e4 5510
e315cd28 5511 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5512 &base_vha->dpc_flags)) {
5513 if (ha->beacon_blink_led == 1)
5514 ha->isp_ops->beacon_blink(base_vha);
5515 }
f6df144c 5516
d7459527
MH		 5517 /* qpair online check */
5518 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5519 &base_vha->dpc_flags)) {
5520 if (ha->flags.eeh_busy ||
5521 ha->flags.pci_channel_io_perm_failure)
5522 online = 0;
5523 else
5524 online = 1;
5525
5526 mutex_lock(&ha->mq_lock);
5527 list_for_each_entry(qpair, &base_vha->qp_list,
5528 qp_list_elem)
5529 qpair->online = online;
5530 mutex_unlock(&ha->mq_lock);
5531 }
5532
8ae6d9c7
GM		 5533 if (!IS_QLAFX00(ha))
5534 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5535
1da177e4 5536 ha->dpc_active = 0;
c142caf0 5537end_loop:
563585ec 5538 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5539 } /* End of while(1) */
563585ec 5540 __set_current_state(TASK_RUNNING);
1da177e4 5541
7c3df132
SK		 5542 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5543 "DPC handler exiting.\n");
1da177e4
LT		 5544
5545 /*
5546 * Make sure that nobody tries to wake us up again.
5547 */
1da177e4
LT		 5548 ha->dpc_active = 0;
5549
ac280b67
AV		 5550 /* Cleanup any residual CTX SRBs. */
5551 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5552
39a11240
CH		 5553 return 0;
5554}
5555
5556void
e315cd28 5557qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5558{
e315cd28 5559 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5560 struct task_struct *t = ha->dpc_thread;
5561
e315cd28 5562 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5563 wake_up_process(t);
1da177e4
LT		 5564}
5565
1da177e4
LT		 5566/*
5567* qla2x00_rst_aen
5568* Processes asynchronous reset.
5569*
5570* Input:
5571* ha = adapter block pointer.
5572*/
5573static void
e315cd28 5574qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5575{
e315cd28
AC		 5576 if (vha->flags.online && !vha->flags.reset_active &&
5577 !atomic_read(&vha->loop_down_timer) &&
5578 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5579 do {
e315cd28 5580 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5581
5582 /*
5583 * Issue marker command only when we are going to start
5584 * the I/O.
5585 */
e315cd28
AC		 5586 vha->marker_needed = 1;
5587 } while (!atomic_read(&vha->loop_down_timer) &&
5588 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5589 }
5590}
5591
1da177e4
LT		 5592/**************************************************************************
5593* qla2x00_timer
5594*
5595* Description:
5596* One second timer
5597*
5598* Context: Interrupt
5599***************************************************************************/
2c3dfe3f 5600void
e315cd28 5601qla2x00_timer(scsi_qla_host_t *vha)
1da177e4 5602{
1da177e4 5603 unsigned long cpu_flags = 0;
1da177e4
LT		 5604 int start_dpc = 0;
5605 int index;
5606 srb_t *sp;
85880801 5607 uint16_t w;
e315cd28 5608 struct qla_hw_data *ha = vha->hw;
73208dfd 5609 struct req_que *req;
85880801 5610
a5b36321 5611 if (ha->flags.eeh_busy) {
7c3df132
SK		 5612 ql_dbg(ql_dbg_timer, vha, 0x6000,
5613 "EEH = %d, restarting timer.\n",
5614 ha->flags.eeh_busy);
a5b36321
LC		 5615 qla2x00_restart_timer(vha, WATCH_INTERVAL);
5616 return;
5617 }
5618
f3ddac19
CD		 5619 /*
5620 * Hardware read to raise pending EEH errors during mailbox waits. If
5621 * the read returns -1 then disable the board.
5622 */
5623 if (!pci_channel_offline(ha->pdev)) {
85880801 5624 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 5625 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 5626 }
1da177e4 5627
cefcaba6 5628 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 5629 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 5630 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
5631 start_dpc++;
7ec0effd
AD		 5632 if (IS_QLA82XX(ha))
5633 qla82xx_watchdog(vha);
5634 else if (IS_QLA8044(ha))
5635 qla8044_watchdog(vha);
579d12b5
SK		 5636 }
5637
8ae6d9c7
GM		 5638 if (!vha->vp_idx && IS_QLAFX00(ha))
5639 qlafx00_timer_routine(vha);
5640
1da177e4 5641 /* Loop down handler. */
e315cd28 5642 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 5643 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
5644 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 5645 && vha->flags.online) {
1da177e4 5646
e315cd28
AC		 5647 if (atomic_read(&vha->loop_down_timer) ==
5648 vha->loop_down_abort_time) {
1da177e4 5649
7c3df132
SK		 5650 ql_log(ql_log_info, vha, 0x6008,
5651 "Loop down - aborting the queues before time expires.\n");
1da177e4 5652
e315cd28
AC		 5653 if (!IS_QLA2100(ha) && vha->link_down_timeout)
5654 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 5655
f08b7251
AV		 5656 /*
5657 * Schedule an ISP abort to return any FCP2-device
5658 * commands.
5659 */
2c3dfe3f 5660 /* NPIV - scan physical port only */
e315cd28 5661 if (!vha->vp_idx) {
2c3dfe3f
SJ		 5662 spin_lock_irqsave(&ha->hardware_lock,
5663 cpu_flags);
73208dfd 5664 req = ha->req_q_map[0];
2c3dfe3f 5665 for (index = 1;
8d93f550 5666 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 5667 index++) {
5668 fc_port_t *sfcp;
5669
e315cd28 5670 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 5671 if (!sp)
5672 continue;
9ba56b95 5673 if (sp->type != SRB_SCSI_CMD)
cf53b069 5674 continue;
2c3dfe3f 5675 sfcp = sp->fcport;
f08b7251 5676 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 5677 continue;
bdf79621 5678
8f7daead
GM		 5679 if (IS_QLA82XX(ha))
5680 set_bit(FCOE_CTX_RESET_NEEDED,
5681 &vha->dpc_flags);
5682 else
5683 set_bit(ISP_ABORT_NEEDED,
e315cd28 5684 &vha->dpc_flags);
2c3dfe3f
SJ		 5685 break;
5686 }
5687 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 5688 cpu_flags);
1da177e4 5689 }
1da177e4
LT		 5690 start_dpc++;
5691 }
5692
5693 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 5694 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 5695 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 5696 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 5697 "Loop down - aborting ISP.\n");
5698
8f7daead
GM		 5699 if (IS_QLA82XX(ha))
5700 set_bit(FCOE_CTX_RESET_NEEDED,
5701 &vha->dpc_flags);
5702 else
5703 set_bit(ISP_ABORT_NEEDED,
5704 &vha->dpc_flags);
1da177e4
LT		 5705 }
5706 }
7c3df132
SK		 5707 ql_dbg(ql_dbg_timer, vha, 0x600a,
5708 "Loop down - seconds remaining %d.\n",
5709 atomic_read(&vha->loop_down_timer));
1da177e4 5710 }
cefcaba6
SK		 5711 /* Check if beacon LED needs to be blinked for physical host only */
5712 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 5713 /* There is no beacon_blink function for ISP82xx */
7ec0effd 5714 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 5715 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
5716 start_dpc++;
5717 }
f6df144c
AV		 5718 }
5719
550bf57d 5720 /* Process any deferred work. */
e315cd28 5721 if (!list_empty(&vha->work_list))
550bf57d
AV		 5722 start_dpc++;
5723
1da177e4 5724 /* Schedule the DPC routine if needed */
e315cd28
AC		 5725 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
5726 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
5727 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 5728 start_dpc ||
e315cd28
AC		 5729 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
5730 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 5731 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
5732 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 5733 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 5734 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 5735 ql_dbg(ql_dbg_timer, vha, 0x600b,
5736 "isp_abort_needed=%d loop_resync_needed=%d "
5737 "fcport_update_needed=%d start_dpc=%d "
5738 "reset_marker_needed=%d",
5739 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
5740 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
5741 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
5742 start_dpc,
5743 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
5744 ql_dbg(ql_dbg_timer, vha, 0x600c,
5745 "beacon_blink_needed=%d isp_unrecoverable=%d "
5746 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 5747 "relogin_needed=%d.\n",
7c3df132
SK		 5748 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
5749 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
5750 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
5751 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 5752 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 5753 qla2xxx_wake_dpc(vha);
7c3df132 5754 }
1da177e4 5755
e315cd28 5756 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 5757}
5758
5433383e
AV		 5759/* Firmware interface routines. */
5760
f73cb695 5761#define FW_BLOBS 11
5433383e
AV		 5762#define FW_ISP21XX 0
5763#define FW_ISP22XX 1
5764#define FW_ISP2300 2
5765#define FW_ISP2322 3
48c02fde 5766#define FW_ISP24XX 4
c3a2f0df 5767#define FW_ISP25XX 5
3a03eb79 5768#define FW_ISP81XX 6
a9083016 5769#define FW_ISP82XX 7
6246b8a1
GM		 5770#define FW_ISP2031 8
5771#define FW_ISP8031 9
2c5bbbb2 5772#define FW_ISP27XX 10
5433383e 5773
bb8ee499
AV		 5774#define FW_FILE_ISP21XX "ql2100_fw.bin"
5775#define FW_FILE_ISP22XX "ql2200_fw.bin"
5776#define FW_FILE_ISP2300 "ql2300_fw.bin"
5777#define FW_FILE_ISP2322 "ql2322_fw.bin"
5778#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 5779#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 5780#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 5781#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 5782#define FW_FILE_ISP2031 "ql2600_fw.bin"
5783#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 5784#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 5785
bb8ee499 5786
e1e82b6f 5787static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 5788
5789static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 5790 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
5791 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
5792 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
5793 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
5794 { .name = FW_FILE_ISP24XX, },
c3a2f0df 5795 { .name = FW_FILE_ISP25XX, },
3a03eb79 5796 { .name = FW_FILE_ISP81XX, },
a9083016 5797 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 5798 { .name = FW_FILE_ISP2031, },
5799 { .name = FW_FILE_ISP8031, },
2c5bbbb2 5800 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 5801};
5802
5803struct fw_blob *
e315cd28 5804qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 5805{
e315cd28 5806 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 5807 struct fw_blob *blob;
5808
5433383e
AV		 5809 if (IS_QLA2100(ha)) {
5810 blob = &qla_fw_blobs[FW_ISP21XX];
5811 } else if (IS_QLA2200(ha)) {
5812 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 5813 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 5814 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 5815 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 5816 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 5817 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 5818 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 5819 } else if (IS_QLA25XX(ha)) {
5820 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 5821 } else if (IS_QLA81XX(ha)) {
5822 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 5823 } else if (IS_QLA82XX(ha)) {
5824 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 5825 } else if (IS_QLA2031(ha)) {
5826 blob = &qla_fw_blobs[FW_ISP2031];
5827 } else if (IS_QLA8031(ha)) {
5828 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 5829 } else if (IS_QLA27XX(ha)) {
5830 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 5831 } else {
5832 return NULL;
5433383e
AV		 5833 }
5834
e1e82b6f 5835 mutex_lock(&qla_fw_lock);
5433383e
AV		 5836 if (blob->fw)
5837 goto out;
5838
5839 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 5840 ql_log(ql_log_warn, vha, 0x0063,
5841 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 5842 blob->fw = NULL;
5843 blob = NULL;
5844 goto out;
5845 }
5846
5847out:
e1e82b6f 5848 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5849 return blob;
5850}
5851
5852static void
5853qla2x00_release_firmware(void)
5854{
5855 int idx;
5856
e1e82b6f 5857 mutex_lock(&qla_fw_lock);
5433383e 5858 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 5859 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 5860 mutex_unlock(&qla_fw_lock);
5433383e
AV		 5861}
5862
14e660e6
SJ		 5863static pci_ers_result_t
5864qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5865{
85880801
AV		 5866 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
5867 struct qla_hw_data *ha = vha->hw;
5868
7c3df132
SK		 5869 ql_dbg(ql_dbg_aer, vha, 0x9000,
5870 "PCI error detected, state %x.\n", state);
b9b12f73 5871
14e660e6
SJ		 5872 switch (state) {
5873 case pci_channel_io_normal:
85880801 5874 ha->flags.eeh_busy = 0;
d7459527
MH		 5875 if (ql2xmqsupport) {
5876 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5877 qla2xxx_wake_dpc(vha);
5878 }
14e660e6
SJ		 5879 return PCI_ERS_RESULT_CAN_RECOVER;
5880 case pci_channel_io_frozen:
85880801 5881 ha->flags.eeh_busy = 1;
a5b36321
LC		 5882 /* For ISP82XX complete any pending mailbox cmd */
5883 if (IS_QLA82XX(ha)) {
7190575f 5884 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 5885 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
5886 qla82xx_clear_pending_mbx(vha);
a5b36321 5887 }
90a86fc0 5888 qla2x00_free_irqs(vha);
14e660e6 5889 pci_disable_device(pdev);
bddd2d65
LC		 5890 /* Return back all IOs */
5891 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 5892 if (ql2xmqsupport) {
5893 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5894 qla2xxx_wake_dpc(vha);
5895 }
14e660e6
SJ		 5896 return PCI_ERS_RESULT_NEED_RESET;
5897 case pci_channel_io_perm_failure:
85880801
AV		 5898 ha->flags.pci_channel_io_perm_failure = 1;
5899 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 5900 if (ql2xmqsupport) {
5901 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
5902 qla2xxx_wake_dpc(vha);
5903 }
14e660e6
SJ		 5904 return PCI_ERS_RESULT_DISCONNECT;
5905 }
5906 return PCI_ERS_RESULT_NEED_RESET;
5907}
5908
5909static pci_ers_result_t
5910qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
5911{
5912 int risc_paused = 0;
5913 uint32_t stat;
5914 unsigned long flags;
e315cd28
AC		 5915 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
5916 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 5917 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
5918 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
5919
bcc5b6d3
SK		 5920 if (IS_QLA82XX(ha))
5921 return PCI_ERS_RESULT_RECOVERED;
5922
14e660e6
SJ		 5923 spin_lock_irqsave(&ha->hardware_lock, flags);
5924 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
5925 stat = RD_REG_DWORD(&reg->hccr);
5926 if (stat & HCCR_RISC_PAUSE)
5927 risc_paused = 1;
5928 } else if (IS_QLA23XX(ha)) {
5929 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
5930 if (stat & HSR_RISC_PAUSED)
5931 risc_paused = 1;
5932 } else if (IS_FWI2_CAPABLE(ha)) {
5933 stat = RD_REG_DWORD(&reg24->host_status);
5934 if (stat & HSRX_RISC_PAUSED)
5935 risc_paused = 1;
5936 }
5937 spin_unlock_irqrestore(&ha->hardware_lock, flags);
5938
5939 if (risc_paused) {
7c3df132
SK		 5940 ql_log(ql_log_info, base_vha, 0x9003,
5941 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 5942 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 5943
5944 return PCI_ERS_RESULT_NEED_RESET;
5945 } else
5946 return PCI_ERS_RESULT_RECOVERED;
5947}
5948
fa492630
SK		 5949static uint32_t
5950qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 5951{
5952 uint32_t rval = QLA_FUNCTION_FAILED;
5953 uint32_t drv_active = 0;
5954 struct qla_hw_data *ha = base_vha->hw;
5955 int fn;
5956 struct pci_dev *other_pdev = NULL;
5957
7c3df132
SK		 5958 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
5959 "Entered %s.\n", __func__);
a5b36321
LC		 5960
5961 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
5962
5963 if (base_vha->flags.online) {
5964 /* Abort all outstanding commands,
5965 * so as to be requeued later */
5966 qla2x00_abort_isp_cleanup(base_vha);
5967 }
5968
5969
5970 fn = PCI_FUNC(ha->pdev->devfn);
5971 while (fn > 0) {
5972 fn--;
7c3df132
SK		 5973 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
5974 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 5975 other_pdev =
5976 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
5977 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
5978 fn));
5979
5980 if (!other_pdev)
5981 continue;
5982 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 5983 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
5984 "Found PCI func available and enable at 0x%x.\n",
5985 fn);
a5b36321
LC		 5986 pci_dev_put(other_pdev);
5987 break;
5988 }
5989 pci_dev_put(other_pdev);
5990 }
5991
5992 if (!fn) {
5993 /* Reset owner */
7c3df132
SK		 5994 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
5995 "This devfn is reset owner = 0x%x.\n",
5996 ha->pdev->devfn);
a5b36321
LC		 5997 qla82xx_idc_lock(ha);
5998
5999 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6000 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6001
6002 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6003 QLA82XX_IDC_VERSION);
6004
6005 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6006 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6007 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6008
6009 qla82xx_idc_unlock(ha);
6010 /* Reset if device is not already reset
6011 * drv_active would be 0 if a reset has already been done
6012 */
6013 if (drv_active)
6014 rval = qla82xx_start_firmware(base_vha);
6015 else
6016 rval = QLA_SUCCESS;
6017 qla82xx_idc_lock(ha);
6018
6019 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6020 ql_log(ql_log_info, base_vha, 0x900b,
6021 "HW State: FAILED.\n");
a5b36321
LC		 6022 qla82xx_clear_drv_active(ha);
6023 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6024 QLA8XXX_DEV_FAILED);
a5b36321 6025 } else {
7c3df132
SK		 6026 ql_log(ql_log_info, base_vha, 0x900c,
6027 "HW State: READY.\n");
a5b36321 6028 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6029 QLA8XXX_DEV_READY);
a5b36321 6030 qla82xx_idc_unlock(ha);
7190575f 6031 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6032 rval = qla82xx_restart_isp(base_vha);
6033 qla82xx_idc_lock(ha);
6034 /* Clear driver state register */
6035 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6036 qla82xx_set_drv_active(base_vha);
6037 }
6038 qla82xx_idc_unlock(ha);
6039 } else {
7c3df132
SK		 6040 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6041 "This devfn is not reset owner = 0x%x.\n",
6042 ha->pdev->devfn);
a5b36321 6043 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6044 QLA8XXX_DEV_READY)) {
7190575f 6045 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6046 rval = qla82xx_restart_isp(base_vha);
6047 qla82xx_idc_lock(ha);
6048 qla82xx_set_drv_active(base_vha);
6049 qla82xx_idc_unlock(ha);
6050 }
6051 }
6052 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6053
6054 return rval;
6055}
6056
14e660e6
SJ		 6057static pci_ers_result_t
6058qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6059{
6060 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6061 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6062 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6063 struct rsp_que *rsp;
6064 int rc, retries = 10;
09483916 6065
7c3df132
SK		 6066 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6067 "Slot Reset.\n");
85880801 6068
90a86fc0
JC		 6069 /* Workaround: qla2xxx driver which access hardware earlier
6070 * needs error state to be pci_channel_io_online.
6071 * Otherwise mailbox command timesout.
6072 */
6073 pdev->error_state = pci_channel_io_normal;
6074
6075 pci_restore_state(pdev);
6076
8c1496bd
RL		 6077 /* pci_restore_state() clears the saved_state flag of the device
6078 * save restored state which resets saved_state flag
6079 */
6080 pci_save_state(pdev);
6081
09483916
BH		 6082 if (ha->mem_only)
6083 rc = pci_enable_device_mem(pdev);
6084 else
6085 rc = pci_enable_device(pdev);
14e660e6 6086
09483916 6087 if (rc) {
7c3df132 6088 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6089 "Can't re-enable PCI device after reset.\n");
a5b36321 6090 goto exit_slot_reset;
14e660e6 6091 }
14e660e6 6092
90a86fc0
JC		 6093 rsp = ha->rsp_q_map[0];
6094 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6095 goto exit_slot_reset;
90a86fc0 6096
e315cd28 6097 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6098 goto exit_slot_reset;
6099
6100 if (IS_QLA82XX(ha)) {
6101 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6102 ret = PCI_ERS_RESULT_RECOVERED;
6103 goto exit_slot_reset;
6104 } else
6105 goto exit_slot_reset;
6106 }
14e660e6 6107
90a86fc0
JC		 6108 while (ha->flags.mbox_busy && retries--)
6109 msleep(1000);
85880801 6110
e315cd28 6111 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6112 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6113 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6114 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6115
90a86fc0 6116
a5b36321 6117exit_slot_reset:
7c3df132
SK		 6118 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6119 "slot_reset return %x.\n", ret);
85880801 6120
14e660e6
SJ		 6121 return ret;
6122}
6123
6124static void
6125qla2xxx_pci_resume(struct pci_dev *pdev)
6126{
e315cd28
AC		 6127 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6128 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6129 int ret;
6130
7c3df132
SK		 6131 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6132 "pci_resume.\n");
85880801 6133
e315cd28 6134 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6135 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6136 ql_log(ql_log_fatal, base_vha, 0x9002,
6137 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6138 }
85880801 6139
3e46f031
LC		 6140 pci_cleanup_aer_uncorrect_error_status(pdev);
6141
85880801 6142 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6143}
6144
2d5a4c34
HM		 6145static void
6146qla83xx_disable_laser(scsi_qla_host_t *vha)
6147{
6148 uint32_t reg, data, fn;
6149 struct qla_hw_data *ha = vha->hw;
6150 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6151
6152 /* pci func #/port # */
6153 ql_dbg(ql_dbg_init, vha, 0x004b,
6154 "Disabling Laser for hba: %p\n", vha);
6155
6156 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6157 (BIT_15|BIT_14|BIT_13|BIT_12));
6158
6159 fn = (fn >> 12);
6160
6161 if (fn & 1)
6162 reg = PORT_1_2031;
6163 else
6164 reg = PORT_0_2031;
6165
6166 data = LASER_OFF_2031;
6167
6168 qla83xx_wr_reg(vha, reg, data);
6169}
6170
5601236b
MH		 6171static int qla2xxx_map_queues(struct Scsi_Host *shost)
6172{
6173 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6174
6175 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6176}
6177
a55b2d21 6178static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6179 .error_detected = qla2xxx_pci_error_detected,
6180 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6181 .slot_reset = qla2xxx_pci_slot_reset,
6182 .resume = qla2xxx_pci_resume,
6183};
6184
5433383e 6185static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6186 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6187 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6188 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6189 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6190 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6199 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6208 { 0 },
6209};
6210MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6211
fca29703 6212static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6213 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6214 .driver = {
6215 .owner = THIS_MODULE,
6216 },
fca29703 6217 .id_table = qla2xxx_pci_tbl,
7ee61397 6218 .probe = qla2x00_probe_one,
4c993f76 6219 .remove = qla2x00_remove_one,
e30d1756 6220 .shutdown = qla2x00_shutdown,
14e660e6 6221 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6222};
6223
75ef9de1 6224static const struct file_operations apidev_fops = {
6a03b4cd 6225 .owner = THIS_MODULE,
6038f373 6226 .llseek = noop_llseek,
6a03b4cd
HZ		 6227};
6228
1da177e4
LT		 6229/**
6230 * qla2x00_module_init - Module initialization.
6231 **/
6232static int __init
6233qla2x00_module_init(void)
6234{
fca29703
AV		 6235 int ret = 0;
6236
1da177e4 6237 /* Allocate cache for SRBs. */
354d6b21 6238 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6239 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6240 if (srb_cachep == NULL) {
7c3df132
SK		 6241 ql_log(ql_log_fatal, NULL, 0x0001,
6242 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6243 return -ENOMEM;
6244 }
6245
2d70c103
NB		 6246 /* Initialize target kmem_cache and mem_pools */
6247 ret = qlt_init();
6248 if (ret < 0) {
6249 kmem_cache_destroy(srb_cachep);
6250 return ret;
6251 } else if (ret > 0) {
6252 /*
6253 * If initiator mode is explictly disabled by qlt_init(),
6254 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6255 * performing scsi_scan_target() during LOOP UP event.
6256 */
6257 qla2xxx_transport_functions.disable_target_scan = 1;
6258 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6259 }
6260
1da177e4
LT		 6261 /* Derive version string. */
6262 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6263 if (ql2xextended_error_logging)
0181944f
AV		 6264 strcat(qla2x00_version_str, "-debug");
6265
1c97a12a
AV		 6266 qla2xxx_transport_template =
6267 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6268 if (!qla2xxx_transport_template) {
6269 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6270 ql_log(ql_log_fatal, NULL, 0x0002,
6271 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6272 qlt_exit();
1da177e4 6273 return -ENODEV;
2c3dfe3f 6274 }
6a03b4cd
HZ		 6275
6276 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6277 if (apidev_major < 0) {
7c3df132
SK		 6278 ql_log(ql_log_fatal, NULL, 0x0003,
6279 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6280 }
6281
2c3dfe3f
SJ		 6282 qla2xxx_transport_vport_template =
6283 fc_attach_transport(&qla2xxx_transport_vport_functions);
6284 if (!qla2xxx_transport_vport_template) {
6285 kmem_cache_destroy(srb_cachep);
2d70c103 6286 qlt_exit();
2c3dfe3f 6287 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6288 ql_log(ql_log_fatal, NULL, 0x0004,
6289 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6290 return -ENODEV;
2c3dfe3f 6291 }
7c3df132
SK		 6292 ql_log(ql_log_info, NULL, 0x0005,
6293 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6294 qla2x00_version_str);
7ee61397 6295 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6296 if (ret) {
6297 kmem_cache_destroy(srb_cachep);
2d70c103 6298 qlt_exit();
fca29703 6299 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6300 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6301 ql_log(ql_log_fatal, NULL, 0x0006,
6302 "pci_register_driver failed...ret=%d Failing load!.\n",
6303 ret);
fca29703
AV		 6304 }
6305 return ret;
1da177e4
LT		 6306}
6307
6308/**
6309 * qla2x00_module_exit - Module cleanup.
6310 **/
6311static void __exit
6312qla2x00_module_exit(void)
6313{
6a03b4cd 6314 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6315 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6316 qla2x00_release_firmware();
354d6b21 6317 kmem_cache_destroy(srb_cachep);
2d70c103 6318 qlt_exit();
a9083016
GM		 6319 if (ctx_cachep)
6320 kmem_cache_destroy(ctx_cachep);
1da177e4 6321 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6322 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6323}
6324
6325module_init(qla2x00_module_init);
6326module_exit(qla2x00_module_exit);
6327
6328MODULE_AUTHOR("QLogic Corporation");
6329MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6330MODULE_LICENSE("GPL");
6331MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6332MODULE_FIRMWARE(FW_FILE_ISP21XX);
6333MODULE_FIRMWARE(FW_FILE_ISP22XX);
6334MODULE_FIRMWARE(FW_FILE_ISP2300);
6335MODULE_FIRMWARE(FW_FILE_ISP2322);
6336MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6337MODULE_FIRMWARE(FW_FILE_ISP25XX);
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