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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
e7240af5
HM		 271int ql2xenablemsix = 1;
272module_param(ql2xenablemsix, int, 0444);
273MODULE_PARM_DESC(ql2xenablemsix,
274 "Set to enable MSI or MSI-X interrupt mechanism.\n"
275 " Default is 1, enable MSI-X interrupt mechanism.\n"
276 " 0 -- enable traditional pin-based mechanism.\n"
277 " 1 -- enable MSI-X interrupt mechanism.\n"
278 " 2 -- enable MSI interrupt mechanism.\n");
279
1da177e4 280/*
fa2a1ce5 281 * SCSI host template entry points
1da177e4
LT		 282 */
283static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 284static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 285static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
286static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 287static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 288static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 289static int qla2xxx_eh_abort(struct scsi_cmnd *);
290static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 291static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 292static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
293static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 294
1a2fbf18 295static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 296static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 297static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 298static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 299static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 300
a5326f86 301struct scsi_host_template qla2xxx_driver_template = {
1da177e4 302 .module = THIS_MODULE,
cb63067a 303 .name = QLA2XXX_DRIVER_NAME,
a5326f86 304 .queuecommand = qla2xxx_queuecommand,
fca29703 305
b6a05c82 306 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 307 .eh_abort_handler = qla2xxx_eh_abort,
308 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 309 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 310 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
311 .eh_host_reset_handler = qla2xxx_eh_host_reset,
312
313 .slave_configure = qla2xxx_slave_configure,
314
315 .slave_alloc = qla2xxx_slave_alloc,
316 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 317 .scan_finished = qla2xxx_scan_finished,
318 .scan_start = qla2xxx_scan_start,
db5ed4df 319 .change_queue_depth = scsi_change_queue_depth,
5601236b 320 .map_queues = qla2xxx_map_queues,
fca29703
AV		 321 .this_id = -1,
322 .cmd_per_lun = 3,
323 .use_clustering = ENABLE_CLUSTERING,
324 .sg_tablesize = SG_ALL,
325
326 .max_sectors = 0xFFFF,
afb046e2 327 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 328
329 .supported_mode = MODE_INITIATOR,
c40ecc12 330 .track_queue_depth = 1,
fca29703
AV		 331};
332
1da177e4 333static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 334struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 335
1da177e4
LT		 336/* TODO Convert to inlines
337 *
338 * Timer routines
339 */
1da177e4 340
2c3dfe3f 341__inline__ void
8e5f4ba0 342qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 343{
8e5f4ba0 344 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 345 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 346 add_timer(&vha->timer);
347 vha->timer_active = 1;
1da177e4
LT		 348}
349
350static inline void
e315cd28 351qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 352{
a9083016 353 /* Currently used for 82XX only. */
7c3df132
SK		 354 if (vha->device_flags & DFLG_DEV_FAILED) {
355 ql_dbg(ql_dbg_timer, vha, 0x600d,
356 "Device in a failed state, returning.\n");
a9083016 357 return;
7c3df132 358 }
a9083016 359
e315cd28 360 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 361}
362
a824ebb3 363static __inline__ void
e315cd28 364qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 365{
e315cd28
AC		 366 del_timer_sync(&vha->timer);
367 vha->timer_active = 0;
1da177e4
LT		 368}
369
1da177e4
LT		 370static int qla2x00_do_dpc(void *data);
371
372static void qla2x00_rst_aen(scsi_qla_host_t *);
373
73208dfd
AC		 374static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
375 struct req_que **, struct rsp_que **);
e30d1756 376static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 377static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 378int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
379 struct qla_qpair *qpair);
1da177e4 380
1da177e4 381/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 382static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
383 struct rsp_que *rsp)
384{
385 struct qla_hw_data *ha = vha->hw;
386 rsp->qpair = ha->base_qpair;
387 rsp->req = req;
388 ha->base_qpair->req = req;
389 ha->base_qpair->rsp = rsp;
390 ha->base_qpair->vha = vha;
391 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
392 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
393 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
394 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
cf19c45d 395 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
8abfa9e2
QT		 396 ha->base_qpair->enable_class_2 = ql2xenableclass2;
397 /* init qpair to this cpu. Will adjust at run time. */
86531887 398 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 399 ha->base_qpair->pdev = ha->pdev;
400
401 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
402 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
403}
404
9a347ff4
CD		 405static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
406 struct rsp_que *rsp)
73208dfd 407{
7c3df132 408 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 409 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 410 GFP_KERNEL);
411 if (!ha->req_q_map) {
7c3df132
SK		 412 ql_log(ql_log_fatal, vha, 0x003b,
413 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 414 goto fail_req_map;
415 }
416
2afa19a9 417 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 418 GFP_KERNEL);
419 if (!ha->rsp_q_map) {
7c3df132
SK		 420 ql_log(ql_log_fatal, vha, 0x003c,
421 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 422 goto fail_rsp_map;
423 }
d7459527 424
e326d22a
QT		 425 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
426 if (ha->base_qpair == NULL) {
427 ql_log(ql_log_warn, vha, 0x00e0,
428 "Failed to allocate base queue pair memory.\n");
429 goto fail_base_qpair;
430 }
431
8abfa9e2 432 qla_init_base_qpair(vha, req, rsp);
e326d22a 433
c38d1baf 434 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 435 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
436 GFP_KERNEL);
437 if (!ha->queue_pair_map) {
438 ql_log(ql_log_fatal, vha, 0x0180,
439 "Unable to allocate memory for queue pair ptrs.\n");
440 goto fail_qpair_map;
441 }
d7459527
MH		 442 }
443
9a347ff4
CD		 444 /*
445 * Make sure we record at least the request and response queue zero in
446 * case we need to free them if part of the probe fails.
447 */
448 ha->rsp_q_map[0] = rsp;
449 ha->req_q_map[0] = req;
73208dfd
AC		 450 set_bit(0, ha->rsp_qid_map);
451 set_bit(0, ha->req_qid_map);
79c67fb6 452 return 0;
73208dfd 453
d7459527 454fail_qpair_map:
82de802a
QT		 455 kfree(ha->base_qpair);
456 ha->base_qpair = NULL;
457fail_base_qpair:
d7459527
MH		 458 kfree(ha->rsp_q_map);
459 ha->rsp_q_map = NULL;
73208dfd
AC		 460fail_rsp_map:
461 kfree(ha->req_q_map);
462 ha->req_q_map = NULL;
463fail_req_map:
464 return -ENOMEM;
465}
466
2afa19a9 467static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 468{
8ae6d9c7
GM		 469 if (IS_QLAFX00(ha)) {
470 if (req && req->ring_fx00)
471 dma_free_coherent(&ha->pdev->dev,
472 (req->length_fx00 + 1) * sizeof(request_t),
473 req->ring_fx00, req->dma_fx00);
474 } else if (req && req->ring)
73208dfd
AC		 475 dma_free_coherent(&ha->pdev->dev,
476 (req->length + 1) * sizeof(request_t),
477 req->ring, req->dma);
478
a5082923 479 if (req)
8d93f550 480 kfree(req->outstanding_cmds);
a5082923
BK		 481
482 kfree(req);
73208dfd
AC		 483}
484
2afa19a9
AC		 485static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
486{
8ae6d9c7
GM		 487 if (IS_QLAFX00(ha)) {
488 if (rsp && rsp->ring)
489 dma_free_coherent(&ha->pdev->dev,
490 (rsp->length_fx00 + 1) * sizeof(request_t),
491 rsp->ring_fx00, rsp->dma_fx00);
492 } else if (rsp && rsp->ring) {
2afa19a9
AC		 493 dma_free_coherent(&ha->pdev->dev,
494 (rsp->length + 1) * sizeof(response_t),
495 rsp->ring, rsp->dma);
8ae6d9c7 496 }
a5082923 497 kfree(rsp);
2afa19a9
AC		 498}
499
73208dfd
AC		 500static void qla2x00_free_queues(struct qla_hw_data *ha)
501{
502 struct req_que *req;
503 struct rsp_que *rsp;
504 int cnt;
093df737 505 unsigned long flags;
73208dfd 506
82de802a
QT		 507 if (ha->queue_pair_map) {
508 kfree(ha->queue_pair_map);
509 ha->queue_pair_map = NULL;
510 }
511 if (ha->base_qpair) {
512 kfree(ha->base_qpair);
513 ha->base_qpair = NULL;
514 }
515
093df737 516 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 517 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 518 if (!test_bit(cnt, ha->req_qid_map))
519 continue;
520
73208dfd 521 req = ha->req_q_map[cnt];
093df737
QT		 522 clear_bit(cnt, ha->req_qid_map);
523 ha->req_q_map[cnt] = NULL;
524
525 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 526 qla2x00_free_req_que(ha, req);
093df737 527 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 528 }
093df737
QT		 529 spin_unlock_irqrestore(&ha->hardware_lock, flags);
530
73208dfd
AC		 531 kfree(ha->req_q_map);
532 ha->req_q_map = NULL;
2afa19a9 533
093df737
QT		 534
535 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 536 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 537 if (!test_bit(cnt, ha->rsp_qid_map))
538 continue;
539
2afa19a9 540 rsp = ha->rsp_q_map[cnt];
c3c42394 541 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 542 ha->rsp_q_map[cnt] = NULL;
543 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 544 qla2x00_free_rsp_que(ha, rsp);
093df737 545 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 546 }
093df737
QT		 547 spin_unlock_irqrestore(&ha->hardware_lock, flags);
548
2afa19a9
AC		 549 kfree(ha->rsp_q_map);
550 ha->rsp_q_map = NULL;
73208dfd
AC		 551}
552
1da177e4 553static char *
e315cd28 554qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 555{
e315cd28 556 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 557 static char *pci_bus_modes[] = {
558 "33", "66", "100", "133",
559 };
560 uint16_t pci_bus;
561
562 strcpy(str, "PCI");
563 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
564 if (pci_bus) {
565 strcat(str, "-X (");
566 strcat(str, pci_bus_modes[pci_bus]);
567 } else {
568 pci_bus = (ha->pci_attr & BIT_8) >> 8;
569 strcat(str, " (");
570 strcat(str, pci_bus_modes[pci_bus]);
571 }
572 strcat(str, " MHz)");
573
574 return (str);
575}
576
fca29703 577static char *
e315cd28 578qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 579{
580 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 581 struct qla_hw_data *ha = vha->hw;
fca29703 582 uint32_t pci_bus;
fca29703 583
62a276f8 584 if (pci_is_pcie(ha->pdev)) {
fca29703 585 char lwstr[6];
62a276f8 586 uint32_t lstat, lspeed, lwidth;
fca29703 587
62a276f8
BH		 588 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
589 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
590 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 591
592 strcpy(str, "PCIe (");
49300af7
SK		 593 switch (lspeed) {
594 case 1:
c87a0d8c 595 strcat(str, "2.5GT/s ");
49300af7
SK		 596 break;
597 case 2:
c87a0d8c 598 strcat(str, "5.0GT/s ");
49300af7
SK		 599 break;
600 case 3:
601 strcat(str, "8.0GT/s ");
602 break;
603 default:
fca29703 604 strcat(str, "<unknown> ");
49300af7
SK		 605 break;
606 }
fca29703
AV		 607 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
608 strcat(str, lwstr);
609
610 return str;
611 }
612
613 strcpy(str, "PCI");
614 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
615 if (pci_bus == 0 || pci_bus == 8) {
616 strcat(str, " (");
617 strcat(str, pci_bus_modes[pci_bus >> 3]);
618 } else {
619 strcat(str, "-X ");
620 if (pci_bus & BIT_2)
621 strcat(str, "Mode 2");
622 else
623 strcat(str, "Mode 1");
624 strcat(str, " (");
625 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
626 }
627 strcat(str, " MHz)");
628
629 return str;
630}
631
e5f82ab8 632static char *
df57caba 633qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 634{
635 char un_str[10];
e315cd28 636 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 637
df57caba
HM		 638 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
639 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 640
641 if (ha->fw_attributes & BIT_9) {
642 strcat(str, "FLX");
643 return (str);
644 }
645
646 switch (ha->fw_attributes & 0xFF) {
647 case 0x7:
648 strcat(str, "EF");
649 break;
650 case 0x17:
651 strcat(str, "TP");
652 break;
653 case 0x37:
654 strcat(str, "IP");
655 break;
656 case 0x77:
657 strcat(str, "VI");
658 break;
659 default:
660 sprintf(un_str, "(%x)", ha->fw_attributes);
661 strcat(str, un_str);
662 break;
663 }
664 if (ha->fw_attributes & 0x100)
665 strcat(str, "X");
666
667 return (str);
668}
669
e5f82ab8 670static char *
df57caba 671qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 672{
e315cd28 673 struct qla_hw_data *ha = vha->hw;
f0883ac6 674
df57caba 675 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 676 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 677 return str;
fca29703
AV		 678}
679
9ba56b95 680void
25ff6af1 681qla2x00_sp_free_dma(void *ptr)
fca29703 682{
25ff6af1
JC		 683 srb_t *sp = ptr;
684 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 685 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 686 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 687
9ba56b95
GM		 688 if (sp->flags & SRB_DMA_VALID) {
689 scsi_dma_unmap(cmd);
690 sp->flags &= ~SRB_DMA_VALID;
7c3df132 691 }
fca29703 692
9ba56b95
GM		 693 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
694 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
695 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
696 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
697 }
698
d5ff0eed
JC		 699 if (!ctx)
700 goto end;
701
9ba56b95
GM		 702 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
703 /* List assured to be having elements */
d5ff0eed 704 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 705 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
706 }
707
708 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 709 struct crc_context *ctx0 = ctx;
710
711 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 712 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
713 }
714
715 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 716 struct ct6_dsd *ctx1 = ctx;
fca29703 717
9ba56b95 718 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 719 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 720 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
721 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
722 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
723 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 724 }
725
d5ff0eed 726end:
6fcd98fd 727 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 728 CMD_SP(cmd) = NULL;
729 qla2x00_rel_sp(sp);
730 }
9ba56b95
GM		 731}
732
d7459527 733void
25ff6af1 734qla2x00_sp_compl(void *ptr, int res)
9ba56b95 735{
25ff6af1 736 srb_t *sp = ptr;
9ba56b95
GM		 737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738
739 cmd->result = res;
740
741 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 742 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 743 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
744 sp, GET_CMD_SP(sp));
745 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 746 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 747 return;
748 }
749 if (!atomic_dec_and_test(&sp->ref_count))
750 return;
751
f3caa990 752 sp->free(sp);
9ba56b95 753 cmd->scsi_done(cmd);
fca29703
AV		 754}
755
d7459527 756void
25ff6af1 757qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 758{
759 srb_t *sp = (srb_t *)ptr;
760 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
761 struct qla_hw_data *ha = sp->fcport->vha->hw;
762 void *ctx = GET_CMD_CTX_SP(sp);
763
764 if (sp->flags & SRB_DMA_VALID) {
765 scsi_dma_unmap(cmd);
766 sp->flags &= ~SRB_DMA_VALID;
767 }
768
769 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
770 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
771 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
772 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
773 }
774
d5ff0eed
JC		 775 if (!ctx)
776 goto end;
777
d7459527
MH		 778 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
779 /* List assured to be having elements */
d5ff0eed 780 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 781 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
782 }
783
784 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 785 struct crc_context *ctx0 = ctx;
786
787 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 788 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
789 }
790
791 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 792 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 793 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
794 ctx1->fcp_cmnd_dma);
795 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
796 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
797 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
798 mempool_free(ctx1, ha->ctx_mempool);
799 }
d5ff0eed 800end:
d7459527
MH		 801 CMD_SP(cmd) = NULL;
802 qla2xxx_rel_qpair_sp(sp->qpair, sp);
803}
804
805void
25ff6af1 806qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 807{
25ff6af1 808 srb_t *sp = ptr;
d7459527
MH		 809 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
810
811 cmd->result = res;
812
813 if (atomic_read(&sp->ref_count) == 0) {
814 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
815 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
816 sp, GET_CMD_SP(sp));
817 if (ql2xextended_error_logging & ql_dbg_io)
818 WARN_ON(atomic_read(&sp->ref_count) == 0);
819 return;
820 }
821 if (!atomic_dec_and_test(&sp->ref_count))
822 return;
823
f3caa990 824 sp->free(sp);
d7459527
MH		 825 cmd->scsi_done(cmd);
826}
827
8ae6d9c7
GM		 828/* If we are SP1 here, we need to still take and release the host_lock as SP1
829 * does not have the changes necessary to avoid taking host->host_lock.
830 */
1da177e4 831static int
f5e3e40b 832qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 833{
134ae078 834 scsi_qla_host_t *vha = shost_priv(host);
fca29703 835 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 836 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 837 struct qla_hw_data *ha = vha->hw;
838 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 839 srb_t *sp;
840 int rval;
5601236b
MH		 841 struct qla_qpair *qpair = NULL;
842 uint32_t tag;
843 uint16_t hwq;
fca29703 844
04dfaa53
MFO		 845 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
846 cmd->result = DID_NO_CONNECT << 16;
847 goto qc24_fail_command;
848 }
849
5601236b
MH		 850 if (ha->mqenable) {
851 if (shost_use_blk_mq(vha->host)) {
852 tag = blk_mq_unique_tag(cmd->request);
853 hwq = blk_mq_unique_tag_to_hwq(tag);
854 qpair = ha->queue_pair_map[hwq];
855 } else if (vha->vp_idx && vha->qpair) {
856 qpair = vha->qpair;
857 }
858
859 if (qpair)
860 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 861 }
862
85880801 863 if (ha->flags.eeh_busy) {
7c3df132 864 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 865 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 866 "PCI Channel IO permanent failure, exiting "
867 "cmd=%p.\n", cmd);
b9b12f73 868 cmd->result = DID_NO_CONNECT << 16;
7c3df132 869 } else {
5f28d2d7 870 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 871 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 872 cmd->result = DID_REQUEUE << 16;
7c3df132 873 }
14e660e6
SJ		 874 goto qc24_fail_command;
875 }
876
19a7b4ae
JSEC		 877 rval = fc_remote_port_chkready(rport);
878 if (rval) {
879 cmd->result = rval;
5f28d2d7 880 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 881 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
882 cmd, rval);
fca29703
AV		 883 goto qc24_fail_command;
884 }
885
bad75002
AE		 886 if (!vha->flags.difdix_supported &&
887 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 888 ql_dbg(ql_dbg_io, vha, 0x3004,
889 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
890 cmd);
bad75002
AE		 891 cmd->result = DID_NO_CONNECT << 16;
892 goto qc24_fail_command;
893 }
aa651be8
CD		 894
895 if (!fcport) {
896 cmd->result = DID_NO_CONNECT << 16;
897 goto qc24_fail_command;
898 }
899
fca29703
AV		 900 if (atomic_read(&fcport->state) != FCS_ONLINE) {
901 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 902 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 903 ql_dbg(ql_dbg_io, vha, 0x3005,
904 "Returning DNC, fcport_state=%d loop_state=%d.\n",
905 atomic_read(&fcport->state),
906 atomic_read(&base_vha->loop_state));
fca29703
AV		 907 cmd->result = DID_NO_CONNECT << 16;
908 goto qc24_fail_command;
909 }
7b594131 910 goto qc24_target_busy;
fca29703
AV		 911 }
912
e05fe292
CD		 913 /*
914 * Return target busy if we've received a non-zero retry_delay_timer
915 * in a FCP_RSP.
916 */
975f7d46
BP		 917 if (fcport->retry_delay_timestamp == 0) {
918 /* retry delay not set */
919 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 920 fcport->retry_delay_timestamp = 0;
921 else
922 goto qc24_target_busy;
923
b00ee7d7 924 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 925 if (!sp)
f5e3e40b 926 goto qc24_host_busy;
fca29703 927
9ba56b95
GM		 928 sp->u.scmd.cmd = cmd;
929 sp->type = SRB_SCSI_CMD;
930 atomic_set(&sp->ref_count, 1);
931 CMD_SP(cmd) = (void *)sp;
932 sp->free = qla2x00_sp_free_dma;
933 sp->done = qla2x00_sp_compl;
934
e315cd28 935 rval = ha->isp_ops->start_scsi(sp);
7c3df132 936 if (rval != QLA_SUCCESS) {
53016ed3 937 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 938 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 939 goto qc24_host_busy_free_sp;
7c3df132 940 }
fca29703 941
fca29703
AV		 942 return 0;
943
944qc24_host_busy_free_sp:
f3caa990 945 sp->free(sp);
fca29703 946
f5e3e40b 947qc24_host_busy:
fca29703
AV		 948 return SCSI_MLQUEUE_HOST_BUSY;
949
7b594131
MC		 950qc24_target_busy:
951 return SCSI_MLQUEUE_TARGET_BUSY;
952
fca29703 953qc24_fail_command:
f5e3e40b 954 cmd->scsi_done(cmd);
fca29703
AV		 955
956 return 0;
957}
958
d7459527
MH		 959/* For MQ supported I/O */
960int
961qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
962 struct qla_qpair *qpair)
963{
964 scsi_qla_host_t *vha = shost_priv(host);
965 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
966 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
967 struct qla_hw_data *ha = vha->hw;
968 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
969 srb_t *sp;
970 int rval;
971
972 rval = fc_remote_port_chkready(rport);
973 if (rval) {
974 cmd->result = rval;
975 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
976 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
977 cmd, rval);
978 goto qc24_fail_command;
979 }
980
981 if (!fcport) {
982 cmd->result = DID_NO_CONNECT << 16;
983 goto qc24_fail_command;
984 }
985
986 if (atomic_read(&fcport->state) != FCS_ONLINE) {
987 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
988 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
989 ql_dbg(ql_dbg_io, vha, 0x3077,
990 "Returning DNC, fcport_state=%d loop_state=%d.\n",
991 atomic_read(&fcport->state),
992 atomic_read(&base_vha->loop_state));
993 cmd->result = DID_NO_CONNECT << 16;
994 goto qc24_fail_command;
995 }
996 goto qc24_target_busy;
997 }
998
999 /*
1000 * Return target busy if we've received a non-zero retry_delay_timer
1001 * in a FCP_RSP.
1002 */
1003 if (fcport->retry_delay_timestamp == 0) {
1004 /* retry delay not set */
1005 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1006 fcport->retry_delay_timestamp = 0;
1007 else
1008 goto qc24_target_busy;
1009
1010 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1011 if (!sp)
1012 goto qc24_host_busy;
1013
1014 sp->u.scmd.cmd = cmd;
1015 sp->type = SRB_SCSI_CMD;
1016 atomic_set(&sp->ref_count, 1);
1017 CMD_SP(cmd) = (void *)sp;
1018 sp->free = qla2xxx_qpair_sp_free_dma;
1019 sp->done = qla2xxx_qpair_sp_compl;
1020 sp->qpair = qpair;
1021
1022 rval = ha->isp_ops->start_scsi_mq(sp);
1023 if (rval != QLA_SUCCESS) {
1024 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1025 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1026 if (rval == QLA_INTERFACE_ERROR)
1027 goto qc24_fail_command;
1028 goto qc24_host_busy_free_sp;
1029 }
1030
1031 return 0;
1032
1033qc24_host_busy_free_sp:
f3caa990 1034 sp->free(sp);
d7459527
MH		 1035
1036qc24_host_busy:
1037 return SCSI_MLQUEUE_HOST_BUSY;
1038
1039qc24_target_busy:
1040 return SCSI_MLQUEUE_TARGET_BUSY;
1041
1042qc24_fail_command:
1043 cmd->scsi_done(cmd);
1044
1045 return 0;
1046}
1047
1da177e4
LT		 1048/*
1049 * qla2x00_eh_wait_on_command
1050 * Waits for the command to be returned by the Firmware for some
1051 * max time.
1052 *
1053 * Input:
1da177e4 1054 * cmd = Scsi Command to wait on.
1da177e4
LT		 1055 *
1056 * Return:
1057 * Not Found : 0
1058 * Found : 1
1059 */
1060static int
e315cd28 1061qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1062{
fe74c71f 1063#define ABORT_POLLING_PERIOD 1000
478c3b03 1064#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1065 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1066 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1067 struct qla_hw_data *ha = vha->hw;
f4f051eb 1068 int ret = QLA_SUCCESS;
1da177e4 1069
85880801 1070 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1071 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1072 "Return:eh_wait.\n");
85880801
AV		 1073 return ret;
1074 }
1075
d970432c 1076 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1077 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1078 }
1079 if (CMD_SP(cmd))
1080 ret = QLA_FUNCTION_FAILED;
1da177e4 1081
f4f051eb 1082 return ret;
1da177e4
LT		 1083}
1084
1085/*
1086 * qla2x00_wait_for_hba_online
fa2a1ce5 1087 * Wait till the HBA is online after going through
1da177e4
LT		 1088 * <= MAX_RETRIES_OF_ISP_ABORT or
1089 * finally HBA is disabled ie marked offline
1090 *
1091 * Input:
1092 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1093 *
1094 * Note:
1da177e4
LT		 1095 * Does context switching-Release SPIN_LOCK
1096 * (if any) before calling this routine.
1097 *
1098 * Return:
1099 * Success (Adapter is online) : 0
1100 * Failed (Adapter is offline/disabled) : 1
1101 */
854165f4 1102int
e315cd28 1103qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1104{
fca29703
AV		 1105 int return_status;
1106 unsigned long wait_online;
e315cd28
AC		 1107 struct qla_hw_data *ha = vha->hw;
1108 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1109
fa2a1ce5 1110 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1111 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1112 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1113 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1114 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1115
1116 msleep(1000);
1117 }
e315cd28 1118 if (base_vha->flags.online)
fa2a1ce5 1119 return_status = QLA_SUCCESS;
1da177e4
LT		 1120 else
1121 return_status = QLA_FUNCTION_FAILED;
1122
1da177e4
LT		 1123 return (return_status);
1124}
1125
726b8548
QT		 1126static inline int test_fcport_count(scsi_qla_host_t *vha)
1127{
1128 struct qla_hw_data *ha = vha->hw;
1129 unsigned long flags;
1130 int res;
1131
1132 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1133 ql_dbg(ql_dbg_init, vha, 0x00ec,
1134 "tgt %p, fcport_count=%d\n",
1135 vha, vha->fcport_count);
726b8548
QT		 1136 res = (vha->fcport_count == 0);
1137 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1138
1139 return res;
1140}
1141
1142/*
1143 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1144 * it has dependency on UNLOADING flag to stop device discovery
1145 */
e0788f4a 1146void
726b8548
QT		 1147qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1148{
1149 qla2x00_mark_all_devices_lost(vha, 0);
1150
b85e0957 1151 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1152}
1153
86fbee86 1154/*
638a1a01
SC		 1155 * qla2x00_wait_for_hba_ready
1156 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1157 *
1158 * Input:
1159 * ha - pointer to host adapter structure
1160 *
1161 * Note:
1162 * Does context switching-Release SPIN_LOCK
1163 * (if any) before calling this routine.
1164 *
86fbee86 1165 */
638a1a01
SC		 1166static void
1167qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1168{
86fbee86 1169 struct qla_hw_data *ha = vha->hw;
783e0dc4 1170 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1171
1d483901
DC		 1172 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1173 ha->flags.mbox_busy) ||
1174 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1175 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1176 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1177 break;
86fbee86 1178 msleep(1000);
783e0dc4 1179 }
86fbee86
LC		 1180}
1181
2533cf67
LC		 1182int
1183qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1184{
1185 int return_status;
1186 unsigned long wait_reset;
1187 struct qla_hw_data *ha = vha->hw;
1188 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1189
1190 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1191 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1192 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1193 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1194 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1195
1196 msleep(1000);
1197
1198 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1199 ha->flags.chip_reset_done)
1200 break;
1201 }
1202 if (ha->flags.chip_reset_done)
1203 return_status = QLA_SUCCESS;
1204 else
1205 return_status = QLA_FUNCTION_FAILED;
1206
1207 return return_status;
1208}
1209
083a469d
GM		 1210static void
1211sp_get(struct srb *sp)
1212{
1213 atomic_inc(&sp->ref_count);
1214}
1215
a465537a
SC		 1216#define ISP_REG_DISCONNECT 0xffffffffU
1217/**************************************************************************
1218* qla2x00_isp_reg_stat
1219*
1220* Description:
1221* Read the host status register of ISP before aborting the command.
1222*
1223* Input:
1224* ha = pointer to host adapter structure.
1225*
1226*
1227* Returns:
1228* Either true or false.
1229*
1230* Note: Return true if there is register disconnect.
1231**************************************************************************/
1232static inline
1233uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1234{
1235 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1236 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1237
bf6061b1
SC		 1238 if (IS_P3P_TYPE(ha))
1239 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1240 else
1241 return ((RD_REG_DWORD(&reg->host_status)) ==
1242 ISP_REG_DISCONNECT);
a465537a
SC		 1243}
1244
1da177e4
LT		 1245/**************************************************************************
1246* qla2xxx_eh_abort
1247*
1248* Description:
1249* The abort function will abort the specified command.
1250*
1251* Input:
1252* cmd = Linux SCSI command packet to be aborted.
1253*
1254* Returns:
1255* Either SUCCESS or FAILED.
1256*
1257* Note:
2ea00202 1258* Only return FAILED if command not returned by firmware.
1da177e4 1259**************************************************************************/
e5f82ab8 1260static int
1da177e4
LT		 1261qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1262{
e315cd28 1263 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1264 srb_t *sp;
4e98d3b8 1265 int ret;
9cb78c16
HR		 1266 unsigned int id;
1267 uint64_t lun;
18e144d3 1268 unsigned long flags;
f934c9d0 1269 int rval, wait = 0;
e315cd28 1270 struct qla_hw_data *ha = vha->hw;
1da177e4 1271
a465537a
SC		 1272 if (qla2x00_isp_reg_stat(ha)) {
1273 ql_log(ql_log_info, vha, 0x8042,
1274 "PCI/Register disconnect, exiting.\n");
1275 return FAILED;
1276 }
f4f051eb 1277 if (!CMD_SP(cmd))
2ea00202 1278 return SUCCESS;
1da177e4 1279
4e98d3b8
AV		 1280 ret = fc_block_scsi_eh(cmd);
1281 if (ret != 0)
1282 return ret;
1283 ret = SUCCESS;
1284
f4f051eb
AV		 1285 id = cmd->device->id;
1286 lun = cmd->device->lun;
1da177e4 1287
e315cd28 1288 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1289 sp = (srb_t *) CMD_SP(cmd);
1290 if (!sp) {
1291 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1292 return SUCCESS;
1293 }
1da177e4 1294
7c3df132 1295 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1296 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1297 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1298
170babc3
MC		 1299 /* Get a reference to the sp and drop the lock.*/
1300 sp_get(sp);
083a469d 1301
e315cd28 1302 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1303 rval = ha->isp_ops->abort_command(sp);
1304 if (rval) {
96219424 1305 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1306 ret = SUCCESS;
96219424 1307 else
f934c9d0
CD		 1308 ret = FAILED;
1309
7c3df132 1310 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1311 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1312 } else {
7c3df132 1313 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1314 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1315 wait = 1;
1316 }
75942064
SK		 1317
1318 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1319 sp->done(sp, 0);
75942064 1320 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1321
bc91ade9
CD		 1322 /* Did the command return during mailbox execution? */
1323 if (ret == FAILED && !CMD_SP(cmd))
1324 ret = SUCCESS;
1325
f4f051eb 1326 /* Wait for the command to be returned. */
2ea00202 1327 if (wait) {
e315cd28 1328 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1329 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1330 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1331 ret = FAILED;
f4f051eb 1332 }
1da177e4 1333 }
1da177e4 1334
7c3df132 1335 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1336 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1337 vha->host_no, id, lun, wait, ret);
1da177e4 1338
f4f051eb
AV		 1339 return ret;
1340}
1da177e4 1341
4d78c973 1342int
e315cd28 1343qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1344 uint64_t l, enum nexus_wait_type type)
f4f051eb 1345{
17d98630 1346 int cnt, match, status;
18e144d3 1347 unsigned long flags;
e315cd28 1348 struct qla_hw_data *ha = vha->hw;
73208dfd 1349 struct req_que *req;
4d78c973 1350 srb_t *sp;
9ba56b95 1351 struct scsi_cmnd *cmd;
1da177e4 1352
523ec773 1353 status = QLA_SUCCESS;
17d98630 1354
e315cd28 1355 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1356 req = vha->req;
17d98630 1357 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1358 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1359 sp = req->outstanding_cmds[cnt];
1360 if (!sp)
523ec773 1361 continue;
9ba56b95 1362 if (sp->type != SRB_SCSI_CMD)
cf53b069 1363 continue;
25ff6af1 1364 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1365 continue;
1366 match = 0;
9ba56b95 1367 cmd = GET_CMD_SP(sp);
17d98630
AC		 1368 switch (type) {
1369 case WAIT_HOST:
1370 match = 1;
1371 break;
1372 case WAIT_TARGET:
9ba56b95 1373 match = cmd->device->id == t;
17d98630
AC		 1374 break;
1375 case WAIT_LUN:
9ba56b95
GM		 1376 match = (cmd->device->id == t &&
1377 cmd->device->lun == l);
17d98630 1378 break;
73208dfd 1379 }
17d98630
AC		 1380 if (!match)
1381 continue;
1382
1383 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1384 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1385 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1386 }
e315cd28 1387 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1388
1389 return status;
1da177e4
LT		 1390}
1391
523ec773
AV		 1392static char *reset_errors[] = {
1393 "HBA not online",
1394 "HBA not ready",
1395 "Task management failed",
1396 "Waiting for command completions",
1397};
1da177e4 1398
e5f82ab8 1399static int
523ec773 1400__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1401 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1402{
e315cd28 1403 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1404 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1405 int err;
1da177e4 1406
7c3df132 1407 if (!fcport) {
523ec773 1408 return FAILED;
7c3df132 1409 }
1da177e4 1410
4e98d3b8
AV		 1411 err = fc_block_scsi_eh(cmd);
1412 if (err != 0)
1413 return err;
1414
7c3df132 1415 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1416 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1417 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1418
523ec773 1419 err = 0;
7c3df132
SK		 1420 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1421 ql_log(ql_log_warn, vha, 0x800a,
1422 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1423 goto eh_reset_failed;
7c3df132 1424 }
523ec773 1425 err = 2;
2afa19a9 1426 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1427 != QLA_SUCCESS) {
1428 ql_log(ql_log_warn, vha, 0x800c,
1429 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1430 goto eh_reset_failed;
7c3df132 1431 }
523ec773 1432 err = 3;
e315cd28 1433 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1434 cmd->device->lun, type) != QLA_SUCCESS) {
1435 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1436 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1437 goto eh_reset_failed;
7c3df132 1438 }
523ec773 1439
7c3df132 1440 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1441 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1442 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1443
1444 return SUCCESS;
1445
4d78c973 1446eh_reset_failed:
7c3df132 1447 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1448 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1449 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1450 cmd);
523ec773
AV		 1451 return FAILED;
1452}
1da177e4 1453
523ec773
AV		 1454static int
1455qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1456{
e315cd28
AC		 1457 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1458 struct qla_hw_data *ha = vha->hw;
1da177e4 1459
a465537a
SC		 1460 if (qla2x00_isp_reg_stat(ha)) {
1461 ql_log(ql_log_info, vha, 0x803e,
1462 "PCI/Register disconnect, exiting.\n");
1463 return FAILED;
1464 }
1465
523ec773
AV		 1466 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1467 ha->isp_ops->lun_reset);
1da177e4
LT		 1468}
1469
1da177e4 1470static int
523ec773 1471qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1472{
e315cd28
AC		 1473 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1474 struct qla_hw_data *ha = vha->hw;
1da177e4 1475
a465537a
SC		 1476 if (qla2x00_isp_reg_stat(ha)) {
1477 ql_log(ql_log_info, vha, 0x803f,
1478 "PCI/Register disconnect, exiting.\n");
1479 return FAILED;
1480 }
1481
523ec773
AV		 1482 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1483 ha->isp_ops->target_reset);
1da177e4
LT		 1484}
1485
1da177e4
LT		 1486/**************************************************************************
1487* qla2xxx_eh_bus_reset
1488*
1489* Description:
1490* The bus reset function will reset the bus and abort any executing
1491* commands.
1492*
1493* Input:
1494* cmd = Linux SCSI command packet of the command that cause the
1495* bus reset.
1496*
1497* Returns:
1498* SUCCESS/FAILURE (defined as macro in scsi.h).
1499*
1500**************************************************************************/
e5f82ab8 1501static int
1da177e4
LT		 1502qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1503{
e315cd28 1504 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1505 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1506 int ret = FAILED;
9cb78c16
HR		 1507 unsigned int id;
1508 uint64_t lun;
a465537a
SC		 1509 struct qla_hw_data *ha = vha->hw;
1510
1511 if (qla2x00_isp_reg_stat(ha)) {
1512 ql_log(ql_log_info, vha, 0x8040,
1513 "PCI/Register disconnect, exiting.\n");
1514 return FAILED;
1515 }
f4f051eb 1516
f4f051eb
AV		 1517 id = cmd->device->id;
1518 lun = cmd->device->lun;
1da177e4 1519
7c3df132 1520 if (!fcport) {
f4f051eb 1521 return ret;
7c3df132 1522 }
1da177e4 1523
4e98d3b8
AV		 1524 ret = fc_block_scsi_eh(cmd);
1525 if (ret != 0)
1526 return ret;
1527 ret = FAILED;
1528
7c3df132 1529 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1530 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1531
e315cd28 1532 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1533 ql_log(ql_log_fatal, vha, 0x8013,
1534 "Wait for hba online failed board disabled.\n");
f4f051eb 1535 goto eh_bus_reset_done;
1da177e4
LT		 1536 }
1537
ad537689
SK		 1538 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1539 ret = SUCCESS;
1540
f4f051eb
AV		 1541 if (ret == FAILED)
1542 goto eh_bus_reset_done;
1da177e4 1543
9a41a62b 1544 /* Flush outstanding commands. */
4d78c973 1545 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1546 QLA_SUCCESS) {
1547 ql_log(ql_log_warn, vha, 0x8014,
1548 "Wait for pending commands failed.\n");
9a41a62b 1549 ret = FAILED;
7c3df132 1550 }
1da177e4 1551
f4f051eb 1552eh_bus_reset_done:
7c3df132 1553 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1554 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1555 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1556
f4f051eb 1557 return ret;
1da177e4
LT		 1558}
1559
1560/**************************************************************************
1561* qla2xxx_eh_host_reset
1562*
1563* Description:
1564* The reset function will reset the Adapter.
1565*
1566* Input:
1567* cmd = Linux SCSI command packet of the command that cause the
1568* adapter reset.
1569*
1570* Returns:
1571* Either SUCCESS or FAILED.
1572*
1573* Note:
1574**************************************************************************/
e5f82ab8 1575static int
1da177e4
LT		 1576qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1577{
e315cd28 1578 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1579 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1580 int ret = FAILED;
9cb78c16
HR		 1581 unsigned int id;
1582 uint64_t lun;
e315cd28 1583 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1584
a465537a
SC		 1585 if (qla2x00_isp_reg_stat(ha)) {
1586 ql_log(ql_log_info, vha, 0x8041,
1587 "PCI/Register disconnect, exiting.\n");
1588 schedule_work(&ha->board_disable);
1589 return SUCCESS;
1590 }
1591
f4f051eb
AV		 1592 id = cmd->device->id;
1593 lun = cmd->device->lun;
f4f051eb 1594
7c3df132 1595 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1596 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1597
63ee7072
CD		 1598 /*
1599 * No point in issuing another reset if one is active. Also do not
1600 * attempt a reset if we are updating flash.
1601 */
1602 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1603 goto eh_host_reset_lock;
1da177e4 1604
e315cd28
AC		 1605 if (vha != base_vha) {
1606 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1607 goto eh_host_reset_lock;
e315cd28 1608 } else {
7ec0effd 1609 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1610 if (!qla82xx_fcoe_ctx_reset(vha)) {
1611 /* Ctx reset success */
1612 ret = SUCCESS;
1613 goto eh_host_reset_lock;
1614 }
1615 /* fall thru if ctx reset failed */
1616 }
68ca949c
AC		 1617 if (ha->wq)
1618 flush_workqueue(ha->wq);
1619
e315cd28 1620 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1621 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1622 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1623 /* failed. schedule dpc to try */
1624 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1625
7c3df132
SK		 1626 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1627 ql_log(ql_log_warn, vha, 0x802a,
1628 "wait for hba online failed.\n");
e315cd28 1629 goto eh_host_reset_lock;
7c3df132 1630 }
e315cd28
AC		 1631 }
1632 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1633 }
1da177e4 1634
e315cd28 1635 /* Waiting for command to be returned to OS.*/
4d78c973 1636 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1637 QLA_SUCCESS)
f4f051eb 1638 ret = SUCCESS;
1da177e4 1639
f4f051eb 1640eh_host_reset_lock:
cfb0919c 1641 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1642 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1643 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1644
f4f051eb
AV		 1645 return ret;
1646}
1da177e4
LT		 1647
1648/*
1649* qla2x00_loop_reset
1650* Issue loop reset.
1651*
1652* Input:
1653* ha = adapter block pointer.
1654*
1655* Returns:
1656* 0 = success
1657*/
a4722cf2 1658int
e315cd28 1659qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1660{
0c8c39af 1661 int ret;
bdf79621 1662 struct fc_port *fcport;
e315cd28 1663 struct qla_hw_data *ha = vha->hw;
1da177e4 1664
5854771e
AB		 1665 if (IS_QLAFX00(ha)) {
1666 return qlafx00_loop_reset(vha);
1667 }
1668
f4c496c1 1669 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1670 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1671 if (fcport->port_type != FCT_TARGET)
1672 continue;
1673
1674 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1675 if (ret != QLA_SUCCESS) {
7c3df132 1676 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1677 "Bus Reset failed: Reset=%d "
7c3df132 1678 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1679 }
1680 }
1681 }
1682
8ae6d9c7 1683
6246b8a1 1684 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1685 atomic_set(&vha->loop_state, LOOP_DOWN);
1686 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1687 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1688 ret = qla2x00_full_login_lip(vha);
0c8c39af 1689 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1690 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1691 "full_login_lip=%d.\n", ret);
749af3d5 1692 }
0c8c39af
AV		 1693 }
1694
0d6e61bc 1695 if (ha->flags.enable_lip_reset) {
e315cd28 1696 ret = qla2x00_lip_reset(vha);
ad537689 1697 if (ret != QLA_SUCCESS)
7c3df132
SK		 1698 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1699 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1700 }
1701
1da177e4 1702 /* Issue marker command only when we are going to start the I/O */
e315cd28 1703 vha->marker_needed = 1;
1da177e4 1704
0c8c39af 1705 return QLA_SUCCESS;
1da177e4
LT		 1706}
1707
df4bf0bb 1708void
e315cd28 1709qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1710{
4cd3b6eb 1711 int que, cnt, status;
df4bf0bb
AV		 1712 unsigned long flags;
1713 srb_t *sp;
e315cd28 1714 struct qla_hw_data *ha = vha->hw;
73208dfd 1715 struct req_que *req;
c5419e26
QT		 1716 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1717 struct qla_tgt_cmd *cmd;
1718 uint8_t trace = 0;
c0cb4496 1719
79c67fb6
BK		 1720 if (!ha->req_q_map)
1721 return;
df4bf0bb 1722 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1723 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1724 req = ha->req_q_map[que];
73208dfd
AC		 1725 if (!req)
1726 continue;
8d93f550
CD		 1727 if (!req->outstanding_cmds)
1728 continue;
1729 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1730 sp = req->outstanding_cmds[cnt];
e612d465 1731 if (sp) {
c5419e26
QT		 1732 req->outstanding_cmds[cnt] = NULL;
1733 if (sp->cmd_type == TYPE_SRB) {
6fcd98fd 1734 if (sp->type == SRB_NVME_CMD ||
1735 sp->type == SRB_NVME_LS) {
e84067d7
DG		 1736 sp_get(sp);
1737 spin_unlock_irqrestore(
1738 &ha->hardware_lock, flags);
1739 qla_nvme_abort(ha, sp);
1740 spin_lock_irqsave(
1741 &ha->hardware_lock, flags);
1742 } else if (GET_CMD_SP(sp) &&
c5419e26 1743 !ha->flags.eeh_busy &&
d61cca60
SC		 1744 (!test_bit(ABORT_ISP_ACTIVE,
1745 &vha->dpc_flags)) &&
c5419e26
QT		 1746 (sp->type == SRB_SCSI_CMD)) {
1747 /*
e84067d7
DG		 1748 * Don't abort commands in
1749 * adapter during EEH
1750 * recovery as it's not
1751 * accessible/responding.
1752 *
c5419e26
QT		 1753 * Get a reference to the sp
1754 * and drop the lock. The
1755 * reference ensures this
1756 * sp->done() call and not the
1757 * call in qla2xxx_eh_abort()
1758 * ends the SCSI command (with
1759 * result 'res').
1760 */
1761 sp_get(sp);
1762 spin_unlock_irqrestore(
1763 &ha->hardware_lock, flags);
1764 status = qla2xxx_eh_abort(
1765 GET_CMD_SP(sp));
1766 spin_lock_irqsave(
1767 &ha->hardware_lock, flags);
1768 /*
1769 * Get rid of extra reference
1770 * if immediate exit from
1771 * ql2xxx_eh_abort
1772 */
1773 if (status == FAILED &&
1774 (qla2x00_isp_reg_stat(ha)))
1775 atomic_dec(
1776 &sp->ref_count);
1777 }
1778 sp->done(sp, res);
1779 } else {
1780 if (!vha->hw->tgt.tgt_ops || !tgt ||
1781 qla_ini_mode_enabled(vha)) {
1782 if (!trace)
1783 ql_dbg(ql_dbg_tgt_mgt,
1784 vha, 0xf003,
1785 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1786 vha->dpc_flags);
1787 continue;
1788 }
1789 cmd = (struct qla_tgt_cmd *)sp;
1790 qlt_abort_cmd_on_host_reset(cmd->vha,
1791 cmd);
c733ab35 1792 }
73208dfd 1793 }
df4bf0bb
AV		 1794 }
1795 }
1796 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1797}
1798
f4f051eb
AV		 1799static int
1800qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1801{
bdf79621 1802 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1803
19a7b4ae 1804 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1805 return -ENXIO;
bdf79621 1806
19a7b4ae 1807 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1808
f4f051eb
AV		 1809 return 0;
1810}
1da177e4 1811
f4f051eb
AV		 1812static int
1813qla2xxx_slave_configure(struct scsi_device *sdev)
1814{
e315cd28 1815 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1816 struct req_que *req = vha->req;
8482e118 1817
9e522cd8
AE		 1818 if (IS_T10_PI_CAPABLE(vha->hw))
1819 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1820
db5ed4df 1821 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1822 return 0;
1823}
1da177e4 1824
f4f051eb
AV		 1825static void
1826qla2xxx_slave_destroy(struct scsi_device *sdev)
1827{
1828 sdev->hostdata = NULL;
1da177e4
LT		 1829}
1830
1831/**
1832 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1833 * @ha: HA context
1834 *
1835 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1836 * supported addressing method.
1837 */
1838static void
53303c42 1839qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1840{
7524f9b9 1841 /* Assume a 32bit DMA mask. */
1da177e4 1842 ha->flags.enable_64bit_addressing = 0;
1da177e4 1843
6a35528a 1844 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1845 /* Any upper-dword bits set? */
1846 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1847 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1848 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1849 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1850 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1851 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1852 return;
1da177e4 1853 }
1da177e4 1854 }
7524f9b9 1855
284901a9
YH		 1856 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1857 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1858}
1859
fd34f556 1860static void
e315cd28 1861qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1862{
1863 unsigned long flags = 0;
1864 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1865
1866 spin_lock_irqsave(&ha->hardware_lock, flags);
1867 ha->interrupts_on = 1;
1868 /* enable risc and host interrupts */
1869 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1870 RD_REG_WORD(&reg->ictrl);
1871 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1872
1873}
1874
1875static void
e315cd28 1876qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1877{
1878 unsigned long flags = 0;
1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1880
1881 spin_lock_irqsave(&ha->hardware_lock, flags);
1882 ha->interrupts_on = 0;
1883 /* disable risc and host interrupts */
1884 WRT_REG_WORD(&reg->ictrl, 0);
1885 RD_REG_WORD(&reg->ictrl);
1886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1887}
1888
1889static void
e315cd28 1890qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1891{
1892 unsigned long flags = 0;
1893 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1894
1895 spin_lock_irqsave(&ha->hardware_lock, flags);
1896 ha->interrupts_on = 1;
1897 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1898 RD_REG_DWORD(&reg->ictrl);
1899 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1900}
1901
1902static void
e315cd28 1903qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1904{
1905 unsigned long flags = 0;
1906 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1907
124f85e6
AV		 1908 if (IS_NOPOLLING_TYPE(ha))
1909 return;
fd34f556
AV		 1910 spin_lock_irqsave(&ha->hardware_lock, flags);
1911 ha->interrupts_on = 0;
1912 WRT_REG_DWORD(&reg->ictrl, 0);
1913 RD_REG_DWORD(&reg->ictrl);
1914 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1915}
1916
706f457d
GM		 1917static int
1918qla2x00_iospace_config(struct qla_hw_data *ha)
1919{
1920 resource_size_t pio;
1921 uint16_t msix;
706f457d 1922
706f457d
GM		 1923 if (pci_request_selected_regions(ha->pdev, ha->bars,
1924 QLA2XXX_DRIVER_NAME)) {
1925 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1926 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1927 pci_name(ha->pdev));
1928 goto iospace_error_exit;
1929 }
1930 if (!(ha->bars & 1))
1931 goto skip_pio;
1932
1933 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1934 pio = pci_resource_start(ha->pdev, 0);
1935 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1936 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1937 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1938 "Invalid pci I/O region size (%s).\n",
1939 pci_name(ha->pdev));
1940 pio = 0;
1941 }
1942 } else {
1943 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1944 "Region #0 no a PIO resource (%s).\n",
1945 pci_name(ha->pdev));
1946 pio = 0;
1947 }
1948 ha->pio_address = pio;
1949 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1950 "PIO address=%llu.\n",
1951 (unsigned long long)ha->pio_address);
1952
1953skip_pio:
1954 /* Use MMIO operations for all accesses. */
1955 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1956 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1957 "Region #1 not an MMIO resource (%s), aborting.\n",
1958 pci_name(ha->pdev));
1959 goto iospace_error_exit;
1960 }
1961 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1962 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1963 "Invalid PCI mem region size (%s), aborting.\n",
1964 pci_name(ha->pdev));
1965 goto iospace_error_exit;
1966 }
1967
1968 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1969 if (!ha->iobase) {
1970 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1971 "Cannot remap MMIO (%s), aborting.\n",
1972 pci_name(ha->pdev));
1973 goto iospace_error_exit;
1974 }
1975
1976 /* Determine queue resources */
1977 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1978 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 1979 if (!ql2xmqsupport || !ql2xnvmeenable ||
1980 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1981 goto mqiobase_exit;
1982
1983 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1984 pci_resource_len(ha->pdev, 3));
1985 if (ha->mqiobase) {
1986 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1987 "MQIO Base=%p.\n", ha->mqiobase);
1988 /* Read MSIX vector size of the board */
1989 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1990 ha->msix_count = msix + 1;
706f457d 1991 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1992 /* MB interrupt uses 1 vector */
1993 ha->max_req_queues = ha->msix_count - 1;
1994 ha->max_rsp_queues = ha->max_req_queues;
1995 /* Queue pairs is the max value minus the base queue pair */
1996 ha->max_qpairs = ha->max_rsp_queues - 1;
1997 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1998 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1999
706f457d 2000 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2001 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2002 } else
2003 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2004 "BAR 3 not enabled.\n");
2005
2006mqiobase_exit:
706f457d 2007 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2008 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2009 return (0);
2010
2011iospace_error_exit:
2012 return (-ENOMEM);
2013}
2014
2015
6246b8a1
GM		 2016static int
2017qla83xx_iospace_config(struct qla_hw_data *ha)
2018{
2019 uint16_t msix;
6246b8a1
GM		 2020
2021 if (pci_request_selected_regions(ha->pdev, ha->bars,
2022 QLA2XXX_DRIVER_NAME)) {
2023 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2024 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2025 pci_name(ha->pdev));
2026
2027 goto iospace_error_exit;
2028 }
2029
2030 /* Use MMIO operations for all accesses. */
2031 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2032 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2033 "Invalid pci I/O region size (%s).\n",
2034 pci_name(ha->pdev));
2035 goto iospace_error_exit;
2036 }
2037 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2038 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2039 "Invalid PCI mem region size (%s), aborting\n",
2040 pci_name(ha->pdev));
2041 goto iospace_error_exit;
2042 }
2043
2044 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2045 if (!ha->iobase) {
2046 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2047 "Cannot remap MMIO (%s), aborting.\n",
2048 pci_name(ha->pdev));
2049 goto iospace_error_exit;
2050 }
2051
2052 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2053 /* 83XX 26XX always use MQ type access for queues
2054 * - mbar 2, a.k.a region 4 */
2055 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2056 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2057 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2058 pci_resource_len(ha->pdev, 4));
2059
2060 if (!ha->mqiobase) {
2061 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2062 "BAR2/region4 not enabled\n");
2063 goto mqiobase_exit;
2064 }
2065
2066 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2067 pci_resource_len(ha->pdev, 2));
2068 if (ha->msixbase) {
2069 /* Read MSIX vector size of the board */
2070 pci_read_config_word(ha->pdev,
2071 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2072 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2073 /*
2074 * By default, driver uses at least two msix vectors
2075 * (default & rspq)
2076 */
c38d1baf 2077 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2078 /* MB interrupt uses 1 vector */
2079 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2080
2081 /* ATIOQ needs 1 vector. That's 1 less QPair */
2082 if (QLA_TGT_MODE_ENABLED())
2083 ha->max_req_queues--;
2084
d0d2c68b
MH		 2085 ha->max_rsp_queues = ha->max_req_queues;
2086
d7459527
MH		 2087 /* Queue pairs is the max value minus
2088 * the base queue pair */
2089 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2090 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2091 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2092 }
2093 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2094 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2095 } else
2096 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2097 "BAR 1 not enabled.\n");
2098
2099mqiobase_exit:
6246b8a1 2100 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2101 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2102 return 0;
2103
2104iospace_error_exit:
2105 return -ENOMEM;
2106}
2107
fd34f556
AV		 2108static struct isp_operations qla2100_isp_ops = {
2109 .pci_config = qla2100_pci_config,
2110 .reset_chip = qla2x00_reset_chip,
2111 .chip_diag = qla2x00_chip_diag,
2112 .config_rings = qla2x00_config_rings,
2113 .reset_adapter = qla2x00_reset_adapter,
2114 .nvram_config = qla2x00_nvram_config,
2115 .update_fw_options = qla2x00_update_fw_options,
2116 .load_risc = qla2x00_load_risc,
2117 .pci_info_str = qla2x00_pci_info_str,
2118 .fw_version_str = qla2x00_fw_version_str,
2119 .intr_handler = qla2100_intr_handler,
2120 .enable_intrs = qla2x00_enable_intrs,
2121 .disable_intrs = qla2x00_disable_intrs,
2122 .abort_command = qla2x00_abort_command,
523ec773
AV		 2123 .target_reset = qla2x00_abort_target,
2124 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2125 .fabric_login = qla2x00_login_fabric,
2126 .fabric_logout = qla2x00_fabric_logout,
2127 .calc_req_entries = qla2x00_calc_iocbs_32,
2128 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2129 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2130 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2131 .read_nvram = qla2x00_read_nvram_data,
2132 .write_nvram = qla2x00_write_nvram_data,
2133 .fw_dump = qla2100_fw_dump,
2134 .beacon_on = NULL,
2135 .beacon_off = NULL,
2136 .beacon_blink = NULL,
2137 .read_optrom = qla2x00_read_optrom_data,
2138 .write_optrom = qla2x00_write_optrom_data,
2139 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2140 .start_scsi = qla2x00_start_scsi,
d7459527 2141 .start_scsi_mq = NULL,
a9083016 2142 .abort_isp = qla2x00_abort_isp,
706f457d 2143 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2144 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2145};
2146
2147static struct isp_operations qla2300_isp_ops = {
2148 .pci_config = qla2300_pci_config,
2149 .reset_chip = qla2x00_reset_chip,
2150 .chip_diag = qla2x00_chip_diag,
2151 .config_rings = qla2x00_config_rings,
2152 .reset_adapter = qla2x00_reset_adapter,
2153 .nvram_config = qla2x00_nvram_config,
2154 .update_fw_options = qla2x00_update_fw_options,
2155 .load_risc = qla2x00_load_risc,
2156 .pci_info_str = qla2x00_pci_info_str,
2157 .fw_version_str = qla2x00_fw_version_str,
2158 .intr_handler = qla2300_intr_handler,
2159 .enable_intrs = qla2x00_enable_intrs,
2160 .disable_intrs = qla2x00_disable_intrs,
2161 .abort_command = qla2x00_abort_command,
523ec773
AV		 2162 .target_reset = qla2x00_abort_target,
2163 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2164 .fabric_login = qla2x00_login_fabric,
2165 .fabric_logout = qla2x00_fabric_logout,
2166 .calc_req_entries = qla2x00_calc_iocbs_32,
2167 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2168 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2169 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2170 .read_nvram = qla2x00_read_nvram_data,
2171 .write_nvram = qla2x00_write_nvram_data,
2172 .fw_dump = qla2300_fw_dump,
2173 .beacon_on = qla2x00_beacon_on,
2174 .beacon_off = qla2x00_beacon_off,
2175 .beacon_blink = qla2x00_beacon_blink,
2176 .read_optrom = qla2x00_read_optrom_data,
2177 .write_optrom = qla2x00_write_optrom_data,
2178 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2179 .start_scsi = qla2x00_start_scsi,
d7459527 2180 .start_scsi_mq = NULL,
a9083016 2181 .abort_isp = qla2x00_abort_isp,
7ec0effd 2182 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2183 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2184};
2185
2186static struct isp_operations qla24xx_isp_ops = {
2187 .pci_config = qla24xx_pci_config,
2188 .reset_chip = qla24xx_reset_chip,
2189 .chip_diag = qla24xx_chip_diag,
2190 .config_rings = qla24xx_config_rings,
2191 .reset_adapter = qla24xx_reset_adapter,
2192 .nvram_config = qla24xx_nvram_config,
2193 .update_fw_options = qla24xx_update_fw_options,
2194 .load_risc = qla24xx_load_risc,
2195 .pci_info_str = qla24xx_pci_info_str,
2196 .fw_version_str = qla24xx_fw_version_str,
2197 .intr_handler = qla24xx_intr_handler,
2198 .enable_intrs = qla24xx_enable_intrs,
2199 .disable_intrs = qla24xx_disable_intrs,
2200 .abort_command = qla24xx_abort_command,
523ec773
AV		 2201 .target_reset = qla24xx_abort_target,
2202 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2203 .fabric_login = qla24xx_login_fabric,
2204 .fabric_logout = qla24xx_fabric_logout,
2205 .calc_req_entries = NULL,
2206 .build_iocbs = NULL,
2207 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2208 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2209 .read_nvram = qla24xx_read_nvram_data,
2210 .write_nvram = qla24xx_write_nvram_data,
2211 .fw_dump = qla24xx_fw_dump,
2212 .beacon_on = qla24xx_beacon_on,
2213 .beacon_off = qla24xx_beacon_off,
2214 .beacon_blink = qla24xx_beacon_blink,
2215 .read_optrom = qla24xx_read_optrom_data,
2216 .write_optrom = qla24xx_write_optrom_data,
2217 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2218 .start_scsi = qla24xx_start_scsi,
d7459527 2219 .start_scsi_mq = NULL,
a9083016 2220 .abort_isp = qla2x00_abort_isp,
7ec0effd 2221 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2222 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2223};
2224
c3a2f0df
AV		 2225static struct isp_operations qla25xx_isp_ops = {
2226 .pci_config = qla25xx_pci_config,
2227 .reset_chip = qla24xx_reset_chip,
2228 .chip_diag = qla24xx_chip_diag,
2229 .config_rings = qla24xx_config_rings,
2230 .reset_adapter = qla24xx_reset_adapter,
2231 .nvram_config = qla24xx_nvram_config,
2232 .update_fw_options = qla24xx_update_fw_options,
2233 .load_risc = qla24xx_load_risc,
2234 .pci_info_str = qla24xx_pci_info_str,
2235 .fw_version_str = qla24xx_fw_version_str,
2236 .intr_handler = qla24xx_intr_handler,
2237 .enable_intrs = qla24xx_enable_intrs,
2238 .disable_intrs = qla24xx_disable_intrs,
2239 .abort_command = qla24xx_abort_command,
523ec773
AV		 2240 .target_reset = qla24xx_abort_target,
2241 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2242 .fabric_login = qla24xx_login_fabric,
2243 .fabric_logout = qla24xx_fabric_logout,
2244 .calc_req_entries = NULL,
2245 .build_iocbs = NULL,
2246 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2247 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2248 .read_nvram = qla25xx_read_nvram_data,
2249 .write_nvram = qla25xx_write_nvram_data,
2250 .fw_dump = qla25xx_fw_dump,
2251 .beacon_on = qla24xx_beacon_on,
2252 .beacon_off = qla24xx_beacon_off,
2253 .beacon_blink = qla24xx_beacon_blink,
338c9161 2254 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2255 .write_optrom = qla24xx_write_optrom_data,
2256 .get_flash_version = qla24xx_get_flash_version,
bad75002 2257 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2258 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2259 .abort_isp = qla2x00_abort_isp,
7ec0effd 2260 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2261 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2262};
2263
3a03eb79
AV		 2264static struct isp_operations qla81xx_isp_ops = {
2265 .pci_config = qla25xx_pci_config,
2266 .reset_chip = qla24xx_reset_chip,
2267 .chip_diag = qla24xx_chip_diag,
2268 .config_rings = qla24xx_config_rings,
2269 .reset_adapter = qla24xx_reset_adapter,
2270 .nvram_config = qla81xx_nvram_config,
2271 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2272 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2273 .pci_info_str = qla24xx_pci_info_str,
2274 .fw_version_str = qla24xx_fw_version_str,
2275 .intr_handler = qla24xx_intr_handler,
2276 .enable_intrs = qla24xx_enable_intrs,
2277 .disable_intrs = qla24xx_disable_intrs,
2278 .abort_command = qla24xx_abort_command,
2279 .target_reset = qla24xx_abort_target,
2280 .lun_reset = qla24xx_lun_reset,
2281 .fabric_login = qla24xx_login_fabric,
2282 .fabric_logout = qla24xx_fabric_logout,
2283 .calc_req_entries = NULL,
2284 .build_iocbs = NULL,
2285 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2286 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2287 .read_nvram = NULL,
2288 .write_nvram = NULL,
3a03eb79
AV		 2289 .fw_dump = qla81xx_fw_dump,
2290 .beacon_on = qla24xx_beacon_on,
2291 .beacon_off = qla24xx_beacon_off,
6246b8a1 2292 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2293 .read_optrom = qla25xx_read_optrom_data,
2294 .write_optrom = qla24xx_write_optrom_data,
2295 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2296 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2297 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2298 .abort_isp = qla2x00_abort_isp,
7ec0effd 2299 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2300 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2301};
2302
2303static struct isp_operations qla82xx_isp_ops = {
2304 .pci_config = qla82xx_pci_config,
2305 .reset_chip = qla82xx_reset_chip,
2306 .chip_diag = qla24xx_chip_diag,
2307 .config_rings = qla82xx_config_rings,
2308 .reset_adapter = qla24xx_reset_adapter,
2309 .nvram_config = qla81xx_nvram_config,
2310 .update_fw_options = qla24xx_update_fw_options,
2311 .load_risc = qla82xx_load_risc,
9d55ca66 2312 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2313 .fw_version_str = qla24xx_fw_version_str,
2314 .intr_handler = qla82xx_intr_handler,
2315 .enable_intrs = qla82xx_enable_intrs,
2316 .disable_intrs = qla82xx_disable_intrs,
2317 .abort_command = qla24xx_abort_command,
2318 .target_reset = qla24xx_abort_target,
2319 .lun_reset = qla24xx_lun_reset,
2320 .fabric_login = qla24xx_login_fabric,
2321 .fabric_logout = qla24xx_fabric_logout,
2322 .calc_req_entries = NULL,
2323 .build_iocbs = NULL,
2324 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2325 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2326 .read_nvram = qla24xx_read_nvram_data,
2327 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2328 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2329 .beacon_on = qla82xx_beacon_on,
2330 .beacon_off = qla82xx_beacon_off,
2331 .beacon_blink = NULL,
a9083016
GM		 2332 .read_optrom = qla82xx_read_optrom_data,
2333 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2334 .get_flash_version = qla82xx_get_flash_version,
a9083016 2335 .start_scsi = qla82xx_start_scsi,
d7459527 2336 .start_scsi_mq = NULL,
a9083016 2337 .abort_isp = qla82xx_abort_isp,
706f457d 2338 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2339 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2340};
2341
7ec0effd
AD		 2342static struct isp_operations qla8044_isp_ops = {
2343 .pci_config = qla82xx_pci_config,
2344 .reset_chip = qla82xx_reset_chip,
2345 .chip_diag = qla24xx_chip_diag,
2346 .config_rings = qla82xx_config_rings,
2347 .reset_adapter = qla24xx_reset_adapter,
2348 .nvram_config = qla81xx_nvram_config,
2349 .update_fw_options = qla24xx_update_fw_options,
2350 .load_risc = qla82xx_load_risc,
2351 .pci_info_str = qla24xx_pci_info_str,
2352 .fw_version_str = qla24xx_fw_version_str,
2353 .intr_handler = qla8044_intr_handler,
2354 .enable_intrs = qla82xx_enable_intrs,
2355 .disable_intrs = qla82xx_disable_intrs,
2356 .abort_command = qla24xx_abort_command,
2357 .target_reset = qla24xx_abort_target,
2358 .lun_reset = qla24xx_lun_reset,
2359 .fabric_login = qla24xx_login_fabric,
2360 .fabric_logout = qla24xx_fabric_logout,
2361 .calc_req_entries = NULL,
2362 .build_iocbs = NULL,
2363 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2364 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2365 .read_nvram = NULL,
2366 .write_nvram = NULL,
a1b23c5a 2367 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2368 .beacon_on = qla82xx_beacon_on,
2369 .beacon_off = qla82xx_beacon_off,
2370 .beacon_blink = NULL,
888e639d 2371 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2372 .write_optrom = qla8044_write_optrom_data,
2373 .get_flash_version = qla82xx_get_flash_version,
2374 .start_scsi = qla82xx_start_scsi,
d7459527 2375 .start_scsi_mq = NULL,
7ec0effd
AD		 2376 .abort_isp = qla8044_abort_isp,
2377 .iospace_config = qla82xx_iospace_config,
2378 .initialize_adapter = qla2x00_initialize_adapter,
2379};
2380
6246b8a1
GM		 2381static struct isp_operations qla83xx_isp_ops = {
2382 .pci_config = qla25xx_pci_config,
2383 .reset_chip = qla24xx_reset_chip,
2384 .chip_diag = qla24xx_chip_diag,
2385 .config_rings = qla24xx_config_rings,
2386 .reset_adapter = qla24xx_reset_adapter,
2387 .nvram_config = qla81xx_nvram_config,
2388 .update_fw_options = qla81xx_update_fw_options,
2389 .load_risc = qla81xx_load_risc,
2390 .pci_info_str = qla24xx_pci_info_str,
2391 .fw_version_str = qla24xx_fw_version_str,
2392 .intr_handler = qla24xx_intr_handler,
2393 .enable_intrs = qla24xx_enable_intrs,
2394 .disable_intrs = qla24xx_disable_intrs,
2395 .abort_command = qla24xx_abort_command,
2396 .target_reset = qla24xx_abort_target,
2397 .lun_reset = qla24xx_lun_reset,
2398 .fabric_login = qla24xx_login_fabric,
2399 .fabric_logout = qla24xx_fabric_logout,
2400 .calc_req_entries = NULL,
2401 .build_iocbs = NULL,
2402 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2403 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2404 .read_nvram = NULL,
2405 .write_nvram = NULL,
2406 .fw_dump = qla83xx_fw_dump,
2407 .beacon_on = qla24xx_beacon_on,
2408 .beacon_off = qla24xx_beacon_off,
2409 .beacon_blink = qla83xx_beacon_blink,
2410 .read_optrom = qla25xx_read_optrom_data,
2411 .write_optrom = qla24xx_write_optrom_data,
2412 .get_flash_version = qla24xx_get_flash_version,
2413 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2414 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2415 .abort_isp = qla2x00_abort_isp,
2416 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2417 .initialize_adapter = qla2x00_initialize_adapter,
2418};
2419
2420static struct isp_operations qlafx00_isp_ops = {
2421 .pci_config = qlafx00_pci_config,
2422 .reset_chip = qlafx00_soft_reset,
2423 .chip_diag = qlafx00_chip_diag,
2424 .config_rings = qlafx00_config_rings,
2425 .reset_adapter = qlafx00_soft_reset,
2426 .nvram_config = NULL,
2427 .update_fw_options = NULL,
2428 .load_risc = NULL,
2429 .pci_info_str = qlafx00_pci_info_str,
2430 .fw_version_str = qlafx00_fw_version_str,
2431 .intr_handler = qlafx00_intr_handler,
2432 .enable_intrs = qlafx00_enable_intrs,
2433 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2434 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2435 .target_reset = qlafx00_abort_target,
2436 .lun_reset = qlafx00_lun_reset,
2437 .fabric_login = NULL,
2438 .fabric_logout = NULL,
2439 .calc_req_entries = NULL,
2440 .build_iocbs = NULL,
2441 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2442 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2443 .read_nvram = qla24xx_read_nvram_data,
2444 .write_nvram = qla24xx_write_nvram_data,
2445 .fw_dump = NULL,
2446 .beacon_on = qla24xx_beacon_on,
2447 .beacon_off = qla24xx_beacon_off,
2448 .beacon_blink = NULL,
2449 .read_optrom = qla24xx_read_optrom_data,
2450 .write_optrom = qla24xx_write_optrom_data,
2451 .get_flash_version = qla24xx_get_flash_version,
2452 .start_scsi = qlafx00_start_scsi,
d7459527 2453 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2454 .abort_isp = qlafx00_abort_isp,
2455 .iospace_config = qlafx00_iospace_config,
2456 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2457};
2458
f73cb695
CD		 2459static struct isp_operations qla27xx_isp_ops = {
2460 .pci_config = qla25xx_pci_config,
2461 .reset_chip = qla24xx_reset_chip,
2462 .chip_diag = qla24xx_chip_diag,
2463 .config_rings = qla24xx_config_rings,
2464 .reset_adapter = qla24xx_reset_adapter,
2465 .nvram_config = qla81xx_nvram_config,
2466 .update_fw_options = qla81xx_update_fw_options,
2467 .load_risc = qla81xx_load_risc,
2468 .pci_info_str = qla24xx_pci_info_str,
2469 .fw_version_str = qla24xx_fw_version_str,
2470 .intr_handler = qla24xx_intr_handler,
2471 .enable_intrs = qla24xx_enable_intrs,
2472 .disable_intrs = qla24xx_disable_intrs,
2473 .abort_command = qla24xx_abort_command,
2474 .target_reset = qla24xx_abort_target,
2475 .lun_reset = qla24xx_lun_reset,
2476 .fabric_login = qla24xx_login_fabric,
2477 .fabric_logout = qla24xx_fabric_logout,
2478 .calc_req_entries = NULL,
2479 .build_iocbs = NULL,
2480 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2481 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2482 .read_nvram = NULL,
2483 .write_nvram = NULL,
2484 .fw_dump = qla27xx_fwdump,
2485 .beacon_on = qla24xx_beacon_on,
2486 .beacon_off = qla24xx_beacon_off,
2487 .beacon_blink = qla83xx_beacon_blink,
2488 .read_optrom = qla25xx_read_optrom_data,
2489 .write_optrom = qla24xx_write_optrom_data,
2490 .get_flash_version = qla24xx_get_flash_version,
2491 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2492 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2493 .abort_isp = qla2x00_abort_isp,
2494 .iospace_config = qla83xx_iospace_config,
2495 .initialize_adapter = qla2x00_initialize_adapter,
2496};
2497
ea5b6382 2498static inline void
e315cd28 2499qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2500{
2501 ha->device_type = DT_EXTENDED_IDS;
2502 switch (ha->pdev->device) {
2503 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2504 ha->isp_type |= DT_ISP2100;
ea5b6382 2505 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2506 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2507 break;
2508 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2509 ha->isp_type |= DT_ISP2200;
ea5b6382 2510 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2511 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2512 break;
2513 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2514 ha->isp_type |= DT_ISP2300;
4a59f71d 2515 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2516 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2517 break;
2518 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2519 ha->isp_type |= DT_ISP2312;
4a59f71d 2520 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2522 break;
2523 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2524 ha->isp_type |= DT_ISP2322;
4a59f71d 2525 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2526 if (ha->pdev->subsystem_vendor == 0x1028 &&
2527 ha->pdev->subsystem_device == 0x0170)
2528 ha->device_type |= DT_OEM_001;
441d1072 2529 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2530 break;
2531 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2532 ha->isp_type |= DT_ISP6312;
441d1072 2533 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2534 break;
2535 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2536 ha->isp_type |= DT_ISP6322;
441d1072 2537 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2538 break;
2539 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2540 ha->isp_type |= DT_ISP2422;
4a59f71d 2541 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2542 ha->device_type |= DT_FWI2;
c76f2c01 2543 ha->device_type |= DT_IIDMA;
441d1072 2544 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2545 break;
2546 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2547 ha->isp_type |= DT_ISP2432;
4a59f71d 2548 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2549 ha->device_type |= DT_FWI2;
c76f2c01 2550 ha->device_type |= DT_IIDMA;
441d1072 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2552 break;
4d4df193 2553 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2554 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2555 ha->device_type |= DT_ZIO_SUPPORTED;
2556 ha->device_type |= DT_FWI2;
2557 ha->device_type |= DT_IIDMA;
2558 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2559 break;
044cc6c8 2560 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2561 ha->isp_type |= DT_ISP5422;
e428924c 2562 ha->device_type |= DT_FWI2;
441d1072 2563 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2564 break;
044cc6c8 2565 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2566 ha->isp_type |= DT_ISP5432;
e428924c 2567 ha->device_type |= DT_FWI2;
441d1072 2568 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2569 break;
c3a2f0df 2570 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2571 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2572 ha->device_type |= DT_ZIO_SUPPORTED;
2573 ha->device_type |= DT_FWI2;
2574 ha->device_type |= DT_IIDMA;
441d1072 2575 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2576 break;
3a03eb79 2577 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2578 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2579 ha->device_type |= DT_ZIO_SUPPORTED;
2580 ha->device_type |= DT_FWI2;
2581 ha->device_type |= DT_IIDMA;
2582 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2583 break;
a9083016 2584 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2585 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2586 ha->device_type |= DT_ZIO_SUPPORTED;
2587 ha->device_type |= DT_FWI2;
2588 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2589 /* Initialize 82XX ISP flags */
2590 qla82xx_init_flags(ha);
2591 break;
7ec0effd 2592 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2593 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2594 ha->device_type |= DT_ZIO_SUPPORTED;
2595 ha->device_type |= DT_FWI2;
2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2597 /* Initialize 82XX ISP flags */
2598 qla82xx_init_flags(ha);
2599 break;
6246b8a1 2600 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2601 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2602 ha->device_type |= DT_ZIO_SUPPORTED;
2603 ha->device_type |= DT_FWI2;
2604 ha->device_type |= DT_IIDMA;
2605 ha->device_type |= DT_T10_PI;
2606 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2607 break;
2608 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2609 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2610 ha->device_type |= DT_ZIO_SUPPORTED;
2611 ha->device_type |= DT_FWI2;
2612 ha->device_type |= DT_IIDMA;
2613 ha->device_type |= DT_T10_PI;
2614 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2615 break;
8ae6d9c7 2616 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2617 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2618 break;
f73cb695 2619 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2620 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2621 ha->device_type |= DT_ZIO_SUPPORTED;
2622 ha->device_type |= DT_FWI2;
2623 ha->device_type |= DT_IIDMA;
8ce3f570 2624 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2625 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2626 break;
2c5bbbb2 2627 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2628 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2629 ha->device_type |= DT_ZIO_SUPPORTED;
2630 ha->device_type |= DT_FWI2;
2631 ha->device_type |= DT_IIDMA;
8ce3f570 2632 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2633 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2634 break;
2b48992f 2635 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2636 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2637 ha->device_type |= DT_ZIO_SUPPORTED;
2638 ha->device_type |= DT_FWI2;
2639 ha->device_type |= DT_IIDMA;
8ce3f570 2640 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2641 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2642 break;
ea5b6382 2643 }
e5b68a61 2644
a9083016 2645 if (IS_QLA82XX(ha))
43a9c38b 2646 ha->port_no = ha->portnum & 1;
f73cb695 2647 else {
a9083016
GM		 2648 /* Get adapter physical port no from interrupt pin register. */
2649 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2650 if (IS_QLA27XX(ha))
2651 ha->port_no--;
2652 else
2653 ha->port_no = !(ha->port_no & 1);
2654 }
a9083016 2655
7c3df132 2656 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2657 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2658 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2659}
2660
1e99e33a
AV		 2661static void
2662qla2xxx_scan_start(struct Scsi_Host *shost)
2663{
e315cd28 2664 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2665
cbc8eb67
AV		 2666 if (vha->hw->flags.running_gold_fw)
2667 return;
2668
e315cd28
AC		 2669 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2670 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2671 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2672 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2673}
2674
2675static int
2676qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2677{
e315cd28 2678 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2679
a5dd506e
BK		 2680 if (test_bit(UNLOADING, &vha->dpc_flags))
2681 return 1;
e315cd28 2682 if (!vha->host)
1e99e33a 2683 return 1;
e315cd28 2684 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2685 return 1;
2686
e315cd28 2687 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2688}
2689
ec7193e2
QT		 2690static void qla2x00_iocb_work_fn(struct work_struct *work)
2691{
2692 struct scsi_qla_host *vha = container_of(work,
2693 struct scsi_qla_host, iocb_work);
2694 int cnt = 0;
2695
2696 while (!list_empty(&vha->work_list)) {
2697 qla2x00_do_work(vha);
2698 cnt++;
2699 if (cnt > 10)
2700 break;
2701 }
2702}
2703
1da177e4
LT		 2704/*
2705 * PCI driver interface
2706 */
6f039790 2707static int
7ee61397 2708qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2709{
a1541d5a 2710 int ret = -ENODEV;
1da177e4 2711 struct Scsi_Host *host;
e315cd28
AC		 2712 scsi_qla_host_t *base_vha = NULL;
2713 struct qla_hw_data *ha;
29856e28 2714 char pci_info[30];
7d613ac6 2715 char fw_str[30], wq_name[30];
5433383e 2716 struct scsi_host_template *sht;
642ef983 2717 int bars, mem_only = 0;
e315cd28 2718 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2719 struct req_que *req = NULL;
2720 struct rsp_que *rsp = NULL;
5601236b 2721 int i;
d7459527 2722
285d0321 2723 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2724 sht = &qla2xxx_driver_template;
5433383e 2725 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2726 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2727 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2728 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2729 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2730 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2731 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2732 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2733 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2734 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2735 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2736 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2737 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2738 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2739 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2740 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2741 mem_only = 1;
7c3df132
SK		 2742 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2743 "Mem only adapter.\n");
285d0321 2744 }
7c3df132
SK		 2745 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2746 "Bars=%d.\n", bars);
285d0321 2747
09483916
BH		 2748 if (mem_only) {
2749 if (pci_enable_device_mem(pdev))
ddff7ed4 2750 return ret;
09483916
BH		 2751 } else {
2752 if (pci_enable_device(pdev))
ddff7ed4 2753 return ret;
09483916 2754 }
285d0321 2755
0927678f
JB		 2756 /* This may fail but that's ok */
2757 pci_enable_pcie_error_reporting(pdev);
285d0321 2758
e315cd28
AC		 2759 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2760 if (!ha) {
7c3df132
SK		 2761 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2762 "Unable to allocate memory for ha.\n");
ddff7ed4 2763 goto disable_device;
1da177e4 2764 }
7c3df132
SK		 2765 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2766 "Memory allocated for ha=%p.\n", ha);
e315cd28 2767 ha->pdev = pdev;
33e79977
QT		 2768 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2769 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2770 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2771 spin_lock_init(&ha->tgt.atio_lock);
2772
deeae7a6 2773 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2774
2775 /* Clear our data area */
285d0321 2776 ha->bars = bars;
09483916 2777 ha->mem_only = mem_only;
df4bf0bb 2778 spin_lock_init(&ha->hardware_lock);
339aa70e 2779 spin_lock_init(&ha->vport_slock);
a9b6f722 2780 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2781 mutex_init(&ha->optrom_mutex);
1da177e4 2782
ea5b6382
AV		 2783 /* Set ISP-type information. */
2784 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2785
2786 /* Set EEH reset type to fundamental if required by hba */
95676112 2787 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2788 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2789 pdev->needs_freset = 1;
ca79cf66 2790
cba1e47f
CD		 2791 ha->prev_topology = 0;
2792 ha->init_cb_size = sizeof(init_cb_t);
2793 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2794 ha->optrom_size = OPTROM_SIZE_2300;
2795
abbd8870 2796 /* Assign ISP specific operations. */
1da177e4 2797 if (IS_QLA2100(ha)) {
642ef983 2798 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2799 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2800 req_length = REQUEST_ENTRY_CNT_2100;
2801 rsp_length = RESPONSE_ENTRY_CNT_2100;
2802 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2803 ha->gid_list_info_size = 4;
3a03eb79
AV		 2804 ha->flash_conf_off = ~0;
2805 ha->flash_data_off = ~0;
2806 ha->nvram_conf_off = ~0;
2807 ha->nvram_data_off = ~0;
fd34f556 2808 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2809 } else if (IS_QLA2200(ha)) {
642ef983 2810 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2811 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2812 req_length = REQUEST_ENTRY_CNT_2200;
2813 rsp_length = RESPONSE_ENTRY_CNT_2100;
2814 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2815 ha->gid_list_info_size = 4;
3a03eb79
AV		 2816 ha->flash_conf_off = ~0;
2817 ha->flash_data_off = ~0;
2818 ha->nvram_conf_off = ~0;
2819 ha->nvram_data_off = ~0;
fd34f556 2820 ha->isp_ops = &qla2100_isp_ops;
fca29703 2821 } else if (IS_QLA23XX(ha)) {
642ef983 2822 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2823 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2824 req_length = REQUEST_ENTRY_CNT_2200;
2825 rsp_length = RESPONSE_ENTRY_CNT_2300;
2826 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2827 ha->gid_list_info_size = 6;
854165f4
AV		 2828 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2829 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2830 ha->flash_conf_off = ~0;
2831 ha->flash_data_off = ~0;
2832 ha->nvram_conf_off = ~0;
2833 ha->nvram_data_off = ~0;
fd34f556 2834 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2835 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2836 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2837 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2838 req_length = REQUEST_ENTRY_CNT_24XX;
2839 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2840 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2841 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2842 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2843 ha->gid_list_info_size = 8;
854165f4 2844 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2845 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2846 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2847 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2848 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2849 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2850 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2851 } else if (IS_QLA25XX(ha)) {
642ef983 2852 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2853 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2854 req_length = REQUEST_ENTRY_CNT_24XX;
2855 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2856 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2857 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2858 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2859 ha->gid_list_info_size = 8;
2860 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2861 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2862 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2863 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2864 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2865 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2866 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2867 } else if (IS_QLA81XX(ha)) {
642ef983 2868 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2869 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2870 req_length = REQUEST_ENTRY_CNT_24XX;
2871 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2872 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2873 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2874 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2875 ha->gid_list_info_size = 8;
2876 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2877 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2878 ha->isp_ops = &qla81xx_isp_ops;
2879 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2880 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2881 ha->nvram_conf_off = ~0;
2882 ha->nvram_data_off = ~0;
a9083016 2883 } else if (IS_QLA82XX(ha)) {
642ef983 2884 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2885 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2886 req_length = REQUEST_ENTRY_CNT_82XX;
2887 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2888 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2889 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2890 ha->gid_list_info_size = 8;
2891 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2892 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2893 ha->isp_ops = &qla82xx_isp_ops;
2894 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2895 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2896 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2897 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2898 } else if (IS_QLA8044(ha)) {
2899 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2900 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2901 req_length = REQUEST_ENTRY_CNT_82XX;
2902 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2903 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2904 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2905 ha->gid_list_info_size = 8;
2906 ha->optrom_size = OPTROM_SIZE_83XX;
2907 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2908 ha->isp_ops = &qla8044_isp_ops;
2909 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2910 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2911 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2912 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2913 } else if (IS_QLA83XX(ha)) {
7d613ac6 2914 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2915 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2916 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2917 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2918 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2919 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2920 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2921 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2922 ha->gid_list_info_size = 8;
2923 ha->optrom_size = OPTROM_SIZE_83XX;
2924 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2925 ha->isp_ops = &qla83xx_isp_ops;
2926 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2927 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2928 ha->nvram_conf_off = ~0;
2929 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2930 } else if (IS_QLAFX00(ha)) {
2931 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2932 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2933 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2934 req_length = REQUEST_ENTRY_CNT_FX00;
2935 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2936 ha->isp_ops = &qlafx00_isp_ops;
2937 ha->port_down_retry_count = 30; /* default value */
2938 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2939 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2940 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2941 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2942 ha->mr.host_info_resend = false;
2943 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2944 } else if (IS_QLA27XX(ha)) {
2945 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2946 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2947 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2948 req_length = REQUEST_ENTRY_CNT_83XX;
2949 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2950 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2951 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2952 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2953 ha->gid_list_info_size = 8;
2954 ha->optrom_size = OPTROM_SIZE_83XX;
2955 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2956 ha->isp_ops = &qla27xx_isp_ops;
2957 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2958 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2959 ha->nvram_conf_off = ~0;
2960 ha->nvram_data_off = ~0;
1da177e4 2961 }
6246b8a1 2962
7c3df132
SK		 2963 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2964 "mbx_count=%d, req_length=%d, "
2965 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2966 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2967 "max_fibre_devices=%d.\n",
7c3df132
SK		 2968 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2969 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2970 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2971 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2972 "isp_ops=%p, flash_conf_off=%d, "
2973 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2974 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2975 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2976
2977 /* Configure PCI I/O space */
2978 ret = ha->isp_ops->iospace_config(ha);
2979 if (ret)
0a63ad12 2980 goto iospace_config_failed;
706f457d
GM		 2981
2982 ql_log_pci(ql_log_info, pdev, 0x001d,
2983 "Found an ISP%04X irq %d iobase 0x%p.\n",
2984 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2985 mutex_init(&ha->vport_lock);
d7459527 2986 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2987 init_completion(&ha->mbx_cmd_comp);
2988 complete(&ha->mbx_cmd_comp);
2989 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2990 init_completion(&ha->dcbx_comp);
f356bef1 2991 init_completion(&ha->lb_portup_comp);
1da177e4 2992
2c3dfe3f 2993 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2994
53303c42 2995 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2996 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2997 "64 Bit addressing is %s.\n",
2998 ha->flags.enable_64bit_addressing ? "enable" :
2999 "disable");
73208dfd 3000 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3001 if (ret) {
7c3df132
SK		 3002 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3003 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3004
e315cd28
AC		 3005 goto probe_hw_failed;
3006 }
3007
73208dfd 3008 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3009 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3010 req->max_q_depth = ql2xmaxqdepth;
3011
e315cd28
AC		 3012
3013 base_vha = qla2x00_create_host(sht, ha);
3014 if (!base_vha) {
a1541d5a 3015 ret = -ENOMEM;
e315cd28 3016 goto probe_hw_failed;
1da177e4
LT		 3017 }
3018
e315cd28 3019 pci_set_drvdata(pdev, base_vha);
6b383979 3020 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3021
e315cd28 3022 host = base_vha->host;
2afa19a9 3023 base_vha->req = req;
73208dfd 3024 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 3025 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 3026 else
e315cd28
AC		 3027 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3028 base_vha->vp_idx;
58548cb5 3029
8ae6d9c7
GM		 3030 /* Setup fcport template structure. */
3031 ha->mr.fcport.vha = base_vha;
3032 ha->mr.fcport.port_type = FCT_UNKNOWN;
3033 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3034 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3035 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3036 ha->mr.fcport.scan_state = 1;
3037
58548cb5
GM		 3038 /* Set the SG table size based on ISP type */
3039 if (!IS_FWI2_CAPABLE(ha)) {
3040 if (IS_QLA2100(ha))
3041 host->sg_tablesize = 32;
3042 } else {
3043 if (!IS_QLA82XX(ha))
3044 host->sg_tablesize = QLA_SG_ALL;
3045 }
642ef983 3046 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3047 host->cmd_per_lun = 3;
3048 host->unique_id = host->host_no;
e02587d7 3049 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3050 host->max_cmd_len = 32;
3051 else
3052 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3053 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3054 /* Older HBAs support only 16-bit LUNs */
3055 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3056 ql2xmaxlun > 0xffff)
3057 host->max_lun = 0xffff;
3058 else
3059 host->max_lun = ql2xmaxlun;
e315cd28 3060 host->transportt = qla2xxx_transport_template;
9a069e19 3061 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3062
7c3df132
SK		 3063 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3064 "max_id=%d this_id=%d "
3065 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3066 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3067 host->this_id, host->cmd_per_lun, host->unique_id,
3068 host->max_cmd_len, host->max_channel, host->max_lun,
3069 host->transportt, sht->vendor_id);
3070
1010f21e
HM		 3071 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3072
d7459527
MH		 3073 /* Set up the irqs */
3074 ret = qla2x00_request_irqs(ha, rsp);
3075 if (ret)
79c67fb6 3076 goto probe_failed;
d7459527 3077
9a347ff4 3078 /* Alloc arrays of request and response ring ptrs */
a5082923
BK		 3079 ret = qla2x00_alloc_queues(ha, req, rsp);
3080 if (ret) {
9a347ff4
CD		 3081 ql_log(ql_log_fatal, base_vha, 0x003d,
3082 "Failed to allocate memory for queue pointers..."
3083 "aborting.\n");
79c67fb6 3084 goto probe_failed;
9a347ff4
CD		 3085 }
3086
5601236b
MH		 3087 if (ha->mqenable && shost_use_blk_mq(host)) {
3088 /* number of hardware queues supported by blk/scsi-mq*/
3089 host->nr_hw_queues = ha->max_qpairs;
3090
3091 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3092 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3093 } else {
3094 if (ql2xnvmeenable) {
3095 host->nr_hw_queues = ha->max_qpairs;
3096 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3097 "FC-NVMe support is enabled, HW queues=%d\n",
3098 host->nr_hw_queues);
3099 } else {
3100 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3101 "blk/scsi-mq disabled.\n");
3102 }
3103 }
5601236b 3104
2d70c103 3105 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3106
90a86fc0
JC		 3107 pci_save_state(pdev);
3108
9a347ff4 3109 /* Assign back pointers */
2afa19a9
AC		 3110 rsp->req = req;
3111 req->rsp = rsp;
9a347ff4 3112
8ae6d9c7
GM		 3113 if (IS_QLAFX00(ha)) {
3114 ha->rsp_q_map[0] = rsp;
3115 ha->req_q_map[0] = req;
3116 set_bit(0, ha->req_qid_map);
3117 set_bit(0, ha->rsp_qid_map);
3118 }
3119
08029990
AV		 3120 /* FWI2-capable only. */
3121 req->req_q_in = &ha->iobase->isp24.req_q_in;
3122 req->req_q_out = &ha->iobase->isp24.req_q_out;
3123 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3124 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3125 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3126 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3127 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3128 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3129 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3130 }
3131
8ae6d9c7
GM		 3132 if (IS_QLAFX00(ha)) {
3133 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3134 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3135 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3136 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3137 }
3138
7ec0effd 3139 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3140 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3141 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3142 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3143 }
3144
7c3df132
SK		 3145 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3146 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3147 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3148 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3149 "req->req_q_in=%p req->req_q_out=%p "
3150 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3151 req->req_q_in, req->req_q_out,
3152 rsp->rsp_q_in, rsp->rsp_q_out);
3153 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3154 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3155 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3156 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3157 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3158 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3159
8ae6d9c7 3160 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3161 ql_log(ql_log_fatal, base_vha, 0x00d6,
3162 "Failed to initialize adapter - Adapter flags %x.\n",
3163 base_vha->device_flags);
1da177e4 3164
a9083016
GM		 3165 if (IS_QLA82XX(ha)) {
3166 qla82xx_idc_lock(ha);
3167 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3168 QLA8XXX_DEV_FAILED);
a9083016 3169 qla82xx_idc_unlock(ha);
7c3df132
SK		 3170 ql_log(ql_log_fatal, base_vha, 0x00d7,
3171 "HW State: FAILED.\n");
7ec0effd
AD		 3172 } else if (IS_QLA8044(ha)) {
3173 qla8044_idc_lock(ha);
3174 qla8044_wr_direct(base_vha,
3175 QLA8044_CRB_DEV_STATE_INDEX,
3176 QLA8XXX_DEV_FAILED);
3177 qla8044_idc_unlock(ha);
3178 ql_log(ql_log_fatal, base_vha, 0x0150,
3179 "HW State: FAILED.\n");
a9083016
GM		 3180 }
3181
a1541d5a 3182 ret = -ENODEV;
1da177e4
LT		 3183 goto probe_failed;
3184 }
3185
3b1bef64
CD		 3186 if (IS_QLAFX00(ha))
3187 host->can_queue = QLAFX00_MAX_CANQUEUE;
3188 else
3189 host->can_queue = req->num_outstanding_cmds - 10;
3190
3191 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3192 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3193 host->can_queue, base_vha->req,
3194 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3195
6bc11475 3196 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
7616c248
AP		 3197 if (unlikely(!ha->wq)) {
3198 ret = -ENOMEM;
3199 goto probe_failed;
3200 }
6bc11475 3201
e326d22a
QT		 3202 if (ha->mqenable) {
3203 bool mq = false;
3204 bool startit = false;
e326d22a
QT		 3205
3206 if (QLA_TGT_MODE_ENABLED()) {
3207 mq = true;
3208 startit = false;
3209 }
3210
3211 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3212 shost_use_blk_mq(host)) {
3213 mq = true;
3214 startit = true;
3215 }
3216
3217 if (mq) {
3218 /* Create start of day qpairs for Block MQ */
5601236b 3219 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3220 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3221 }
3222 }
68ca949c 3223
cbc8eb67
AV		 3224 if (ha->flags.running_gold_fw)
3225 goto skip_dpc;
3226
1da177e4
LT		 3227 /*
3228 * Startup the kernel thread for this host adapter
3229 */
39a11240 3230 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3231 "%s_dpc", base_vha->host_str);
39a11240 3232 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3233 ql_log(ql_log_fatal, base_vha, 0x00ed,
3234 "Failed to start DPC thread.\n");
39a11240 3235 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3236 ha->dpc_thread = NULL;
1da177e4
LT		 3237 goto probe_failed;
3238 }
7c3df132
SK		 3239 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3240 "DPC thread started successfully.\n");
1da177e4 3241
2d70c103
NB		 3242 /*
3243 * If we're not coming up in initiator mode, we might sit for
3244 * a while without waking up the dpc thread, which leads to a
3245 * stuck process warning. So just kick the dpc once here and
3246 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3247 */
3248 qla2xxx_wake_dpc(base_vha);
3249
f3ddac19
CD		 3250 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3251
81178772
SK		 3252 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3253 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3254 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3255 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3256
3257 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3258 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3259 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3260 INIT_WORK(&ha->idc_state_handler,
3261 qla83xx_idc_state_handler_work);
3262 INIT_WORK(&ha->nic_core_unrecoverable,
3263 qla83xx_nic_core_unrecoverable_work);
3264 }
3265
cbc8eb67 3266skip_dpc:
e315cd28
AC		 3267 list_add_tail(&base_vha->list, &ha->vp_list);
3268 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3269
3270 /* Initialized the timer */
8e5f4ba0 3271 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3272 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3273 "Started qla2x00_timer with "
3274 "interval=%d.\n", WATCH_INTERVAL);
3275 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3276 "Detected hba at address=%p.\n",
3277 ha);
d19044c3 3278
e02587d7 3279 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3280 if (ha->fw_attributes & BIT_4) {
9e522cd8 3281 int prot = 0, guard;
bad75002 3282 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3283 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3284 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3285 if (ql2xenabledif == 1)
3286 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3287 scsi_host_set_prot(host,
8cb2049c 3288 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3289 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3290 | SHOST_DIF_TYPE3_PROTECTION
3291 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3292 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3293 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3294
3295 guard = SHOST_DIX_GUARD_CRC;
3296
3297 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3298 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3299 guard |= SHOST_DIX_GUARD_IP;
3300
3301 scsi_host_set_guard(host, guard);
bad75002
AE		 3302 } else
3303 base_vha->flags.difdix_supported = 0;
3304 }
3305
a9083016
GM		 3306 ha->isp_ops->enable_intrs(ha);
3307
1fe19ee4
AB		 3308 if (IS_QLAFX00(ha)) {
3309 ret = qlafx00_fx_disc(base_vha,
3310 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3311 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3312 QLA_SG_ALL : 128;
3313 }
3314
a1541d5a
AV		 3315 ret = scsi_add_host(host, &pdev->dev);
3316 if (ret)
3317 goto probe_failed;
3318
1486400f
MR		 3319 base_vha->flags.init_done = 1;
3320 base_vha->flags.online = 1;
edaa5c74 3321 ha->prev_minidump_failed = 0;
1486400f 3322
7c3df132
SK		 3323 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3324 "Init done and hba is online.\n");
3325
726b8548
QT		 3326 if (qla_ini_mode_enabled(base_vha) ||
3327 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3328 scsi_scan_host(host);
3329 else
3330 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3331 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3332
e315cd28 3333 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3334
8ae6d9c7 3335 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3336 ret = qlafx00_fx_disc(base_vha,
3337 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3338
3339 /* Register system information */
3340 ret = qlafx00_fx_disc(base_vha,
3341 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3342 }
3343
e315cd28 3344 qla2x00_init_host_attr(base_vha);
a1541d5a 3345
e315cd28 3346 qla2x00_dfs_setup(base_vha);
df613b96 3347
03eb912a
AB		 3348 ql_log(ql_log_info, base_vha, 0x00fb,
3349 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3350 ql_log(ql_log_info, base_vha, 0x00fc,
3351 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3352 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3353 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3354 base_vha->host_no,
df57caba 3355 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3356
2d70c103
NB		 3357 qlt_add_target(ha, base_vha);
3358
6b383979 3359 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3360
3361 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3362 return -ENODEV;
3363
e4e3a2ce
QT		 3364 if (ha->flags.detected_lr_sfp) {
3365 ql_log(ql_log_info, base_vha, 0xffff,
3366 "Reset chip to pick up LR SFP setting\n");
3367 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3368 qla2xxx_wake_dpc(base_vha);
3369 }
3370
1da177e4
LT		 3371 return 0;
3372
3373probe_failed:
e6e392ff
BK		 3374 if (base_vha->gnl.l) {
3375 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3376 base_vha->gnl.l, base_vha->gnl.ldma);
3377 base_vha->gnl.l = NULL;
3378 }
3379
b9978769
AV		 3380 if (base_vha->timer_active)
3381 qla2x00_stop_timer(base_vha);
3382 base_vha->flags.online = 0;
3383 if (ha->dpc_thread) {
3384 struct task_struct *t = ha->dpc_thread;
3385
3386 ha->dpc_thread = NULL;
3387 kthread_stop(t);
3388 }
3389
e315cd28 3390 qla2x00_free_device(base_vha);
e315cd28 3391 scsi_host_put(base_vha->host);
a5082923
BK		 3392 /*
3393 * Need to NULL out local req/rsp after
3394 * qla2x00_free_device => qla2x00_free_queues frees
3395 * what these are pointing to. Or else we'll
3396 * fall over below in qla2x00_free_req/rsp_que.
3397 */
3398 req = NULL;
3399 rsp = NULL;
1da177e4 3400
e315cd28 3401probe_hw_failed:
97424fae 3402 qla2x00_mem_free(ha);
3403 qla2x00_free_req_que(ha, req);
3404 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3405 qla2x00_clear_drv_active(ha);
3406
0a63ad12 3407iospace_config_failed:
7ec0effd 3408 if (IS_P3P_TYPE(ha)) {
0a63ad12 3409 if (!ha->nx_pcibase)
f73cb695 3410 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3411 if (!ql2xdbwr)
f73cb695 3412 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3413 } else {
3414 if (ha->iobase)
3415 iounmap(ha->iobase);
8ae6d9c7
GM		 3416 if (ha->cregbase)
3417 iounmap(ha->cregbase);
a9083016 3418 }
e315cd28
AC		 3419 pci_release_selected_regions(ha->pdev, ha->bars);
3420 kfree(ha);
1da177e4 3421
ddff7ed4 3422disable_device:
e315cd28 3423 pci_disable_device(pdev);
a1541d5a 3424 return ret;
1da177e4 3425}
1da177e4 3426
e30d1756
MI		 3427static void
3428qla2x00_shutdown(struct pci_dev *pdev)
3429{
3430 scsi_qla_host_t *vha;
3431 struct qla_hw_data *ha;
3432
3433 vha = pci_get_drvdata(pdev);
3434 ha = vha->hw;
3435
efdb5760
SC		 3436 ql_log(ql_log_info, vha, 0xfffa,
3437 "Adapter shutdown\n");
3438
3439 /*
3440 * Prevent future board_disable and wait
3441 * until any pending board_disable has completed.
3442 */
3443 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3444 cancel_work_sync(&ha->board_disable);
3445
3446 if (!atomic_read(&pdev->enable_cnt))
3447 return;
3448
42479343
AB		 3449 /* Notify ISPFX00 firmware */
3450 if (IS_QLAFX00(ha))
3451 qlafx00_driver_shutdown(vha, 20);
3452
e30d1756
MI		 3453 /* Turn-off FCE trace */
3454 if (ha->flags.fce_enabled) {
3455 qla2x00_disable_fce_trace(vha, NULL, NULL);
3456 ha->flags.fce_enabled = 0;
3457 }
3458
3459 /* Turn-off EFT trace */
3460 if (ha->eft)
3461 qla2x00_disable_eft_trace(vha);
3462
3463 /* Stop currently executing firmware. */
3464 qla2x00_try_to_stop_firmware(vha);
3465
c0579128
NP		 3466 /* Disable timer */
3467 if (vha->timer_active)
3468 qla2x00_stop_timer(vha);
3469
e30d1756
MI		 3470 /* Turn adapter off line */
3471 vha->flags.online = 0;
3472
3473 /* turn-off interrupts on the card */
3474 if (ha->interrupts_on) {
3475 vha->flags.init_done = 0;
3476 ha->isp_ops->disable_intrs(ha);
3477 }
3478
3479 qla2x00_free_irqs(vha);
3480
3481 qla2x00_free_fw_dump(ha);
61d41f61 3482
61d41f61 3483 pci_disable_device(pdev);
efdb5760
SC		 3484 ql_log(ql_log_info, vha, 0xfffe,
3485 "Adapter shutdown successfully.\n");
e30d1756
MI		 3486}
3487
fe1b806f 3488/* Deletes all the virtual ports for a given ha */
4c993f76 3489static void
fe1b806f 3490qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3491{
fe1b806f 3492 scsi_qla_host_t *vha;
feafb7b1 3493 unsigned long flags;
e315cd28 3494
43ebf16d
AE		 3495 mutex_lock(&ha->vport_lock);
3496 while (ha->cur_vport_count) {
43ebf16d 3497 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3498
43ebf16d
AE		 3499 BUG_ON(base_vha->list.next == &ha->vp_list);
3500 /* This assumes first entry in ha->vp_list is always base vha */
3501 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3502 scsi_host_get(vha->host);
feafb7b1 3503
43ebf16d
AE		 3504 spin_unlock_irqrestore(&ha->vport_slock, flags);
3505 mutex_unlock(&ha->vport_lock);
3506
3507 fc_vport_terminate(vha->fc_vport);
3508 scsi_host_put(vha->host);
feafb7b1 3509
43ebf16d 3510 mutex_lock(&ha->vport_lock);
e315cd28 3511 }
43ebf16d 3512 mutex_unlock(&ha->vport_lock);
fe1b806f 3513}
1da177e4 3514
fe1b806f
CD		 3515/* Stops all deferred work threads */
3516static void
3517qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3518{
7d613ac6
SV		 3519 /* Cancel all work and destroy DPC workqueues */
3520 if (ha->dpc_lp_wq) {
3521 cancel_work_sync(&ha->idc_aen);
3522 destroy_workqueue(ha->dpc_lp_wq);
3523 ha->dpc_lp_wq = NULL;
3524 }
3525
3526 if (ha->dpc_hp_wq) {
3527 cancel_work_sync(&ha->nic_core_reset);
3528 cancel_work_sync(&ha->idc_state_handler);
3529 cancel_work_sync(&ha->nic_core_unrecoverable);
3530 destroy_workqueue(ha->dpc_hp_wq);
3531 ha->dpc_hp_wq = NULL;
3532 }
3533
b9978769
AV		 3534 /* Kill the kernel thread for this host */
3535 if (ha->dpc_thread) {
3536 struct task_struct *t = ha->dpc_thread;
3537
3538 /*
3539 * qla2xxx_wake_dpc checks for ->dpc_thread
3540 * so we need to zero it out.
3541 */
3542 ha->dpc_thread = NULL;
3543 kthread_stop(t);
3544 }
fe1b806f 3545}
1da177e4 3546
fe1b806f
CD		 3547static void
3548qla2x00_unmap_iobases(struct qla_hw_data *ha)
3549{
a9083016 3550 if (IS_QLA82XX(ha)) {
b963752f 3551
f73cb695 3552 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3553 if (!ql2xdbwr)
f73cb695 3554 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3555 } else {
3556 if (ha->iobase)
3557 iounmap(ha->iobase);
1da177e4 3558
8ae6d9c7
GM		 3559 if (ha->cregbase)
3560 iounmap(ha->cregbase);
3561
a9083016
GM		 3562 if (ha->mqiobase)
3563 iounmap(ha->mqiobase);
6246b8a1 3564
f73cb695 3565 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3566 iounmap(ha->msixbase);
a9083016 3567 }
fe1b806f
CD		 3568}
3569
3570static void
db7157d4 3571qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3572{
fe1b806f
CD		 3573 if (IS_QLA8044(ha)) {
3574 qla8044_idc_lock(ha);
c41afc9a 3575 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3576 qla8044_idc_unlock(ha);
3577 } else if (IS_QLA82XX(ha)) {
3578 qla82xx_idc_lock(ha);
3579 qla82xx_clear_drv_active(ha);
3580 qla82xx_idc_unlock(ha);
3581 }
3582}
3583
3584static void
3585qla2x00_remove_one(struct pci_dev *pdev)
3586{
3587 scsi_qla_host_t *base_vha;
3588 struct qla_hw_data *ha;
3589
beb9e315
JL		 3590 base_vha = pci_get_drvdata(pdev);
3591 ha = base_vha->hw;
3592
3593 /* Indicate device removal to prevent future board_disable and wait
3594 * until any pending board_disable has completed. */
3595 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3596 cancel_work_sync(&ha->board_disable);
3597
fe1b806f 3598 /*
beb9e315
JL		 3599 * If the PCI device is disabled then there was a PCI-disconnect and
3600 * qla2x00_disable_board_on_pci_error has taken care of most of the
3601 * resources.
fe1b806f 3602 */
beb9e315 3603 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3604 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3605 base_vha->gnl.l, base_vha->gnl.ldma);
e6e392ff 3606 base_vha->gnl.l = NULL;
beb9e315
JL		 3607 scsi_host_put(base_vha->host);
3608 kfree(ha);
3609 pci_set_drvdata(pdev, NULL);
fe1b806f 3610 return;
beb9e315 3611 }
638a1a01
SC		 3612 qla2x00_wait_for_hba_ready(base_vha);
3613
08e05b6b
QT		 3614 qla2x00_wait_for_sess_deletion(base_vha);
3615
726b8548
QT		 3616 /*
3617 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3618 * where it was set first.
3619 */
3620 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3621 return;
3622
fe1b806f 3623 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3624
3625 qla_nvme_delete(base_vha);
3626
726b8548
QT		 3627 dma_free_coherent(&ha->pdev->dev,
3628 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3629
e6e392ff
BK		 3630 base_vha->gnl.l = NULL;
3631
fe1b806f
CD		 3632 if (IS_QLAFX00(ha))
3633 qlafx00_driver_shutdown(base_vha, 20);
3634
3635 qla2x00_delete_all_vps(ha, base_vha);
3636
3637 if (IS_QLA8031(ha)) {
3638 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3639 "Clearing fcoe driver presence.\n");
3640 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3641 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3642 "Error while clearing DRV-Presence.\n");
3643 }
3644
3645 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3646
3647 qla2x00_dfs_remove(base_vha);
3648
3649 qla84xx_put_chip(base_vha);
3650
2d5a4c34
HM		 3651 /* Laser should be disabled only for ISP2031 */
3652 if (IS_QLA2031(ha))
3653 qla83xx_disable_laser(base_vha);
3654
fe1b806f
CD		 3655 /* Disable timer */
3656 if (base_vha->timer_active)
3657 qla2x00_stop_timer(base_vha);
3658
3659 base_vha->flags.online = 0;
3660
b0d6cabd
HM		 3661 /* free DMA memory */
3662 if (ha->exlogin_buf)
3663 qla2x00_free_exlogin_buffer(ha);
3664
2f56a7f1
HM		 3665 /* free DMA memory */
3666 if (ha->exchoffld_buf)
3667 qla2x00_free_exchoffld_buffer(ha);
3668
fe1b806f
CD		 3669 qla2x00_destroy_deferred_work(ha);
3670
3671 qlt_remove_target(ha, base_vha);
3672
3673 qla2x00_free_sysfs_attr(base_vha, true);
3674
3675 fc_remove_host(base_vha->host);
482c9dc7 3676 qlt_remove_target_resources(ha);
fe1b806f
CD		 3677
3678 scsi_remove_host(base_vha->host);
3679
3680 qla2x00_free_device(base_vha);
3681
db7157d4 3682 qla2x00_clear_drv_active(ha);
fe1b806f 3683
d2749ffa
AE		 3684 scsi_host_put(base_vha->host);
3685
fe1b806f 3686 qla2x00_unmap_iobases(ha);
73208dfd 3687
e315cd28
AC		 3688 pci_release_selected_regions(ha->pdev, ha->bars);
3689 kfree(ha);
1da177e4 3690
90a86fc0
JC		 3691 pci_disable_pcie_error_reporting(pdev);
3692
665db93b 3693 pci_disable_device(pdev);
1da177e4 3694}
1da177e4
LT		 3695
3696static void
e315cd28 3697qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3698{
e315cd28 3699 struct qla_hw_data *ha = vha->hw;
1da177e4 3700
85880801
AV		 3701 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3702
3703 /* Disable timer */
3704 if (vha->timer_active)
3705 qla2x00_stop_timer(vha);
3706
2afa19a9 3707 qla25xx_delete_queues(vha);
fe1b806f 3708
df613b96 3709 if (ha->flags.fce_enabled)
e315cd28 3710 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3711
a7a167bf 3712 if (ha->eft)
e315cd28 3713 qla2x00_disable_eft_trace(vha);
a7a167bf 3714
f6ef3b18 3715 /* Stop currently executing firmware. */
e315cd28 3716 qla2x00_try_to_stop_firmware(vha);
1da177e4 3717
85880801
AV		 3718 vha->flags.online = 0;
3719
f6ef3b18 3720 /* turn-off interrupts on the card */
a9083016
GM		 3721 if (ha->interrupts_on) {
3722 vha->flags.init_done = 0;
fd34f556 3723 ha->isp_ops->disable_intrs(ha);
a9083016 3724 }
f6ef3b18 3725
093df737
QT		 3726 qla2x00_free_fcports(vha);
3727
e315cd28 3728 qla2x00_free_irqs(vha);
1da177e4 3729
093df737
QT		 3730 /* Flush the work queue and remove it */
3731 if (ha->wq) {
3732 flush_workqueue(ha->wq);
3733 destroy_workqueue(ha->wq);
3734 ha->wq = NULL;
3735 }
3736
8867048b 3737
e315cd28 3738 qla2x00_mem_free(ha);
73208dfd 3739
08de2844
GM		 3740 qla82xx_md_free(vha);
3741
73208dfd 3742 qla2x00_free_queues(ha);
1da177e4
LT		 3743}
3744
8867048b
CD		 3745void qla2x00_free_fcports(struct scsi_qla_host *vha)
3746{
3747 fc_port_t *fcport, *tfcport;
3748
3749 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3750 list_del(&fcport->list);
5f16b331 3751 qla2x00_clear_loop_id(fcport);
8867048b 3752 kfree(fcport);
8867048b
CD		 3753 }
3754}
3755
d97994dc 3756static inline void
e315cd28 3757qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3758 int defer)
3759{
d97994dc 3760 struct fc_rport *rport;
67becc00 3761 scsi_qla_host_t *base_vha;
044d78e1 3762 unsigned long flags;
d97994dc
AV		 3763
3764 if (!fcport->rport)
3765 return;
3766
3767 rport = fcport->rport;
3768 if (defer) {
67becc00 3769 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3770 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3771 fcport->drport = rport;
044d78e1 3772 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3773 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3774 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3775 qla2xxx_wake_dpc(base_vha);
2d70c103 3776 } else {
df673274 3777 int now;
726b8548 3778 if (rport) {
83548fe2
QT		 3779 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3780 "%s %8phN. rport %p roles %x\n",
3781 __func__, fcport->port_name, rport,
3782 rport->roles);
d20ed91b 3783 fc_remote_port_delete(rport);
726b8548 3784 }
df673274 3785 qlt_do_generation_tick(vha, &now);
2d70c103 3786 }
d97994dc
AV		 3787}
3788
1da177e4
LT		 3789/*
3790 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3791 *
3792 * Input: ha = adapter block pointer. fcport = port structure pointer.
3793 *
3794 * Return: None.
3795 *
3796 * Context:
3797 */
e315cd28 3798void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3799 int do_login, int defer)
1da177e4 3800{
8ae6d9c7
GM		 3801 if (IS_QLAFX00(vha->hw)) {
3802 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3803 qla2x00_schedule_rport_del(vha, fcport, defer);
3804 return;
3805 }
3806
2c3dfe3f 3807 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3808 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3809 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3810 qla2x00_schedule_rport_del(vha, fcport, defer);
3811 }
fa2a1ce5 3812 /*
1da177e4
LT		 3813 * We may need to retry the login, so don't change the state of the
3814 * port but do the retries.
3815 */
3816 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3817 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3818
3819 if (!do_login)
3820 return;
3821
a1d0285e
AE		 3822 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3823
1da177e4 3824 if (fcport->login_retry == 0) {
e315cd28 3825 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3826
83548fe2 3827 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3828 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3829 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3830 }
3831}
3832
3833/*
3834 * qla2x00_mark_all_devices_lost
3835 * Updates fcport state when device goes offline.
3836 *
3837 * Input:
3838 * ha = adapter block pointer.
3839 * fcport = port structure pointer.
3840 *
3841 * Return:
3842 * None.
3843 *
3844 * Context:
3845 */
3846void
e315cd28 3847qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3848{
3849 fc_port_t *fcport;
3850
83548fe2
QT		 3851 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3852 "Mark all dev lost\n");
726b8548 3853
e315cd28 3854 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3855 fcport->scan_state = 0;
147c591f 3856 qlt_schedule_sess_for_deletion(fcport);
726b8548 3857
c6d39e23 3858 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3859 continue;
0d6e61bc 3860
1da177e4
LT		 3861 /*
3862 * No point in marking the device as lost, if the device is
3863 * already DEAD.
3864 */
3865 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3866 continue;
e315cd28 3867 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3868 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3869 if (defer)
3870 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3871 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3872 qla2x00_schedule_rport_del(vha, fcport, defer);
3873 }
1da177e4
LT		 3874 }
3875}
3876
3877/*
3878* qla2x00_mem_alloc
3879* Allocates adapter memory.
3880*
3881* Returns:
3882* 0 = success.
e8711085 3883* !0 = failure.
1da177e4 3884*/
e8711085 3885static int
73208dfd
AC		 3886qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3887 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3888{
3889 char name[16];
1da177e4 3890
e8711085 3891 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3892 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3893 if (!ha->init_cb)
e315cd28 3894 goto fail;
e8711085 3895
2d70c103
NB		 3896 if (qlt_mem_alloc(ha) < 0)
3897 goto fail_free_init_cb;
3898
642ef983
CD		 3899 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3900 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3901 if (!ha->gid_list)
2d70c103 3902 goto fail_free_tgt_mem;
1da177e4 3903
e8711085
AV		 3904 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3905 if (!ha->srb_mempool)
e315cd28 3906 goto fail_free_gid_list;
e8711085 3907
7ec0effd 3908 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3909 /* Allocate cache for CT6 Ctx. */
3910 if (!ctx_cachep) {
3911 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3912 sizeof(struct ct6_dsd), 0,
3913 SLAB_HWCACHE_ALIGN, NULL);
3914 if (!ctx_cachep)
fc1ffd6c 3915 goto fail_free_srb_mempool;
a9083016
GM		 3916 }
3917 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3918 ctx_cachep);
3919 if (!ha->ctx_mempool)
3920 goto fail_free_srb_mempool;
7c3df132
SK		 3921 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3922 "ctx_cachep=%p ctx_mempool=%p.\n",
3923 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3924 }
3925
e8711085
AV		 3926 /* Get memory for cached NVRAM */
3927 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3928 if (!ha->nvram)
a9083016 3929 goto fail_free_ctx_mempool;
e8711085 3930
e315cd28
AC		 3931 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3932 ha->pdev->device);
3933 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3934 DMA_POOL_SIZE, 8, 0);
3935 if (!ha->s_dma_pool)
3936 goto fail_free_nvram;
3937
7c3df132
SK		 3938 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3939 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3940 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3941
7ec0effd 3942 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3943 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3944 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3945 if (!ha->dl_dma_pool) {
7c3df132
SK		 3946 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3947 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3948 goto fail_s_dma_pool;
3949 }
3950
3951 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3952 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3953 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3954 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3955 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3956 goto fail_dl_dma_pool;
3957 }
7c3df132
SK		 3958 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3959 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3960 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3961 }
3962
e8711085
AV		 3963 /* Allocate memory for SNS commands */
3964 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3965 /* Get consistent memory allocated for SNS commands */
e8711085 3966 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3967 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3968 if (!ha->sns_cmd)
e315cd28 3969 goto fail_dma_pool;
7c3df132 3970 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3971 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3972 } else {
e315cd28 3973 /* Get consistent memory allocated for MS IOCB */
e8711085 3974 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3975 &ha->ms_iocb_dma);
e8711085 3976 if (!ha->ms_iocb)
e315cd28
AC		 3977 goto fail_dma_pool;
3978 /* Get consistent memory allocated for CT SNS commands */
e8711085 3979 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3980 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3981 if (!ha->ct_sns)
3982 goto fail_free_ms_iocb;
7c3df132
SK		 3983 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3984 "ms_iocb=%p ct_sns=%p.\n",
3985 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3986 }
3987
e315cd28 3988 /* Allocate memory for request ring */
73208dfd
AC		 3989 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3990 if (!*req) {
7c3df132
SK		 3991 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3992 "Failed to allocate memory for req.\n");
e315cd28
AC		 3993 goto fail_req;
3994 }
73208dfd
AC		 3995 (*req)->length = req_len;
3996 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3997 ((*req)->length + 1) * sizeof(request_t),
3998 &(*req)->dma, GFP_KERNEL);
3999 if (!(*req)->ring) {
7c3df132
SK		 4000 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4001 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4002 goto fail_req_ring;
4003 }
4004 /* Allocate memory for response ring */
73208dfd
AC		 4005 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4006 if (!*rsp) {
7c3df132
SK		 4007 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4008 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4009 goto fail_rsp;
4010 }
73208dfd
AC		 4011 (*rsp)->hw = ha;
4012 (*rsp)->length = rsp_len;
4013 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4014 ((*rsp)->length + 1) * sizeof(response_t),
4015 &(*rsp)->dma, GFP_KERNEL);
4016 if (!(*rsp)->ring) {
7c3df132
SK		 4017 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4018 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4019 goto fail_rsp_ring;
4020 }
73208dfd
AC		 4021 (*req)->rsp = *rsp;
4022 (*rsp)->req = *req;
7c3df132
SK		 4023 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4024 "req=%p req->length=%d req->ring=%p rsp=%p "
4025 "rsp->length=%d rsp->ring=%p.\n",
4026 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4027 (*rsp)->ring);
73208dfd
AC		 4028 /* Allocate memory for NVRAM data for vports */
4029 if (ha->nvram_npiv_size) {
4030 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 4031 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 4032 if (!ha->npiv_info) {
7c3df132
SK		 4033 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4034 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4035 goto fail_npiv_info;
4036 }
4037 } else
4038 ha->npiv_info = NULL;
e8711085 4039
b64b0e8f 4040 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4041 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4042 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4043 &ha->ex_init_cb_dma);
4044 if (!ha->ex_init_cb)
4045 goto fail_ex_init_cb;
7c3df132
SK		 4046 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4047 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4048 }
4049
a9083016
GM		 4050 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4051
5ff1d584
AV		 4052 /* Get consistent memory allocated for Async Port-Database. */
4053 if (!IS_FWI2_CAPABLE(ha)) {
4054 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4055 &ha->async_pd_dma);
4056 if (!ha->async_pd)
4057 goto fail_async_pd;
7c3df132
SK		 4058 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4059 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4060 }
4061
e315cd28 4062 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4063
4064 /* Allocate memory for our loop_id bitmap */
4065 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4066 GFP_KERNEL);
4067 if (!ha->loop_id_map)
fc1ffd6c 4068 goto fail_loop_id_map;
5f16b331
CD		 4069 else {
4070 qla2x00_set_reserved_loop_ids(ha);
4071 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4072 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4073 }
4074
e4e3a2ce
QT		 4075 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4076 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4077 if (!ha->sfp_data) {
4078 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4079 "Unable to allocate memory for SFP read-data.\n");
4080 goto fail_sfp_data;
4081 }
4082
b2a72ec3 4083 return 0;
e315cd28 4084
e4e3a2ce
QT		 4085fail_sfp_data:
4086 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4087fail_loop_id_map:
4088 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4089fail_async_pd:
4090 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4091fail_ex_init_cb:
4092 kfree(ha->npiv_info);
73208dfd
AC		 4093fail_npiv_info:
4094 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4095 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4096 (*rsp)->ring = NULL;
4097 (*rsp)->dma = 0;
e315cd28 4098fail_rsp_ring:
73208dfd 4099 kfree(*rsp);
a5082923 4100 *rsp = NULL;
e315cd28 4101fail_rsp:
73208dfd
AC		 4102 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4103 sizeof(request_t), (*req)->ring, (*req)->dma);
4104 (*req)->ring = NULL;
4105 (*req)->dma = 0;
e315cd28 4106fail_req_ring:
73208dfd 4107 kfree(*req);
a5082923 4108 *req = NULL;
e315cd28
AC		 4109fail_req:
4110 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4111 ha->ct_sns, ha->ct_sns_dma);
4112 ha->ct_sns = NULL;
4113 ha->ct_sns_dma = 0;
e8711085
AV		 4114fail_free_ms_iocb:
4115 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4116 ha->ms_iocb = NULL;
4117 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4118
4119 if (ha->sns_cmd)
4120 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4121 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4122fail_dma_pool:
bad75002 4123 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4124 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4125 ha->fcp_cmnd_dma_pool = NULL;
4126 }
4127fail_dl_dma_pool:
bad75002 4128 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4129 dma_pool_destroy(ha->dl_dma_pool);
4130 ha->dl_dma_pool = NULL;
4131 }
4132fail_s_dma_pool:
e315cd28
AC		 4133 dma_pool_destroy(ha->s_dma_pool);
4134 ha->s_dma_pool = NULL;
e8711085
AV		 4135fail_free_nvram:
4136 kfree(ha->nvram);
4137 ha->nvram = NULL;
a9083016 4138fail_free_ctx_mempool:
fc1ffd6c
QT		 4139 if (ha->ctx_mempool)
4140 mempool_destroy(ha->ctx_mempool);
a9083016 4141 ha->ctx_mempool = NULL;
e8711085 4142fail_free_srb_mempool:
fc1ffd6c
QT		 4143 if (ha->srb_mempool)
4144 mempool_destroy(ha->srb_mempool);
e8711085 4145 ha->srb_mempool = NULL;
e8711085 4146fail_free_gid_list:
642ef983
CD		 4147 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4148 ha->gid_list,
e315cd28 4149 ha->gid_list_dma);
e8711085
AV		 4150 ha->gid_list = NULL;
4151 ha->gid_list_dma = 0;
2d70c103
NB		 4152fail_free_tgt_mem:
4153 qlt_mem_free(ha);
e315cd28
AC		 4154fail_free_init_cb:
4155 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4156 ha->init_cb_dma);
4157 ha->init_cb = NULL;
4158 ha->init_cb_dma = 0;
e8711085 4159fail:
7c3df132
SK		 4160 ql_log(ql_log_fatal, NULL, 0x0030,
4161 "Memory allocation failure.\n");
e8711085 4162 return -ENOMEM;
1da177e4
LT		 4163}
4164
b0d6cabd
HM		 4165int
4166qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4167{
4168 int rval;
4169 uint16_t size, max_cnt, temp;
4170 struct qla_hw_data *ha = vha->hw;
4171
4172 /* Return if we don't need to alloacate any extended logins */
4173 if (!ql2xexlogins)
4174 return QLA_SUCCESS;
4175
99e1b683
QT		 4176 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4177 return QLA_SUCCESS;
4178
b0d6cabd
HM		 4179 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4180 max_cnt = 0;
4181 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4182 if (rval != QLA_SUCCESS) {
4183 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4184 "Failed to get exlogin status.\n");
4185 return rval;
4186 }
4187
4188 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4189 temp *= size;
4190
4191 if (temp != ha->exlogin_size) {
4192 qla2x00_free_exlogin_buffer(ha);
4193 ha->exlogin_size = temp;
4194
4195 ql_log(ql_log_info, vha, 0xd024,
4196 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4197 max_cnt, size, temp);
4198
4199 ql_log(ql_log_info, vha, 0xd025,
4200 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4201
4202 /* Get consistent memory for extended logins */
4203 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4204 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4205 if (!ha->exlogin_buf) {
4206 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4207 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4208 return -ENOMEM;
4209 }
b0d6cabd
HM		 4210 }
4211
4212 /* Now configure the dma buffer */
4213 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4214 if (rval) {
83548fe2 4215 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4216 "Setup extended login buffer ****FAILED****.\n");
4217 qla2x00_free_exlogin_buffer(ha);
4218 }
4219
4220 return rval;
4221}
4222
4223/*
4224* qla2x00_free_exlogin_buffer
4225*
4226* Input:
4227* ha = adapter block pointer
4228*/
4229void
4230qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4231{
4232 if (ha->exlogin_buf) {
4233 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4234 ha->exlogin_buf, ha->exlogin_buf_dma);
4235 ha->exlogin_buf = NULL;
4236 ha->exlogin_size = 0;
4237 }
4238}
4239
99e1b683
QT		 4240static void
4241qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4242{
4243 u32 temp;
4244 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4245
4246 if (qla_ini_mode_enabled(vha)) {
4247 if (ql2xiniexchg > max_cnt)
4248 ql2xiniexchg = max_cnt;
4249
4250 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4251 *ret_cnt = ql2xiniexchg;
4252 } else if (qla_tgt_mode_enabled(vha)) {
4253 if (ql2xexchoffld > max_cnt)
4254 ql2xexchoffld = max_cnt;
4255
4256 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4257 *ret_cnt = ql2xexchoffld;
4258 } else if (qla_dual_mode_enabled(vha)) {
4259 temp = ql2xiniexchg + ql2xexchoffld;
4260 if (temp > max_cnt) {
4261 ql2xiniexchg -= (temp - max_cnt)/2;
4262 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4263 temp = max_cnt;
4264 }
4265
4266 if (temp > FW_DEF_EXCHANGES_CNT)
4267 *ret_cnt = temp;
4268 }
4269}
4270
2f56a7f1
HM		 4271int
4272qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4273{
4274 int rval;
99e1b683
QT		 4275 u16 size, max_cnt;
4276 u32 temp;
2f56a7f1
HM		 4277 struct qla_hw_data *ha = vha->hw;
4278
99e1b683
QT		 4279 if (!ha->flags.exchoffld_enabled)
4280 return QLA_SUCCESS;
4281
4282 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4283 return QLA_SUCCESS;
4284
2f56a7f1
HM		 4285 max_cnt = 0;
4286 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4287 if (rval != QLA_SUCCESS) {
4288 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4289 "Failed to get exlogin status.\n");
4290 return rval;
4291 }
4292
99e1b683
QT		 4293 qla2x00_number_of_exch(vha, &temp, max_cnt);
4294 temp *= size;
2f56a7f1 4295
99e1b683
QT		 4296 if (temp != ha->exchoffld_size) {
4297 qla2x00_free_exchoffld_buffer(ha);
4298 ha->exchoffld_size = temp;
4299
4300 ql_log(ql_log_info, vha, 0xd016,
4301 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4302 max_cnt, size, temp);
4303
4304 ql_log(ql_log_info, vha, 0xd017,
4305 "Exchange Buffers requested size = 0x%x\n",
4306 ha->exchoffld_size);
4307
4308 /* Get consistent memory for extended logins */
4309 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4310 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4311 if (!ha->exchoffld_buf) {
4312 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4313 "Failed to allocate memory for exchoffld_buf_dma.\n");
4314 return -ENOMEM;
4315 }
2f56a7f1
HM		 4316 }
4317
4318 /* Now configure the dma buffer */
99e1b683 4319 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4320 if (rval) {
4321 ql_log(ql_log_fatal, vha, 0xd02e,
4322 "Setup exchange offload buffer ****FAILED****.\n");
4323 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4324 } else {
4325 /* re-adjust number of target exchange */
4326 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4327
4328 if (qla_ini_mode_enabled(vha))
4329 icb->exchange_count = 0;
4330 else
4331 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4332 }
4333
4334 return rval;
4335}
4336
4337/*
4338* qla2x00_free_exchoffld_buffer
4339*
4340* Input:
4341* ha = adapter block pointer
4342*/
4343void
4344qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4345{
4346 if (ha->exchoffld_buf) {
4347 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4348 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4349 ha->exchoffld_buf = NULL;
4350 ha->exchoffld_size = 0;
4351 }
4352}
4353
1da177e4 4354/*
e30d1756
MI		 4355* qla2x00_free_fw_dump
4356* Frees fw dump stuff.
1da177e4
LT		 4357*
4358* Input:
7ec0effd 4359* ha = adapter block pointer
1da177e4 4360*/
a824ebb3 4361static void
e30d1756 4362qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4363{
df613b96 4364 if (ha->fce)
f73cb695
CD		 4365 dma_free_coherent(&ha->pdev->dev,
4366 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4367
f73cb695
CD		 4368 if (ha->eft)
4369 dma_free_coherent(&ha->pdev->dev,
4370 EFT_SIZE, ha->eft, ha->eft_dma);
4371
4372 if (ha->fw_dump)
a7a167bf 4373 vfree(ha->fw_dump);
f73cb695
CD		 4374 if (ha->fw_dump_template)
4375 vfree(ha->fw_dump_template);
4376
e30d1756
MI		 4377 ha->fce = NULL;
4378 ha->fce_dma = 0;
4379 ha->eft = NULL;
4380 ha->eft_dma = 0;
e30d1756 4381 ha->fw_dumped = 0;
61f098dd 4382 ha->fw_dump_cap_flags = 0;
e30d1756 4383 ha->fw_dump_reading = 0;
f73cb695
CD		 4384 ha->fw_dump = NULL;
4385 ha->fw_dump_len = 0;
4386 ha->fw_dump_template = NULL;
4387 ha->fw_dump_template_len = 0;
e30d1756
MI		 4388}
4389
4390/*
4391* qla2x00_mem_free
4392* Frees all adapter allocated memory.
4393*
4394* Input:
4395* ha = adapter block pointer.
4396*/
4397static void
4398qla2x00_mem_free(struct qla_hw_data *ha)
4399{
4400 qla2x00_free_fw_dump(ha);
4401
81178772
SK		 4402 if (ha->mctp_dump)
4403 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4404 ha->mctp_dump_dma);
4405
e30d1756
MI		 4406 if (ha->srb_mempool)
4407 mempool_destroy(ha->srb_mempool);
a7a167bf 4408
11bbc1d8
AV		 4409 if (ha->dcbx_tlv)
4410 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4411 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4412
ce0423f4
AV		 4413 if (ha->xgmac_data)
4414 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4415 ha->xgmac_data, ha->xgmac_data_dma);
4416
1da177e4
LT		 4417 if (ha->sns_cmd)
4418 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4419 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4420
4421 if (ha->ct_sns)
4422 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4423 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4424
88729e53 4425 if (ha->sfp_data)
e4e3a2ce
QT		 4426 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4427 ha->sfp_data_dma);
88729e53 4428
1da177e4
LT		 4429 if (ha->ms_iocb)
4430 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4431
b64b0e8f 4432 if (ha->ex_init_cb)
a9083016
GM		 4433 dma_pool_free(ha->s_dma_pool,
4434 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4435
5ff1d584
AV		 4436 if (ha->async_pd)
4437 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4438
1da177e4
LT		 4439 if (ha->s_dma_pool)
4440 dma_pool_destroy(ha->s_dma_pool);
4441
1da177e4 4442 if (ha->gid_list)
642ef983
CD		 4443 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4444 ha->gid_list, ha->gid_list_dma);
1da177e4 4445
a9083016
GM		 4446 if (IS_QLA82XX(ha)) {
4447 if (!list_empty(&ha->gbl_dsd_list)) {
4448 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4449
4450 /* clean up allocated prev pool */
4451 list_for_each_entry_safe(dsd_ptr,
4452 tdsd_ptr, &ha->gbl_dsd_list, list) {
4453 dma_pool_free(ha->dl_dma_pool,
4454 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4455 list_del(&dsd_ptr->list);
4456 kfree(dsd_ptr);
4457 }
4458 }
4459 }
4460
4461 if (ha->dl_dma_pool)
4462 dma_pool_destroy(ha->dl_dma_pool);
4463
4464 if (ha->fcp_cmnd_dma_pool)
4465 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4466
4467 if (ha->ctx_mempool)
4468 mempool_destroy(ha->ctx_mempool);
4469
2d70c103
NB		 4470 qlt_mem_free(ha);
4471
e315cd28
AC		 4472 if (ha->init_cb)
4473 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4474 ha->init_cb, ha->init_cb_dma);
79c67fb6 4475
a5082923
BK		 4476 vfree(ha->optrom_buffer);
4477 kfree(ha->nvram);
4478 kfree(ha->npiv_info);
4479 kfree(ha->swl);
4480 kfree(ha->loop_id_map);
1da177e4 4481
e8711085 4482 ha->srb_mempool = NULL;
a9083016 4483 ha->ctx_mempool = NULL;
1da177e4
LT		 4484 ha->sns_cmd = NULL;
4485 ha->sns_cmd_dma = 0;
4486 ha->ct_sns = NULL;
4487 ha->ct_sns_dma = 0;
4488 ha->ms_iocb = NULL;
4489 ha->ms_iocb_dma = 0;
1da177e4
LT		 4490 ha->init_cb = NULL;
4491 ha->init_cb_dma = 0;
b64b0e8f
AV		 4492 ha->ex_init_cb = NULL;
4493 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4494 ha->async_pd = NULL;
4495 ha->async_pd_dma = 0;
79c67fb6
BK		 4496 ha->loop_id_map = NULL;
4497 ha->npiv_info = NULL;
4498 ha->optrom_buffer = NULL;
4499 ha->swl = NULL;
4500 ha->nvram = NULL;
4501 ha->mctp_dump = NULL;
4502 ha->dcbx_tlv = NULL;
4503 ha->xgmac_data = NULL;
4504 ha->sfp_data = NULL;
1da177e4
LT		 4505
4506 ha->s_dma_pool = NULL;
a9083016
GM		 4507 ha->dl_dma_pool = NULL;
4508 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4509
1da177e4
LT		 4510 ha->gid_list = NULL;
4511 ha->gid_list_dma = 0;
2d70c103
NB		 4512
4513 ha->tgt.atio_ring = NULL;
4514 ha->tgt.atio_dma = 0;
4515 ha->tgt.tgt_vp_map = NULL;
e315cd28 4516}
1da177e4 4517
e315cd28
AC		 4518struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4519 struct qla_hw_data *ha)
4520{
4521 struct Scsi_Host *host;
4522 struct scsi_qla_host *vha = NULL;
854165f4 4523
e315cd28 4524 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4525 if (!host) {
7c3df132
SK		 4526 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4527 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4528 return NULL;
e315cd28
AC		 4529 }
4530
4531 /* Clear our data area */
4532 vha = shost_priv(host);
4533 memset(vha, 0, sizeof(scsi_qla_host_t));
4534
4535 vha->host = host;
4536 vha->host_no = host->host_no;
4537 vha->hw = ha;
4538
4539 INIT_LIST_HEAD(&vha->vp_fcports);
4540 INIT_LIST_HEAD(&vha->work_list);
4541 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4542 INIT_LIST_HEAD(&vha->qla_cmd_list);
4543 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4544 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4545 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4546 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4547 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4548 INIT_LIST_HEAD(&vha->nvme_rport_list);
f7b6ee5f 4549 INIT_LIST_HEAD(&vha->gpnid_list);
e315cd28 4550
f999f4c1 4551 spin_lock_init(&vha->work_lock);
8b2f5ff3 4552 spin_lock_init(&vha->cmd_list_lock);
31fdcce1 4553 spin_lock_init(&vha->gnl.fcports_lock);
726b8548 4554 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4555 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4556
2fdbc65e
BVA		 4557 vha->gnl.size = sizeof(struct get_name_list_extended) *
4558 (ha->max_loop_id + 1);
41dc529a
QT		 4559 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4560 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4561 if (!vha->gnl.l) {
83548fe2 4562 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4563 "Alloc failed for name list.\n");
4564 scsi_remove_host(vha->host);
4565 return NULL;
4566 }
f999f4c1 4567
e315cd28 4568 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4569 ql_dbg(ql_dbg_init, vha, 0x0041,
4570 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4571 vha->host, vha->hw, vha,
4572 dev_name(&(ha->pdev->dev)));
4573
e315cd28 4574 return vha;
1da177e4
LT		 4575}
4576
726b8548 4577struct qla_work_evt *
f999f4c1 4578qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4579{
4580 struct qla_work_evt *e;
feafb7b1
AE		 4581 uint8_t bail;
4582
4583 QLA_VHA_MARK_BUSY(vha, bail);
4584 if (bail)
4585 return NULL;
0971de7f 4586
f999f4c1 4587 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4588 if (!e) {
4589 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4590 return NULL;
feafb7b1 4591 }
0971de7f
AV		 4592
4593 INIT_LIST_HEAD(&e->list);
4594 e->type = type;
4595 e->flags = QLA_EVT_FLAG_FREE;
4596 return e;
4597}
4598
726b8548 4599int
f999f4c1 4600qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4601{
f999f4c1 4602 unsigned long flags;
0971de7f 4603
f999f4c1 4604 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4605 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4606 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4607
4608 if (QLA_EARLY_LINKUP(vha->hw))
4609 schedule_work(&vha->iocb_work);
4610 else
4611 qla2xxx_wake_dpc(vha);
f999f4c1 4612
0971de7f
AV		 4613 return QLA_SUCCESS;
4614}
4615
4616int
e315cd28 4617qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4618 u32 data)
4619{
4620 struct qla_work_evt *e;
4621
f999f4c1 4622 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4623 if (!e)
4624 return QLA_FUNCTION_FAILED;
4625
4626 e->u.aen.code = code;
4627 e->u.aen.data = data;
f999f4c1 4628 return qla2x00_post_work(vha, e);
0971de7f
AV		 4629}
4630
8a659571
AV		 4631int
4632qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4633{
4634 struct qla_work_evt *e;
4635
f999f4c1 4636 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4637 if (!e)
4638 return QLA_FUNCTION_FAILED;
4639
4640 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4641 return qla2x00_post_work(vha, e);
8a659571
AV		 4642}
4643
ac280b67
AV		 4644#define qla2x00_post_async_work(name, type) \
4645int qla2x00_post_async_##name##_work( \
4646 struct scsi_qla_host *vha, \
4647 fc_port_t *fcport, uint16_t *data) \
4648{ \
4649 struct qla_work_evt *e; \
4650 \
4651 e = qla2x00_alloc_work(vha, type); \
4652 if (!e) \
4653 return QLA_FUNCTION_FAILED; \
4654 \
4655 e->u.logio.fcport = fcport; \
4656 if (data) { \
4657 e->u.logio.data[0] = data[0]; \
4658 e->u.logio.data[1] = data[1]; \
4659 } \
bbe045a9 4660 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4661 return qla2x00_post_work(vha, e); \
4662}
4663
4664qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4665qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4666qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4667qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4668qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4669
3420d36c
AV		 4670int
4671qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4672{
4673 struct qla_work_evt *e;
4674
4675 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4676 if (!e)
4677 return QLA_FUNCTION_FAILED;
4678
4679 e->u.uevent.code = code;
4680 return qla2x00_post_work(vha, e);
4681}
4682
4683static void
4684qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4685{
4686 char event_string[40];
4687 char *envp[] = { event_string, NULL };
4688
4689 switch (code) {
4690 case QLA_UEVENT_CODE_FW_DUMP:
4691 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4692 vha->host_no);
4693 break;
4694 default:
4695 /* do nothing */
4696 break;
4697 }
4698 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4699}
4700
8ae6d9c7
GM		 4701int
4702qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4703 uint32_t *data, int cnt)
4704{
4705 struct qla_work_evt *e;
4706
4707 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4708 if (!e)
4709 return QLA_FUNCTION_FAILED;
4710
4711 e->u.aenfx.evtcode = evtcode;
4712 e->u.aenfx.count = cnt;
4713 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4714 return qla2x00_post_work(vha, e);
4715}
4716
726b8548
QT		 4717int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4718{
4719 struct qla_work_evt *e;
4720
4721 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4722 if (!e)
4723 return QLA_FUNCTION_FAILED;
4724
4725 e->u.fcport.fcport = fcport;
4726 return qla2x00_post_work(vha, e);
4727}
4728
4729static
4730void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4731{
4732 unsigned long flags;
b5d15312 4733 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4734 struct qlt_plogi_ack_t *pla =
4735 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4736 uint8_t free_fcport = 0;
726b8548 4737
ca3dad22
QT		 4738 ql_dbg(ql_dbg_disc, vha, 0xffff,
4739 "%s %d %8phC enter\n",
4740 __func__, __LINE__, e->u.new_sess.port_name);
4741
726b8548
QT		 4742 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4743 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4744 if (fcport) {
4745 fcport->d_id = e->u.new_sess.id;
4746 if (pla) {
4747 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4748 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4749 /* we took an extra ref_count to prevent PLOGI ACK when
4750 * fcport/sess has not been created.
4751 */
4752 pla->ref_count--;
4753 }
4754 } else {
b5d15312 4755 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4756 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4757 if (fcport) {
4758 fcport->d_id = e->u.new_sess.id;
4759 fcport->scan_state = QLA_FCPORT_FOUND;
4760 fcport->flags |= FCF_FABRIC_DEVICE;
4761 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4762
4763 memcpy(fcport->port_name, e->u.new_sess.port_name,
4764 WWN_SIZE);
b5d15312
QT		 4765 } else {
4766 ql_dbg(ql_dbg_disc, vha, 0xffff,
4767 "%s %8phC mem alloc fail.\n",
4768 __func__, e->u.new_sess.port_name);
4769
4770 if (pla)
4771 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4772 return;
4773 }
4774
4775 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4776 /* search again to make sure one else got ahead */
4777 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4778 e->u.new_sess.port_name, 1);
4779 if (tfcp) {
4780 /* should rarily happen */
4781 ql_dbg(ql_dbg_disc, vha, 0xffff,
4782 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4783 __func__, tfcp->port_name, tfcp->disc_state,
4784 tfcp->fw_login_state);
4785
4786 free_fcport = 1;
4787 } else {
726b8548
QT		 4788 list_add_tail(&fcport->list, &vha->vp_fcports);
4789
adce30f1
QT		 4790 }
4791 if (pla) {
4792 qlt_plogi_ack_link(vha, pla, fcport,
4793 QLT_PLOGI_LINK_SAME_WWN);
4794 pla->ref_count--;
726b8548
QT		 4795 }
4796 }
4797 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4798
4799 if (fcport) {
ca3dad22
QT		 4800 if (N2N_TOPO(vha->hw))
4801 fcport->flags &= ~FCF_FABRIC_DEVICE;
4802
49ef16f4 4803 if (pla) {
ca3dad22
QT		 4804 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
4805 u16 wd3_lo;
4806
4807 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4808 fcport->local = 0;
4809 fcport->loop_id =
4810 le16_to_cpu(
4811 pla->iocb.u.isp24.nport_handle);
4812 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4813 wd3_lo =
4814 le16_to_cpu(
4815 pla->iocb.u.isp24.u.prli.wd3_lo);
4816
4817 if (wd3_lo & BIT_7)
4818 fcport->conf_compl_supported = 1;
4819
4820 if ((wd3_lo & BIT_4) == 0)
4821 fcport->port_type = FCT_INITIATOR;
4822 else
4823 fcport->port_type = FCT_TARGET;
4824 }
726b8548 4825 qlt_plogi_ack_unref(vha, pla);
49ef16f4 4826 } else {
31fdcce1
HR		 4827 fc_port_t *dfcp = NULL;
4828
49ef16f4
QT		 4829 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4830 tfcp = qla2x00_find_fcport_by_nportid(vha,
4831 &e->u.new_sess.id, 1);
4832 if (tfcp && (tfcp != fcport)) {
4833 /*
4834 * We have a conflict fcport with same NportID.
4835 */
4836 ql_dbg(ql_dbg_disc, vha, 0xffff,
4837 "%s %8phC found conflict b4 add. DS %d LS %d\n",
4838 __func__, tfcp->port_name, tfcp->disc_state,
4839 tfcp->fw_login_state);
4840
4841 switch (tfcp->disc_state) {
4842 case DSC_DELETED:
4843 break;
4844 case DSC_DELETE_PEND:
4845 fcport->login_pause = 1;
4846 tfcp->conflict = fcport;
4847 break;
4848 default:
4849 fcport->login_pause = 1;
4850 tfcp->conflict = fcport;
31fdcce1 4851 dfcp = tfcp;
49ef16f4
QT		 4852 break;
4853 }
4854 }
4855 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
31fdcce1
HR		 4856 if (dfcp)
4857 qlt_schedule_sess_for_deletion(tfcp);
4858
49ef16f4
QT		 4859 qla24xx_async_gnl(vha, fcport);
4860 }
726b8548 4861 }
b5d15312
QT		 4862
4863 if (free_fcport) {
4864 qla2x00_free_fcport(fcport);
4865 if (pla)
4866 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4867 }
726b8548
QT		 4868}
4869
ac280b67 4870void
e315cd28 4871qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4872{
f999f4c1
AV		 4873 struct qla_work_evt *e, *tmp;
4874 unsigned long flags;
4875 LIST_HEAD(work);
0971de7f 4876
f999f4c1
AV		 4877 spin_lock_irqsave(&vha->work_lock, flags);
4878 list_splice_init(&vha->work_list, &work);
4879 spin_unlock_irqrestore(&vha->work_lock, flags);
4880
4881 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4882 list_del_init(&e->list);
0971de7f
AV		 4883
4884 switch (e->type) {
4885 case QLA_EVT_AEN:
e315cd28 4886 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4887 e->u.aen.code, e->u.aen.data);
4888 break;
8a659571
AV		 4889 case QLA_EVT_IDC_ACK:
4890 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4891 break;
ac280b67
AV		 4892 case QLA_EVT_ASYNC_LOGIN:
4893 qla2x00_async_login(vha, e->u.logio.fcport,
4894 e->u.logio.data);
4895 break;
ac280b67
AV		 4896 case QLA_EVT_ASYNC_LOGOUT:
4897 qla2x00_async_logout(vha, e->u.logio.fcport);
4898 break;
4899 case QLA_EVT_ASYNC_LOGOUT_DONE:
4900 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4901 e->u.logio.data);
4902 break;
5ff1d584
AV		 4903 case QLA_EVT_ASYNC_ADISC:
4904 qla2x00_async_adisc(vha, e->u.logio.fcport,
4905 e->u.logio.data);
4906 break;
4907 case QLA_EVT_ASYNC_ADISC_DONE:
4908 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4909 e->u.logio.data);
4910 break;
3420d36c
AV		 4911 case QLA_EVT_UEVENT:
4912 qla2x00_uevent_emit(vha, e->u.uevent.code);
4913 break;
8ae6d9c7
GM		 4914 case QLA_EVT_AENFX:
4915 qlafx00_process_aen(vha, e);
4916 break;
726b8548
QT		 4917 case QLA_EVT_GIDPN:
4918 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4919 break;
4920 case QLA_EVT_GPNID:
4921 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4922 break;
4923 case QLA_EVT_GPNID_DONE:
4924 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4925 break;
4926 case QLA_EVT_NEW_SESS:
4927 qla24xx_create_new_sess(vha, e);
4928 break;
4929 case QLA_EVT_GPDB:
4930 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4931 e->u.fcport.opt);
4932 break;
a5d42f4c
DG		 4933 case QLA_EVT_PRLI:
4934 qla24xx_async_prli(vha, e->u.fcport.fcport);
4935 break;
726b8548
QT		 4936 case QLA_EVT_GPSC:
4937 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4938 break;
4939 case QLA_EVT_UPD_FCPORT:
4940 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4941 break;
4942 case QLA_EVT_GNL:
4943 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4944 break;
4945 case QLA_EVT_NACK:
4946 qla24xx_do_nack_work(vha, e);
4947 break;
0971de7f
AV		 4948 }
4949 if (e->flags & QLA_EVT_FLAG_FREE)
4950 kfree(e);
feafb7b1
AE		 4951
4952 /* For each work completed decrement vha ref count */
4953 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4954 }
e315cd28 4955}
f999f4c1 4956
e315cd28
AC		 4957/* Relogins all the fcports of a vport
4958 * Context: dpc thread
4959 */
4960void qla2x00_relogin(struct scsi_qla_host *vha)
4961{
4962 fc_port_t *fcport;
c6b2fca8 4963 int status;
726b8548 4964 struct event_arg ea;
e315cd28
AC		 4965
4966 list_for_each_entry(fcport, &vha->vp_fcports, list) {
ca3dad22
QT		 4967 /*
4968 * If the port is not ONLINE then try to login
4969 * to it if we haven't run out of retries.
4970 */
5ff1d584 4971 if (atomic_read(&fcport->state) != FCS_ONLINE &&
bbe045a9
QT		 4972 fcport->login_retry &&
4973 !(fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE))) {
ca3dad22 4974 if (vha->hw->current_topology != ISP_CFG_NL) {
83548fe2 4975 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4976 "%s %8phC DS %d LS %d\n", __func__,
4977 fcport->port_name, fcport->disc_state,
4978 fcport->fw_login_state);
4979 memset(&ea, 0, sizeof(ea));
4980 ea.event = FCME_RELOGIN;
4981 ea.fcport = fcport;
4982 qla2x00_fcport_event_handler(vha, &ea);
ca3dad22 4983 } else if (vha->hw->current_topology == ISP_CFG_NL) {
5118a256 4984 fcport->login_retry--;
e315cd28
AC		 4985 status = qla2x00_local_device_login(vha,
4986 fcport);
726b8548
QT		 4987 if (status == QLA_SUCCESS) {
4988 fcport->old_loop_id = fcport->loop_id;
4989 ql_dbg(ql_dbg_disc, vha, 0x2003,
4990 "Port login OK: logged in ID 0x%x.\n",
4991 fcport->loop_id);
4992 qla2x00_update_fcport(vha, fcport);
4993 } else if (status == 1) {
4994 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4995 /* retry the login again */
4996 ql_dbg(ql_dbg_disc, vha, 0x2007,
4997 "Retrying %d login again loop_id 0x%x.\n",
4998 fcport->login_retry,
4999 fcport->loop_id);
5000 } else {
5001 fcport->login_retry = 0;
5002 }
e315cd28 5003
726b8548
QT		 5004 if (fcport->login_retry == 0 &&
5005 status != QLA_SUCCESS)
5006 qla2x00_clear_loop_id(fcport);
e315cd28 5007 }
e315cd28
AC		 5008 }
5009 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5010 break;
0971de7f 5011 }
0971de7f
AV		 5012}
5013
7d613ac6
SV		 5014/* Schedule work on any of the dpc-workqueues */
5015void
5016qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5017{
5018 struct qla_hw_data *ha = base_vha->hw;
5019
5020 switch (work_code) {
5021 case MBA_IDC_AEN: /* 0x8200 */
5022 if (ha->dpc_lp_wq)
5023 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5024 break;
5025
5026 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5027 if (!ha->flags.nic_core_reset_hdlr_active) {
5028 if (ha->dpc_hp_wq)
5029 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5030 } else
5031 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5032 "NIC Core reset is already active. Skip "
5033 "scheduling it again.\n");
5034 break;
5035 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5036 if (ha->dpc_hp_wq)
5037 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5038 break;
5039 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5040 if (ha->dpc_hp_wq)
5041 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5042 break;
5043 default:
5044 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5045 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5046 }
5047
5048 return;
5049}
5050
5051/* Work: Perform NIC Core Unrecoverable state handling */
5052void
5053qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5054{
5055 struct qla_hw_data *ha =
2ad1b67c 5056 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5057 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5058 uint32_t dev_state = 0;
5059
5060 qla83xx_idc_lock(base_vha, 0);
5061 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5062 qla83xx_reset_ownership(base_vha);
5063 if (ha->flags.nic_core_reset_owner) {
5064 ha->flags.nic_core_reset_owner = 0;
5065 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5066 QLA8XXX_DEV_FAILED);
5067 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5068 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5069 }
5070 qla83xx_idc_unlock(base_vha, 0);
5071}
5072
5073/* Work: Execute IDC state handler */
5074void
5075qla83xx_idc_state_handler_work(struct work_struct *work)
5076{
5077 struct qla_hw_data *ha =
2ad1b67c 5078 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5079 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5080 uint32_t dev_state = 0;
5081
5082 qla83xx_idc_lock(base_vha, 0);
5083 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5084 if (dev_state == QLA8XXX_DEV_FAILED ||
5085 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5086 qla83xx_idc_state_handler(base_vha);
5087 qla83xx_idc_unlock(base_vha, 0);
5088}
5089
fa492630 5090static int
7d613ac6
SV		 5091qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5092{
5093 int rval = QLA_SUCCESS;
5094 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5095 uint32_t heart_beat_counter1, heart_beat_counter2;
5096
5097 do {
5098 if (time_after(jiffies, heart_beat_wait)) {
5099 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5100 "Nic Core f/w is not alive.\n");
5101 rval = QLA_FUNCTION_FAILED;
5102 break;
5103 }
5104
5105 qla83xx_idc_lock(base_vha, 0);
5106 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5107 &heart_beat_counter1);
5108 qla83xx_idc_unlock(base_vha, 0);
5109 msleep(100);
5110 qla83xx_idc_lock(base_vha, 0);
5111 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5112 &heart_beat_counter2);
5113 qla83xx_idc_unlock(base_vha, 0);
5114 } while (heart_beat_counter1 == heart_beat_counter2);
5115
5116 return rval;
5117}
5118
5119/* Work: Perform NIC Core Reset handling */
5120void
5121qla83xx_nic_core_reset_work(struct work_struct *work)
5122{
5123 struct qla_hw_data *ha =
5124 container_of(work, struct qla_hw_data, nic_core_reset);
5125 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5126 uint32_t dev_state = 0;
5127
81178772
SK		 5128 if (IS_QLA2031(ha)) {
5129 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5130 ql_log(ql_log_warn, base_vha, 0xb081,
5131 "Failed to dump mctp\n");
5132 return;
5133 }
5134
7d613ac6
SV		 5135 if (!ha->flags.nic_core_reset_hdlr_active) {
5136 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5137 qla83xx_idc_lock(base_vha, 0);
5138 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5139 &dev_state);
5140 qla83xx_idc_unlock(base_vha, 0);
5141 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5142 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5143 "Nic Core f/w is alive.\n");
5144 return;
5145 }
5146 }
5147
5148 ha->flags.nic_core_reset_hdlr_active = 1;
5149 if (qla83xx_nic_core_reset(base_vha)) {
5150 /* NIC Core reset failed. */
5151 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5152 "NIC Core reset failed.\n");
5153 }
5154 ha->flags.nic_core_reset_hdlr_active = 0;
5155 }
5156}
5157
5158/* Work: Handle 8200 IDC aens */
5159void
5160qla83xx_service_idc_aen(struct work_struct *work)
5161{
5162 struct qla_hw_data *ha =
5163 container_of(work, struct qla_hw_data, idc_aen);
5164 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5165 uint32_t dev_state, idc_control;
5166
5167 qla83xx_idc_lock(base_vha, 0);
5168 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5169 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5170 qla83xx_idc_unlock(base_vha, 0);
5171 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5172 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5173 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5174 "Application requested NIC Core Reset.\n");
5175 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5176 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5177 QLA_SUCCESS) {
5178 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5179 "Other protocol driver requested NIC Core Reset.\n");
5180 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5181 }
5182 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5183 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5184 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5185 }
5186}
5187
5188static void
5189qla83xx_wait_logic(void)
5190{
5191 int i;
5192
5193 /* Yield CPU */
5194 if (!in_interrupt()) {
5195 /*
5196 * Wait about 200ms before retrying again.
5197 * This controls the number of retries for single
5198 * lock operation.
5199 */
5200 msleep(100);
5201 schedule();
5202 } else {
5203 for (i = 0; i < 20; i++)
5204 cpu_relax(); /* This a nop instr on i386 */
5205 }
5206}
5207
fa492630 5208static int
7d613ac6
SV		 5209qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5210{
5211 int rval;
5212 uint32_t data;
5213 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5214 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5215 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5216 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5217 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5218
5219 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5220 if (rval)
5221 return rval;
5222
5223 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5224 return QLA_SUCCESS;
5225 } else {
5226 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5227 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5228 data);
5229 if (rval)
5230 return rval;
5231
5232 msleep(200);
5233
5234 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5235 &data);
5236 if (rval)
5237 return rval;
5238
5239 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5240 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5241 ~(idc_lck_rcvry_stage_mask));
5242 rval = qla83xx_wr_reg(base_vha,
5243 QLA83XX_IDC_LOCK_RECOVERY, data);
5244 if (rval)
5245 return rval;
5246
5247 /* Forcefully perform IDC UnLock */
5248 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5249 &data);
5250 if (rval)
5251 return rval;
5252 /* Clear lock-id by setting 0xff */
5253 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5254 0xff);
5255 if (rval)
5256 return rval;
5257 /* Clear lock-recovery by setting 0x0 */
5258 rval = qla83xx_wr_reg(base_vha,
5259 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5260 if (rval)
5261 return rval;
5262 } else
5263 return QLA_SUCCESS;
5264 }
5265
5266 return rval;
5267}
5268
fa492630 5269static int
7d613ac6
SV		 5270qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5271{
5272 int rval = QLA_SUCCESS;
5273 uint32_t o_drv_lockid, n_drv_lockid;
5274 unsigned long lock_recovery_timeout;
5275
5276 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5277retry_lockid:
5278 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5279 if (rval)
5280 goto exit;
5281
5282 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5283 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5284 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5285 return QLA_SUCCESS;
5286 else
5287 return QLA_FUNCTION_FAILED;
5288 }
5289
5290 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5291 if (rval)
5292 goto exit;
5293
5294 if (o_drv_lockid == n_drv_lockid) {
5295 qla83xx_wait_logic();
5296 goto retry_lockid;
5297 } else
5298 return QLA_SUCCESS;
5299
5300exit:
5301 return rval;
5302}
5303
5304void
5305qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5306{
5307 uint16_t options = (requester_id << 15) | BIT_6;
5308 uint32_t data;
6c315553 5309 uint32_t lock_owner;
7d613ac6
SV		 5310 struct qla_hw_data *ha = base_vha->hw;
5311
5312 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5313retry_lock:
5314 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5315 == QLA_SUCCESS) {
5316 if (data) {
5317 /* Setting lock-id to our function-number */
5318 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5319 ha->portnum);
5320 } else {
6c315553
SK		 5321 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5322 &lock_owner);
7d613ac6 5323 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5324 "Failed to acquire IDC lock, acquired by %d, "
5325 "retrying...\n", lock_owner);
7d613ac6
SV		 5326
5327 /* Retry/Perform IDC-Lock recovery */
5328 if (qla83xx_idc_lock_recovery(base_vha)
5329 == QLA_SUCCESS) {
5330 qla83xx_wait_logic();
5331 goto retry_lock;
5332 } else
5333 ql_log(ql_log_warn, base_vha, 0xb075,
5334 "IDC Lock recovery FAILED.\n");
5335 }
5336
5337 }
5338
5339 return;
5340
5341 /* XXX: IDC-lock implementation using access-control mbx */
5342retry_lock2:
5343 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5344 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5345 "Failed to acquire IDC lock. retrying...\n");
5346 /* Retry/Perform IDC-Lock recovery */
5347 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5348 qla83xx_wait_logic();
5349 goto retry_lock2;
5350 } else
5351 ql_log(ql_log_warn, base_vha, 0xb076,
5352 "IDC Lock recovery FAILED.\n");
5353 }
5354
5355 return;
5356}
5357
5358void
5359qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5360{
5897cb2f
BVA		 5361#if 0
5362 uint16_t options = (requester_id << 15) | BIT_7;
5363#endif
5364 uint16_t retry;
7d613ac6
SV		 5365 uint32_t data;
5366 struct qla_hw_data *ha = base_vha->hw;
5367
5368 /* IDC-unlock implementation using driver-unlock/lock-id
5369 * remote registers
5370 */
5371 retry = 0;
5372retry_unlock:
5373 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5374 == QLA_SUCCESS) {
5375 if (data == ha->portnum) {
5376 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5377 /* Clearing lock-id by setting 0xff */
5378 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5379 } else if (retry < 10) {
5380 /* SV: XXX: IDC unlock retrying needed here? */
5381
5382 /* Retry for IDC-unlock */
5383 qla83xx_wait_logic();
5384 retry++;
5385 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5386 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5387 goto retry_unlock;
5388 }
5389 } else if (retry < 10) {
5390 /* Retry for IDC-unlock */
5391 qla83xx_wait_logic();
5392 retry++;
5393 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5394 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5395 goto retry_unlock;
5396 }
5397
5398 return;
5399
5897cb2f 5400#if 0
7d613ac6
SV		 5401 /* XXX: IDC-unlock implementation using access-control mbx */
5402 retry = 0;
5403retry_unlock2:
5404 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5405 if (retry < 10) {
5406 /* Retry for IDC-unlock */
5407 qla83xx_wait_logic();
5408 retry++;
5409 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5410 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5411 goto retry_unlock2;
5412 }
5413 }
5414
5415 return;
5897cb2f 5416#endif
7d613ac6
SV		 5417}
5418
5419int
5420__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5421{
5422 int rval = QLA_SUCCESS;
5423 struct qla_hw_data *ha = vha->hw;
5424 uint32_t drv_presence;
5425
5426 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5427 if (rval == QLA_SUCCESS) {
5428 drv_presence |= (1 << ha->portnum);
5429 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5430 drv_presence);
5431 }
5432
5433 return rval;
5434}
5435
5436int
5437qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5438{
5439 int rval = QLA_SUCCESS;
5440
5441 qla83xx_idc_lock(vha, 0);
5442 rval = __qla83xx_set_drv_presence(vha);
5443 qla83xx_idc_unlock(vha, 0);
5444
5445 return rval;
5446}
5447
5448int
5449__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5450{
5451 int rval = QLA_SUCCESS;
5452 struct qla_hw_data *ha = vha->hw;
5453 uint32_t drv_presence;
5454
5455 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5456 if (rval == QLA_SUCCESS) {
5457 drv_presence &= ~(1 << ha->portnum);
5458 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5459 drv_presence);
5460 }
5461
5462 return rval;
5463}
5464
5465int
5466qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5467{
5468 int rval = QLA_SUCCESS;
5469
5470 qla83xx_idc_lock(vha, 0);
5471 rval = __qla83xx_clear_drv_presence(vha);
5472 qla83xx_idc_unlock(vha, 0);
5473
5474 return rval;
5475}
5476
fa492630 5477static void
7d613ac6
SV		 5478qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5479{
5480 struct qla_hw_data *ha = vha->hw;
5481 uint32_t drv_ack, drv_presence;
5482 unsigned long ack_timeout;
5483
5484 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5485 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5486 while (1) {
5487 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5488 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5489 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5490 break;
5491
5492 if (time_after_eq(jiffies, ack_timeout)) {
5493 ql_log(ql_log_warn, vha, 0xb067,
5494 "RESET ACK TIMEOUT! drv_presence=0x%x "
5495 "drv_ack=0x%x\n", drv_presence, drv_ack);
5496 /*
5497 * The function(s) which did not ack in time are forced
5498 * to withdraw any further participation in the IDC
5499 * reset.
5500 */
5501 if (drv_ack != drv_presence)
5502 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5503 drv_ack);
5504 break;
5505 }
5506
5507 qla83xx_idc_unlock(vha, 0);
5508 msleep(1000);
5509 qla83xx_idc_lock(vha, 0);
5510 }
5511
5512 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5513 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5514}
5515
fa492630 5516static int
7d613ac6
SV		 5517qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5518{
5519 int rval = QLA_SUCCESS;
5520 uint32_t idc_control;
5521
5522 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5523 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5524
5525 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5526 __qla83xx_get_idc_control(vha, &idc_control);
5527 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5528 __qla83xx_set_idc_control(vha, 0);
5529
5530 qla83xx_idc_unlock(vha, 0);
5531 rval = qla83xx_restart_nic_firmware(vha);
5532 qla83xx_idc_lock(vha, 0);
5533
5534 if (rval != QLA_SUCCESS) {
5535 ql_log(ql_log_fatal, vha, 0xb06a,
5536 "Failed to restart NIC f/w.\n");
5537 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5538 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5539 } else {
5540 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5541 "Success in restarting nic f/w.\n");
5542 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5543 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5544 }
5545
5546 return rval;
5547}
5548
5549/* Assumes idc_lock always held on entry */
5550int
5551qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5552{
5553 struct qla_hw_data *ha = base_vha->hw;
5554 int rval = QLA_SUCCESS;
5555 unsigned long dev_init_timeout;
5556 uint32_t dev_state;
5557
5558 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5559 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5560
5561 while (1) {
5562
5563 if (time_after_eq(jiffies, dev_init_timeout)) {
5564 ql_log(ql_log_warn, base_vha, 0xb06e,
5565 "Initialization TIMEOUT!\n");
5566 /* Init timeout. Disable further NIC Core
5567 * communication.
5568 */
5569 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5570 QLA8XXX_DEV_FAILED);
5571 ql_log(ql_log_info, base_vha, 0xb06f,
5572 "HW State: FAILED.\n");
5573 }
5574
5575 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5576 switch (dev_state) {
5577 case QLA8XXX_DEV_READY:
5578 if (ha->flags.nic_core_reset_owner)
5579 qla83xx_idc_audit(base_vha,
5580 IDC_AUDIT_COMPLETION);
5581 ha->flags.nic_core_reset_owner = 0;
5582 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5583 "Reset_owner reset by 0x%x.\n",
5584 ha->portnum);
5585 goto exit;
5586 case QLA8XXX_DEV_COLD:
5587 if (ha->flags.nic_core_reset_owner)
5588 rval = qla83xx_device_bootstrap(base_vha);
5589 else {
5590 /* Wait for AEN to change device-state */
5591 qla83xx_idc_unlock(base_vha, 0);
5592 msleep(1000);
5593 qla83xx_idc_lock(base_vha, 0);
5594 }
5595 break;
5596 case QLA8XXX_DEV_INITIALIZING:
5597 /* Wait for AEN to change device-state */
5598 qla83xx_idc_unlock(base_vha, 0);
5599 msleep(1000);
5600 qla83xx_idc_lock(base_vha, 0);
5601 break;
5602 case QLA8XXX_DEV_NEED_RESET:
5603 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5604 qla83xx_need_reset_handler(base_vha);
5605 else {
5606 /* Wait for AEN to change device-state */
5607 qla83xx_idc_unlock(base_vha, 0);
5608 msleep(1000);
5609 qla83xx_idc_lock(base_vha, 0);
5610 }
5611 /* reset timeout value after need reset handler */
5612 dev_init_timeout = jiffies +
5613 (ha->fcoe_dev_init_timeout * HZ);
5614 break;
5615 case QLA8XXX_DEV_NEED_QUIESCENT:
5616 /* XXX: DEBUG for now */
5617 qla83xx_idc_unlock(base_vha, 0);
5618 msleep(1000);
5619 qla83xx_idc_lock(base_vha, 0);
5620 break;
5621 case QLA8XXX_DEV_QUIESCENT:
5622 /* XXX: DEBUG for now */
5623 if (ha->flags.quiesce_owner)
5624 goto exit;
5625
5626 qla83xx_idc_unlock(base_vha, 0);
5627 msleep(1000);
5628 qla83xx_idc_lock(base_vha, 0);
5629 dev_init_timeout = jiffies +
5630 (ha->fcoe_dev_init_timeout * HZ);
5631 break;
5632 case QLA8XXX_DEV_FAILED:
5633 if (ha->flags.nic_core_reset_owner)
5634 qla83xx_idc_audit(base_vha,
5635 IDC_AUDIT_COMPLETION);
5636 ha->flags.nic_core_reset_owner = 0;
5637 __qla83xx_clear_drv_presence(base_vha);
5638 qla83xx_idc_unlock(base_vha, 0);
5639 qla8xxx_dev_failed_handler(base_vha);
5640 rval = QLA_FUNCTION_FAILED;
5641 qla83xx_idc_lock(base_vha, 0);
5642 goto exit;
5643 case QLA8XXX_BAD_VALUE:
5644 qla83xx_idc_unlock(base_vha, 0);
5645 msleep(1000);
5646 qla83xx_idc_lock(base_vha, 0);
5647 break;
5648 default:
5649 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5650 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5651 qla83xx_idc_unlock(base_vha, 0);
5652 qla8xxx_dev_failed_handler(base_vha);
5653 rval = QLA_FUNCTION_FAILED;
5654 qla83xx_idc_lock(base_vha, 0);
5655 goto exit;
5656 }
5657 }
5658
5659exit:
5660 return rval;
5661}
5662
f3ddac19
CD		 5663void
5664qla2x00_disable_board_on_pci_error(struct work_struct *work)
5665{
5666 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5667 board_disable);
5668 struct pci_dev *pdev = ha->pdev;
5669 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5670
726b8548
QT		 5671 /*
5672 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5673 * where it was set first.
5674 */
5675 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5676 return;
5677
f3ddac19
CD		 5678 ql_log(ql_log_warn, base_vha, 0x015b,
5679 "Disabling adapter.\n");
5680
efdb5760
SC		 5681 if (!atomic_read(&pdev->enable_cnt)) {
5682 ql_log(ql_log_info, base_vha, 0xfffc,
5683 "PCI device disabled, no action req for PCI error=%lx\n",
5684 base_vha->pci_flags);
5685 return;
5686 }
5687
726b8548
QT		 5688 qla2x00_wait_for_sess_deletion(base_vha);
5689
f3ddac19
CD		 5690 set_bit(UNLOADING, &base_vha->dpc_flags);
5691
5692 qla2x00_delete_all_vps(ha, base_vha);
5693
5694 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5695
5696 qla2x00_dfs_remove(base_vha);
5697
5698 qla84xx_put_chip(base_vha);
5699
5700 if (base_vha->timer_active)
5701 qla2x00_stop_timer(base_vha);
5702
5703 base_vha->flags.online = 0;
5704
5705 qla2x00_destroy_deferred_work(ha);
5706
5707 /*
5708 * Do not try to stop beacon blink as it will issue a mailbox
5709 * command.
5710 */
5711 qla2x00_free_sysfs_attr(base_vha, false);
5712
5713 fc_remove_host(base_vha->host);
5714
5715 scsi_remove_host(base_vha->host);
5716
5717 base_vha->flags.init_done = 0;
5718 qla25xx_delete_queues(base_vha);
f3ddac19 5719 qla2x00_free_fcports(base_vha);
093df737 5720 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5721 qla2x00_mem_free(ha);
5722 qla82xx_md_free(base_vha);
5723 qla2x00_free_queues(ha);
5724
f3ddac19
CD		 5725 qla2x00_unmap_iobases(ha);
5726
5727 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5728 pci_disable_pcie_error_reporting(pdev);
5729 pci_disable_device(pdev);
f3ddac19 5730
beb9e315
JL		 5731 /*
5732 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5733 */
f3ddac19
CD		 5734}
5735
1da177e4
LT		 5736/**************************************************************************
5737* qla2x00_do_dpc
5738* This kernel thread is a task that is schedule by the interrupt handler
5739* to perform the background processing for interrupts.
5740*
5741* Notes:
5742* This task always run in the context of a kernel thread. It
5743* is kick-off by the driver's detect code and starts up
5744* up one per adapter. It immediately goes to sleep and waits for
5745* some fibre event. When either the interrupt handler or
5746* the timer routine detects a event it will one of the task
5747* bits then wake us up.
5748**************************************************************************/
5749static int
5750qla2x00_do_dpc(void *data)
5751{
e315cd28
AC		 5752 scsi_qla_host_t *base_vha;
5753 struct qla_hw_data *ha;
d7459527
MH		 5754 uint32_t online;
5755 struct qla_qpair *qpair;
1da177e4 5756
e315cd28
AC		 5757 ha = (struct qla_hw_data *)data;
5758 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5759
8698a745 5760 set_user_nice(current, MIN_NICE);
1da177e4 5761
563585ec 5762 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5763 while (!kthread_should_stop()) {
7c3df132
SK		 5764 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5765 "DPC handler sleeping.\n");
1da177e4 5766
39a11240 5767 schedule();
1da177e4 5768
c142caf0
AV		 5769 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5770 goto end_loop;
1da177e4 5771
85880801 5772 if (ha->flags.eeh_busy) {
7c3df132
SK		 5773 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5774 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5775 goto end_loop;
85880801
AV		 5776 }
5777
1da177e4
LT		 5778 ha->dpc_active = 1;
5779
5f28d2d7
SK		 5780 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5781 "DPC handler waking up, dpc_flags=0x%lx.\n",
5782 base_vha->dpc_flags);
1da177e4 5783
a29b3dd7
JC		 5784 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5785 break;
5786
e315cd28 5787 qla2x00_do_work(base_vha);
0971de7f 5788
7ec0effd
AD		 5789 if (IS_P3P_TYPE(ha)) {
5790 if (IS_QLA8044(ha)) {
5791 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5792 &base_vha->dpc_flags)) {
5793 qla8044_idc_lock(ha);
5794 qla8044_wr_direct(base_vha,
5795 QLA8044_CRB_DEV_STATE_INDEX,
5796 QLA8XXX_DEV_FAILED);
5797 qla8044_idc_unlock(ha);
5798 ql_log(ql_log_info, base_vha, 0x4004,
5799 "HW State: FAILED.\n");
5800 qla8044_device_state_handler(base_vha);
5801 continue;
5802 }
5803
5804 } else {
5805 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5806 &base_vha->dpc_flags)) {
5807 qla82xx_idc_lock(ha);
5808 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5809 QLA8XXX_DEV_FAILED);
5810 qla82xx_idc_unlock(ha);
5811 ql_log(ql_log_info, base_vha, 0x0151,
5812 "HW State: FAILED.\n");
5813 qla82xx_device_state_handler(base_vha);
5814 continue;
5815 }
a9083016
GM		 5816 }
5817
5818 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5819 &base_vha->dpc_flags)) {
5820
7c3df132
SK		 5821 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5822 "FCoE context reset scheduled.\n");
a9083016
GM		 5823 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5824 &base_vha->dpc_flags))) {
5825 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5826 /* FCoE-ctx reset failed.
5827 * Escalate to chip-reset
5828 */
5829 set_bit(ISP_ABORT_NEEDED,
5830 &base_vha->dpc_flags);
5831 }
5832 clear_bit(ABORT_ISP_ACTIVE,
5833 &base_vha->dpc_flags);
5834 }
5835
7c3df132
SK		 5836 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5837 "FCoE context reset end.\n");
a9083016 5838 }
8ae6d9c7
GM		 5839 } else if (IS_QLAFX00(ha)) {
5840 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5841 &base_vha->dpc_flags)) {
5842 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5843 "Firmware Reset Recovery\n");
5844 if (qlafx00_reset_initialize(base_vha)) {
5845 /* Failed. Abort isp later. */
5846 if (!test_bit(UNLOADING,
f92f82d6 5847 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5848 set_bit(ISP_UNRECOVERABLE,
5849 &base_vha->dpc_flags);
5850 ql_dbg(ql_dbg_dpc, base_vha,
5851 0x4021,
5852 "Reset Recovery Failed\n");
f92f82d6 5853 }
8ae6d9c7
GM		 5854 }
5855 }
5856
5857 if (test_and_clear_bit(FX00_TARGET_SCAN,
5858 &base_vha->dpc_flags)) {
5859 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5860 "ISPFx00 Target Scan scheduled\n");
5861 if (qlafx00_rescan_isp(base_vha)) {
5862 if (!test_bit(UNLOADING,
5863 &base_vha->dpc_flags))
5864 set_bit(ISP_UNRECOVERABLE,
5865 &base_vha->dpc_flags);
5866 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5867 "ISPFx00 Target Scan Failed\n");
5868 }
5869 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5870 "ISPFx00 Target Scan End\n");
5871 }
e8f5e95d
AB		 5872 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5873 &base_vha->dpc_flags)) {
5874 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5875 "ISPFx00 Host Info resend scheduled\n");
5876 qlafx00_fx_disc(base_vha,
5877 &base_vha->hw->mr.fcport,
5878 FXDISC_REG_HOST_INFO);
5879 }
a9083016
GM		 5880 }
5881
e4e3a2ce
QT		 5882 if (test_and_clear_bit(DETECT_SFP_CHANGE,
5883 &base_vha->dpc_flags) &&
5884 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
5885 qla24xx_detect_sfp(base_vha);
5886
5887 if (ha->flags.detected_lr_sfp !=
5888 ha->flags.using_lr_setting)
5889 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
5890 }
5891
e3e6fcef
QT		 5892 if (test_and_clear_bit
5893 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
5894 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
4af79e86
QT		 5895 bool do_reset = true;
5896
5897 switch (ql2x_ini_mode) {
5898 case QLA2XXX_INI_MODE_ENABLED:
5899 break;
5900 case QLA2XXX_INI_MODE_DISABLED:
5901 if (!qla_tgt_mode_enabled(base_vha))
5902 do_reset = false;
5903 break;
5904 case QLA2XXX_INI_MODE_DUAL:
5905 if (!qla_dual_mode_enabled(base_vha))
5906 do_reset = false;
5907 break;
5908 default:
5909 break;
5910 }
1da177e4 5911
4af79e86 5912 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5913 &base_vha->dpc_flags))) {
4af79e86
QT		 5914 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5915 "ISP abort scheduled.\n");
a9083016 5916 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5917 /* failed. retry later */
5918 set_bit(ISP_ABORT_NEEDED,
e315cd28 5919 &base_vha->dpc_flags);
99363ef8 5920 }
e315cd28
AC		 5921 clear_bit(ABORT_ISP_ACTIVE,
5922 &base_vha->dpc_flags);
4af79e86
QT		 5923 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5924 "ISP abort end.\n");
99363ef8 5925 }
1da177e4
LT		 5926 }
5927
a394aac8
DJ		 5928 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5929 &base_vha->dpc_flags)) {
e315cd28 5930 qla2x00_update_fcports(base_vha);
c9c5ced9 5931 }
d97994dc 5932
8ae6d9c7
GM		 5933 if (IS_QLAFX00(ha))
5934 goto loop_resync_check;
5935
579d12b5 5936 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5937 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5938 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5939 if (IS_P3P_TYPE(ha)) {
5940 if (IS_QLA82XX(ha))
5941 qla82xx_device_state_handler(base_vha);
5942 if (IS_QLA8044(ha))
5943 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5944 clear_bit(ISP_QUIESCE_NEEDED,
5945 &base_vha->dpc_flags);
5946 if (!ha->flags.quiesce_owner) {
5947 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5948 if (IS_QLA82XX(ha)) {
5949 qla82xx_idc_lock(ha);
5950 qla82xx_clear_qsnt_ready(
5951 base_vha);
5952 qla82xx_idc_unlock(ha);
5953 } else if (IS_QLA8044(ha)) {
5954 qla8044_idc_lock(ha);
5955 qla8044_clear_qsnt_ready(
5956 base_vha);
5957 qla8044_idc_unlock(ha);
5958 }
8fcd6b8b
CD		 5959 }
5960 } else {
5961 clear_bit(ISP_QUIESCE_NEEDED,
5962 &base_vha->dpc_flags);
5963 qla2x00_quiesce_io(base_vha);
579d12b5 5964 }
7c3df132
SK		 5965 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5966 "Quiescence mode end.\n");
579d12b5
SK		 5967 }
5968
e315cd28 5969 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5970 &base_vha->dpc_flags) &&
e315cd28 5971 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5972
7c3df132
SK		 5973 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5974 "Reset marker scheduled.\n");
e315cd28
AC		 5975 qla2x00_rst_aen(base_vha);
5976 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5977 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5978 "Reset marker end.\n");
1da177e4
LT		 5979 }
5980
5981 /* Retry each device up to login retry count */
5118a256 5982 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 5983 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5984 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5985
5118a256
QT		 5986 if (!base_vha->relogin_jif ||
5987 time_after_eq(jiffies, base_vha->relogin_jif)) {
5988 base_vha->relogin_jif = jiffies + HZ;
5989 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
5990
5991 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5992 "Relogin scheduled.\n");
5993 qla2x00_relogin(base_vha);
5994 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5995 "Relogin end.\n");
5996 }
1da177e4 5997 }
8ae6d9c7 5998loop_resync_check:
e315cd28 5999 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6000 &base_vha->dpc_flags)) {
1da177e4 6001
7c3df132
SK		 6002 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6003 "Loop resync scheduled.\n");
1da177e4
LT		 6004
6005 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6006 &base_vha->dpc_flags))) {
1da177e4 6007
52c82823 6008 qla2x00_loop_resync(base_vha);
1da177e4 6009
e315cd28
AC		 6010 clear_bit(LOOP_RESYNC_ACTIVE,
6011 &base_vha->dpc_flags);
1da177e4
LT		 6012 }
6013
7c3df132
SK		 6014 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6015 "Loop resync end.\n");
1da177e4
LT		 6016 }
6017
8ae6d9c7
GM		 6018 if (IS_QLAFX00(ha))
6019 goto intr_on_check;
6020
e315cd28
AC		 6021 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6022 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6023 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6024 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6025 }
6026
8ae6d9c7 6027intr_on_check:
1da177e4 6028 if (!ha->interrupts_on)
fd34f556 6029 ha->isp_ops->enable_intrs(ha);
1da177e4 6030
e315cd28 6031 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6032 &base_vha->dpc_flags)) {
6033 if (ha->beacon_blink_led == 1)
6034 ha->isp_ops->beacon_blink(base_vha);
6035 }
f6df144c 6036
d7459527
MH		 6037 /* qpair online check */
6038 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6039 &base_vha->dpc_flags)) {
6040 if (ha->flags.eeh_busy ||
6041 ha->flags.pci_channel_io_perm_failure)
6042 online = 0;
6043 else
6044 online = 1;
6045
6046 mutex_lock(&ha->mq_lock);
6047 list_for_each_entry(qpair, &base_vha->qp_list,
6048 qp_list_elem)
6049 qpair->online = online;
6050 mutex_unlock(&ha->mq_lock);
6051 }
6052
deeae7a6
DG		 6053 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
6054 ql_log(ql_log_info, base_vha, 0xffffff,
6055 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6056 ha->nvme_last_rptd_aen);
6057 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
6058 ql_log(ql_log_info, base_vha, 0xffffff,
6059 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6060 ha->nvme_last_rptd_aen);
6061 }
6062 }
6063
8ae6d9c7
GM		 6064 if (!IS_QLAFX00(ha))
6065 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6066
1da177e4 6067 ha->dpc_active = 0;
c142caf0 6068end_loop:
563585ec 6069 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6070 } /* End of while(1) */
563585ec 6071 __set_current_state(TASK_RUNNING);
1da177e4 6072
7c3df132
SK		 6073 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6074 "DPC handler exiting.\n");
1da177e4
LT		 6075
6076 /*
6077 * Make sure that nobody tries to wake us up again.
6078 */
1da177e4
LT		 6079 ha->dpc_active = 0;
6080
ac280b67
AV		 6081 /* Cleanup any residual CTX SRBs. */
6082 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6083
39a11240
CH		 6084 return 0;
6085}
6086
6087void
e315cd28 6088qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6089{
e315cd28 6090 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6091 struct task_struct *t = ha->dpc_thread;
6092
e315cd28 6093 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6094 wake_up_process(t);
1da177e4
LT		 6095}
6096
1da177e4
LT		 6097/*
6098* qla2x00_rst_aen
6099* Processes asynchronous reset.
6100*
6101* Input:
6102* ha = adapter block pointer.
6103*/
6104static void
e315cd28 6105qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6106{
e315cd28
AC		 6107 if (vha->flags.online && !vha->flags.reset_active &&
6108 !atomic_read(&vha->loop_down_timer) &&
6109 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6110 do {
e315cd28 6111 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6112
6113 /*
6114 * Issue marker command only when we are going to start
6115 * the I/O.
6116 */
e315cd28
AC		 6117 vha->marker_needed = 1;
6118 } while (!atomic_read(&vha->loop_down_timer) &&
6119 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6120 }
6121}
6122
1da177e4
LT		 6123/**************************************************************************
6124* qla2x00_timer
6125*
6126* Description:
6127* One second timer
6128*
6129* Context: Interrupt
6130***************************************************************************/
2c3dfe3f 6131void
8e5f4ba0 6132qla2x00_timer(struct timer_list *t)
1da177e4 6133{
8e5f4ba0 6134 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6135 unsigned long cpu_flags = 0;
1da177e4
LT		 6136 int start_dpc = 0;
6137 int index;
6138 srb_t *sp;
85880801 6139 uint16_t w;
e315cd28 6140 struct qla_hw_data *ha = vha->hw;
73208dfd 6141 struct req_que *req;
85880801 6142
a5b36321 6143 if (ha->flags.eeh_busy) {
7c3df132
SK		 6144 ql_dbg(ql_dbg_timer, vha, 0x6000,
6145 "EEH = %d, restarting timer.\n",
6146 ha->flags.eeh_busy);
a5b36321
LC		 6147 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6148 return;
6149 }
6150
f3ddac19
CD		 6151 /*
6152 * Hardware read to raise pending EEH errors during mailbox waits. If
6153 * the read returns -1 then disable the board.
6154 */
6155 if (!pci_channel_offline(ha->pdev)) {
85880801 6156 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6157 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6158 }
1da177e4 6159
cefcaba6 6160 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6161 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6162 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6163 start_dpc++;
7ec0effd
AD		 6164 if (IS_QLA82XX(ha))
6165 qla82xx_watchdog(vha);
6166 else if (IS_QLA8044(ha))
6167 qla8044_watchdog(vha);
579d12b5
SK		 6168 }
6169
8ae6d9c7
GM		 6170 if (!vha->vp_idx && IS_QLAFX00(ha))
6171 qlafx00_timer_routine(vha);
6172
1da177e4 6173 /* Loop down handler. */
e315cd28 6174 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6175 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6176 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6177 && vha->flags.online) {
1da177e4 6178
e315cd28
AC		 6179 if (atomic_read(&vha->loop_down_timer) ==
6180 vha->loop_down_abort_time) {
1da177e4 6181
7c3df132
SK		 6182 ql_log(ql_log_info, vha, 0x6008,
6183 "Loop down - aborting the queues before time expires.\n");
1da177e4 6184
e315cd28
AC		 6185 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6186 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6187
f08b7251
AV		 6188 /*
6189 * Schedule an ISP abort to return any FCP2-device
6190 * commands.
6191 */
2c3dfe3f 6192 /* NPIV - scan physical port only */
e315cd28 6193 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6194 spin_lock_irqsave(&ha->hardware_lock,
6195 cpu_flags);
73208dfd 6196 req = ha->req_q_map[0];
2c3dfe3f 6197 for (index = 1;
8d93f550 6198 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6199 index++) {
6200 fc_port_t *sfcp;
6201
e315cd28 6202 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6203 if (!sp)
6204 continue;
c5419e26
QT		 6205 if (sp->cmd_type != TYPE_SRB)
6206 continue;
9ba56b95 6207 if (sp->type != SRB_SCSI_CMD)
cf53b069 6208 continue;
2c3dfe3f 6209 sfcp = sp->fcport;
f08b7251 6210 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6211 continue;
bdf79621 6212
8f7daead
GM		 6213 if (IS_QLA82XX(ha))
6214 set_bit(FCOE_CTX_RESET_NEEDED,
6215 &vha->dpc_flags);
6216 else
6217 set_bit(ISP_ABORT_NEEDED,
e315cd28 6218 &vha->dpc_flags);
2c3dfe3f
SJ		 6219 break;
6220 }
6221 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6222 cpu_flags);
1da177e4 6223 }
1da177e4
LT		 6224 start_dpc++;
6225 }
6226
6227 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6228 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6229 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6230 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6231 "Loop down - aborting ISP.\n");
6232
8f7daead
GM		 6233 if (IS_QLA82XX(ha))
6234 set_bit(FCOE_CTX_RESET_NEEDED,
6235 &vha->dpc_flags);
6236 else
6237 set_bit(ISP_ABORT_NEEDED,
6238 &vha->dpc_flags);
1da177e4
LT		 6239 }
6240 }
7c3df132
SK		 6241 ql_dbg(ql_dbg_timer, vha, 0x600a,
6242 "Loop down - seconds remaining %d.\n",
6243 atomic_read(&vha->loop_down_timer));
1da177e4 6244 }
cefcaba6
SK		 6245 /* Check if beacon LED needs to be blinked for physical host only */
6246 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6247 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6248 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6249 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6250 start_dpc++;
6251 }
f6df144c
AV		 6252 }
6253
550bf57d 6254 /* Process any deferred work. */
e315cd28 6255 if (!list_empty(&vha->work_list))
550bf57d
AV		 6256 start_dpc++;
6257
7401bc18
DG		 6258 /*
6259 * FC-NVME
6260 * see if the active AEN count has changed from what was last reported.
6261 */
deeae7a6
DG		 6262 if (!vha->vp_idx &&
6263 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6264 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6265 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6266 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6267 ha->nvme_last_rptd_aen);
6268 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6269 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6270 start_dpc++;
7401bc18
DG		 6271 }
6272
1da177e4 6273 /* Schedule the DPC routine if needed */
e315cd28
AC		 6274 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6275 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6276 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6277 start_dpc ||
e315cd28
AC		 6278 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6279 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6280 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6281 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6282 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6283 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6284 ql_dbg(ql_dbg_timer, vha, 0x600b,
6285 "isp_abort_needed=%d loop_resync_needed=%d "
6286 "fcport_update_needed=%d start_dpc=%d "
6287 "reset_marker_needed=%d",
6288 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6289 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6290 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6291 start_dpc,
6292 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6293 ql_dbg(ql_dbg_timer, vha, 0x600c,
6294 "beacon_blink_needed=%d isp_unrecoverable=%d "
6295 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6296 "relogin_needed=%d.\n",
7c3df132
SK		 6297 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6298 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6299 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6300 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6301 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6302 qla2xxx_wake_dpc(vha);
7c3df132 6303 }
1da177e4 6304
e315cd28 6305 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6306}
6307
5433383e
AV		 6308/* Firmware interface routines. */
6309
f73cb695 6310#define FW_BLOBS 11
5433383e
AV		 6311#define FW_ISP21XX 0
6312#define FW_ISP22XX 1
6313#define FW_ISP2300 2
6314#define FW_ISP2322 3
48c02fde 6315#define FW_ISP24XX 4
c3a2f0df 6316#define FW_ISP25XX 5
3a03eb79 6317#define FW_ISP81XX 6
a9083016 6318#define FW_ISP82XX 7
6246b8a1
GM		 6319#define FW_ISP2031 8
6320#define FW_ISP8031 9
2c5bbbb2 6321#define FW_ISP27XX 10
5433383e 6322
bb8ee499
AV		 6323#define FW_FILE_ISP21XX "ql2100_fw.bin"
6324#define FW_FILE_ISP22XX "ql2200_fw.bin"
6325#define FW_FILE_ISP2300 "ql2300_fw.bin"
6326#define FW_FILE_ISP2322 "ql2322_fw.bin"
6327#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6328#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6329#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6330#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6331#define FW_FILE_ISP2031 "ql2600_fw.bin"
6332#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6333#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6334
bb8ee499 6335
e1e82b6f 6336static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6337
6338static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6339 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6340 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6341 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6342 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6343 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6344 { .name = FW_FILE_ISP25XX, },
3a03eb79 6345 { .name = FW_FILE_ISP81XX, },
a9083016 6346 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6347 { .name = FW_FILE_ISP2031, },
6348 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6349 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6350};
6351
6352struct fw_blob *
e315cd28 6353qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6354{
e315cd28 6355 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6356 struct fw_blob *blob;
6357
5433383e
AV		 6358 if (IS_QLA2100(ha)) {
6359 blob = &qla_fw_blobs[FW_ISP21XX];
6360 } else if (IS_QLA2200(ha)) {
6361 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6362 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6363 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6364 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6365 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6366 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6367 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6368 } else if (IS_QLA25XX(ha)) {
6369 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6370 } else if (IS_QLA81XX(ha)) {
6371 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6372 } else if (IS_QLA82XX(ha)) {
6373 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6374 } else if (IS_QLA2031(ha)) {
6375 blob = &qla_fw_blobs[FW_ISP2031];
6376 } else if (IS_QLA8031(ha)) {
6377 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6378 } else if (IS_QLA27XX(ha)) {
6379 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6380 } else {
6381 return NULL;
5433383e
AV		 6382 }
6383
e1e82b6f 6384 mutex_lock(&qla_fw_lock);
5433383e
AV		 6385 if (blob->fw)
6386 goto out;
6387
6388 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6389 ql_log(ql_log_warn, vha, 0x0063,
6390 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6391 blob->fw = NULL;
6392 blob = NULL;
6393 goto out;
6394 }
6395
6396out:
e1e82b6f 6397 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6398 return blob;
6399}
6400
6401static void
6402qla2x00_release_firmware(void)
6403{
6404 int idx;
6405
e1e82b6f 6406 mutex_lock(&qla_fw_lock);
5433383e 6407 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6408 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6409 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6410}
6411
14e660e6
SJ		 6412static pci_ers_result_t
6413qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6414{
85880801
AV		 6415 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6416 struct qla_hw_data *ha = vha->hw;
6417
7c3df132
SK		 6418 ql_dbg(ql_dbg_aer, vha, 0x9000,
6419 "PCI error detected, state %x.\n", state);
b9b12f73 6420
efdb5760
SC		 6421 if (!atomic_read(&pdev->enable_cnt)) {
6422 ql_log(ql_log_info, vha, 0xffff,
6423 "PCI device is disabled,state %x\n", state);
6424 return PCI_ERS_RESULT_NEED_RESET;
6425 }
6426
14e660e6
SJ		 6427 switch (state) {
6428 case pci_channel_io_normal:
85880801 6429 ha->flags.eeh_busy = 0;
c38d1baf 6430 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6431 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6432 qla2xxx_wake_dpc(vha);
6433 }
14e660e6
SJ		 6434 return PCI_ERS_RESULT_CAN_RECOVER;
6435 case pci_channel_io_frozen:
85880801 6436 ha->flags.eeh_busy = 1;
a5b36321
LC		 6437 /* For ISP82XX complete any pending mailbox cmd */
6438 if (IS_QLA82XX(ha)) {
7190575f 6439 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6440 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6441 qla82xx_clear_pending_mbx(vha);
a5b36321 6442 }
90a86fc0 6443 qla2x00_free_irqs(vha);
14e660e6 6444 pci_disable_device(pdev);
bddd2d65
LC		 6445 /* Return back all IOs */
6446 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
c38d1baf 6447 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6448 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6449 qla2xxx_wake_dpc(vha);
6450 }
14e660e6
SJ		 6451 return PCI_ERS_RESULT_NEED_RESET;
6452 case pci_channel_io_perm_failure:
85880801
AV		 6453 ha->flags.pci_channel_io_perm_failure = 1;
6454 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6455 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6456 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6457 qla2xxx_wake_dpc(vha);
6458 }
14e660e6
SJ		 6459 return PCI_ERS_RESULT_DISCONNECT;
6460 }
6461 return PCI_ERS_RESULT_NEED_RESET;
6462}
6463
6464static pci_ers_result_t
6465qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6466{
6467 int risc_paused = 0;
6468 uint32_t stat;
6469 unsigned long flags;
e315cd28
AC		 6470 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6471 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6472 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6473 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6474
bcc5b6d3
SK		 6475 if (IS_QLA82XX(ha))
6476 return PCI_ERS_RESULT_RECOVERED;
6477
14e660e6
SJ		 6478 spin_lock_irqsave(&ha->hardware_lock, flags);
6479 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6480 stat = RD_REG_DWORD(&reg->hccr);
6481 if (stat & HCCR_RISC_PAUSE)
6482 risc_paused = 1;
6483 } else if (IS_QLA23XX(ha)) {
6484 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6485 if (stat & HSR_RISC_PAUSED)
6486 risc_paused = 1;
6487 } else if (IS_FWI2_CAPABLE(ha)) {
6488 stat = RD_REG_DWORD(&reg24->host_status);
6489 if (stat & HSRX_RISC_PAUSED)
6490 risc_paused = 1;
6491 }
6492 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6493
6494 if (risc_paused) {
7c3df132
SK		 6495 ql_log(ql_log_info, base_vha, 0x9003,
6496 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6497 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6498
6499 return PCI_ERS_RESULT_NEED_RESET;
6500 } else
6501 return PCI_ERS_RESULT_RECOVERED;
6502}
6503
fa492630
SK		 6504static uint32_t
6505qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6506{
6507 uint32_t rval = QLA_FUNCTION_FAILED;
6508 uint32_t drv_active = 0;
6509 struct qla_hw_data *ha = base_vha->hw;
6510 int fn;
6511 struct pci_dev *other_pdev = NULL;
6512
7c3df132
SK		 6513 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6514 "Entered %s.\n", __func__);
a5b36321
LC		 6515
6516 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6517
6518 if (base_vha->flags.online) {
6519 /* Abort all outstanding commands,
6520 * so as to be requeued later */
6521 qla2x00_abort_isp_cleanup(base_vha);
6522 }
6523
6524
6525 fn = PCI_FUNC(ha->pdev->devfn);
6526 while (fn > 0) {
6527 fn--;
7c3df132
SK		 6528 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6529 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6530 other_pdev =
6531 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6532 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6533 fn));
6534
6535 if (!other_pdev)
6536 continue;
6537 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6538 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6539 "Found PCI func available and enable at 0x%x.\n",
6540 fn);
a5b36321
LC		 6541 pci_dev_put(other_pdev);
6542 break;
6543 }
6544 pci_dev_put(other_pdev);
6545 }
6546
6547 if (!fn) {
6548 /* Reset owner */
7c3df132
SK		 6549 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6550 "This devfn is reset owner = 0x%x.\n",
6551 ha->pdev->devfn);
a5b36321
LC		 6552 qla82xx_idc_lock(ha);
6553
6554 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6555 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6556
6557 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6558 QLA82XX_IDC_VERSION);
6559
6560 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6561 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6562 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6563
6564 qla82xx_idc_unlock(ha);
6565 /* Reset if device is not already reset
6566 * drv_active would be 0 if a reset has already been done
6567 */
6568 if (drv_active)
6569 rval = qla82xx_start_firmware(base_vha);
6570 else
6571 rval = QLA_SUCCESS;
6572 qla82xx_idc_lock(ha);
6573
6574 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6575 ql_log(ql_log_info, base_vha, 0x900b,
6576 "HW State: FAILED.\n");
a5b36321
LC		 6577 qla82xx_clear_drv_active(ha);
6578 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6579 QLA8XXX_DEV_FAILED);
a5b36321 6580 } else {
7c3df132
SK		 6581 ql_log(ql_log_info, base_vha, 0x900c,
6582 "HW State: READY.\n");
a5b36321 6583 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6584 QLA8XXX_DEV_READY);
a5b36321 6585 qla82xx_idc_unlock(ha);
7190575f 6586 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6587 rval = qla82xx_restart_isp(base_vha);
6588 qla82xx_idc_lock(ha);
6589 /* Clear driver state register */
6590 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6591 qla82xx_set_drv_active(base_vha);
6592 }
6593 qla82xx_idc_unlock(ha);
6594 } else {
7c3df132
SK		 6595 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6596 "This devfn is not reset owner = 0x%x.\n",
6597 ha->pdev->devfn);
a5b36321 6598 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6599 QLA8XXX_DEV_READY)) {
7190575f 6600 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6601 rval = qla82xx_restart_isp(base_vha);
6602 qla82xx_idc_lock(ha);
6603 qla82xx_set_drv_active(base_vha);
6604 qla82xx_idc_unlock(ha);
6605 }
6606 }
6607 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6608
6609 return rval;
6610}
6611
14e660e6
SJ		 6612static pci_ers_result_t
6613qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6614{
6615 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6616 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6617 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6618 struct rsp_que *rsp;
6619 int rc, retries = 10;
09483916 6620
7c3df132
SK		 6621 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6622 "Slot Reset.\n");
85880801 6623
90a86fc0
JC		 6624 /* Workaround: qla2xxx driver which access hardware earlier
6625 * needs error state to be pci_channel_io_online.
6626 * Otherwise mailbox command timesout.
6627 */
6628 pdev->error_state = pci_channel_io_normal;
6629
6630 pci_restore_state(pdev);
6631
8c1496bd
RL		 6632 /* pci_restore_state() clears the saved_state flag of the device
6633 * save restored state which resets saved_state flag
6634 */
6635 pci_save_state(pdev);
6636
09483916
BH		 6637 if (ha->mem_only)
6638 rc = pci_enable_device_mem(pdev);
6639 else
6640 rc = pci_enable_device(pdev);
14e660e6 6641
09483916 6642 if (rc) {
7c3df132 6643 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6644 "Can't re-enable PCI device after reset.\n");
a5b36321 6645 goto exit_slot_reset;
14e660e6 6646 }
14e660e6 6647
90a86fc0
JC		 6648 rsp = ha->rsp_q_map[0];
6649 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6650 goto exit_slot_reset;
90a86fc0 6651
e315cd28 6652 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6653 goto exit_slot_reset;
6654
6655 if (IS_QLA82XX(ha)) {
6656 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6657 ret = PCI_ERS_RESULT_RECOVERED;
6658 goto exit_slot_reset;
6659 } else
6660 goto exit_slot_reset;
6661 }
14e660e6 6662
90a86fc0
JC		 6663 while (ha->flags.mbox_busy && retries--)
6664 msleep(1000);
85880801 6665
e315cd28 6666 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6667 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6668 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6669 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6670
90a86fc0 6671
a5b36321 6672exit_slot_reset:
7c3df132
SK		 6673 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6674 "slot_reset return %x.\n", ret);
85880801 6675
14e660e6
SJ		 6676 return ret;
6677}
6678
6679static void
6680qla2xxx_pci_resume(struct pci_dev *pdev)
6681{
e315cd28
AC		 6682 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6683 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6684 int ret;
6685
7c3df132
SK		 6686 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6687 "pci_resume.\n");
85880801 6688
e315cd28 6689 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6690 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6691 ql_log(ql_log_fatal, base_vha, 0x9002,
6692 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6693 }
85880801 6694
3e46f031
LC		 6695 pci_cleanup_aer_uncorrect_error_status(pdev);
6696
85880801 6697 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6698}
6699
2d5a4c34
HM		 6700static void
6701qla83xx_disable_laser(scsi_qla_host_t *vha)
6702{
6703 uint32_t reg, data, fn;
6704 struct qla_hw_data *ha = vha->hw;
6705 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6706
6707 /* pci func #/port # */
6708 ql_dbg(ql_dbg_init, vha, 0x004b,
6709 "Disabling Laser for hba: %p\n", vha);
6710
6711 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6712 (BIT_15|BIT_14|BIT_13|BIT_12));
6713
6714 fn = (fn >> 12);
6715
6716 if (fn & 1)
6717 reg = PORT_1_2031;
6718 else
6719 reg = PORT_0_2031;
6720
6721 data = LASER_OFF_2031;
6722
6723 qla83xx_wr_reg(vha, reg, data);
6724}
6725
5601236b
MH		 6726static int qla2xxx_map_queues(struct Scsi_Host *shost)
6727{
a3006568 6728 int rc;
5601236b
MH		 6729 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6730
a3006568
QT		 6731 if (USER_CTRL_IRQ(vha->hw))
6732 rc = blk_mq_map_queues(&shost->tag_set);
6733 else
6734 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6735 return rc;
5601236b
MH		 6736}
6737
a55b2d21 6738static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6739 .error_detected = qla2xxx_pci_error_detected,
6740 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6741 .slot_reset = qla2xxx_pci_slot_reset,
6742 .resume = qla2xxx_pci_resume,
6743};
6744
5433383e 6745static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6746 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6747 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6748 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6749 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6750 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6751 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6752 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6753 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6754 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6755 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6756 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6757 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6758 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6759 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6760 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6761 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6762 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6763 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6764 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6765 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6766 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6767 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6768 { 0 },
6769};
6770MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6771
fca29703 6772static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6773 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6774 .driver = {
6775 .owner = THIS_MODULE,
6776 },
fca29703 6777 .id_table = qla2xxx_pci_tbl,
7ee61397 6778 .probe = qla2x00_probe_one,
4c993f76 6779 .remove = qla2x00_remove_one,
e30d1756 6780 .shutdown = qla2x00_shutdown,
14e660e6 6781 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6782};
6783
75ef9de1 6784static const struct file_operations apidev_fops = {
6a03b4cd 6785 .owner = THIS_MODULE,
6038f373 6786 .llseek = noop_llseek,
6a03b4cd
HZ		 6787};
6788
1da177e4
LT		 6789/**
6790 * qla2x00_module_init - Module initialization.
6791 **/
6792static int __init
6793qla2x00_module_init(void)
6794{
fca29703
AV		 6795 int ret = 0;
6796
1da177e4 6797 /* Allocate cache for SRBs. */
354d6b21 6798 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6799 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6800 if (srb_cachep == NULL) {
7c3df132
SK		 6801 ql_log(ql_log_fatal, NULL, 0x0001,
6802 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6803 return -ENOMEM;
6804 }
6805
2d70c103
NB		 6806 /* Initialize target kmem_cache and mem_pools */
6807 ret = qlt_init();
6808 if (ret < 0) {
8bb67105 6809 goto destroy_cache;
2d70c103
NB		 6810 } else if (ret > 0) {
6811 /*
6812 * If initiator mode is explictly disabled by qlt_init(),
6813 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6814 * performing scsi_scan_target() during LOOP UP event.
6815 */
6816 qla2xxx_transport_functions.disable_target_scan = 1;
6817 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6818 }
6819
1da177e4
LT		 6820 /* Derive version string. */
6821 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6822 if (ql2xextended_error_logging)
0181944f 6823 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6824 if (ql2xextended_error_logging == 1)
6825 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6826
1c97a12a
AV		 6827 qla2xxx_transport_template =
6828 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 6829 if (!qla2xxx_transport_template) {
7c3df132
SK		 6830 ql_log(ql_log_fatal, NULL, 0x0002,
6831 "fc_attach_transport failed...Failing load!.\n");
8bb67105
BVA		 6832 ret = -ENODEV;
6833 goto qlt_exit;
2c3dfe3f 6834 }
6a03b4cd
HZ		 6835
6836 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6837 if (apidev_major < 0) {
7c3df132
SK		 6838 ql_log(ql_log_fatal, NULL, 0x0003,
6839 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6840 }
6841
2c3dfe3f
SJ		 6842 qla2xxx_transport_vport_template =
6843 fc_attach_transport(&qla2xxx_transport_vport_functions);
6844 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 6845 ql_log(ql_log_fatal, NULL, 0x0004,
6846 "fc_attach_transport vport failed...Failing load!.\n");
8bb67105
BVA		 6847 ret = -ENODEV;
6848 goto unreg_chrdev;
2c3dfe3f 6849 }
7c3df132
SK		 6850 ql_log(ql_log_info, NULL, 0x0005,
6851 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6852 qla2x00_version_str);
7ee61397 6853 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 6854 if (ret) {
7c3df132
SK		 6855 ql_log(ql_log_fatal, NULL, 0x0006,
6856 "pci_register_driver failed...ret=%d Failing load!.\n",
6857 ret);
8bb67105 6858 goto release_vport_transport;
fca29703
AV		 6859 }
6860 return ret;
8bb67105
BVA		 6861
6862release_vport_transport:
6863 fc_release_transport(qla2xxx_transport_vport_template);
6864
6865unreg_chrdev:
6866 if (apidev_major >= 0)
6867 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
6868 fc_release_transport(qla2xxx_transport_template);
6869
6870qlt_exit:
6871 qlt_exit();
6872
6873destroy_cache:
6874 kmem_cache_destroy(srb_cachep);
6875 return ret;
1da177e4
LT		 6876}
6877
6878/**
6879 * qla2x00_module_exit - Module cleanup.
6880 **/
6881static void __exit
6882qla2x00_module_exit(void)
6883{
6a03b4cd 6884 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6885 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6886 qla2x00_release_firmware();
354d6b21 6887 kmem_cache_destroy(srb_cachep);
2d70c103 6888 qlt_exit();
a9083016
GM		 6889 if (ctx_cachep)
6890 kmem_cache_destroy(ctx_cachep);
1da177e4 6891 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6892 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6893}
6894
6895module_init(qla2x00_module_init);
6896module_exit(qla2x00_module_exit);
6897
6898MODULE_AUTHOR("QLogic Corporation");
6899MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6900MODULE_LICENSE("GPL");
6901MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6902MODULE_FIRMWARE(FW_FILE_ISP21XX);
6903MODULE_FIRMWARE(FW_FILE_ISP22XX);
6904MODULE_FIRMWARE(FW_FILE_ISP2300);
6905MODULE_FIRMWARE(FW_FILE_ISP2322);
6906MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6907MODULE_FIRMWARE(FW_FILE_ISP25XX);
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