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UBUNTU: Ubuntu-5.3.0-29.31
[mirror_ubuntu-eoan-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
585def9b
QT		 17#include <linux/refcount.h>
18
1da177e4
LT		 19#include <scsi/scsi_tcq.h>
20#include <scsi/scsicam.h>
21#include <scsi/scsi_transport.h>
22#include <scsi/scsi_transport_fc.h>
23
2d70c103
NB		 24#include "qla_target.h"
25
1da177e4
LT		 26/*
27 * Driver version
28 */
29char qla2x00_version_str[40];
30
6a03b4cd
HZ		 31static int apidev_major;
32
1da177e4
LT		 33/*
34 * SRB allocation cache
35 */
d7459527 36struct kmem_cache *srb_cachep;
1da177e4 37
a9083016
GM		 38/*
39 * CT6 CTX allocation cache
40 */
41static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 42/*
43 * error level for logging
44 */
3f006ac3 45uint ql_errlev = 0x8001;
a9083016 46
fa492630 47static int ql2xenableclass2;
2d70c103
NB		 48module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
8ae6d9c7 53
1da177e4 54int ql2xlogintimeout = 20;
f2019cb1 55module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 56MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
a7b61842 59int qlport_down_retry;
f2019cb1 60module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 61MODULE_PARM_DESC(qlport_down_retry,
900d9f98 62 "Maximum number of command retries to a port that returns "
1da177e4
LT		 63 "a PORT-DOWN status.");
64
1da177e4
LT		 65int ql2xplogiabsentdevice;
66module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
900d9f98 69 "a Fabric scan. This is needed for several broken switches. "
0d52e642 70 "Default is 0 - no PLOGI. 1 - perform PLOGI.");
1da177e4 71
1da177e4 72int ql2xloginretrycount = 0;
f2019cb1 73module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 74MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
a7a167bf 77int ql2xallocfwdump = 1;
f2019cb1 78module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 79MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
11010fec 84int ql2xextended_error_logging;
27d94035 85module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 86module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 87MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
3ce8866c 103 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 104
a9083016 105int ql2xshiftctondsd = 6;
f2019cb1 106module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 107MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
58e2753c 111int ql2xfdmienable = 1;
de187df8 112module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 113module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 114MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 117
d213a4b7 118#define MAX_Q_DEPTH 64
50280c01 119static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 120module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 122 "Maximum queue depth to set for each LUN. "
d213a4b7 123 "Default is 64.");
df7baa50 124
e84067d7
DG		 125#if (IS_ENABLED(CONFIG_NVME_FC))
126int ql2xenabledif;
127#else
9e522cd8 128int ql2xenabledif = 2;
e84067d7 129#endif
9e522cd8 130module_param(ql2xenabledif, int, S_IRUGO);
bad75002 131MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 137
e84067d7
DG		 138#if (IS_ENABLED(CONFIG_NVME_FC))
139int ql2xnvmeenable = 1;
140#else
141int ql2xnvmeenable;
142#endif
143module_param(ql2xnvmeenable, int, 0644);
144MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
8cb2049c 148int ql2xenablehba_err_chk = 2;
bad75002
AE		 149module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 152 " Default is 2.\n"
8cb2049c
AE		 153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
bad75002 156
58e2753c 157int ql2xiidmaenable = 1;
f2019cb1 158module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 159MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
d7459527
MH		 163int ql2xmqsupport = 1;
164module_param(ql2xmqsupport, int, S_IRUGO);
165MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 169
170int ql2xfwloadbin;
86e45bf6 171module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 172module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 173MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
ae97c91e 180int ql2xetsenable;
f2019cb1 181module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 182MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
6907869d 186int ql2xdbwr = 1;
86e45bf6 187module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 188MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 192
f4c496c1 193int ql2xtargetreset = 1;
f2019cb1 194module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 195MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
4da26e16 199int ql2xgffidenable;
f2019cb1 200module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 201MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
a9083016 204
043dc1d7 205int ql2xasynctmfenable = 1;
f2019cb1 206module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 207MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
84e13c45 209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 210
211int ql2xdontresethba;
86e45bf6 212module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 213MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
ed0de87c 217
1abf635d
HR		 218uint64_t ql2xmaxlun = MAX_LUNS;
219module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 220MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
08de2844
GM		 224int ql2xmdcapmask = 0x1F;
225module_param(ql2xmdcapmask, int, S_IRUGO);
226MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
6e96fa7b 228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 229
3aadff35 230int ql2xmdenable = 1;
08de2844
GM		 231module_param(ql2xmdenable, int, S_IRUGO);
232MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
3aadff35
GM		 234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
08de2844 236
b0d6cabd
HM		 237int ql2xexlogins = 0;
238module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
99e1b683
QT		 243int ql2xexchoffld = 1024;
244module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 245MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 246 "Number of target exchanges.");
247
248int ql2xiniexchg = 1024;
249module_param(ql2xiniexchg, uint, 0644);
250MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
2f56a7f1 252
f198cafa
HM		 253int ql2xfwholdabts = 0;
254module_param(ql2xfwholdabts, int, S_IRUGO);
255MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
41dc529a
QT		 260int ql2xmvasynctoatio = 1;
261module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
e4e3a2ce
QT		 267int ql2xautodetectsfp = 1;
268module_param(ql2xautodetectsfp, int, 0444);
269MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
e7240af5
HM		 273int ql2xenablemsix = 1;
274module_param(ql2xenablemsix, int, 0444);
275MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
9ecf0b0d
QT		 282int qla2xuseresexchforels;
283module_param(qla2xuseresexchforels, int, 0444);
284MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
b3ede8ea 288static int ql2xprotmask;
7855d2ba
MP		 289module_param(ql2xprotmask, int, 0644);
290MODULE_PARM_DESC(ql2xprotmask,
291 "Override DIF/DIX protection capabilities mask\n"
292 "Default is 0 which sets protection mask based on "
293 "capabilities reported by HBA firmware.\n");
294
b3ede8ea 295static int ql2xprotguard;
7855d2ba
MP		 296module_param(ql2xprotguard, int, 0644);
297MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
298 " 0 -- Let HBA firmware decide\n"
299 " 1 -- Force T10 CRC\n"
300 " 2 -- Force IP checksum\n");
301
50b81275
GM		 302int ql2xdifbundlinginternalbuffers;
303module_param(ql2xdifbundlinginternalbuffers, int, 0644);
304MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers,
305 "Force using internal buffers for DIF information\n"
306 "0 (Default). Based on check.\n"
307 "1 Force using internal buffers\n");
308
1a2fbf18 309static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 310static void qla2x00_free_device(scsi_qla_host_t *);
5601236b 311static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 312static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 313
45235022 314
1da177e4 315static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 316struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 317
1da177e4
LT		 318/* TODO Convert to inlines
319 *
320 * Timer routines
321 */
1da177e4 322
2c3dfe3f 323__inline__ void
8e5f4ba0 324qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 325{
8e5f4ba0 326 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 327 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 328 add_timer(&vha->timer);
329 vha->timer_active = 1;
1da177e4
LT		 330}
331
332static inline void
e315cd28 333qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
a9083016 335 /* Currently used for 82XX only. */
7c3df132
SK		 336 if (vha->device_flags & DFLG_DEV_FAILED) {
337 ql_dbg(ql_dbg_timer, vha, 0x600d,
338 "Device in a failed state, returning.\n");
a9083016 339 return;
7c3df132 340 }
a9083016 341
e315cd28 342 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 343}
344
a824ebb3 345static __inline__ void
e315cd28 346qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 347{
e315cd28
AC		 348 del_timer_sync(&vha->timer);
349 vha->timer_active = 0;
1da177e4
LT		 350}
351
1da177e4
LT		 352static int qla2x00_do_dpc(void *data);
353
354static void qla2x00_rst_aen(scsi_qla_host_t *);
355
73208dfd
AC		 356static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
357 struct req_que **, struct rsp_que **);
e30d1756 358static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 359static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 360int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
361 struct qla_qpair *qpair);
1da177e4 362
1da177e4 363/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 364static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
365 struct rsp_que *rsp)
366{
367 struct qla_hw_data *ha = vha->hw;
bd432bb5 368
8abfa9e2
QT		 369 rsp->qpair = ha->base_qpair;
370 rsp->req = req;
0691094f 371 ha->base_qpair->hw = ha;
8abfa9e2
QT		 372 ha->base_qpair->req = req;
373 ha->base_qpair->rsp = rsp;
374 ha->base_qpair->vha = vha;
375 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
376 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
377 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
6a629468 378 ha->base_qpair->srb_mempool = ha->srb_mempool;
8abfa9e2
QT		 379 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
380 ha->base_qpair->enable_class_2 = ql2xenableclass2;
381 /* init qpair to this cpu. Will adjust at run time. */
86531887 382 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
8abfa9e2
QT		 383 ha->base_qpair->pdev = ha->pdev;
384
ecc89f25 385 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
8abfa9e2
QT		 386 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
387}
388
9a347ff4
CD		 389static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
390 struct rsp_que *rsp)
73208dfd 391{
7c3df132 392 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
bd432bb5 393
6396bb22 394 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
73208dfd
AC		 395 GFP_KERNEL);
396 if (!ha->req_q_map) {
7c3df132
SK		 397 ql_log(ql_log_fatal, vha, 0x003b,
398 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 399 goto fail_req_map;
400 }
401
6396bb22 402 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
73208dfd
AC		 403 GFP_KERNEL);
404 if (!ha->rsp_q_map) {
7c3df132
SK		 405 ql_log(ql_log_fatal, vha, 0x003c,
406 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 407 goto fail_rsp_map;
408 }
d7459527 409
e326d22a
QT		 410 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
411 if (ha->base_qpair == NULL) {
412 ql_log(ql_log_warn, vha, 0x00e0,
413 "Failed to allocate base queue pair memory.\n");
414 goto fail_base_qpair;
415 }
416
8abfa9e2 417 qla_init_base_qpair(vha, req, rsp);
e326d22a 418
c38d1baf 419 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
d7459527
MH		 420 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
421 GFP_KERNEL);
422 if (!ha->queue_pair_map) {
423 ql_log(ql_log_fatal, vha, 0x0180,
424 "Unable to allocate memory for queue pair ptrs.\n");
425 goto fail_qpair_map;
426 }
d7459527
MH		 427 }
428
9a347ff4
CD		 429 /*
430 * Make sure we record at least the request and response queue zero in
431 * case we need to free them if part of the probe fails.
432 */
433 ha->rsp_q_map[0] = rsp;
434 ha->req_q_map[0] = req;
73208dfd
AC		 435 set_bit(0, ha->rsp_qid_map);
436 set_bit(0, ha->req_qid_map);
6a2cf8d3 437 return 0;
73208dfd 438
d7459527 439fail_qpair_map:
82de802a
QT		 440 kfree(ha->base_qpair);
441 ha->base_qpair = NULL;
442fail_base_qpair:
d7459527
MH		 443 kfree(ha->rsp_q_map);
444 ha->rsp_q_map = NULL;
73208dfd
AC		 445fail_rsp_map:
446 kfree(ha->req_q_map);
447 ha->req_q_map = NULL;
448fail_req_map:
449 return -ENOMEM;
450}
451
2afa19a9 452static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 453{
8ae6d9c7
GM		 454 if (IS_QLAFX00(ha)) {
455 if (req && req->ring_fx00)
456 dma_free_coherent(&ha->pdev->dev,
457 (req->length_fx00 + 1) * sizeof(request_t),
458 req->ring_fx00, req->dma_fx00);
459 } else if (req && req->ring)
73208dfd
AC		 460 dma_free_coherent(&ha->pdev->dev,
461 (req->length + 1) * sizeof(request_t),
462 req->ring, req->dma);
463
6d634067 464 if (req)
8d93f550 465 kfree(req->outstanding_cmds);
6d634067
BK		 466
467 kfree(req);
73208dfd
AC		 468}
469
2afa19a9
AC		 470static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
471{
8ae6d9c7 472 if (IS_QLAFX00(ha)) {
3f6c9be2 473 if (rsp && rsp->ring_fx00)
8ae6d9c7
GM		 474 dma_free_coherent(&ha->pdev->dev,
475 (rsp->length_fx00 + 1) * sizeof(request_t),
476 rsp->ring_fx00, rsp->dma_fx00);
477 } else if (rsp && rsp->ring) {
2afa19a9
AC		 478 dma_free_coherent(&ha->pdev->dev,
479 (rsp->length + 1) * sizeof(response_t),
480 rsp->ring, rsp->dma);
8ae6d9c7 481 }
6d634067 482 kfree(rsp);
2afa19a9
AC		 483}
484
73208dfd
AC		 485static void qla2x00_free_queues(struct qla_hw_data *ha)
486{
487 struct req_que *req;
488 struct rsp_que *rsp;
489 int cnt;
093df737 490 unsigned long flags;
73208dfd 491
82de802a
QT		 492 if (ha->queue_pair_map) {
493 kfree(ha->queue_pair_map);
494 ha->queue_pair_map = NULL;
495 }
496 if (ha->base_qpair) {
497 kfree(ha->base_qpair);
498 ha->base_qpair = NULL;
499 }
500
093df737 501 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 502 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 503 if (!test_bit(cnt, ha->req_qid_map))
504 continue;
505
73208dfd 506 req = ha->req_q_map[cnt];
093df737
QT		 507 clear_bit(cnt, ha->req_qid_map);
508 ha->req_q_map[cnt] = NULL;
509
510 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 511 qla2x00_free_req_que(ha, req);
093df737 512 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 513 }
093df737
QT		 514 spin_unlock_irqrestore(&ha->hardware_lock, flags);
515
73208dfd
AC		 516 kfree(ha->req_q_map);
517 ha->req_q_map = NULL;
2afa19a9 518
093df737
QT		 519
520 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 521 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 522 if (!test_bit(cnt, ha->rsp_qid_map))
523 continue;
524
2afa19a9 525 rsp = ha->rsp_q_map[cnt];
c3c42394 526 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 527 ha->rsp_q_map[cnt] = NULL;
528 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 529 qla2x00_free_rsp_que(ha, rsp);
093df737 530 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 531 }
093df737
QT		 532 spin_unlock_irqrestore(&ha->hardware_lock, flags);
533
2afa19a9
AC		 534 kfree(ha->rsp_q_map);
535 ha->rsp_q_map = NULL;
73208dfd
AC		 536}
537
1da177e4 538static char *
e315cd28 539qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 540{
e315cd28 541 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 542 static char *pci_bus_modes[] = {
543 "33", "66", "100", "133",
544 };
545 uint16_t pci_bus;
546
547 strcpy(str, "PCI");
548 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
549 if (pci_bus) {
550 strcat(str, "-X (");
551 strcat(str, pci_bus_modes[pci_bus]);
552 } else {
553 pci_bus = (ha->pci_attr & BIT_8) >> 8;
554 strcat(str, " (");
555 strcat(str, pci_bus_modes[pci_bus]);
556 }
557 strcat(str, " MHz)");
558
559 return (str);
560}
561
fca29703 562static char *
e315cd28 563qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 564{
565 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 566 struct qla_hw_data *ha = vha->hw;
fca29703 567 uint32_t pci_bus;
fca29703 568
62a276f8 569 if (pci_is_pcie(ha->pdev)) {
fca29703 570 char lwstr[6];
62a276f8 571 uint32_t lstat, lspeed, lwidth;
fca29703 572
62a276f8
BH		 573 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
574 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
575 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 576
577 strcpy(str, "PCIe (");
49300af7
SK		 578 switch (lspeed) {
579 case 1:
c87a0d8c 580 strcat(str, "2.5GT/s ");
49300af7
SK		 581 break;
582 case 2:
c87a0d8c 583 strcat(str, "5.0GT/s ");
49300af7
SK		 584 break;
585 case 3:
586 strcat(str, "8.0GT/s ");
587 break;
588 default:
fca29703 589 strcat(str, "<unknown> ");
49300af7
SK		 590 break;
591 }
fca29703
AV		 592 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
593 strcat(str, lwstr);
594
595 return str;
596 }
597
598 strcpy(str, "PCI");
599 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
600 if (pci_bus == 0 || pci_bus == 8) {
601 strcat(str, " (");
602 strcat(str, pci_bus_modes[pci_bus >> 3]);
603 } else {
604 strcat(str, "-X ");
605 if (pci_bus & BIT_2)
606 strcat(str, "Mode 2");
607 else
608 strcat(str, "Mode 1");
609 strcat(str, " (");
610 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
611 }
612 strcat(str, " MHz)");
613
614 return str;
615}
616
e5f82ab8 617static char *
df57caba 618qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 619{
620 char un_str[10];
e315cd28 621 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 622
df57caba
HM		 623 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
624 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 625
626 if (ha->fw_attributes & BIT_9) {
627 strcat(str, "FLX");
628 return (str);
629 }
630
631 switch (ha->fw_attributes & 0xFF) {
632 case 0x7:
633 strcat(str, "EF");
634 break;
635 case 0x17:
636 strcat(str, "TP");
637 break;
638 case 0x37:
639 strcat(str, "IP");
640 break;
641 case 0x77:
642 strcat(str, "VI");
643 break;
644 default:
645 sprintf(un_str, "(%x)", ha->fw_attributes);
646 strcat(str, un_str);
647 break;
648 }
649 if (ha->fw_attributes & 0x100)
650 strcat(str, "X");
651
652 return (str);
653}
654
e5f82ab8 655static char *
df57caba 656qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 657{
e315cd28 658 struct qla_hw_data *ha = vha->hw;
f0883ac6 659
df57caba 660 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 661 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 662 return str;
fca29703
AV		 663}
664
9ba56b95 665void
25ff6af1 666qla2x00_sp_free_dma(void *ptr)
fca29703 667{
25ff6af1
JC		 668 srb_t *sp = ptr;
669 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 670 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 671 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 672
9ba56b95
GM		 673 if (sp->flags & SRB_DMA_VALID) {
674 scsi_dma_unmap(cmd);
675 sp->flags &= ~SRB_DMA_VALID;
7c3df132 676 }
fca29703 677
9ba56b95
GM		 678 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
679 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
680 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
681 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
682 }
683
d5ff0eed 684 if (!ctx)
711a08d7 685 return;
d5ff0eed 686
9ba56b95
GM		 687 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
688 /* List assured to be having elements */
d5ff0eed 689 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 690 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
691 }
692
693 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 694 struct crc_context *ctx0 = ctx;
695
696 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 697 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
698 }
699
700 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 701 struct ct6_dsd *ctx1 = ctx;
fca29703 702
9ba56b95 703 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 704 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 705 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
706 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
707 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
708 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95 709 }
9ba56b95
GM		 710}
711
d7459527 712void
25ff6af1 713qla2x00_sp_compl(void *ptr, int res)
9ba56b95 714{
25ff6af1 715 srb_t *sp = ptr;
9ba56b95 716 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 717 struct completion *comp = sp->comp;
9ba56b95 718
db4bf822 719 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
9ba56b95 720 return;
219d27d7
BVA		 721
722 atomic_dec(&sp->ref_count);
9ba56b95 723
f3caa990 724 sp->free(sp);
740e2935 725 cmd->result = res;
711a08d7 726 CMD_SP(cmd) = NULL;
9ba56b95 727 cmd->scsi_done(cmd);
219d27d7
BVA		 728 if (comp)
729 complete(comp);
711a08d7 730 qla2x00_rel_sp(sp);
fca29703
AV		 731}
732
d7459527 733void
25ff6af1 734qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 735{
736 srb_t *sp = (srb_t *)ptr;
737 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
738 struct qla_hw_data *ha = sp->fcport->vha->hw;
739 void *ctx = GET_CMD_CTX_SP(sp);
740
741 if (sp->flags & SRB_DMA_VALID) {
742 scsi_dma_unmap(cmd);
743 sp->flags &= ~SRB_DMA_VALID;
744 }
745
746 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
747 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
748 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
749 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
750 }
751
d5ff0eed 752 if (!ctx)
711a08d7 753 return;
d5ff0eed 754
d7459527
MH		 755 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
756 /* List assured to be having elements */
d5ff0eed 757 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 758 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
759 }
760
50b81275 761 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) {
d8f945bf 762 struct crc_context *difctx = ctx;
50b81275
GM		 763 struct dsd_dma *dif_dsd, *nxt_dsd;
764
765 list_for_each_entry_safe(dif_dsd, nxt_dsd,
766 &difctx->ldif_dma_hndl_list, list) {
767 list_del(&dif_dsd->list);
768 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr,
769 dif_dsd->dsd_list_dma);
770 kfree(dif_dsd);
771 difctx->no_dif_bundl--;
772 }
773
774 list_for_each_entry_safe(dif_dsd, nxt_dsd,
775 &difctx->ldif_dsd_list, list) {
776 list_del(&dif_dsd->list);
777 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr,
778 dif_dsd->dsd_list_dma);
779 kfree(dif_dsd);
780 difctx->no_ldif_dsd--;
781 }
782
783 if (difctx->no_ldif_dsd) {
784 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
785 "%s: difctx->no_ldif_dsd=%x\n",
786 __func__, difctx->no_ldif_dsd);
787 }
788
789 if (difctx->no_dif_bundl) {
790 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022,
791 "%s: difctx->no_dif_bundl=%x\n",
792 __func__, difctx->no_dif_bundl);
793 }
794 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID;
d7459527 795 }
d8f945bf
BVA		 796
797 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
798 struct ct6_dsd *ctx1 = ctx;
799
800 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
801 ctx1->fcp_cmnd_dma);
802 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
803 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
804 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
805 mempool_free(ctx1, ha->ctx_mempool);
806 sp->flags &= ~SRB_FCP_CMND_DMA_VALID;
807 }
808
809 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
810 struct crc_context *ctx0 = ctx;
811
812 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
813 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
814 }
d7459527
MH		 815}
816
817void
25ff6af1 818qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 819{
25ff6af1 820 srb_t *sp = ptr;
d7459527 821 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
219d27d7 822 struct completion *comp = sp->comp;
d7459527 823
db4bf822 824 if (WARN_ON_ONCE(atomic_read(&sp->ref_count) == 0))
d7459527 825 return;
219d27d7
BVA		 826
827 atomic_dec(&sp->ref_count);
d7459527 828
f3caa990 829 sp->free(sp);
711a08d7
GM		 830 cmd->result = res;
831 CMD_SP(cmd) = NULL;
d7459527 832 cmd->scsi_done(cmd);
219d27d7
BVA		 833 if (comp)
834 complete(comp);
711a08d7 835 qla2xxx_rel_qpair_sp(sp->qpair, sp);
d7459527
MH		 836}
837
1da177e4 838static int
f5e3e40b 839qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 840{
134ae078 841 scsi_qla_host_t *vha = shost_priv(host);
fca29703 842 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 843 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 844 struct qla_hw_data *ha = vha->hw;
845 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 846 srb_t *sp;
847 int rval;
5601236b
MH		 848 struct qla_qpair *qpair = NULL;
849 uint32_t tag;
850 uint16_t hwq;
fca29703 851
2dbb02fd
BVA		 852 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) ||
853 WARN_ON_ONCE(!rport)) {
04dfaa53
MFO		 854 cmd->result = DID_NO_CONNECT << 16;
855 goto qc24_fail_command;
856 }
857
5601236b 858 if (ha->mqenable) {
f664a3cc
JA		 859 tag = blk_mq_unique_tag(cmd->request);
860 hwq = blk_mq_unique_tag_to_hwq(tag);
861 qpair = ha->queue_pair_map[hwq];
5601236b
MH		 862
863 if (qpair)
864 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 865 }
866
85880801 867 if (ha->flags.eeh_busy) {
7c3df132 868 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 869 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 870 "PCI Channel IO permanent failure, exiting "
871 "cmd=%p.\n", cmd);
b9b12f73 872 cmd->result = DID_NO_CONNECT << 16;
7c3df132 873 } else {
5f28d2d7 874 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 875 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 876 cmd->result = DID_REQUEUE << 16;
7c3df132 877 }
14e660e6
SJ		 878 goto qc24_fail_command;
879 }
880
19a7b4ae
JSEC		 881 rval = fc_remote_port_chkready(rport);
882 if (rval) {
883 cmd->result = rval;
5f28d2d7 884 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 885 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
886 cmd, rval);
fca29703
AV		 887 goto qc24_fail_command;
888 }
889
bad75002
AE		 890 if (!vha->flags.difdix_supported &&
891 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 892 ql_dbg(ql_dbg_io, vha, 0x3004,
893 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
894 cmd);
bad75002
AE		 895 cmd->result = DID_NO_CONNECT << 16;
896 goto qc24_fail_command;
897 }
aa651be8
CD		 898
899 if (!fcport) {
900 cmd->result = DID_NO_CONNECT << 16;
901 goto qc24_fail_command;
902 }
903
fca29703
AV		 904 if (atomic_read(&fcport->state) != FCS_ONLINE) {
905 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 906 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 907 ql_dbg(ql_dbg_io, vha, 0x3005,
908 "Returning DNC, fcport_state=%d loop_state=%d.\n",
909 atomic_read(&fcport->state),
910 atomic_read(&base_vha->loop_state));
fca29703
AV		 911 cmd->result = DID_NO_CONNECT << 16;
912 goto qc24_fail_command;
913 }
7b594131 914 goto qc24_target_busy;
fca29703
AV		 915 }
916
e05fe292
CD		 917 /*
918 * Return target busy if we've received a non-zero retry_delay_timer
919 * in a FCP_RSP.
920 */
975f7d46
BP		 921 if (fcport->retry_delay_timestamp == 0) {
922 /* retry delay not set */
923 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 924 fcport->retry_delay_timestamp = 0;
925 else
926 goto qc24_target_busy;
927
b00ee7d7 928 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 929 if (!sp)
f5e3e40b 930 goto qc24_host_busy;
fca29703 931
9ba56b95
GM		 932 sp->u.scmd.cmd = cmd;
933 sp->type = SRB_SCSI_CMD;
934 atomic_set(&sp->ref_count, 1);
935 CMD_SP(cmd) = (void *)sp;
936 sp->free = qla2x00_sp_free_dma;
937 sp->done = qla2x00_sp_compl;
938
e315cd28 939 rval = ha->isp_ops->start_scsi(sp);
7c3df132 940 if (rval != QLA_SUCCESS) {
53016ed3 941 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 942 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 943 goto qc24_host_busy_free_sp;
7c3df132 944 }
fca29703 945
fca29703
AV		 946 return 0;
947
948qc24_host_busy_free_sp:
f3caa990 949 sp->free(sp);
fca29703 950
f5e3e40b 951qc24_host_busy:
fca29703
AV		 952 return SCSI_MLQUEUE_HOST_BUSY;
953
7b594131
MC		 954qc24_target_busy:
955 return SCSI_MLQUEUE_TARGET_BUSY;
956
fca29703 957qc24_fail_command:
f5e3e40b 958 cmd->scsi_done(cmd);
fca29703
AV		 959
960 return 0;
961}
962
d7459527
MH		 963/* For MQ supported I/O */
964int
965qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
966 struct qla_qpair *qpair)
967{
968 scsi_qla_host_t *vha = shost_priv(host);
969 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
970 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
971 struct qla_hw_data *ha = vha->hw;
972 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
973 srb_t *sp;
974 int rval;
975
2dbb02fd 976 rval = rport ? fc_remote_port_chkready(rport) : FC_PORTSTATE_OFFLINE;
d7459527
MH		 977 if (rval) {
978 cmd->result = rval;
979 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
980 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
981 cmd, rval);
982 goto qc24_fail_command;
983 }
984
985 if (!fcport) {
986 cmd->result = DID_NO_CONNECT << 16;
987 goto qc24_fail_command;
988 }
989
990 if (atomic_read(&fcport->state) != FCS_ONLINE) {
991 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
992 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
993 ql_dbg(ql_dbg_io, vha, 0x3077,
994 "Returning DNC, fcport_state=%d loop_state=%d.\n",
995 atomic_read(&fcport->state),
996 atomic_read(&base_vha->loop_state));
997 cmd->result = DID_NO_CONNECT << 16;
998 goto qc24_fail_command;
999 }
1000 goto qc24_target_busy;
1001 }
1002
1003 /*
1004 * Return target busy if we've received a non-zero retry_delay_timer
1005 * in a FCP_RSP.
1006 */
1007 if (fcport->retry_delay_timestamp == 0) {
1008 /* retry delay not set */
1009 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1010 fcport->retry_delay_timestamp = 0;
1011 else
1012 goto qc24_target_busy;
1013
6a629468 1014 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
d7459527
MH		 1015 if (!sp)
1016 goto qc24_host_busy;
1017
1018 sp->u.scmd.cmd = cmd;
1019 sp->type = SRB_SCSI_CMD;
1020 atomic_set(&sp->ref_count, 1);
1021 CMD_SP(cmd) = (void *)sp;
1022 sp->free = qla2xxx_qpair_sp_free_dma;
1023 sp->done = qla2xxx_qpair_sp_compl;
1024 sp->qpair = qpair;
1025
1026 rval = ha->isp_ops->start_scsi_mq(sp);
1027 if (rval != QLA_SUCCESS) {
1028 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1029 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1030 if (rval == QLA_INTERFACE_ERROR)
1031 goto qc24_fail_command;
1032 goto qc24_host_busy_free_sp;
1033 }
1034
1035 return 0;
1036
1037qc24_host_busy_free_sp:
f3caa990 1038 sp->free(sp);
d7459527
MH		 1039
1040qc24_host_busy:
1041 return SCSI_MLQUEUE_HOST_BUSY;
1042
1043qc24_target_busy:
1044 return SCSI_MLQUEUE_TARGET_BUSY;
1045
1046qc24_fail_command:
1047 cmd->scsi_done(cmd);
1048
1049 return 0;
1050}
1051
1da177e4
LT		 1052/*
1053 * qla2x00_eh_wait_on_command
1054 * Waits for the command to be returned by the Firmware for some
1055 * max time.
1056 *
1057 * Input:
1da177e4 1058 * cmd = Scsi Command to wait on.
1da177e4
LT		 1059 *
1060 * Return:
1061 * Not Found : 0
1062 * Found : 1
1063 */
1064static int
e315cd28 1065qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1066{
fe74c71f 1067#define ABORT_POLLING_PERIOD 1000
478c3b03 1068#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1069 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1070 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1071 struct qla_hw_data *ha = vha->hw;
f4f051eb 1072 int ret = QLA_SUCCESS;
1da177e4 1073
85880801 1074 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1075 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1076 "Return:eh_wait.\n");
85880801
AV		 1077 return ret;
1078 }
1079
d970432c 1080 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1081 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1082 }
1083 if (CMD_SP(cmd))
1084 ret = QLA_FUNCTION_FAILED;
1da177e4 1085
f4f051eb 1086 return ret;
1da177e4
LT		 1087}
1088
1089/*
1090 * qla2x00_wait_for_hba_online
fa2a1ce5 1091 * Wait till the HBA is online after going through
1da177e4
LT		 1092 * <= MAX_RETRIES_OF_ISP_ABORT or
1093 * finally HBA is disabled ie marked offline
1094 *
1095 * Input:
1096 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1097 *
1098 * Note:
1da177e4
LT		 1099 * Does context switching-Release SPIN_LOCK
1100 * (if any) before calling this routine.
1101 *
1102 * Return:
1103 * Success (Adapter is online) : 0
1104 * Failed (Adapter is offline/disabled) : 1
1105 */
854165f4 1106int
e315cd28 1107qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1108{
fca29703
AV		 1109 int return_status;
1110 unsigned long wait_online;
e315cd28
AC		 1111 struct qla_hw_data *ha = vha->hw;
1112 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1113
fa2a1ce5 1114 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1115 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1116 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1117 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1118 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1119
1120 msleep(1000);
1121 }
e315cd28 1122 if (base_vha->flags.online)
fa2a1ce5 1123 return_status = QLA_SUCCESS;
1da177e4
LT		 1124 else
1125 return_status = QLA_FUNCTION_FAILED;
1126
1da177e4
LT		 1127 return (return_status);
1128}
1129
726b8548
QT		 1130static inline int test_fcport_count(scsi_qla_host_t *vha)
1131{
1132 struct qla_hw_data *ha = vha->hw;
1133 unsigned long flags;
1134 int res;
1135
1136 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1137 ql_dbg(ql_dbg_init, vha, 0x00ec,
1138 "tgt %p, fcport_count=%d\n",
1139 vha, vha->fcport_count);
726b8548
QT		 1140 res = (vha->fcport_count == 0);
1141 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1142
1143 return res;
1144}
1145
1146/*
1147 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1148 * it has dependency on UNLOADING flag to stop device discovery
1149 */
efa93f48 1150void
726b8548
QT		 1151qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1152{
1153 qla2x00_mark_all_devices_lost(vha, 0);
1154
b85e0957 1155 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
cd4fb33f 1156 flush_workqueue(vha->hw->wq);
726b8548
QT		 1157}
1158
86fbee86 1159/*
638a1a01
SC		 1160 * qla2x00_wait_for_hba_ready
1161 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1162 *
1163 * Input:
1164 * ha - pointer to host adapter structure
1165 *
1166 * Note:
1167 * Does context switching-Release SPIN_LOCK
1168 * (if any) before calling this routine.
1169 *
86fbee86 1170 */
638a1a01
SC		 1171static void
1172qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1173{
86fbee86 1174 struct qla_hw_data *ha = vha->hw;
783e0dc4 1175 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1176
1d483901
DC		 1177 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1178 ha->flags.mbox_busy) ||
1179 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1180 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1181 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1182 break;
86fbee86 1183 msleep(1000);
783e0dc4 1184 }
86fbee86
LC		 1185}
1186
2533cf67
LC		 1187int
1188qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1189{
1190 int return_status;
1191 unsigned long wait_reset;
1192 struct qla_hw_data *ha = vha->hw;
1193 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1194
1195 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1196 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1197 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1198 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1199 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1200
1201 msleep(1000);
1202
1203 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1204 ha->flags.chip_reset_done)
1205 break;
1206 }
1207 if (ha->flags.chip_reset_done)
1208 return_status = QLA_SUCCESS;
1209 else
1210 return_status = QLA_FUNCTION_FAILED;
1211
1212 return return_status;
1213}
1214
585def9b 1215static int
083a469d
GM		 1216sp_get(struct srb *sp)
1217{
845bbb09 1218 if (!refcount_inc_not_zero((refcount_t *)&sp->ref_count))
585def9b
QT		 1219 /* kref get fail */
1220 return ENXIO;
1221 else
1222 return 0;
083a469d
GM		 1223}
1224
a465537a
SC		 1225#define ISP_REG_DISCONNECT 0xffffffffU
1226/**************************************************************************
1227* qla2x00_isp_reg_stat
1228*
1229* Description:
1230* Read the host status register of ISP before aborting the command.
1231*
1232* Input:
1233* ha = pointer to host adapter structure.
1234*
1235*
1236* Returns:
1237* Either true or false.
1238*
1239* Note: Return true if there is register disconnect.
1240**************************************************************************/
1241static inline
1242uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1243{
1244 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1245 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1246
bf6061b1
SC		 1247 if (IS_P3P_TYPE(ha))
1248 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1249 else
1250 return ((RD_REG_DWORD(&reg->host_status)) ==
1251 ISP_REG_DISCONNECT);
a465537a
SC		 1252}
1253
1da177e4
LT		 1254/**************************************************************************
1255* qla2xxx_eh_abort
1256*
1257* Description:
1258* The abort function will abort the specified command.
1259*
1260* Input:
1261* cmd = Linux SCSI command packet to be aborted.
1262*
1263* Returns:
1264* Either SUCCESS or FAILED.
1265*
1266* Note:
2ea00202 1267* Only return FAILED if command not returned by firmware.
1da177e4 1268**************************************************************************/
e5f82ab8 1269static int
1da177e4
LT		 1270qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1271{
e315cd28 1272 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1273 srb_t *sp;
4e98d3b8 1274 int ret;
9cb78c16
HR		 1275 unsigned int id;
1276 uint64_t lun;
18e144d3 1277 unsigned long flags;
219d27d7 1278 int rval;
e315cd28 1279 struct qla_hw_data *ha = vha->hw;
585def9b 1280 struct qla_qpair *qpair;
1da177e4 1281
a465537a
SC		 1282 if (qla2x00_isp_reg_stat(ha)) {
1283 ql_log(ql_log_info, vha, 0x8042,
1284 "PCI/Register disconnect, exiting.\n");
1285 return FAILED;
1286 }
1da177e4 1287
4e98d3b8
AV		 1288 ret = fc_block_scsi_eh(cmd);
1289 if (ret != 0)
1290 return ret;
4e98d3b8 1291
170babc3 1292 sp = (srb_t *) CMD_SP(cmd);
585def9b
QT		 1293 if (!sp)
1294 return SUCCESS;
1295
1296 qpair = sp->qpair;
1297 if (!qpair)
1298 return SUCCESS;
1299
1300 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
219d27d7 1301 if (sp->type != SRB_SCSI_CMD || GET_CMD_SP(sp) != cmd) {
585def9b
QT		 1302 /* there's a chance an interrupt could clear
1303 the ptr as part of done & free */
1304 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1305 return SUCCESS;
1306 }
1da177e4 1307
585def9b
QT		 1308 if (sp_get(sp)){
1309 /* ref_count is already 0 */
1310 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
170babc3
MC		 1311 return SUCCESS;
1312 }
585def9b
QT		 1313 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1314
1315 id = cmd->device->id;
1316 lun = cmd->device->lun;
1da177e4 1317
7c3df132 1318 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1319 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1320 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1321
f934c9d0 1322 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1323 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1324 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval);
f934c9d0 1325
219d27d7
BVA		 1326 switch (rval) {
1327 case QLA_SUCCESS:
711a08d7 1328 /*
219d27d7
BVA		 1329 * The command has been aborted. That means that the firmware
1330 * won't report a completion.
711a08d7 1331 */
219d27d7
BVA		 1332 sp->done(sp, DID_ABORT << 16);
1333 ret = SUCCESS;
1334 break;
1335 default:
1336 /*
1337 * Either abort failed or abort and completion raced. Let
1338 * the SCSI core retry the abort in the former case.
1339 */
1340 ret = FAILED;
1341 break;
1da177e4 1342 }
219d27d7 1343
7c3df132 1344 ql_log(ql_log_info, vha, 0x801c,
219d27d7
BVA		 1345 "Abort command issued nexus=%ld:%d:%llu -- %x.\n",
1346 vha->host_no, id, lun, ret);
1da177e4 1347
f4f051eb
AV		 1348 return ret;
1349}
1da177e4 1350
4d78c973 1351int
e315cd28 1352qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1353 uint64_t l, enum nexus_wait_type type)
f4f051eb 1354{
17d98630 1355 int cnt, match, status;
18e144d3 1356 unsigned long flags;
e315cd28 1357 struct qla_hw_data *ha = vha->hw;
73208dfd 1358 struct req_que *req;
4d78c973 1359 srb_t *sp;
9ba56b95 1360 struct scsi_cmnd *cmd;
1da177e4 1361
523ec773 1362 status = QLA_SUCCESS;
17d98630 1363
e315cd28 1364 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1365 req = vha->req;
17d98630 1366 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1367 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1368 sp = req->outstanding_cmds[cnt];
1369 if (!sp)
523ec773 1370 continue;
9ba56b95 1371 if (sp->type != SRB_SCSI_CMD)
cf53b069 1372 continue;
25ff6af1 1373 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1374 continue;
1375 match = 0;
9ba56b95 1376 cmd = GET_CMD_SP(sp);
17d98630
AC		 1377 switch (type) {
1378 case WAIT_HOST:
1379 match = 1;
1380 break;
1381 case WAIT_TARGET:
9ba56b95 1382 match = cmd->device->id == t;
17d98630
AC		 1383 break;
1384 case WAIT_LUN:
9ba56b95
GM		 1385 match = (cmd->device->id == t &&
1386 cmd->device->lun == l);
17d98630 1387 break;
73208dfd 1388 }
17d98630
AC		 1389 if (!match)
1390 continue;
1391
1392 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1393 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1394 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1395 }
e315cd28 1396 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1397
1398 return status;
1da177e4
LT		 1399}
1400
523ec773
AV		 1401static char *reset_errors[] = {
1402 "HBA not online",
1403 "HBA not ready",
1404 "Task management failed",
1405 "Waiting for command completions",
1406};
1da177e4 1407
e5f82ab8 1408static int
523ec773 1409__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1410 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1411{
e315cd28 1412 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1413 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1414 int err;
1da177e4 1415
7c3df132 1416 if (!fcport) {
523ec773 1417 return FAILED;
7c3df132 1418 }
1da177e4 1419
4e98d3b8
AV		 1420 err = fc_block_scsi_eh(cmd);
1421 if (err != 0)
1422 return err;
1423
7c3df132 1424 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1425 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1426 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1427
523ec773 1428 err = 0;
7c3df132
SK		 1429 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1430 ql_log(ql_log_warn, vha, 0x800a,
1431 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1432 goto eh_reset_failed;
7c3df132 1433 }
523ec773 1434 err = 2;
ac444b4f 1435 if (do_reset(fcport, cmd->device->lun, 1)
7c3df132
SK		 1436 != QLA_SUCCESS) {
1437 ql_log(ql_log_warn, vha, 0x800c,
1438 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1439 goto eh_reset_failed;
7c3df132 1440 }
523ec773 1441 err = 3;
e315cd28 1442 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1443 cmd->device->lun, type) != QLA_SUCCESS) {
1444 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1445 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1446 goto eh_reset_failed;
7c3df132 1447 }
523ec773 1448
7c3df132 1449 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1450 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1451 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1452
1453 return SUCCESS;
1454
4d78c973 1455eh_reset_failed:
7c3df132 1456 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1457 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1458 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1459 cmd);
523ec773
AV		 1460 return FAILED;
1461}
1da177e4 1462
523ec773
AV		 1463static int
1464qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1465{
e315cd28
AC		 1466 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1467 struct qla_hw_data *ha = vha->hw;
1da177e4 1468
a465537a
SC		 1469 if (qla2x00_isp_reg_stat(ha)) {
1470 ql_log(ql_log_info, vha, 0x803e,
1471 "PCI/Register disconnect, exiting.\n");
1472 return FAILED;
1473 }
1474
523ec773
AV		 1475 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1476 ha->isp_ops->lun_reset);
1da177e4
LT		 1477}
1478
1da177e4 1479static int
523ec773 1480qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1481{
e315cd28
AC		 1482 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1483 struct qla_hw_data *ha = vha->hw;
1da177e4 1484
a465537a
SC		 1485 if (qla2x00_isp_reg_stat(ha)) {
1486 ql_log(ql_log_info, vha, 0x803f,
1487 "PCI/Register disconnect, exiting.\n");
1488 return FAILED;
1489 }
1490
523ec773
AV		 1491 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1492 ha->isp_ops->target_reset);
1da177e4
LT		 1493}
1494
1da177e4
LT		 1495/**************************************************************************
1496* qla2xxx_eh_bus_reset
1497*
1498* Description:
1499* The bus reset function will reset the bus and abort any executing
1500* commands.
1501*
1502* Input:
1503* cmd = Linux SCSI command packet of the command that cause the
1504* bus reset.
1505*
1506* Returns:
1507* SUCCESS/FAILURE (defined as macro in scsi.h).
1508*
1509**************************************************************************/
e5f82ab8 1510static int
1da177e4
LT		 1511qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1512{
e315cd28 1513 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1514 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1515 int ret = FAILED;
9cb78c16
HR		 1516 unsigned int id;
1517 uint64_t lun;
a465537a
SC		 1518 struct qla_hw_data *ha = vha->hw;
1519
1520 if (qla2x00_isp_reg_stat(ha)) {
1521 ql_log(ql_log_info, vha, 0x8040,
1522 "PCI/Register disconnect, exiting.\n");
1523 return FAILED;
1524 }
f4f051eb 1525
f4f051eb
AV		 1526 id = cmd->device->id;
1527 lun = cmd->device->lun;
1da177e4 1528
7c3df132 1529 if (!fcport) {
f4f051eb 1530 return ret;
7c3df132 1531 }
1da177e4 1532
4e98d3b8
AV		 1533 ret = fc_block_scsi_eh(cmd);
1534 if (ret != 0)
1535 return ret;
1536 ret = FAILED;
1537
7c3df132 1538 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1539 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1540
e315cd28 1541 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1542 ql_log(ql_log_fatal, vha, 0x8013,
1543 "Wait for hba online failed board disabled.\n");
f4f051eb 1544 goto eh_bus_reset_done;
1da177e4
LT		 1545 }
1546
ad537689
SK		 1547 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1548 ret = SUCCESS;
1549
f4f051eb
AV		 1550 if (ret == FAILED)
1551 goto eh_bus_reset_done;
1da177e4 1552
9a41a62b 1553 /* Flush outstanding commands. */
4d78c973 1554 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1555 QLA_SUCCESS) {
1556 ql_log(ql_log_warn, vha, 0x8014,
1557 "Wait for pending commands failed.\n");
9a41a62b 1558 ret = FAILED;
7c3df132 1559 }
1da177e4 1560
f4f051eb 1561eh_bus_reset_done:
7c3df132 1562 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1563 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1564 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1565
f4f051eb 1566 return ret;
1da177e4
LT		 1567}
1568
1569/**************************************************************************
1570* qla2xxx_eh_host_reset
1571*
1572* Description:
1573* The reset function will reset the Adapter.
1574*
1575* Input:
1576* cmd = Linux SCSI command packet of the command that cause the
1577* adapter reset.
1578*
1579* Returns:
1580* Either SUCCESS or FAILED.
1581*
1582* Note:
1583**************************************************************************/
e5f82ab8 1584static int
1da177e4
LT		 1585qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1586{
e315cd28 1587 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1588 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1589 int ret = FAILED;
9cb78c16
HR		 1590 unsigned int id;
1591 uint64_t lun;
e315cd28 1592 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1593
a465537a
SC		 1594 if (qla2x00_isp_reg_stat(ha)) {
1595 ql_log(ql_log_info, vha, 0x8041,
1596 "PCI/Register disconnect, exiting.\n");
1597 schedule_work(&ha->board_disable);
1598 return SUCCESS;
1599 }
1600
f4f051eb
AV		 1601 id = cmd->device->id;
1602 lun = cmd->device->lun;
f4f051eb 1603
7c3df132 1604 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1605 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1606
63ee7072
CD		 1607 /*
1608 * No point in issuing another reset if one is active. Also do not
1609 * attempt a reset if we are updating flash.
1610 */
1611 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1612 goto eh_host_reset_lock;
1da177e4 1613
e315cd28
AC		 1614 if (vha != base_vha) {
1615 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1616 goto eh_host_reset_lock;
e315cd28 1617 } else {
7ec0effd 1618 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1619 if (!qla82xx_fcoe_ctx_reset(vha)) {
1620 /* Ctx reset success */
1621 ret = SUCCESS;
1622 goto eh_host_reset_lock;
1623 }
1624 /* fall thru if ctx reset failed */
1625 }
68ca949c
AC		 1626 if (ha->wq)
1627 flush_workqueue(ha->wq);
1628
e315cd28 1629 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1630 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1631 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1632 /* failed. schedule dpc to try */
1633 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1634
7c3df132
SK		 1635 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1636 ql_log(ql_log_warn, vha, 0x802a,
1637 "wait for hba online failed.\n");
e315cd28 1638 goto eh_host_reset_lock;
7c3df132 1639 }
e315cd28
AC		 1640 }
1641 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1642 }
1da177e4 1643
e315cd28 1644 /* Waiting for command to be returned to OS.*/
4d78c973 1645 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1646 QLA_SUCCESS)
f4f051eb 1647 ret = SUCCESS;
1da177e4 1648
f4f051eb 1649eh_host_reset_lock:
cfb0919c 1650 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1651 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1652 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1653
f4f051eb
AV		 1654 return ret;
1655}
1da177e4
LT		 1656
1657/*
1658* qla2x00_loop_reset
1659* Issue loop reset.
1660*
1661* Input:
1662* ha = adapter block pointer.
1663*
1664* Returns:
1665* 0 = success
1666*/
a4722cf2 1667int
e315cd28 1668qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1669{
0c8c39af 1670 int ret;
bdf79621 1671 struct fc_port *fcport;
e315cd28 1672 struct qla_hw_data *ha = vha->hw;
1da177e4 1673
5854771e
AB		 1674 if (IS_QLAFX00(ha)) {
1675 return qlafx00_loop_reset(vha);
1676 }
1677
f4c496c1 1678 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1679 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1680 if (fcport->port_type != FCT_TARGET)
1681 continue;
1682
1683 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1684 if (ret != QLA_SUCCESS) {
7c3df132 1685 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1686 "Bus Reset failed: Reset=%d "
7c3df132 1687 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1688 }
1689 }
1690 }
1691
8ae6d9c7 1692
6246b8a1 1693 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1694 atomic_set(&vha->loop_state, LOOP_DOWN);
1695 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1696 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1697 ret = qla2x00_full_login_lip(vha);
0c8c39af 1698 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1699 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1700 "full_login_lip=%d.\n", ret);
749af3d5 1701 }
0c8c39af
AV		 1702 }
1703
0d6e61bc 1704 if (ha->flags.enable_lip_reset) {
e315cd28 1705 ret = qla2x00_lip_reset(vha);
ad537689 1706 if (ret != QLA_SUCCESS)
7c3df132
SK		 1707 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1708 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1709 }
1710
1da177e4 1711 /* Issue marker command only when we are going to start the I/O */
e315cd28 1712 vha->marker_needed = 1;
1da177e4 1713
0c8c39af 1714 return QLA_SUCCESS;
1da177e4
LT		 1715}
1716
c4e521b6
BVA		 1717static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1718 unsigned long *flags)
1719 __releases(qp->qp_lock_ptr)
1720 __acquires(qp->qp_lock_ptr)
1721{
219d27d7 1722 DECLARE_COMPLETION_ONSTACK(comp);
c4e521b6
BVA		 1723 scsi_qla_host_t *vha = qp->vha;
1724 struct qla_hw_data *ha = vha->hw;
219d27d7 1725 int rval;
c4e521b6 1726
219d27d7
BVA		 1727 if (sp_get(sp))
1728 return;
1729
1730 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS ||
1731 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy &&
1732 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1733 !qla2x00_isp_reg_stat(ha))) {
1734 sp->comp = &comp;
219d27d7 1735 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
5589b08e 1736 rval = ha->isp_ops->abort_command(sp);
219d27d7
BVA		 1737
1738 switch (rval) {
1739 case QLA_SUCCESS:
1740 sp->done(sp, res);
1741 break;
1742 case QLA_FUNCTION_PARAMETER_ERROR:
1743 wait_for_completion(&comp);
1744 break;
c4e521b6 1745 }
219d27d7
BVA		 1746
1747 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1748 sp->comp = NULL;
c4e521b6 1749 }
c4e521b6
BVA		 1750}
1751
bbead493
QT		 1752static void
1753__qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
df4bf0bb 1754{
eb023220 1755 int cnt;
df4bf0bb
AV		 1756 unsigned long flags;
1757 srb_t *sp;
bbead493 1758 scsi_qla_host_t *vha = qp->vha;
e315cd28 1759 struct qla_hw_data *ha = vha->hw;
73208dfd 1760 struct req_que *req;
c5419e26
QT		 1761 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1762 struct qla_tgt_cmd *cmd;
c0cb4496 1763
6a2cf8d3
BK		 1764 if (!ha->req_q_map)
1765 return;
bbead493
QT		 1766 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1767 req = qp->req;
1768 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1769 sp = req->outstanding_cmds[cnt];
1770 if (sp) {
1771 req->outstanding_cmds[cnt] = NULL;
6b0431d6
QT		 1772 switch (sp->cmd_type) {
1773 case TYPE_SRB:
c4e521b6 1774 qla2x00_abort_srb(qp, sp, res, &flags);
585def9b
QT		 1775 break;
1776 case TYPE_TGT_CMD:
bbead493
QT		 1777 if (!vha->hw->tgt.tgt_ops || !tgt ||
1778 qla_ini_mode_enabled(vha)) {
585def9b
QT		 1779 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1780 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1781 vha->dpc_flags);
bbead493 1782 continue;
c733ab35 1783 }
bbead493 1784 cmd = (struct qla_tgt_cmd *)sp;
aefed3e5 1785 cmd->aborted = 1;
585def9b
QT		 1786 break;
1787 case TYPE_TGT_TMCMD:
aefed3e5 1788 /* Skip task management functions. */
585def9b
QT		 1789 break;
1790 default:
1791 break;
73208dfd 1792 }
df4bf0bb
AV		 1793 }
1794 }
bbead493
QT		 1795 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1796}
1797
1798void
1799qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1800{
1801 int que;
1802 struct qla_hw_data *ha = vha->hw;
1803
1804 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1805
1806 for (que = 0; que < ha->max_qpairs; que++) {
1807 if (!ha->queue_pair_map[que])
1808 continue;
1809
1810 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1811 }
df4bf0bb
AV		 1812}
1813
f4f051eb
AV		 1814static int
1815qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1816{
bdf79621 1817 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1818
19a7b4ae 1819 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1820 return -ENXIO;
bdf79621 1821
19a7b4ae 1822 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1823
f4f051eb
AV		 1824 return 0;
1825}
1da177e4 1826
f4f051eb
AV		 1827static int
1828qla2xxx_slave_configure(struct scsi_device *sdev)
1829{
e315cd28 1830 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1831 struct req_que *req = vha->req;
8482e118 1832
9e522cd8
AE		 1833 if (IS_T10_PI_CAPABLE(vha->hw))
1834 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1835
db5ed4df 1836 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1837 return 0;
1838}
1da177e4 1839
f4f051eb
AV		 1840static void
1841qla2xxx_slave_destroy(struct scsi_device *sdev)
1842{
1843 sdev->hostdata = NULL;
1da177e4
LT		 1844}
1845
1846/**
1847 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1848 * @ha: HA context
1849 *
1850 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1851 * supported addressing method.
1852 */
1853static void
53303c42 1854qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1855{
7524f9b9 1856 /* Assume a 32bit DMA mask. */
1da177e4 1857 ha->flags.enable_64bit_addressing = 0;
1da177e4 1858
6a35528a 1859 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1860 /* Any upper-dword bits set? */
1861 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1862 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1863 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1864 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1865 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1866 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1867 return;
1da177e4 1868 }
1da177e4 1869 }
7524f9b9 1870
284901a9
YH		 1871 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1872 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1873}
1874
fd34f556 1875static void
e315cd28 1876qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1877{
1878 unsigned long flags = 0;
1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1880
1881 spin_lock_irqsave(&ha->hardware_lock, flags);
1882 ha->interrupts_on = 1;
1883 /* enable risc and host interrupts */
1884 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1885 RD_REG_WORD(&reg->ictrl);
1886 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1887
1888}
1889
1890static void
e315cd28 1891qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1892{
1893 unsigned long flags = 0;
1894 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1895
1896 spin_lock_irqsave(&ha->hardware_lock, flags);
1897 ha->interrupts_on = 0;
1898 /* disable risc and host interrupts */
1899 WRT_REG_WORD(&reg->ictrl, 0);
1900 RD_REG_WORD(&reg->ictrl);
1901 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1902}
1903
1904static void
e315cd28 1905qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1906{
1907 unsigned long flags = 0;
1908 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1909
1910 spin_lock_irqsave(&ha->hardware_lock, flags);
1911 ha->interrupts_on = 1;
1912 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1913 RD_REG_DWORD(&reg->ictrl);
1914 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1915}
1916
1917static void
e315cd28 1918qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1919{
1920 unsigned long flags = 0;
1921 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1922
124f85e6
AV		 1923 if (IS_NOPOLLING_TYPE(ha))
1924 return;
fd34f556
AV		 1925 spin_lock_irqsave(&ha->hardware_lock, flags);
1926 ha->interrupts_on = 0;
1927 WRT_REG_DWORD(&reg->ictrl, 0);
1928 RD_REG_DWORD(&reg->ictrl);
1929 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1930}
1931
706f457d
GM		 1932static int
1933qla2x00_iospace_config(struct qla_hw_data *ha)
1934{
1935 resource_size_t pio;
1936 uint16_t msix;
706f457d 1937
706f457d
GM		 1938 if (pci_request_selected_regions(ha->pdev, ha->bars,
1939 QLA2XXX_DRIVER_NAME)) {
1940 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1941 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1942 pci_name(ha->pdev));
1943 goto iospace_error_exit;
1944 }
1945 if (!(ha->bars & 1))
1946 goto skip_pio;
1947
1948 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1949 pio = pci_resource_start(ha->pdev, 0);
1950 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1951 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1952 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1953 "Invalid pci I/O region size (%s).\n",
1954 pci_name(ha->pdev));
1955 pio = 0;
1956 }
1957 } else {
1958 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1959 "Region #0 no a PIO resource (%s).\n",
1960 pci_name(ha->pdev));
1961 pio = 0;
1962 }
1963 ha->pio_address = pio;
1964 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1965 "PIO address=%llu.\n",
1966 (unsigned long long)ha->pio_address);
1967
1968skip_pio:
1969 /* Use MMIO operations for all accesses. */
1970 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1971 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1972 "Region #1 not an MMIO resource (%s), aborting.\n",
1973 pci_name(ha->pdev));
1974 goto iospace_error_exit;
1975 }
1976 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1978 "Invalid PCI mem region size (%s), aborting.\n",
1979 pci_name(ha->pdev));
1980 goto iospace_error_exit;
1981 }
1982
1983 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1984 if (!ha->iobase) {
1985 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1986 "Cannot remap MMIO (%s), aborting.\n",
1987 pci_name(ha->pdev));
1988 goto iospace_error_exit;
1989 }
1990
1991 /* Determine queue resources */
1992 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1993 ha->msix_count = QLA_BASE_VECTORS;
c38d1baf
HM		 1994 if (!ql2xmqsupport || !ql2xnvmeenable ||
1995 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1996 goto mqiobase_exit;
1997
1998 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1999 pci_resource_len(ha->pdev, 3));
2000 if (ha->mqiobase) {
2001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2002 "MQIO Base=%p.\n", ha->mqiobase);
2003 /* Read MSIX vector size of the board */
2004 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 2005 ha->msix_count = msix + 1;
706f457d 2006 /* Max queues are bounded by available msix vectors */
d7459527
MH		 2007 /* MB interrupt uses 1 vector */
2008 ha->max_req_queues = ha->msix_count - 1;
2009 ha->max_rsp_queues = ha->max_req_queues;
2010 /* Queue pairs is the max value minus the base queue pair */
2011 ha->max_qpairs = ha->max_rsp_queues - 1;
2012 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2013 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2014
706f457d 2015 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 2016 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 2017 } else
2018 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2019 "BAR 3 not enabled.\n");
2020
2021mqiobase_exit:
706f457d 2022 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 2023 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 2024 return (0);
2025
2026iospace_error_exit:
2027 return (-ENOMEM);
2028}
2029
2030
6246b8a1
GM		 2031static int
2032qla83xx_iospace_config(struct qla_hw_data *ha)
2033{
2034 uint16_t msix;
6246b8a1
GM		 2035
2036 if (pci_request_selected_regions(ha->pdev, ha->bars,
2037 QLA2XXX_DRIVER_NAME)) {
2038 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2039 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2040 pci_name(ha->pdev));
2041
2042 goto iospace_error_exit;
2043 }
2044
2045 /* Use MMIO operations for all accesses. */
2046 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2047 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2048 "Invalid pci I/O region size (%s).\n",
2049 pci_name(ha->pdev));
2050 goto iospace_error_exit;
2051 }
2052 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2053 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2054 "Invalid PCI mem region size (%s), aborting\n",
2055 pci_name(ha->pdev));
2056 goto iospace_error_exit;
2057 }
2058
2059 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2060 if (!ha->iobase) {
2061 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2062 "Cannot remap MMIO (%s), aborting.\n",
2063 pci_name(ha->pdev));
2064 goto iospace_error_exit;
2065 }
2066
2067 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2068 /* 83XX 26XX always use MQ type access for queues
2069 * - mbar 2, a.k.a region 4 */
2070 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2071 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2072 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2073 pci_resource_len(ha->pdev, 4));
2074
2075 if (!ha->mqiobase) {
2076 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2077 "BAR2/region4 not enabled\n");
2078 goto mqiobase_exit;
2079 }
2080
2081 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2082 pci_resource_len(ha->pdev, 2));
2083 if (ha->msixbase) {
2084 /* Read MSIX vector size of the board */
2085 pci_read_config_word(ha->pdev,
2086 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2087 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2088 /*
2089 * By default, driver uses at least two msix vectors
2090 * (default & rspq)
2091 */
c38d1baf 2092 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 2093 /* MB interrupt uses 1 vector */
2094 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2095
2096 /* ATIOQ needs 1 vector. That's 1 less QPair */
2097 if (QLA_TGT_MODE_ENABLED())
2098 ha->max_req_queues--;
2099
d0d2c68b
MH		 2100 ha->max_rsp_queues = ha->max_req_queues;
2101
d7459527
MH		 2102 /* Queue pairs is the max value minus
2103 * the base queue pair */
2104 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2105 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2106 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2107 }
2108 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2109 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2110 } else
2111 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2112 "BAR 1 not enabled.\n");
2113
2114mqiobase_exit:
6246b8a1 2115 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2116 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2117 return 0;
2118
2119iospace_error_exit:
2120 return -ENOMEM;
2121}
2122
fd34f556
AV		 2123static struct isp_operations qla2100_isp_ops = {
2124 .pci_config = qla2100_pci_config,
2125 .reset_chip = qla2x00_reset_chip,
2126 .chip_diag = qla2x00_chip_diag,
2127 .config_rings = qla2x00_config_rings,
2128 .reset_adapter = qla2x00_reset_adapter,
2129 .nvram_config = qla2x00_nvram_config,
2130 .update_fw_options = qla2x00_update_fw_options,
2131 .load_risc = qla2x00_load_risc,
2132 .pci_info_str = qla2x00_pci_info_str,
2133 .fw_version_str = qla2x00_fw_version_str,
2134 .intr_handler = qla2100_intr_handler,
2135 .enable_intrs = qla2x00_enable_intrs,
2136 .disable_intrs = qla2x00_disable_intrs,
2137 .abort_command = qla2x00_abort_command,
523ec773
AV		 2138 .target_reset = qla2x00_abort_target,
2139 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2140 .fabric_login = qla2x00_login_fabric,
2141 .fabric_logout = qla2x00_fabric_logout,
2142 .calc_req_entries = qla2x00_calc_iocbs_32,
2143 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2144 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2145 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2146 .read_nvram = qla2x00_read_nvram_data,
2147 .write_nvram = qla2x00_write_nvram_data,
2148 .fw_dump = qla2100_fw_dump,
2149 .beacon_on = NULL,
2150 .beacon_off = NULL,
2151 .beacon_blink = NULL,
2152 .read_optrom = qla2x00_read_optrom_data,
2153 .write_optrom = qla2x00_write_optrom_data,
2154 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2155 .start_scsi = qla2x00_start_scsi,
d7459527 2156 .start_scsi_mq = NULL,
a9083016 2157 .abort_isp = qla2x00_abort_isp,
706f457d 2158 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2159 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2160};
2161
2162static struct isp_operations qla2300_isp_ops = {
2163 .pci_config = qla2300_pci_config,
2164 .reset_chip = qla2x00_reset_chip,
2165 .chip_diag = qla2x00_chip_diag,
2166 .config_rings = qla2x00_config_rings,
2167 .reset_adapter = qla2x00_reset_adapter,
2168 .nvram_config = qla2x00_nvram_config,
2169 .update_fw_options = qla2x00_update_fw_options,
2170 .load_risc = qla2x00_load_risc,
2171 .pci_info_str = qla2x00_pci_info_str,
2172 .fw_version_str = qla2x00_fw_version_str,
2173 .intr_handler = qla2300_intr_handler,
2174 .enable_intrs = qla2x00_enable_intrs,
2175 .disable_intrs = qla2x00_disable_intrs,
2176 .abort_command = qla2x00_abort_command,
523ec773
AV		 2177 .target_reset = qla2x00_abort_target,
2178 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2179 .fabric_login = qla2x00_login_fabric,
2180 .fabric_logout = qla2x00_fabric_logout,
2181 .calc_req_entries = qla2x00_calc_iocbs_32,
2182 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2183 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2184 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2185 .read_nvram = qla2x00_read_nvram_data,
2186 .write_nvram = qla2x00_write_nvram_data,
2187 .fw_dump = qla2300_fw_dump,
2188 .beacon_on = qla2x00_beacon_on,
2189 .beacon_off = qla2x00_beacon_off,
2190 .beacon_blink = qla2x00_beacon_blink,
2191 .read_optrom = qla2x00_read_optrom_data,
2192 .write_optrom = qla2x00_write_optrom_data,
2193 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2194 .start_scsi = qla2x00_start_scsi,
d7459527 2195 .start_scsi_mq = NULL,
a9083016 2196 .abort_isp = qla2x00_abort_isp,
7ec0effd 2197 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2198 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2199};
2200
2201static struct isp_operations qla24xx_isp_ops = {
2202 .pci_config = qla24xx_pci_config,
2203 .reset_chip = qla24xx_reset_chip,
2204 .chip_diag = qla24xx_chip_diag,
2205 .config_rings = qla24xx_config_rings,
2206 .reset_adapter = qla24xx_reset_adapter,
2207 .nvram_config = qla24xx_nvram_config,
2208 .update_fw_options = qla24xx_update_fw_options,
2209 .load_risc = qla24xx_load_risc,
2210 .pci_info_str = qla24xx_pci_info_str,
2211 .fw_version_str = qla24xx_fw_version_str,
2212 .intr_handler = qla24xx_intr_handler,
2213 .enable_intrs = qla24xx_enable_intrs,
2214 .disable_intrs = qla24xx_disable_intrs,
2215 .abort_command = qla24xx_abort_command,
523ec773
AV		 2216 .target_reset = qla24xx_abort_target,
2217 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2218 .fabric_login = qla24xx_login_fabric,
2219 .fabric_logout = qla24xx_fabric_logout,
2220 .calc_req_entries = NULL,
2221 .build_iocbs = NULL,
2222 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2223 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2224 .read_nvram = qla24xx_read_nvram_data,
2225 .write_nvram = qla24xx_write_nvram_data,
2226 .fw_dump = qla24xx_fw_dump,
2227 .beacon_on = qla24xx_beacon_on,
2228 .beacon_off = qla24xx_beacon_off,
2229 .beacon_blink = qla24xx_beacon_blink,
2230 .read_optrom = qla24xx_read_optrom_data,
2231 .write_optrom = qla24xx_write_optrom_data,
2232 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2233 .start_scsi = qla24xx_start_scsi,
d7459527 2234 .start_scsi_mq = NULL,
a9083016 2235 .abort_isp = qla2x00_abort_isp,
7ec0effd 2236 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2237 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2238};
2239
c3a2f0df
AV		 2240static struct isp_operations qla25xx_isp_ops = {
2241 .pci_config = qla25xx_pci_config,
2242 .reset_chip = qla24xx_reset_chip,
2243 .chip_diag = qla24xx_chip_diag,
2244 .config_rings = qla24xx_config_rings,
2245 .reset_adapter = qla24xx_reset_adapter,
2246 .nvram_config = qla24xx_nvram_config,
2247 .update_fw_options = qla24xx_update_fw_options,
2248 .load_risc = qla24xx_load_risc,
2249 .pci_info_str = qla24xx_pci_info_str,
2250 .fw_version_str = qla24xx_fw_version_str,
2251 .intr_handler = qla24xx_intr_handler,
2252 .enable_intrs = qla24xx_enable_intrs,
2253 .disable_intrs = qla24xx_disable_intrs,
2254 .abort_command = qla24xx_abort_command,
523ec773
AV		 2255 .target_reset = qla24xx_abort_target,
2256 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2257 .fabric_login = qla24xx_login_fabric,
2258 .fabric_logout = qla24xx_fabric_logout,
2259 .calc_req_entries = NULL,
2260 .build_iocbs = NULL,
2261 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2262 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2263 .read_nvram = qla25xx_read_nvram_data,
2264 .write_nvram = qla25xx_write_nvram_data,
2265 .fw_dump = qla25xx_fw_dump,
2266 .beacon_on = qla24xx_beacon_on,
2267 .beacon_off = qla24xx_beacon_off,
2268 .beacon_blink = qla24xx_beacon_blink,
338c9161 2269 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2270 .write_optrom = qla24xx_write_optrom_data,
2271 .get_flash_version = qla24xx_get_flash_version,
bad75002 2272 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2273 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2274 .abort_isp = qla2x00_abort_isp,
7ec0effd 2275 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2276 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2277};
2278
3a03eb79
AV		 2279static struct isp_operations qla81xx_isp_ops = {
2280 .pci_config = qla25xx_pci_config,
2281 .reset_chip = qla24xx_reset_chip,
2282 .chip_diag = qla24xx_chip_diag,
2283 .config_rings = qla24xx_config_rings,
2284 .reset_adapter = qla24xx_reset_adapter,
2285 .nvram_config = qla81xx_nvram_config,
2286 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2287 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2288 .pci_info_str = qla24xx_pci_info_str,
2289 .fw_version_str = qla24xx_fw_version_str,
2290 .intr_handler = qla24xx_intr_handler,
2291 .enable_intrs = qla24xx_enable_intrs,
2292 .disable_intrs = qla24xx_disable_intrs,
2293 .abort_command = qla24xx_abort_command,
2294 .target_reset = qla24xx_abort_target,
2295 .lun_reset = qla24xx_lun_reset,
2296 .fabric_login = qla24xx_login_fabric,
2297 .fabric_logout = qla24xx_fabric_logout,
2298 .calc_req_entries = NULL,
2299 .build_iocbs = NULL,
2300 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2301 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2302 .read_nvram = NULL,
2303 .write_nvram = NULL,
3a03eb79
AV		 2304 .fw_dump = qla81xx_fw_dump,
2305 .beacon_on = qla24xx_beacon_on,
2306 .beacon_off = qla24xx_beacon_off,
6246b8a1 2307 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2308 .read_optrom = qla25xx_read_optrom_data,
2309 .write_optrom = qla24xx_write_optrom_data,
2310 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2311 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2312 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2313 .abort_isp = qla2x00_abort_isp,
7ec0effd 2314 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2315 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2316};
2317
2318static struct isp_operations qla82xx_isp_ops = {
2319 .pci_config = qla82xx_pci_config,
2320 .reset_chip = qla82xx_reset_chip,
2321 .chip_diag = qla24xx_chip_diag,
2322 .config_rings = qla82xx_config_rings,
2323 .reset_adapter = qla24xx_reset_adapter,
2324 .nvram_config = qla81xx_nvram_config,
2325 .update_fw_options = qla24xx_update_fw_options,
2326 .load_risc = qla82xx_load_risc,
9d55ca66 2327 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2328 .fw_version_str = qla24xx_fw_version_str,
2329 .intr_handler = qla82xx_intr_handler,
2330 .enable_intrs = qla82xx_enable_intrs,
2331 .disable_intrs = qla82xx_disable_intrs,
2332 .abort_command = qla24xx_abort_command,
2333 .target_reset = qla24xx_abort_target,
2334 .lun_reset = qla24xx_lun_reset,
2335 .fabric_login = qla24xx_login_fabric,
2336 .fabric_logout = qla24xx_fabric_logout,
2337 .calc_req_entries = NULL,
2338 .build_iocbs = NULL,
2339 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2340 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2341 .read_nvram = qla24xx_read_nvram_data,
2342 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2343 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2344 .beacon_on = qla82xx_beacon_on,
2345 .beacon_off = qla82xx_beacon_off,
2346 .beacon_blink = NULL,
a9083016
GM		 2347 .read_optrom = qla82xx_read_optrom_data,
2348 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2349 .get_flash_version = qla82xx_get_flash_version,
a9083016 2350 .start_scsi = qla82xx_start_scsi,
d7459527 2351 .start_scsi_mq = NULL,
a9083016 2352 .abort_isp = qla82xx_abort_isp,
706f457d 2353 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2354 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2355};
2356
7ec0effd
AD		 2357static struct isp_operations qla8044_isp_ops = {
2358 .pci_config = qla82xx_pci_config,
2359 .reset_chip = qla82xx_reset_chip,
2360 .chip_diag = qla24xx_chip_diag,
2361 .config_rings = qla82xx_config_rings,
2362 .reset_adapter = qla24xx_reset_adapter,
2363 .nvram_config = qla81xx_nvram_config,
2364 .update_fw_options = qla24xx_update_fw_options,
2365 .load_risc = qla82xx_load_risc,
2366 .pci_info_str = qla24xx_pci_info_str,
2367 .fw_version_str = qla24xx_fw_version_str,
2368 .intr_handler = qla8044_intr_handler,
2369 .enable_intrs = qla82xx_enable_intrs,
2370 .disable_intrs = qla82xx_disable_intrs,
2371 .abort_command = qla24xx_abort_command,
2372 .target_reset = qla24xx_abort_target,
2373 .lun_reset = qla24xx_lun_reset,
2374 .fabric_login = qla24xx_login_fabric,
2375 .fabric_logout = qla24xx_fabric_logout,
2376 .calc_req_entries = NULL,
2377 .build_iocbs = NULL,
2378 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2379 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2380 .read_nvram = NULL,
2381 .write_nvram = NULL,
a1b23c5a 2382 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2383 .beacon_on = qla82xx_beacon_on,
2384 .beacon_off = qla82xx_beacon_off,
2385 .beacon_blink = NULL,
888e639d 2386 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2387 .write_optrom = qla8044_write_optrom_data,
2388 .get_flash_version = qla82xx_get_flash_version,
2389 .start_scsi = qla82xx_start_scsi,
d7459527 2390 .start_scsi_mq = NULL,
7ec0effd
AD		 2391 .abort_isp = qla8044_abort_isp,
2392 .iospace_config = qla82xx_iospace_config,
2393 .initialize_adapter = qla2x00_initialize_adapter,
2394};
2395
6246b8a1
GM		 2396static struct isp_operations qla83xx_isp_ops = {
2397 .pci_config = qla25xx_pci_config,
2398 .reset_chip = qla24xx_reset_chip,
2399 .chip_diag = qla24xx_chip_diag,
2400 .config_rings = qla24xx_config_rings,
2401 .reset_adapter = qla24xx_reset_adapter,
2402 .nvram_config = qla81xx_nvram_config,
2403 .update_fw_options = qla81xx_update_fw_options,
2404 .load_risc = qla81xx_load_risc,
2405 .pci_info_str = qla24xx_pci_info_str,
2406 .fw_version_str = qla24xx_fw_version_str,
2407 .intr_handler = qla24xx_intr_handler,
2408 .enable_intrs = qla24xx_enable_intrs,
2409 .disable_intrs = qla24xx_disable_intrs,
2410 .abort_command = qla24xx_abort_command,
2411 .target_reset = qla24xx_abort_target,
2412 .lun_reset = qla24xx_lun_reset,
2413 .fabric_login = qla24xx_login_fabric,
2414 .fabric_logout = qla24xx_fabric_logout,
2415 .calc_req_entries = NULL,
2416 .build_iocbs = NULL,
2417 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2418 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2419 .read_nvram = NULL,
2420 .write_nvram = NULL,
2421 .fw_dump = qla83xx_fw_dump,
2422 .beacon_on = qla24xx_beacon_on,
2423 .beacon_off = qla24xx_beacon_off,
2424 .beacon_blink = qla83xx_beacon_blink,
2425 .read_optrom = qla25xx_read_optrom_data,
2426 .write_optrom = qla24xx_write_optrom_data,
2427 .get_flash_version = qla24xx_get_flash_version,
2428 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2429 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2430 .abort_isp = qla2x00_abort_isp,
2431 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2432 .initialize_adapter = qla2x00_initialize_adapter,
2433};
2434
2435static struct isp_operations qlafx00_isp_ops = {
2436 .pci_config = qlafx00_pci_config,
2437 .reset_chip = qlafx00_soft_reset,
2438 .chip_diag = qlafx00_chip_diag,
2439 .config_rings = qlafx00_config_rings,
2440 .reset_adapter = qlafx00_soft_reset,
2441 .nvram_config = NULL,
2442 .update_fw_options = NULL,
2443 .load_risc = NULL,
2444 .pci_info_str = qlafx00_pci_info_str,
2445 .fw_version_str = qlafx00_fw_version_str,
2446 .intr_handler = qlafx00_intr_handler,
2447 .enable_intrs = qlafx00_enable_intrs,
2448 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2449 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2450 .target_reset = qlafx00_abort_target,
2451 .lun_reset = qlafx00_lun_reset,
2452 .fabric_login = NULL,
2453 .fabric_logout = NULL,
2454 .calc_req_entries = NULL,
2455 .build_iocbs = NULL,
2456 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2457 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2458 .read_nvram = qla24xx_read_nvram_data,
2459 .write_nvram = qla24xx_write_nvram_data,
2460 .fw_dump = NULL,
2461 .beacon_on = qla24xx_beacon_on,
2462 .beacon_off = qla24xx_beacon_off,
2463 .beacon_blink = NULL,
2464 .read_optrom = qla24xx_read_optrom_data,
2465 .write_optrom = qla24xx_write_optrom_data,
2466 .get_flash_version = qla24xx_get_flash_version,
2467 .start_scsi = qlafx00_start_scsi,
d7459527 2468 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2469 .abort_isp = qlafx00_abort_isp,
2470 .iospace_config = qlafx00_iospace_config,
2471 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2472};
2473
f73cb695
CD		 2474static struct isp_operations qla27xx_isp_ops = {
2475 .pci_config = qla25xx_pci_config,
2476 .reset_chip = qla24xx_reset_chip,
2477 .chip_diag = qla24xx_chip_diag,
2478 .config_rings = qla24xx_config_rings,
2479 .reset_adapter = qla24xx_reset_adapter,
2480 .nvram_config = qla81xx_nvram_config,
2481 .update_fw_options = qla81xx_update_fw_options,
2482 .load_risc = qla81xx_load_risc,
2483 .pci_info_str = qla24xx_pci_info_str,
2484 .fw_version_str = qla24xx_fw_version_str,
2485 .intr_handler = qla24xx_intr_handler,
2486 .enable_intrs = qla24xx_enable_intrs,
2487 .disable_intrs = qla24xx_disable_intrs,
2488 .abort_command = qla24xx_abort_command,
2489 .target_reset = qla24xx_abort_target,
2490 .lun_reset = qla24xx_lun_reset,
2491 .fabric_login = qla24xx_login_fabric,
2492 .fabric_logout = qla24xx_fabric_logout,
2493 .calc_req_entries = NULL,
2494 .build_iocbs = NULL,
2495 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2496 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2497 .read_nvram = NULL,
2498 .write_nvram = NULL,
2499 .fw_dump = qla27xx_fwdump,
2500 .beacon_on = qla24xx_beacon_on,
2501 .beacon_off = qla24xx_beacon_off,
2502 .beacon_blink = qla83xx_beacon_blink,
2503 .read_optrom = qla25xx_read_optrom_data,
2504 .write_optrom = qla24xx_write_optrom_data,
2505 .get_flash_version = qla24xx_get_flash_version,
2506 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2507 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2508 .abort_isp = qla2x00_abort_isp,
2509 .iospace_config = qla83xx_iospace_config,
2510 .initialize_adapter = qla2x00_initialize_adapter,
2511};
2512
ea5b6382 2513static inline void
e315cd28 2514qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2515{
2516 ha->device_type = DT_EXTENDED_IDS;
2517 switch (ha->pdev->device) {
2518 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2519 ha->isp_type |= DT_ISP2100;
ea5b6382 2520 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2522 break;
2523 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2524 ha->isp_type |= DT_ISP2200;
ea5b6382 2525 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2526 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2527 break;
2528 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2529 ha->isp_type |= DT_ISP2300;
4a59f71d 2530 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2531 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2532 break;
2533 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2534 ha->isp_type |= DT_ISP2312;
4a59f71d 2535 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2536 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2537 break;
2538 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2539 ha->isp_type |= DT_ISP2322;
4a59f71d 2540 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2541 if (ha->pdev->subsystem_vendor == 0x1028 &&
2542 ha->pdev->subsystem_device == 0x0170)
2543 ha->device_type |= DT_OEM_001;
441d1072 2544 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2545 break;
2546 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2547 ha->isp_type |= DT_ISP6312;
441d1072 2548 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2549 break;
2550 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2551 ha->isp_type |= DT_ISP6322;
441d1072 2552 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2553 break;
2554 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2555 ha->isp_type |= DT_ISP2422;
4a59f71d 2556 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2557 ha->device_type |= DT_FWI2;
c76f2c01 2558 ha->device_type |= DT_IIDMA;
441d1072 2559 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2560 break;
2561 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2562 ha->isp_type |= DT_ISP2432;
4a59f71d 2563 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2564 ha->device_type |= DT_FWI2;
c76f2c01 2565 ha->device_type |= DT_IIDMA;
441d1072 2566 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2567 break;
4d4df193 2568 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2569 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2570 ha->device_type |= DT_ZIO_SUPPORTED;
2571 ha->device_type |= DT_FWI2;
2572 ha->device_type |= DT_IIDMA;
2573 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2574 break;
044cc6c8 2575 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2576 ha->isp_type |= DT_ISP5422;
e428924c 2577 ha->device_type |= DT_FWI2;
441d1072 2578 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2579 break;
044cc6c8 2580 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2581 ha->isp_type |= DT_ISP5432;
e428924c 2582 ha->device_type |= DT_FWI2;
441d1072 2583 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2584 break;
c3a2f0df 2585 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2586 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2587 ha->device_type |= DT_ZIO_SUPPORTED;
2588 ha->device_type |= DT_FWI2;
2589 ha->device_type |= DT_IIDMA;
441d1072 2590 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2591 break;
3a03eb79 2592 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2593 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2594 ha->device_type |= DT_ZIO_SUPPORTED;
2595 ha->device_type |= DT_FWI2;
2596 ha->device_type |= DT_IIDMA;
2597 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2598 break;
a9083016 2599 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2600 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2601 ha->device_type |= DT_ZIO_SUPPORTED;
2602 ha->device_type |= DT_FWI2;
2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2604 /* Initialize 82XX ISP flags */
2605 qla82xx_init_flags(ha);
2606 break;
7ec0effd 2607 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2608 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2609 ha->device_type |= DT_ZIO_SUPPORTED;
2610 ha->device_type |= DT_FWI2;
2611 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2612 /* Initialize 82XX ISP flags */
2613 qla82xx_init_flags(ha);
2614 break;
6246b8a1 2615 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2616 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2617 ha->device_type |= DT_ZIO_SUPPORTED;
2618 ha->device_type |= DT_FWI2;
2619 ha->device_type |= DT_IIDMA;
2620 ha->device_type |= DT_T10_PI;
2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2622 break;
2623 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2624 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2625 ha->device_type |= DT_ZIO_SUPPORTED;
2626 ha->device_type |= DT_FWI2;
2627 ha->device_type |= DT_IIDMA;
2628 ha->device_type |= DT_T10_PI;
2629 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2630 break;
8ae6d9c7 2631 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2632 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2633 break;
f73cb695 2634 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2635 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2636 ha->device_type |= DT_ZIO_SUPPORTED;
2637 ha->device_type |= DT_FWI2;
2638 ha->device_type |= DT_IIDMA;
8ce3f570 2639 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2641 break;
2c5bbbb2 2642 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2643 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2644 ha->device_type |= DT_ZIO_SUPPORTED;
2645 ha->device_type |= DT_FWI2;
2646 ha->device_type |= DT_IIDMA;
8ce3f570 2647 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2649 break;
2b48992f 2650 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2651 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2652 ha->device_type |= DT_ZIO_SUPPORTED;
2653 ha->device_type |= DT_FWI2;
2654 ha->device_type |= DT_IIDMA;
8ce3f570 2655 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2657 break;
ecc89f25
JC		 2658 case PCI_DEVICE_ID_QLOGIC_ISP2081:
2659 case PCI_DEVICE_ID_QLOGIC_ISP2089:
2660 ha->isp_type |= DT_ISP2081;
2661 ha->device_type |= DT_ZIO_SUPPORTED;
2662 ha->device_type |= DT_FWI2;
2663 ha->device_type |= DT_IIDMA;
2664 ha->device_type |= DT_T10_PI;
2665 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2666 break;
2667 case PCI_DEVICE_ID_QLOGIC_ISP2281:
2668 case PCI_DEVICE_ID_QLOGIC_ISP2289:
2669 ha->isp_type |= DT_ISP2281;
2670 ha->device_type |= DT_ZIO_SUPPORTED;
2671 ha->device_type |= DT_FWI2;
2672 ha->device_type |= DT_IIDMA;
2673 ha->device_type |= DT_T10_PI;
2674 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2675 break;
ea5b6382 2676 }
e5b68a61 2677
a9083016 2678 if (IS_QLA82XX(ha))
43a9c38b 2679 ha->port_no = ha->portnum & 1;
f73cb695 2680 else {
a9083016
GM		 2681 /* Get adapter physical port no from interrupt pin register. */
2682 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
ecc89f25
JC		 2683 if (IS_QLA25XX(ha) || IS_QLA2031(ha) ||
2684 IS_QLA27XX(ha) || IS_QLA28XX(ha))
f73cb695
CD		 2685 ha->port_no--;
2686 else
2687 ha->port_no = !(ha->port_no & 1);
2688 }
a9083016 2689
7c3df132 2690 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2691 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2692 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2693}
2694
1e99e33a
AV		 2695static void
2696qla2xxx_scan_start(struct Scsi_Host *shost)
2697{
e315cd28 2698 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2699
cbc8eb67
AV		 2700 if (vha->hw->flags.running_gold_fw)
2701 return;
2702
e315cd28
AC		 2703 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2704 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2705 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2706 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2707}
2708
2709static int
2710qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2711{
e315cd28 2712 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2713
a5dd506e
BK		 2714 if (test_bit(UNLOADING, &vha->dpc_flags))
2715 return 1;
e315cd28 2716 if (!vha->host)
1e99e33a 2717 return 1;
e315cd28 2718 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2719 return 1;
2720
e315cd28 2721 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2722}
2723
ec7193e2
QT		 2724static void qla2x00_iocb_work_fn(struct work_struct *work)
2725{
2726 struct scsi_qla_host *vha = container_of(work,
2727 struct scsi_qla_host, iocb_work);
9b3e0f4d
QT		 2728 struct qla_hw_data *ha = vha->hw;
2729 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
0aca7784 2730 int i = 2;
9b3e0f4d
QT		 2731 unsigned long flags;
2732
2733 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2734 return;
ec7193e2 2735
9b3e0f4d 2736 while (!list_empty(&vha->work_list) && i > 0) {
ec7193e2 2737 qla2x00_do_work(vha);
9b3e0f4d 2738 i--;
ec7193e2 2739 }
9b3e0f4d
QT		 2740
2741 spin_lock_irqsave(&vha->work_lock, flags);
2742 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2743 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 2744}
2745
1da177e4
LT		 2746/*
2747 * PCI driver interface
2748 */
6f039790 2749static int
7ee61397 2750qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2751{
a1541d5a 2752 int ret = -ENODEV;
1da177e4 2753 struct Scsi_Host *host;
e315cd28
AC		 2754 scsi_qla_host_t *base_vha = NULL;
2755 struct qla_hw_data *ha;
29856e28 2756 char pci_info[30];
7d613ac6 2757 char fw_str[30], wq_name[30];
5433383e 2758 struct scsi_host_template *sht;
642ef983 2759 int bars, mem_only = 0;
e315cd28 2760 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2761 struct req_que *req = NULL;
2762 struct rsp_que *rsp = NULL;
5601236b 2763 int i;
d7459527 2764
285d0321 2765 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2766 sht = &qla2xxx_driver_template;
5433383e 2767 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2768 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2769 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2770 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2771 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2772 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2773 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2774 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2775 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2776 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2777 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2778 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2779 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f 2780 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
ecc89f25
JC		 2781 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 ||
2782 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 ||
2783 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 ||
2784 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 ||
2785 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) {
285d0321 2786 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2787 mem_only = 1;
7c3df132
SK		 2788 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2789 "Mem only adapter.\n");
285d0321 2790 }
7c3df132
SK		 2791 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2792 "Bars=%d.\n", bars);
285d0321 2793
09483916
BH		 2794 if (mem_only) {
2795 if (pci_enable_device_mem(pdev))
ddff7ed4 2796 return ret;
09483916
BH		 2797 } else {
2798 if (pci_enable_device(pdev))
ddff7ed4 2799 return ret;
09483916 2800 }
285d0321 2801
0927678f
JB		 2802 /* This may fail but that's ok */
2803 pci_enable_pcie_error_reporting(pdev);
285d0321 2804
5da05a26
GM		 2805 /* Turn off T10-DIF when FC-NVMe is enabled */
2806 if (ql2xnvmeenable)
2807 ql2xenabledif = 0;
2808
e315cd28
AC		 2809 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2810 if (!ha) {
7c3df132
SK		 2811 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2812 "Unable to allocate memory for ha.\n");
ddff7ed4 2813 goto disable_device;
1da177e4 2814 }
7c3df132
SK		 2815 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2816 "Memory allocated for ha=%p.\n", ha);
e315cd28 2817 ha->pdev = pdev;
33e79977
QT		 2818 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2819 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2820 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2821 spin_lock_init(&ha->tgt.atio_lock);
2822
deeae7a6 2823 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2824
2825 /* Clear our data area */
285d0321 2826 ha->bars = bars;
09483916 2827 ha->mem_only = mem_only;
df4bf0bb 2828 spin_lock_init(&ha->hardware_lock);
339aa70e 2829 spin_lock_init(&ha->vport_slock);
a9b6f722 2830 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2831 mutex_init(&ha->optrom_mutex);
1da177e4 2832
ea5b6382
AV		 2833 /* Set ISP-type information. */
2834 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2835
2836 /* Set EEH reset type to fundamental if required by hba */
95676112 2837 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
ecc89f25 2838 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
ca79cf66 2839 pdev->needs_freset = 1;
ca79cf66 2840
cba1e47f
CD		 2841 ha->prev_topology = 0;
2842 ha->init_cb_size = sizeof(init_cb_t);
2843 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2844 ha->optrom_size = OPTROM_SIZE_2300;
d1e3635a 2845 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
b2000805
QT		 2846 atomic_set(&ha->num_pend_mbx_stage1, 0);
2847 atomic_set(&ha->num_pend_mbx_stage2, 0);
2848 atomic_set(&ha->num_pend_mbx_stage3, 0);
8b4673ba
QT		 2849 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2850 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
cba1e47f 2851
abbd8870 2852 /* Assign ISP specific operations. */
1da177e4 2853 if (IS_QLA2100(ha)) {
642ef983 2854 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2855 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2856 req_length = REQUEST_ENTRY_CNT_2100;
2857 rsp_length = RESPONSE_ENTRY_CNT_2100;
2858 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2859 ha->gid_list_info_size = 4;
3a03eb79
AV		 2860 ha->flash_conf_off = ~0;
2861 ha->flash_data_off = ~0;
2862 ha->nvram_conf_off = ~0;
2863 ha->nvram_data_off = ~0;
fd34f556 2864 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2865 } else if (IS_QLA2200(ha)) {
642ef983 2866 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2867 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2868 req_length = REQUEST_ENTRY_CNT_2200;
2869 rsp_length = RESPONSE_ENTRY_CNT_2100;
2870 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2871 ha->gid_list_info_size = 4;
3a03eb79
AV		 2872 ha->flash_conf_off = ~0;
2873 ha->flash_data_off = ~0;
2874 ha->nvram_conf_off = ~0;
2875 ha->nvram_data_off = ~0;
fd34f556 2876 ha->isp_ops = &qla2100_isp_ops;
fca29703 2877 } else if (IS_QLA23XX(ha)) {
642ef983 2878 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2879 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2880 req_length = REQUEST_ENTRY_CNT_2200;
2881 rsp_length = RESPONSE_ENTRY_CNT_2300;
2882 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2883 ha->gid_list_info_size = 6;
854165f4
AV		 2884 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2885 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2886 ha->flash_conf_off = ~0;
2887 ha->flash_data_off = ~0;
2888 ha->nvram_conf_off = ~0;
2889 ha->nvram_data_off = ~0;
fd34f556 2890 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2891 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2892 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2893 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2894 req_length = REQUEST_ENTRY_CNT_24XX;
2895 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2896 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2897 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2898 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2899 ha->gid_list_info_size = 8;
854165f4 2900 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2901 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2902 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2903 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2904 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2905 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2906 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2907 } else if (IS_QLA25XX(ha)) {
642ef983 2908 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2909 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2910 req_length = REQUEST_ENTRY_CNT_24XX;
2911 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2912 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2913 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2914 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2915 ha->gid_list_info_size = 8;
2916 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2917 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2918 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2919 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2920 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2921 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2922 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2923 } else if (IS_QLA81XX(ha)) {
642ef983 2924 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2925 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2926 req_length = REQUEST_ENTRY_CNT_24XX;
2927 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2928 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2929 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2930 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2931 ha->gid_list_info_size = 8;
2932 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2933 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2934 ha->isp_ops = &qla81xx_isp_ops;
2935 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2936 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2937 ha->nvram_conf_off = ~0;
2938 ha->nvram_data_off = ~0;
a9083016 2939 } else if (IS_QLA82XX(ha)) {
642ef983 2940 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2941 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2942 req_length = REQUEST_ENTRY_CNT_82XX;
2943 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2944 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2945 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2946 ha->gid_list_info_size = 8;
2947 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2948 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2949 ha->isp_ops = &qla82xx_isp_ops;
2950 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2951 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2952 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2953 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2954 } else if (IS_QLA8044(ha)) {
2955 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2956 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2957 req_length = REQUEST_ENTRY_CNT_82XX;
2958 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2959 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2960 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2961 ha->gid_list_info_size = 8;
2962 ha->optrom_size = OPTROM_SIZE_83XX;
2963 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2964 ha->isp_ops = &qla8044_isp_ops;
2965 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2966 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2967 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2968 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2969 } else if (IS_QLA83XX(ha)) {
7d613ac6 2970 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2971 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2972 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2973 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2974 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2975 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2976 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2977 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2978 ha->gid_list_info_size = 8;
2979 ha->optrom_size = OPTROM_SIZE_83XX;
2980 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2981 ha->isp_ops = &qla83xx_isp_ops;
2982 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2983 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2984 ha->nvram_conf_off = ~0;
2985 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2986 } else if (IS_QLAFX00(ha)) {
2987 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2988 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2989 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2990 req_length = REQUEST_ENTRY_CNT_FX00;
2991 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2992 ha->isp_ops = &qlafx00_isp_ops;
2993 ha->port_down_retry_count = 30; /* default value */
2994 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2995 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2996 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2997 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2998 ha->mr.host_info_resend = false;
2999 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 3000 } else if (IS_QLA27XX(ha)) {
3001 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3002 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3003 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 3004 req_length = REQUEST_ENTRY_CNT_83XX;
3005 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 3006 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 3007 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3008 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3009 ha->gid_list_info_size = 8;
3010 ha->optrom_size = OPTROM_SIZE_83XX;
3011 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3012 ha->isp_ops = &qla27xx_isp_ops;
3013 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3014 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3015 ha->nvram_conf_off = ~0;
3016 ha->nvram_data_off = ~0;
ecc89f25
JC		 3017 } else if (IS_QLA28XX(ha)) {
3018 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3019 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3020 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3021 req_length = REQUEST_ENTRY_CNT_24XX;
3022 rsp_length = RESPONSE_ENTRY_CNT_2300;
3023 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3024 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3025 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3026 ha->gid_list_info_size = 8;
3027 ha->optrom_size = OPTROM_SIZE_28XX;
3028 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3029 ha->isp_ops = &qla27xx_isp_ops;
3030 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX;
3031 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX;
3032 ha->nvram_conf_off = ~0;
3033 ha->nvram_data_off = ~0;
1da177e4 3034 }
6246b8a1 3035
7c3df132
SK		 3036 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3037 "mbx_count=%d, req_length=%d, "
3038 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 3039 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3040 "max_fibre_devices=%d.\n",
7c3df132
SK		 3041 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3042 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 3043 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 3044 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3045 "isp_ops=%p, flash_conf_off=%d, "
3046 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3047 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3048 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 3049
3050 /* Configure PCI I/O space */
3051 ret = ha->isp_ops->iospace_config(ha);
3052 if (ret)
0a63ad12 3053 goto iospace_config_failed;
706f457d
GM		 3054
3055 ql_log_pci(ql_log_info, pdev, 0x001d,
3056 "Found an ISP%04X irq %d iobase 0x%p.\n",
3057 pdev->device, pdev->irq, ha->iobase);
6c2f527c 3058 mutex_init(&ha->vport_lock);
d7459527 3059 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 3060 init_completion(&ha->mbx_cmd_comp);
3061 complete(&ha->mbx_cmd_comp);
3062 init_completion(&ha->mbx_intr_comp);
23f2ebd1 3063 init_completion(&ha->dcbx_comp);
f356bef1 3064 init_completion(&ha->lb_portup_comp);
1da177e4 3065
2c3dfe3f 3066 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 3067
53303c42 3068 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 3069 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3070 "64 Bit addressing is %s.\n",
3071 ha->flags.enable_64bit_addressing ? "enable" :
3072 "disable");
73208dfd 3073 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 3074 if (ret) {
7c3df132
SK		 3075 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3076 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 3077
e315cd28
AC		 3078 goto probe_hw_failed;
3079 }
3080
73208dfd 3081 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 3082 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 3083 req->max_q_depth = ql2xmaxqdepth;
3084
e315cd28
AC		 3085
3086 base_vha = qla2x00_create_host(sht, ha);
3087 if (!base_vha) {
a1541d5a 3088 ret = -ENOMEM;
e315cd28 3089 goto probe_hw_failed;
1da177e4
LT		 3090 }
3091
e315cd28 3092 pci_set_drvdata(pdev, base_vha);
6b383979 3093 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3094
e315cd28 3095 host = base_vha->host;
2afa19a9 3096 base_vha->req = req;
73208dfd 3097 if (IS_QLA2XXX_MIDTYPE(ha))
f6602f3b
QT		 3098 base_vha->mgmt_svr_loop_id =
3099 qla2x00_reserve_mgmt_server_loop_id(base_vha);
73208dfd 3100 else
e315cd28
AC		 3101 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3102 base_vha->vp_idx;
58548cb5 3103
8ae6d9c7
GM		 3104 /* Setup fcport template structure. */
3105 ha->mr.fcport.vha = base_vha;
3106 ha->mr.fcport.port_type = FCT_UNKNOWN;
3107 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3108 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3109 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3110 ha->mr.fcport.scan_state = 1;
3111
58548cb5
GM		 3112 /* Set the SG table size based on ISP type */
3113 if (!IS_FWI2_CAPABLE(ha)) {
3114 if (IS_QLA2100(ha))
3115 host->sg_tablesize = 32;
3116 } else {
3117 if (!IS_QLA82XX(ha))
3118 host->sg_tablesize = QLA_SG_ALL;
3119 }
642ef983 3120 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3121 host->cmd_per_lun = 3;
3122 host->unique_id = host->host_no;
e02587d7 3123 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3124 host->max_cmd_len = 32;
3125 else
3126 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3127 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3128 /* Older HBAs support only 16-bit LUNs */
3129 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3130 ql2xmaxlun > 0xffff)
3131 host->max_lun = 0xffff;
3132 else
3133 host->max_lun = ql2xmaxlun;
e315cd28 3134 host->transportt = qla2xxx_transport_template;
9a069e19 3135 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3136
7c3df132
SK		 3137 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3138 "max_id=%d this_id=%d "
3139 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3140 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3141 host->this_id, host->cmd_per_lun, host->unique_id,
3142 host->max_cmd_len, host->max_channel, host->max_lun,
3143 host->transportt, sht->vendor_id);
3144
1010f21e
HM		 3145 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3146
d7459527
MH		 3147 /* Set up the irqs */
3148 ret = qla2x00_request_irqs(ha, rsp);
3149 if (ret)
6a2cf8d3 3150 goto probe_failed;
d7459527 3151
9a347ff4 3152 /* Alloc arrays of request and response ring ptrs */
6d634067
BK		 3153 ret = qla2x00_alloc_queues(ha, req, rsp);
3154 if (ret) {
9a347ff4
CD		 3155 ql_log(ql_log_fatal, base_vha, 0x003d,
3156 "Failed to allocate memory for queue pointers..."
3157 "aborting.\n");
6a2cf8d3 3158 goto probe_failed;
9a347ff4
CD		 3159 }
3160
f664a3cc 3161 if (ha->mqenable) {
5601236b
MH		 3162 /* number of hardware queues supported by blk/scsi-mq*/
3163 host->nr_hw_queues = ha->max_qpairs;
3164
3165 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3166 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
c38d1baf
HM		 3167 } else {
3168 if (ql2xnvmeenable) {
3169 host->nr_hw_queues = ha->max_qpairs;
3170 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3171 "FC-NVMe support is enabled, HW queues=%d\n",
3172 host->nr_hw_queues);
3173 } else {
3174 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3175 "blk/scsi-mq disabled.\n");
3176 }
3177 }
5601236b 3178
2d70c103 3179 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3180
90a86fc0
JC		 3181 pci_save_state(pdev);
3182
9a347ff4 3183 /* Assign back pointers */
2afa19a9
AC		 3184 rsp->req = req;
3185 req->rsp = rsp;
9a347ff4 3186
8ae6d9c7
GM		 3187 if (IS_QLAFX00(ha)) {
3188 ha->rsp_q_map[0] = rsp;
3189 ha->req_q_map[0] = req;
3190 set_bit(0, ha->req_qid_map);
3191 set_bit(0, ha->rsp_qid_map);
3192 }
3193
08029990
AV		 3194 /* FWI2-capable only. */
3195 req->req_q_in = &ha->iobase->isp24.req_q_in;
3196 req->req_q_out = &ha->iobase->isp24.req_q_out;
3197 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3198 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
ecc89f25
JC		 3199 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3200 IS_QLA28XX(ha)) {
08029990
AV		 3201 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3202 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3203 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3204 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3205 }
3206
8ae6d9c7
GM		 3207 if (IS_QLAFX00(ha)) {
3208 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3209 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3210 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3211 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3212 }
3213
7ec0effd 3214 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3215 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3216 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3217 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3218 }
3219
7c3df132
SK		 3220 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3221 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3222 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3223 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3224 "req->req_q_in=%p req->req_q_out=%p "
3225 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3226 req->req_q_in, req->req_q_out,
3227 rsp->rsp_q_in, rsp->rsp_q_out);
3228 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3229 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3230 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3231 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3232 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3233 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3234
d48cc67c 3235 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3e515f91
AP		 3236 if (unlikely(!ha->wq)) {
3237 ret = -ENOMEM;
3238 goto probe_failed;
3239 }
d48cc67c 3240
8ae6d9c7 3241 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3242 ql_log(ql_log_fatal, base_vha, 0x00d6,
3243 "Failed to initialize adapter - Adapter flags %x.\n",
3244 base_vha->device_flags);
1da177e4 3245
a9083016
GM		 3246 if (IS_QLA82XX(ha)) {
3247 qla82xx_idc_lock(ha);
3248 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3249 QLA8XXX_DEV_FAILED);
a9083016 3250 qla82xx_idc_unlock(ha);
7c3df132
SK		 3251 ql_log(ql_log_fatal, base_vha, 0x00d7,
3252 "HW State: FAILED.\n");
7ec0effd
AD		 3253 } else if (IS_QLA8044(ha)) {
3254 qla8044_idc_lock(ha);
3255 qla8044_wr_direct(base_vha,
3256 QLA8044_CRB_DEV_STATE_INDEX,
3257 QLA8XXX_DEV_FAILED);
3258 qla8044_idc_unlock(ha);
3259 ql_log(ql_log_fatal, base_vha, 0x0150,
3260 "HW State: FAILED.\n");
a9083016
GM		 3261 }
3262
a1541d5a 3263 ret = -ENODEV;
1da177e4
LT		 3264 goto probe_failed;
3265 }
3266
3b1bef64
CD		 3267 if (IS_QLAFX00(ha))
3268 host->can_queue = QLAFX00_MAX_CANQUEUE;
3269 else
3270 host->can_queue = req->num_outstanding_cmds - 10;
3271
3272 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3273 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3274 host->can_queue, base_vha->req,
3275 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3276
e326d22a 3277 if (ha->mqenable) {
e326d22a 3278 bool startit = false;
e326d22a 3279
f664a3cc 3280 if (QLA_TGT_MODE_ENABLED())
e326d22a 3281 startit = false;
e326d22a 3282
f664a3cc 3283 if (ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED)
e326d22a 3284 startit = true;
e326d22a 3285
f664a3cc
JA		 3286 /* Create start of day qpairs for Block MQ */
3287 for (i = 0; i < ha->max_qpairs; i++)
3288 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b 3289 }
68ca949c 3290
cbc8eb67
AV		 3291 if (ha->flags.running_gold_fw)
3292 goto skip_dpc;
3293
1da177e4
LT		 3294 /*
3295 * Startup the kernel thread for this host adapter
3296 */
39a11240 3297 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3298 "%s_dpc", base_vha->host_str);
39a11240 3299 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3300 ql_log(ql_log_fatal, base_vha, 0x00ed,
3301 "Failed to start DPC thread.\n");
39a11240 3302 ret = PTR_ERR(ha->dpc_thread);
e2532b4a 3303 ha->dpc_thread = NULL;
1da177e4
LT		 3304 goto probe_failed;
3305 }
7c3df132
SK		 3306 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3307 "DPC thread started successfully.\n");
1da177e4 3308
2d70c103
NB		 3309 /*
3310 * If we're not coming up in initiator mode, we might sit for
3311 * a while without waking up the dpc thread, which leads to a
3312 * stuck process warning. So just kick the dpc once here and
3313 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3314 */
3315 qla2xxx_wake_dpc(base_vha);
3316
f3ddac19
CD		 3317 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3318
81178772
SK		 3319 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3320 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3321 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3322 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3323
3324 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3325 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3326 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3327 INIT_WORK(&ha->idc_state_handler,
3328 qla83xx_idc_state_handler_work);
3329 INIT_WORK(&ha->nic_core_unrecoverable,
3330 qla83xx_nic_core_unrecoverable_work);
3331 }
3332
cbc8eb67 3333skip_dpc:
e315cd28
AC		 3334 list_add_tail(&base_vha->list, &ha->vp_list);
3335 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3336
3337 /* Initialized the timer */
8e5f4ba0 3338 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3339 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3340 "Started qla2x00_timer with "
3341 "interval=%d.\n", WATCH_INTERVAL);
3342 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3343 "Detected hba at address=%p.\n",
3344 ha);
d19044c3 3345
e02587d7 3346 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3347 if (ha->fw_attributes & BIT_4) {
9e522cd8 3348 int prot = 0, guard;
bd432bb5 3349
bad75002 3350 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3351 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3352 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3353 if (ql2xenabledif == 1)
3354 prot = SHOST_DIX_TYPE0_PROTECTION;
7855d2ba
MP		 3355 if (ql2xprotmask)
3356 scsi_host_set_prot(host, ql2xprotmask);
3357 else
3358 scsi_host_set_prot(host,
3359 prot | SHOST_DIF_TYPE1_PROTECTION
3360 | SHOST_DIF_TYPE2_PROTECTION
3361 | SHOST_DIF_TYPE3_PROTECTION
3362 | SHOST_DIX_TYPE1_PROTECTION
3363 | SHOST_DIX_TYPE2_PROTECTION
3364 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3365
3366 guard = SHOST_DIX_GUARD_CRC;
3367
3368 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3369 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3370 guard |= SHOST_DIX_GUARD_IP;
3371
7855d2ba
MP		 3372 if (ql2xprotguard)
3373 scsi_host_set_guard(host, ql2xprotguard);
3374 else
3375 scsi_host_set_guard(host, guard);
bad75002
AE		 3376 } else
3377 base_vha->flags.difdix_supported = 0;
3378 }
3379
a9083016
GM		 3380 ha->isp_ops->enable_intrs(ha);
3381
1fe19ee4
AB		 3382 if (IS_QLAFX00(ha)) {
3383 ret = qlafx00_fx_disc(base_vha,
3384 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3385 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3386 QLA_SG_ALL : 128;
3387 }
3388
a1541d5a
AV		 3389 ret = scsi_add_host(host, &pdev->dev);
3390 if (ret)
3391 goto probe_failed;
3392
1486400f
MR		 3393 base_vha->flags.init_done = 1;
3394 base_vha->flags.online = 1;
edaa5c74 3395 ha->prev_minidump_failed = 0;
1486400f 3396
7c3df132
SK		 3397 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3398 "Init done and hba is online.\n");
3399
726b8548
QT		 3400 if (qla_ini_mode_enabled(base_vha) ||
3401 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3402 scsi_scan_host(host);
3403 else
3404 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3405 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3406
e315cd28 3407 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3408
8ae6d9c7 3409 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3410 ret = qlafx00_fx_disc(base_vha,
3411 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3412
3413 /* Register system information */
3414 ret = qlafx00_fx_disc(base_vha,
3415 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3416 }
3417
e315cd28 3418 qla2x00_init_host_attr(base_vha);
a1541d5a 3419
e315cd28 3420 qla2x00_dfs_setup(base_vha);
df613b96 3421
03eb912a
AB		 3422 ql_log(ql_log_info, base_vha, 0x00fb,
3423 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3424 ql_log(ql_log_info, base_vha, 0x00fc,
3425 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3426 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3427 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3428 base_vha->host_no,
df57caba 3429 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3430
2d70c103
NB		 3431 qlt_add_target(ha, base_vha);
3432
6b383979 3433 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3434
3435 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3436 return -ENODEV;
3437
e4e3a2ce
QT		 3438 if (ha->flags.detected_lr_sfp) {
3439 ql_log(ql_log_info, base_vha, 0xffff,
3440 "Reset chip to pick up LR SFP setting\n");
3441 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3442 qla2xxx_wake_dpc(base_vha);
3443 }
3444
1da177e4
LT		 3445 return 0;
3446
3447probe_failed:
26fa656e
BK		 3448 if (base_vha->gnl.l) {
3449 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3450 base_vha->gnl.l, base_vha->gnl.ldma);
3451 base_vha->gnl.l = NULL;
3452 }
3453
b9978769
AV		 3454 if (base_vha->timer_active)
3455 qla2x00_stop_timer(base_vha);
3456 base_vha->flags.online = 0;
3457 if (ha->dpc_thread) {
3458 struct task_struct *t = ha->dpc_thread;
3459
3460 ha->dpc_thread = NULL;
3461 kthread_stop(t);
3462 }
3463
e315cd28 3464 qla2x00_free_device(base_vha);
e315cd28 3465 scsi_host_put(base_vha->host);
6d634067
BK		 3466 /*
3467 * Need to NULL out local req/rsp after
3468 * qla2x00_free_device => qla2x00_free_queues frees
3469 * what these are pointing to. Or else we'll
3470 * fall over below in qla2x00_free_req/rsp_que.
3471 */
3472 req = NULL;
3473 rsp = NULL;
1da177e4 3474
e315cd28 3475probe_hw_failed:
d64d6c56 3476 qla2x00_mem_free(ha);
3477 qla2x00_free_req_que(ha, req);
3478 qla2x00_free_rsp_que(ha, rsp);
1a2fbf18
JL		 3479 qla2x00_clear_drv_active(ha);
3480
0a63ad12 3481iospace_config_failed:
7ec0effd 3482 if (IS_P3P_TYPE(ha)) {
0a63ad12 3483 if (!ha->nx_pcibase)
f73cb695 3484 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3485 if (!ql2xdbwr)
f73cb695 3486 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3487 } else {
3488 if (ha->iobase)
3489 iounmap(ha->iobase);
8ae6d9c7
GM		 3490 if (ha->cregbase)
3491 iounmap(ha->cregbase);
a9083016 3492 }
e315cd28
AC		 3493 pci_release_selected_regions(ha->pdev, ha->bars);
3494 kfree(ha);
1da177e4 3495
ddff7ed4 3496disable_device:
e315cd28 3497 pci_disable_device(pdev);
a1541d5a 3498 return ret;
1da177e4 3499}
1da177e4 3500
e30d1756
MI		 3501static void
3502qla2x00_shutdown(struct pci_dev *pdev)
3503{
3504 scsi_qla_host_t *vha;
3505 struct qla_hw_data *ha;
3506
3507 vha = pci_get_drvdata(pdev);
3508 ha = vha->hw;
3509
efdb5760
SC		 3510 ql_log(ql_log_info, vha, 0xfffa,
3511 "Adapter shutdown\n");
3512
3513 /*
3514 * Prevent future board_disable and wait
3515 * until any pending board_disable has completed.
3516 */
3517 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3518 cancel_work_sync(&ha->board_disable);
3519
3520 if (!atomic_read(&pdev->enable_cnt))
3521 return;
3522
42479343
AB		 3523 /* Notify ISPFX00 firmware */
3524 if (IS_QLAFX00(ha))
3525 qlafx00_driver_shutdown(vha, 20);
3526
e30d1756
MI		 3527 /* Turn-off FCE trace */
3528 if (ha->flags.fce_enabled) {
3529 qla2x00_disable_fce_trace(vha, NULL, NULL);
3530 ha->flags.fce_enabled = 0;
3531 }
3532
3533 /* Turn-off EFT trace */
3534 if (ha->eft)
3535 qla2x00_disable_eft_trace(vha);
3536
ecc89f25
JC		 3537 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3538 IS_QLA28XX(ha)) {
3407fc37
QT		 3539 if (ha->flags.fw_started)
3540 qla2x00_abort_isp_cleanup(vha);
3541 } else {
3542 /* Stop currently executing firmware. */
3543 qla2x00_try_to_stop_firmware(vha);
3544 }
e30d1756 3545
34ab524f
NP		 3546 /* Disable timer */
3547 if (vha->timer_active)
3548 qla2x00_stop_timer(vha);
3549
e30d1756
MI		 3550 /* Turn adapter off line */
3551 vha->flags.online = 0;
3552
3553 /* turn-off interrupts on the card */
3554 if (ha->interrupts_on) {
3555 vha->flags.init_done = 0;
3556 ha->isp_ops->disable_intrs(ha);
3557 }
3558
3559 qla2x00_free_irqs(vha);
3560
3561 qla2x00_free_fw_dump(ha);
61d41f61 3562
61d41f61 3563 pci_disable_device(pdev);
efdb5760
SC		 3564 ql_log(ql_log_info, vha, 0xfffe,
3565 "Adapter shutdown successfully.\n");
e30d1756
MI		 3566}
3567
fe1b806f 3568/* Deletes all the virtual ports for a given ha */
4c993f76 3569static void
fe1b806f 3570qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3571{
fe1b806f 3572 scsi_qla_host_t *vha;
feafb7b1 3573 unsigned long flags;
e315cd28 3574
43ebf16d
AE		 3575 mutex_lock(&ha->vport_lock);
3576 while (ha->cur_vport_count) {
43ebf16d 3577 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3578
43ebf16d
AE		 3579 BUG_ON(base_vha->list.next == &ha->vp_list);
3580 /* This assumes first entry in ha->vp_list is always base vha */
3581 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3582 scsi_host_get(vha->host);
feafb7b1 3583
43ebf16d
AE		 3584 spin_unlock_irqrestore(&ha->vport_slock, flags);
3585 mutex_unlock(&ha->vport_lock);
3586
5e6803b4
HM		 3587 qla_nvme_delete(vha);
3588
43ebf16d
AE		 3589 fc_vport_terminate(vha->fc_vport);
3590 scsi_host_put(vha->host);
feafb7b1 3591
43ebf16d 3592 mutex_lock(&ha->vport_lock);
e315cd28 3593 }
43ebf16d 3594 mutex_unlock(&ha->vport_lock);
fe1b806f 3595}
1da177e4 3596
fe1b806f
CD		 3597/* Stops all deferred work threads */
3598static void
3599qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3600{
7d613ac6
SV		 3601 /* Cancel all work and destroy DPC workqueues */
3602 if (ha->dpc_lp_wq) {
3603 cancel_work_sync(&ha->idc_aen);
3604 destroy_workqueue(ha->dpc_lp_wq);
3605 ha->dpc_lp_wq = NULL;
3606 }
3607
3608 if (ha->dpc_hp_wq) {
3609 cancel_work_sync(&ha->nic_core_reset);
3610 cancel_work_sync(&ha->idc_state_handler);
3611 cancel_work_sync(&ha->nic_core_unrecoverable);
3612 destroy_workqueue(ha->dpc_hp_wq);
3613 ha->dpc_hp_wq = NULL;
3614 }
3615
b9978769
AV		 3616 /* Kill the kernel thread for this host */
3617 if (ha->dpc_thread) {
3618 struct task_struct *t = ha->dpc_thread;
3619
3620 /*
3621 * qla2xxx_wake_dpc checks for ->dpc_thread
3622 * so we need to zero it out.
3623 */
3624 ha->dpc_thread = NULL;
3625 kthread_stop(t);
3626 }
fe1b806f 3627}
1da177e4 3628
fe1b806f
CD		 3629static void
3630qla2x00_unmap_iobases(struct qla_hw_data *ha)
3631{
a9083016 3632 if (IS_QLA82XX(ha)) {
b963752f 3633
f73cb695 3634 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3635 if (!ql2xdbwr)
f73cb695 3636 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3637 } else {
3638 if (ha->iobase)
3639 iounmap(ha->iobase);
1da177e4 3640
8ae6d9c7
GM		 3641 if (ha->cregbase)
3642 iounmap(ha->cregbase);
3643
a9083016
GM		 3644 if (ha->mqiobase)
3645 iounmap(ha->mqiobase);
6246b8a1 3646
ecc89f25
JC		 3647 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&
3648 ha->msixbase)
6246b8a1 3649 iounmap(ha->msixbase);
a9083016 3650 }
fe1b806f
CD		 3651}
3652
3653static void
db7157d4 3654qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3655{
fe1b806f
CD		 3656 if (IS_QLA8044(ha)) {
3657 qla8044_idc_lock(ha);
c41afc9a 3658 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3659 qla8044_idc_unlock(ha);
3660 } else if (IS_QLA82XX(ha)) {
3661 qla82xx_idc_lock(ha);
3662 qla82xx_clear_drv_active(ha);
3663 qla82xx_idc_unlock(ha);
3664 }
3665}
3666
3667static void
3668qla2x00_remove_one(struct pci_dev *pdev)
3669{
3670 scsi_qla_host_t *base_vha;
3671 struct qla_hw_data *ha;
3672
beb9e315
JL		 3673 base_vha = pci_get_drvdata(pdev);
3674 ha = base_vha->hw;
45235022
QT		 3675 ql_log(ql_log_info, base_vha, 0xb079,
3676 "Removing driver\n");
beb9e315
JL		 3677
3678 /* Indicate device removal to prevent future board_disable and wait
3679 * until any pending board_disable has completed. */
3680 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3681 cancel_work_sync(&ha->board_disable);
3682
fe1b806f 3683 /*
beb9e315
JL		 3684 * If the PCI device is disabled then there was a PCI-disconnect and
3685 * qla2x00_disable_board_on_pci_error has taken care of most of the
3686 * resources.
fe1b806f 3687 */
beb9e315 3688 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3689 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3690 base_vha->gnl.l, base_vha->gnl.ldma);
26fa656e 3691 base_vha->gnl.l = NULL;
beb9e315
JL		 3692 scsi_host_put(base_vha->host);
3693 kfree(ha);
3694 pci_set_drvdata(pdev, NULL);
fe1b806f 3695 return;
beb9e315 3696 }
638a1a01
SC		 3697 qla2x00_wait_for_hba_ready(base_vha);
3698
ecc89f25
JC		 3699 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
3700 IS_QLA28XX(ha)) {
45235022
QT		 3701 if (ha->flags.fw_started)
3702 qla2x00_abort_isp_cleanup(base_vha);
3703 } else if (!IS_QLAFX00(ha)) {
3704 if (IS_QLA8031(ha)) {
3705 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3706 "Clearing fcoe driver presence.\n");
3707 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3708 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3709 "Error while clearing DRV-Presence.\n");
3710 }
3711
3712 qla2x00_try_to_stop_firmware(base_vha);
3713 }
3714
2ce87cc5
QT		 3715 qla2x00_wait_for_sess_deletion(base_vha);
3716
726b8548
QT		 3717 /*
3718 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3719 * where it was set first.
3720 */
3721 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3722 return;
3723
fe1b806f 3724 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3725
3726 qla_nvme_delete(base_vha);
3727
726b8548
QT		 3728 dma_free_coherent(&ha->pdev->dev,
3729 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f 3730
26fa656e
BK		 3731 base_vha->gnl.l = NULL;
3732
a4239945
QT		 3733 vfree(base_vha->scan.l);
3734
fe1b806f
CD		 3735 if (IS_QLAFX00(ha))
3736 qlafx00_driver_shutdown(base_vha, 20);
3737
3738 qla2x00_delete_all_vps(ha, base_vha);
3739
fe1b806f
CD		 3740 qla2x00_dfs_remove(base_vha);
3741
3742 qla84xx_put_chip(base_vha);
3743
3744 /* Disable timer */
3745 if (base_vha->timer_active)
3746 qla2x00_stop_timer(base_vha);
3747
3748 base_vha->flags.online = 0;
3749
b0d6cabd
HM		 3750 /* free DMA memory */
3751 if (ha->exlogin_buf)
3752 qla2x00_free_exlogin_buffer(ha);
3753
2f56a7f1
HM		 3754 /* free DMA memory */
3755 if (ha->exchoffld_buf)
3756 qla2x00_free_exchoffld_buffer(ha);
3757
fe1b806f
CD		 3758 qla2x00_destroy_deferred_work(ha);
3759
3760 qlt_remove_target(ha, base_vha);
3761
3762 qla2x00_free_sysfs_attr(base_vha, true);
3763
3764 fc_remove_host(base_vha->host);
482c9dc7 3765 qlt_remove_target_resources(ha);
fe1b806f
CD		 3766
3767 scsi_remove_host(base_vha->host);
3768
3769 qla2x00_free_device(base_vha);
3770
db7157d4 3771 qla2x00_clear_drv_active(ha);
fe1b806f 3772
d2749ffa
AE		 3773 scsi_host_put(base_vha->host);
3774
fe1b806f 3775 qla2x00_unmap_iobases(ha);
73208dfd 3776
e315cd28
AC		 3777 pci_release_selected_regions(ha->pdev, ha->bars);
3778 kfree(ha);
1da177e4 3779
90a86fc0
JC		 3780 pci_disable_pcie_error_reporting(pdev);
3781
665db93b 3782 pci_disable_device(pdev);
1da177e4 3783}
1da177e4
LT		 3784
3785static void
e315cd28 3786qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3787{
e315cd28 3788 struct qla_hw_data *ha = vha->hw;
1da177e4 3789
85880801
AV		 3790 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3791
3792 /* Disable timer */
3793 if (vha->timer_active)
3794 qla2x00_stop_timer(vha);
3795
2afa19a9 3796 qla25xx_delete_queues(vha);
85880801
AV		 3797 vha->flags.online = 0;
3798
f6ef3b18 3799 /* turn-off interrupts on the card */
a9083016
GM		 3800 if (ha->interrupts_on) {
3801 vha->flags.init_done = 0;
fd34f556 3802 ha->isp_ops->disable_intrs(ha);
a9083016 3803 }
f6ef3b18 3804
093df737
QT		 3805 qla2x00_free_fcports(vha);
3806
e315cd28 3807 qla2x00_free_irqs(vha);
1da177e4 3808
093df737
QT		 3809 /* Flush the work queue and remove it */
3810 if (ha->wq) {
3811 flush_workqueue(ha->wq);
3812 destroy_workqueue(ha->wq);
3813 ha->wq = NULL;
3814 }
3815
8867048b 3816
e315cd28 3817 qla2x00_mem_free(ha);
73208dfd 3818
08de2844
GM		 3819 qla82xx_md_free(vha);
3820
73208dfd 3821 qla2x00_free_queues(ha);
1da177e4
LT		 3822}
3823
8867048b
CD		 3824void qla2x00_free_fcports(struct scsi_qla_host *vha)
3825{
3826 fc_port_t *fcport, *tfcport;
3827
ffbc6476
QT		 3828 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list)
3829 qla2x00_free_fcport(fcport);
8867048b
CD		 3830}
3831
d97994dc 3832static inline void
e315cd28 3833qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3834 int defer)
3835{
d97994dc 3836 struct fc_rport *rport;
67becc00 3837 scsi_qla_host_t *base_vha;
044d78e1 3838 unsigned long flags;
d97994dc
AV		 3839
3840 if (!fcport->rport)
3841 return;
3842
3843 rport = fcport->rport;
3844 if (defer) {
67becc00 3845 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3846 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3847 fcport->drport = rport;
044d78e1 3848 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3849 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3850 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3851 qla2xxx_wake_dpc(base_vha);
2d70c103 3852 } else {
df673274 3853 int now;
bd432bb5 3854
726b8548 3855 if (rport) {
83548fe2
QT		 3856 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3857 "%s %8phN. rport %p roles %x\n",
3858 __func__, fcport->port_name, rport,
3859 rport->roles);
d20ed91b 3860 fc_remote_port_delete(rport);
726b8548 3861 }
df673274 3862 qlt_do_generation_tick(vha, &now);
2d70c103 3863 }
d97994dc
AV		 3864}
3865
1da177e4
LT		 3866/*
3867 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3868 *
3869 * Input: ha = adapter block pointer. fcport = port structure pointer.
3870 *
3871 * Return: None.
3872 *
3873 * Context:
3874 */
e315cd28 3875void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3876 int do_login, int defer)
1da177e4 3877{
8ae6d9c7
GM		 3878 if (IS_QLAFX00(vha->hw)) {
3879 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3880 qla2x00_schedule_rport_del(vha, fcport, defer);
3881 return;
3882 }
3883
2c3dfe3f 3884 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3885 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3886 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3887 qla2x00_schedule_rport_del(vha, fcport, defer);
3888 }
fa2a1ce5 3889 /*
1da177e4
LT		 3890 * We may need to retry the login, so don't change the state of the
3891 * port but do the retries.
3892 */
3893 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3894 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3895
3896 if (!do_login)
3897 return;
3898
a1d0285e 3899 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1da177e4
LT		 3900}
3901
3902/*
3903 * qla2x00_mark_all_devices_lost
3904 * Updates fcport state when device goes offline.
3905 *
3906 * Input:
3907 * ha = adapter block pointer.
3908 * fcport = port structure pointer.
3909 *
3910 * Return:
3911 * None.
3912 *
3913 * Context:
3914 */
3915void
e315cd28 3916qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3917{
3918 fc_port_t *fcport;
3919
83548fe2
QT		 3920 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3921 "Mark all dev lost\n");
726b8548 3922
e315cd28 3923 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548 3924 fcport->scan_state = 0;
d8630bb9 3925 qlt_schedule_sess_for_deletion(fcport);
726b8548 3926
c6d39e23 3927 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3928 continue;
0d6e61bc 3929
1da177e4
LT		 3930 /*
3931 * No point in marking the device as lost, if the device is
3932 * already DEAD.
3933 */
3934 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3935 continue;
e315cd28 3936 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3937 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3938 if (defer)
3939 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3940 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3941 qla2x00_schedule_rport_del(vha, fcport, defer);
3942 }
1da177e4
LT		 3943 }
3944}
3945
0e145a59
BVA		 3946static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha)
3947{
3948 int i;
3949
3950 if (IS_FWI2_CAPABLE(ha))
3951 return;
3952
3953 for (i = 0; i < SNS_FIRST_LOOP_ID; i++)
3954 set_bit(i, ha->loop_id_map);
3955 set_bit(MANAGEMENT_SERVER, ha->loop_id_map);
3956 set_bit(BROADCAST, ha->loop_id_map);
3957}
3958
1da177e4
LT		 3959/*
3960* qla2x00_mem_alloc
3961* Allocates adapter memory.
3962*
3963* Returns:
3964* 0 = success.
e8711085 3965* !0 = failure.
1da177e4 3966*/
e8711085 3967static int
73208dfd
AC		 3968qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3969 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3970{
3971 char name[16];
1da177e4 3972
e8711085 3973 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3974 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3975 if (!ha->init_cb)
e315cd28 3976 goto fail;
e8711085 3977
2d70c103
NB		 3978 if (qlt_mem_alloc(ha) < 0)
3979 goto fail_free_init_cb;
3980
642ef983
CD		 3981 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3982 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3983 if (!ha->gid_list)
2d70c103 3984 goto fail_free_tgt_mem;
1da177e4 3985
e8711085
AV		 3986 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3987 if (!ha->srb_mempool)
e315cd28 3988 goto fail_free_gid_list;
e8711085 3989
7ec0effd 3990 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3991 /* Allocate cache for CT6 Ctx. */
3992 if (!ctx_cachep) {
3993 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3994 sizeof(struct ct6_dsd), 0,
3995 SLAB_HWCACHE_ALIGN, NULL);
3996 if (!ctx_cachep)
fc1ffd6c 3997 goto fail_free_srb_mempool;
a9083016
GM		 3998 }
3999 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
4000 ctx_cachep);
4001 if (!ha->ctx_mempool)
4002 goto fail_free_srb_mempool;
7c3df132
SK		 4003 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
4004 "ctx_cachep=%p ctx_mempool=%p.\n",
4005 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 4006 }
4007
e8711085
AV		 4008 /* Get memory for cached NVRAM */
4009 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
4010 if (!ha->nvram)
a9083016 4011 goto fail_free_ctx_mempool;
e8711085 4012
e315cd28
AC		 4013 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
4014 ha->pdev->device);
4015 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4016 DMA_POOL_SIZE, 8, 0);
4017 if (!ha->s_dma_pool)
4018 goto fail_free_nvram;
4019
7c3df132
SK		 4020 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
4021 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
4022 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
4023
7ec0effd 4024 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 4025 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4026 DSD_LIST_DMA_POOL_SIZE, 8, 0);
4027 if (!ha->dl_dma_pool) {
7c3df132
SK		 4028 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
4029 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 4030 goto fail_s_dma_pool;
4031 }
4032
4033 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
4034 FCP_CMND_DMA_POOL_SIZE, 8, 0);
4035 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 4036 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4037 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 4038 goto fail_dl_dma_pool;
4039 }
50b81275
GM		 4040
4041 if (ql2xenabledif) {
4042 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE;
4043 struct dsd_dma *dsd, *nxt;
4044 uint i;
4045 /* Creata a DMA pool of buffers for DIF bundling */
4046 ha->dif_bundl_pool = dma_pool_create(name,
4047 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0);
4048 if (!ha->dif_bundl_pool) {
4049 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4050 "%s: failed create dif_bundl_pool\n",
4051 __func__);
4052 goto fail_dif_bundl_dma_pool;
4053 }
4054
4055 INIT_LIST_HEAD(&ha->pool.good.head);
4056 INIT_LIST_HEAD(&ha->pool.unusable.head);
4057 ha->pool.good.count = 0;
4058 ha->pool.unusable.count = 0;
4059 for (i = 0; i < 128; i++) {
4060 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC);
4061 if (!dsd) {
4062 ql_dbg_pci(ql_dbg_init, ha->pdev,
4063 0xe0ee, "%s: failed alloc dsd\n",
4064 __func__);
4065 return 1;
4066 }
4067 ha->dif_bundle_kallocs++;
4068
4069 dsd->dsd_addr = dma_pool_alloc(
4070 ha->dif_bundl_pool, GFP_ATOMIC,
4071 &dsd->dsd_list_dma);
4072 if (!dsd->dsd_addr) {
4073 ql_dbg_pci(ql_dbg_init, ha->pdev,
4074 0xe0ee,
4075 "%s: failed alloc ->dsd_addr\n",
4076 __func__);
4077 kfree(dsd);
4078 ha->dif_bundle_kallocs--;
4079 continue;
4080 }
4081 ha->dif_bundle_dma_allocs++;
4082
4083 /*
4084 * if DMA buffer crosses 4G boundary,
4085 * put it on bad list
4086 */
4087 if (MSD(dsd->dsd_list_dma) ^
4088 MSD(dsd->dsd_list_dma + bufsize)) {
4089 list_add_tail(&dsd->list,
4090 &ha->pool.unusable.head);
4091 ha->pool.unusable.count++;
4092 } else {
4093 list_add_tail(&dsd->list,
4094 &ha->pool.good.head);
4095 ha->pool.good.count++;
4096 }
4097 }
4098
4099 /* return the good ones back to the pool */
4100 list_for_each_entry_safe(dsd, nxt,
4101 &ha->pool.good.head, list) {
4102 list_del(&dsd->list);
4103 dma_pool_free(ha->dif_bundl_pool,
4104 dsd->dsd_addr, dsd->dsd_list_dma);
4105 ha->dif_bundle_dma_allocs--;
4106 kfree(dsd);
4107 ha->dif_bundle_kallocs--;
4108 }
4109
4110 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024,
4111 "%s: dif dma pool (good=%u unusable=%u)\n",
4112 __func__, ha->pool.good.count,
4113 ha->pool.unusable.count);
4114 }
4115
7c3df132 4116 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
50b81275
GM		 4117 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n",
4118 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool,
4119 ha->dif_bundl_pool);
a9083016
GM		 4120 }
4121
e8711085
AV		 4122 /* Allocate memory for SNS commands */
4123 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 4124 /* Get consistent memory allocated for SNS commands */
e8711085 4125 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4126 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 4127 if (!ha->sns_cmd)
e315cd28 4128 goto fail_dma_pool;
7c3df132 4129 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 4130 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 4131 } else {
e315cd28 4132 /* Get consistent memory allocated for MS IOCB */
e8711085 4133 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 4134 &ha->ms_iocb_dma);
e8711085 4135 if (!ha->ms_iocb)
e315cd28
AC		 4136 goto fail_dma_pool;
4137 /* Get consistent memory allocated for CT SNS commands */
e8711085 4138 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 4139 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 4140 if (!ha->ct_sns)
4141 goto fail_free_ms_iocb;
7c3df132
SK		 4142 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4143 "ms_iocb=%p ct_sns=%p.\n",
4144 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 4145 }
4146
e315cd28 4147 /* Allocate memory for request ring */
73208dfd
AC		 4148 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4149 if (!*req) {
7c3df132
SK		 4150 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4151 "Failed to allocate memory for req.\n");
e315cd28
AC		 4152 goto fail_req;
4153 }
73208dfd
AC		 4154 (*req)->length = req_len;
4155 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4156 ((*req)->length + 1) * sizeof(request_t),
4157 &(*req)->dma, GFP_KERNEL);
4158 if (!(*req)->ring) {
7c3df132
SK		 4159 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4160 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 4161 goto fail_req_ring;
4162 }
4163 /* Allocate memory for response ring */
73208dfd
AC		 4164 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4165 if (!*rsp) {
7c3df132
SK		 4166 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4167 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 4168 goto fail_rsp;
4169 }
73208dfd
AC		 4170 (*rsp)->hw = ha;
4171 (*rsp)->length = rsp_len;
4172 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4173 ((*rsp)->length + 1) * sizeof(response_t),
4174 &(*rsp)->dma, GFP_KERNEL);
4175 if (!(*rsp)->ring) {
7c3df132
SK		 4176 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4177 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 4178 goto fail_rsp_ring;
4179 }
73208dfd
AC		 4180 (*req)->rsp = *rsp;
4181 (*rsp)->req = *req;
7c3df132
SK		 4182 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4183 "req=%p req->length=%d req->ring=%p rsp=%p "
4184 "rsp->length=%d rsp->ring=%p.\n",
4185 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4186 (*rsp)->ring);
73208dfd
AC		 4187 /* Allocate memory for NVRAM data for vports */
4188 if (ha->nvram_npiv_size) {
6396bb22
KC		 4189 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4190 sizeof(struct qla_npiv_entry),
4191 GFP_KERNEL);
73208dfd 4192 if (!ha->npiv_info) {
7c3df132
SK		 4193 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4194 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 4195 goto fail_npiv_info;
4196 }
4197 } else
4198 ha->npiv_info = NULL;
e8711085 4199
b64b0e8f 4200 /* Get consistent memory allocated for EX-INIT-CB. */
ecc89f25
JC		 4201 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) ||
4202 IS_QLA28XX(ha)) {
b64b0e8f
AV		 4203 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4204 &ha->ex_init_cb_dma);
4205 if (!ha->ex_init_cb)
4206 goto fail_ex_init_cb;
7c3df132
SK		 4207 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4208 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4209 }
4210
a9083016
GM		 4211 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4212
5ff1d584
AV		 4213 /* Get consistent memory allocated for Async Port-Database. */
4214 if (!IS_FWI2_CAPABLE(ha)) {
4215 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4216 &ha->async_pd_dma);
4217 if (!ha->async_pd)
4218 goto fail_async_pd;
7c3df132
SK		 4219 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4220 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4221 }
4222
e315cd28 4223 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4224
4225 /* Allocate memory for our loop_id bitmap */
6396bb22
KC		 4226 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4227 sizeof(long),
4228 GFP_KERNEL);
5f16b331 4229 if (!ha->loop_id_map)
fc1ffd6c 4230 goto fail_loop_id_map;
5f16b331
CD		 4231 else {
4232 qla2x00_set_reserved_loop_ids(ha);
4233 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4234 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4235 }
4236
e4e3a2ce
QT		 4237 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4238 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4239 if (!ha->sfp_data) {
4240 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4241 "Unable to allocate memory for SFP read-data.\n");
4242 goto fail_sfp_data;
4243 }
4244
3f006ac3
MH		 4245 ha->flt = dma_alloc_coherent(&ha->pdev->dev,
4246 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma,
4247 GFP_KERNEL);
4248 if (!ha->flt) {
4249 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4250 "Unable to allocate memory for FLT.\n");
4251 goto fail_flt_buffer;
4252 }
4253
b2a72ec3 4254 return 0;
e315cd28 4255
3f006ac3
MH		 4256fail_flt_buffer:
4257 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4258 ha->sfp_data, ha->sfp_data_dma);
e4e3a2ce
QT		 4259fail_sfp_data:
4260 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4261fail_loop_id_map:
4262 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4263fail_async_pd:
4264 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4265fail_ex_init_cb:
4266 kfree(ha->npiv_info);
73208dfd
AC		 4267fail_npiv_info:
4268 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4269 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4270 (*rsp)->ring = NULL;
4271 (*rsp)->dma = 0;
e315cd28 4272fail_rsp_ring:
73208dfd 4273 kfree(*rsp);
6d634067 4274 *rsp = NULL;
e315cd28 4275fail_rsp:
73208dfd
AC		 4276 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4277 sizeof(request_t), (*req)->ring, (*req)->dma);
4278 (*req)->ring = NULL;
4279 (*req)->dma = 0;
e315cd28 4280fail_req_ring:
73208dfd 4281 kfree(*req);
6d634067 4282 *req = NULL;
e315cd28
AC		 4283fail_req:
4284 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4285 ha->ct_sns, ha->ct_sns_dma);
4286 ha->ct_sns = NULL;
4287 ha->ct_sns_dma = 0;
e8711085
AV		 4288fail_free_ms_iocb:
4289 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4290 ha->ms_iocb = NULL;
4291 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4292
4293 if (ha->sns_cmd)
4294 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4295 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4296fail_dma_pool:
50b81275
GM		 4297 if (ql2xenabledif) {
4298 struct dsd_dma *dsd, *nxt;
4299
4300 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4301 list) {
4302 list_del(&dsd->list);
4303 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4304 dsd->dsd_list_dma);
4305 ha->dif_bundle_dma_allocs--;
4306 kfree(dsd);
4307 ha->dif_bundle_kallocs--;
4308 ha->pool.unusable.count--;
4309 }
4310 dma_pool_destroy(ha->dif_bundl_pool);
4311 ha->dif_bundl_pool = NULL;
4312 }
4313
4314fail_dif_bundl_dma_pool:
bad75002 4315 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4316 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4317 ha->fcp_cmnd_dma_pool = NULL;
4318 }
4319fail_dl_dma_pool:
bad75002 4320 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4321 dma_pool_destroy(ha->dl_dma_pool);
4322 ha->dl_dma_pool = NULL;
4323 }
4324fail_s_dma_pool:
e315cd28
AC		 4325 dma_pool_destroy(ha->s_dma_pool);
4326 ha->s_dma_pool = NULL;
e8711085
AV		 4327fail_free_nvram:
4328 kfree(ha->nvram);
4329 ha->nvram = NULL;
a9083016 4330fail_free_ctx_mempool:
75c1d48a 4331 mempool_destroy(ha->ctx_mempool);
a9083016 4332 ha->ctx_mempool = NULL;
e8711085 4333fail_free_srb_mempool:
75c1d48a 4334 mempool_destroy(ha->srb_mempool);
e8711085 4335 ha->srb_mempool = NULL;
e8711085 4336fail_free_gid_list:
642ef983
CD		 4337 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4338 ha->gid_list,
e315cd28 4339 ha->gid_list_dma);
e8711085
AV		 4340 ha->gid_list = NULL;
4341 ha->gid_list_dma = 0;
2d70c103
NB		 4342fail_free_tgt_mem:
4343 qlt_mem_free(ha);
e315cd28
AC		 4344fail_free_init_cb:
4345 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4346 ha->init_cb_dma);
4347 ha->init_cb = NULL;
4348 ha->init_cb_dma = 0;
e8711085 4349fail:
7c3df132
SK		 4350 ql_log(ql_log_fatal, NULL, 0x0030,
4351 "Memory allocation failure.\n");
e8711085 4352 return -ENOMEM;
1da177e4
LT		 4353}
4354
b0d6cabd
HM		 4355int
4356qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4357{
4358 int rval;
4359 uint16_t size, max_cnt, temp;
4360 struct qla_hw_data *ha = vha->hw;
4361
4362 /* Return if we don't need to alloacate any extended logins */
4363 if (!ql2xexlogins)
4364 return QLA_SUCCESS;
4365
99e1b683
QT		 4366 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4367 return QLA_SUCCESS;
4368
b0d6cabd
HM		 4369 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4370 max_cnt = 0;
4371 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4372 if (rval != QLA_SUCCESS) {
4373 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4374 "Failed to get exlogin status.\n");
4375 return rval;
4376 }
4377
4378 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4379 temp *= size;
4380
4381 if (temp != ha->exlogin_size) {
4382 qla2x00_free_exlogin_buffer(ha);
4383 ha->exlogin_size = temp;
4384
4385 ql_log(ql_log_info, vha, 0xd024,
4386 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4387 max_cnt, size, temp);
4388
4389 ql_log(ql_log_info, vha, 0xd025,
4390 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4391
4392 /* Get consistent memory for extended logins */
4393 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4394 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4395 if (!ha->exlogin_buf) {
4396 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4397 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4398 return -ENOMEM;
4399 }
b0d6cabd
HM		 4400 }
4401
4402 /* Now configure the dma buffer */
4403 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4404 if (rval) {
83548fe2 4405 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4406 "Setup extended login buffer ****FAILED****.\n");
4407 qla2x00_free_exlogin_buffer(ha);
4408 }
4409
4410 return rval;
4411}
4412
4413/*
4414* qla2x00_free_exlogin_buffer
4415*
4416* Input:
4417* ha = adapter block pointer
4418*/
4419void
4420qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4421{
4422 if (ha->exlogin_buf) {
4423 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4424 ha->exlogin_buf, ha->exlogin_buf_dma);
4425 ha->exlogin_buf = NULL;
4426 ha->exlogin_size = 0;
4427 }
4428}
4429
99e1b683
QT		 4430static void
4431qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4432{
4433 u32 temp;
0645cb83 4434 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
99e1b683
QT		 4435 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4436
d1e3635a
QT		 4437 if (max_cnt > vha->hw->max_exchg)
4438 max_cnt = vha->hw->max_exchg;
4439
99e1b683 4440 if (qla_ini_mode_enabled(vha)) {
0645cb83
QT		 4441 if (vha->ql2xiniexchg > max_cnt)
4442 vha->ql2xiniexchg = max_cnt;
4443
4444 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4445 *ret_cnt = vha->ql2xiniexchg;
99e1b683 4446
99e1b683 4447 } else if (qla_tgt_mode_enabled(vha)) {
0645cb83
QT		 4448 if (vha->ql2xexchoffld > max_cnt) {
4449 vha->ql2xexchoffld = max_cnt;
4450 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4451 }
99e1b683 4452
0645cb83
QT		 4453 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4454 *ret_cnt = vha->ql2xexchoffld;
99e1b683 4455 } else if (qla_dual_mode_enabled(vha)) {
0645cb83 4456 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
99e1b683 4457 if (temp > max_cnt) {
0645cb83
QT		 4458 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4459 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
99e1b683 4460 temp = max_cnt;
0645cb83 4461 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
99e1b683
QT		 4462 }
4463
4464 if (temp > FW_DEF_EXCHANGES_CNT)
4465 *ret_cnt = temp;
4466 }
4467}
4468
2f56a7f1
HM		 4469int
4470qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4471{
4472 int rval;
d1e3635a
QT		 4473 u16 size, max_cnt;
4474 u32 actual_cnt, totsz;
2f56a7f1
HM		 4475 struct qla_hw_data *ha = vha->hw;
4476
99e1b683
QT		 4477 if (!ha->flags.exchoffld_enabled)
4478 return QLA_SUCCESS;
4479
4480 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4481 return QLA_SUCCESS;
4482
2f56a7f1
HM		 4483 max_cnt = 0;
4484 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4485 if (rval != QLA_SUCCESS) {
4486 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4487 "Failed to get exlogin status.\n");
4488 return rval;
4489 }
4490
d1e3635a
QT		 4491 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4492 ql_log(ql_log_info, vha, 0xd014,
4493 "Actual exchange offload count: %d.\n", actual_cnt);
4494
4495 totsz = actual_cnt * size;
2f56a7f1 4496
d1e3635a 4497 if (totsz != ha->exchoffld_size) {
99e1b683 4498 qla2x00_free_exchoffld_buffer(ha);
0645cb83
QT		 4499 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4500 ha->exchoffld_size = 0;
4501 ha->flags.exchoffld_enabled = 0;
4502 return QLA_SUCCESS;
4503 }
4504
d1e3635a 4505 ha->exchoffld_size = totsz;
99e1b683
QT		 4506
4507 ql_log(ql_log_info, vha, 0xd016,
d1e3635a
QT		 4508 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4509 max_cnt, actual_cnt, size, totsz);
99e1b683
QT		 4510
4511 ql_log(ql_log_info, vha, 0xd017,
4512 "Exchange Buffers requested size = 0x%x\n",
4513 ha->exchoffld_size);
4514
4515 /* Get consistent memory for extended logins */
4516 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4517 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4518 if (!ha->exchoffld_buf) {
4519 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
d1e3635a
QT		 4520 "Failed to allocate memory for Exchange Offload.\n");
4521
4522 if (ha->max_exchg >
4523 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4524 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4525 } else if (ha->max_exchg >
4526 (FW_DEF_EXCHANGES_CNT + 512)) {
4527 ha->max_exchg -= 512;
4528 } else {
4529 ha->flags.exchoffld_enabled = 0;
4530 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4531 "Disabling Exchange offload due to lack of memory\n");
4532 }
4533 ha->exchoffld_size = 0;
4534
99e1b683
QT		 4535 return -ENOMEM;
4536 }
0645cb83
QT		 4537 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4538 /* pathological case */
4539 qla2x00_free_exchoffld_buffer(ha);
4540 ha->exchoffld_size = 0;
4541 ha->flags.exchoffld_enabled = 0;
4542 ql_log(ql_log_info, vha, 0xd016,
4543 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4544 ha->exchoffld_size, actual_cnt, size, totsz);
4545 return 0;
2f56a7f1
HM		 4546 }
4547
4548 /* Now configure the dma buffer */
99e1b683 4549 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4550 if (rval) {
4551 ql_log(ql_log_fatal, vha, 0xd02e,
4552 "Setup exchange offload buffer ****FAILED****.\n");
4553 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4554 } else {
4555 /* re-adjust number of target exchange */
4556 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4557
4558 if (qla_ini_mode_enabled(vha))
4559 icb->exchange_count = 0;
4560 else
0645cb83 4561 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
2f56a7f1
HM		 4562 }
4563
4564 return rval;
4565}
4566
4567/*
4568* qla2x00_free_exchoffld_buffer
4569*
4570* Input:
4571* ha = adapter block pointer
4572*/
4573void
4574qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4575{
4576 if (ha->exchoffld_buf) {
4577 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4578 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4579 ha->exchoffld_buf = NULL;
4580 ha->exchoffld_size = 0;
4581 }
4582}
4583
1da177e4 4584/*
e30d1756
MI		 4585* qla2x00_free_fw_dump
4586* Frees fw dump stuff.
1da177e4
LT		 4587*
4588* Input:
7ec0effd 4589* ha = adapter block pointer
1da177e4 4590*/
a824ebb3 4591static void
e30d1756 4592qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4593{
a28d9e4e
JC		 4594 struct fwdt *fwdt = ha->fwdt;
4595 uint j;
4596
df613b96 4597 if (ha->fce)
f73cb695
CD		 4598 dma_free_coherent(&ha->pdev->dev,
4599 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4600
f73cb695
CD		 4601 if (ha->eft)
4602 dma_free_coherent(&ha->pdev->dev,
4603 EFT_SIZE, ha->eft, ha->eft_dma);
4604
4605 if (ha->fw_dump)
a7a167bf 4606 vfree(ha->fw_dump);
f73cb695 4607
e30d1756
MI		 4608 ha->fce = NULL;
4609 ha->fce_dma = 0;
4610 ha->eft = NULL;
4611 ha->eft_dma = 0;
e30d1756 4612 ha->fw_dumped = 0;
61f098dd 4613 ha->fw_dump_cap_flags = 0;
e30d1756 4614 ha->fw_dump_reading = 0;
f73cb695
CD		 4615 ha->fw_dump = NULL;
4616 ha->fw_dump_len = 0;
a28d9e4e
JC		 4617
4618 for (j = 0; j < 2; j++, fwdt++) {
4619 if (fwdt->template)
4620 vfree(fwdt->template);
4621 fwdt->template = NULL;
4622 fwdt->length = 0;
4623 }
e30d1756
MI		 4624}
4625
4626/*
4627* qla2x00_mem_free
4628* Frees all adapter allocated memory.
4629*
4630* Input:
4631* ha = adapter block pointer.
4632*/
4633static void
4634qla2x00_mem_free(struct qla_hw_data *ha)
4635{
4636 qla2x00_free_fw_dump(ha);
4637
81178772
SK		 4638 if (ha->mctp_dump)
4639 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4640 ha->mctp_dump_dma);
5365bf99 4641 ha->mctp_dump = NULL;
81178772 4642
75c1d48a 4643 mempool_destroy(ha->srb_mempool);
5365bf99 4644 ha->srb_mempool = NULL;
a7a167bf 4645
11bbc1d8
AV		 4646 if (ha->dcbx_tlv)
4647 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4648 ha->dcbx_tlv, ha->dcbx_tlv_dma);
5365bf99 4649 ha->dcbx_tlv = NULL;
11bbc1d8 4650
ce0423f4
AV		 4651 if (ha->xgmac_data)
4652 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4653 ha->xgmac_data, ha->xgmac_data_dma);
5365bf99 4654 ha->xgmac_data = NULL;
ce0423f4 4655
1da177e4
LT		 4656 if (ha->sns_cmd)
4657 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4658 ha->sns_cmd, ha->sns_cmd_dma);
5365bf99
BVA		 4659 ha->sns_cmd = NULL;
4660 ha->sns_cmd_dma = 0;
1da177e4
LT		 4661
4662 if (ha->ct_sns)
4663 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4664 ha->ct_sns, ha->ct_sns_dma);
5365bf99
BVA		 4665 ha->ct_sns = NULL;
4666 ha->ct_sns_dma = 0;
1da177e4 4667
88729e53 4668 if (ha->sfp_data)
e4e3a2ce
QT		 4669 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4670 ha->sfp_data_dma);
5365bf99 4671 ha->sfp_data = NULL;
88729e53 4672
3f006ac3
MH		 4673 if (ha->flt)
4674 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE,
4675 ha->flt, ha->flt_dma);
dc035d4e
BVA		 4676 ha->flt = NULL;
4677 ha->flt_dma = 0;
3f006ac3 4678
1da177e4
LT		 4679 if (ha->ms_iocb)
4680 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
5365bf99
BVA		 4681 ha->ms_iocb = NULL;
4682 ha->ms_iocb_dma = 0;
1da177e4 4683
b64b0e8f 4684 if (ha->ex_init_cb)
a9083016
GM		 4685 dma_pool_free(ha->s_dma_pool,
4686 ha->ex_init_cb, ha->ex_init_cb_dma);
5365bf99
BVA		 4687 ha->ex_init_cb = NULL;
4688 ha->ex_init_cb_dma = 0;
b64b0e8f 4689
5ff1d584
AV		 4690 if (ha->async_pd)
4691 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5365bf99
BVA		 4692 ha->async_pd = NULL;
4693 ha->async_pd_dma = 0;
5ff1d584 4694
75c1d48a 4695 dma_pool_destroy(ha->s_dma_pool);
5365bf99 4696 ha->s_dma_pool = NULL;
1da177e4 4697
1da177e4 4698 if (ha->gid_list)
642ef983
CD		 4699 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4700 ha->gid_list, ha->gid_list_dma);
5365bf99
BVA		 4701 ha->gid_list = NULL;
4702 ha->gid_list_dma = 0;
1da177e4 4703
a9083016
GM		 4704 if (IS_QLA82XX(ha)) {
4705 if (!list_empty(&ha->gbl_dsd_list)) {
4706 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4707
4708 /* clean up allocated prev pool */
4709 list_for_each_entry_safe(dsd_ptr,
4710 tdsd_ptr, &ha->gbl_dsd_list, list) {
4711 dma_pool_free(ha->dl_dma_pool,
4712 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4713 list_del(&dsd_ptr->list);
4714 kfree(dsd_ptr);
4715 }
4716 }
4717 }
4718
75c1d48a 4719 dma_pool_destroy(ha->dl_dma_pool);
5365bf99 4720 ha->dl_dma_pool = NULL;
a9083016 4721
75c1d48a 4722 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
5365bf99 4723 ha->fcp_cmnd_dma_pool = NULL;
a9083016 4724
75c1d48a 4725 mempool_destroy(ha->ctx_mempool);
5365bf99 4726 ha->ctx_mempool = NULL;
a9083016 4727
50b81275
GM		 4728 if (ql2xenabledif) {
4729 struct dsd_dma *dsd, *nxt;
4730
4731 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head,
4732 list) {
4733 list_del(&dsd->list);
4734 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4735 dsd->dsd_list_dma);
4736 ha->dif_bundle_dma_allocs--;
4737 kfree(dsd);
4738 ha->dif_bundle_kallocs--;
4739 ha->pool.unusable.count--;
4740 }
4741 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) {
4742 list_del(&dsd->list);
4743 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr,
4744 dsd->dsd_list_dma);
4745 ha->dif_bundle_dma_allocs--;
4746 kfree(dsd);
4747 ha->dif_bundle_kallocs--;
4748 }
4749 }
4750
4751 if (ha->dif_bundl_pool)
4752 dma_pool_destroy(ha->dif_bundl_pool);
dc035d4e 4753 ha->dif_bundl_pool = NULL;
50b81275 4754
2d70c103
NB		 4755 qlt_mem_free(ha);
4756
e315cd28
AC		 4757 if (ha->init_cb)
4758 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4759 ha->init_cb, ha->init_cb_dma);
5365bf99
BVA		 4760 ha->init_cb = NULL;
4761 ha->init_cb_dma = 0;
6a2cf8d3 4762
6d634067 4763 vfree(ha->optrom_buffer);
5365bf99 4764 ha->optrom_buffer = NULL;
6d634067 4765 kfree(ha->nvram);
5365bf99 4766 ha->nvram = NULL;
6d634067 4767 kfree(ha->npiv_info);
5365bf99 4768 ha->npiv_info = NULL;
6d634067 4769 kfree(ha->swl);
5365bf99 4770 ha->swl = NULL;
6d634067 4771 kfree(ha->loop_id_map);
6a2cf8d3 4772 ha->loop_id_map = NULL;
e315cd28 4773}
1da177e4 4774
e315cd28
AC		 4775struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4776 struct qla_hw_data *ha)
4777{
4778 struct Scsi_Host *host;
4779 struct scsi_qla_host *vha = NULL;
854165f4 4780
e315cd28 4781 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4782 if (!host) {
7c3df132
SK		 4783 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4784 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4785 return NULL;
e315cd28
AC		 4786 }
4787
4788 /* Clear our data area */
4789 vha = shost_priv(host);
4790 memset(vha, 0, sizeof(scsi_qla_host_t));
4791
4792 vha->host = host;
4793 vha->host_no = host->host_no;
4794 vha->hw = ha;
4795
0645cb83
QT		 4796 vha->qlini_mode = ql2x_ini_mode;
4797 vha->ql2xexchoffld = ql2xexchoffld;
4798 vha->ql2xiniexchg = ql2xiniexchg;
4799
e315cd28
AC		 4800 INIT_LIST_HEAD(&vha->vp_fcports);
4801 INIT_LIST_HEAD(&vha->work_list);
4802 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4803 INIT_LIST_HEAD(&vha->qla_cmd_list);
4804 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4805 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4806 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4807 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4808 INIT_LIST_HEAD(&vha->gnl.fcports);
2d73ac61 4809 INIT_LIST_HEAD(&vha->gpnid_list);
9b3e0f4d 4810 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
e315cd28 4811
f999f4c1 4812 spin_lock_init(&vha->work_lock);
8b2f5ff3 4813 spin_lock_init(&vha->cmd_list_lock);
726b8548 4814 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4815 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4816
2fdbc65e
BVA		 4817 vha->gnl.size = sizeof(struct get_name_list_extended) *
4818 (ha->max_loop_id + 1);
41dc529a
QT		 4819 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4820 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4821 if (!vha->gnl.l) {
83548fe2 4822 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4823 "Alloc failed for name list.\n");
4824 scsi_remove_host(vha->host);
4825 return NULL;
4826 }
f999f4c1 4827
a4239945
QT		 4828 /* todo: what about ext login? */
4829 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4830 vha->scan.l = vmalloc(vha->scan.size);
4831 if (!vha->scan.l) {
4832 ql_log(ql_log_fatal, vha, 0xd04a,
4833 "Alloc failed for scan database.\n");
4834 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4835 vha->gnl.l, vha->gnl.ldma);
26fa656e 4836 vha->gnl.l = NULL;
a4239945
QT		 4837 scsi_remove_host(vha->host);
4838 return NULL;
4839 }
f352eeb7 4840 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
a4239945 4841
e315cd28 4842 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4843 ql_dbg(ql_dbg_init, vha, 0x0041,
4844 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4845 vha->host, vha->hw, vha,
4846 dev_name(&(ha->pdev->dev)));
4847
e315cd28 4848 return vha;
1da177e4
LT		 4849}
4850
726b8548 4851struct qla_work_evt *
f999f4c1 4852qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4853{
4854 struct qla_work_evt *e;
feafb7b1
AE		 4855 uint8_t bail;
4856
4857 QLA_VHA_MARK_BUSY(vha, bail);
4858 if (bail)
4859 return NULL;
0971de7f 4860
f999f4c1 4861 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4862 if (!e) {
4863 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4864 return NULL;
feafb7b1 4865 }
0971de7f
AV		 4866
4867 INIT_LIST_HEAD(&e->list);
4868 e->type = type;
4869 e->flags = QLA_EVT_FLAG_FREE;
4870 return e;
4871}
4872
726b8548 4873int
f999f4c1 4874qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4875{
f999f4c1 4876 unsigned long flags;
9b3e0f4d 4877 bool q = false;
0971de7f 4878
f999f4c1 4879 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4880 list_add_tail(&e->list, &vha->work_list);
9b3e0f4d
QT		 4881
4882 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4883 q = true;
4884
f999f4c1 4885 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2 4886
9b3e0f4d
QT		 4887 if (q)
4888 queue_work(vha->hw->wq, &vha->iocb_work);
f999f4c1 4889
0971de7f
AV		 4890 return QLA_SUCCESS;
4891}
4892
4893int
e315cd28 4894qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4895 u32 data)
4896{
4897 struct qla_work_evt *e;
4898
f999f4c1 4899 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4900 if (!e)
4901 return QLA_FUNCTION_FAILED;
4902
4903 e->u.aen.code = code;
4904 e->u.aen.data = data;
f999f4c1 4905 return qla2x00_post_work(vha, e);
0971de7f
AV		 4906}
4907
8a659571
AV		 4908int
4909qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4910{
4911 struct qla_work_evt *e;
4912
f999f4c1 4913 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4914 if (!e)
4915 return QLA_FUNCTION_FAILED;
4916
4917 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4918 return qla2x00_post_work(vha, e);
8a659571
AV		 4919}
4920
ac280b67
AV		 4921#define qla2x00_post_async_work(name, type) \
4922int qla2x00_post_async_##name##_work( \
4923 struct scsi_qla_host *vha, \
4924 fc_port_t *fcport, uint16_t *data) \
4925{ \
4926 struct qla_work_evt *e; \
4927 \
4928 e = qla2x00_alloc_work(vha, type); \
4929 if (!e) \
4930 return QLA_FUNCTION_FAILED; \
4931 \
4932 e->u.logio.fcport = fcport; \
4933 if (data) { \
4934 e->u.logio.data[0] = data[0]; \
4935 e->u.logio.data[1] = data[1]; \
4936 } \
6d674927 4937 fcport->flags |= FCF_ASYNC_ACTIVE; \
ac280b67
AV		 4938 return qla2x00_post_work(vha, e); \
4939}
4940
4941qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4942qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4943qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584 4944qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
11aea16a
QT		 4945qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4946qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
ac280b67 4947
3420d36c
AV		 4948int
4949qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4950{
4951 struct qla_work_evt *e;
4952
4953 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4954 if (!e)
4955 return QLA_FUNCTION_FAILED;
4956
4957 e->u.uevent.code = code;
4958 return qla2x00_post_work(vha, e);
4959}
4960
4961static void
4962qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4963{
4964 char event_string[40];
4965 char *envp[] = { event_string, NULL };
4966
4967 switch (code) {
4968 case QLA_UEVENT_CODE_FW_DUMP:
4969 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4970 vha->host_no);
4971 break;
4972 default:
4973 /* do nothing */
4974 break;
4975 }
4976 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4977}
4978
8ae6d9c7
GM		 4979int
4980qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4981 uint32_t *data, int cnt)
4982{
4983 struct qla_work_evt *e;
4984
4985 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4986 if (!e)
4987 return QLA_FUNCTION_FAILED;
4988
4989 e->u.aenfx.evtcode = evtcode;
4990 e->u.aenfx.count = cnt;
4991 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4992 return qla2x00_post_work(vha, e);
4993}
4994
cd4ed6b4 4995void qla24xx_sched_upd_fcport(fc_port_t *fcport)
726b8548 4996{
cd4ed6b4 4997 unsigned long flags;
726b8548 4998
cd4ed6b4
QT		 4999 if (IS_SW_RESV_ADDR(fcport->d_id))
5000 return;
726b8548 5001
cd4ed6b4
QT		 5002 spin_lock_irqsave(&fcport->vha->work_lock, flags);
5003 if (fcport->disc_state == DSC_UPD_FCPORT) {
5004 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5005 return;
5006 }
5007 fcport->jiffies_at_registration = jiffies;
5008 fcport->sec_since_registration = 0;
5009 fcport->next_disc_state = DSC_DELETED;
5010 fcport->disc_state = DSC_UPD_FCPORT;
5011 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
5012
5013 queue_work(system_unbound_wq, &fcport->reg_work);
726b8548
QT		 5014}
5015
5016static
5017void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
5018{
5019 unsigned long flags;
b5d15312 5020 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 5021 struct qlt_plogi_ack_t *pla =
5022 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 5023 uint8_t free_fcport = 0;
726b8548 5024
9cd883f0
QT		 5025 ql_dbg(ql_dbg_disc, vha, 0xffff,
5026 "%s %d %8phC enter\n",
5027 __func__, __LINE__, e->u.new_sess.port_name);
5028
726b8548
QT		 5029 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5030 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
5031 if (fcport) {
5032 fcport->d_id = e->u.new_sess.id;
5033 if (pla) {
5034 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
9b3e0f4d
QT		 5035 memcpy(fcport->node_name,
5036 pla->iocb.u.isp24.u.plogi.node_name,
5037 WWN_SIZE);
726b8548
QT		 5038 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
5039 /* we took an extra ref_count to prevent PLOGI ACK when
5040 * fcport/sess has not been created.
5041 */
5042 pla->ref_count--;
5043 }
5044 } else {
b5d15312 5045 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 5046 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5047 if (fcport) {
5048 fcport->d_id = e->u.new_sess.id;
726b8548
QT		 5049 fcport->flags |= FCF_FABRIC_DEVICE;
5050 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
c64a87f9 5051 if (e->u.new_sess.fc4_type == FS_FC4TYPE_FCP)
a4239945 5052 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
726b8548 5053
c64a87f9 5054 if (e->u.new_sess.fc4_type == FS_FC4TYPE_NVME) {
2b5b9647
DT		 5055 fcport->fc4_type = FC4_TYPE_OTHER;
5056 fcport->fc4f_nvme = FC4_TYPE_NVME;
5057 }
33b28357 5058
726b8548
QT		 5059 memcpy(fcport->port_name, e->u.new_sess.port_name,
5060 WWN_SIZE);
da892d2d
QT		 5061
5062 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N)
5063 fcport->n2n_flag = 1;
5064
b5d15312
QT		 5065 } else {
5066 ql_dbg(ql_dbg_disc, vha, 0xffff,
5067 "%s %8phC mem alloc fail.\n",
5068 __func__, e->u.new_sess.port_name);
5069
5070 if (pla)
5071 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5072 return;
5073 }
5074
5075 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
a4239945 5076 /* search again to make sure no one else got ahead */
b5d15312
QT		 5077 tfcp = qla2x00_find_fcport_by_wwpn(vha,
5078 e->u.new_sess.port_name, 1);
5079 if (tfcp) {
5080 /* should rarily happen */
5081 ql_dbg(ql_dbg_disc, vha, 0xffff,
5082 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
5083 __func__, tfcp->port_name, tfcp->disc_state,
5084 tfcp->fw_login_state);
5085
5086 free_fcport = 1;
5087 } else {
726b8548
QT		 5088 list_add_tail(&fcport->list, &vha->vp_fcports);
5089
19759033
QT		 5090 }
5091 if (pla) {
5092 qlt_plogi_ack_link(vha, pla, fcport,
5093 QLT_PLOGI_LINK_SAME_WWN);
5094 pla->ref_count--;
726b8548
QT		 5095 }
5096 }
5097 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5098
5099 if (fcport) {
a4239945
QT		 5100 fcport->id_changed = 1;
5101 fcport->scan_state = QLA_FCPORT_FOUND;
45d84c42 5102 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
a4239945
QT		 5103 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
5104
5ef696aa 5105 if (pla) {
9cd883f0
QT		 5106 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
5107 u16 wd3_lo;
5108
5109 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5110 fcport->local = 0;
5111 fcport->loop_id =
5112 le16_to_cpu(
5113 pla->iocb.u.isp24.nport_handle);
5114 fcport->fw_login_state = DSC_LS_PRLI_PEND;
5115 wd3_lo =
5116 le16_to_cpu(
5117 pla->iocb.u.isp24.u.prli.wd3_lo);
5118
5119 if (wd3_lo & BIT_7)
5120 fcport->conf_compl_supported = 1;
5121
5122 if ((wd3_lo & BIT_4) == 0)
5123 fcport->port_type = FCT_INITIATOR;
5124 else
5125 fcport->port_type = FCT_TARGET;
5126 }
726b8548 5127 qlt_plogi_ack_unref(vha, pla);
5ef696aa 5128 } else {
1c6cacf4
HR		 5129 fc_port_t *dfcp = NULL;
5130
5ef696aa
QT		 5131 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5132 tfcp = qla2x00_find_fcport_by_nportid(vha,
5133 &e->u.new_sess.id, 1);
5134 if (tfcp && (tfcp != fcport)) {
5135 /*
5136 * We have a conflict fcport with same NportID.
5137 */
5138 ql_dbg(ql_dbg_disc, vha, 0xffff,
5139 "%s %8phC found conflict b4 add. DS %d LS %d\n",
5140 __func__, tfcp->port_name, tfcp->disc_state,
5141 tfcp->fw_login_state);
5142
5143 switch (tfcp->disc_state) {
5144 case DSC_DELETED:
5145 break;
5146 case DSC_DELETE_PEND:
5147 fcport->login_pause = 1;
5148 tfcp->conflict = fcport;
5149 break;
5150 default:
5151 fcport->login_pause = 1;
5152 tfcp->conflict = fcport;
1c6cacf4 5153 dfcp = tfcp;
5ef696aa
QT		 5154 break;
5155 }
5156 }
5157 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1c6cacf4
HR		 5158 if (dfcp)
5159 qlt_schedule_sess_for_deletion(tfcp);
a4239945 5160
8777e431 5161 if (N2N_TOPO(vha->hw)) {
b61b5953
QT		 5162 fcport->flags &= ~FCF_FABRIC_DEVICE;
5163 fcport->keep_nport_handle = 1;
8777e431
QT		 5164 if (vha->flags.nvme_enabled) {
5165 fcport->fc4f_nvme = 1;
5166 fcport->n2n_flag = 1;
5167 }
5168 fcport->fw_login_state = 0;
5169 /*
5170 * wait link init done before sending login
5171 */
5172 } else {
5173 qla24xx_fcport_handle_login(vha, fcport);
5174 }
5ef696aa 5175 }
726b8548 5176 }
b5d15312
QT		 5177
5178 if (free_fcport) {
5179 qla2x00_free_fcport(fcport);
5180 if (pla)
5181 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5182 }
726b8548
QT		 5183}
5184
e374f9f5
QT		 5185static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5186{
5187 struct srb *sp = e->u.iosb.sp;
5188 int rval;
5189
5190 rval = qla2x00_start_sp(sp);
5191 if (rval != QLA_SUCCESS) {
5192 ql_dbg(ql_dbg_disc, vha, 0x2043,
5193 "%s: %s: Re-issue IOCB failed (%d).\n",
5194 __func__, sp->name, rval);
5195 qla24xx_sp_unmap(vha, sp);
5196 }
5197}
5198
ac280b67 5199void
e315cd28 5200qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 5201{
f999f4c1
AV		 5202 struct qla_work_evt *e, *tmp;
5203 unsigned long flags;
5204 LIST_HEAD(work);
80676d05 5205 int rc;
0971de7f 5206
f999f4c1
AV		 5207 spin_lock_irqsave(&vha->work_lock, flags);
5208 list_splice_init(&vha->work_list, &work);
5209 spin_unlock_irqrestore(&vha->work_lock, flags);
5210
5211 list_for_each_entry_safe(e, tmp, &work, list) {
80676d05 5212 rc = QLA_SUCCESS;
0971de7f
AV		 5213 switch (e->type) {
5214 case QLA_EVT_AEN:
e315cd28 5215 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 5216 e->u.aen.code, e->u.aen.data);
5217 break;
8a659571
AV		 5218 case QLA_EVT_IDC_ACK:
5219 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5220 break;
ac280b67
AV		 5221 case QLA_EVT_ASYNC_LOGIN:
5222 qla2x00_async_login(vha, e->u.logio.fcport,
5223 e->u.logio.data);
5224 break;
ac280b67 5225 case QLA_EVT_ASYNC_LOGOUT:
80676d05 5226 rc = qla2x00_async_logout(vha, e->u.logio.fcport);
ac280b67
AV		 5227 break;
5228 case QLA_EVT_ASYNC_LOGOUT_DONE:
5229 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5230 e->u.logio.data);
5231 break;
5ff1d584
AV		 5232 case QLA_EVT_ASYNC_ADISC:
5233 qla2x00_async_adisc(vha, e->u.logio.fcport,
5234 e->u.logio.data);
5235 break;
3420d36c
AV		 5236 case QLA_EVT_UEVENT:
5237 qla2x00_uevent_emit(vha, e->u.uevent.code);
5238 break;
8ae6d9c7
GM		 5239 case QLA_EVT_AENFX:
5240 qlafx00_process_aen(vha, e);
5241 break;
726b8548
QT		 5242 case QLA_EVT_GPNID:
5243 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5244 break;
e374f9f5
QT		 5245 case QLA_EVT_UNMAP:
5246 qla24xx_sp_unmap(vha, e->u.iosb.sp);
726b8548 5247 break;
9b3e0f4d
QT		 5248 case QLA_EVT_RELOGIN:
5249 qla2x00_relogin(vha);
5250 break;
726b8548
QT		 5251 case QLA_EVT_NEW_SESS:
5252 qla24xx_create_new_sess(vha, e);
5253 break;
5254 case QLA_EVT_GPDB:
5255 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5256 e->u.fcport.opt);
5257 break;
a5d42f4c
DG		 5258 case QLA_EVT_PRLI:
5259 qla24xx_async_prli(vha, e->u.fcport.fcport);
5260 break;
726b8548
QT		 5261 case QLA_EVT_GPSC:
5262 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5263 break;
726b8548
QT		 5264 case QLA_EVT_GNL:
5265 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5266 break;
5267 case QLA_EVT_NACK:
5268 qla24xx_do_nack_work(vha, e);
5269 break;
11aea16a 5270 case QLA_EVT_ASYNC_PRLO:
80676d05 5271 rc = qla2x00_async_prlo(vha, e->u.logio.fcport);
11aea16a
QT		 5272 break;
5273 case QLA_EVT_ASYNC_PRLO_DONE:
5274 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5275 e->u.logio.data);
5276 break;
a4239945 5277 case QLA_EVT_GPNFT:
33b28357
QT		 5278 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5279 e->u.gpnft.sp);
a4239945
QT		 5280 break;
5281 case QLA_EVT_GPNFT_DONE:
5282 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5283 break;
5284 case QLA_EVT_GNNFT_DONE:
5285 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5286 break;
5287 case QLA_EVT_GNNID:
5288 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5289 break;
5290 case QLA_EVT_GFPNID:
5291 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5292 break;
e374f9f5
QT		 5293 case QLA_EVT_SP_RETRY:
5294 qla_sp_retry(vha, e);
cc28e0ac
QT		 5295 break;
5296 case QLA_EVT_IIDMA:
5297 qla_do_iidma_work(vha, e->u.fcport.fcport);
5298 break;
8777e431
QT		 5299 case QLA_EVT_ELS_PLOGI:
5300 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5301 e->u.fcport.fcport, false);
5302 break;
0971de7f 5303 }
80676d05
QT		 5304
5305 if (rc == EAGAIN) {
5306 /* put 'work' at head of 'vha->work_list' */
5307 spin_lock_irqsave(&vha->work_lock, flags);
5308 list_splice(&work, &vha->work_list);
5309 spin_unlock_irqrestore(&vha->work_lock, flags);
5310 break;
5311 }
5312 list_del_init(&e->list);
0971de7f
AV		 5313 if (e->flags & QLA_EVT_FLAG_FREE)
5314 kfree(e);
feafb7b1
AE		 5315
5316 /* For each work completed decrement vha ref count */
5317 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 5318 }
e315cd28 5319}
f999f4c1 5320
9b3e0f4d
QT		 5321int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5322{
5323 struct qla_work_evt *e;
5324
5325 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5326
5327 if (!e) {
5328 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5329 return QLA_FUNCTION_FAILED;
5330 }
5331
5332 return qla2x00_post_work(vha, e);
5333}
5334
e315cd28
AC		 5335/* Relogins all the fcports of a vport
5336 * Context: dpc thread
5337 */
5338void qla2x00_relogin(struct scsi_qla_host *vha)
5339{
5340 fc_port_t *fcport;
23dd98a6 5341 int status, relogin_needed = 0;
726b8548 5342 struct event_arg ea;
e315cd28
AC		 5343
5344 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9cd883f0
QT		 5345 /*
5346 * If the port is not ONLINE then try to login
5347 * to it if we haven't run out of retries.
5348 */
5ff1d584 5349 if (atomic_read(&fcport->state) != FCS_ONLINE &&
23dd98a6
QT		 5350 fcport->login_retry) {
5351 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5352 fcport->disc_state == DSC_LOGIN_COMPLETE)
5353 continue;
e315cd28 5354
23dd98a6
QT		 5355 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5356 fcport->disc_state == DSC_DELETE_PEND) {
5357 relogin_needed = 1;
5358 } else {
5359 if (vha->hw->current_topology != ISP_CFG_NL) {
5360 memset(&ea, 0, sizeof(ea));
5361 ea.event = FCME_RELOGIN;
5362 ea.fcport = fcport;
5363 qla2x00_fcport_event_handler(vha, &ea);
5364 } else if (vha->hw->current_topology ==
5365 ISP_CFG_NL) {
5366 fcport->login_retry--;
5367 status =
5368 qla2x00_local_device_login(vha,
5369 fcport);
5370 if (status == QLA_SUCCESS) {
5371 fcport->old_loop_id =
5372 fcport->loop_id;
5373 ql_dbg(ql_dbg_disc, vha, 0x2003,
5374 "Port login OK: logged in ID 0x%x.\n",
5375 fcport->loop_id);
5376 qla2x00_update_fcport
5377 (vha, fcport);
5378 } else if (status == 1) {
5379 set_bit(RELOGIN_NEEDED,
5380 &vha->dpc_flags);
5381 /* retry the login again */
5382 ql_dbg(ql_dbg_disc, vha, 0x2007,
5383 "Retrying %d login again loop_id 0x%x.\n",
5384 fcport->login_retry,
5385 fcport->loop_id);
5386 } else {
5387 fcport->login_retry = 0;
5388 }
e315cd28 5389
23dd98a6
QT		 5390 if (fcport->login_retry == 0 &&
5391 status != QLA_SUCCESS)
5392 qla2x00_clear_loop_id(fcport);
5393 }
e315cd28 5394 }
e315cd28
AC		 5395 }
5396 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5397 break;
0971de7f 5398 }
9b3e0f4d 5399
23dd98a6
QT		 5400 if (relogin_needed)
5401 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5402
9b3e0f4d
QT		 5403 ql_dbg(ql_dbg_disc, vha, 0x400e,
5404 "Relogin end.\n");
0971de7f
AV		 5405}
5406
7d613ac6
SV		 5407/* Schedule work on any of the dpc-workqueues */
5408void
5409qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5410{
5411 struct qla_hw_data *ha = base_vha->hw;
5412
5413 switch (work_code) {
5414 case MBA_IDC_AEN: /* 0x8200 */
5415 if (ha->dpc_lp_wq)
5416 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5417 break;
5418
5419 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5420 if (!ha->flags.nic_core_reset_hdlr_active) {
5421 if (ha->dpc_hp_wq)
5422 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5423 } else
5424 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5425 "NIC Core reset is already active. Skip "
5426 "scheduling it again.\n");
5427 break;
5428 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5429 if (ha->dpc_hp_wq)
5430 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5431 break;
5432 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5433 if (ha->dpc_hp_wq)
5434 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5435 break;
5436 default:
5437 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 5438 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 5439 }
5440
5441 return;
5442}
5443
5444/* Work: Perform NIC Core Unrecoverable state handling */
5445void
5446qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5447{
5448 struct qla_hw_data *ha =
2ad1b67c 5449 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 5450 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5451 uint32_t dev_state = 0;
5452
5453 qla83xx_idc_lock(base_vha, 0);
5454 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5455 qla83xx_reset_ownership(base_vha);
5456 if (ha->flags.nic_core_reset_owner) {
5457 ha->flags.nic_core_reset_owner = 0;
5458 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5459 QLA8XXX_DEV_FAILED);
5460 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5461 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5462 }
5463 qla83xx_idc_unlock(base_vha, 0);
5464}
5465
5466/* Work: Execute IDC state handler */
5467void
5468qla83xx_idc_state_handler_work(struct work_struct *work)
5469{
5470 struct qla_hw_data *ha =
2ad1b67c 5471 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 5472 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5473 uint32_t dev_state = 0;
5474
5475 qla83xx_idc_lock(base_vha, 0);
5476 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5477 if (dev_state == QLA8XXX_DEV_FAILED ||
5478 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5479 qla83xx_idc_state_handler(base_vha);
5480 qla83xx_idc_unlock(base_vha, 0);
5481}
5482
fa492630 5483static int
7d613ac6
SV		 5484qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5485{
5486 int rval = QLA_SUCCESS;
5487 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5488 uint32_t heart_beat_counter1, heart_beat_counter2;
5489
5490 do {
5491 if (time_after(jiffies, heart_beat_wait)) {
5492 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5493 "Nic Core f/w is not alive.\n");
5494 rval = QLA_FUNCTION_FAILED;
5495 break;
5496 }
5497
5498 qla83xx_idc_lock(base_vha, 0);
5499 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5500 &heart_beat_counter1);
5501 qla83xx_idc_unlock(base_vha, 0);
5502 msleep(100);
5503 qla83xx_idc_lock(base_vha, 0);
5504 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5505 &heart_beat_counter2);
5506 qla83xx_idc_unlock(base_vha, 0);
5507 } while (heart_beat_counter1 == heart_beat_counter2);
5508
5509 return rval;
5510}
5511
5512/* Work: Perform NIC Core Reset handling */
5513void
5514qla83xx_nic_core_reset_work(struct work_struct *work)
5515{
5516 struct qla_hw_data *ha =
5517 container_of(work, struct qla_hw_data, nic_core_reset);
5518 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5519 uint32_t dev_state = 0;
5520
81178772
SK		 5521 if (IS_QLA2031(ha)) {
5522 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5523 ql_log(ql_log_warn, base_vha, 0xb081,
5524 "Failed to dump mctp\n");
5525 return;
5526 }
5527
7d613ac6
SV		 5528 if (!ha->flags.nic_core_reset_hdlr_active) {
5529 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5530 qla83xx_idc_lock(base_vha, 0);
5531 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5532 &dev_state);
5533 qla83xx_idc_unlock(base_vha, 0);
5534 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5535 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5536 "Nic Core f/w is alive.\n");
5537 return;
5538 }
5539 }
5540
5541 ha->flags.nic_core_reset_hdlr_active = 1;
5542 if (qla83xx_nic_core_reset(base_vha)) {
5543 /* NIC Core reset failed. */
5544 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5545 "NIC Core reset failed.\n");
5546 }
5547 ha->flags.nic_core_reset_hdlr_active = 0;
5548 }
5549}
5550
5551/* Work: Handle 8200 IDC aens */
5552void
5553qla83xx_service_idc_aen(struct work_struct *work)
5554{
5555 struct qla_hw_data *ha =
5556 container_of(work, struct qla_hw_data, idc_aen);
5557 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5558 uint32_t dev_state, idc_control;
5559
5560 qla83xx_idc_lock(base_vha, 0);
5561 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5562 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5563 qla83xx_idc_unlock(base_vha, 0);
5564 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5565 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5566 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5567 "Application requested NIC Core Reset.\n");
5568 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5569 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5570 QLA_SUCCESS) {
5571 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5572 "Other protocol driver requested NIC Core Reset.\n");
5573 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5574 }
5575 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5576 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5577 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5578 }
5579}
5580
5581static void
5582qla83xx_wait_logic(void)
5583{
5584 int i;
5585
5586 /* Yield CPU */
5587 if (!in_interrupt()) {
5588 /*
5589 * Wait about 200ms before retrying again.
5590 * This controls the number of retries for single
5591 * lock operation.
5592 */
5593 msleep(100);
5594 schedule();
5595 } else {
5596 for (i = 0; i < 20; i++)
5597 cpu_relax(); /* This a nop instr on i386 */
5598 }
5599}
5600
fa492630 5601static int
7d613ac6
SV		 5602qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5603{
5604 int rval;
5605 uint32_t data;
5606 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5607 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5608 struct qla_hw_data *ha = base_vha->hw;
bd432bb5 5609
6c315553
SK		 5610 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5611 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5612
5613 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5614 if (rval)
5615 return rval;
5616
5617 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5618 return QLA_SUCCESS;
5619 } else {
5620 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5621 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5622 data);
5623 if (rval)
5624 return rval;
5625
5626 msleep(200);
5627
5628 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5629 &data);
5630 if (rval)
5631 return rval;
5632
5633 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5634 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5635 ~(idc_lck_rcvry_stage_mask));
5636 rval = qla83xx_wr_reg(base_vha,
5637 QLA83XX_IDC_LOCK_RECOVERY, data);
5638 if (rval)
5639 return rval;
5640
5641 /* Forcefully perform IDC UnLock */
5642 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5643 &data);
5644 if (rval)
5645 return rval;
5646 /* Clear lock-id by setting 0xff */
5647 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5648 0xff);
5649 if (rval)
5650 return rval;
5651 /* Clear lock-recovery by setting 0x0 */
5652 rval = qla83xx_wr_reg(base_vha,
5653 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5654 if (rval)
5655 return rval;
5656 } else
5657 return QLA_SUCCESS;
5658 }
5659
5660 return rval;
5661}
5662
fa492630 5663static int
7d613ac6
SV		 5664qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5665{
5666 int rval = QLA_SUCCESS;
5667 uint32_t o_drv_lockid, n_drv_lockid;
5668 unsigned long lock_recovery_timeout;
5669
5670 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5671retry_lockid:
5672 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5673 if (rval)
5674 goto exit;
5675
5676 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5677 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5678 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5679 return QLA_SUCCESS;
5680 else
5681 return QLA_FUNCTION_FAILED;
5682 }
5683
5684 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5685 if (rval)
5686 goto exit;
5687
5688 if (o_drv_lockid == n_drv_lockid) {
5689 qla83xx_wait_logic();
5690 goto retry_lockid;
5691 } else
5692 return QLA_SUCCESS;
5693
5694exit:
5695 return rval;
5696}
5697
5698void
5699qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5700{
5701 uint16_t options = (requester_id << 15) | BIT_6;
5702 uint32_t data;
6c315553 5703 uint32_t lock_owner;
7d613ac6
SV		 5704 struct qla_hw_data *ha = base_vha->hw;
5705
5706 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5707retry_lock:
5708 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5709 == QLA_SUCCESS) {
5710 if (data) {
5711 /* Setting lock-id to our function-number */
5712 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5713 ha->portnum);
5714 } else {
6c315553
SK		 5715 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5716 &lock_owner);
7d613ac6 5717 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5718 "Failed to acquire IDC lock, acquired by %d, "
5719 "retrying...\n", lock_owner);
7d613ac6
SV		 5720
5721 /* Retry/Perform IDC-Lock recovery */
5722 if (qla83xx_idc_lock_recovery(base_vha)
5723 == QLA_SUCCESS) {
5724 qla83xx_wait_logic();
5725 goto retry_lock;
5726 } else
5727 ql_log(ql_log_warn, base_vha, 0xb075,
5728 "IDC Lock recovery FAILED.\n");
5729 }
5730
5731 }
5732
5733 return;
5734
5735 /* XXX: IDC-lock implementation using access-control mbx */
5736retry_lock2:
5737 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5738 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5739 "Failed to acquire IDC lock. retrying...\n");
5740 /* Retry/Perform IDC-Lock recovery */
5741 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5742 qla83xx_wait_logic();
5743 goto retry_lock2;
5744 } else
5745 ql_log(ql_log_warn, base_vha, 0xb076,
5746 "IDC Lock recovery FAILED.\n");
5747 }
5748
5749 return;
5750}
5751
5752void
5753qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5754{
5897cb2f
BVA		 5755#if 0
5756 uint16_t options = (requester_id << 15) | BIT_7;
5757#endif
5758 uint16_t retry;
7d613ac6
SV		 5759 uint32_t data;
5760 struct qla_hw_data *ha = base_vha->hw;
5761
5762 /* IDC-unlock implementation using driver-unlock/lock-id
5763 * remote registers
5764 */
5765 retry = 0;
5766retry_unlock:
5767 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5768 == QLA_SUCCESS) {
5769 if (data == ha->portnum) {
5770 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5771 /* Clearing lock-id by setting 0xff */
5772 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5773 } else if (retry < 10) {
5774 /* SV: XXX: IDC unlock retrying needed here? */
5775
5776 /* Retry for IDC-unlock */
5777 qla83xx_wait_logic();
5778 retry++;
5779 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5780 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5781 goto retry_unlock;
5782 }
5783 } else if (retry < 10) {
5784 /* Retry for IDC-unlock */
5785 qla83xx_wait_logic();
5786 retry++;
5787 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5788 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5789 goto retry_unlock;
5790 }
5791
5792 return;
5793
5897cb2f 5794#if 0
7d613ac6
SV		 5795 /* XXX: IDC-unlock implementation using access-control mbx */
5796 retry = 0;
5797retry_unlock2:
5798 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5799 if (retry < 10) {
5800 /* Retry for IDC-unlock */
5801 qla83xx_wait_logic();
5802 retry++;
5803 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5804 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5805 goto retry_unlock2;
5806 }
5807 }
5808
5809 return;
5897cb2f 5810#endif
7d613ac6
SV		 5811}
5812
5813int
5814__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5815{
5816 int rval = QLA_SUCCESS;
5817 struct qla_hw_data *ha = vha->hw;
5818 uint32_t drv_presence;
5819
5820 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5821 if (rval == QLA_SUCCESS) {
5822 drv_presence |= (1 << ha->portnum);
5823 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5824 drv_presence);
5825 }
5826
5827 return rval;
5828}
5829
5830int
5831qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5832{
5833 int rval = QLA_SUCCESS;
5834
5835 qla83xx_idc_lock(vha, 0);
5836 rval = __qla83xx_set_drv_presence(vha);
5837 qla83xx_idc_unlock(vha, 0);
5838
5839 return rval;
5840}
5841
5842int
5843__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5844{
5845 int rval = QLA_SUCCESS;
5846 struct qla_hw_data *ha = vha->hw;
5847 uint32_t drv_presence;
5848
5849 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5850 if (rval == QLA_SUCCESS) {
5851 drv_presence &= ~(1 << ha->portnum);
5852 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5853 drv_presence);
5854 }
5855
5856 return rval;
5857}
5858
5859int
5860qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5861{
5862 int rval = QLA_SUCCESS;
5863
5864 qla83xx_idc_lock(vha, 0);
5865 rval = __qla83xx_clear_drv_presence(vha);
5866 qla83xx_idc_unlock(vha, 0);
5867
5868 return rval;
5869}
5870
fa492630 5871static void
7d613ac6
SV		 5872qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5873{
5874 struct qla_hw_data *ha = vha->hw;
5875 uint32_t drv_ack, drv_presence;
5876 unsigned long ack_timeout;
5877
5878 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5879 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5880 while (1) {
5881 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5882 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5883 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5884 break;
5885
5886 if (time_after_eq(jiffies, ack_timeout)) {
5887 ql_log(ql_log_warn, vha, 0xb067,
5888 "RESET ACK TIMEOUT! drv_presence=0x%x "
5889 "drv_ack=0x%x\n", drv_presence, drv_ack);
5890 /*
5891 * The function(s) which did not ack in time are forced
5892 * to withdraw any further participation in the IDC
5893 * reset.
5894 */
5895 if (drv_ack != drv_presence)
5896 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5897 drv_ack);
5898 break;
5899 }
5900
5901 qla83xx_idc_unlock(vha, 0);
5902 msleep(1000);
5903 qla83xx_idc_lock(vha, 0);
5904 }
5905
5906 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5907 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5908}
5909
fa492630 5910static int
7d613ac6
SV		 5911qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5912{
5913 int rval = QLA_SUCCESS;
5914 uint32_t idc_control;
5915
5916 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5917 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5918
5919 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5920 __qla83xx_get_idc_control(vha, &idc_control);
5921 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5922 __qla83xx_set_idc_control(vha, 0);
5923
5924 qla83xx_idc_unlock(vha, 0);
5925 rval = qla83xx_restart_nic_firmware(vha);
5926 qla83xx_idc_lock(vha, 0);
5927
5928 if (rval != QLA_SUCCESS) {
5929 ql_log(ql_log_fatal, vha, 0xb06a,
5930 "Failed to restart NIC f/w.\n");
5931 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5932 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5933 } else {
5934 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5935 "Success in restarting nic f/w.\n");
5936 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5937 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5938 }
5939
5940 return rval;
5941}
5942
5943/* Assumes idc_lock always held on entry */
5944int
5945qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5946{
5947 struct qla_hw_data *ha = base_vha->hw;
5948 int rval = QLA_SUCCESS;
5949 unsigned long dev_init_timeout;
5950 uint32_t dev_state;
5951
5952 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5953 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5954
5955 while (1) {
5956
5957 if (time_after_eq(jiffies, dev_init_timeout)) {
5958 ql_log(ql_log_warn, base_vha, 0xb06e,
5959 "Initialization TIMEOUT!\n");
5960 /* Init timeout. Disable further NIC Core
5961 * communication.
5962 */
5963 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5964 QLA8XXX_DEV_FAILED);
5965 ql_log(ql_log_info, base_vha, 0xb06f,
5966 "HW State: FAILED.\n");
5967 }
5968
5969 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5970 switch (dev_state) {
5971 case QLA8XXX_DEV_READY:
5972 if (ha->flags.nic_core_reset_owner)
5973 qla83xx_idc_audit(base_vha,
5974 IDC_AUDIT_COMPLETION);
5975 ha->flags.nic_core_reset_owner = 0;
5976 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5977 "Reset_owner reset by 0x%x.\n",
5978 ha->portnum);
5979 goto exit;
5980 case QLA8XXX_DEV_COLD:
5981 if (ha->flags.nic_core_reset_owner)
5982 rval = qla83xx_device_bootstrap(base_vha);
5983 else {
5984 /* Wait for AEN to change device-state */
5985 qla83xx_idc_unlock(base_vha, 0);
5986 msleep(1000);
5987 qla83xx_idc_lock(base_vha, 0);
5988 }
5989 break;
5990 case QLA8XXX_DEV_INITIALIZING:
5991 /* Wait for AEN to change device-state */
5992 qla83xx_idc_unlock(base_vha, 0);
5993 msleep(1000);
5994 qla83xx_idc_lock(base_vha, 0);
5995 break;
5996 case QLA8XXX_DEV_NEED_RESET:
5997 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5998 qla83xx_need_reset_handler(base_vha);
5999 else {
6000 /* Wait for AEN to change device-state */
6001 qla83xx_idc_unlock(base_vha, 0);
6002 msleep(1000);
6003 qla83xx_idc_lock(base_vha, 0);
6004 }
6005 /* reset timeout value after need reset handler */
6006 dev_init_timeout = jiffies +
6007 (ha->fcoe_dev_init_timeout * HZ);
6008 break;
6009 case QLA8XXX_DEV_NEED_QUIESCENT:
6010 /* XXX: DEBUG for now */
6011 qla83xx_idc_unlock(base_vha, 0);
6012 msleep(1000);
6013 qla83xx_idc_lock(base_vha, 0);
6014 break;
6015 case QLA8XXX_DEV_QUIESCENT:
6016 /* XXX: DEBUG for now */
6017 if (ha->flags.quiesce_owner)
6018 goto exit;
6019
6020 qla83xx_idc_unlock(base_vha, 0);
6021 msleep(1000);
6022 qla83xx_idc_lock(base_vha, 0);
6023 dev_init_timeout = jiffies +
6024 (ha->fcoe_dev_init_timeout * HZ);
6025 break;
6026 case QLA8XXX_DEV_FAILED:
6027 if (ha->flags.nic_core_reset_owner)
6028 qla83xx_idc_audit(base_vha,
6029 IDC_AUDIT_COMPLETION);
6030 ha->flags.nic_core_reset_owner = 0;
6031 __qla83xx_clear_drv_presence(base_vha);
6032 qla83xx_idc_unlock(base_vha, 0);
6033 qla8xxx_dev_failed_handler(base_vha);
6034 rval = QLA_FUNCTION_FAILED;
6035 qla83xx_idc_lock(base_vha, 0);
6036 goto exit;
6037 case QLA8XXX_BAD_VALUE:
6038 qla83xx_idc_unlock(base_vha, 0);
6039 msleep(1000);
6040 qla83xx_idc_lock(base_vha, 0);
6041 break;
6042 default:
6043 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 6044 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 6045 qla83xx_idc_unlock(base_vha, 0);
6046 qla8xxx_dev_failed_handler(base_vha);
6047 rval = QLA_FUNCTION_FAILED;
6048 qla83xx_idc_lock(base_vha, 0);
6049 goto exit;
6050 }
6051 }
6052
6053exit:
6054 return rval;
6055}
6056
f3ddac19
CD		 6057void
6058qla2x00_disable_board_on_pci_error(struct work_struct *work)
6059{
6060 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
6061 board_disable);
6062 struct pci_dev *pdev = ha->pdev;
6063 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6064
726b8548
QT		 6065 /*
6066 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 6067 * where it was set first.
6068 */
6069 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6070 return;
6071
f3ddac19
CD		 6072 ql_log(ql_log_warn, base_vha, 0x015b,
6073 "Disabling adapter.\n");
6074
efdb5760
SC		 6075 if (!atomic_read(&pdev->enable_cnt)) {
6076 ql_log(ql_log_info, base_vha, 0xfffc,
6077 "PCI device disabled, no action req for PCI error=%lx\n",
6078 base_vha->pci_flags);
6079 return;
6080 }
6081
726b8548
QT		 6082 qla2x00_wait_for_sess_deletion(base_vha);
6083
f3ddac19
CD		 6084 set_bit(UNLOADING, &base_vha->dpc_flags);
6085
6086 qla2x00_delete_all_vps(ha, base_vha);
6087
6088 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6089
6090 qla2x00_dfs_remove(base_vha);
6091
6092 qla84xx_put_chip(base_vha);
6093
6094 if (base_vha->timer_active)
6095 qla2x00_stop_timer(base_vha);
6096
6097 base_vha->flags.online = 0;
6098
6099 qla2x00_destroy_deferred_work(ha);
6100
6101 /*
6102 * Do not try to stop beacon blink as it will issue a mailbox
6103 * command.
6104 */
6105 qla2x00_free_sysfs_attr(base_vha, false);
6106
6107 fc_remove_host(base_vha->host);
6108
6109 scsi_remove_host(base_vha->host);
6110
6111 base_vha->flags.init_done = 0;
6112 qla25xx_delete_queues(base_vha);
f3ddac19 6113 qla2x00_free_fcports(base_vha);
093df737 6114 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 6115 qla2x00_mem_free(ha);
6116 qla82xx_md_free(base_vha);
6117 qla2x00_free_queues(ha);
6118
f3ddac19
CD		 6119 qla2x00_unmap_iobases(ha);
6120
6121 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 6122 pci_disable_pcie_error_reporting(pdev);
6123 pci_disable_device(pdev);
f3ddac19 6124
beb9e315
JL		 6125 /*
6126 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
6127 */
f3ddac19
CD		 6128}
6129
1da177e4
LT		 6130/**************************************************************************
6131* qla2x00_do_dpc
6132* This kernel thread is a task that is schedule by the interrupt handler
6133* to perform the background processing for interrupts.
6134*
6135* Notes:
6136* This task always run in the context of a kernel thread. It
6137* is kick-off by the driver's detect code and starts up
6138* up one per adapter. It immediately goes to sleep and waits for
6139* some fibre event. When either the interrupt handler or
6140* the timer routine detects a event it will one of the task
6141* bits then wake us up.
6142**************************************************************************/
6143static int
6144qla2x00_do_dpc(void *data)
6145{
e315cd28
AC		 6146 scsi_qla_host_t *base_vha;
6147 struct qla_hw_data *ha;
d7459527
MH		 6148 uint32_t online;
6149 struct qla_qpair *qpair;
1da177e4 6150
e315cd28
AC		 6151 ha = (struct qla_hw_data *)data;
6152 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 6153
8698a745 6154 set_user_nice(current, MIN_NICE);
1da177e4 6155
563585ec 6156 set_current_state(TASK_INTERRUPTIBLE);
39a11240 6157 while (!kthread_should_stop()) {
7c3df132
SK		 6158 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
6159 "DPC handler sleeping.\n");
1da177e4 6160
39a11240 6161 schedule();
1da177e4 6162
c142caf0
AV		 6163 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
6164 goto end_loop;
1da177e4 6165
85880801 6166 if (ha->flags.eeh_busy) {
7c3df132
SK		 6167 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
6168 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 6169 goto end_loop;
85880801
AV		 6170 }
6171
1da177e4
LT		 6172 ha->dpc_active = 1;
6173
5f28d2d7
SK		 6174 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
6175 "DPC handler waking up, dpc_flags=0x%lx.\n",
6176 base_vha->dpc_flags);
1da177e4 6177
a29b3dd7
JC		 6178 if (test_bit(UNLOADING, &base_vha->dpc_flags))
6179 break;
6180
7ec0effd
AD		 6181 if (IS_P3P_TYPE(ha)) {
6182 if (IS_QLA8044(ha)) {
6183 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6184 &base_vha->dpc_flags)) {
6185 qla8044_idc_lock(ha);
6186 qla8044_wr_direct(base_vha,
6187 QLA8044_CRB_DEV_STATE_INDEX,
6188 QLA8XXX_DEV_FAILED);
6189 qla8044_idc_unlock(ha);
6190 ql_log(ql_log_info, base_vha, 0x4004,
6191 "HW State: FAILED.\n");
6192 qla8044_device_state_handler(base_vha);
6193 continue;
6194 }
6195
6196 } else {
6197 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6198 &base_vha->dpc_flags)) {
6199 qla82xx_idc_lock(ha);
6200 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6201 QLA8XXX_DEV_FAILED);
6202 qla82xx_idc_unlock(ha);
6203 ql_log(ql_log_info, base_vha, 0x0151,
6204 "HW State: FAILED.\n");
6205 qla82xx_device_state_handler(base_vha);
6206 continue;
6207 }
a9083016
GM		 6208 }
6209
6210 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6211 &base_vha->dpc_flags)) {
6212
7c3df132
SK		 6213 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6214 "FCoE context reset scheduled.\n");
a9083016
GM		 6215 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6216 &base_vha->dpc_flags))) {
6217 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6218 /* FCoE-ctx reset failed.
6219 * Escalate to chip-reset
6220 */
6221 set_bit(ISP_ABORT_NEEDED,
6222 &base_vha->dpc_flags);
6223 }
6224 clear_bit(ABORT_ISP_ACTIVE,
6225 &base_vha->dpc_flags);
6226 }
6227
7c3df132
SK		 6228 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6229 "FCoE context reset end.\n");
a9083016 6230 }
8ae6d9c7
GM		 6231 } else if (IS_QLAFX00(ha)) {
6232 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6233 &base_vha->dpc_flags)) {
6234 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6235 "Firmware Reset Recovery\n");
6236 if (qlafx00_reset_initialize(base_vha)) {
6237 /* Failed. Abort isp later. */
6238 if (!test_bit(UNLOADING,
f92f82d6 6239 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 6240 set_bit(ISP_UNRECOVERABLE,
6241 &base_vha->dpc_flags);
6242 ql_dbg(ql_dbg_dpc, base_vha,
6243 0x4021,
6244 "Reset Recovery Failed\n");
f92f82d6 6245 }
8ae6d9c7
GM		 6246 }
6247 }
6248
6249 if (test_and_clear_bit(FX00_TARGET_SCAN,
6250 &base_vha->dpc_flags)) {
6251 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6252 "ISPFx00 Target Scan scheduled\n");
6253 if (qlafx00_rescan_isp(base_vha)) {
6254 if (!test_bit(UNLOADING,
6255 &base_vha->dpc_flags))
6256 set_bit(ISP_UNRECOVERABLE,
6257 &base_vha->dpc_flags);
6258 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6259 "ISPFx00 Target Scan Failed\n");
6260 }
6261 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6262 "ISPFx00 Target Scan End\n");
6263 }
e8f5e95d
AB		 6264 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6265 &base_vha->dpc_flags)) {
6266 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6267 "ISPFx00 Host Info resend scheduled\n");
6268 qlafx00_fx_disc(base_vha,
6269 &base_vha->hw->mr.fcport,
6270 FXDISC_REG_HOST_INFO);
6271 }
a9083016
GM		 6272 }
6273
e4e3a2ce
QT		 6274 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6275 &base_vha->dpc_flags) &&
6276 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6277 qla24xx_detect_sfp(base_vha);
6278
6279 if (ha->flags.detected_lr_sfp !=
6280 ha->flags.using_lr_setting)
6281 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6282 }
6283
b08abbd9
QT		 6284 if (test_and_clear_bit
6285 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6286 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
93eca613
QT		 6287 bool do_reset = true;
6288
0645cb83 6289 switch (base_vha->qlini_mode) {
93eca613
QT		 6290 case QLA2XXX_INI_MODE_ENABLED:
6291 break;
6292 case QLA2XXX_INI_MODE_DISABLED:
0645cb83
QT		 6293 if (!qla_tgt_mode_enabled(base_vha) &&
6294 !ha->flags.fw_started)
93eca613
QT		 6295 do_reset = false;
6296 break;
6297 case QLA2XXX_INI_MODE_DUAL:
0645cb83
QT		 6298 if (!qla_dual_mode_enabled(base_vha) &&
6299 !ha->flags.fw_started)
93eca613
QT		 6300 do_reset = false;
6301 break;
6302 default:
6303 break;
6304 }
1da177e4 6305
93eca613 6306 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 6307 &base_vha->dpc_flags))) {
93eca613
QT		 6308 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6309 "ISP abort scheduled.\n");
a9083016 6310 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 6311 /* failed. retry later */
6312 set_bit(ISP_ABORT_NEEDED,
e315cd28 6313 &base_vha->dpc_flags);
99363ef8 6314 }
e315cd28
AC		 6315 clear_bit(ABORT_ISP_ACTIVE,
6316 &base_vha->dpc_flags);
93eca613
QT		 6317 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6318 "ISP abort end.\n");
99363ef8 6319 }
1da177e4
LT		 6320 }
6321
a394aac8
DJ		 6322 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6323 &base_vha->dpc_flags)) {
e315cd28 6324 qla2x00_update_fcports(base_vha);
c9c5ced9 6325 }
d97994dc 6326
8ae6d9c7
GM		 6327 if (IS_QLAFX00(ha))
6328 goto loop_resync_check;
6329
579d12b5 6330 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 6331 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6332 "Quiescence mode scheduled.\n");
7ec0effd
AD		 6333 if (IS_P3P_TYPE(ha)) {
6334 if (IS_QLA82XX(ha))
6335 qla82xx_device_state_handler(base_vha);
6336 if (IS_QLA8044(ha))
6337 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 6338 clear_bit(ISP_QUIESCE_NEEDED,
6339 &base_vha->dpc_flags);
6340 if (!ha->flags.quiesce_owner) {
6341 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 6342 if (IS_QLA82XX(ha)) {
6343 qla82xx_idc_lock(ha);
6344 qla82xx_clear_qsnt_ready(
6345 base_vha);
6346 qla82xx_idc_unlock(ha);
6347 } else if (IS_QLA8044(ha)) {
6348 qla8044_idc_lock(ha);
6349 qla8044_clear_qsnt_ready(
6350 base_vha);
6351 qla8044_idc_unlock(ha);
6352 }
8fcd6b8b
CD		 6353 }
6354 } else {
6355 clear_bit(ISP_QUIESCE_NEEDED,
6356 &base_vha->dpc_flags);
6357 qla2x00_quiesce_io(base_vha);
579d12b5 6358 }
7c3df132
SK		 6359 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6360 "Quiescence mode end.\n");
579d12b5
SK		 6361 }
6362
e315cd28 6363 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 6364 &base_vha->dpc_flags) &&
e315cd28 6365 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 6366
7c3df132
SK		 6367 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6368 "Reset marker scheduled.\n");
e315cd28
AC		 6369 qla2x00_rst_aen(base_vha);
6370 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 6371 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6372 "Reset marker end.\n");
1da177e4
LT		 6373 }
6374
6375 /* Retry each device up to login retry count */
4005a995 6376 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
e315cd28
AC		 6377 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6378 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 6379
4005a995
QT		 6380 if (!base_vha->relogin_jif ||
6381 time_after_eq(jiffies, base_vha->relogin_jif)) {
6382 base_vha->relogin_jif = jiffies + HZ;
6383 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6384
9b3e0f4d 6385 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
4005a995 6386 "Relogin scheduled.\n");
9b3e0f4d 6387 qla24xx_post_relogin_work(base_vha);
4005a995 6388 }
1da177e4 6389 }
8ae6d9c7 6390loop_resync_check:
e315cd28 6391 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 6392 &base_vha->dpc_flags)) {
1da177e4 6393
7c3df132
SK		 6394 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6395 "Loop resync scheduled.\n");
1da177e4
LT		 6396
6397 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 6398 &base_vha->dpc_flags))) {
1da177e4 6399
52c82823 6400 qla2x00_loop_resync(base_vha);
1da177e4 6401
e315cd28
AC		 6402 clear_bit(LOOP_RESYNC_ACTIVE,
6403 &base_vha->dpc_flags);
1da177e4
LT		 6404 }
6405
7c3df132
SK		 6406 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6407 "Loop resync end.\n");
1da177e4
LT		 6408 }
6409
8ae6d9c7
GM		 6410 if (IS_QLAFX00(ha))
6411 goto intr_on_check;
6412
e315cd28
AC		 6413 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6414 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6415 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6416 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 6417 }
6418
8ae6d9c7 6419intr_on_check:
1da177e4 6420 if (!ha->interrupts_on)
fd34f556 6421 ha->isp_ops->enable_intrs(ha);
1da177e4 6422
e315cd28 6423 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 6424 &base_vha->dpc_flags)) {
6425 if (ha->beacon_blink_led == 1)
6426 ha->isp_ops->beacon_blink(base_vha);
6427 }
f6df144c 6428
d7459527
MH		 6429 /* qpair online check */
6430 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6431 &base_vha->dpc_flags)) {
6432 if (ha->flags.eeh_busy ||
6433 ha->flags.pci_channel_io_perm_failure)
6434 online = 0;
6435 else
6436 online = 1;
6437
6438 mutex_lock(&ha->mq_lock);
6439 list_for_each_entry(qpair, &base_vha->qp_list,
6440 qp_list_elem)
6441 qpair->online = online;
6442 mutex_unlock(&ha->mq_lock);
6443 }
6444
8b4673ba
QT		 6445 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6446 &base_vha->dpc_flags)) {
deeae7a6
DG		 6447 ql_log(ql_log_info, base_vha, 0xffffff,
6448 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6449 ha->nvme_last_rptd_aen);
8b4673ba
QT		 6450 if (qla27xx_set_zio_threshold(base_vha,
6451 ha->nvme_last_rptd_aen)) {
deeae7a6 6452 ql_log(ql_log_info, base_vha, 0xffffff,
8b4673ba
QT		 6453 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6454 ha->nvme_last_rptd_aen);
deeae7a6
DG		 6455 }
6456 }
6457
8b4673ba
QT		 6458 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6459 &base_vha->dpc_flags)) {
6460 ql_log(ql_log_info, base_vha, 0xffffff,
6461 "SET ZIO Activity exchange threshold to %d.\n",
6462 ha->last_zio_threshold);
6463 qla27xx_set_zio_threshold(base_vha,
6464 ha->last_zio_threshold);
6465 }
6466
8ae6d9c7
GM		 6467 if (!IS_QLAFX00(ha))
6468 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 6469
48acad09
QT		 6470 if (test_and_clear_bit(N2N_LINK_RESET,
6471 &base_vha->dpc_flags)) {
6472 qla2x00_lip_reset(base_vha);
6473 }
6474
1da177e4 6475 ha->dpc_active = 0;
c142caf0 6476end_loop:
563585ec 6477 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 6478 } /* End of while(1) */
563585ec 6479 __set_current_state(TASK_RUNNING);
1da177e4 6480
7c3df132
SK		 6481 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6482 "DPC handler exiting.\n");
1da177e4
LT		 6483
6484 /*
6485 * Make sure that nobody tries to wake us up again.
6486 */
1da177e4
LT		 6487 ha->dpc_active = 0;
6488
ac280b67
AV		 6489 /* Cleanup any residual CTX SRBs. */
6490 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6491
39a11240
CH		 6492 return 0;
6493}
6494
6495void
e315cd28 6496qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 6497{
e315cd28 6498 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 6499 struct task_struct *t = ha->dpc_thread;
6500
e315cd28 6501 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 6502 wake_up_process(t);
1da177e4
LT		 6503}
6504
1da177e4
LT		 6505/*
6506* qla2x00_rst_aen
6507* Processes asynchronous reset.
6508*
6509* Input:
6510* ha = adapter block pointer.
6511*/
6512static void
e315cd28 6513qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 6514{
e315cd28
AC		 6515 if (vha->flags.online && !vha->flags.reset_active &&
6516 !atomic_read(&vha->loop_down_timer) &&
6517 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 6518 do {
e315cd28 6519 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6520
6521 /*
6522 * Issue marker command only when we are going to start
6523 * the I/O.
6524 */
e315cd28
AC		 6525 vha->marker_needed = 1;
6526 } while (!atomic_read(&vha->loop_down_timer) &&
6527 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 6528 }
6529}
6530
1da177e4
LT		 6531/**************************************************************************
6532* qla2x00_timer
6533*
6534* Description:
6535* One second timer
6536*
6537* Context: Interrupt
6538***************************************************************************/
2c3dfe3f 6539void
8e5f4ba0 6540qla2x00_timer(struct timer_list *t)
1da177e4 6541{
8e5f4ba0 6542 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 6543 unsigned long cpu_flags = 0;
1da177e4
LT		 6544 int start_dpc = 0;
6545 int index;
6546 srb_t *sp;
85880801 6547 uint16_t w;
e315cd28 6548 struct qla_hw_data *ha = vha->hw;
73208dfd 6549 struct req_que *req;
85880801 6550
a5b36321 6551 if (ha->flags.eeh_busy) {
7c3df132
SK		 6552 ql_dbg(ql_dbg_timer, vha, 0x6000,
6553 "EEH = %d, restarting timer.\n",
6554 ha->flags.eeh_busy);
a5b36321
LC		 6555 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6556 return;
6557 }
6558
f3ddac19
CD		 6559 /*
6560 * Hardware read to raise pending EEH errors during mailbox waits. If
6561 * the read returns -1 then disable the board.
6562 */
6563 if (!pci_channel_offline(ha->pdev)) {
85880801 6564 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6565 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6566 }
1da177e4 6567
cefcaba6 6568 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6569 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6570 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6571 start_dpc++;
7ec0effd
AD		 6572 if (IS_QLA82XX(ha))
6573 qla82xx_watchdog(vha);
6574 else if (IS_QLA8044(ha))
6575 qla8044_watchdog(vha);
579d12b5
SK		 6576 }
6577
8ae6d9c7
GM		 6578 if (!vha->vp_idx && IS_QLAFX00(ha))
6579 qlafx00_timer_routine(vha);
6580
1da177e4 6581 /* Loop down handler. */
e315cd28 6582 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6583 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6584 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6585 && vha->flags.online) {
1da177e4 6586
e315cd28
AC		 6587 if (atomic_read(&vha->loop_down_timer) ==
6588 vha->loop_down_abort_time) {
1da177e4 6589
7c3df132
SK		 6590 ql_log(ql_log_info, vha, 0x6008,
6591 "Loop down - aborting the queues before time expires.\n");
1da177e4 6592
e315cd28
AC		 6593 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6594 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6595
f08b7251
AV		 6596 /*
6597 * Schedule an ISP abort to return any FCP2-device
6598 * commands.
6599 */
2c3dfe3f 6600 /* NPIV - scan physical port only */
e315cd28 6601 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6602 spin_lock_irqsave(&ha->hardware_lock,
6603 cpu_flags);
73208dfd 6604 req = ha->req_q_map[0];
2c3dfe3f 6605 for (index = 1;
8d93f550 6606 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6607 index++) {
6608 fc_port_t *sfcp;
6609
e315cd28 6610 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6611 if (!sp)
6612 continue;
c5419e26
QT		 6613 if (sp->cmd_type != TYPE_SRB)
6614 continue;
9ba56b95 6615 if (sp->type != SRB_SCSI_CMD)
cf53b069 6616 continue;
2c3dfe3f 6617 sfcp = sp->fcport;
f08b7251 6618 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6619 continue;
bdf79621 6620
8f7daead
GM		 6621 if (IS_QLA82XX(ha))
6622 set_bit(FCOE_CTX_RESET_NEEDED,
6623 &vha->dpc_flags);
6624 else
6625 set_bit(ISP_ABORT_NEEDED,
e315cd28 6626 &vha->dpc_flags);
2c3dfe3f
SJ		 6627 break;
6628 }
6629 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6630 cpu_flags);
1da177e4 6631 }
1da177e4
LT		 6632 start_dpc++;
6633 }
6634
6635 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6636 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6637 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6638 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6639 "Loop down - aborting ISP.\n");
6640
8f7daead
GM		 6641 if (IS_QLA82XX(ha))
6642 set_bit(FCOE_CTX_RESET_NEEDED,
6643 &vha->dpc_flags);
6644 else
6645 set_bit(ISP_ABORT_NEEDED,
6646 &vha->dpc_flags);
1da177e4
LT		 6647 }
6648 }
7c3df132
SK		 6649 ql_dbg(ql_dbg_timer, vha, 0x600a,
6650 "Loop down - seconds remaining %d.\n",
6651 atomic_read(&vha->loop_down_timer));
1da177e4 6652 }
cefcaba6
SK		 6653 /* Check if beacon LED needs to be blinked for physical host only */
6654 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6655 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6656 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6657 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6658 start_dpc++;
6659 }
f6df144c
AV		 6660 }
6661
550bf57d 6662 /* Process any deferred work. */
9b3e0f4d
QT		 6663 if (!list_empty(&vha->work_list)) {
6664 unsigned long flags;
6665 bool q = false;
6666
6667 spin_lock_irqsave(&vha->work_lock, flags);
6668 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6669 q = true;
6670 spin_unlock_irqrestore(&vha->work_lock, flags);
6671 if (q)
6672 queue_work(vha->hw->wq, &vha->iocb_work);
6673 }
550bf57d 6674
7401bc18
DG		 6675 /*
6676 * FC-NVME
6677 * see if the active AEN count has changed from what was last reported.
6678 */
b2d1453a
GM		 6679 if (!vha->vp_idx &&
6680 (atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen) &&
6681 ha->zio_mode == QLA_ZIO_MODE_6 &&
6682 !ha->flags.host_shutting_down) {
7401bc18 6683 ql_log(ql_log_info, vha, 0x3002,
8b4673ba
QT		 6684 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6685 ha->nvme_last_rptd_aen);
deeae7a6 6686 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
8b4673ba
QT		 6687 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6688 start_dpc++;
6689 }
6690
6691 if (!vha->vp_idx &&
6692 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6693 (ha->zio_mode == QLA_ZIO_MODE_6) &&
ecc89f25 6694 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
8b4673ba
QT		 6695 ql_log(ql_log_info, vha, 0x3002,
6696 "Sched: Set ZIO exchange threshold to %d.\n",
6697 ha->last_zio_threshold);
6698 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
deeae7a6
DG		 6699 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6700 start_dpc++;
7401bc18
DG		 6701 }
6702
1da177e4 6703 /* Schedule the DPC routine if needed */
e315cd28
AC		 6704 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6705 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6706 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6707 start_dpc ||
e315cd28
AC		 6708 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6709 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6710 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6711 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6712 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6713 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6714 ql_dbg(ql_dbg_timer, vha, 0x600b,
6715 "isp_abort_needed=%d loop_resync_needed=%d "
6716 "fcport_update_needed=%d start_dpc=%d "
6717 "reset_marker_needed=%d",
6718 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6719 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6720 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6721 start_dpc,
6722 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6723 ql_dbg(ql_dbg_timer, vha, 0x600c,
6724 "beacon_blink_needed=%d isp_unrecoverable=%d "
6725 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6726 "relogin_needed=%d.\n",
7c3df132
SK		 6727 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6728 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6729 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6730 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6731 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6732 qla2xxx_wake_dpc(vha);
7c3df132 6733 }
1da177e4 6734
e315cd28 6735 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6736}
6737
5433383e
AV		 6738/* Firmware interface routines. */
6739
5433383e
AV		 6740#define FW_ISP21XX 0
6741#define FW_ISP22XX 1
6742#define FW_ISP2300 2
6743#define FW_ISP2322 3
48c02fde 6744#define FW_ISP24XX 4
c3a2f0df 6745#define FW_ISP25XX 5
3a03eb79 6746#define FW_ISP81XX 6
a9083016 6747#define FW_ISP82XX 7
6246b8a1
GM		 6748#define FW_ISP2031 8
6749#define FW_ISP8031 9
2c5bbbb2 6750#define FW_ISP27XX 10
ecc89f25 6751#define FW_ISP28XX 11
5433383e 6752
bb8ee499
AV		 6753#define FW_FILE_ISP21XX "ql2100_fw.bin"
6754#define FW_FILE_ISP22XX "ql2200_fw.bin"
6755#define FW_FILE_ISP2300 "ql2300_fw.bin"
6756#define FW_FILE_ISP2322 "ql2322_fw.bin"
6757#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6758#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6759#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6760#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6761#define FW_FILE_ISP2031 "ql2600_fw.bin"
6762#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6763#define FW_FILE_ISP27XX "ql2700_fw.bin"
ecc89f25 6764#define FW_FILE_ISP28XX "ql2800_fw.bin"
f73cb695 6765
bb8ee499 6766
e1e82b6f 6767static DEFINE_MUTEX(qla_fw_lock);
5433383e 6768
ecc89f25 6769static struct fw_blob qla_fw_blobs[] = {
bb8ee499
AV		 6770 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6771 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6772 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6773 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6774 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6775 { .name = FW_FILE_ISP25XX, },
3a03eb79 6776 { .name = FW_FILE_ISP81XX, },
a9083016 6777 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6778 { .name = FW_FILE_ISP2031, },
6779 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6780 { .name = FW_FILE_ISP27XX, },
ecc89f25
JC		 6781 { .name = FW_FILE_ISP28XX, },
6782 { .name = NULL, },
5433383e
AV		 6783};
6784
6785struct fw_blob *
e315cd28 6786qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6787{
e315cd28 6788 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6789 struct fw_blob *blob;
6790
5433383e
AV		 6791 if (IS_QLA2100(ha)) {
6792 blob = &qla_fw_blobs[FW_ISP21XX];
6793 } else if (IS_QLA2200(ha)) {
6794 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6795 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6796 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6797 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6798 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6799 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6800 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6801 } else if (IS_QLA25XX(ha)) {
6802 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6803 } else if (IS_QLA81XX(ha)) {
6804 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6805 } else if (IS_QLA82XX(ha)) {
6806 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6807 } else if (IS_QLA2031(ha)) {
6808 blob = &qla_fw_blobs[FW_ISP2031];
6809 } else if (IS_QLA8031(ha)) {
6810 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6811 } else if (IS_QLA27XX(ha)) {
6812 blob = &qla_fw_blobs[FW_ISP27XX];
ecc89f25
JC		 6813 } else if (IS_QLA28XX(ha)) {
6814 blob = &qla_fw_blobs[FW_ISP28XX];
8a655229
DC		 6815 } else {
6816 return NULL;
5433383e
AV		 6817 }
6818
ecc89f25
JC		 6819 if (!blob->name)
6820 return NULL;
6821
e1e82b6f 6822 mutex_lock(&qla_fw_lock);
5433383e
AV		 6823 if (blob->fw)
6824 goto out;
6825
6826 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6827 ql_log(ql_log_warn, vha, 0x0063,
6828 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6829 blob->fw = NULL;
6830 blob = NULL;
5433383e
AV		 6831 }
6832
6833out:
e1e82b6f 6834 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6835 return blob;
6836}
6837
6838static void
6839qla2x00_release_firmware(void)
6840{
ecc89f25 6841 struct fw_blob *blob;
5433383e 6842
e1e82b6f 6843 mutex_lock(&qla_fw_lock);
ecc89f25
JC		 6844 for (blob = qla_fw_blobs; blob->name; blob++)
6845 release_firmware(blob->fw);
e1e82b6f 6846 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6847}
6848
5386a4e6
QT		 6849static void qla_pci_error_cleanup(scsi_qla_host_t *vha)
6850{
6851 struct qla_hw_data *ha = vha->hw;
6852 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
6853 struct qla_qpair *qpair = NULL;
6854 struct scsi_qla_host *vp;
6855 fc_port_t *fcport;
6856 int i;
6857 unsigned long flags;
6858
6859 ha->chip_reset++;
6860
6861 ha->base_qpair->chip_reset = ha->chip_reset;
6862 for (i = 0; i < ha->max_qpairs; i++) {
6863 if (ha->queue_pair_map[i])
6864 ha->queue_pair_map[i]->chip_reset =
6865 ha->base_qpair->chip_reset;
6866 }
6867
6868 /* purge MBox commands */
6869 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6870 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6871 complete(&ha->mbx_intr_comp);
6872 }
6873
6874 i = 0;
6875
6876 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6877 atomic_read(&ha->num_pend_mbx_stage2) ||
6878 atomic_read(&ha->num_pend_mbx_stage1)) {
6879 msleep(20);
6880 i++;
6881 if (i > 50)
6882 break;
6883 }
6884
6885 ha->flags.purge_mbox = 0;
6886
6887 mutex_lock(&ha->mq_lock);
6888 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
6889 qpair->online = 0;
6890 mutex_unlock(&ha->mq_lock);
6891
6892 qla2x00_mark_all_devices_lost(vha, 0);
6893
6894 spin_lock_irqsave(&ha->vport_slock, flags);
6895 list_for_each_entry(vp, &ha->vp_list, list) {
6896 atomic_inc(&vp->vref_count);
6897 spin_unlock_irqrestore(&ha->vport_slock, flags);
6898 qla2x00_mark_all_devices_lost(vp, 0);
6899 spin_lock_irqsave(&ha->vport_slock, flags);
6900 atomic_dec(&vp->vref_count);
6901 }
6902 spin_unlock_irqrestore(&ha->vport_slock, flags);
6903
6904 /* Clear all async request states across all VPs. */
6905 list_for_each_entry(fcport, &vha->vp_fcports, list)
6906 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6907
6908 spin_lock_irqsave(&ha->vport_slock, flags);
6909 list_for_each_entry(vp, &ha->vp_list, list) {
6910 atomic_inc(&vp->vref_count);
6911 spin_unlock_irqrestore(&ha->vport_slock, flags);
6912 list_for_each_entry(fcport, &vp->vp_fcports, list)
6913 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6914 spin_lock_irqsave(&ha->vport_slock, flags);
6915 atomic_dec(&vp->vref_count);
6916 }
6917 spin_unlock_irqrestore(&ha->vport_slock, flags);
6918}
6919
6920
14e660e6
SJ		 6921static pci_ers_result_t
6922qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6923{
85880801
AV		 6924 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6925 struct qla_hw_data *ha = vha->hw;
6926
7c3df132
SK		 6927 ql_dbg(ql_dbg_aer, vha, 0x9000,
6928 "PCI error detected, state %x.\n", state);
b9b12f73 6929
efdb5760
SC		 6930 if (!atomic_read(&pdev->enable_cnt)) {
6931 ql_log(ql_log_info, vha, 0xffff,
6932 "PCI device is disabled,state %x\n", state);
6933 return PCI_ERS_RESULT_NEED_RESET;
6934 }
6935
14e660e6
SJ		 6936 switch (state) {
6937 case pci_channel_io_normal:
85880801 6938 ha->flags.eeh_busy = 0;
c38d1baf 6939 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6940 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6941 qla2xxx_wake_dpc(vha);
6942 }
14e660e6
SJ		 6943 return PCI_ERS_RESULT_CAN_RECOVER;
6944 case pci_channel_io_frozen:
85880801 6945 ha->flags.eeh_busy = 1;
5386a4e6 6946 qla_pci_error_cleanup(vha);
14e660e6
SJ		 6947 return PCI_ERS_RESULT_NEED_RESET;
6948 case pci_channel_io_perm_failure:
85880801
AV		 6949 ha->flags.pci_channel_io_perm_failure = 1;
6950 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
c38d1baf 6951 if (ql2xmqsupport || ql2xnvmeenable) {
d7459527
MH		 6952 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6953 qla2xxx_wake_dpc(vha);
6954 }
14e660e6
SJ		 6955 return PCI_ERS_RESULT_DISCONNECT;
6956 }
6957 return PCI_ERS_RESULT_NEED_RESET;
6958}
6959
6960static pci_ers_result_t
6961qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6962{
6963 int risc_paused = 0;
6964 uint32_t stat;
6965 unsigned long flags;
e315cd28
AC		 6966 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6967 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6968 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6969 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6970
bcc5b6d3
SK		 6971 if (IS_QLA82XX(ha))
6972 return PCI_ERS_RESULT_RECOVERED;
6973
14e660e6
SJ		 6974 spin_lock_irqsave(&ha->hardware_lock, flags);
6975 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6976 stat = RD_REG_DWORD(&reg->hccr);
6977 if (stat & HCCR_RISC_PAUSE)
6978 risc_paused = 1;
6979 } else if (IS_QLA23XX(ha)) {
6980 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6981 if (stat & HSR_RISC_PAUSED)
6982 risc_paused = 1;
6983 } else if (IS_FWI2_CAPABLE(ha)) {
6984 stat = RD_REG_DWORD(&reg24->host_status);
6985 if (stat & HSRX_RISC_PAUSED)
6986 risc_paused = 1;
6987 }
6988 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6989
6990 if (risc_paused) {
7c3df132
SK		 6991 ql_log(ql_log_info, base_vha, 0x9003,
6992 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6993 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6994
6995 return PCI_ERS_RESULT_NEED_RESET;
6996 } else
6997 return PCI_ERS_RESULT_RECOVERED;
6998}
6999
7000static pci_ers_result_t
7001qla2xxx_pci_slot_reset(struct pci_dev *pdev)
7002{
7003 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 7004 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7005 struct qla_hw_data *ha = base_vha->hw;
5386a4e6
QT		 7006 int rc;
7007 struct qla_qpair *qpair = NULL;
09483916 7008
7c3df132
SK		 7009 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
7010 "Slot Reset.\n");
85880801 7011
90a86fc0
JC		 7012 /* Workaround: qla2xxx driver which access hardware earlier
7013 * needs error state to be pci_channel_io_online.
7014 * Otherwise mailbox command timesout.
7015 */
7016 pdev->error_state = pci_channel_io_normal;
7017
7018 pci_restore_state(pdev);
7019
8c1496bd
RL		 7020 /* pci_restore_state() clears the saved_state flag of the device
7021 * save restored state which resets saved_state flag
7022 */
7023 pci_save_state(pdev);
7024
09483916
BH		 7025 if (ha->mem_only)
7026 rc = pci_enable_device_mem(pdev);
7027 else
7028 rc = pci_enable_device(pdev);
14e660e6 7029
09483916 7030 if (rc) {
7c3df132 7031 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 7032 "Can't re-enable PCI device after reset.\n");
a5b36321 7033 goto exit_slot_reset;
14e660e6 7034 }
14e660e6 7035
90a86fc0 7036
e315cd28 7037 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 7038 goto exit_slot_reset;
7039
5386a4e6
QT		 7040 mutex_lock(&ha->mq_lock);
7041 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7042 qpair->online = 1;
7043 mutex_unlock(&ha->mq_lock);
85880801 7044
5386a4e6 7045 base_vha->flags.online = 1;
e315cd28 7046 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 7047 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 7048 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 7049 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 7050
90a86fc0 7051
a5b36321 7052exit_slot_reset:
7c3df132
SK		 7053 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
7054 "slot_reset return %x.\n", ret);
85880801 7055
14e660e6
SJ		 7056 return ret;
7057}
7058
7059static void
7060qla2xxx_pci_resume(struct pci_dev *pdev)
7061{
e315cd28
AC		 7062 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7063 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 7064 int ret;
7065
7c3df132
SK		 7066 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
7067 "pci_resume.\n");
85880801 7068
5386a4e6
QT		 7069 ha->flags.eeh_busy = 0;
7070
e315cd28 7071 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 7072 if (ret != QLA_SUCCESS) {
7c3df132
SK		 7073 ql_log(ql_log_fatal, base_vha, 0x9002,
7074 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 7075 }
14e660e6
SJ		 7076}
7077
590f806d
QT		 7078static void
7079qla_pci_reset_prepare(struct pci_dev *pdev)
7080{
7081 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7082 struct qla_hw_data *ha = base_vha->hw;
7083 struct qla_qpair *qpair;
7084
7085 ql_log(ql_log_warn, base_vha, 0xffff,
7086 "%s.\n", __func__);
7087
7088 /*
7089 * PCI FLR/function reset is about to reset the
7090 * slot. Stop the chip to stop all DMA access.
7091 * It is assumed that pci_reset_done will be called
7092 * after FLR to resume Chip operation.
7093 */
7094 ha->flags.eeh_busy = 1;
7095 mutex_lock(&ha->mq_lock);
7096 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7097 qpair->online = 0;
7098 mutex_unlock(&ha->mq_lock);
7099
7100 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7101 qla2x00_abort_isp_cleanup(base_vha);
7102 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16);
7103}
7104
7105static void
7106qla_pci_reset_done(struct pci_dev *pdev)
7107{
7108 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
7109 struct qla_hw_data *ha = base_vha->hw;
7110 struct qla_qpair *qpair;
7111
7112 ql_log(ql_log_warn, base_vha, 0xffff,
7113 "%s.\n", __func__);
7114
7115 /*
7116 * FLR just completed by PCI layer. Resume adapter
7117 */
7118 ha->flags.eeh_busy = 0;
7119 mutex_lock(&ha->mq_lock);
7120 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem)
7121 qpair->online = 1;
7122 mutex_unlock(&ha->mq_lock);
7123
7124 base_vha->flags.online = 1;
7125 ha->isp_ops->abort_isp(base_vha);
7126 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
7127}
7128
5601236b
MH		 7129static int qla2xxx_map_queues(struct Scsi_Host *shost)
7130{
d68b850e 7131 int rc;
5601236b 7132 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
485b0eca 7133 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
5601236b 7134
f3e02695 7135 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase)
ed76e329 7136 rc = blk_mq_map_queues(qmap);
d68b850e 7137 else
f0783d43 7138 rc = blk_mq_pci_map_queues(qmap, vha->hw->pdev, vha->irq_offset);
d68b850e 7139 return rc;
5601236b
MH		 7140}
7141
6515ad71
BVA		 7142struct scsi_host_template qla2xxx_driver_template = {
7143 .module = THIS_MODULE,
7144 .name = QLA2XXX_DRIVER_NAME,
7145 .queuecommand = qla2xxx_queuecommand,
7146
7147 .eh_timed_out = fc_eh_timed_out,
7148 .eh_abort_handler = qla2xxx_eh_abort,
7149 .eh_device_reset_handler = qla2xxx_eh_device_reset,
7150 .eh_target_reset_handler = qla2xxx_eh_target_reset,
7151 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
7152 .eh_host_reset_handler = qla2xxx_eh_host_reset,
7153
7154 .slave_configure = qla2xxx_slave_configure,
7155
7156 .slave_alloc = qla2xxx_slave_alloc,
7157 .slave_destroy = qla2xxx_slave_destroy,
7158 .scan_finished = qla2xxx_scan_finished,
7159 .scan_start = qla2xxx_scan_start,
7160 .change_queue_depth = scsi_change_queue_depth,
7161 .map_queues = qla2xxx_map_queues,
7162 .this_id = -1,
7163 .cmd_per_lun = 3,
7164 .sg_tablesize = SG_ALL,
7165
7166 .max_sectors = 0xFFFF,
7167 .shost_attrs = qla2x00_host_attrs,
7168
7169 .supported_mode = MODE_INITIATOR,
7170 .track_queue_depth = 1,
7171};
7172
a55b2d21 7173static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 7174 .error_detected = qla2xxx_pci_error_detected,
7175 .mmio_enabled = qla2xxx_pci_mmio_enabled,
7176 .slot_reset = qla2xxx_pci_slot_reset,
7177 .resume = qla2xxx_pci_resume,
590f806d
QT		 7178 .reset_prepare = qla_pci_reset_prepare,
7179 .reset_done = qla_pci_reset_done,
14e660e6
SJ		 7180};
7181
5433383e 7182static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 7183 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
7184 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
7185 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
7186 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
7187 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
7188 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
7189 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
7190 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
7191 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 7192 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 7193 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
7194 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 7195 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 7196 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 7197 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 7198 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 7199 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 7200 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 7201 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 7202 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 7203 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 7204 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
ecc89f25
JC		 7205 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) },
7206 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) },
7207 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) },
7208 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) },
7209 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) },
5433383e
AV		 7210 { 0 },
7211};
7212MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
7213
fca29703 7214static struct pci_driver qla2xxx_pci_driver = {
cb63067a 7215 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 7216 .driver = {
7217 .owner = THIS_MODULE,
7218 },
fca29703 7219 .id_table = qla2xxx_pci_tbl,
7ee61397 7220 .probe = qla2x00_probe_one,
4c993f76 7221 .remove = qla2x00_remove_one,
e30d1756 7222 .shutdown = qla2x00_shutdown,
14e660e6 7223 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 7224};
7225
75ef9de1 7226static const struct file_operations apidev_fops = {
6a03b4cd 7227 .owner = THIS_MODULE,
6038f373 7228 .llseek = noop_llseek,
6a03b4cd
HZ		 7229};
7230
1da177e4
LT		 7231/**
7232 * qla2x00_module_init - Module initialization.
7233 **/
7234static int __init
7235qla2x00_module_init(void)
7236{
fca29703
AV		 7237 int ret = 0;
7238
bc04459c
BVA		 7239 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64);
7240 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64);
7241 BUILD_BUG_ON(sizeof(cont_entry_t) != 64);
7242 BUILD_BUG_ON(sizeof(init_cb_t) != 96);
7243 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64);
7244 BUILD_BUG_ON(sizeof(request_t) != 64);
7245 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64);
7246 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64);
7247 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64);
7248 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64);
7249 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64);
7250 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64);
7251 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64);
7252 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64);
7253 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64);
7254 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64);
7255 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64);
7256 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128);
7257 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128);
7258 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64);
7259 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064);
7260 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64);
7261 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56);
7262
1da177e4 7263 /* Allocate cache for SRBs. */
354d6b21 7264 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 7265 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 7266 if (srb_cachep == NULL) {
7c3df132
SK		 7267 ql_log(ql_log_fatal, NULL, 0x0001,
7268 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 7269 return -ENOMEM;
7270 }
7271
2d70c103
NB		 7272 /* Initialize target kmem_cache and mem_pools */
7273 ret = qlt_init();
7274 if (ret < 0) {
c794d24e 7275 goto destroy_cache;
2d70c103
NB		 7276 } else if (ret > 0) {
7277 /*
7278 * If initiator mode is explictly disabled by qlt_init(),
7279 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7280 * performing scsi_scan_target() during LOOP UP event.
7281 */
7282 qla2xxx_transport_functions.disable_target_scan = 1;
7283 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7284 }
7285
1da177e4
LT		 7286 /* Derive version string. */
7287 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 7288 if (ql2xextended_error_logging)
0181944f 7289 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 7290 if (ql2xextended_error_logging == 1)
7291 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 7292
0645cb83
QT		 7293 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7294 qla_insert_tgt_attrs();
7295
1c97a12a
AV		 7296 qla2xxx_transport_template =
7297 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f 7298 if (!qla2xxx_transport_template) {
7c3df132
SK		 7299 ql_log(ql_log_fatal, NULL, 0x0002,
7300 "fc_attach_transport failed...Failing load!.\n");
c794d24e
BVA		 7301 ret = -ENODEV;
7302 goto qlt_exit;
2c3dfe3f 7303 }
6a03b4cd
HZ		 7304
7305 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7306 if (apidev_major < 0) {
7c3df132
SK		 7307 ql_log(ql_log_fatal, NULL, 0x0003,
7308 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 7309 }
7310
2c3dfe3f
SJ		 7311 qla2xxx_transport_vport_template =
7312 fc_attach_transport(&qla2xxx_transport_vport_functions);
7313 if (!qla2xxx_transport_vport_template) {
7c3df132
SK		 7314 ql_log(ql_log_fatal, NULL, 0x0004,
7315 "fc_attach_transport vport failed...Failing load!.\n");
c794d24e
BVA		 7316 ret = -ENODEV;
7317 goto unreg_chrdev;
2c3dfe3f 7318 }
7c3df132
SK		 7319 ql_log(ql_log_info, NULL, 0x0005,
7320 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 7321 qla2x00_version_str);
7ee61397 7322 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703 7323 if (ret) {
7c3df132
SK		 7324 ql_log(ql_log_fatal, NULL, 0x0006,
7325 "pci_register_driver failed...ret=%d Failing load!.\n",
7326 ret);
c794d24e 7327 goto release_vport_transport;
fca29703
AV		 7328 }
7329 return ret;
c794d24e
BVA		 7330
7331release_vport_transport:
7332 fc_release_transport(qla2xxx_transport_vport_template);
7333
7334unreg_chrdev:
7335 if (apidev_major >= 0)
7336 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7337 fc_release_transport(qla2xxx_transport_template);
7338
7339qlt_exit:
7340 qlt_exit();
7341
7342destroy_cache:
7343 kmem_cache_destroy(srb_cachep);
7344 return ret;
1da177e4
LT		 7345}
7346
7347/**
7348 * qla2x00_module_exit - Module cleanup.
7349 **/
7350static void __exit
7351qla2x00_module_exit(void)
7352{
7ee61397 7353 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 7354 qla2x00_release_firmware();
75c1d48a 7355 kmem_cache_destroy(ctx_cachep);
2c3dfe3f 7356 fc_release_transport(qla2xxx_transport_vport_template);
59c209a6
BVA		 7357 if (apidev_major >= 0)
7358 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7359 fc_release_transport(qla2xxx_transport_template);
7360 qlt_exit();
7361 kmem_cache_destroy(srb_cachep);
1da177e4
LT		 7362}
7363
7364module_init(qla2x00_module_init);
7365module_exit(qla2x00_module_exit);
7366
7367MODULE_AUTHOR("QLogic Corporation");
7368MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7369MODULE_LICENSE("GPL");
7370MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 7371MODULE_FIRMWARE(FW_FILE_ISP21XX);
7372MODULE_FIRMWARE(FW_FILE_ISP22XX);
7373MODULE_FIRMWARE(FW_FILE_ISP2300);
7374MODULE_FIRMWARE(FW_FILE_ISP2322);
7375MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 7376MODULE_FIRMWARE(FW_FILE_ISP25XX);
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