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[SCSI] qla2xxx: Enhancements to support ISP83xx.
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
07e264b7 3 * Copyright (c) 2003-2011 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
5a0e3ad6 10#include <linux/slab.h>
2c96d8d0 11#include <linux/vmalloc.h>
1da177e4
LT		 12#include <asm/uaccess.h>
13
1da177e4
LT		 14/*
15 * NVRAM support routines
16 */
17
18/**
fa2a1ce5 19 * qla2x00_lock_nvram_access() -
1da177e4
LT		 20 * @ha: HA context
21 */
a824ebb3 22static void
7b867cf7 23qla2x00_lock_nvram_access(struct qla_hw_data *ha)
1da177e4
LT		 24{
25 uint16_t data;
3d71644c 26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 27
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(&reg->nvram);
30 while (data & NVR_BUSY) {
31 udelay(100);
32 data = RD_REG_WORD(&reg->nvram);
33 }
34
35 /* Lock resource */
36 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
38 udelay(5);
39 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
41 /* Lock failed */
42 udelay(100);
43 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
45 udelay(5);
46 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 }
48 }
49}
50
51/**
fa2a1ce5 52 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 53 * @ha: HA context
54 */
a824ebb3 55static void
7b867cf7 56qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
1da177e4 57{
3d71644c 58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 59
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
63 }
64}
65
7b867cf7
AC		 66/**
67 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @ha: HA context
69 * @data: Serial interface selector
70 */
71static void
72qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73{
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75
76 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
78 NVRAM_DELAY();
79 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
80 NVR_WRT_ENABLE);
81 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
82 NVRAM_DELAY();
83 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
85 NVRAM_DELAY();
86}
87
88/**
89 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
90 * NVRAM.
91 * @ha: HA context
92 * @nv_cmd: NVRAM command
93 *
94 * Bit definitions for NVRAM command:
95 *
96 * Bit 26 = start bit
97 * Bit 25, 24 = opcode
98 * Bit 23-16 = address
99 * Bit 15-0 = write data
100 *
101 * Returns the word read from nvram @addr.
102 */
103static uint16_t
104qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
105{
106 uint8_t cnt;
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
108 uint16_t data = 0;
109 uint16_t reg_data;
110
111 /* Send command to NVRAM. */
112 nv_cmd <<= 5;
113 for (cnt = 0; cnt < 11; cnt++) {
114 if (nv_cmd & BIT_31)
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 else
117 qla2x00_nv_write(ha, 0);
118 nv_cmd <<= 1;
119 }
120
121 /* Read data from NVRAM. */
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
125 NVRAM_DELAY();
126 data <<= 1;
127 reg_data = RD_REG_WORD(&reg->nvram);
128 if (reg_data & NVR_DATA_IN)
129 data |= BIT_0;
130 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
131 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
132 NVRAM_DELAY();
133 }
134
135 /* Deselect chip. */
136 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
137 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
138 NVRAM_DELAY();
139
140 return data;
141}
142
143
1da177e4
LT		 144/**
145 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
146 * request routine to get the word from NVRAM.
147 * @ha: HA context
148 * @addr: Address in NVRAM to read
149 *
150 * Returns the word read from nvram @addr.
151 */
a824ebb3 152static uint16_t
7b867cf7 153qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
1da177e4
LT		 154{
155 uint16_t data;
156 uint32_t nv_cmd;
157
158 nv_cmd = addr << 16;
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
161
162 return (data);
163}
164
7b867cf7
AC		 165/**
166 * qla2x00_nv_deselect() - Deselect NVRAM operations.
167 * @ha: HA context
168 */
169static void
170qla2x00_nv_deselect(struct qla_hw_data *ha)
171{
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173
174 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
175 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
176 NVRAM_DELAY();
177}
178
1da177e4
LT		 179/**
180 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @ha: HA context
182 * @addr: Address in NVRAM to write
183 * @data: word to program
184 */
a824ebb3 185static void
7b867cf7 186qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
1da177e4
LT		 187{
188 int count;
189 uint16_t word;
45aeaf1e 190 uint32_t nv_cmd, wait_cnt;
3d71644c 191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7c3df132 192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1da177e4
LT		 193
194 qla2x00_nv_write(ha, NVR_DATA_OUT);
195 qla2x00_nv_write(ha, 0);
196 qla2x00_nv_write(ha, 0);
197
198 for (word = 0; word < 8; word++)
199 qla2x00_nv_write(ha, NVR_DATA_OUT);
200
201 qla2x00_nv_deselect(ha);
202
203 /* Write data */
204 nv_cmd = (addr << 16) | NV_WRITE_OP;
205 nv_cmd |= data;
206 nv_cmd <<= 5;
207 for (count = 0; count < 27; count++) {
208 if (nv_cmd & BIT_31)
209 qla2x00_nv_write(ha, NVR_DATA_OUT);
210 else
211 qla2x00_nv_write(ha, 0);
212
213 nv_cmd <<= 1;
214 }
215
216 qla2x00_nv_deselect(ha);
217
218 /* Wait for NVRAM to become ready */
219 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 220 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 221 wait_cnt = NVR_WAIT_CNT;
1da177e4 222 do {
45aeaf1e 223 if (!--wait_cnt) {
7c3df132
SK		 224 ql_dbg(ql_dbg_user, vha, 0x708d,
225 "NVRAM didn't go ready...\n");
45aeaf1e
RA		 226 break;
227 }
1da177e4
LT		 228 NVRAM_DELAY();
229 word = RD_REG_WORD(&reg->nvram);
230 } while ((word & NVR_DATA_IN) == 0);
231
232 qla2x00_nv_deselect(ha);
233
234 /* Disable writes */
235 qla2x00_nv_write(ha, NVR_DATA_OUT);
236 for (count = 0; count < 10; count++)
237 qla2x00_nv_write(ha, 0);
238
239 qla2x00_nv_deselect(ha);
240}
241
459c5378 242static int
7b867cf7
AC		 243qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
244 uint16_t data, uint32_t tmo)
459c5378
AV		 245{
246 int ret, count;
247 uint16_t word;
248 uint32_t nv_cmd;
249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
250
251 ret = QLA_SUCCESS;
252
253 qla2x00_nv_write(ha, NVR_DATA_OUT);
254 qla2x00_nv_write(ha, 0);
255 qla2x00_nv_write(ha, 0);
256
257 for (word = 0; word < 8; word++)
258 qla2x00_nv_write(ha, NVR_DATA_OUT);
259
260 qla2x00_nv_deselect(ha);
261
262 /* Write data */
263 nv_cmd = (addr << 16) | NV_WRITE_OP;
264 nv_cmd |= data;
265 nv_cmd <<= 5;
266 for (count = 0; count < 27; count++) {
267 if (nv_cmd & BIT_31)
268 qla2x00_nv_write(ha, NVR_DATA_OUT);
269 else
270 qla2x00_nv_write(ha, 0);
271
272 nv_cmd <<= 1;
273 }
274
275 qla2x00_nv_deselect(ha);
276
277 /* Wait for NVRAM to become ready */
278 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 279 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 280 do {
281 NVRAM_DELAY();
282 word = RD_REG_WORD(&reg->nvram);
283 if (!--tmo) {
284 ret = QLA_FUNCTION_FAILED;
285 break;
286 }
287 } while ((word & NVR_DATA_IN) == 0);
288
289 qla2x00_nv_deselect(ha);
290
291 /* Disable writes */
292 qla2x00_nv_write(ha, NVR_DATA_OUT);
293 for (count = 0; count < 10; count++)
294 qla2x00_nv_write(ha, 0);
295
296 qla2x00_nv_deselect(ha);
297
298 return ret;
299}
300
459c5378
AV		 301/**
302 * qla2x00_clear_nvram_protection() -
303 * @ha: HA context
304 */
305static int
7b867cf7 306qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
459c5378
AV		 307{
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 310 uint32_t word, wait_cnt;
459c5378 311 uint16_t wprot, wprot_old;
7c3df132 312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
459c5378
AV		 313
314 /* Clear NVRAM write protection. */
315 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 316
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 319 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 322 /* Write enable. */
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
328
329 qla2x00_nv_deselect(ha);
330
331 /* Enable protection register. */
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337
338 qla2x00_nv_deselect(ha);
339
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346
347 qla2x00_nv_deselect(ha);
348
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 351 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 352 wait_cnt = NVR_WAIT_CNT;
459c5378 353 do {
45aeaf1e 354 if (!--wait_cnt) {
7c3df132
SK		 355 ql_dbg(ql_dbg_user, vha, 0x708e,
356 "NVRAM didn't go ready...\n");
45aeaf1e
RA		 357 break;
358 }
459c5378
AV		 359 NVRAM_DELAY();
360 word = RD_REG_WORD(&reg->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
45aeaf1e
RA		 363 if (wait_cnt)
364 ret = QLA_SUCCESS;
459c5378 365 } else
45aeaf1e 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 367
368 return ret;
369}
370
371static void
7b867cf7 372qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
459c5378
AV		 373{
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 375 uint32_t word, wait_cnt;
7c3df132 376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
459c5378
AV		 377
378 if (stat != QLA_SUCCESS)
379 return;
380
381 /* Set NVRAM write protection. */
382 /* Write enable. */
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
388
389 qla2x00_nv_deselect(ha);
390
391 /* Enable protection register. */
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397
398 qla2x00_nv_deselect(ha);
399
400 /* Enable protection register. */
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406
407 qla2x00_nv_deselect(ha);
408
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 411 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 412 wait_cnt = NVR_WAIT_CNT;
459c5378 413 do {
45aeaf1e 414 if (!--wait_cnt) {
7c3df132
SK		 415 ql_dbg(ql_dbg_user, vha, 0x708f,
416 "NVRAM didn't go ready...\n");
45aeaf1e
RA		 417 break;
418 }
459c5378
AV		 419 NVRAM_DELAY();
420 word = RD_REG_WORD(&reg->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
422}
423
424
425/*****************************************************************************/
426/* Flash Manipulation Routines */
427/*****************************************************************************/
428
429static inline uint32_t
3a03eb79 430flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 431{
3a03eb79 432 return ha->flash_conf_off | faddr;
459c5378
AV		 433}
434
435static inline uint32_t
3a03eb79 436flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
459c5378 437{
3a03eb79 438 return ha->flash_data_off | faddr;
459c5378
AV		 439}
440
441static inline uint32_t
3a03eb79 442nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 443{
3a03eb79 444 return ha->nvram_conf_off | naddr;
459c5378
AV		 445}
446
447static inline uint32_t
3a03eb79 448nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
459c5378 449{
3a03eb79 450 return ha->nvram_data_off | naddr;
459c5378
AV		 451}
452
e5f82ab8 453static uint32_t
7b867cf7 454qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
459c5378
AV		 455{
456 int rval;
457 uint32_t cnt, data;
458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
459
460 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
461 /* Wait for READ cycle to complete. */
462 rval = QLA_SUCCESS;
463 for (cnt = 3000;
464 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
465 rval == QLA_SUCCESS; cnt--) {
466 if (cnt)
467 udelay(10);
468 else
469 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 470 cond_resched();
459c5378
AV		 471 }
472
473 /* TODO: What happens if we time out? */
474 data = 0xDEADDEAD;
475 if (rval == QLA_SUCCESS)
476 data = RD_REG_DWORD(&reg->flash_data);
477
478 return data;
479}
480
481uint32_t *
7b867cf7 482qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 483 uint32_t dwords)
484{
485 uint32_t i;
3a03eb79
AV		 486 struct qla_hw_data *ha = vha->hw;
487
459c5378
AV		 488 /* Dword reads to flash. */
489 for (i = 0; i < dwords; i++, faddr++)
3a03eb79
AV		 490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491 flash_data_addr(ha, faddr)));
459c5378 492
459c5378
AV		 493 return dwptr;
494}
495
e5f82ab8 496static int
7b867cf7 497qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
459c5378
AV		 498{
499 int rval;
500 uint32_t cnt;
501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
502
503 WRT_REG_DWORD(&reg->flash_data, data);
504 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
505 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
506 /* Wait for Write cycle to complete. */
507 rval = QLA_SUCCESS;
508 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
509 rval == QLA_SUCCESS; cnt--) {
510 if (cnt)
511 udelay(10);
512 else
513 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 514 cond_resched();
459c5378
AV		 515 }
516 return rval;
517}
518
e5f82ab8 519static void
7b867cf7 520qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
459c5378
AV		 521 uint8_t *flash_id)
522{
523 uint32_t ids;
524
3a03eb79 525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
459c5378
AV		 526 *man_id = LSB(ids);
527 *flash_id = MSB(ids);
45aeaf1e
RA		 528
529 /* Check if man_id and flash_id are valid. */
530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
531 /* Read information using 0x9f opcode
532 * Device ID, Mfg ID would be read in the format:
533 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
534 * Example: ATMEL 0x00 01 45 1F
535 * Extract MFG and Dev ID from last two bytes.
536 */
3a03eb79 537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
45aeaf1e
RA		 538 *man_id = LSB(ids);
539 *flash_id = MSB(ids);
540 }
459c5378
AV		 541}
542
c00d8994 543static int
7b867cf7 544qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
c00d8994
AV		 545{
546 const char *loc, *locations[] = { "DEF", "PCI" };
547 uint32_t pcihdr, pcids;
548 uint32_t *dcode;
549 uint8_t *buf, *bcode, last_image;
550 uint16_t cnt, chksum, *wptr;
551 struct qla_flt_location *fltl;
7b867cf7 552 struct qla_hw_data *ha = vha->hw;
73208dfd 553 struct req_que *req = ha->req_q_map[0];
c00d8994
AV		 554
555 /*
556 * FLT-location structure resides after the last PCI region.
557 */
558
559 /* Begin with sane defaults. */
560 loc = locations[0];
3a03eb79
AV		 561 *start = 0;
562 if (IS_QLA24XX_TYPE(ha))
563 *start = FA_FLASH_LAYOUT_ADDR_24;
564 else if (IS_QLA25XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR;
566 else if (IS_QLA81XX(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_81;
a9083016
GM		 568 else if (IS_QLA82XX(ha)) {
569 *start = FA_FLASH_LAYOUT_ADDR_82;
570 goto end;
6246b8a1
GM		 571 } else if (IS_QLA83XX(ha)) {
572 *start = FA_FLASH_LAYOUT_ADDR_83;
573 goto end;
a9083016 574 }
c00d8994 575 /* Begin with first PCI expansion ROM header. */
7b867cf7
AC		 576 buf = (uint8_t *)req->ring;
577 dcode = (uint32_t *)req->ring;
c00d8994
AV		 578 pcihdr = 0;
579 last_image = 1;
580 do {
581 /* Verify PCI expansion ROM header. */
7b867cf7 582 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
c00d8994
AV		 583 bcode = buf + (pcihdr % 4);
584 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
585 goto end;
586
587 /* Locate PCI data structure. */
588 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
7b867cf7 589 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
c00d8994
AV		 590 bcode = buf + (pcihdr % 4);
591
592 /* Validate signature of PCI data structure. */
593 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
594 bcode[0x2] != 'I' || bcode[0x3] != 'R')
595 goto end;
596
597 last_image = bcode[0x15] & BIT_7;
598
599 /* Locate next PCI expansion ROM. */
600 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
601 } while (!last_image);
602
603 /* Now verify FLT-location structure. */
7b867cf7
AC		 604 fltl = (struct qla_flt_location *)req->ring;
605 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
c00d8994
AV		 606 sizeof(struct qla_flt_location) >> 2);
607 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
608 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
609 goto end;
610
7b867cf7 611 wptr = (uint16_t *)req->ring;
c00d8994
AV		 612 cnt = sizeof(struct qla_flt_location) >> 1;
613 for (chksum = 0; cnt; cnt--)
614 chksum += le16_to_cpu(*wptr++);
615 if (chksum) {
7c3df132 616 ql_log(ql_log_fatal, vha, 0x0045,
c00d8994 617 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
7c3df132
SK		 618 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
619 buf, sizeof(struct qla_flt_location));
c00d8994
AV		 620 return QLA_FUNCTION_FAILED;
621 }
622
623 /* Good data. Use specified location. */
624 loc = locations[1];
79c13a74
HZ		 625 *start = (le16_to_cpu(fltl->start_hi) << 16 |
626 le16_to_cpu(fltl->start_lo)) >> 2;
c00d8994 627end:
7c3df132
SK		 628 ql_dbg(ql_dbg_init, vha, 0x0046,
629 "FLTL[%s] = 0x%x.\n",
630 loc, *start);
c00d8994
AV		 631 return QLA_SUCCESS;
632}
633
634static void
7b867cf7 635qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
c00d8994
AV		 636{
637 const char *loc, *locations[] = { "DEF", "FLT" };
3a03eb79
AV		 638 const uint32_t def_fw[] =
639 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
640 const uint32_t def_boot[] =
641 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
642 const uint32_t def_vpd_nvram[] =
643 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
3d79038f
AV		 644 const uint32_t def_vpd0[] =
645 { 0, 0, FA_VPD0_ADDR_81 };
646 const uint32_t def_vpd1[] =
647 { 0, 0, FA_VPD1_ADDR_81 };
648 const uint32_t def_nvram0[] =
649 { 0, 0, FA_NVRAM0_ADDR_81 };
650 const uint32_t def_nvram1[] =
651 { 0, 0, FA_NVRAM1_ADDR_81 };
3a03eb79
AV		 652 const uint32_t def_fdt[] =
653 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
654 FA_FLASH_DESCR_ADDR_81 };
655 const uint32_t def_npiv_conf0[] =
656 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
657 FA_NPIV_CONF0_ADDR_81 };
658 const uint32_t def_npiv_conf1[] =
659 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
660 FA_NPIV_CONF1_ADDR_81 };
09ff701a
SR		 661 const uint32_t fcp_prio_cfg0[] =
662 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
663 0 };
664 const uint32_t fcp_prio_cfg1[] =
665 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
666 0 };
3a03eb79 667 uint32_t def;
c00d8994
AV		 668 uint16_t *wptr;
669 uint16_t cnt, chksum;
670 uint32_t start;
671 struct qla_flt_header *flt;
672 struct qla_flt_region *region;
7b867cf7 673 struct qla_hw_data *ha = vha->hw;
73208dfd 674 struct req_que *req = ha->req_q_map[0];
c00d8994 675
2f0f3f4f
MI		 676 def = 0;
677 if (IS_QLA25XX(ha))
678 def = 1;
679 else if (IS_QLA81XX(ha))
680 def = 2;
ff8073ff
AV		 681
682 /* Assign FCP prio region since older adapters may not have FLT, or
683 FCP prio region in it's FLT.
684 */
685 ha->flt_region_fcp_prio = ha->flags.port0 ?
686 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
687
c00d8994 688 ha->flt_region_flt = flt_addr;
7b867cf7
AC		 689 wptr = (uint16_t *)req->ring;
690 flt = (struct qla_flt_header *)req->ring;
c00d8994 691 region = (struct qla_flt_region *)&flt[1];
7b867cf7 692 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994
AV		 693 flt_addr << 2, OPTROM_BURST_SIZE);
694 if (*wptr == __constant_cpu_to_le16(0xffff))
695 goto no_flash_data;
696 if (flt->version != __constant_cpu_to_le16(1)) {
7c3df132
SK		 697 ql_log(ql_log_warn, vha, 0x0047,
698 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
c00d8994 699 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
7c3df132 700 le16_to_cpu(flt->checksum));
c00d8994
AV		 701 goto no_flash_data;
702 }
703
704 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
705 for (chksum = 0; cnt; cnt--)
706 chksum += le16_to_cpu(*wptr++);
707 if (chksum) {
7c3df132
SK		 708 ql_log(ql_log_fatal, vha, 0x0048,
709 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
c00d8994 710 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
7c3df132 711 le16_to_cpu(flt->checksum));
c00d8994
AV		 712 goto no_flash_data;
713 }
714
715 loc = locations[1];
716 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
717 for ( ; cnt; cnt--, region++) {
718 /* Store addresses as DWORD offsets. */
719 start = le32_to_cpu(region->start) >> 2;
7c3df132
SK		 720 ql_dbg(ql_dbg_init, vha, 0x0049,
721 "FLT[%02x]: start=0x%x "
722 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code),
723 start, le32_to_cpu(region->end) >> 2,
724 le32_to_cpu(region->size));
c00d8994 725
9088608e 726 switch (le32_to_cpu(region->code) & 0xff) {
6246b8a1
GM		 727 case FLT_REG_FCOE_FW:
728 if (!IS_QLA8031(ha))
729 break;
730 ha->flt_region_fw = start;
731 break;
c00d8994 732 case FLT_REG_FW:
6246b8a1
GM		 733 if (IS_QLA8031(ha))
734 break;
c00d8994
AV		 735 ha->flt_region_fw = start;
736 break;
737 case FLT_REG_BOOT_CODE:
738 ha->flt_region_boot = start;
739 break;
740 case FLT_REG_VPD_0:
6246b8a1
GM		 741 if (IS_QLA8031(ha))
742 break;
c00d8994 743 ha->flt_region_vpd_nvram = start;
a9083016
GM		 744 if (IS_QLA82XX(ha))
745 break;
e5b68a61 746 if (ha->flags.port0)
3d79038f
AV		 747 ha->flt_region_vpd = start;
748 break;
749 case FLT_REG_VPD_1:
6246b8a1 750 if (IS_QLA82XX(ha) || IS_QLA8031(ha))
a9083016 751 break;
e5b68a61 752 if (!ha->flags.port0)
3d79038f
AV		 753 ha->flt_region_vpd = start;
754 break;
755 case FLT_REG_NVRAM_0:
6246b8a1
GM		 756 if (IS_QLA8031(ha))
757 break;
e5b68a61 758 if (ha->flags.port0)
3d79038f
AV		 759 ha->flt_region_nvram = start;
760 break;
761 case FLT_REG_NVRAM_1:
6246b8a1
GM		 762 if (IS_QLA8031(ha))
763 break;
e5b68a61 764 if (!ha->flags.port0)
3d79038f 765 ha->flt_region_nvram = start;
c00d8994
AV		 766 break;
767 case FLT_REG_FDT:
768 ha->flt_region_fdt = start;
769 break;
272976ca 770 case FLT_REG_NPIV_CONF_0:
e5b68a61 771 if (ha->flags.port0)
272976ca
AV		 772 ha->flt_region_npiv_conf = start;
773 break;
774 case FLT_REG_NPIV_CONF_1:
e5b68a61 775 if (!ha->flags.port0)
272976ca
AV		 776 ha->flt_region_npiv_conf = start;
777 break;
cbc8eb67
AV		 778 case FLT_REG_GOLD_FW:
779 ha->flt_region_gold_fw = start;
780 break;
09ff701a 781 case FLT_REG_FCP_PRIO_0:
bfdaa761 782 if (ha->flags.port0)
09ff701a
SR		 783 ha->flt_region_fcp_prio = start;
784 break;
785 case FLT_REG_FCP_PRIO_1:
bfdaa761 786 if (!ha->flags.port0)
09ff701a
SR		 787 ha->flt_region_fcp_prio = start;
788 break;
a9083016
GM		 789 case FLT_REG_BOOT_CODE_82XX:
790 ha->flt_region_boot = start;
791 break;
792 case FLT_REG_FW_82XX:
793 ha->flt_region_fw = start;
794 break;
795 case FLT_REG_GOLD_FW_82XX:
796 ha->flt_region_gold_fw = start;
797 break;
798 case FLT_REG_BOOTLOAD_82XX:
799 ha->flt_region_bootload = start;
800 break;
801 case FLT_REG_VPD_82XX:
802 ha->flt_region_vpd = start;
803 break;
6246b8a1
GM		 804 case FLT_REG_FCOE_VPD_0:
805 if (!IS_QLA8031(ha))
806 break;
807 ha->flt_region_vpd_nvram = start;
808 if (ha->flags.port0)
809 ha->flt_region_vpd = start;
810 break;
811 case FLT_REG_FCOE_VPD_1:
812 if (!IS_QLA8031(ha))
813 break;
814 if (!ha->flags.port0)
815 ha->flt_region_vpd = start;
816 break;
817 case FLT_REG_FCOE_NVRAM_0:
818 if (!IS_QLA8031(ha))
819 break;
820 if (ha->flags.port0)
821 ha->flt_region_nvram = start;
822 break;
823 case FLT_REG_FCOE_NVRAM_1:
824 if (!IS_QLA8031(ha))
825 break;
826 if (!ha->flags.port0)
827 ha->flt_region_nvram = start;
828 break;
c00d8994
AV		 829 }
830 }
831 goto done;
832
833no_flash_data:
834 /* Use hardcoded defaults. */
835 loc = locations[0];
3a03eb79
AV		 836 ha->flt_region_fw = def_fw[def];
837 ha->flt_region_boot = def_boot[def];
838 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
e5b68a61 839 ha->flt_region_vpd = ha->flags.port0 ?
09ff701a 840 def_vpd0[def] : def_vpd1[def];
e5b68a61 841 ha->flt_region_nvram = ha->flags.port0 ?
09ff701a 842 def_nvram0[def] : def_nvram1[def];
3a03eb79 843 ha->flt_region_fdt = def_fdt[def];
e5b68a61 844 ha->flt_region_npiv_conf = ha->flags.port0 ?
09ff701a 845 def_npiv_conf0[def] : def_npiv_conf1[def];
c00d8994 846done:
7c3df132 847 ql_dbg(ql_dbg_init, vha, 0x004a,
6246b8a1
GM		 848 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
849 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
850 loc, ha->flt_region_boot, ha->flt_region_fw,
851 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
852 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
853 ha->flt_region_fcp_prio);
c00d8994
AV		 854}
855
856static void
7b867cf7 857qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
7d232c74 858{
821b3996 859#define FLASH_BLK_SIZE_4K 0x1000
7d232c74
AV		 860#define FLASH_BLK_SIZE_32K 0x8000
861#define FLASH_BLK_SIZE_64K 0x10000
c00d8994 862 const char *loc, *locations[] = { "MID", "FDT" };
7d232c74
AV		 863 uint16_t cnt, chksum;
864 uint16_t *wptr;
865 struct qla_fdt_layout *fdt;
866 uint8_t man_id, flash_id;
a9083016 867 uint16_t mid = 0, fid = 0;
7b867cf7 868 struct qla_hw_data *ha = vha->hw;
73208dfd 869 struct req_que *req = ha->req_q_map[0];
7d232c74 870
7b867cf7
AC		 871 wptr = (uint16_t *)req->ring;
872 fdt = (struct qla_fdt_layout *)req->ring;
873 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
c00d8994 874 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
7d232c74
AV		 875 if (*wptr == __constant_cpu_to_le16(0xffff))
876 goto no_flash_data;
877 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
878 fdt->sig[3] != 'D')
879 goto no_flash_data;
880
881 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
882 cnt++)
883 chksum += le16_to_cpu(*wptr++);
884 if (chksum) {
7c3df132
SK		 885 ql_dbg(ql_dbg_init, vha, 0x004c,
886 "Inconsistent FDT detected:"
887 " checksum=0x%x id=%c version0x%x.\n", chksum,
888 fdt->sig[0], le16_to_cpu(fdt->version));
889 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
890 (uint8_t *)fdt, sizeof(*fdt));
7d232c74
AV		 891 goto no_flash_data;
892 }
893
c00d8994
AV		 894 loc = locations[1];
895 mid = le16_to_cpu(fdt->man_id);
896 fid = le16_to_cpu(fdt->id);
7d232c74 897 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
3a03eb79 898 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
7d232c74
AV		 899 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
900 if (fdt->unprotect_sec_cmd) {
3a03eb79 901 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
7d232c74
AV		 902 fdt->unprotect_sec_cmd);
903 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
3a03eb79
AV		 904 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
905 flash_conf_addr(ha, 0x0336);
7d232c74 906 }
c00d8994 907 goto done;
7d232c74 908no_flash_data:
c00d8994 909 loc = locations[0];
a9083016
GM		 910 if (IS_QLA82XX(ha)) {
911 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
912 goto done;
913 }
7d232c74 914 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
c00d8994
AV		 915 mid = man_id;
916 fid = flash_id;
7d232c74 917 ha->fdt_wrt_disable = 0x9c;
3a03eb79 918 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
7d232c74
AV		 919 switch (man_id) {
920 case 0xbf: /* STT flash. */
921 if (flash_id == 0x8e)
922 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
923 else
924 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
925
926 if (flash_id == 0x80)
3a03eb79 927 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
7d232c74
AV		 928 break;
929 case 0x13: /* ST M25P80. */
930 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
931 break;
932 case 0x1f: /* Atmel 26DF081A. */
821b3996 933 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
3a03eb79
AV		 934 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
935 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
936 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
7d232c74
AV		 937 break;
938 default:
939 /* Default to 64 kb sector size. */
940 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
941 break;
942 }
c00d8994 943done:
7c3df132 944 ql_dbg(ql_dbg_init, vha, 0x004d,
d8424f68
JP		 945 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
946 "pr=%x wrtd=0x%x blk=0x%x.\n",
947 loc, mid, fid,
7d232c74 948 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
7c3df132
SK		 949 ha->fdt_wrt_disable, ha->fdt_block_size);
950
7d232c74
AV		 951}
952
a9083016
GM		 953static void
954qla2xxx_get_idc_param(scsi_qla_host_t *vha)
955{
956#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
957 uint32_t *wptr;
958 struct qla_hw_data *ha = vha->hw;
959 struct req_que *req = ha->req_q_map[0];
960
961 if (!IS_QLA82XX(ha))
962 return;
963
964 wptr = (uint32_t *)req->ring;
965 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
966 QLA82XX_IDC_PARAM_ADDR , 8);
967
968 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
969 ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
970 ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
971 } else {
972 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
973 ha->nx_reset_timeout = le32_to_cpu(*wptr);
974 }
7c3df132
SK		 975 ql_dbg(ql_dbg_init, vha, 0x004e,
976 "nx_dev_init_timeout=%d "
977 "nx_reset_timeout=%d.\n", ha->nx_dev_init_timeout,
978 ha->nx_reset_timeout);
a9083016
GM		 979 return;
980}
981
c00d8994 982int
7b867cf7 983qla2xxx_get_flash_info(scsi_qla_host_t *vha)
c00d8994
AV		 984{
985 int ret;
986 uint32_t flt_addr;
7b867cf7 987 struct qla_hw_data *ha = vha->hw;
c00d8994 988
6246b8a1
GM		 989 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
990 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
c00d8994
AV		 991 return QLA_SUCCESS;
992
7b867cf7 993 ret = qla2xxx_find_flt_start(vha, &flt_addr);
c00d8994
AV		 994 if (ret != QLA_SUCCESS)
995 return ret;
996
7b867cf7
AC		 997 qla2xxx_get_flt_info(vha, flt_addr);
998 qla2xxx_get_fdt_info(vha);
a9083016 999 qla2xxx_get_idc_param(vha);
c00d8994
AV		 1000
1001 return QLA_SUCCESS;
1002}
1003
272976ca 1004void
7b867cf7 1005qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
272976ca
AV		 1006{
1007#define NPIV_CONFIG_SIZE (16*1024)
1008 void *data;
1009 uint16_t *wptr;
1010 uint16_t cnt, chksum;
73208dfd 1011 int i;
272976ca
AV		 1012 struct qla_npiv_header hdr;
1013 struct qla_npiv_entry *entry;
7b867cf7 1014 struct qla_hw_data *ha = vha->hw;
272976ca 1015
6246b8a1
GM		 1016 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1017 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
272976ca
AV		 1018 return;
1019
7b867cf7 1020 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
272976ca
AV		 1021 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1022 if (hdr.version == __constant_cpu_to_le16(0xffff))
1023 return;
1024 if (hdr.version != __constant_cpu_to_le16(1)) {
7c3df132
SK		 1025 ql_dbg(ql_dbg_user, vha, 0x7090,
1026 "Unsupported NPIV-Config "
272976ca
AV		 1027 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1028 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
7c3df132 1029 le16_to_cpu(hdr.checksum));
272976ca
AV		 1030 return;
1031 }
1032
1033 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1034 if (!data) {
7c3df132
SK		 1035 ql_log(ql_log_warn, vha, 0x7091,
1036 "Unable to allocate memory for data.\n");
272976ca
AV		 1037 return;
1038 }
1039
7b867cf7 1040 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
272976ca
AV		 1041 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1042
1043 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1044 sizeof(struct qla_npiv_entry)) >> 1;
1045 for (wptr = data, chksum = 0; cnt; cnt--)
1046 chksum += le16_to_cpu(*wptr++);
1047 if (chksum) {
7c3df132
SK		 1048 ql_dbg(ql_dbg_user, vha, 0x7092,
1049 "Inconsistent NPIV-Config "
272976ca
AV		 1050 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1051 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
7c3df132 1052 le16_to_cpu(hdr.checksum));
272976ca
AV		 1053 goto done;
1054 }
1055
1056 entry = data + sizeof(struct qla_npiv_header);
1057 cnt = le16_to_cpu(hdr.entries);
73208dfd 1058 for (i = 0; cnt; cnt--, entry++, i++) {
272976ca
AV		 1059 uint16_t flags;
1060 struct fc_vport_identifiers vid;
1061 struct fc_vport *vport;
1062
40859ae5
AC		 1063 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1064
272976ca
AV		 1065 flags = le16_to_cpu(entry->flags);
1066 if (flags == 0xffff)
1067 continue;
1068 if ((flags & BIT_0) == 0)
1069 continue;
1070
1071 memset(&vid, 0, sizeof(vid));
1072 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1073 vid.vport_type = FC_PORTTYPE_NPIV;
1074 vid.disable = false;
1075 vid.port_name = wwn_to_u64(entry->port_name);
1076 vid.node_name = wwn_to_u64(entry->node_name);
1077
7c3df132
SK		 1078 ql_dbg(ql_dbg_user, vha, 0x7093,
1079 "NPIV[%02x]: wwpn=%llx "
1080 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1081 (unsigned long long)vid.port_name,
1082 (unsigned long long)vid.node_name,
1083 le16_to_cpu(entry->vf_id),
1084 entry->q_qos, entry->f_qos);
73208dfd
AC		 1085
1086 if (i < QLA_PRECONFIG_VPORTS) {
1087 vport = fc_vport_create(vha->host, 0, &vid);
1088 if (!vport)
7c3df132
SK		 1089 ql_log(ql_log_warn, vha, 0x7094,
1090 "NPIV-Config Failed to create vport [%02x]: "
1091 "wwpn=%llx wwnn=%llx.\n", cnt,
1092 (unsigned long long)vid.port_name,
1093 (unsigned long long)vid.node_name);
73208dfd 1094 }
272976ca
AV		 1095 }
1096done:
1097 kfree(data);
1098}
1099
1d2874de
JC		 1100static int
1101qla24xx_unprotect_flash(scsi_qla_host_t *vha)
cb8dacbf 1102{
1d2874de 1103 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 1104 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1105
1d2874de
JC		 1106 if (ha->flags.fac_supported)
1107 return qla81xx_fac_do_write_enable(vha, 1);
1108
cb8dacbf
AV		 1109 /* Enable flash write. */
1110 WRT_REG_DWORD(&reg->ctrl_status,
1111 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1112 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1113
7d232c74 1114 if (!ha->fdt_wrt_disable)
1d2874de 1115 goto done;
7d232c74 1116
b872ca40 1117 /* Disable flash write-protection, first clear SR protection bit */
3a03eb79 1118 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
b872ca40 1119 /* Then write zero again to clear remaining SR bits.*/
3a03eb79 1120 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1d2874de
JC		 1121done:
1122 return QLA_SUCCESS;
cb8dacbf
AV		 1123}
1124
1d2874de
JC		 1125static int
1126qla24xx_protect_flash(scsi_qla_host_t *vha)
cb8dacbf
AV		 1127{
1128 uint32_t cnt;
1d2874de 1129 struct qla_hw_data *ha = vha->hw;
cb8dacbf
AV		 1130 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1131
1d2874de
JC		 1132 if (ha->flags.fac_supported)
1133 return qla81xx_fac_do_write_enable(vha, 0);
1134
7d232c74
AV		 1135 if (!ha->fdt_wrt_disable)
1136 goto skip_wrt_protect;
1137
cb8dacbf 1138 /* Enable flash write-protection and wait for completion. */
3a03eb79 1139 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
7d232c74 1140 ha->fdt_wrt_disable);
cb8dacbf 1141 for (cnt = 300; cnt &&
3a03eb79 1142 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
cb8dacbf
AV		 1143 cnt--) {
1144 udelay(10);
1145 }
1146
7d232c74 1147skip_wrt_protect:
cb8dacbf
AV		 1148 /* Disable flash write. */
1149 WRT_REG_DWORD(&reg->ctrl_status,
1150 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1151 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1d2874de
JC		 1152
1153 return QLA_SUCCESS;
1154}
1155
1156static int
1157qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1158{
1159 struct qla_hw_data *ha = vha->hw;
1160 uint32_t start, finish;
1161
1162 if (ha->flags.fac_supported) {
1163 start = fdata >> 2;
1164 finish = start + (ha->fdt_block_size >> 2) - 1;
1165 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1166 start), flash_data_addr(ha, finish));
1167 }
1168
1169 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1170 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1171 ((fdata >> 16) & 0xff));
cb8dacbf
AV		 1172}
1173
e5f82ab8 1174static int
7b867cf7 1175qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
459c5378
AV		 1176 uint32_t dwords)
1177{
1178 int ret;
7c283177 1179 uint32_t liter;
7d232c74 1180 uint32_t sec_mask, rest_addr;
85d0acbb 1181 uint32_t fdata;
338c9161
AV		 1182 dma_addr_t optrom_dma;
1183 void *optrom = NULL;
7b867cf7 1184 struct qla_hw_data *ha = vha->hw;
459c5378 1185
338c9161 1186 /* Prepare burst-capable write on supported ISPs. */
6246b8a1
GM		 1187 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha)) &&
1188 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
338c9161
AV		 1189 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1190 &optrom_dma, GFP_KERNEL);
1191 if (!optrom) {
7c3df132
SK		 1192 ql_log(ql_log_warn, vha, 0x7095,
1193 "Unable to allocate "
1194 "memory for optrom burst write (%x KB).\n",
1195 OPTROM_BURST_SIZE / 1024);
338c9161
AV		 1196 }
1197 }
1198
7d232c74 1199 rest_addr = (ha->fdt_block_size >> 2) - 1;
85d0acbb 1200 sec_mask = ~rest_addr;
459c5378 1201
1d2874de
JC		 1202 ret = qla24xx_unprotect_flash(vha);
1203 if (ret != QLA_SUCCESS) {
7c3df132 1204 ql_log(ql_log_warn, vha, 0x7096,
1d2874de
JC		 1205 "Unable to unprotect flash for update.\n");
1206 goto done;
1207 }
459c5378 1208
338c9161 1209 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
85d0acbb 1210 fdata = (faddr & sec_mask) << 2;
45aeaf1e 1211
338c9161 1212 /* Are we at the beginning of a sector? */
85d0acbb 1213 if ((faddr & rest_addr) == 0) {
7d232c74
AV		 1214 /* Do sector unprotect. */
1215 if (ha->fdt_unprotect_sec_cmd)
338c9161 1216 qla24xx_write_flash_dword(ha,
7d232c74 1217 ha->fdt_unprotect_sec_cmd,
338c9161 1218 (fdata & 0xff00) | ((fdata << 16) &
459c5378 1219 0xff0000) | ((fdata >> 16) & 0xff));
1d2874de 1220 ret = qla24xx_erase_sector(vha, fdata);
338c9161 1221 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1222 ql_dbg(ql_dbg_user, vha, 0x7007,
1223 "Unable to erase erase sector: address=%x.\n",
1224 faddr);
338c9161 1225 break;
459c5378 1226 }
338c9161
AV		 1227 }
1228
1229 /* Go with burst-write. */
94d6a2b3 1230 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
338c9161 1231 /* Copy data to DMA'ble buffer. */
7c283177 1232 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
338c9161 1233
7b867cf7 1234 ret = qla2x00_load_ram(vha, optrom_dma,
3a03eb79 1235 flash_data_addr(ha, faddr),
338c9161 1236 OPTROM_BURST_DWORDS);
459c5378 1237 if (ret != QLA_SUCCESS) {
7c3df132 1238 ql_log(ql_log_warn, vha, 0x7097,
338c9161
AV		 1239 "Unable to burst-write optrom segment "
1240 "(%x/%x/%llx).\n", ret,
3a03eb79 1241 flash_data_addr(ha, faddr),
875baf3c 1242 (unsigned long long)optrom_dma);
7c3df132 1243 ql_log(ql_log_warn, vha, 0x7098,
338c9161
AV		 1244 "Reverting to slow-write.\n");
1245
1246 dma_free_coherent(&ha->pdev->dev,
1247 OPTROM_BURST_SIZE, optrom, optrom_dma);
1248 optrom = NULL;
1249 } else {
1250 liter += OPTROM_BURST_DWORDS - 1;
1251 faddr += OPTROM_BURST_DWORDS - 1;
1252 dwptr += OPTROM_BURST_DWORDS - 1;
1253 continue;
459c5378 1254 }
338c9161 1255 }
45aeaf1e 1256
338c9161 1257 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1258 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
338c9161 1259 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1260 ql_dbg(ql_dbg_user, vha, 0x7006,
1261 "Unable to program flash address=%x data=%x.\n",
1262 faddr, *dwptr);
338c9161 1263 break;
459c5378 1264 }
338c9161 1265
7d232c74
AV		 1266 /* Do sector protect. */
1267 if (ha->fdt_unprotect_sec_cmd &&
338c9161
AV		 1268 ((faddr & rest_addr) == rest_addr))
1269 qla24xx_write_flash_dword(ha,
7d232c74 1270 ha->fdt_protect_sec_cmd,
338c9161
AV		 1271 (fdata & 0xff00) | ((fdata << 16) &
1272 0xff0000) | ((fdata >> 16) & 0xff));
1273 }
459c5378 1274
1d2874de
JC		 1275 ret = qla24xx_protect_flash(vha);
1276 if (ret != QLA_SUCCESS)
7c3df132 1277 ql_log(ql_log_warn, vha, 0x7099,
1d2874de
JC		 1278 "Unable to protect flash after update.\n");
1279done:
338c9161
AV		 1280 if (optrom)
1281 dma_free_coherent(&ha->pdev->dev,
1282 OPTROM_BURST_SIZE, optrom, optrom_dma);
1283
459c5378
AV		 1284 return ret;
1285}
1286
1287uint8_t *
7b867cf7 1288qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1289 uint32_t bytes)
1290{
1291 uint32_t i;
1292 uint16_t *wptr;
7b867cf7 1293 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1294
1295 /* Word reads to NVRAM via registers. */
1296 wptr = (uint16_t *)buf;
1297 qla2x00_lock_nvram_access(ha);
1298 for (i = 0; i < bytes >> 1; i++, naddr++)
1299 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1300 naddr));
1301 qla2x00_unlock_nvram_access(ha);
1302
1303 return buf;
1304}
1305
1306uint8_t *
7b867cf7 1307qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1308 uint32_t bytes)
1309{
1310 uint32_t i;
1311 uint32_t *dwptr;
3a03eb79 1312 struct qla_hw_data *ha = vha->hw;
459c5378 1313
a9083016
GM		 1314 if (IS_QLA82XX(ha))
1315 return buf;
1316
459c5378
AV		 1317 /* Dword reads to flash. */
1318 dwptr = (uint32_t *)buf;
1319 for (i = 0; i < bytes >> 2; i++, naddr++)
3a03eb79
AV		 1320 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1321 nvram_data_addr(ha, naddr)));
459c5378 1322
459c5378
AV		 1323 return buf;
1324}
1325
1326int
7b867cf7 1327qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1328 uint32_t bytes)
1329{
1330 int ret, stat;
1331 uint32_t i;
1332 uint16_t *wptr;
2c96d8d0 1333 unsigned long flags;
7b867cf7 1334 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1335
1336 ret = QLA_SUCCESS;
1337
2c96d8d0 1338 spin_lock_irqsave(&ha->hardware_lock, flags);
459c5378
AV		 1339 qla2x00_lock_nvram_access(ha);
1340
1341 /* Disable NVRAM write-protection. */
1342 stat = qla2x00_clear_nvram_protection(ha);
1343
1344 wptr = (uint16_t *)buf;
1345 for (i = 0; i < bytes >> 1; i++, naddr++) {
1346 qla2x00_write_nvram_word(ha, naddr,
1347 cpu_to_le16(*wptr));
1348 wptr++;
1349 }
1350
1351 /* Enable NVRAM write-protection. */
1352 qla2x00_set_nvram_protection(ha, stat);
1353
1354 qla2x00_unlock_nvram_access(ha);
2c96d8d0 1355 spin_unlock_irqrestore(&ha->hardware_lock, flags);
459c5378
AV		 1356
1357 return ret;
1358}
1359
1360int
7b867cf7 1361qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
459c5378
AV		 1362 uint32_t bytes)
1363{
1364 int ret;
1365 uint32_t i;
1366 uint32_t *dwptr;
7b867cf7 1367 struct qla_hw_data *ha = vha->hw;
459c5378
AV		 1368 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1369
1370 ret = QLA_SUCCESS;
1371
a9083016
GM		 1372 if (IS_QLA82XX(ha))
1373 return ret;
1374
459c5378
AV		 1375 /* Enable flash write. */
1376 WRT_REG_DWORD(&reg->ctrl_status,
1377 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1378 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1379
1380 /* Disable NVRAM write-protection. */
3a03eb79
AV		 1381 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1382 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
459c5378
AV		 1383
1384 /* Dword writes to flash. */
1385 dwptr = (uint32_t *)buf;
1386 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1387 ret = qla24xx_write_flash_dword(ha,
3a03eb79 1388 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
459c5378 1389 if (ret != QLA_SUCCESS) {
7c3df132 1390 ql_dbg(ql_dbg_user, vha, 0x709a,
7640335e 1391 "Unable to program nvram address=%x data=%x.\n",
7c3df132 1392 naddr, *dwptr);
459c5378
AV		 1393 break;
1394 }
1395 }
1396
1397 /* Enable NVRAM write-protection. */
3a03eb79 1398 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
459c5378
AV		 1399
1400 /* Disable flash write. */
1401 WRT_REG_DWORD(&reg->ctrl_status,
1402 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1403 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1404
459c5378
AV		 1405 return ret;
1406}
f6df144c 1407
c3a2f0df 1408uint8_t *
7b867cf7 1409qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1410 uint32_t bytes)
1411{
1412 uint32_t i;
1413 uint32_t *dwptr;
7b867cf7 1414 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1415
1416 /* Dword reads to flash. */
1417 dwptr = (uint32_t *)buf;
1418 for (i = 0; i < bytes >> 2; i++, naddr++)
1419 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
3a03eb79 1420 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
c3a2f0df
AV		 1421
1422 return buf;
1423}
1424
1425int
7b867cf7 1426qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
c3a2f0df
AV		 1427 uint32_t bytes)
1428{
7b867cf7 1429 struct qla_hw_data *ha = vha->hw;
2c96d8d0
AV		 1430#define RMW_BUFFER_SIZE (64 * 1024)
1431 uint8_t *dbuf;
1432
1433 dbuf = vmalloc(RMW_BUFFER_SIZE);
1434 if (!dbuf)
1435 return QLA_MEMORY_ALLOC_FAILED;
7b867cf7 1436 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1437 RMW_BUFFER_SIZE);
1438 memcpy(dbuf + (naddr << 2), buf, bytes);
7b867cf7 1439 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
2c96d8d0
AV		 1440 RMW_BUFFER_SIZE);
1441 vfree(dbuf);
1442
1443 return QLA_SUCCESS;
c3a2f0df 1444}
f6df144c
AV		 1445
1446static inline void
7b867cf7 1447qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c
AV		 1448{
1449 if (IS_QLA2322(ha)) {
1450 /* Flip all colors. */
1451 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1452 /* Turn off. */
1453 ha->beacon_color_state = 0;
1454 *pflags = GPIO_LED_ALL_OFF;
1455 } else {
1456 /* Turn on. */
1457 ha->beacon_color_state = QLA_LED_ALL_ON;
1458 *pflags = GPIO_LED_RGA_ON;
1459 }
1460 } else {
1461 /* Flip green led only. */
1462 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1463 /* Turn off. */
1464 ha->beacon_color_state = 0;
1465 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1466 } else {
1467 /* Turn on. */
1468 ha->beacon_color_state = QLA_LED_GRN_ON;
1469 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1470 }
1471 }
1472}
1473
948882f6
AV		 1474#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1475
f6df144c 1476void
7b867cf7 1477qla2x00_beacon_blink(struct scsi_qla_host *vha)
f6df144c
AV		 1478{
1479 uint16_t gpio_enable;
1480 uint16_t gpio_data;
1481 uint16_t led_color = 0;
1482 unsigned long flags;
7b867cf7 1483 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1484 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1485
a9083016
GM		 1486 if (IS_QLA82XX(ha))
1487 return;
1488
f6df144c
AV		 1489 spin_lock_irqsave(&ha->hardware_lock, flags);
1490
1491 /* Save the Original GPIOE. */
1492 if (ha->pio_address) {
948882f6
AV		 1493 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1494 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c
AV		 1495 } else {
1496 gpio_enable = RD_REG_WORD(&reg->gpioe);
1497 gpio_data = RD_REG_WORD(&reg->gpiod);
1498 }
1499
1500 /* Set the modified gpio_enable values */
1501 gpio_enable |= GPIO_LED_MASK;
1502
1503 if (ha->pio_address) {
948882f6 1504 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c
AV		 1505 } else {
1506 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1507 RD_REG_WORD(&reg->gpioe);
1508 }
1509
1510 qla2x00_flip_colors(ha, &led_color);
1511
1512 /* Clear out any previously set LED color. */
1513 gpio_data &= ~GPIO_LED_MASK;
1514
1515 /* Set the new input LED color to GPIOD. */
1516 gpio_data |= led_color;
1517
1518 /* Set the modified gpio_data values */
1519 if (ha->pio_address) {
948882f6 1520 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c
AV		 1521 } else {
1522 WRT_REG_WORD(&reg->gpiod, gpio_data);
1523 RD_REG_WORD(&reg->gpiod);
1524 }
1525
1526 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1527}
1528
1529int
7b867cf7 1530qla2x00_beacon_on(struct scsi_qla_host *vha)
f6df144c
AV		 1531{
1532 uint16_t gpio_enable;
1533 uint16_t gpio_data;
1534 unsigned long flags;
7b867cf7 1535 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1536 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1537
1538 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1539 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1540
7b867cf7 1541 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
7c3df132 1542 ql_log(ql_log_warn, vha, 0x709b,
f6df144c
AV		 1543 "Unable to update fw options (beacon on).\n");
1544 return QLA_FUNCTION_FAILED;
1545 }
1546
f6df144c
AV		 1547 /* Turn off LEDs. */
1548 spin_lock_irqsave(&ha->hardware_lock, flags);
1549 if (ha->pio_address) {
948882f6
AV		 1550 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1551 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
f6df144c
AV		 1552 } else {
1553 gpio_enable = RD_REG_WORD(&reg->gpioe);
1554 gpio_data = RD_REG_WORD(&reg->gpiod);
1555 }
1556 gpio_enable |= GPIO_LED_MASK;
1557
1558 /* Set the modified gpio_enable values. */
1559 if (ha->pio_address) {
948882f6 1560 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
f6df144c
AV		 1561 } else {
1562 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1563 RD_REG_WORD(&reg->gpioe);
1564 }
1565
1566 /* Clear out previously set LED colour. */
1567 gpio_data &= ~GPIO_LED_MASK;
1568 if (ha->pio_address) {
948882f6 1569 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
f6df144c
AV		 1570 } else {
1571 WRT_REG_WORD(&reg->gpiod, gpio_data);
1572 RD_REG_WORD(&reg->gpiod);
1573 }
1574 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1575
1576 /*
1577 * Let the per HBA timer kick off the blinking process based on
1578 * the following flags. No need to do anything else now.
1579 */
1580 ha->beacon_blink_led = 1;
1581 ha->beacon_color_state = 0;
1582
1583 return QLA_SUCCESS;
1584}
1585
1586int
7b867cf7 1587qla2x00_beacon_off(struct scsi_qla_host *vha)
f6df144c
AV		 1588{
1589 int rval = QLA_SUCCESS;
7b867cf7 1590 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1591
1592 ha->beacon_blink_led = 0;
1593
1594 /* Set the on flag so when it gets flipped it will be off. */
1595 if (IS_QLA2322(ha))
1596 ha->beacon_color_state = QLA_LED_ALL_ON;
1597 else
1598 ha->beacon_color_state = QLA_LED_GRN_ON;
1599
7b867cf7 1600 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
f6df144c
AV		 1601
1602 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1603 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1604
7b867cf7 1605 rval = qla2x00_set_fw_options(vha, ha->fw_options);
f6df144c 1606 if (rval != QLA_SUCCESS)
7c3df132 1607 ql_log(ql_log_warn, vha, 0x709c,
f6df144c
AV		 1608 "Unable to update fw options (beacon off).\n");
1609 return rval;
1610}
1611
1612
1613static inline void
7b867cf7 1614qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
f6df144c
AV		 1615{
1616 /* Flip all colors. */
1617 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1618 /* Turn off. */
1619 ha->beacon_color_state = 0;
1620 *pflags = 0;
1621 } else {
1622 /* Turn on. */
1623 ha->beacon_color_state = QLA_LED_ALL_ON;
1624 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1625 }
1626}
1627
1628void
7b867cf7 1629qla24xx_beacon_blink(struct scsi_qla_host *vha)
f6df144c
AV		 1630{
1631 uint16_t led_color = 0;
1632 uint32_t gpio_data;
1633 unsigned long flags;
7b867cf7 1634 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1635 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1636
1637 /* Save the Original GPIOD. */
1638 spin_lock_irqsave(&ha->hardware_lock, flags);
1639 gpio_data = RD_REG_DWORD(&reg->gpiod);
1640
1641 /* Enable the gpio_data reg for update. */
1642 gpio_data |= GPDX_LED_UPDATE_MASK;
1643
1644 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1645 gpio_data = RD_REG_DWORD(&reg->gpiod);
1646
1647 /* Set the color bits. */
1648 qla24xx_flip_colors(ha, &led_color);
1649
1650 /* Clear out any previously set LED color. */
1651 gpio_data &= ~GPDX_LED_COLOR_MASK;
1652
1653 /* Set the new input LED color to GPIOD. */
1654 gpio_data |= led_color;
1655
1656 /* Set the modified gpio_data values. */
1657 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1658 gpio_data = RD_REG_DWORD(&reg->gpiod);
1659 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1660}
1661
6246b8a1
GM		 1662void
1663qla83xx_beacon_blink(struct scsi_qla_host *vha)
1664{
1665 uint32_t led_select_value;
1666 struct qla_hw_data *ha = vha->hw;
1667 uint16_t led_cfg[6];
1668 uint16_t orig_led_cfg[6];
1669
1670 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha))
1671 return;
1672
1673 if (IS_QLA2031(ha) && ha->beacon_blink_led) {
1674 if (ha->flags.port0)
1675 led_select_value = 0x00201320;
1676 else
1677 led_select_value = 0x00201328;
1678
1679 qla83xx_write_remote_reg(vha, led_select_value, 0x40002000);
1680 qla83xx_write_remote_reg(vha, led_select_value + 4, 0x40002000);
1681 msleep(1000);
1682 qla83xx_write_remote_reg(vha, led_select_value, 0x40004000);
1683 qla83xx_write_remote_reg(vha, led_select_value + 4, 0x40004000);
1684 } else if ((IS_QLA8031(ha) || IS_QLA81XX(ha)) && ha->beacon_blink_led) {
1685 int rval;
1686
1687 /* Save Current */
1688 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1689 /* Do the blink */
1690 if (rval == QLA_SUCCESS) {
1691 if (IS_QLA81XX(ha)) {
1692 led_cfg[0] = 0x4000;
1693 led_cfg[1] = 0x2000;
1694 led_cfg[2] = 0;
1695 led_cfg[3] = 0;
1696 led_cfg[4] = 0;
1697 led_cfg[5] = 0;
1698 } else {
1699 led_cfg[0] = 0x4000;
1700 led_cfg[1] = 0x4000;
1701 led_cfg[2] = 0x4000;
1702 led_cfg[3] = 0x2000;
1703 led_cfg[4] = 0;
1704 led_cfg[5] = 0x2000;
1705 }
1706 rval = qla81xx_set_led_config(vha, led_cfg);
1707 msleep(1000);
1708 if (IS_QLA81XX(ha)) {
1709 led_cfg[0] = 0x4000;
1710 led_cfg[1] = 0x2000;
1711 led_cfg[2] = 0;
1712 } else {
1713 led_cfg[0] = 0x4000;
1714 led_cfg[1] = 0x2000;
1715 led_cfg[2] = 0x4000;
1716 led_cfg[3] = 0x4000;
1717 led_cfg[4] = 0;
1718 led_cfg[5] = 0x2000;
1719 }
1720 rval = qla81xx_set_led_config(vha, led_cfg);
1721 }
1722 /* On exit, restore original (presumes no status change) */
1723 qla81xx_set_led_config(vha, orig_led_cfg);
1724 }
1725}
1726
f6df144c 1727int
7b867cf7 1728qla24xx_beacon_on(struct scsi_qla_host *vha)
f6df144c
AV		 1729{
1730 uint32_t gpio_data;
1731 unsigned long flags;
7b867cf7 1732 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1733 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1734
a9083016
GM		 1735 if (IS_QLA82XX(ha))
1736 return QLA_SUCCESS;
1737
6246b8a1
GM		 1738 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1739 goto skip_gpio; /* let blink handle it */
1740
f6df144c
AV		 1741 if (ha->beacon_blink_led == 0) {
1742 /* Enable firmware for update */
1743 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1744
7b867cf7 1745 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
f6df144c
AV		 1746 return QLA_FUNCTION_FAILED;
1747
7b867cf7 1748 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
f6df144c 1749 QLA_SUCCESS) {
7c3df132 1750 ql_log(ql_log_warn, vha, 0x7009,
f6df144c
AV		 1751 "Unable to update fw options (beacon on).\n");
1752 return QLA_FUNCTION_FAILED;
1753 }
1754
6246b8a1
GM		 1755 if (IS_QLA2031(ha))
1756 goto skip_gpio;
1757
f6df144c
AV		 1758 spin_lock_irqsave(&ha->hardware_lock, flags);
1759 gpio_data = RD_REG_DWORD(&reg->gpiod);
1760
1761 /* Enable the gpio_data reg for update. */
1762 gpio_data |= GPDX_LED_UPDATE_MASK;
1763 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1764 RD_REG_DWORD(&reg->gpiod);
1765
1766 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1767 }
1768
1769 /* So all colors blink together. */
1770 ha->beacon_color_state = 0;
1771
6246b8a1 1772skip_gpio:
f6df144c
AV		 1773 /* Let the per HBA timer kick off the blinking process. */
1774 ha->beacon_blink_led = 1;
1775
1776 return QLA_SUCCESS;
1777}
1778
1779int
7b867cf7 1780qla24xx_beacon_off(struct scsi_qla_host *vha)
f6df144c
AV		 1781{
1782 uint32_t gpio_data;
1783 unsigned long flags;
7b867cf7 1784 struct qla_hw_data *ha = vha->hw;
f6df144c
AV		 1785 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1786
a9083016
GM		 1787 if (IS_QLA82XX(ha))
1788 return QLA_SUCCESS;
1789
f6df144c 1790 ha->beacon_blink_led = 0;
6246b8a1
GM		 1791
1792 if (IS_QLA2031(ha))
1793 goto set_fw_options;
1794
1795 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1796 return QLA_SUCCESS;
1797
f6df144c
AV		 1798 ha->beacon_color_state = QLA_LED_ALL_ON;
1799
7b867cf7 1800 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
f6df144c
AV		 1801
1802 /* Give control back to firmware. */
1803 spin_lock_irqsave(&ha->hardware_lock, flags);
1804 gpio_data = RD_REG_DWORD(&reg->gpiod);
1805
1806 /* Disable the gpio_data reg for update. */
1807 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1808 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1809 RD_REG_DWORD(&reg->gpiod);
1810 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1811
6246b8a1 1812set_fw_options:
f6df144c
AV		 1813 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1814
7b867cf7 1815 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
7c3df132
SK		 1816 ql_log(ql_log_warn, vha, 0x704d,
1817 "Unable to update fw options (beacon on).\n");
f6df144c
AV		 1818 return QLA_FUNCTION_FAILED;
1819 }
1820
7b867cf7 1821 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
7c3df132
SK		 1822 ql_log(ql_log_warn, vha, 0x704e,
1823 "Unable to update fw options (beacon on).\n");
f6df144c
AV		 1824 return QLA_FUNCTION_FAILED;
1825 }
1826
1827 return QLA_SUCCESS;
1828}
854165f4
AV		 1829
1830
1831/*
1832 * Flash support routines
1833 */
1834
1835/**
1836 * qla2x00_flash_enable() - Setup flash for reading and writing.
1837 * @ha: HA context
1838 */
1839static void
7b867cf7 1840qla2x00_flash_enable(struct qla_hw_data *ha)
854165f4
AV		 1841{
1842 uint16_t data;
1843 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1844
1845 data = RD_REG_WORD(&reg->ctrl_status);
1846 data |= CSR_FLASH_ENABLE;
1847 WRT_REG_WORD(&reg->ctrl_status, data);
1848 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1849}
1850
1851/**
1852 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1853 * @ha: HA context
1854 */
1855static void
7b867cf7 1856qla2x00_flash_disable(struct qla_hw_data *ha)
854165f4
AV		 1857{
1858 uint16_t data;
1859 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1860
1861 data = RD_REG_WORD(&reg->ctrl_status);
1862 data &= ~(CSR_FLASH_ENABLE);
1863 WRT_REG_WORD(&reg->ctrl_status, data);
1864 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1865}
1866
1867/**
1868 * qla2x00_read_flash_byte() - Reads a byte from flash
1869 * @ha: HA context
1870 * @addr: Address in flash to read
1871 *
1872 * A word is read from the chip, but, only the lower byte is valid.
1873 *
1874 * Returns the byte read from flash @addr.
1875 */
1876static uint8_t
7b867cf7 1877qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
854165f4
AV		 1878{
1879 uint16_t data;
1880 uint16_t bank_select;
1881 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1882
1883 bank_select = RD_REG_WORD(&reg->ctrl_status);
1884
1885 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1886 /* Specify 64K address range: */
1887 /* clear out Module Select and Flash Address bits [19:16]. */
1888 bank_select &= ~0xf8;
1889 bank_select |= addr >> 12 & 0xf0;
1890 bank_select |= CSR_FLASH_64K_BANK;
1891 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1892 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1893
1894 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1895 data = RD_REG_WORD(&reg->flash_data);
1896
1897 return (uint8_t)data;
1898 }
1899
1900 /* Setup bit 16 of flash address. */
1901 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1902 bank_select |= CSR_FLASH_64K_BANK;
1903 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1904 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1905 } else if (((addr & BIT_16) == 0) &&
1906 (bank_select & CSR_FLASH_64K_BANK)) {
1907 bank_select &= ~(CSR_FLASH_64K_BANK);
1908 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1909 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1910 }
1911
1912 /* Always perform IO mapped accesses to the FLASH registers. */
1913 if (ha->pio_address) {
1914 uint16_t data2;
1915
948882f6 1916 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
854165f4 1917 do {
948882f6 1918 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4
AV		 1919 barrier();
1920 cpu_relax();
948882f6 1921 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
854165f4
AV		 1922 } while (data != data2);
1923 } else {
1924 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1925 data = qla2x00_debounce_register(&reg->flash_data);
1926 }
1927
1928 return (uint8_t)data;
1929}
1930
1931/**
1932 * qla2x00_write_flash_byte() - Write a byte to flash
1933 * @ha: HA context
1934 * @addr: Address in flash to write
1935 * @data: Data to write
1936 */
1937static void
7b867cf7 1938qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
854165f4
AV		 1939{
1940 uint16_t bank_select;
1941 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1942
1943 bank_select = RD_REG_WORD(&reg->ctrl_status);
1944 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1945 /* Specify 64K address range: */
1946 /* clear out Module Select and Flash Address bits [19:16]. */
1947 bank_select &= ~0xf8;
1948 bank_select |= addr >> 12 & 0xf0;
1949 bank_select |= CSR_FLASH_64K_BANK;
1950 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1951 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1952
1953 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1954 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1955 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1956 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1957
1958 return;
1959 }
1960
1961 /* Setup bit 16 of flash address. */
1962 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1963 bank_select |= CSR_FLASH_64K_BANK;
1964 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1965 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1966 } else if (((addr & BIT_16) == 0) &&
1967 (bank_select & CSR_FLASH_64K_BANK)) {
1968 bank_select &= ~(CSR_FLASH_64K_BANK);
1969 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1970 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1971 }
1972
1973 /* Always perform IO mapped accesses to the FLASH registers. */
1974 if (ha->pio_address) {
948882f6
AV		 1975 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1976 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
854165f4
AV		 1977 } else {
1978 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1979 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1980 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1981 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1982 }
1983}
1984
1985/**
1986 * qla2x00_poll_flash() - Polls flash for completion.
1987 * @ha: HA context
1988 * @addr: Address in flash to poll
1989 * @poll_data: Data to be polled
1990 * @man_id: Flash manufacturer ID
1991 * @flash_id: Flash ID
1992 *
1993 * This function polls the device until bit 7 of what is read matches data
1994 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1995 * out (a fatal error). The flash book recommeds reading bit 7 again after
1996 * reading bit 5 as a 1.
1997 *
1998 * Returns 0 on success, else non-zero.
1999 */
2000static int
7b867cf7 2001qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
854165f4
AV		 2002 uint8_t man_id, uint8_t flash_id)
2003{
2004 int status;
2005 uint8_t flash_data;
2006 uint32_t cnt;
2007
2008 status = 1;
2009
2010 /* Wait for 30 seconds for command to finish. */
2011 poll_data &= BIT_7;
2012 for (cnt = 3000000; cnt; cnt--) {
2013 flash_data = qla2x00_read_flash_byte(ha, addr);
2014 if ((flash_data & BIT_7) == poll_data) {
2015 status = 0;
2016 break;
2017 }
2018
2019 if (man_id != 0x40 && man_id != 0xda) {
2020 if ((flash_data & BIT_5) && cnt > 2)
2021 cnt = 2;
2022 }
2023 udelay(10);
2024 barrier();
40a2e34a 2025 cond_resched();
854165f4
AV		 2026 }
2027 return status;
2028}
2029
854165f4
AV		 2030/**
2031 * qla2x00_program_flash_address() - Programs a flash address
2032 * @ha: HA context
2033 * @addr: Address in flash to program
2034 * @data: Data to be written in flash
2035 * @man_id: Flash manufacturer ID
2036 * @flash_id: Flash ID
2037 *
2038 * Returns 0 on success, else non-zero.
2039 */
2040static int
7b867cf7
AC		 2041qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2042 uint8_t data, uint8_t man_id, uint8_t flash_id)
854165f4
AV		 2043{
2044 /* Write Program Command Sequence. */
2045 if (IS_OEM_001(ha)) {
2046 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2047 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2048 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2049 qla2x00_write_flash_byte(ha, addr, data);
2050 } else {
2051 if (man_id == 0xda && flash_id == 0xc1) {
2052 qla2x00_write_flash_byte(ha, addr, data);
2053 if (addr & 0x7e)
2054 return 0;
2055 } else {
2056 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2057 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2058 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2059 qla2x00_write_flash_byte(ha, addr, data);
2060 }
2061 }
2062
2063 udelay(150);
2064
2065 /* Wait for write to complete. */
2066 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2067}
2068
2069/**
2070 * qla2x00_erase_flash() - Erase the flash.
2071 * @ha: HA context
2072 * @man_id: Flash manufacturer ID
2073 * @flash_id: Flash ID
2074 *
2075 * Returns 0 on success, else non-zero.
2076 */
2077static int
7b867cf7 2078qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
854165f4
AV		 2079{
2080 /* Individual Sector Erase Command Sequence */
2081 if (IS_OEM_001(ha)) {
2082 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2083 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2084 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2085 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2086 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2087 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2088 } else {
2089 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2090 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2091 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2092 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2093 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2094 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2095 }
2096
2097 udelay(150);
2098
2099 /* Wait for erase to complete. */
2100 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2101}
2102
2103/**
2104 * qla2x00_erase_flash_sector() - Erase a flash sector.
2105 * @ha: HA context
2106 * @addr: Flash sector to erase
2107 * @sec_mask: Sector address mask
2108 * @man_id: Flash manufacturer ID
2109 * @flash_id: Flash ID
2110 *
2111 * Returns 0 on success, else non-zero.
2112 */
2113static int
7b867cf7 2114qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
854165f4
AV		 2115 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2116{
2117 /* Individual Sector Erase Command Sequence */
2118 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2119 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2120 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2121 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2122 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2123 if (man_id == 0x1f && flash_id == 0x13)
2124 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2125 else
2126 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2127
2128 udelay(150);
2129
2130 /* Wait for erase to complete. */
2131 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2132}
2133
2134/**
2135 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2136 * @man_id: Flash manufacturer ID
2137 * @flash_id: Flash ID
2138 */
2139static void
7b867cf7 2140qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
854165f4
AV		 2141 uint8_t *flash_id)
2142{
2143 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2144 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2145 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2146 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2147 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2148 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2149 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2150 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2151}
2152
30c47662 2153static void
7b867cf7
AC		 2154qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2155 uint32_t saddr, uint32_t length)
30c47662
AV		 2156{
2157 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2158 uint32_t midpoint, ilength;
2159 uint8_t data;
2160
2161 midpoint = length / 2;
2162
2163 WRT_REG_WORD(&reg->nvram, 0);
2164 RD_REG_WORD(&reg->nvram);
2165 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2166 if (ilength == midpoint) {
2167 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2168 RD_REG_WORD(&reg->nvram);
2169 }
2170 data = qla2x00_read_flash_byte(ha, saddr);
2171 if (saddr % 100)
2172 udelay(10);
2173 *tmp_buf = data;
40a2e34a 2174 cond_resched();
30c47662
AV		 2175 }
2176}
854165f4
AV		 2177
2178static inline void
7b867cf7 2179qla2x00_suspend_hba(struct scsi_qla_host *vha)
854165f4
AV		 2180{
2181 int cnt;
2182 unsigned long flags;
7b867cf7 2183 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 2184 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2185
2186 /* Suspend HBA. */
7b867cf7 2187 scsi_block_requests(vha->host);
fd34f556 2188 ha->isp_ops->disable_intrs(ha);
854165f4
AV		 2189 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2190
2191 /* Pause RISC. */
2192 spin_lock_irqsave(&ha->hardware_lock, flags);
2193 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2194 RD_REG_WORD(&reg->hccr);
2195 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2196 for (cnt = 0; cnt < 30000; cnt++) {
2197 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
2198 break;
2199 udelay(100);
2200 }
2201 } else {
2202 udelay(10);
2203 }
2204 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2205}
2206
2207static inline void
7b867cf7 2208qla2x00_resume_hba(struct scsi_qla_host *vha)
854165f4 2209{
7b867cf7
AC		 2210 struct qla_hw_data *ha = vha->hw;
2211
854165f4
AV		 2212 /* Resume HBA. */
2213 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7
AC		 2214 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2215 qla2xxx_wake_dpc(vha);
2533cf67 2216 qla2x00_wait_for_chip_reset(vha);
7b867cf7 2217 scsi_unblock_requests(vha->host);
854165f4
AV		 2218}
2219
2220uint8_t *
7b867cf7 2221qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 2222 uint32_t offset, uint32_t length)
2223{
854165f4
AV		 2224 uint32_t addr, midpoint;
2225 uint8_t *data;
7b867cf7 2226 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 2227 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2228
2229 /* Suspend HBA. */
7b867cf7 2230 qla2x00_suspend_hba(vha);
854165f4
AV		 2231
2232 /* Go with read. */
854165f4
AV		 2233 midpoint = ha->optrom_size / 2;
2234
2235 qla2x00_flash_enable(ha);
2236 WRT_REG_WORD(&reg->nvram, 0);
2237 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2238 for (addr = offset, data = buf; addr < length; addr++, data++) {
2239 if (addr == midpoint) {
2240 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2241 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2242 }
2243
2244 *data = qla2x00_read_flash_byte(ha, addr);
2245 }
2246 qla2x00_flash_disable(ha);
854165f4
AV		 2247
2248 /* Resume HBA. */
7b867cf7 2249 qla2x00_resume_hba(vha);
854165f4
AV		 2250
2251 return buf;
2252}
2253
2254int
7b867cf7 2255qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 2256 uint32_t offset, uint32_t length)
2257{
2258
2259 int rval;
854165f4
AV		 2260 uint8_t man_id, flash_id, sec_number, data;
2261 uint16_t wd;
2262 uint32_t addr, liter, sec_mask, rest_addr;
7b867cf7 2263 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 2264 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2265
2266 /* Suspend HBA. */
7b867cf7 2267 qla2x00_suspend_hba(vha);
854165f4
AV		 2268
2269 rval = QLA_SUCCESS;
2270 sec_number = 0;
2271
2272 /* Reset ISP chip. */
854165f4
AV		 2273 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2274 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2275
2276 /* Go with write. */
2277 qla2x00_flash_enable(ha);
2278 do { /* Loop once to provide quick error exit */
2279 /* Structure of flash memory based on manufacturer */
2280 if (IS_OEM_001(ha)) {
2281 /* OEM variant with special flash part. */
2282 man_id = flash_id = 0;
2283 rest_addr = 0xffff;
2284 sec_mask = 0x10000;
2285 goto update_flash;
2286 }
2287 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2288 switch (man_id) {
2289 case 0x20: /* ST flash. */
2290 if (flash_id == 0xd2 || flash_id == 0xe3) {
2291 /*
2292 * ST m29w008at part - 64kb sector size with
2293 * 32kb,8kb,8kb,16kb sectors at memory address
2294 * 0xf0000.
2295 */
2296 rest_addr = 0xffff;
2297 sec_mask = 0x10000;
2298 break;
2299 }
2300 /*
2301 * ST m29w010b part - 16kb sector size
2302 * Default to 16kb sectors
2303 */
2304 rest_addr = 0x3fff;
2305 sec_mask = 0x1c000;
2306 break;
2307 case 0x40: /* Mostel flash. */
2308 /* Mostel v29c51001 part - 512 byte sector size. */
2309 rest_addr = 0x1ff;
2310 sec_mask = 0x1fe00;
2311 break;
2312 case 0xbf: /* SST flash. */
2313 /* SST39sf10 part - 4kb sector size. */
2314 rest_addr = 0xfff;
2315 sec_mask = 0x1f000;
2316 break;
2317 case 0xda: /* Winbond flash. */
2318 /* Winbond W29EE011 part - 256 byte sector size. */
2319 rest_addr = 0x7f;
2320 sec_mask = 0x1ff80;
2321 break;
2322 case 0xc2: /* Macronix flash. */
2323 /* 64k sector size. */
2324 if (flash_id == 0x38 || flash_id == 0x4f) {
2325 rest_addr = 0xffff;
2326 sec_mask = 0x10000;
2327 break;
2328 }
2329 /* Fall through... */
2330
2331 case 0x1f: /* Atmel flash. */
2332 /* 512k sector size. */
2333 if (flash_id == 0x13) {
2334 rest_addr = 0x7fffffff;
2335 sec_mask = 0x80000000;
2336 break;
2337 }
2338 /* Fall through... */
2339
2340 case 0x01: /* AMD flash. */
2341 if (flash_id == 0x38 || flash_id == 0x40 ||
2342 flash_id == 0x4f) {
2343 /* Am29LV081 part - 64kb sector size. */
2344 /* Am29LV002BT part - 64kb sector size. */
2345 rest_addr = 0xffff;
2346 sec_mask = 0x10000;
2347 break;
2348 } else if (flash_id == 0x3e) {
2349 /*
2350 * Am29LV008b part - 64kb sector size with
2351 * 32kb,8kb,8kb,16kb sector at memory address
2352 * h0xf0000.
2353 */
2354 rest_addr = 0xffff;
2355 sec_mask = 0x10000;
2356 break;
2357 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2358 /*
2359 * Am29LV010 part or AM29f010 - 16kb sector
2360 * size.
2361 */
2362 rest_addr = 0x3fff;
2363 sec_mask = 0x1c000;
2364 break;
2365 } else if (flash_id == 0x6d) {
2366 /* Am29LV001 part - 8kb sector size. */
2367 rest_addr = 0x1fff;
2368 sec_mask = 0x1e000;
2369 break;
2370 }
2371 default:
2372 /* Default to 16 kb sector size. */
2373 rest_addr = 0x3fff;
2374 sec_mask = 0x1c000;
2375 break;
2376 }
2377
2378update_flash:
2379 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2380 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2381 rval = QLA_FUNCTION_FAILED;
2382 break;
2383 }
2384 }
2385
2386 for (addr = offset, liter = 0; liter < length; liter++,
2387 addr++) {
2388 data = buf[liter];
2389 /* Are we at the beginning of a sector? */
2390 if ((addr & rest_addr) == 0) {
2391 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2392 if (addr >= 0x10000UL) {
2393 if (((addr >> 12) & 0xf0) &&
2394 ((man_id == 0x01 &&
2395 flash_id == 0x3e) ||
2396 (man_id == 0x20 &&
2397 flash_id == 0xd2))) {
2398 sec_number++;
2399 if (sec_number == 1) {
2400 rest_addr =
2401 0x7fff;
2402 sec_mask =
2403 0x18000;
2404 } else if (
2405 sec_number == 2 ||
2406 sec_number == 3) {
2407 rest_addr =
2408 0x1fff;
2409 sec_mask =
2410 0x1e000;
2411 } else if (
2412 sec_number == 4) {
2413 rest_addr =
2414 0x3fff;
2415 sec_mask =
2416 0x1c000;
2417 }
2418 }
2419 }
2420 } else if (addr == ha->optrom_size / 2) {
2421 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2422 RD_REG_WORD(&reg->nvram);
2423 }
2424
2425 if (flash_id == 0xda && man_id == 0xc1) {
2426 qla2x00_write_flash_byte(ha, 0x5555,
2427 0xaa);
2428 qla2x00_write_flash_byte(ha, 0x2aaa,
2429 0x55);
2430 qla2x00_write_flash_byte(ha, 0x5555,
2431 0xa0);
2432 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2433 /* Then erase it */
2434 if (qla2x00_erase_flash_sector(ha,
2435 addr, sec_mask, man_id,
2436 flash_id)) {
2437 rval = QLA_FUNCTION_FAILED;
2438 break;
2439 }
2440 if (man_id == 0x01 && flash_id == 0x6d)
2441 sec_number++;
2442 }
2443 }
2444
2445 if (man_id == 0x01 && flash_id == 0x6d) {
2446 if (sec_number == 1 &&
2447 addr == (rest_addr - 1)) {
2448 rest_addr = 0x0fff;
2449 sec_mask = 0x1f000;
2450 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2451 rest_addr = 0x3fff;
2452 sec_mask = 0x1c000;
2453 }
2454 }
2455
2456 if (qla2x00_program_flash_address(ha, addr, data,
2457 man_id, flash_id)) {
2458 rval = QLA_FUNCTION_FAILED;
2459 break;
2460 }
40a2e34a 2461 cond_resched();
854165f4
AV		 2462 }
2463 } while (0);
2464 qla2x00_flash_disable(ha);
854165f4
AV		 2465
2466 /* Resume HBA. */
7b867cf7 2467 qla2x00_resume_hba(vha);
854165f4
AV		 2468
2469 return rval;
2470}
2471
2472uint8_t *
7b867cf7 2473qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 2474 uint32_t offset, uint32_t length)
2475{
7b867cf7
AC		 2476 struct qla_hw_data *ha = vha->hw;
2477
854165f4 2478 /* Suspend HBA. */
7b867cf7 2479 scsi_block_requests(vha->host);
854165f4
AV		 2480 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2481
2482 /* Go with read. */
7b867cf7 2483 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
854165f4
AV		 2484
2485 /* Resume HBA. */
2486 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2487 scsi_unblock_requests(vha->host);
854165f4
AV		 2488
2489 return buf;
2490}
2491
2492int
7b867cf7 2493qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
854165f4
AV		 2494 uint32_t offset, uint32_t length)
2495{
2496 int rval;
7b867cf7 2497 struct qla_hw_data *ha = vha->hw;
854165f4
AV		 2498
2499 /* Suspend HBA. */
7b867cf7 2500 scsi_block_requests(vha->host);
854165f4
AV		 2501 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2502
2503 /* Go with write. */
7b867cf7 2504 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
854165f4
AV		 2505 length >> 2);
2506
854165f4 2507 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
7b867cf7 2508 scsi_unblock_requests(vha->host);
854165f4
AV		 2509
2510 return rval;
2511}
30c47662 2512
338c9161 2513uint8_t *
7b867cf7 2514qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
338c9161
AV		 2515 uint32_t offset, uint32_t length)
2516{
2517 int rval;
2518 dma_addr_t optrom_dma;
2519 void *optrom;
2520 uint8_t *pbuf;
2521 uint32_t faddr, left, burst;
7b867cf7 2522 struct qla_hw_data *ha = vha->hw;
338c9161 2523
368bbe07
AV		 2524 if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2525 goto try_fast;
b7cc176c 2526 if (offset & 0xfff)
338c9161
AV		 2527 goto slow_read;
2528 if (length < OPTROM_BURST_SIZE)
2529 goto slow_read;
2530
368bbe07 2531try_fast:
338c9161
AV		 2532 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2533 &optrom_dma, GFP_KERNEL);
2534 if (!optrom) {
7c3df132
SK		 2535 ql_log(ql_log_warn, vha, 0x00cc,
2536 "Unable to allocate memory for optrom burst read (%x KB).\n",
2537 OPTROM_BURST_SIZE / 1024);
338c9161
AV		 2538 goto slow_read;
2539 }
2540
2541 pbuf = buf;
2542 faddr = offset >> 2;
2543 left = length >> 2;
2544 burst = OPTROM_BURST_DWORDS;
2545 while (left != 0) {
2546 if (burst > left)
2547 burst = left;
2548
7b867cf7 2549 rval = qla2x00_dump_ram(vha, optrom_dma,
3a03eb79 2550 flash_data_addr(ha, faddr), burst);
338c9161 2551 if (rval) {
7c3df132
SK		 2552 ql_log(ql_log_warn, vha, 0x00f5,
2553 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2554 rval, flash_data_addr(ha, faddr),
875baf3c 2555 (unsigned long long)optrom_dma);
7c3df132 2556 ql_log(ql_log_warn, vha, 0x00f6,
338c9161
AV		 2557 "Reverting to slow-read.\n");
2558
2559 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2560 optrom, optrom_dma);
2561 goto slow_read;
2562 }
2563
2564 memcpy(pbuf, optrom, burst * 4);
2565
2566 left -= burst;
2567 faddr += burst;
2568 pbuf += burst * 4;
2569 }
2570
2571 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2572 optrom_dma);
2573
2574 return buf;
2575
2576slow_read:
7b867cf7 2577 return qla24xx_read_optrom_data(vha, buf, offset, length);
338c9161
AV		 2578}
2579
30c47662
AV		 2580/**
2581 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2582 * @ha: HA context
2583 * @pcids: Pointer to the FCODE PCI data structure
2584 *
2585 * The process of retrieving the FCODE version information is at best
2586 * described as interesting.
2587 *
2588 * Within the first 100h bytes of the image an ASCII string is present
2589 * which contains several pieces of information including the FCODE
2590 * version. Unfortunately it seems the only reliable way to retrieve
2591 * the version is by scanning for another sentinel within the string,
2592 * the FCODE build date:
2593 *
2594 * ... 2.00.02 10/17/02 ...
2595 *
2596 * Returns QLA_SUCCESS on successful retrieval of version.
2597 */
2598static void
7b867cf7 2599qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
30c47662
AV		 2600{
2601 int ret = QLA_FUNCTION_FAILED;
2602 uint32_t istart, iend, iter, vend;
2603 uint8_t do_next, rbyte, *vbyte;
2604
2605 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2606
2607 /* Skip the PCI data structure. */
2608 istart = pcids +
2609 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2610 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2611 iend = istart + 0x100;
2612 do {
2613 /* Scan for the sentinel date string...eeewww. */
2614 do_next = 0;
2615 iter = istart;
2616 while ((iter < iend) && !do_next) {
2617 iter++;
2618 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2619 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2620 '/')
2621 do_next++;
2622 else if (qla2x00_read_flash_byte(ha,
2623 iter + 3) == '/')
2624 do_next++;
2625 }
2626 }
2627 if (!do_next)
2628 break;
2629
2630 /* Backtrack to previous ' ' (space). */
2631 do_next = 0;
2632 while ((iter > istart) && !do_next) {
2633 iter--;
2634 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2635 do_next++;
2636 }
2637 if (!do_next)
2638 break;
2639
2640 /*
2641 * Mark end of version tag, and find previous ' ' (space) or
2642 * string length (recent FCODE images -- major hack ahead!!!).
2643 */
2644 vend = iter - 1;
2645 do_next = 0;
2646 while ((iter > istart) && !do_next) {
2647 iter--;
2648 rbyte = qla2x00_read_flash_byte(ha, iter);
2649 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2650 do_next++;
2651 }
2652 if (!do_next)
2653 break;
2654
2655 /* Mark beginning of version tag, and copy data. */
2656 iter++;
2657 if ((vend - iter) &&
2658 ((vend - iter) < sizeof(ha->fcode_revision))) {
2659 vbyte = ha->fcode_revision;
2660 while (iter <= vend) {
2661 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2662 iter++;
2663 }
2664 ret = QLA_SUCCESS;
2665 }
2666 } while (0);
2667
2668 if (ret != QLA_SUCCESS)
2669 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2670}
2671
2672int
7b867cf7 2673qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2674{
2675 int ret = QLA_SUCCESS;
2676 uint8_t code_type, last_image;
2677 uint32_t pcihdr, pcids;
2678 uint8_t *dbyte;
2679 uint16_t *dcode;
7b867cf7 2680 struct qla_hw_data *ha = vha->hw;
30c47662
AV		 2681
2682 if (!ha->pio_address || !mbuf)
2683 return QLA_FUNCTION_FAILED;
2684
2685 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2686 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2687 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2688 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2689
2690 qla2x00_flash_enable(ha);
2691
2692 /* Begin with first PCI expansion ROM header. */
2693 pcihdr = 0;
2694 last_image = 1;
2695 do {
2696 /* Verify PCI expansion ROM header. */
2697 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2698 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2699 /* No signature */
7c3df132
SK		 2700 ql_log(ql_log_fatal, vha, 0x0050,
2701 "No matching ROM signature.\n");
30c47662
AV		 2702 ret = QLA_FUNCTION_FAILED;
2703 break;
2704 }
2705
2706 /* Locate PCI data structure. */
2707 pcids = pcihdr +
2708 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2709 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2710
2711 /* Validate signature of PCI data structure. */
2712 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2713 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2714 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2715 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2716 /* Incorrect header. */
7c3df132
SK		 2717 ql_log(ql_log_fatal, vha, 0x0051,
2718 "PCI data struct not found pcir_adr=%x.\n", pcids);
30c47662
AV		 2719 ret = QLA_FUNCTION_FAILED;
2720 break;
2721 }
2722
2723 /* Read version */
2724 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2725 switch (code_type) {
2726 case ROM_CODE_TYPE_BIOS:
2727 /* Intel x86, PC-AT compatible. */
2728 ha->bios_revision[0] =
2729 qla2x00_read_flash_byte(ha, pcids + 0x12);
2730 ha->bios_revision[1] =
2731 qla2x00_read_flash_byte(ha, pcids + 0x13);
7c3df132
SK		 2732 ql_dbg(ql_dbg_init, vha, 0x0052,
2733 "Read BIOS %d.%d.\n",
2734 ha->bios_revision[1], ha->bios_revision[0]);
30c47662
AV		 2735 break;
2736 case ROM_CODE_TYPE_FCODE:
2737 /* Open Firmware standard for PCI (FCode). */
2738 /* Eeeewww... */
2739 qla2x00_get_fcode_version(ha, pcids);
2740 break;
2741 case ROM_CODE_TYPE_EFI:
2742 /* Extensible Firmware Interface (EFI). */
2743 ha->efi_revision[0] =
2744 qla2x00_read_flash_byte(ha, pcids + 0x12);
2745 ha->efi_revision[1] =
2746 qla2x00_read_flash_byte(ha, pcids + 0x13);
7c3df132
SK		 2747 ql_dbg(ql_dbg_init, vha, 0x0053,
2748 "Read EFI %d.%d.\n",
2749 ha->efi_revision[1], ha->efi_revision[0]);
30c47662
AV		 2750 break;
2751 default:
7c3df132
SK		 2752 ql_log(ql_log_warn, vha, 0x0054,
2753 "Unrecognized code type %x at pcids %x.\n",
2754 code_type, pcids);
30c47662
AV		 2755 break;
2756 }
2757
2758 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2759
2760 /* Locate next PCI expansion ROM. */
2761 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2762 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2763 } while (!last_image);
2764
2765 if (IS_QLA2322(ha)) {
2766 /* Read firmware image information. */
2767 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2768 dbyte = mbuf;
2769 memset(dbyte, 0, 8);
2770 dcode = (uint16_t *)dbyte;
2771
c00d8994 2772 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
30c47662 2773 8);
7c3df132
SK		 2774 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2775 "Dumping fw "
2776 "ver from flash:.\n");
2777 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2778 (uint8_t *)dbyte, 8);
30c47662
AV		 2779
2780 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2781 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2782 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2783 dcode[3] == 0)) {
7c3df132
SK		 2784 ql_log(ql_log_warn, vha, 0x0057,
2785 "Unrecognized fw revision at %x.\n",
2786 ha->flt_region_fw * 4);
30c47662
AV		 2787 } else {
2788 /* values are in big endian */
2789 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2790 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2791 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
7c3df132
SK		 2792 ql_dbg(ql_dbg_init, vha, 0x0058,
2793 "FW Version: "
2794 "%d.%d.%d.\n", ha->fw_revision[0],
2795 ha->fw_revision[1], ha->fw_revision[2]);
30c47662
AV		 2796 }
2797 }
2798
2799 qla2x00_flash_disable(ha);
2800
2801 return ret;
2802}
2803
2804int
7b867cf7 2805qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
30c47662
AV		 2806{
2807 int ret = QLA_SUCCESS;
2808 uint32_t pcihdr, pcids;
2809 uint32_t *dcode;
2810 uint8_t *bcode;
2811 uint8_t code_type, last_image;
2812 int i;
7b867cf7 2813 struct qla_hw_data *ha = vha->hw;
30c47662 2814
a9083016
GM		 2815 if (IS_QLA82XX(ha))
2816 return ret;
2817
30c47662
AV		 2818 if (!mbuf)
2819 return QLA_FUNCTION_FAILED;
2820
2821 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2822 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2823 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2824 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2825
2826 dcode = mbuf;
2827
2828 /* Begin with first PCI expansion ROM header. */
6315a5f8 2829 pcihdr = ha->flt_region_boot << 2;
30c47662
AV		 2830 last_image = 1;
2831 do {
2832 /* Verify PCI expansion ROM header. */
7b867cf7 2833 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
30c47662
AV		 2834 bcode = mbuf + (pcihdr % 4);
2835 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2836 /* No signature */
7c3df132
SK		 2837 ql_log(ql_log_fatal, vha, 0x0059,
2838 "No matching ROM signature.\n");
30c47662
AV		 2839 ret = QLA_FUNCTION_FAILED;
2840 break;
2841 }
2842
2843 /* Locate PCI data structure. */
2844 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2845
7b867cf7 2846 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
30c47662
AV		 2847 bcode = mbuf + (pcihdr % 4);
2848
2849 /* Validate signature of PCI data structure. */
2850 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2851 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2852 /* Incorrect header. */
7c3df132
SK		 2853 ql_log(ql_log_fatal, vha, 0x005a,
2854 "PCI data struct not found pcir_adr=%x.\n", pcids);
30c47662
AV		 2855 ret = QLA_FUNCTION_FAILED;
2856 break;
2857 }
2858
2859 /* Read version */
2860 code_type = bcode[0x14];
2861 switch (code_type) {
2862 case ROM_CODE_TYPE_BIOS:
2863 /* Intel x86, PC-AT compatible. */
2864 ha->bios_revision[0] = bcode[0x12];
2865 ha->bios_revision[1] = bcode[0x13];
7c3df132
SK		 2866 ql_dbg(ql_dbg_init, vha, 0x005b,
2867 "Read BIOS %d.%d.\n",
2868 ha->bios_revision[1], ha->bios_revision[0]);
30c47662
AV		 2869 break;
2870 case ROM_CODE_TYPE_FCODE:
2871 /* Open Firmware standard for PCI (FCode). */
2872 ha->fcode_revision[0] = bcode[0x12];
2873 ha->fcode_revision[1] = bcode[0x13];
7c3df132
SK		 2874 ql_dbg(ql_dbg_init, vha, 0x005c,
2875 "Read FCODE %d.%d.\n",
2876 ha->fcode_revision[1], ha->fcode_revision[0]);
30c47662
AV		 2877 break;
2878 case ROM_CODE_TYPE_EFI:
2879 /* Extensible Firmware Interface (EFI). */
2880 ha->efi_revision[0] = bcode[0x12];
2881 ha->efi_revision[1] = bcode[0x13];
7c3df132
SK		 2882 ql_dbg(ql_dbg_init, vha, 0x005d,
2883 "Read EFI %d.%d.\n",
2884 ha->efi_revision[1], ha->efi_revision[0]);
30c47662
AV		 2885 break;
2886 default:
7c3df132
SK		 2887 ql_log(ql_log_warn, vha, 0x005e,
2888 "Unrecognized code type %x at pcids %x.\n",
2889 code_type, pcids);
30c47662
AV		 2890 break;
2891 }
2892
2893 last_image = bcode[0x15] & BIT_7;
2894
2895 /* Locate next PCI expansion ROM. */
2896 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2897 } while (!last_image);
2898
2899 /* Read firmware image information. */
2900 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2901 dcode = mbuf;
2902
7b867cf7 2903 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
30c47662
AV		 2904 for (i = 0; i < 4; i++)
2905 dcode[i] = be32_to_cpu(dcode[i]);
2906
2907 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2908 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2909 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2910 dcode[3] == 0)) {
7c3df132
SK		 2911 ql_log(ql_log_warn, vha, 0x005f,
2912 "Unrecognized fw revision at %x.\n",
2913 ha->flt_region_fw * 4);
30c47662
AV		 2914 } else {
2915 ha->fw_revision[0] = dcode[0];
2916 ha->fw_revision[1] = dcode[1];
2917 ha->fw_revision[2] = dcode[2];
2918 ha->fw_revision[3] = dcode[3];
7c3df132
SK		 2919 ql_dbg(ql_dbg_init, vha, 0x0060,
2920 "Firmware revision %d.%d.%d.%d.\n",
2921 ha->fw_revision[0], ha->fw_revision[1],
2922 ha->fw_revision[2], ha->fw_revision[3]);
30c47662
AV		 2923 }
2924
0f2d962f
MI		 2925 /* Check for golden firmware and get version if available */
2926 if (!IS_QLA81XX(ha)) {
2927 /* Golden firmware is not present in non 81XX adapters */
2928 return ret;
2929 }
2930
2931 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
2932 dcode = mbuf;
2933 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
2934 ha->flt_region_gold_fw << 2, 32);
2935
2936 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
2937 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
7c3df132
SK		 2938 ql_log(ql_log_warn, vha, 0x0056,
2939 "Unrecognized golden fw at 0x%x.\n",
2940 ha->flt_region_gold_fw * 4);
0f2d962f
MI		 2941 return ret;
2942 }
2943
2944 for (i = 4; i < 8; i++)
2945 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
2946
30c47662
AV		 2947 return ret;
2948}
cb8dacbf 2949
1ee27146
JC		 2950static int
2951qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2952{
2953 if (pos >= end || *pos != 0x82)
2954 return 0;
2955
2956 pos += 3 + pos[1];
2957 if (pos >= end || *pos != 0x90)
2958 return 0;
2959
2960 pos += 3 + pos[1];
2961 if (pos >= end || *pos != 0x78)
2962 return 0;
2963
2964 return 1;
2965}
2966
2967int
7b867cf7 2968qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
1ee27146 2969{
7b867cf7 2970 struct qla_hw_data *ha = vha->hw;
1ee27146
JC		 2971 uint8_t *pos = ha->vpd;
2972 uint8_t *end = pos + ha->vpd_size;
2973 int len = 0;
2974
2975 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2976 return 0;
2977
2978 while (pos < end && *pos != 0x78) {
2979 len = (*pos == 0x82) ? pos[1] : pos[2];
2980
2981 if (!strncmp(pos, key, strlen(key)))
2982 break;
2983
2984 if (*pos != 0x90 && *pos != 0x91)
2985 pos += len;
2986
2987 pos += 3;
2988 }
2989
2990 if (pos < end - len && *pos != 0x78)
2991 return snprintf(str, size, "%.*s", len, pos + 3);
2992
2993 return 0;
2994}
09ff701a
SR		 2995
2996int
2997qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
2998{
2999 int len, max_len;
3000 uint32_t fcp_prio_addr;
3001 struct qla_hw_data *ha = vha->hw;
3002
3003 if (!ha->fcp_prio_cfg) {
3004 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3005 if (!ha->fcp_prio_cfg) {
7c3df132
SK		 3006 ql_log(ql_log_warn, vha, 0x00d5,
3007 "Unable to allocate memory for fcp priorty data (%x).\n",
3008 FCP_PRIO_CFG_SIZE);
09ff701a
SR		 3009 return QLA_FUNCTION_FAILED;
3010 }
3011 }
3012 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3013
3014 fcp_prio_addr = ha->flt_region_fcp_prio;
3015
3016 /* first read the fcp priority data header from flash */
3017 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3018 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3019
7c3df132 3020 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
09ff701a
SR		 3021 goto fail;
3022
3023 /* read remaining FCP CMD config data from flash */
3024 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3025 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3026 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3027
3028 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3029 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3030
3031 /* revalidate the entire FCP priority config data, including entries */
7c3df132 3032 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
09ff701a
SR		 3033 goto fail;
3034
3035 ha->flags.fcp_prio_enabled = 1;
3036 return QLA_SUCCESS;
3037fail:
3038 vfree(ha->fcp_prio_cfg);
3039 ha->fcp_prio_cfg = NULL;
3040 return QLA_FUNCTION_FAILED;
3041}
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