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[SCSI] qla2xxx: printk fixes
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
10#include <asm/uaccess.h>
11
12static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
13static void qla2x00_nv_deselect(scsi_qla_host_t *);
14static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
15
16/*
17 * NVRAM support routines
18 */
19
20/**
fa2a1ce5 21 * qla2x00_lock_nvram_access() -
1da177e4
LT		 22 * @ha: HA context
23 */
24void
25qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
26{
27 uint16_t data;
3d71644c 28 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 29
30 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
31 data = RD_REG_WORD(&reg->nvram);
32 while (data & NVR_BUSY) {
33 udelay(100);
34 data = RD_REG_WORD(&reg->nvram);
35 }
36
37 /* Lock resource */
38 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
39 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 udelay(5);
41 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
42 while ((data & BIT_0) == 0) {
43 /* Lock failed */
44 udelay(100);
45 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
46 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 udelay(5);
48 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
49 }
50 }
51}
52
53/**
fa2a1ce5 54 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 55 * @ha: HA context
56 */
57void
58qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
59{
3d71644c 60 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 61
62 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
63 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
64 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
65 }
66}
67
1da177e4
LT		 68/**
69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
70 * request routine to get the word from NVRAM.
71 * @ha: HA context
72 * @addr: Address in NVRAM to read
73 *
74 * Returns the word read from nvram @addr.
75 */
76uint16_t
77qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
78{
79 uint16_t data;
80 uint32_t nv_cmd;
81
82 nv_cmd = addr << 16;
83 nv_cmd |= NV_READ_OP;
84 data = qla2x00_nvram_request(ha, nv_cmd);
85
86 return (data);
87}
88
89/**
90 * qla2x00_write_nvram_word() - Write NVRAM data.
91 * @ha: HA context
92 * @addr: Address in NVRAM to write
93 * @data: word to program
94 */
95void
96qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
97{
98 int count;
99 uint16_t word;
45aeaf1e 100 uint32_t nv_cmd, wait_cnt;
3d71644c 101 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 102
103 qla2x00_nv_write(ha, NVR_DATA_OUT);
104 qla2x00_nv_write(ha, 0);
105 qla2x00_nv_write(ha, 0);
106
107 for (word = 0; word < 8; word++)
108 qla2x00_nv_write(ha, NVR_DATA_OUT);
109
110 qla2x00_nv_deselect(ha);
111
112 /* Write data */
113 nv_cmd = (addr << 16) | NV_WRITE_OP;
114 nv_cmd |= data;
115 nv_cmd <<= 5;
116 for (count = 0; count < 27; count++) {
117 if (nv_cmd & BIT_31)
118 qla2x00_nv_write(ha, NVR_DATA_OUT);
119 else
120 qla2x00_nv_write(ha, 0);
121
122 nv_cmd <<= 1;
123 }
124
125 qla2x00_nv_deselect(ha);
126
127 /* Wait for NVRAM to become ready */
128 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 129 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 130 wait_cnt = NVR_WAIT_CNT;
1da177e4 131 do {
45aeaf1e
RA		 132 if (!--wait_cnt) {
133 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
134 __func__, ha->host_no));
135 break;
136 }
1da177e4
LT		 137 NVRAM_DELAY();
138 word = RD_REG_WORD(&reg->nvram);
139 } while ((word & NVR_DATA_IN) == 0);
140
141 qla2x00_nv_deselect(ha);
142
143 /* Disable writes */
144 qla2x00_nv_write(ha, NVR_DATA_OUT);
145 for (count = 0; count < 10; count++)
146 qla2x00_nv_write(ha, 0);
147
148 qla2x00_nv_deselect(ha);
149}
150
459c5378
AV		 151static int
152qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
153 uint32_t tmo)
154{
155 int ret, count;
156 uint16_t word;
157 uint32_t nv_cmd;
158 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
159
160 ret = QLA_SUCCESS;
161
162 qla2x00_nv_write(ha, NVR_DATA_OUT);
163 qla2x00_nv_write(ha, 0);
164 qla2x00_nv_write(ha, 0);
165
166 for (word = 0; word < 8; word++)
167 qla2x00_nv_write(ha, NVR_DATA_OUT);
168
169 qla2x00_nv_deselect(ha);
170
171 /* Write data */
172 nv_cmd = (addr << 16) | NV_WRITE_OP;
173 nv_cmd |= data;
174 nv_cmd <<= 5;
175 for (count = 0; count < 27; count++) {
176 if (nv_cmd & BIT_31)
177 qla2x00_nv_write(ha, NVR_DATA_OUT);
178 else
179 qla2x00_nv_write(ha, 0);
180
181 nv_cmd <<= 1;
182 }
183
184 qla2x00_nv_deselect(ha);
185
186 /* Wait for NVRAM to become ready */
187 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 188 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 189 do {
190 NVRAM_DELAY();
191 word = RD_REG_WORD(&reg->nvram);
192 if (!--tmo) {
193 ret = QLA_FUNCTION_FAILED;
194 break;
195 }
196 } while ((word & NVR_DATA_IN) == 0);
197
198 qla2x00_nv_deselect(ha);
199
200 /* Disable writes */
201 qla2x00_nv_write(ha, NVR_DATA_OUT);
202 for (count = 0; count < 10; count++)
203 qla2x00_nv_write(ha, 0);
204
205 qla2x00_nv_deselect(ha);
206
207 return ret;
208}
209
1da177e4
LT		 210/**
211 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
212 * NVRAM.
213 * @ha: HA context
214 * @nv_cmd: NVRAM command
215 *
216 * Bit definitions for NVRAM command:
217 *
218 * Bit 26 = start bit
219 * Bit 25, 24 = opcode
220 * Bit 23-16 = address
221 * Bit 15-0 = write data
222 *
223 * Returns the word read from nvram @addr.
224 */
225static uint16_t
226qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
227{
228 uint8_t cnt;
3d71644c 229 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 230 uint16_t data = 0;
231 uint16_t reg_data;
232
233 /* Send command to NVRAM. */
234 nv_cmd <<= 5;
235 for (cnt = 0; cnt < 11; cnt++) {
236 if (nv_cmd & BIT_31)
237 qla2x00_nv_write(ha, NVR_DATA_OUT);
238 else
239 qla2x00_nv_write(ha, 0);
240 nv_cmd <<= 1;
241 }
242
243 /* Read data from NVRAM. */
244 for (cnt = 0; cnt < 16; cnt++) {
245 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
dcb36ce9 246 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1da177e4
LT		 247 NVRAM_DELAY();
248 data <<= 1;
249 reg_data = RD_REG_WORD(&reg->nvram);
250 if (reg_data & NVR_DATA_IN)
251 data |= BIT_0;
252 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
253 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
254 NVRAM_DELAY();
255 }
256
257 /* Deselect chip. */
258 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
259 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
260 NVRAM_DELAY();
261
262 return (data);
263}
264
265/**
266 * qla2x00_nv_write() - Clean NVRAM operations.
267 * @ha: HA context
268 */
269static void
270qla2x00_nv_deselect(scsi_qla_host_t *ha)
271{
3d71644c 272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 273
274 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
275 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
276 NVRAM_DELAY();
277}
278
279/**
280 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
281 * @ha: HA context
282 * @data: Serial interface selector
283 */
284static void
285qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
286{
3d71644c 287 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 288
289 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
290 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
291 NVRAM_DELAY();
292 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
293 NVR_WRT_ENABLE);
294 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
295 NVRAM_DELAY();
296 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
297 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
298 NVRAM_DELAY();
299}
300
459c5378
AV		 301/**
302 * qla2x00_clear_nvram_protection() -
303 * @ha: HA context
304 */
305static int
306qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
307{
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 310 uint32_t word, wait_cnt;
459c5378
AV		 311 uint16_t wprot, wprot_old;
312
313 /* Clear NVRAM write protection. */
314 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 315
316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 318 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
320 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 321 /* Write enable. */
322 qla2x00_nv_write(ha, NVR_DATA_OUT);
323 qla2x00_nv_write(ha, 0);
324 qla2x00_nv_write(ha, 0);
325 for (word = 0; word < 8; word++)
326 qla2x00_nv_write(ha, NVR_DATA_OUT);
327
328 qla2x00_nv_deselect(ha);
329
330 /* Enable protection register. */
331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
332 qla2x00_nv_write(ha, NVR_PR_ENABLE);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 for (word = 0; word < 8; word++)
335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
336
337 qla2x00_nv_deselect(ha);
338
339 /* Clear protection register (ffff is cleared). */
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 for (word = 0; word < 8; word++)
344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
345
346 qla2x00_nv_deselect(ha);
347
348 /* Wait for NVRAM to become ready. */
349 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 350 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 351 wait_cnt = NVR_WAIT_CNT;
459c5378 352 do {
45aeaf1e
RA		 353 if (!--wait_cnt) {
354 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
355 "ready...\n", __func__,
356 ha->host_no));
357 break;
358 }
459c5378
AV		 359 NVRAM_DELAY();
360 word = RD_REG_WORD(&reg->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
45aeaf1e
RA		 363 if (wait_cnt)
364 ret = QLA_SUCCESS;
459c5378 365 } else
45aeaf1e 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 367
368 return ret;
369}
370
371static void
372qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
373{
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 375 uint32_t word, wait_cnt;
459c5378
AV		 376
377 if (stat != QLA_SUCCESS)
378 return;
379
380 /* Set NVRAM write protection. */
381 /* Write enable. */
382 qla2x00_nv_write(ha, NVR_DATA_OUT);
383 qla2x00_nv_write(ha, 0);
384 qla2x00_nv_write(ha, 0);
385 for (word = 0; word < 8; word++)
386 qla2x00_nv_write(ha, NVR_DATA_OUT);
387
388 qla2x00_nv_deselect(ha);
389
390 /* Enable protection register. */
391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
392 qla2x00_nv_write(ha, NVR_PR_ENABLE);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 for (word = 0; word < 8; word++)
395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
396
397 qla2x00_nv_deselect(ha);
398
399 /* Enable protection register. */
400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
403 for (word = 0; word < 8; word++)
404 qla2x00_nv_write(ha, NVR_PR_ENABLE);
405
406 qla2x00_nv_deselect(ha);
407
408 /* Wait for NVRAM to become ready. */
409 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 410 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 411 wait_cnt = NVR_WAIT_CNT;
459c5378 412 do {
45aeaf1e
RA		 413 if (!--wait_cnt) {
414 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
415 __func__, ha->host_no));
416 break;
417 }
459c5378
AV		 418 NVRAM_DELAY();
419 word = RD_REG_WORD(&reg->nvram);
420 } while ((word & NVR_DATA_IN) == 0);
421}
422
423
424/*****************************************************************************/
425/* Flash Manipulation Routines */
426/*****************************************************************************/
427
338c9161
AV		 428#define OPTROM_BURST_SIZE 0x1000
429#define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
430
459c5378
AV		 431static inline uint32_t
432flash_conf_to_access_addr(uint32_t faddr)
433{
434 return FARX_ACCESS_FLASH_CONF | faddr;
435}
436
437static inline uint32_t
438flash_data_to_access_addr(uint32_t faddr)
439{
440 return FARX_ACCESS_FLASH_DATA | faddr;
441}
442
443static inline uint32_t
444nvram_conf_to_access_addr(uint32_t naddr)
445{
446 return FARX_ACCESS_NVRAM_CONF | naddr;
447}
448
449static inline uint32_t
450nvram_data_to_access_addr(uint32_t naddr)
451{
452 return FARX_ACCESS_NVRAM_DATA | naddr;
453}
454
e5f82ab8 455static uint32_t
459c5378
AV		 456qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
457{
458 int rval;
459 uint32_t cnt, data;
460 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
461
462 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
463 /* Wait for READ cycle to complete. */
464 rval = QLA_SUCCESS;
465 for (cnt = 3000;
466 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
467 rval == QLA_SUCCESS; cnt--) {
468 if (cnt)
469 udelay(10);
470 else
471 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 472 cond_resched();
459c5378
AV		 473 }
474
475 /* TODO: What happens if we time out? */
476 data = 0xDEADDEAD;
477 if (rval == QLA_SUCCESS)
478 data = RD_REG_DWORD(&reg->flash_data);
479
480 return data;
481}
482
483uint32_t *
484qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
485 uint32_t dwords)
486{
487 uint32_t i;
459c5378
AV		 488
489 /* Dword reads to flash. */
490 for (i = 0; i < dwords; i++, faddr++)
491 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
492 flash_data_to_access_addr(faddr)));
493
459c5378
AV		 494 return dwptr;
495}
496
e5f82ab8 497static int
459c5378
AV		 498qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
499{
500 int rval;
501 uint32_t cnt;
502 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
503
504 WRT_REG_DWORD(&reg->flash_data, data);
505 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
506 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
507 /* Wait for Write cycle to complete. */
508 rval = QLA_SUCCESS;
509 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
510 rval == QLA_SUCCESS; cnt--) {
511 if (cnt)
512 udelay(10);
513 else
514 rval = QLA_FUNCTION_TIMEOUT;
40a2e34a 515 cond_resched();
459c5378
AV		 516 }
517 return rval;
518}
519
e5f82ab8 520static void
459c5378
AV		 521qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
522 uint8_t *flash_id)
523{
524 uint32_t ids;
525
526 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
527 *man_id = LSB(ids);
528 *flash_id = MSB(ids);
45aeaf1e
RA		 529
530 /* Check if man_id and flash_id are valid. */
531 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
532 /* Read information using 0x9f opcode
533 * Device ID, Mfg ID would be read in the format:
534 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
535 * Example: ATMEL 0x00 01 45 1F
536 * Extract MFG and Dev ID from last two bytes.
537 */
538 ids = qla24xx_read_flash_dword(ha,
539 flash_data_to_access_addr(0xd009f));
540 *man_id = LSB(ids);
541 *flash_id = MSB(ids);
542 }
459c5378
AV		 543}
544
e5f82ab8 545static int
459c5378
AV		 546qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
547 uint32_t dwords)
548{
549 int ret;
338c9161
AV		 550 uint32_t liter, miter;
551 uint32_t sec_mask, rest_addr, conf_addr;
45aeaf1e 552 uint32_t fdata, findex ;
459c5378
AV		 553 uint8_t man_id, flash_id;
554 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
338c9161
AV		 555 dma_addr_t optrom_dma;
556 void *optrom = NULL;
557 uint32_t *s, *d;
459c5378
AV		 558
559 ret = QLA_SUCCESS;
560
338c9161 561 /* Prepare burst-capable write on supported ISPs. */
b7cc176c 562 if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
338c9161
AV		 563 dwords > OPTROM_BURST_DWORDS) {
564 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
565 &optrom_dma, GFP_KERNEL);
566 if (!optrom) {
567 qla_printk(KERN_DEBUG, ha,
568 "Unable to allocate memory for optrom burst write "
569 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
570 }
571 }
572
459c5378
AV		 573 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
574 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
575 ha->host_no, man_id, flash_id));
576
577 conf_addr = flash_conf_to_access_addr(0x03d8);
578 switch (man_id) {
fa2a1ce5 579 case 0xbf: /* STT flash. */
338c9161
AV		 580 if (flash_id == 0x8e) {
581 rest_addr = 0x3fff;
582 sec_mask = 0x7c000;
583 } else {
584 rest_addr = 0x1fff;
585 sec_mask = 0x7e000;
586 }
459c5378
AV		 587 if (flash_id == 0x80)
588 conf_addr = flash_conf_to_access_addr(0x0352);
589 break;
fa2a1ce5 590 case 0x13: /* ST M25P80. */
459c5378 591 rest_addr = 0x3fff;
338c9161 592 sec_mask = 0x7c000;
459c5378 593 break;
45aeaf1e 594 case 0x1f: // Atmel 26DF081A
338c9161
AV		 595 rest_addr = 0x3fff;
596 sec_mask = 0x7c000;
45aeaf1e
RA		 597 conf_addr = flash_conf_to_access_addr(0x0320);
598 break;
459c5378 599 default:
fa2a1ce5 600 /* Default to 64 kb sector size. */
459c5378 601 rest_addr = 0x3fff;
338c9161 602 sec_mask = 0x7c000;
459c5378
AV		 603 break;
604 }
605
606 /* Enable flash write. */
607 WRT_REG_DWORD(&reg->ctrl_status,
608 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
609 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
610
611 /* Disable flash write-protection. */
612 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
45aeaf1e
RA		 613 /* Some flash parts need an additional zero-write to clear bits.*/
614 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
459c5378 615
338c9161
AV		 616 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
617 if (man_id == 0x1f) {
618 findex = faddr << 2;
619 fdata = findex & sec_mask;
620 } else {
621 findex = faddr;
622 fdata = (findex & sec_mask) << 2;
623 }
45aeaf1e 624
338c9161
AV		 625 /* Are we at the beginning of a sector? */
626 if ((findex & rest_addr) == 0) {
627 /* Do sector unprotect at 4K boundry for Atmel part. */
628 if (man_id == 0x1f)
629 qla24xx_write_flash_dword(ha,
630 flash_conf_to_access_addr(0x0339),
631 (fdata & 0xff00) | ((fdata << 16) &
459c5378 632 0xff0000) | ((fdata >> 16) & 0xff));
338c9161
AV		 633 ret = qla24xx_write_flash_dword(ha, conf_addr,
634 (fdata & 0xff00) |((fdata << 16) &
635 0xff0000) | ((fdata >> 16) & 0xff));
636 if (ret != QLA_SUCCESS) {
637 DEBUG9(printk("%s(%ld) Unable to flash "
638 "sector: address=%x.\n", __func__,
639 ha->host_no, faddr));
640 break;
459c5378 641 }
338c9161
AV		 642 }
643
644 /* Go with burst-write. */
645 if (optrom && (liter + OPTROM_BURST_DWORDS) < dwords) {
646 /* Copy data to DMA'ble buffer. */
647 for (miter = 0, s = optrom, d = dwptr;
648 miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
649 *s = cpu_to_le32(*d);
650
651 ret = qla2x00_load_ram(ha, optrom_dma,
459c5378 652 flash_data_to_access_addr(faddr),
338c9161 653 OPTROM_BURST_DWORDS);
459c5378 654 if (ret != QLA_SUCCESS) {
338c9161
AV		 655 qla_printk(KERN_WARNING, ha,
656 "Unable to burst-write optrom segment "
657 "(%x/%x/%llx).\n", ret,
658 flash_data_to_access_addr(faddr),
875baf3c 659 (unsigned long long)optrom_dma);
338c9161
AV		 660 qla_printk(KERN_WARNING, ha,
661 "Reverting to slow-write.\n");
662
663 dma_free_coherent(&ha->pdev->dev,
664 OPTROM_BURST_SIZE, optrom, optrom_dma);
665 optrom = NULL;
666 } else {
667 liter += OPTROM_BURST_DWORDS - 1;
668 faddr += OPTROM_BURST_DWORDS - 1;
669 dwptr += OPTROM_BURST_DWORDS - 1;
670 continue;
459c5378 671 }
338c9161 672 }
45aeaf1e 673
338c9161
AV		 674 ret = qla24xx_write_flash_dword(ha,
675 flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
676 if (ret != QLA_SUCCESS) {
677 DEBUG9(printk("%s(%ld) Unable to program flash "
678 "address=%x data=%x.\n", __func__,
679 ha->host_no, faddr, *dwptr));
680 break;
459c5378 681 }
338c9161
AV		 682
683 /* Do sector protect at 4K boundry for Atmel part. */
684 if (man_id == 0x1f &&
685 ((faddr & rest_addr) == rest_addr))
686 qla24xx_write_flash_dword(ha,
687 flash_conf_to_access_addr(0x0336),
688 (fdata & 0xff00) | ((fdata << 16) &
689 0xff0000) | ((fdata >> 16) & 0xff));
690 }
459c5378 691
e978010c
AV		 692 /* Enable flash write-protection. */
693 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
694
459c5378
AV		 695 /* Disable flash write. */
696 WRT_REG_DWORD(&reg->ctrl_status,
697 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
698 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
699
338c9161
AV		 700 if (optrom)
701 dma_free_coherent(&ha->pdev->dev,
702 OPTROM_BURST_SIZE, optrom, optrom_dma);
703
459c5378
AV		 704 return ret;
705}
706
707uint8_t *
708qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
709 uint32_t bytes)
710{
711 uint32_t i;
712 uint16_t *wptr;
713
714 /* Word reads to NVRAM via registers. */
715 wptr = (uint16_t *)buf;
716 qla2x00_lock_nvram_access(ha);
717 for (i = 0; i < bytes >> 1; i++, naddr++)
718 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
719 naddr));
720 qla2x00_unlock_nvram_access(ha);
721
722 return buf;
723}
724
725uint8_t *
726qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
727 uint32_t bytes)
728{
729 uint32_t i;
730 uint32_t *dwptr;
459c5378
AV		 731
732 /* Dword reads to flash. */
733 dwptr = (uint32_t *)buf;
734 for (i = 0; i < bytes >> 2; i++, naddr++)
735 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
736 nvram_data_to_access_addr(naddr)));
737
459c5378
AV		 738 return buf;
739}
740
741int
742qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
743 uint32_t bytes)
744{
745 int ret, stat;
746 uint32_t i;
747 uint16_t *wptr;
748
749 ret = QLA_SUCCESS;
750
751 qla2x00_lock_nvram_access(ha);
752
753 /* Disable NVRAM write-protection. */
754 stat = qla2x00_clear_nvram_protection(ha);
755
756 wptr = (uint16_t *)buf;
757 for (i = 0; i < bytes >> 1; i++, naddr++) {
758 qla2x00_write_nvram_word(ha, naddr,
759 cpu_to_le16(*wptr));
760 wptr++;
761 }
762
763 /* Enable NVRAM write-protection. */
764 qla2x00_set_nvram_protection(ha, stat);
765
766 qla2x00_unlock_nvram_access(ha);
767
768 return ret;
769}
770
771int
772qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
773 uint32_t bytes)
774{
775 int ret;
776 uint32_t i;
777 uint32_t *dwptr;
778 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
779
780 ret = QLA_SUCCESS;
781
459c5378
AV		 782 /* Enable flash write. */
783 WRT_REG_DWORD(&reg->ctrl_status,
784 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
785 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
786
787 /* Disable NVRAM write-protection. */
788 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
789 0);
790 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
791 0);
792
793 /* Dword writes to flash. */
794 dwptr = (uint32_t *)buf;
795 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
796 ret = qla24xx_write_flash_dword(ha,
797 nvram_data_to_access_addr(naddr),
798 cpu_to_le32(*dwptr));
799 if (ret != QLA_SUCCESS) {
800 DEBUG9(printk("%s(%ld) Unable to program "
801 "nvram address=%x data=%x.\n", __func__,
802 ha->host_no, naddr, *dwptr));
803 break;
804 }
805 }
806
807 /* Enable NVRAM write-protection. */
808 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
809 0x8c);
810
811 /* Disable flash write. */
812 WRT_REG_DWORD(&reg->ctrl_status,
813 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
814 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
815
459c5378
AV		 816 return ret;
817}
f6df144c 818
c3a2f0df
AV		 819uint8_t *
820qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
821 uint32_t bytes)
822{
823 uint32_t i;
824 uint32_t *dwptr;
825
826 /* Dword reads to flash. */
827 dwptr = (uint32_t *)buf;
828 for (i = 0; i < bytes >> 2; i++, naddr++)
829 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
830 flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr)));
831
832 return buf;
833}
834
835int
836qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
837 uint32_t bytes)
838{
839 return qla24xx_write_flash_data(ha, (uint32_t *)buf,
840 FA_VPD_NVRAM_ADDR | naddr, bytes >> 2);
841}
f6df144c
AV		 842
843static inline void
844qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
845{
846 if (IS_QLA2322(ha)) {
847 /* Flip all colors. */
848 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
849 /* Turn off. */
850 ha->beacon_color_state = 0;
851 *pflags = GPIO_LED_ALL_OFF;
852 } else {
853 /* Turn on. */
854 ha->beacon_color_state = QLA_LED_ALL_ON;
855 *pflags = GPIO_LED_RGA_ON;
856 }
857 } else {
858 /* Flip green led only. */
859 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
860 /* Turn off. */
861 ha->beacon_color_state = 0;
862 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
863 } else {
864 /* Turn on. */
865 ha->beacon_color_state = QLA_LED_GRN_ON;
866 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
867 }
868 }
869}
870
871void
872qla2x00_beacon_blink(struct scsi_qla_host *ha)
873{
874 uint16_t gpio_enable;
875 uint16_t gpio_data;
876 uint16_t led_color = 0;
877 unsigned long flags;
878 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
879
880 if (ha->pio_address)
881 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
882
883 spin_lock_irqsave(&ha->hardware_lock, flags);
884
885 /* Save the Original GPIOE. */
886 if (ha->pio_address) {
887 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
888 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
889 } else {
890 gpio_enable = RD_REG_WORD(&reg->gpioe);
891 gpio_data = RD_REG_WORD(&reg->gpiod);
892 }
893
894 /* Set the modified gpio_enable values */
895 gpio_enable |= GPIO_LED_MASK;
896
897 if (ha->pio_address) {
898 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
899 } else {
900 WRT_REG_WORD(&reg->gpioe, gpio_enable);
901 RD_REG_WORD(&reg->gpioe);
902 }
903
904 qla2x00_flip_colors(ha, &led_color);
905
906 /* Clear out any previously set LED color. */
907 gpio_data &= ~GPIO_LED_MASK;
908
909 /* Set the new input LED color to GPIOD. */
910 gpio_data |= led_color;
911
912 /* Set the modified gpio_data values */
913 if (ha->pio_address) {
914 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
915 } else {
916 WRT_REG_WORD(&reg->gpiod, gpio_data);
917 RD_REG_WORD(&reg->gpiod);
918 }
919
920 spin_unlock_irqrestore(&ha->hardware_lock, flags);
921}
922
923int
924qla2x00_beacon_on(struct scsi_qla_host *ha)
925{
926 uint16_t gpio_enable;
927 uint16_t gpio_data;
928 unsigned long flags;
929 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
930
931 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
932 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
933
934 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
935 qla_printk(KERN_WARNING, ha,
936 "Unable to update fw options (beacon on).\n");
937 return QLA_FUNCTION_FAILED;
938 }
939
940 if (ha->pio_address)
941 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
942
943 /* Turn off LEDs. */
944 spin_lock_irqsave(&ha->hardware_lock, flags);
945 if (ha->pio_address) {
946 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
947 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
948 } else {
949 gpio_enable = RD_REG_WORD(&reg->gpioe);
950 gpio_data = RD_REG_WORD(&reg->gpiod);
951 }
952 gpio_enable |= GPIO_LED_MASK;
953
954 /* Set the modified gpio_enable values. */
955 if (ha->pio_address) {
956 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
957 } else {
958 WRT_REG_WORD(&reg->gpioe, gpio_enable);
959 RD_REG_WORD(&reg->gpioe);
960 }
961
962 /* Clear out previously set LED colour. */
963 gpio_data &= ~GPIO_LED_MASK;
964 if (ha->pio_address) {
965 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
966 } else {
967 WRT_REG_WORD(&reg->gpiod, gpio_data);
968 RD_REG_WORD(&reg->gpiod);
969 }
970 spin_unlock_irqrestore(&ha->hardware_lock, flags);
971
972 /*
973 * Let the per HBA timer kick off the blinking process based on
974 * the following flags. No need to do anything else now.
975 */
976 ha->beacon_blink_led = 1;
977 ha->beacon_color_state = 0;
978
979 return QLA_SUCCESS;
980}
981
982int
983qla2x00_beacon_off(struct scsi_qla_host *ha)
984{
985 int rval = QLA_SUCCESS;
986
987 ha->beacon_blink_led = 0;
988
989 /* Set the on flag so when it gets flipped it will be off. */
990 if (IS_QLA2322(ha))
991 ha->beacon_color_state = QLA_LED_ALL_ON;
992 else
993 ha->beacon_color_state = QLA_LED_GRN_ON;
994
fd34f556 995 ha->isp_ops->beacon_blink(ha); /* This turns green LED off */
f6df144c
AV		 996
997 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
998 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
999
1000 rval = qla2x00_set_fw_options(ha, ha->fw_options);
1001 if (rval != QLA_SUCCESS)
1002 qla_printk(KERN_WARNING, ha,
1003 "Unable to update fw options (beacon off).\n");
1004 return rval;
1005}
1006
1007
1008static inline void
1009qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1010{
1011 /* Flip all colors. */
1012 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1013 /* Turn off. */
1014 ha->beacon_color_state = 0;
1015 *pflags = 0;
1016 } else {
1017 /* Turn on. */
1018 ha->beacon_color_state = QLA_LED_ALL_ON;
1019 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1020 }
1021}
1022
1023void
1024qla24xx_beacon_blink(struct scsi_qla_host *ha)
1025{
1026 uint16_t led_color = 0;
1027 uint32_t gpio_data;
1028 unsigned long flags;
1029 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1030
1031 /* Save the Original GPIOD. */
1032 spin_lock_irqsave(&ha->hardware_lock, flags);
1033 gpio_data = RD_REG_DWORD(&reg->gpiod);
1034
1035 /* Enable the gpio_data reg for update. */
1036 gpio_data |= GPDX_LED_UPDATE_MASK;
1037
1038 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1039 gpio_data = RD_REG_DWORD(&reg->gpiod);
1040
1041 /* Set the color bits. */
1042 qla24xx_flip_colors(ha, &led_color);
1043
1044 /* Clear out any previously set LED color. */
1045 gpio_data &= ~GPDX_LED_COLOR_MASK;
1046
1047 /* Set the new input LED color to GPIOD. */
1048 gpio_data |= led_color;
1049
1050 /* Set the modified gpio_data values. */
1051 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1052 gpio_data = RD_REG_DWORD(&reg->gpiod);
1053 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1054}
1055
1056int
1057qla24xx_beacon_on(struct scsi_qla_host *ha)
1058{
1059 uint32_t gpio_data;
1060 unsigned long flags;
1061 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1062
1063 if (ha->beacon_blink_led == 0) {
1064 /* Enable firmware for update */
1065 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1066
1067 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1068 return QLA_FUNCTION_FAILED;
1069
1070 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1071 QLA_SUCCESS) {
1072 qla_printk(KERN_WARNING, ha,
1073 "Unable to update fw options (beacon on).\n");
1074 return QLA_FUNCTION_FAILED;
1075 }
1076
1077 spin_lock_irqsave(&ha->hardware_lock, flags);
1078 gpio_data = RD_REG_DWORD(&reg->gpiod);
1079
1080 /* Enable the gpio_data reg for update. */
1081 gpio_data |= GPDX_LED_UPDATE_MASK;
1082 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1083 RD_REG_DWORD(&reg->gpiod);
1084
1085 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1086 }
1087
1088 /* So all colors blink together. */
1089 ha->beacon_color_state = 0;
1090
1091 /* Let the per HBA timer kick off the blinking process. */
1092 ha->beacon_blink_led = 1;
1093
1094 return QLA_SUCCESS;
1095}
1096
1097int
1098qla24xx_beacon_off(struct scsi_qla_host *ha)
1099{
1100 uint32_t gpio_data;
1101 unsigned long flags;
1102 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1103
1104 ha->beacon_blink_led = 0;
1105 ha->beacon_color_state = QLA_LED_ALL_ON;
1106
fd34f556 1107 ha->isp_ops->beacon_blink(ha); /* Will flip to all off. */
f6df144c
AV		 1108
1109 /* Give control back to firmware. */
1110 spin_lock_irqsave(&ha->hardware_lock, flags);
1111 gpio_data = RD_REG_DWORD(&reg->gpiod);
1112
1113 /* Disable the gpio_data reg for update. */
1114 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1115 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1116 RD_REG_DWORD(&reg->gpiod);
1117 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1118
1119 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1120
1121 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1122 qla_printk(KERN_WARNING, ha,
1123 "Unable to update fw options (beacon off).\n");
1124 return QLA_FUNCTION_FAILED;
1125 }
1126
1127 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1128 qla_printk(KERN_WARNING, ha,
1129 "Unable to get fw options (beacon off).\n");
1130 return QLA_FUNCTION_FAILED;
1131 }
1132
1133 return QLA_SUCCESS;
1134}
854165f4
AV		 1135
1136
1137/*
1138 * Flash support routines
1139 */
1140
1141/**
1142 * qla2x00_flash_enable() - Setup flash for reading and writing.
1143 * @ha: HA context
1144 */
1145static void
1146qla2x00_flash_enable(scsi_qla_host_t *ha)
1147{
1148 uint16_t data;
1149 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1150
1151 data = RD_REG_WORD(&reg->ctrl_status);
1152 data |= CSR_FLASH_ENABLE;
1153 WRT_REG_WORD(&reg->ctrl_status, data);
1154 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1155}
1156
1157/**
1158 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1159 * @ha: HA context
1160 */
1161static void
1162qla2x00_flash_disable(scsi_qla_host_t *ha)
1163{
1164 uint16_t data;
1165 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1166
1167 data = RD_REG_WORD(&reg->ctrl_status);
1168 data &= ~(CSR_FLASH_ENABLE);
1169 WRT_REG_WORD(&reg->ctrl_status, data);
1170 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1171}
1172
1173/**
1174 * qla2x00_read_flash_byte() - Reads a byte from flash
1175 * @ha: HA context
1176 * @addr: Address in flash to read
1177 *
1178 * A word is read from the chip, but, only the lower byte is valid.
1179 *
1180 * Returns the byte read from flash @addr.
1181 */
1182static uint8_t
1183qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1184{
1185 uint16_t data;
1186 uint16_t bank_select;
1187 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1188
1189 bank_select = RD_REG_WORD(&reg->ctrl_status);
1190
1191 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1192 /* Specify 64K address range: */
1193 /* clear out Module Select and Flash Address bits [19:16]. */
1194 bank_select &= ~0xf8;
1195 bank_select |= addr >> 12 & 0xf0;
1196 bank_select |= CSR_FLASH_64K_BANK;
1197 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1198 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1199
1200 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1201 data = RD_REG_WORD(&reg->flash_data);
1202
1203 return (uint8_t)data;
1204 }
1205
1206 /* Setup bit 16 of flash address. */
1207 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1208 bank_select |= CSR_FLASH_64K_BANK;
1209 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1210 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1211 } else if (((addr & BIT_16) == 0) &&
1212 (bank_select & CSR_FLASH_64K_BANK)) {
1213 bank_select &= ~(CSR_FLASH_64K_BANK);
1214 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1215 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1216 }
1217
1218 /* Always perform IO mapped accesses to the FLASH registers. */
1219 if (ha->pio_address) {
1220 uint16_t data2;
1221
1222 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1223 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1224 do {
1225 data = RD_REG_WORD_PIO(&reg->flash_data);
1226 barrier();
1227 cpu_relax();
1228 data2 = RD_REG_WORD_PIO(&reg->flash_data);
1229 } while (data != data2);
1230 } else {
1231 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1232 data = qla2x00_debounce_register(&reg->flash_data);
1233 }
1234
1235 return (uint8_t)data;
1236}
1237
1238/**
1239 * qla2x00_write_flash_byte() - Write a byte to flash
1240 * @ha: HA context
1241 * @addr: Address in flash to write
1242 * @data: Data to write
1243 */
1244static void
1245qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1246{
1247 uint16_t bank_select;
1248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1249
1250 bank_select = RD_REG_WORD(&reg->ctrl_status);
1251 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1252 /* Specify 64K address range: */
1253 /* clear out Module Select and Flash Address bits [19:16]. */
1254 bank_select &= ~0xf8;
1255 bank_select |= addr >> 12 & 0xf0;
1256 bank_select |= CSR_FLASH_64K_BANK;
1257 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1258 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1259
1260 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1261 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1262 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1263 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1264
1265 return;
1266 }
1267
1268 /* Setup bit 16 of flash address. */
1269 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1270 bank_select |= CSR_FLASH_64K_BANK;
1271 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1272 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1273 } else if (((addr & BIT_16) == 0) &&
1274 (bank_select & CSR_FLASH_64K_BANK)) {
1275 bank_select &= ~(CSR_FLASH_64K_BANK);
1276 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1277 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1278 }
1279
1280 /* Always perform IO mapped accesses to the FLASH registers. */
1281 if (ha->pio_address) {
1282 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1283 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1284 WRT_REG_WORD_PIO(&reg->flash_data, (uint16_t)data);
1285 } else {
1286 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1287 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1288 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1289 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1290 }
1291}
1292
1293/**
1294 * qla2x00_poll_flash() - Polls flash for completion.
1295 * @ha: HA context
1296 * @addr: Address in flash to poll
1297 * @poll_data: Data to be polled
1298 * @man_id: Flash manufacturer ID
1299 * @flash_id: Flash ID
1300 *
1301 * This function polls the device until bit 7 of what is read matches data
1302 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1303 * out (a fatal error). The flash book recommeds reading bit 7 again after
1304 * reading bit 5 as a 1.
1305 *
1306 * Returns 0 on success, else non-zero.
1307 */
1308static int
1309qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1310 uint8_t man_id, uint8_t flash_id)
1311{
1312 int status;
1313 uint8_t flash_data;
1314 uint32_t cnt;
1315
1316 status = 1;
1317
1318 /* Wait for 30 seconds for command to finish. */
1319 poll_data &= BIT_7;
1320 for (cnt = 3000000; cnt; cnt--) {
1321 flash_data = qla2x00_read_flash_byte(ha, addr);
1322 if ((flash_data & BIT_7) == poll_data) {
1323 status = 0;
1324 break;
1325 }
1326
1327 if (man_id != 0x40 && man_id != 0xda) {
1328 if ((flash_data & BIT_5) && cnt > 2)
1329 cnt = 2;
1330 }
1331 udelay(10);
1332 barrier();
40a2e34a 1333 cond_resched();
854165f4
AV		 1334 }
1335 return status;
1336}
1337
854165f4
AV		 1338/**
1339 * qla2x00_program_flash_address() - Programs a flash address
1340 * @ha: HA context
1341 * @addr: Address in flash to program
1342 * @data: Data to be written in flash
1343 * @man_id: Flash manufacturer ID
1344 * @flash_id: Flash ID
1345 *
1346 * Returns 0 on success, else non-zero.
1347 */
1348static int
1349qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1350 uint8_t man_id, uint8_t flash_id)
1351{
1352 /* Write Program Command Sequence. */
1353 if (IS_OEM_001(ha)) {
1354 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1355 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1356 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1357 qla2x00_write_flash_byte(ha, addr, data);
1358 } else {
1359 if (man_id == 0xda && flash_id == 0xc1) {
1360 qla2x00_write_flash_byte(ha, addr, data);
1361 if (addr & 0x7e)
1362 return 0;
1363 } else {
1364 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1365 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1366 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1367 qla2x00_write_flash_byte(ha, addr, data);
1368 }
1369 }
1370
1371 udelay(150);
1372
1373 /* Wait for write to complete. */
1374 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1375}
1376
1377/**
1378 * qla2x00_erase_flash() - Erase the flash.
1379 * @ha: HA context
1380 * @man_id: Flash manufacturer ID
1381 * @flash_id: Flash ID
1382 *
1383 * Returns 0 on success, else non-zero.
1384 */
1385static int
1386qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1387{
1388 /* Individual Sector Erase Command Sequence */
1389 if (IS_OEM_001(ha)) {
1390 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1391 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1392 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1393 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1394 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1395 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1396 } else {
1397 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1398 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1399 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1400 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1401 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1402 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1403 }
1404
1405 udelay(150);
1406
1407 /* Wait for erase to complete. */
1408 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1409}
1410
1411/**
1412 * qla2x00_erase_flash_sector() - Erase a flash sector.
1413 * @ha: HA context
1414 * @addr: Flash sector to erase
1415 * @sec_mask: Sector address mask
1416 * @man_id: Flash manufacturer ID
1417 * @flash_id: Flash ID
1418 *
1419 * Returns 0 on success, else non-zero.
1420 */
1421static int
1422qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1423 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1424{
1425 /* Individual Sector Erase Command Sequence */
1426 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1427 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1428 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1429 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1430 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1431 if (man_id == 0x1f && flash_id == 0x13)
1432 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1433 else
1434 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1435
1436 udelay(150);
1437
1438 /* Wait for erase to complete. */
1439 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1440}
1441
1442/**
1443 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1444 * @man_id: Flash manufacturer ID
1445 * @flash_id: Flash ID
1446 */
1447static void
1448qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1449 uint8_t *flash_id)
1450{
1451 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1452 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1453 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1454 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1455 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1456 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1457 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1458 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1459}
1460
30c47662
AV		 1461static void
1462qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1463 uint32_t length)
1464{
1465 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1466 uint32_t midpoint, ilength;
1467 uint8_t data;
1468
1469 midpoint = length / 2;
1470
1471 WRT_REG_WORD(&reg->nvram, 0);
1472 RD_REG_WORD(&reg->nvram);
1473 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1474 if (ilength == midpoint) {
1475 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1476 RD_REG_WORD(&reg->nvram);
1477 }
1478 data = qla2x00_read_flash_byte(ha, saddr);
1479 if (saddr % 100)
1480 udelay(10);
1481 *tmp_buf = data;
40a2e34a 1482 cond_resched();
30c47662
AV		 1483 }
1484}
854165f4
AV		 1485
1486static inline void
1487qla2x00_suspend_hba(struct scsi_qla_host *ha)
1488{
1489 int cnt;
1490 unsigned long flags;
1491 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1492
1493 /* Suspend HBA. */
1494 scsi_block_requests(ha->host);
fd34f556 1495 ha->isp_ops->disable_intrs(ha);
854165f4
AV		 1496 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1497
1498 /* Pause RISC. */
1499 spin_lock_irqsave(&ha->hardware_lock, flags);
1500 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1501 RD_REG_WORD(&reg->hccr);
1502 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1503 for (cnt = 0; cnt < 30000; cnt++) {
1504 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1505 break;
1506 udelay(100);
1507 }
1508 } else {
1509 udelay(10);
1510 }
1511 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1512}
1513
1514static inline void
1515qla2x00_resume_hba(struct scsi_qla_host *ha)
1516{
1517 /* Resume HBA. */
1518 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1519 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
39a11240 1520 qla2xxx_wake_dpc(ha);
854165f4
AV		 1521 qla2x00_wait_for_hba_online(ha);
1522 scsi_unblock_requests(ha->host);
1523}
1524
1525uint8_t *
1526qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1527 uint32_t offset, uint32_t length)
1528{
854165f4
AV		 1529 uint32_t addr, midpoint;
1530 uint8_t *data;
1531 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1532
1533 /* Suspend HBA. */
1534 qla2x00_suspend_hba(ha);
1535
1536 /* Go with read. */
854165f4
AV		 1537 midpoint = ha->optrom_size / 2;
1538
1539 qla2x00_flash_enable(ha);
1540 WRT_REG_WORD(&reg->nvram, 0);
1541 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1542 for (addr = offset, data = buf; addr < length; addr++, data++) {
1543 if (addr == midpoint) {
1544 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1545 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1546 }
1547
1548 *data = qla2x00_read_flash_byte(ha, addr);
1549 }
1550 qla2x00_flash_disable(ha);
854165f4
AV		 1551
1552 /* Resume HBA. */
1553 qla2x00_resume_hba(ha);
1554
1555 return buf;
1556}
1557
1558int
1559qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1560 uint32_t offset, uint32_t length)
1561{
1562
1563 int rval;
854165f4
AV		 1564 uint8_t man_id, flash_id, sec_number, data;
1565 uint16_t wd;
1566 uint32_t addr, liter, sec_mask, rest_addr;
1567 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1568
1569 /* Suspend HBA. */
1570 qla2x00_suspend_hba(ha);
1571
1572 rval = QLA_SUCCESS;
1573 sec_number = 0;
1574
1575 /* Reset ISP chip. */
854165f4
AV		 1576 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1577 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1578
1579 /* Go with write. */
1580 qla2x00_flash_enable(ha);
1581 do { /* Loop once to provide quick error exit */
1582 /* Structure of flash memory based on manufacturer */
1583 if (IS_OEM_001(ha)) {
1584 /* OEM variant with special flash part. */
1585 man_id = flash_id = 0;
1586 rest_addr = 0xffff;
1587 sec_mask = 0x10000;
1588 goto update_flash;
1589 }
1590 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1591 switch (man_id) {
1592 case 0x20: /* ST flash. */
1593 if (flash_id == 0xd2 || flash_id == 0xe3) {
1594 /*
1595 * ST m29w008at part - 64kb sector size with
1596 * 32kb,8kb,8kb,16kb sectors at memory address
1597 * 0xf0000.
1598 */
1599 rest_addr = 0xffff;
1600 sec_mask = 0x10000;
1601 break;
1602 }
1603 /*
1604 * ST m29w010b part - 16kb sector size
1605 * Default to 16kb sectors
1606 */
1607 rest_addr = 0x3fff;
1608 sec_mask = 0x1c000;
1609 break;
1610 case 0x40: /* Mostel flash. */
1611 /* Mostel v29c51001 part - 512 byte sector size. */
1612 rest_addr = 0x1ff;
1613 sec_mask = 0x1fe00;
1614 break;
1615 case 0xbf: /* SST flash. */
1616 /* SST39sf10 part - 4kb sector size. */
1617 rest_addr = 0xfff;
1618 sec_mask = 0x1f000;
1619 break;
1620 case 0xda: /* Winbond flash. */
1621 /* Winbond W29EE011 part - 256 byte sector size. */
1622 rest_addr = 0x7f;
1623 sec_mask = 0x1ff80;
1624 break;
1625 case 0xc2: /* Macronix flash. */
1626 /* 64k sector size. */
1627 if (flash_id == 0x38 || flash_id == 0x4f) {
1628 rest_addr = 0xffff;
1629 sec_mask = 0x10000;
1630 break;
1631 }
1632 /* Fall through... */
1633
1634 case 0x1f: /* Atmel flash. */
1635 /* 512k sector size. */
1636 if (flash_id == 0x13) {
1637 rest_addr = 0x7fffffff;
1638 sec_mask = 0x80000000;
1639 break;
1640 }
1641 /* Fall through... */
1642
1643 case 0x01: /* AMD flash. */
1644 if (flash_id == 0x38 || flash_id == 0x40 ||
1645 flash_id == 0x4f) {
1646 /* Am29LV081 part - 64kb sector size. */
1647 /* Am29LV002BT part - 64kb sector size. */
1648 rest_addr = 0xffff;
1649 sec_mask = 0x10000;
1650 break;
1651 } else if (flash_id == 0x3e) {
1652 /*
1653 * Am29LV008b part - 64kb sector size with
1654 * 32kb,8kb,8kb,16kb sector at memory address
1655 * h0xf0000.
1656 */
1657 rest_addr = 0xffff;
1658 sec_mask = 0x10000;
1659 break;
1660 } else if (flash_id == 0x20 || flash_id == 0x6e) {
1661 /*
1662 * Am29LV010 part or AM29f010 - 16kb sector
1663 * size.
1664 */
1665 rest_addr = 0x3fff;
1666 sec_mask = 0x1c000;
1667 break;
1668 } else if (flash_id == 0x6d) {
1669 /* Am29LV001 part - 8kb sector size. */
1670 rest_addr = 0x1fff;
1671 sec_mask = 0x1e000;
1672 break;
1673 }
1674 default:
1675 /* Default to 16 kb sector size. */
1676 rest_addr = 0x3fff;
1677 sec_mask = 0x1c000;
1678 break;
1679 }
1680
1681update_flash:
1682 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1683 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1684 rval = QLA_FUNCTION_FAILED;
1685 break;
1686 }
1687 }
1688
1689 for (addr = offset, liter = 0; liter < length; liter++,
1690 addr++) {
1691 data = buf[liter];
1692 /* Are we at the beginning of a sector? */
1693 if ((addr & rest_addr) == 0) {
1694 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1695 if (addr >= 0x10000UL) {
1696 if (((addr >> 12) & 0xf0) &&
1697 ((man_id == 0x01 &&
1698 flash_id == 0x3e) ||
1699 (man_id == 0x20 &&
1700 flash_id == 0xd2))) {
1701 sec_number++;
1702 if (sec_number == 1) {
1703 rest_addr =
1704 0x7fff;
1705 sec_mask =
1706 0x18000;
1707 } else if (
1708 sec_number == 2 ||
1709 sec_number == 3) {
1710 rest_addr =
1711 0x1fff;
1712 sec_mask =
1713 0x1e000;
1714 } else if (
1715 sec_number == 4) {
1716 rest_addr =
1717 0x3fff;
1718 sec_mask =
1719 0x1c000;
1720 }
1721 }
1722 }
1723 } else if (addr == ha->optrom_size / 2) {
1724 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1725 RD_REG_WORD(&reg->nvram);
1726 }
1727
1728 if (flash_id == 0xda && man_id == 0xc1) {
1729 qla2x00_write_flash_byte(ha, 0x5555,
1730 0xaa);
1731 qla2x00_write_flash_byte(ha, 0x2aaa,
1732 0x55);
1733 qla2x00_write_flash_byte(ha, 0x5555,
1734 0xa0);
1735 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1736 /* Then erase it */
1737 if (qla2x00_erase_flash_sector(ha,
1738 addr, sec_mask, man_id,
1739 flash_id)) {
1740 rval = QLA_FUNCTION_FAILED;
1741 break;
1742 }
1743 if (man_id == 0x01 && flash_id == 0x6d)
1744 sec_number++;
1745 }
1746 }
1747
1748 if (man_id == 0x01 && flash_id == 0x6d) {
1749 if (sec_number == 1 &&
1750 addr == (rest_addr - 1)) {
1751 rest_addr = 0x0fff;
1752 sec_mask = 0x1f000;
1753 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1754 rest_addr = 0x3fff;
1755 sec_mask = 0x1c000;
1756 }
1757 }
1758
1759 if (qla2x00_program_flash_address(ha, addr, data,
1760 man_id, flash_id)) {
1761 rval = QLA_FUNCTION_FAILED;
1762 break;
1763 }
40a2e34a 1764 cond_resched();
854165f4
AV		 1765 }
1766 } while (0);
1767 qla2x00_flash_disable(ha);
854165f4
AV		 1768
1769 /* Resume HBA. */
1770 qla2x00_resume_hba(ha);
1771
1772 return rval;
1773}
1774
1775uint8_t *
1776qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1777 uint32_t offset, uint32_t length)
1778{
1779 /* Suspend HBA. */
1780 scsi_block_requests(ha->host);
854165f4
AV		 1781 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1782
1783 /* Go with read. */
1784 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1785
1786 /* Resume HBA. */
1787 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
854165f4
AV		 1788 scsi_unblock_requests(ha->host);
1789
1790 return buf;
1791}
1792
1793int
1794qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1795 uint32_t offset, uint32_t length)
1796{
1797 int rval;
1798
1799 /* Suspend HBA. */
1800 scsi_block_requests(ha->host);
854165f4
AV		 1801 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1802
1803 /* Go with write. */
1804 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1805 length >> 2);
1806
1807 /* Resume HBA -- RISC reset needed. */
1808 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1809 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
39a11240 1810 qla2xxx_wake_dpc(ha);
854165f4
AV		 1811 qla2x00_wait_for_hba_online(ha);
1812 scsi_unblock_requests(ha->host);
1813
1814 return rval;
1815}
30c47662 1816
338c9161
AV		 1817uint8_t *
1818qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1819 uint32_t offset, uint32_t length)
1820{
1821 int rval;
1822 dma_addr_t optrom_dma;
1823 void *optrom;
1824 uint8_t *pbuf;
1825 uint32_t faddr, left, burst;
1826
b7cc176c 1827 if (offset & 0xfff)
338c9161
AV		 1828 goto slow_read;
1829 if (length < OPTROM_BURST_SIZE)
1830 goto slow_read;
1831
1832 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1833 &optrom_dma, GFP_KERNEL);
1834 if (!optrom) {
1835 qla_printk(KERN_DEBUG, ha,
1836 "Unable to allocate memory for optrom burst read "
1837 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1838
1839 goto slow_read;
1840 }
1841
1842 pbuf = buf;
1843 faddr = offset >> 2;
1844 left = length >> 2;
1845 burst = OPTROM_BURST_DWORDS;
1846 while (left != 0) {
1847 if (burst > left)
1848 burst = left;
1849
1850 rval = qla2x00_dump_ram(ha, optrom_dma,
1851 flash_data_to_access_addr(faddr), burst);
1852 if (rval) {
1853 qla_printk(KERN_WARNING, ha,
1854 "Unable to burst-read optrom segment "
1855 "(%x/%x/%llx).\n", rval,
875baf3c
AM		 1856 flash_data_to_access_addr(faddr),
1857 (unsigned long long)optrom_dma);
338c9161
AV		 1858 qla_printk(KERN_WARNING, ha,
1859 "Reverting to slow-read.\n");
1860
1861 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1862 optrom, optrom_dma);
1863 goto slow_read;
1864 }
1865
1866 memcpy(pbuf, optrom, burst * 4);
1867
1868 left -= burst;
1869 faddr += burst;
1870 pbuf += burst * 4;
1871 }
1872
1873 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
1874 optrom_dma);
1875
1876 return buf;
1877
1878slow_read:
1879 return qla24xx_read_optrom_data(ha, buf, offset, length);
1880}
1881
30c47662
AV		 1882/**
1883 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1884 * @ha: HA context
1885 * @pcids: Pointer to the FCODE PCI data structure
1886 *
1887 * The process of retrieving the FCODE version information is at best
1888 * described as interesting.
1889 *
1890 * Within the first 100h bytes of the image an ASCII string is present
1891 * which contains several pieces of information including the FCODE
1892 * version. Unfortunately it seems the only reliable way to retrieve
1893 * the version is by scanning for another sentinel within the string,
1894 * the FCODE build date:
1895 *
1896 * ... 2.00.02 10/17/02 ...
1897 *
1898 * Returns QLA_SUCCESS on successful retrieval of version.
1899 */
1900static void
1901qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
1902{
1903 int ret = QLA_FUNCTION_FAILED;
1904 uint32_t istart, iend, iter, vend;
1905 uint8_t do_next, rbyte, *vbyte;
1906
1907 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1908
1909 /* Skip the PCI data structure. */
1910 istart = pcids +
1911 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
1912 qla2x00_read_flash_byte(ha, pcids + 0x0A));
1913 iend = istart + 0x100;
1914 do {
1915 /* Scan for the sentinel date string...eeewww. */
1916 do_next = 0;
1917 iter = istart;
1918 while ((iter < iend) && !do_next) {
1919 iter++;
1920 if (qla2x00_read_flash_byte(ha, iter) == '/') {
1921 if (qla2x00_read_flash_byte(ha, iter + 2) ==
1922 '/')
1923 do_next++;
1924 else if (qla2x00_read_flash_byte(ha,
1925 iter + 3) == '/')
1926 do_next++;
1927 }
1928 }
1929 if (!do_next)
1930 break;
1931
1932 /* Backtrack to previous ' ' (space). */
1933 do_next = 0;
1934 while ((iter > istart) && !do_next) {
1935 iter--;
1936 if (qla2x00_read_flash_byte(ha, iter) == ' ')
1937 do_next++;
1938 }
1939 if (!do_next)
1940 break;
1941
1942 /*
1943 * Mark end of version tag, and find previous ' ' (space) or
1944 * string length (recent FCODE images -- major hack ahead!!!).
1945 */
1946 vend = iter - 1;
1947 do_next = 0;
1948 while ((iter > istart) && !do_next) {
1949 iter--;
1950 rbyte = qla2x00_read_flash_byte(ha, iter);
1951 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
1952 do_next++;
1953 }
1954 if (!do_next)
1955 break;
1956
1957 /* Mark beginning of version tag, and copy data. */
1958 iter++;
1959 if ((vend - iter) &&
1960 ((vend - iter) < sizeof(ha->fcode_revision))) {
1961 vbyte = ha->fcode_revision;
1962 while (iter <= vend) {
1963 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
1964 iter++;
1965 }
1966 ret = QLA_SUCCESS;
1967 }
1968 } while (0);
1969
1970 if (ret != QLA_SUCCESS)
1971 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1972}
1973
1974int
1975qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
1976{
1977 int ret = QLA_SUCCESS;
1978 uint8_t code_type, last_image;
1979 uint32_t pcihdr, pcids;
1980 uint8_t *dbyte;
1981 uint16_t *dcode;
1982
1983 if (!ha->pio_address || !mbuf)
1984 return QLA_FUNCTION_FAILED;
1985
1986 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
1987 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
1988 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1989 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
1990
1991 qla2x00_flash_enable(ha);
1992
1993 /* Begin with first PCI expansion ROM header. */
1994 pcihdr = 0;
1995 last_image = 1;
1996 do {
1997 /* Verify PCI expansion ROM header. */
1998 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
1999 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2000 /* No signature */
2001 DEBUG2(printk("scsi(%ld): No matching ROM "
2002 "signature.\n", ha->host_no));
2003 ret = QLA_FUNCTION_FAILED;
2004 break;
2005 }
2006
2007 /* Locate PCI data structure. */
2008 pcids = pcihdr +
2009 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2010 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2011
2012 /* Validate signature of PCI data structure. */
2013 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2014 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2015 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2016 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2017 /* Incorrect header. */
2018 DEBUG2(printk("%s(): PCI data struct not found "
2019 "pcir_adr=%x.\n", __func__, pcids));
2020 ret = QLA_FUNCTION_FAILED;
2021 break;
2022 }
2023
2024 /* Read version */
2025 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2026 switch (code_type) {
2027 case ROM_CODE_TYPE_BIOS:
2028 /* Intel x86, PC-AT compatible. */
2029 ha->bios_revision[0] =
2030 qla2x00_read_flash_byte(ha, pcids + 0x12);
2031 ha->bios_revision[1] =
2032 qla2x00_read_flash_byte(ha, pcids + 0x13);
2033 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2034 ha->bios_revision[1], ha->bios_revision[0]));
2035 break;
2036 case ROM_CODE_TYPE_FCODE:
2037 /* Open Firmware standard for PCI (FCode). */
2038 /* Eeeewww... */
2039 qla2x00_get_fcode_version(ha, pcids);
2040 break;
2041 case ROM_CODE_TYPE_EFI:
2042 /* Extensible Firmware Interface (EFI). */
2043 ha->efi_revision[0] =
2044 qla2x00_read_flash_byte(ha, pcids + 0x12);
2045 ha->efi_revision[1] =
2046 qla2x00_read_flash_byte(ha, pcids + 0x13);
2047 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2048 ha->efi_revision[1], ha->efi_revision[0]));
2049 break;
2050 default:
2051 DEBUG2(printk("%s(): Unrecognized code type %x at "
2052 "pcids %x.\n", __func__, code_type, pcids));
2053 break;
2054 }
2055
2056 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2057
2058 /* Locate next PCI expansion ROM. */
2059 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2060 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2061 } while (!last_image);
2062
2063 if (IS_QLA2322(ha)) {
2064 /* Read firmware image information. */
2065 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2066 dbyte = mbuf;
2067 memset(dbyte, 0, 8);
2068 dcode = (uint16_t *)dbyte;
2069
2070 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10,
2071 8);
2072 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2073 __func__, ha->host_no));
2074 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2075
2076 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2077 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2078 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2079 dcode[3] == 0)) {
2080 DEBUG2(printk("%s(): Unrecognized fw revision at "
2081 "%x.\n", __func__, FA_RISC_CODE_ADDR * 4));
2082 } else {
2083 /* values are in big endian */
2084 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2085 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2086 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2087 }
2088 }
2089
2090 qla2x00_flash_disable(ha);
2091
2092 return ret;
2093}
2094
2095int
2096qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2097{
2098 int ret = QLA_SUCCESS;
2099 uint32_t pcihdr, pcids;
2100 uint32_t *dcode;
2101 uint8_t *bcode;
2102 uint8_t code_type, last_image;
2103 int i;
2104
2105 if (!mbuf)
2106 return QLA_FUNCTION_FAILED;
2107
2108 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2109 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2110 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2111 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2112
2113 dcode = mbuf;
2114
2115 /* Begin with first PCI expansion ROM header. */
2116 pcihdr = 0;
2117 last_image = 1;
2118 do {
2119 /* Verify PCI expansion ROM header. */
2120 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2121 bcode = mbuf + (pcihdr % 4);
2122 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2123 /* No signature */
2124 DEBUG2(printk("scsi(%ld): No matching ROM "
2125 "signature.\n", ha->host_no));
2126 ret = QLA_FUNCTION_FAILED;
2127 break;
2128 }
2129
2130 /* Locate PCI data structure. */
2131 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2132
2133 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2134 bcode = mbuf + (pcihdr % 4);
2135
2136 /* Validate signature of PCI data structure. */
2137 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2138 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2139 /* Incorrect header. */
2140 DEBUG2(printk("%s(): PCI data struct not found "
2141 "pcir_adr=%x.\n", __func__, pcids));
2142 ret = QLA_FUNCTION_FAILED;
2143 break;
2144 }
2145
2146 /* Read version */
2147 code_type = bcode[0x14];
2148 switch (code_type) {
2149 case ROM_CODE_TYPE_BIOS:
2150 /* Intel x86, PC-AT compatible. */
2151 ha->bios_revision[0] = bcode[0x12];
2152 ha->bios_revision[1] = bcode[0x13];
2153 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2154 ha->bios_revision[1], ha->bios_revision[0]));
2155 break;
2156 case ROM_CODE_TYPE_FCODE:
2157 /* Open Firmware standard for PCI (FCode). */
2158 ha->fcode_revision[0] = bcode[0x12];
2159 ha->fcode_revision[1] = bcode[0x13];
2160 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2161 ha->fcode_revision[1], ha->fcode_revision[0]));
2162 break;
2163 case ROM_CODE_TYPE_EFI:
2164 /* Extensible Firmware Interface (EFI). */
2165 ha->efi_revision[0] = bcode[0x12];
2166 ha->efi_revision[1] = bcode[0x13];
2167 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2168 ha->efi_revision[1], ha->efi_revision[0]));
2169 break;
2170 default:
2171 DEBUG2(printk("%s(): Unrecognized code type %x at "
2172 "pcids %x.\n", __func__, code_type, pcids));
2173 break;
2174 }
2175
2176 last_image = bcode[0x15] & BIT_7;
2177
2178 /* Locate next PCI expansion ROM. */
2179 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2180 } while (!last_image);
2181
2182 /* Read firmware image information. */
2183 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2184 dcode = mbuf;
2185
2186 qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4);
2187 for (i = 0; i < 4; i++)
2188 dcode[i] = be32_to_cpu(dcode[i]);
2189
2190 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2191 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2192 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2193 dcode[3] == 0)) {
2194 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2195 __func__, FA_RISC_CODE_ADDR));
2196 } else {
2197 ha->fw_revision[0] = dcode[0];
2198 ha->fw_revision[1] = dcode[1];
2199 ha->fw_revision[2] = dcode[2];
2200 ha->fw_revision[3] = dcode[3];
2201 }
2202
2203 return ret;
2204}
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