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[SCSI] minor bug fixes and cleanups
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / qla2xxx / qla_sup.c
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
1da177e4 4 *
fa90c54f
AV		 5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#include "qla_def.h"
8
9#include <linux/delay.h>
10#include <asm/uaccess.h>
11
12static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
13static void qla2x00_nv_deselect(scsi_qla_host_t *);
14static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
15
16/*
17 * NVRAM support routines
18 */
19
20/**
fa2a1ce5 21 * qla2x00_lock_nvram_access() -
1da177e4
LT		 22 * @ha: HA context
23 */
24void
25qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
26{
27 uint16_t data;
3d71644c 28 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 29
30 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
31 data = RD_REG_WORD(&reg->nvram);
32 while (data & NVR_BUSY) {
33 udelay(100);
34 data = RD_REG_WORD(&reg->nvram);
35 }
36
37 /* Lock resource */
38 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
39 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
40 udelay(5);
41 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
42 while ((data & BIT_0) == 0) {
43 /* Lock failed */
44 udelay(100);
45 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
46 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
47 udelay(5);
48 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
49 }
50 }
51}
52
53/**
fa2a1ce5 54 * qla2x00_unlock_nvram_access() -
1da177e4
LT		 55 * @ha: HA context
56 */
57void
58qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
59{
3d71644c 60 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 61
62 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
63 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
64 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
65 }
66}
67
1da177e4
LT		 68/**
69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
70 * request routine to get the word from NVRAM.
71 * @ha: HA context
72 * @addr: Address in NVRAM to read
73 *
74 * Returns the word read from nvram @addr.
75 */
76uint16_t
77qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
78{
79 uint16_t data;
80 uint32_t nv_cmd;
81
82 nv_cmd = addr << 16;
83 nv_cmd |= NV_READ_OP;
84 data = qla2x00_nvram_request(ha, nv_cmd);
85
86 return (data);
87}
88
89/**
90 * qla2x00_write_nvram_word() - Write NVRAM data.
91 * @ha: HA context
92 * @addr: Address in NVRAM to write
93 * @data: word to program
94 */
95void
96qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
97{
98 int count;
99 uint16_t word;
45aeaf1e 100 uint32_t nv_cmd, wait_cnt;
3d71644c 101 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 102
103 qla2x00_nv_write(ha, NVR_DATA_OUT);
104 qla2x00_nv_write(ha, 0);
105 qla2x00_nv_write(ha, 0);
106
107 for (word = 0; word < 8; word++)
108 qla2x00_nv_write(ha, NVR_DATA_OUT);
109
110 qla2x00_nv_deselect(ha);
111
112 /* Write data */
113 nv_cmd = (addr << 16) | NV_WRITE_OP;
114 nv_cmd |= data;
115 nv_cmd <<= 5;
116 for (count = 0; count < 27; count++) {
117 if (nv_cmd & BIT_31)
118 qla2x00_nv_write(ha, NVR_DATA_OUT);
119 else
120 qla2x00_nv_write(ha, 0);
121
122 nv_cmd <<= 1;
123 }
124
125 qla2x00_nv_deselect(ha);
126
127 /* Wait for NVRAM to become ready */
128 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 129 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 130 wait_cnt = NVR_WAIT_CNT;
1da177e4 131 do {
45aeaf1e
RA		 132 if (!--wait_cnt) {
133 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
134 __func__, ha->host_no));
135 break;
136 }
1da177e4
LT		 137 NVRAM_DELAY();
138 word = RD_REG_WORD(&reg->nvram);
139 } while ((word & NVR_DATA_IN) == 0);
140
141 qla2x00_nv_deselect(ha);
142
143 /* Disable writes */
144 qla2x00_nv_write(ha, NVR_DATA_OUT);
145 for (count = 0; count < 10; count++)
146 qla2x00_nv_write(ha, 0);
147
148 qla2x00_nv_deselect(ha);
149}
150
459c5378
AV		 151static int
152qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
153 uint32_t tmo)
154{
155 int ret, count;
156 uint16_t word;
157 uint32_t nv_cmd;
158 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
159
160 ret = QLA_SUCCESS;
161
162 qla2x00_nv_write(ha, NVR_DATA_OUT);
163 qla2x00_nv_write(ha, 0);
164 qla2x00_nv_write(ha, 0);
165
166 for (word = 0; word < 8; word++)
167 qla2x00_nv_write(ha, NVR_DATA_OUT);
168
169 qla2x00_nv_deselect(ha);
170
171 /* Write data */
172 nv_cmd = (addr << 16) | NV_WRITE_OP;
173 nv_cmd |= data;
174 nv_cmd <<= 5;
175 for (count = 0; count < 27; count++) {
176 if (nv_cmd & BIT_31)
177 qla2x00_nv_write(ha, NVR_DATA_OUT);
178 else
179 qla2x00_nv_write(ha, 0);
180
181 nv_cmd <<= 1;
182 }
183
184 qla2x00_nv_deselect(ha);
185
186 /* Wait for NVRAM to become ready */
187 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 188 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
459c5378
AV		 189 do {
190 NVRAM_DELAY();
191 word = RD_REG_WORD(&reg->nvram);
192 if (!--tmo) {
193 ret = QLA_FUNCTION_FAILED;
194 break;
195 }
196 } while ((word & NVR_DATA_IN) == 0);
197
198 qla2x00_nv_deselect(ha);
199
200 /* Disable writes */
201 qla2x00_nv_write(ha, NVR_DATA_OUT);
202 for (count = 0; count < 10; count++)
203 qla2x00_nv_write(ha, 0);
204
205 qla2x00_nv_deselect(ha);
206
207 return ret;
208}
209
1da177e4
LT		 210/**
211 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
212 * NVRAM.
213 * @ha: HA context
214 * @nv_cmd: NVRAM command
215 *
216 * Bit definitions for NVRAM command:
217 *
218 * Bit 26 = start bit
219 * Bit 25, 24 = opcode
220 * Bit 23-16 = address
221 * Bit 15-0 = write data
222 *
223 * Returns the word read from nvram @addr.
224 */
225static uint16_t
226qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
227{
228 uint8_t cnt;
3d71644c 229 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 230 uint16_t data = 0;
231 uint16_t reg_data;
232
233 /* Send command to NVRAM. */
234 nv_cmd <<= 5;
235 for (cnt = 0; cnt < 11; cnt++) {
236 if (nv_cmd & BIT_31)
237 qla2x00_nv_write(ha, NVR_DATA_OUT);
238 else
239 qla2x00_nv_write(ha, 0);
240 nv_cmd <<= 1;
241 }
242
243 /* Read data from NVRAM. */
244 for (cnt = 0; cnt < 16; cnt++) {
245 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
dcb36ce9 246 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1da177e4
LT		 247 NVRAM_DELAY();
248 data <<= 1;
249 reg_data = RD_REG_WORD(&reg->nvram);
250 if (reg_data & NVR_DATA_IN)
251 data |= BIT_0;
252 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
253 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
254 NVRAM_DELAY();
255 }
256
257 /* Deselect chip. */
258 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
259 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
260 NVRAM_DELAY();
261
262 return (data);
263}
264
265/**
266 * qla2x00_nv_write() - Clean NVRAM operations.
267 * @ha: HA context
268 */
269static void
270qla2x00_nv_deselect(scsi_qla_host_t *ha)
271{
3d71644c 272 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 273
274 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
275 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
276 NVRAM_DELAY();
277}
278
279/**
280 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
281 * @ha: HA context
282 * @data: Serial interface selector
283 */
284static void
285qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
286{
3d71644c 287 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 288
289 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
290 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
291 NVRAM_DELAY();
292 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
293 NVR_WRT_ENABLE);
294 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
295 NVRAM_DELAY();
296 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
297 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
298 NVRAM_DELAY();
299}
300
459c5378
AV		 301/**
302 * qla2x00_clear_nvram_protection() -
303 * @ha: HA context
304 */
305static int
306qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
307{
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 310 uint32_t word, wait_cnt;
459c5378
AV		 311 uint16_t wprot, wprot_old;
312
313 /* Clear NVRAM write protection. */
314 ret = QLA_FUNCTION_FAILED;
45aeaf1e
RA		 315
316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
459c5378 318 __constant_cpu_to_le16(0x1234), 100000);
45aeaf1e
RA		 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
320 if (stat != QLA_SUCCESS || wprot != 0x1234) {
459c5378
AV		 321 /* Write enable. */
322 qla2x00_nv_write(ha, NVR_DATA_OUT);
323 qla2x00_nv_write(ha, 0);
324 qla2x00_nv_write(ha, 0);
325 for (word = 0; word < 8; word++)
326 qla2x00_nv_write(ha, NVR_DATA_OUT);
327
328 qla2x00_nv_deselect(ha);
329
330 /* Enable protection register. */
331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
332 qla2x00_nv_write(ha, NVR_PR_ENABLE);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 for (word = 0; word < 8; word++)
335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
336
337 qla2x00_nv_deselect(ha);
338
339 /* Clear protection register (ffff is cleared). */
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 for (word = 0; word < 8; word++)
344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
345
346 qla2x00_nv_deselect(ha);
347
348 /* Wait for NVRAM to become ready. */
349 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 350 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 351 wait_cnt = NVR_WAIT_CNT;
459c5378 352 do {
45aeaf1e
RA		 353 if (!--wait_cnt) {
354 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
355 "ready...\n", __func__,
356 ha->host_no));
357 break;
358 }
459c5378
AV		 359 NVRAM_DELAY();
360 word = RD_REG_WORD(&reg->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
45aeaf1e
RA		 363 if (wait_cnt)
364 ret = QLA_SUCCESS;
459c5378 365 } else
45aeaf1e 366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
459c5378
AV		 367
368 return ret;
369}
370
371static void
372qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
373{
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
45aeaf1e 375 uint32_t word, wait_cnt;
459c5378
AV		 376
377 if (stat != QLA_SUCCESS)
378 return;
379
380 /* Set NVRAM write protection. */
381 /* Write enable. */
382 qla2x00_nv_write(ha, NVR_DATA_OUT);
383 qla2x00_nv_write(ha, 0);
384 qla2x00_nv_write(ha, 0);
385 for (word = 0; word < 8; word++)
386 qla2x00_nv_write(ha, NVR_DATA_OUT);
387
388 qla2x00_nv_deselect(ha);
389
390 /* Enable protection register. */
391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
392 qla2x00_nv_write(ha, NVR_PR_ENABLE);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 for (word = 0; word < 8; word++)
395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
396
397 qla2x00_nv_deselect(ha);
398
399 /* Enable protection register. */
400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
403 for (word = 0; word < 8; word++)
404 qla2x00_nv_write(ha, NVR_PR_ENABLE);
405
406 qla2x00_nv_deselect(ha);
407
408 /* Wait for NVRAM to become ready. */
409 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
dcb36ce9 410 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
45aeaf1e 411 wait_cnt = NVR_WAIT_CNT;
459c5378 412 do {
45aeaf1e
RA		 413 if (!--wait_cnt) {
414 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
415 __func__, ha->host_no));
416 break;
417 }
459c5378
AV		 418 NVRAM_DELAY();
419 word = RD_REG_WORD(&reg->nvram);
420 } while ((word & NVR_DATA_IN) == 0);
421}
422
423
424/*****************************************************************************/
425/* Flash Manipulation Routines */
426/*****************************************************************************/
427
428static inline uint32_t
429flash_conf_to_access_addr(uint32_t faddr)
430{
431 return FARX_ACCESS_FLASH_CONF | faddr;
432}
433
434static inline uint32_t
435flash_data_to_access_addr(uint32_t faddr)
436{
437 return FARX_ACCESS_FLASH_DATA | faddr;
438}
439
440static inline uint32_t
441nvram_conf_to_access_addr(uint32_t naddr)
442{
443 return FARX_ACCESS_NVRAM_CONF | naddr;
444}
445
446static inline uint32_t
447nvram_data_to_access_addr(uint32_t naddr)
448{
449 return FARX_ACCESS_NVRAM_DATA | naddr;
450}
451
452uint32_t
453qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
454{
455 int rval;
456 uint32_t cnt, data;
457 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458
459 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
460 /* Wait for READ cycle to complete. */
461 rval = QLA_SUCCESS;
462 for (cnt = 3000;
463 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
464 rval == QLA_SUCCESS; cnt--) {
465 if (cnt)
466 udelay(10);
467 else
468 rval = QLA_FUNCTION_TIMEOUT;
469 }
470
471 /* TODO: What happens if we time out? */
472 data = 0xDEADDEAD;
473 if (rval == QLA_SUCCESS)
474 data = RD_REG_DWORD(&reg->flash_data);
475
476 return data;
477}
478
479uint32_t *
480qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
481 uint32_t dwords)
482{
483 uint32_t i;
459c5378
AV		 484
485 /* Dword reads to flash. */
486 for (i = 0; i < dwords; i++, faddr++)
487 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
488 flash_data_to_access_addr(faddr)));
489
459c5378
AV		 490 return dwptr;
491}
492
493int
494qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
495{
496 int rval;
497 uint32_t cnt;
498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
499
500 WRT_REG_DWORD(&reg->flash_data, data);
501 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
502 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
503 /* Wait for Write cycle to complete. */
504 rval = QLA_SUCCESS;
505 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
506 rval == QLA_SUCCESS; cnt--) {
507 if (cnt)
508 udelay(10);
509 else
510 rval = QLA_FUNCTION_TIMEOUT;
511 }
512 return rval;
513}
514
515void
516qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
517 uint8_t *flash_id)
518{
519 uint32_t ids;
520
521 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
522 *man_id = LSB(ids);
523 *flash_id = MSB(ids);
45aeaf1e
RA		 524
525 /* Check if man_id and flash_id are valid. */
526 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
527 /* Read information using 0x9f opcode
528 * Device ID, Mfg ID would be read in the format:
529 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
530 * Example: ATMEL 0x00 01 45 1F
531 * Extract MFG and Dev ID from last two bytes.
532 */
533 ids = qla24xx_read_flash_dword(ha,
534 flash_data_to_access_addr(0xd009f));
535 *man_id = LSB(ids);
536 *flash_id = MSB(ids);
537 }
459c5378
AV		 538}
539
540int
541qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
542 uint32_t dwords)
543{
544 int ret;
545 uint32_t liter;
45aeaf1e
RA		 546 uint32_t sec_mask, rest_addr, conf_addr, sec_end_mask;
547 uint32_t fdata, findex ;
459c5378
AV		 548 uint8_t man_id, flash_id;
549 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
550
551 ret = QLA_SUCCESS;
552
459c5378
AV		 553 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
554 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
555 ha->host_no, man_id, flash_id));
556
45aeaf1e 557 sec_end_mask = 0;
459c5378
AV		 558 conf_addr = flash_conf_to_access_addr(0x03d8);
559 switch (man_id) {
fa2a1ce5 560 case 0xbf: /* STT flash. */
459c5378
AV		 561 rest_addr = 0x1fff;
562 sec_mask = 0x3e000;
563 if (flash_id == 0x80)
564 conf_addr = flash_conf_to_access_addr(0x0352);
565 break;
fa2a1ce5 566 case 0x13: /* ST M25P80. */
459c5378
AV		 567 rest_addr = 0x3fff;
568 sec_mask = 0x3c000;
569 break;
45aeaf1e
RA		 570 case 0x1f: // Atmel 26DF081A
571 rest_addr = 0x0fff;
572 sec_mask = 0xff000;
573 sec_end_mask = 0x003ff;
574 conf_addr = flash_conf_to_access_addr(0x0320);
575 break;
459c5378 576 default:
fa2a1ce5 577 /* Default to 64 kb sector size. */
459c5378
AV		 578 rest_addr = 0x3fff;
579 sec_mask = 0x3c000;
580 break;
581 }
582
583 /* Enable flash write. */
584 WRT_REG_DWORD(&reg->ctrl_status,
585 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
586 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
587
588 /* Disable flash write-protection. */
589 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
45aeaf1e
RA		 590 /* Some flash parts need an additional zero-write to clear bits.*/
591 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
459c5378
AV		 592
593 do { /* Loop once to provide quick error exit. */
594 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
45aeaf1e
RA		 595 if (man_id == 0x1f) {
596 findex = faddr << 2;
597 fdata = findex & sec_mask;
598 } else {
599 findex = faddr;
600 fdata = (findex & sec_mask) << 2;
601 }
602
459c5378 603 /* Are we at the beginning of a sector? */
45aeaf1e
RA		 604 if ((findex & rest_addr) == 0) {
605 /*
606 * Do sector unprotect at 4K boundry for Atmel
607 * part.
608 */
609 if (man_id == 0x1f)
610 qla24xx_write_flash_dword(ha,
611 flash_conf_to_access_addr(0x0339),
612 (fdata & 0xff00) | ((fdata << 16) &
613 0xff0000) | ((fdata >> 16) & 0xff));
459c5378
AV		 614 fdata = (faddr & sec_mask) << 2;
615 ret = qla24xx_write_flash_dword(ha, conf_addr,
616 (fdata & 0xff00) |((fdata << 16) &
617 0xff0000) | ((fdata >> 16) & 0xff));
618 if (ret != QLA_SUCCESS) {
619 DEBUG9(printk("%s(%ld) Unable to flash "
620 "sector: address=%x.\n", __func__,
621 ha->host_no, faddr));
622 break;
623 }
624 }
625 ret = qla24xx_write_flash_dword(ha,
626 flash_data_to_access_addr(faddr),
627 cpu_to_le32(*dwptr));
628 if (ret != QLA_SUCCESS) {
629 DEBUG9(printk("%s(%ld) Unable to program flash "
630 "address=%x data=%x.\n", __func__,
631 ha->host_no, faddr, *dwptr));
632 break;
633 }
45aeaf1e
RA		 634
635 /* Do sector protect at 4K boundry for Atmel part. */
636 if (man_id == 0x1f &&
637 ((faddr & sec_end_mask) == 0x3ff))
638 qla24xx_write_flash_dword(ha,
639 flash_conf_to_access_addr(0x0336),
640 (fdata & 0xff00) | ((fdata << 16) &
641 0xff0000) | ((fdata >> 16) & 0xff));
459c5378
AV		 642 }
643 } while (0);
644
e978010c
AV		 645 /* Enable flash write-protection. */
646 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
647
459c5378
AV		 648 /* Disable flash write. */
649 WRT_REG_DWORD(&reg->ctrl_status,
650 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
651 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
652
459c5378
AV		 653 return ret;
654}
655
656uint8_t *
657qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
658 uint32_t bytes)
659{
660 uint32_t i;
661 uint16_t *wptr;
662
663 /* Word reads to NVRAM via registers. */
664 wptr = (uint16_t *)buf;
665 qla2x00_lock_nvram_access(ha);
666 for (i = 0; i < bytes >> 1; i++, naddr++)
667 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
668 naddr));
669 qla2x00_unlock_nvram_access(ha);
670
671 return buf;
672}
673
674uint8_t *
675qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
676 uint32_t bytes)
677{
678 uint32_t i;
679 uint32_t *dwptr;
459c5378
AV		 680
681 /* Dword reads to flash. */
682 dwptr = (uint32_t *)buf;
683 for (i = 0; i < bytes >> 2; i++, naddr++)
684 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
685 nvram_data_to_access_addr(naddr)));
686
459c5378
AV		 687 return buf;
688}
689
690int
691qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
692 uint32_t bytes)
693{
694 int ret, stat;
695 uint32_t i;
696 uint16_t *wptr;
697
698 ret = QLA_SUCCESS;
699
700 qla2x00_lock_nvram_access(ha);
701
702 /* Disable NVRAM write-protection. */
703 stat = qla2x00_clear_nvram_protection(ha);
704
705 wptr = (uint16_t *)buf;
706 for (i = 0; i < bytes >> 1; i++, naddr++) {
707 qla2x00_write_nvram_word(ha, naddr,
708 cpu_to_le16(*wptr));
709 wptr++;
710 }
711
712 /* Enable NVRAM write-protection. */
713 qla2x00_set_nvram_protection(ha, stat);
714
715 qla2x00_unlock_nvram_access(ha);
716
717 return ret;
718}
719
720int
721qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
722 uint32_t bytes)
723{
724 int ret;
725 uint32_t i;
726 uint32_t *dwptr;
727 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
728
729 ret = QLA_SUCCESS;
730
459c5378
AV		 731 /* Enable flash write. */
732 WRT_REG_DWORD(&reg->ctrl_status,
733 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
734 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
735
736 /* Disable NVRAM write-protection. */
737 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
738 0);
739 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
740 0);
741
742 /* Dword writes to flash. */
743 dwptr = (uint32_t *)buf;
744 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
745 ret = qla24xx_write_flash_dword(ha,
746 nvram_data_to_access_addr(naddr),
747 cpu_to_le32(*dwptr));
748 if (ret != QLA_SUCCESS) {
749 DEBUG9(printk("%s(%ld) Unable to program "
750 "nvram address=%x data=%x.\n", __func__,
751 ha->host_no, naddr, *dwptr));
752 break;
753 }
754 }
755
756 /* Enable NVRAM write-protection. */
757 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
758 0x8c);
759
760 /* Disable flash write. */
761 WRT_REG_DWORD(&reg->ctrl_status,
762 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
763 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
764
459c5378
AV		 765 return ret;
766}
f6df144c
AV		 767
768
769static inline void
770qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
771{
772 if (IS_QLA2322(ha)) {
773 /* Flip all colors. */
774 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
775 /* Turn off. */
776 ha->beacon_color_state = 0;
777 *pflags = GPIO_LED_ALL_OFF;
778 } else {
779 /* Turn on. */
780 ha->beacon_color_state = QLA_LED_ALL_ON;
781 *pflags = GPIO_LED_RGA_ON;
782 }
783 } else {
784 /* Flip green led only. */
785 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
786 /* Turn off. */
787 ha->beacon_color_state = 0;
788 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
789 } else {
790 /* Turn on. */
791 ha->beacon_color_state = QLA_LED_GRN_ON;
792 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
793 }
794 }
795}
796
797void
798qla2x00_beacon_blink(struct scsi_qla_host *ha)
799{
800 uint16_t gpio_enable;
801 uint16_t gpio_data;
802 uint16_t led_color = 0;
803 unsigned long flags;
804 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
805
806 if (ha->pio_address)
807 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
808
809 spin_lock_irqsave(&ha->hardware_lock, flags);
810
811 /* Save the Original GPIOE. */
812 if (ha->pio_address) {
813 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
814 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
815 } else {
816 gpio_enable = RD_REG_WORD(&reg->gpioe);
817 gpio_data = RD_REG_WORD(&reg->gpiod);
818 }
819
820 /* Set the modified gpio_enable values */
821 gpio_enable |= GPIO_LED_MASK;
822
823 if (ha->pio_address) {
824 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
825 } else {
826 WRT_REG_WORD(&reg->gpioe, gpio_enable);
827 RD_REG_WORD(&reg->gpioe);
828 }
829
830 qla2x00_flip_colors(ha, &led_color);
831
832 /* Clear out any previously set LED color. */
833 gpio_data &= ~GPIO_LED_MASK;
834
835 /* Set the new input LED color to GPIOD. */
836 gpio_data |= led_color;
837
838 /* Set the modified gpio_data values */
839 if (ha->pio_address) {
840 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
841 } else {
842 WRT_REG_WORD(&reg->gpiod, gpio_data);
843 RD_REG_WORD(&reg->gpiod);
844 }
845
846 spin_unlock_irqrestore(&ha->hardware_lock, flags);
847}
848
849int
850qla2x00_beacon_on(struct scsi_qla_host *ha)
851{
852 uint16_t gpio_enable;
853 uint16_t gpio_data;
854 unsigned long flags;
855 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
856
857 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
858 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
859
860 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
861 qla_printk(KERN_WARNING, ha,
862 "Unable to update fw options (beacon on).\n");
863 return QLA_FUNCTION_FAILED;
864 }
865
866 if (ha->pio_address)
867 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
868
869 /* Turn off LEDs. */
870 spin_lock_irqsave(&ha->hardware_lock, flags);
871 if (ha->pio_address) {
872 gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
873 gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
874 } else {
875 gpio_enable = RD_REG_WORD(&reg->gpioe);
876 gpio_data = RD_REG_WORD(&reg->gpiod);
877 }
878 gpio_enable |= GPIO_LED_MASK;
879
880 /* Set the modified gpio_enable values. */
881 if (ha->pio_address) {
882 WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
883 } else {
884 WRT_REG_WORD(&reg->gpioe, gpio_enable);
885 RD_REG_WORD(&reg->gpioe);
886 }
887
888 /* Clear out previously set LED colour. */
889 gpio_data &= ~GPIO_LED_MASK;
890 if (ha->pio_address) {
891 WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
892 } else {
893 WRT_REG_WORD(&reg->gpiod, gpio_data);
894 RD_REG_WORD(&reg->gpiod);
895 }
896 spin_unlock_irqrestore(&ha->hardware_lock, flags);
897
898 /*
899 * Let the per HBA timer kick off the blinking process based on
900 * the following flags. No need to do anything else now.
901 */
902 ha->beacon_blink_led = 1;
903 ha->beacon_color_state = 0;
904
905 return QLA_SUCCESS;
906}
907
908int
909qla2x00_beacon_off(struct scsi_qla_host *ha)
910{
911 int rval = QLA_SUCCESS;
912
913 ha->beacon_blink_led = 0;
914
915 /* Set the on flag so when it gets flipped it will be off. */
916 if (IS_QLA2322(ha))
917 ha->beacon_color_state = QLA_LED_ALL_ON;
918 else
919 ha->beacon_color_state = QLA_LED_GRN_ON;
920
921 ha->isp_ops.beacon_blink(ha); /* This turns green LED off */
922
923 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
924 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
925
926 rval = qla2x00_set_fw_options(ha, ha->fw_options);
927 if (rval != QLA_SUCCESS)
928 qla_printk(KERN_WARNING, ha,
929 "Unable to update fw options (beacon off).\n");
930 return rval;
931}
932
933
934static inline void
935qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
936{
937 /* Flip all colors. */
938 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
939 /* Turn off. */
940 ha->beacon_color_state = 0;
941 *pflags = 0;
942 } else {
943 /* Turn on. */
944 ha->beacon_color_state = QLA_LED_ALL_ON;
945 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
946 }
947}
948
949void
950qla24xx_beacon_blink(struct scsi_qla_host *ha)
951{
952 uint16_t led_color = 0;
953 uint32_t gpio_data;
954 unsigned long flags;
955 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
956
957 /* Save the Original GPIOD. */
958 spin_lock_irqsave(&ha->hardware_lock, flags);
959 gpio_data = RD_REG_DWORD(&reg->gpiod);
960
961 /* Enable the gpio_data reg for update. */
962 gpio_data |= GPDX_LED_UPDATE_MASK;
963
964 WRT_REG_DWORD(&reg->gpiod, gpio_data);
965 gpio_data = RD_REG_DWORD(&reg->gpiod);
966
967 /* Set the color bits. */
968 qla24xx_flip_colors(ha, &led_color);
969
970 /* Clear out any previously set LED color. */
971 gpio_data &= ~GPDX_LED_COLOR_MASK;
972
973 /* Set the new input LED color to GPIOD. */
974 gpio_data |= led_color;
975
976 /* Set the modified gpio_data values. */
977 WRT_REG_DWORD(&reg->gpiod, gpio_data);
978 gpio_data = RD_REG_DWORD(&reg->gpiod);
979 spin_unlock_irqrestore(&ha->hardware_lock, flags);
980}
981
982int
983qla24xx_beacon_on(struct scsi_qla_host *ha)
984{
985 uint32_t gpio_data;
986 unsigned long flags;
987 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
988
989 if (ha->beacon_blink_led == 0) {
990 /* Enable firmware for update */
991 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
992
993 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
994 return QLA_FUNCTION_FAILED;
995
996 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
997 QLA_SUCCESS) {
998 qla_printk(KERN_WARNING, ha,
999 "Unable to update fw options (beacon on).\n");
1000 return QLA_FUNCTION_FAILED;
1001 }
1002
1003 spin_lock_irqsave(&ha->hardware_lock, flags);
1004 gpio_data = RD_REG_DWORD(&reg->gpiod);
1005
1006 /* Enable the gpio_data reg for update. */
1007 gpio_data |= GPDX_LED_UPDATE_MASK;
1008 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1009 RD_REG_DWORD(&reg->gpiod);
1010
1011 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1012 }
1013
1014 /* So all colors blink together. */
1015 ha->beacon_color_state = 0;
1016
1017 /* Let the per HBA timer kick off the blinking process. */
1018 ha->beacon_blink_led = 1;
1019
1020 return QLA_SUCCESS;
1021}
1022
1023int
1024qla24xx_beacon_off(struct scsi_qla_host *ha)
1025{
1026 uint32_t gpio_data;
1027 unsigned long flags;
1028 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1029
1030 ha->beacon_blink_led = 0;
1031 ha->beacon_color_state = QLA_LED_ALL_ON;
1032
1033 ha->isp_ops.beacon_blink(ha); /* Will flip to all off. */
1034
1035 /* Give control back to firmware. */
1036 spin_lock_irqsave(&ha->hardware_lock, flags);
1037 gpio_data = RD_REG_DWORD(&reg->gpiod);
1038
1039 /* Disable the gpio_data reg for update. */
1040 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1041 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1042 RD_REG_DWORD(&reg->gpiod);
1043 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1044
1045 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1046
1047 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1048 qla_printk(KERN_WARNING, ha,
1049 "Unable to update fw options (beacon off).\n");
1050 return QLA_FUNCTION_FAILED;
1051 }
1052
1053 if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1054 qla_printk(KERN_WARNING, ha,
1055 "Unable to get fw options (beacon off).\n");
1056 return QLA_FUNCTION_FAILED;
1057 }
1058
1059 return QLA_SUCCESS;
1060}
854165f4
AV		 1061
1062
1063/*
1064 * Flash support routines
1065 */
1066
1067/**
1068 * qla2x00_flash_enable() - Setup flash for reading and writing.
1069 * @ha: HA context
1070 */
1071static void
1072qla2x00_flash_enable(scsi_qla_host_t *ha)
1073{
1074 uint16_t data;
1075 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1076
1077 data = RD_REG_WORD(&reg->ctrl_status);
1078 data |= CSR_FLASH_ENABLE;
1079 WRT_REG_WORD(&reg->ctrl_status, data);
1080 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1081}
1082
1083/**
1084 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1085 * @ha: HA context
1086 */
1087static void
1088qla2x00_flash_disable(scsi_qla_host_t *ha)
1089{
1090 uint16_t data;
1091 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1092
1093 data = RD_REG_WORD(&reg->ctrl_status);
1094 data &= ~(CSR_FLASH_ENABLE);
1095 WRT_REG_WORD(&reg->ctrl_status, data);
1096 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1097}
1098
1099/**
1100 * qla2x00_read_flash_byte() - Reads a byte from flash
1101 * @ha: HA context
1102 * @addr: Address in flash to read
1103 *
1104 * A word is read from the chip, but, only the lower byte is valid.
1105 *
1106 * Returns the byte read from flash @addr.
1107 */
1108static uint8_t
1109qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1110{
1111 uint16_t data;
1112 uint16_t bank_select;
1113 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1114
1115 bank_select = RD_REG_WORD(&reg->ctrl_status);
1116
1117 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1118 /* Specify 64K address range: */
1119 /* clear out Module Select and Flash Address bits [19:16]. */
1120 bank_select &= ~0xf8;
1121 bank_select |= addr >> 12 & 0xf0;
1122 bank_select |= CSR_FLASH_64K_BANK;
1123 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1124 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1125
1126 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1127 data = RD_REG_WORD(&reg->flash_data);
1128
1129 return (uint8_t)data;
1130 }
1131
1132 /* Setup bit 16 of flash address. */
1133 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1134 bank_select |= CSR_FLASH_64K_BANK;
1135 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1136 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1137 } else if (((addr & BIT_16) == 0) &&
1138 (bank_select & CSR_FLASH_64K_BANK)) {
1139 bank_select &= ~(CSR_FLASH_64K_BANK);
1140 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1141 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1142 }
1143
1144 /* Always perform IO mapped accesses to the FLASH registers. */
1145 if (ha->pio_address) {
1146 uint16_t data2;
1147
1148 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1149 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1150 do {
1151 data = RD_REG_WORD_PIO(&reg->flash_data);
1152 barrier();
1153 cpu_relax();
1154 data2 = RD_REG_WORD_PIO(&reg->flash_data);
1155 } while (data != data2);
1156 } else {
1157 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1158 data = qla2x00_debounce_register(&reg->flash_data);
1159 }
1160
1161 return (uint8_t)data;
1162}
1163
1164/**
1165 * qla2x00_write_flash_byte() - Write a byte to flash
1166 * @ha: HA context
1167 * @addr: Address in flash to write
1168 * @data: Data to write
1169 */
1170static void
1171qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1172{
1173 uint16_t bank_select;
1174 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1175
1176 bank_select = RD_REG_WORD(&reg->ctrl_status);
1177 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1178 /* Specify 64K address range: */
1179 /* clear out Module Select and Flash Address bits [19:16]. */
1180 bank_select &= ~0xf8;
1181 bank_select |= addr >> 12 & 0xf0;
1182 bank_select |= CSR_FLASH_64K_BANK;
1183 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1184 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1185
1186 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1187 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1188 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1189 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1190
1191 return;
1192 }
1193
1194 /* Setup bit 16 of flash address. */
1195 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1196 bank_select |= CSR_FLASH_64K_BANK;
1197 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1198 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1199 } else if (((addr & BIT_16) == 0) &&
1200 (bank_select & CSR_FLASH_64K_BANK)) {
1201 bank_select &= ~(CSR_FLASH_64K_BANK);
1202 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1203 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1204 }
1205
1206 /* Always perform IO mapped accesses to the FLASH registers. */
1207 if (ha->pio_address) {
1208 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1209 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1210 WRT_REG_WORD_PIO(&reg->flash_data, (uint16_t)data);
1211 } else {
1212 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1213 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1214 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1215 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1216 }
1217}
1218
1219/**
1220 * qla2x00_poll_flash() - Polls flash for completion.
1221 * @ha: HA context
1222 * @addr: Address in flash to poll
1223 * @poll_data: Data to be polled
1224 * @man_id: Flash manufacturer ID
1225 * @flash_id: Flash ID
1226 *
1227 * This function polls the device until bit 7 of what is read matches data
1228 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1229 * out (a fatal error). The flash book recommeds reading bit 7 again after
1230 * reading bit 5 as a 1.
1231 *
1232 * Returns 0 on success, else non-zero.
1233 */
1234static int
1235qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1236 uint8_t man_id, uint8_t flash_id)
1237{
1238 int status;
1239 uint8_t flash_data;
1240 uint32_t cnt;
1241
1242 status = 1;
1243
1244 /* Wait for 30 seconds for command to finish. */
1245 poll_data &= BIT_7;
1246 for (cnt = 3000000; cnt; cnt--) {
1247 flash_data = qla2x00_read_flash_byte(ha, addr);
1248 if ((flash_data & BIT_7) == poll_data) {
1249 status = 0;
1250 break;
1251 }
1252
1253 if (man_id != 0x40 && man_id != 0xda) {
1254 if ((flash_data & BIT_5) && cnt > 2)
1255 cnt = 2;
1256 }
1257 udelay(10);
1258 barrier();
1259 }
1260 return status;
1261}
1262
854165f4
AV		 1263/**
1264 * qla2x00_program_flash_address() - Programs a flash address
1265 * @ha: HA context
1266 * @addr: Address in flash to program
1267 * @data: Data to be written in flash
1268 * @man_id: Flash manufacturer ID
1269 * @flash_id: Flash ID
1270 *
1271 * Returns 0 on success, else non-zero.
1272 */
1273static int
1274qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1275 uint8_t man_id, uint8_t flash_id)
1276{
1277 /* Write Program Command Sequence. */
1278 if (IS_OEM_001(ha)) {
1279 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1280 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1281 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1282 qla2x00_write_flash_byte(ha, addr, data);
1283 } else {
1284 if (man_id == 0xda && flash_id == 0xc1) {
1285 qla2x00_write_flash_byte(ha, addr, data);
1286 if (addr & 0x7e)
1287 return 0;
1288 } else {
1289 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1290 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1291 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1292 qla2x00_write_flash_byte(ha, addr, data);
1293 }
1294 }
1295
1296 udelay(150);
1297
1298 /* Wait for write to complete. */
1299 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1300}
1301
1302/**
1303 * qla2x00_erase_flash() - Erase the flash.
1304 * @ha: HA context
1305 * @man_id: Flash manufacturer ID
1306 * @flash_id: Flash ID
1307 *
1308 * Returns 0 on success, else non-zero.
1309 */
1310static int
1311qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1312{
1313 /* Individual Sector Erase Command Sequence */
1314 if (IS_OEM_001(ha)) {
1315 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1316 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1317 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1318 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1319 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1320 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1321 } else {
1322 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1323 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1324 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1325 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1326 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1327 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1328 }
1329
1330 udelay(150);
1331
1332 /* Wait for erase to complete. */
1333 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1334}
1335
1336/**
1337 * qla2x00_erase_flash_sector() - Erase a flash sector.
1338 * @ha: HA context
1339 * @addr: Flash sector to erase
1340 * @sec_mask: Sector address mask
1341 * @man_id: Flash manufacturer ID
1342 * @flash_id: Flash ID
1343 *
1344 * Returns 0 on success, else non-zero.
1345 */
1346static int
1347qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1348 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1349{
1350 /* Individual Sector Erase Command Sequence */
1351 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1352 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1353 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1354 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1355 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1356 if (man_id == 0x1f && flash_id == 0x13)
1357 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1358 else
1359 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1360
1361 udelay(150);
1362
1363 /* Wait for erase to complete. */
1364 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1365}
1366
1367/**
1368 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1369 * @man_id: Flash manufacturer ID
1370 * @flash_id: Flash ID
1371 */
1372static void
1373qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1374 uint8_t *flash_id)
1375{
1376 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1377 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1378 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1379 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1380 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1381 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1382 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1383 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1384}
1385
1386
1387static inline void
1388qla2x00_suspend_hba(struct scsi_qla_host *ha)
1389{
1390 int cnt;
1391 unsigned long flags;
1392 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1393
1394 /* Suspend HBA. */
1395 scsi_block_requests(ha->host);
1396 ha->isp_ops.disable_intrs(ha);
1397 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1398
1399 /* Pause RISC. */
1400 spin_lock_irqsave(&ha->hardware_lock, flags);
1401 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1402 RD_REG_WORD(&reg->hccr);
1403 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1404 for (cnt = 0; cnt < 30000; cnt++) {
1405 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1406 break;
1407 udelay(100);
1408 }
1409 } else {
1410 udelay(10);
1411 }
1412 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1413}
1414
1415static inline void
1416qla2x00_resume_hba(struct scsi_qla_host *ha)
1417{
1418 /* Resume HBA. */
1419 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1420 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
39a11240 1421 qla2xxx_wake_dpc(ha);
854165f4
AV		 1422 qla2x00_wait_for_hba_online(ha);
1423 scsi_unblock_requests(ha->host);
1424}
1425
1426uint8_t *
1427qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1428 uint32_t offset, uint32_t length)
1429{
1430 unsigned long flags;
1431 uint32_t addr, midpoint;
1432 uint8_t *data;
1433 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1434
1435 /* Suspend HBA. */
1436 qla2x00_suspend_hba(ha);
1437
1438 /* Go with read. */
1439 spin_lock_irqsave(&ha->hardware_lock, flags);
1440 midpoint = ha->optrom_size / 2;
1441
1442 qla2x00_flash_enable(ha);
1443 WRT_REG_WORD(&reg->nvram, 0);
1444 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1445 for (addr = offset, data = buf; addr < length; addr++, data++) {
1446 if (addr == midpoint) {
1447 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1448 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1449 }
1450
1451 *data = qla2x00_read_flash_byte(ha, addr);
1452 }
1453 qla2x00_flash_disable(ha);
1454 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1455
1456 /* Resume HBA. */
1457 qla2x00_resume_hba(ha);
1458
1459 return buf;
1460}
1461
1462int
1463qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1464 uint32_t offset, uint32_t length)
1465{
1466
1467 int rval;
1468 unsigned long flags;
1469 uint8_t man_id, flash_id, sec_number, data;
1470 uint16_t wd;
1471 uint32_t addr, liter, sec_mask, rest_addr;
1472 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1473
1474 /* Suspend HBA. */
1475 qla2x00_suspend_hba(ha);
1476
1477 rval = QLA_SUCCESS;
1478 sec_number = 0;
1479
1480 /* Reset ISP chip. */
1481 spin_lock_irqsave(&ha->hardware_lock, flags);
1482 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1483 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1484
1485 /* Go with write. */
1486 qla2x00_flash_enable(ha);
1487 do { /* Loop once to provide quick error exit */
1488 /* Structure of flash memory based on manufacturer */
1489 if (IS_OEM_001(ha)) {
1490 /* OEM variant with special flash part. */
1491 man_id = flash_id = 0;
1492 rest_addr = 0xffff;
1493 sec_mask = 0x10000;
1494 goto update_flash;
1495 }
1496 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1497 switch (man_id) {
1498 case 0x20: /* ST flash. */
1499 if (flash_id == 0xd2 || flash_id == 0xe3) {
1500 /*
1501 * ST m29w008at part - 64kb sector size with
1502 * 32kb,8kb,8kb,16kb sectors at memory address
1503 * 0xf0000.
1504 */
1505 rest_addr = 0xffff;
1506 sec_mask = 0x10000;
1507 break;
1508 }
1509 /*
1510 * ST m29w010b part - 16kb sector size
1511 * Default to 16kb sectors
1512 */
1513 rest_addr = 0x3fff;
1514 sec_mask = 0x1c000;
1515 break;
1516 case 0x40: /* Mostel flash. */
1517 /* Mostel v29c51001 part - 512 byte sector size. */
1518 rest_addr = 0x1ff;
1519 sec_mask = 0x1fe00;
1520 break;
1521 case 0xbf: /* SST flash. */
1522 /* SST39sf10 part - 4kb sector size. */
1523 rest_addr = 0xfff;
1524 sec_mask = 0x1f000;
1525 break;
1526 case 0xda: /* Winbond flash. */
1527 /* Winbond W29EE011 part - 256 byte sector size. */
1528 rest_addr = 0x7f;
1529 sec_mask = 0x1ff80;
1530 break;
1531 case 0xc2: /* Macronix flash. */
1532 /* 64k sector size. */
1533 if (flash_id == 0x38 || flash_id == 0x4f) {
1534 rest_addr = 0xffff;
1535 sec_mask = 0x10000;
1536 break;
1537 }
1538 /* Fall through... */
1539
1540 case 0x1f: /* Atmel flash. */
1541 /* 512k sector size. */
1542 if (flash_id == 0x13) {
1543 rest_addr = 0x7fffffff;
1544 sec_mask = 0x80000000;
1545 break;
1546 }
1547 /* Fall through... */
1548
1549 case 0x01: /* AMD flash. */
1550 if (flash_id == 0x38 || flash_id == 0x40 ||
1551 flash_id == 0x4f) {
1552 /* Am29LV081 part - 64kb sector size. */
1553 /* Am29LV002BT part - 64kb sector size. */
1554 rest_addr = 0xffff;
1555 sec_mask = 0x10000;
1556 break;
1557 } else if (flash_id == 0x3e) {
1558 /*
1559 * Am29LV008b part - 64kb sector size with
1560 * 32kb,8kb,8kb,16kb sector at memory address
1561 * h0xf0000.
1562 */
1563 rest_addr = 0xffff;
1564 sec_mask = 0x10000;
1565 break;
1566 } else if (flash_id == 0x20 || flash_id == 0x6e) {
1567 /*
1568 * Am29LV010 part or AM29f010 - 16kb sector
1569 * size.
1570 */
1571 rest_addr = 0x3fff;
1572 sec_mask = 0x1c000;
1573 break;
1574 } else if (flash_id == 0x6d) {
1575 /* Am29LV001 part - 8kb sector size. */
1576 rest_addr = 0x1fff;
1577 sec_mask = 0x1e000;
1578 break;
1579 }
1580 default:
1581 /* Default to 16 kb sector size. */
1582 rest_addr = 0x3fff;
1583 sec_mask = 0x1c000;
1584 break;
1585 }
1586
1587update_flash:
1588 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1589 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1590 rval = QLA_FUNCTION_FAILED;
1591 break;
1592 }
1593 }
1594
1595 for (addr = offset, liter = 0; liter < length; liter++,
1596 addr++) {
1597 data = buf[liter];
1598 /* Are we at the beginning of a sector? */
1599 if ((addr & rest_addr) == 0) {
1600 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1601 if (addr >= 0x10000UL) {
1602 if (((addr >> 12) & 0xf0) &&
1603 ((man_id == 0x01 &&
1604 flash_id == 0x3e) ||
1605 (man_id == 0x20 &&
1606 flash_id == 0xd2))) {
1607 sec_number++;
1608 if (sec_number == 1) {
1609 rest_addr =
1610 0x7fff;
1611 sec_mask =
1612 0x18000;
1613 } else if (
1614 sec_number == 2 ||
1615 sec_number == 3) {
1616 rest_addr =
1617 0x1fff;
1618 sec_mask =
1619 0x1e000;
1620 } else if (
1621 sec_number == 4) {
1622 rest_addr =
1623 0x3fff;
1624 sec_mask =
1625 0x1c000;
1626 }
1627 }
1628 }
1629 } else if (addr == ha->optrom_size / 2) {
1630 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1631 RD_REG_WORD(&reg->nvram);
1632 }
1633
1634 if (flash_id == 0xda && man_id == 0xc1) {
1635 qla2x00_write_flash_byte(ha, 0x5555,
1636 0xaa);
1637 qla2x00_write_flash_byte(ha, 0x2aaa,
1638 0x55);
1639 qla2x00_write_flash_byte(ha, 0x5555,
1640 0xa0);
1641 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1642 /* Then erase it */
1643 if (qla2x00_erase_flash_sector(ha,
1644 addr, sec_mask, man_id,
1645 flash_id)) {
1646 rval = QLA_FUNCTION_FAILED;
1647 break;
1648 }
1649 if (man_id == 0x01 && flash_id == 0x6d)
1650 sec_number++;
1651 }
1652 }
1653
1654 if (man_id == 0x01 && flash_id == 0x6d) {
1655 if (sec_number == 1 &&
1656 addr == (rest_addr - 1)) {
1657 rest_addr = 0x0fff;
1658 sec_mask = 0x1f000;
1659 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1660 rest_addr = 0x3fff;
1661 sec_mask = 0x1c000;
1662 }
1663 }
1664
1665 if (qla2x00_program_flash_address(ha, addr, data,
1666 man_id, flash_id)) {
1667 rval = QLA_FUNCTION_FAILED;
1668 break;
1669 }
1670 }
1671 } while (0);
1672 qla2x00_flash_disable(ha);
1673 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1674
1675 /* Resume HBA. */
1676 qla2x00_resume_hba(ha);
1677
1678 return rval;
1679}
1680
1681uint8_t *
1682qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1683 uint32_t offset, uint32_t length)
1684{
1685 /* Suspend HBA. */
1686 scsi_block_requests(ha->host);
1687 ha->isp_ops.disable_intrs(ha);
1688 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1689
1690 /* Go with read. */
1691 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1692
1693 /* Resume HBA. */
1694 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1695 ha->isp_ops.enable_intrs(ha);
1696 scsi_unblock_requests(ha->host);
1697
1698 return buf;
1699}
1700
1701int
1702qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1703 uint32_t offset, uint32_t length)
1704{
1705 int rval;
1706
1707 /* Suspend HBA. */
1708 scsi_block_requests(ha->host);
1709 ha->isp_ops.disable_intrs(ha);
1710 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1711
1712 /* Go with write. */
1713 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1714 length >> 2);
1715
1716 /* Resume HBA -- RISC reset needed. */
1717 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1718 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
39a11240 1719 qla2xxx_wake_dpc(ha);
854165f4
AV		 1720 qla2x00_wait_for_hba_online(ha);
1721 scsi_unblock_requests(ha->host);
1722
1723 return rval;
1724}
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