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qla2xxx: Enable fw_dump_size for ISP8044.
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_tmpl.c
CommitLineData
f73cb695
CD		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#include "qla_def.h"
8#include "qla_tmpl.h"
9
10/* note default template is in big endian */
11static const uint32_t ql27xx_fwdt_default_template[] = {
12 0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
13 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
14 0x00000000, 0x00000000, 0x00000000, 0x00000000,
15 0x00000000, 0x00000000, 0x00000000, 0x00000000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000,
17 0x00000000, 0x00000000, 0x00000000, 0x00000000,
18 0x00000000, 0x00000000, 0x00000000, 0x00000000,
19 0x00000000, 0x00000000, 0x00000000, 0x00000000,
20 0x00000000, 0x00000000, 0x00000000, 0x00000000,
21 0x00000000, 0x00000000, 0x00000000, 0x00000000,
22 0x00000000, 0x04010000, 0x14000000, 0x00000000,
23 0x02000000, 0x44000000, 0x09010000, 0x10000000,
24 0x00000000, 0x02000000, 0x01010000, 0x1c000000,
25 0x00000000, 0x02000000, 0x00600000, 0x00000000,
26 0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
27 0x02000000, 0x00600000, 0x00000000, 0xcc000000,
28 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
29 0x10600000, 0x00000000, 0xd4000000, 0x01010000,
30 0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
31 0x00000060, 0xf0000000, 0x00010000, 0x18000000,
32 0x00000000, 0x02000000, 0x00700000, 0x041000c0,
33 0x00010000, 0x18000000, 0x00000000, 0x02000000,
34 0x10700000, 0x041000c0, 0x00010000, 0x18000000,
35 0x00000000, 0x02000000, 0x40700000, 0x041000c0,
36 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
37 0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
38 0x18000000, 0x00000000, 0x02000000, 0x007c0000,
39 0x040300c4, 0x00010000, 0x18000000, 0x00000000,
40 0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
41 0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
42 0x00000000, 0xc0000000, 0x00010000, 0x18000000,
43 0x00000000, 0x02000000, 0x007c0000, 0x04200000,
44 0x0b010000, 0x18000000, 0x00000000, 0x02000000,
45 0x0c000000, 0x00000000, 0x02010000, 0x20000000,
46 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
47 0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
48 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
49 0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
50 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
51 0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
52 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
53 0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
54 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
55 0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
56 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
57 0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
58 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
59 0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
60 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
61 0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
62 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
63 0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
64 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
65 0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
66 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
67 0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
68 0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
69 0x00010000, 0x18000000, 0x00000000, 0x02000000,
70 0x0a000000, 0x04200080, 0x00010000, 0x18000000,
71 0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
72 0x00010000, 0x18000000, 0x00000000, 0x02000000,
73 0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
74 0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
75 0x00010000, 0x18000000, 0x00000000, 0x02000000,
76 0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
77 0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
78 0x00010000, 0x18000000, 0x00000000, 0x02000000,
79 0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
80 0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
81 0x00010000, 0x18000000, 0x00000000, 0x02000000,
82 0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
83 0x00000000, 0x02000000, 0x00300000, 0x041000c0,
84 0x00010000, 0x18000000, 0x00000000, 0x02000000,
85 0x10300000, 0x041000c0, 0x00010000, 0x18000000,
86 0x00000000, 0x02000000, 0x20300000, 0x041000c0,
87 0x00010000, 0x18000000, 0x00000000, 0x02000000,
88 0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
89 0x00000000, 0x02000000, 0x06010000, 0x1c000000,
90 0x00000000, 0x02000000, 0x01000000, 0x00000200,
91 0xff230200, 0x06010000, 0x1c000000, 0x00000000,
92 0x02000000, 0x02000000, 0x00001000, 0x00000000,
93 0x07010000, 0x18000000, 0x00000000, 0x02000000,
94 0x00000000, 0x01000000, 0x07010000, 0x18000000,
95 0x00000000, 0x02000000, 0x00000000, 0x02000000,
96 0x07010000, 0x18000000, 0x00000000, 0x02000000,
97 0x00000000, 0x03000000, 0x0d010000, 0x14000000,
98 0x00000000, 0x02000000, 0x00000000, 0xff000000,
99 0x10000000, 0x00000000, 0x00000080,
100};
101
102static inline void __iomem *
103qla27xx_isp_reg(struct scsi_qla_host *vha)
104{
105 return &vha->hw->iobase->isp24;
106}
107
108static inline void
109qla27xx_insert16(uint16_t value, void *buf, ulong *len)
110{
111 if (buf) {
112 buf += *len;
113 *(__le16 *)buf = cpu_to_le16(value);
114 }
115 *len += sizeof(value);
116}
117
118static inline void
119qla27xx_insert32(uint32_t value, void *buf, ulong *len)
120{
121 if (buf) {
122 buf += *len;
123 *(__le32 *)buf = cpu_to_le32(value);
124 }
125 *len += sizeof(value);
126}
127
128static inline void
129qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
130{
131 ulong cnt = size;
132
133 if (buf && mem) {
134 buf += *len;
135 while (cnt >= sizeof(uint32_t)) {
136 *(__le32 *)buf = cpu_to_le32p(mem);
137 buf += sizeof(uint32_t);
138 mem += sizeof(uint32_t);
139 cnt -= sizeof(uint32_t);
140 }
141 if (cnt)
142 memcpy(buf, mem, cnt);
143 }
144 *len += size;
145}
146
147static inline void
148qla27xx_read8(void *window, void *buf, ulong *len)
149{
150 uint8_t value = ~0;
151
152 if (buf) {
153 value = RD_REG_BYTE((__iomem void *)window);
154 ql_dbg(ql_dbg_misc, NULL, 0xd011,
155 "%s: -> %x\n", __func__, value);
156 }
157 qla27xx_insert32(value, buf, len);
158}
159
160static inline void
161qla27xx_read16(void *window, void *buf, ulong *len)
162{
163 uint16_t value = ~0;
164
165 if (buf) {
166 value = RD_REG_WORD((__iomem void *)window);
167 ql_dbg(ql_dbg_misc, NULL, 0xd012,
168 "%s: -> %x\n", __func__, value);
169 }
170 qla27xx_insert32(value, buf, len);
171}
172
173static inline void
174qla27xx_read32(void *window, void *buf, ulong *len)
175{
176 uint32_t value = ~0;
177
178 if (buf) {
179 value = RD_REG_DWORD((__iomem void *)window);
180 ql_dbg(ql_dbg_misc, NULL, 0xd013,
181 "%s: -> %x\n", __func__, value);
182 }
183 qla27xx_insert32(value, buf, len);
184}
185
186static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *)
187{
188 return
189 (width == 1) ? qla27xx_read8 :
190 (width == 2) ? qla27xx_read16 :
191 qla27xx_read32;
192}
193
0d90c34c
JC		 194static inline void
195qla27xx_read_off(__iomem struct device_reg_24xx *reg,
196 uint offset, void *buf, ulong *len)
197{
198 void *window = (void *)reg + offset;
199
200 if (buf) {
201 ql_dbg(ql_dbg_misc, NULL, 0xd300,
202 "%s: @%x\n", __func__, offset);
203 }
204 qla27xx_read32(window, buf, len);
205}
206
f73cb695
CD		 207static inline void
208qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
209 uint offset, void *buf, ulong *len)
210{
211 void *window = (void *)reg + offset;
212
213 if (buf) {
214 ql_dbg(ql_dbg_misc, NULL, 0xd014,
215 "%s: @%x\n", __func__, offset);
216 }
217 qla27xx_insert32(offset, buf, len);
218 qla27xx_read32(window, buf, len);
219}
220
221static inline void
222qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
223 uint offset, uint32_t data, void *buf)
224{
225 __iomem void *window = reg + offset;
226
227 if (buf) {
228 ql_dbg(ql_dbg_misc, NULL, 0xd015,
229 "%s: @%x <- %x\n", __func__, offset, data);
230 WRT_REG_DWORD(window, data);
231 }
232}
233
234static inline void
235qla27xx_read_window(__iomem struct device_reg_24xx *reg,
236 uint32_t base, uint offset, uint count, uint width, void *buf,
237 ulong *len)
238{
239 void *window = (void *)reg + offset;
240 void (*readn)(void *, void *, ulong *) = qla27xx_read_vector(width);
241
242 if (buf) {
243 ql_dbg(ql_dbg_misc, NULL, 0xd016,
244 "%s: base=%x offset=%x count=%x width=%x\n",
245 __func__, base, offset, count, width);
246 }
247 qla27xx_write_reg(reg, IOBASE_ADDR, base, buf);
248 while (count--) {
249 qla27xx_insert32(base, buf, len);
250 readn(window, buf, len);
251 window += width;
7095388f 252 base++;
f73cb695
CD		 253 }
254}
255
256static inline void
257qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
258{
259 if (buf)
260 ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
261}
262
263static int
264qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
265 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
266{
267 ql_dbg(ql_dbg_misc, vha, 0xd100,
268 "%s: nop [%lx]\n", __func__, *len);
269 qla27xx_skip_entry(ent, buf);
270
271 return false;
272}
273
274static int
275qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
276 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
277{
278 ql_dbg(ql_dbg_misc, vha, 0xd1ff,
279 "%s: end [%lx]\n", __func__, *len);
280 qla27xx_skip_entry(ent, buf);
281
282 /* terminate */
283 return true;
284}
285
286static int
287qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
288 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
289{
290 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
291
292 ql_dbg(ql_dbg_misc, vha, 0xd200,
293 "%s: rdio t1 [%lx]\n", __func__, *len);
294 qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
295 ent->t256.reg_count, ent->t256.reg_width, buf, len);
296
297 return false;
298}
299
300static int
301qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
302 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
303{
304 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
305
306 ql_dbg(ql_dbg_misc, vha, 0xd201,
307 "%s: wrio t1 [%lx]\n", __func__, *len);
308 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
309 qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
310
311 return false;
312}
313
314static int
315qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
316 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
317{
318 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
319
320 ql_dbg(ql_dbg_misc, vha, 0xd202,
321 "%s: rdio t2 [%lx]\n", __func__, *len);
322 qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
323 qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
324 ent->t258.reg_count, ent->t258.reg_width, buf, len);
325
326 return false;
327}
328
329static int
330qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
331 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
332{
333 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
334
335 ql_dbg(ql_dbg_misc, vha, 0xd203,
336 "%s: wrio t2 [%lx]\n", __func__, *len);
337 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
338 qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
339 qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
340
341 return false;
342}
343
344static int
345qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
346 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
347{
348 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
349
350 ql_dbg(ql_dbg_misc, vha, 0xd204,
351 "%s: rdpci [%lx]\n", __func__, *len);
352 qla27xx_read_reg(reg, ent->t260.pci_addr, buf, len);
353
354 return false;
355}
356
357static int
358qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
359 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
360{
361 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
362
363 ql_dbg(ql_dbg_misc, vha, 0xd205,
364 "%s: wrpci [%lx]\n", __func__, *len);
365 qla27xx_write_reg(reg, ent->t261.pci_addr, ent->t261.write_data, buf);
366
367 return false;
368}
369
370static int
371qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
372 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
373{
374 ulong dwords;
375 ulong start;
376 ulong end;
377
378 ql_dbg(ql_dbg_misc, vha, 0xd206,
379 "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
380 start = ent->t262.start_addr;
381 end = ent->t262.end_addr;
382
383 if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
384 ;
385 } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
386 end = vha->hw->fw_memory_size;
387 if (buf)
388 ent->t262.end_addr = end;
389 } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
390 start = vha->hw->fw_shared_ram_start;
391 end = vha->hw->fw_shared_ram_end;
392 if (buf) {
393 ent->t262.start_addr = start;
394 ent->t262.end_addr = end;
395 }
396 } else if (ent->t262.ram_area == T262_RAM_AREA_DDR_RAM) {
397 ql_dbg(ql_dbg_misc, vha, 0xd021,
398 "%s: unsupported ddr ram\n", __func__);
399 qla27xx_skip_entry(ent, buf);
400 goto done;
401 } else {
402 ql_dbg(ql_dbg_misc, vha, 0xd022,
403 "%s: unknown area %u\n", __func__, ent->t262.ram_area);
404 qla27xx_skip_entry(ent, buf);
405 goto done;
406 }
407
408 if (end < start) {
409 ql_dbg(ql_dbg_misc, vha, 0xd023,
410 "%s: bad range (start=%x end=%x)\n", __func__,
411 ent->t262.end_addr, ent->t262.start_addr);
412 qla27xx_skip_entry(ent, buf);
413 goto done;
414 }
415
416 dwords = end - start + 1;
417 if (buf) {
418 ql_dbg(ql_dbg_misc, vha, 0xd024,
419 "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
420 buf += *len;
421 qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
422 }
423 *len += dwords * sizeof(uint32_t);
424done:
425 return false;
426}
427
428static int
429qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
430 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
431{
432 uint count = 0;
433 uint i;
434 uint length;
435
436 ql_dbg(ql_dbg_misc, vha, 0xd207,
437 "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
438 if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
439 for (i = 0; i < vha->hw->max_req_queues; i++) {
440 struct req_que *req = vha->hw->req_q_map[i];
441 if (req || !buf) {
442 length = req ?
443 req->length : REQUEST_ENTRY_CNT_24XX;
444 qla27xx_insert16(i, buf, len);
445 qla27xx_insert16(length, buf, len);
446 qla27xx_insertbuf(req ? req->ring : NULL,
447 length * sizeof(*req->ring), buf, len);
448 count++;
449 }
450 }
451 } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
452 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
453 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
454 if (rsp || !buf) {
455 length = rsp ?
456 rsp->length : RESPONSE_ENTRY_CNT_MQ;
457 qla27xx_insert16(i, buf, len);
458 qla27xx_insert16(length, buf, len);
459 qla27xx_insertbuf(rsp ? rsp->ring : NULL,
460 length * sizeof(*rsp->ring), buf, len);
461 count++;
462 }
463 }
464 } else if (ent->t263.queue_type == T263_QUEUE_TYPE_ATIO) {
465 ql_dbg(ql_dbg_misc, vha, 0xd025,
466 "%s: unsupported atio queue\n", __func__);
467 qla27xx_skip_entry(ent, buf);
468 goto done;
469 } else {
470 ql_dbg(ql_dbg_misc, vha, 0xd026,
471 "%s: unknown queue %u\n", __func__, ent->t263.queue_type);
472 qla27xx_skip_entry(ent, buf);
473 goto done;
474 }
475
476 if (buf)
477 ent->t263.num_queues = count;
478done:
479 return false;
480}
481
482static int
483qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
484 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
485{
486 ql_dbg(ql_dbg_misc, vha, 0xd208,
487 "%s: getfce [%lx]\n", __func__, *len);
488 if (vha->hw->fce) {
489 if (buf) {
490 ent->t264.fce_trace_size = FCE_SIZE;
491 ent->t264.write_pointer = vha->hw->fce_wr;
492 ent->t264.base_pointer = vha->hw->fce_dma;
493 ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
494 ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
495 ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
496 ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
497 ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
498 ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
499 }
500 qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
501 } else {
502 ql_dbg(ql_dbg_misc, vha, 0xd027,
503 "%s: missing fce\n", __func__);
504 qla27xx_skip_entry(ent, buf);
505 }
506
507 return false;
508}
509
510static int
511qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
512 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
513{
514 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
515
516 ql_dbg(ql_dbg_misc, vha, 0xd209,
517 "%s: pause risc [%lx]\n", __func__, *len);
518 if (buf)
61f098dd 519 qla24xx_pause_risc(reg, vha->hw);
f73cb695
CD		 520
521 return false;
522}
523
524static int
525qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
526 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
527{
528 ql_dbg(ql_dbg_misc, vha, 0xd20a,
529 "%s: reset risc [%lx]\n", __func__, *len);
530 if (buf)
531 qla24xx_soft_reset(vha->hw);
532
533 return false;
534}
535
536static int
537qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
538 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
539{
540 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
541
542 ql_dbg(ql_dbg_misc, vha, 0xd20b,
543 "%s: dis intr [%lx]\n", __func__, *len);
544 qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
545
546 return false;
547}
548
549static int
550qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
551 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
552{
553 ql_dbg(ql_dbg_misc, vha, 0xd20c,
554 "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
555 if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) {
556 if (vha->hw->eft) {
557 if (buf) {
558 ent->t268.buf_size = EFT_SIZE;
559 ent->t268.start_addr = vha->hw->eft_dma;
560 }
561 qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
562 } else {
563 ql_dbg(ql_dbg_misc, vha, 0xd028,
564 "%s: missing eft\n", __func__);
565 qla27xx_skip_entry(ent, buf);
566 }
567 } else if (ent->t268.buf_type == T268_BUF_TYPE_EXCH_BUFOFF) {
568 ql_dbg(ql_dbg_misc, vha, 0xd029,
569 "%s: unsupported exchange offload buffer\n", __func__);
570 qla27xx_skip_entry(ent, buf);
571 } else if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_LOGIN) {
572 ql_dbg(ql_dbg_misc, vha, 0xd02a,
573 "%s: unsupported extended login buffer\n", __func__);
574 qla27xx_skip_entry(ent, buf);
575 } else {
576 ql_dbg(ql_dbg_misc, vha, 0xd02b,
577 "%s: unknown buf %x\n", __func__, ent->t268.buf_type);
578 qla27xx_skip_entry(ent, buf);
579 }
580
581 return false;
582}
583
584static int
585qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
586 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
587{
588 ql_dbg(ql_dbg_misc, vha, 0xd20d,
589 "%s: scratch [%lx]\n", __func__, *len);
590 qla27xx_insert32(0xaaaaaaaa, buf, len);
591 qla27xx_insert32(0xbbbbbbbb, buf, len);
592 qla27xx_insert32(0xcccccccc, buf, len);
593 qla27xx_insert32(0xdddddddd, buf, len);
594 qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
595 if (buf)
596 ent->t269.scratch_size = 5 * sizeof(uint32_t);
597
598 return false;
599}
600
601static int
602qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
603 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
604{
605 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
f73cb695
CD		 606 ulong dwords = ent->t270.count;
607 ulong addr = ent->t270.addr;
608
609 ql_dbg(ql_dbg_misc, vha, 0xd20e,
610 "%s: rdremreg [%lx]\n", __func__, *len);
611 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
612 while (dwords--) {
613 qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
f73cb695 614 qla27xx_insert32(addr, buf, len);
0d90c34c 615 qla27xx_read_off(reg, 0xc4, buf, len);
f73cb695
CD		 616 addr++;
617 }
618
619 return false;
620}
621
622static int
623qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
624 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
625{
626 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
627 ulong addr = ent->t271.addr;
0d90c34c 628 ulong data = ent->t271.data;
f73cb695
CD		 629
630 ql_dbg(ql_dbg_misc, vha, 0xd20f,
631 "%s: wrremreg [%lx]\n", __func__, *len);
632 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
0d90c34c 633 qla27xx_write_reg(reg, 0xc4, data, buf);
f73cb695
CD		 634 qla27xx_write_reg(reg, 0xc0, addr, buf);
635
636 return false;
637}
638
639static int
640qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
641 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
642{
643 ulong dwords = ent->t272.count;
644 ulong start = ent->t272.addr;
645
646 ql_dbg(ql_dbg_misc, vha, 0xd210,
647 "%s: rdremram [%lx]\n", __func__, *len);
648 if (buf) {
649 ql_dbg(ql_dbg_misc, vha, 0xd02c,
650 "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
651 buf += *len;
652 qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
653 }
654 *len += dwords * sizeof(uint32_t);
655
656 return false;
657}
658
659static int
660qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
661 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
662{
663 ulong dwords = ent->t273.count;
664 ulong addr = ent->t273.addr;
665 uint32_t value;
666
667 ql_dbg(ql_dbg_misc, vha, 0xd211,
668 "%s: pcicfg [%lx]\n", __func__, *len);
669 while (dwords--) {
670 value = ~0;
671 if (pci_read_config_dword(vha->hw->pdev, addr, &value))
672 ql_dbg(ql_dbg_misc, vha, 0xd02d,
673 "%s: failed pcicfg read at %lx\n", __func__, addr);
674 qla27xx_insert32(addr, buf, len);
675 qla27xx_insert32(value, buf, len);
676 addr += 4;
677 }
678
679 return false;
680}
681
682static int
683qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
684 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
685{
686 ql_dbg(ql_dbg_misc, vha, 0xd2ff,
687 "%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len);
688 qla27xx_skip_entry(ent, buf);
689
690 return false;
691}
692
693struct qla27xx_fwdt_entry_call {
694 int type;
695 int (*call)(
696 struct scsi_qla_host *,
697 struct qla27xx_fwdt_entry *,
698 void *,
699 ulong *);
700};
701
702static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
703 { ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } ,
704 { ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } ,
705 { ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } ,
706 { ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } ,
707 { ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } ,
708 { ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } ,
709 { ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } ,
710 { ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } ,
711 { ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } ,
712 { ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } ,
713 { ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } ,
714 { ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } ,
715 { ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } ,
716 { ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } ,
717 { ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } ,
718 { ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } ,
719 { ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } ,
720 { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
721 { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
722 { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
723 { -1 , qla27xx_fwdt_entry_other }
724};
725
726static inline int (*qla27xx_find_entry(int type))
727 (struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *)
728{
729 struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list;
730
731 while (list->type != -1 && list->type != type)
732 list++;
733
734 return list->call;
735}
736
737static inline void *
738qla27xx_next_entry(void *p)
739{
740 struct qla27xx_fwdt_entry *ent = p;
741
742 return p + ent->hdr.entry_size;
743}
744
745static void
746qla27xx_walk_template(struct scsi_qla_host *vha,
747 struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
748{
749 struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
750 ulong count = tmp->entry_count;
751
752 ql_dbg(ql_dbg_misc, vha, 0xd01a,
753 "%s: entry count %lx\n", __func__, count);
754 while (count--) {
755 if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len))
756 break;
757 ent = qla27xx_next_entry(ent);
758 }
759 ql_dbg(ql_dbg_misc, vha, 0xd01b,
760 "%s: len=%lx\n", __func__, *len);
761}
762
763static void
764qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
765{
766 tmp->capture_timestamp = jiffies;
767}
768
769static void
770qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
771{
772 uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
773 int rval = 0;
774
775 rval = sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu",
776 v+0, v+1, v+2, v+3, v+4, v+5);
777
778 tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0];
779 tmp->driver_info[1] = v[5] << 8 | v[4];
780 tmp->driver_info[2] = 0x12345678;
781}
782
783static void
784qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
785 struct scsi_qla_host *vha)
786{
787 tmp->firmware_version[0] = vha->hw->fw_major_version;
788 tmp->firmware_version[1] = vha->hw->fw_minor_version;
789 tmp->firmware_version[2] = vha->hw->fw_subminor_version;
790 tmp->firmware_version[3] =
791 vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes;
792 tmp->firmware_version[4] =
793 vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0];
794}
795
796static void
797ql27xx_edit_template(struct scsi_qla_host *vha,
798 struct qla27xx_fwdt_template *tmp)
799{
800 qla27xx_time_stamp(tmp);
801 qla27xx_driver_info(tmp);
802 qla27xx_firmware_info(tmp, vha);
803}
804
805static inline uint32_t
806qla27xx_template_checksum(void *p, ulong size)
807{
808 uint32_t *buf = p;
809 uint64_t sum = 0;
810
811 size /= sizeof(*buf);
812
813 while (size--)
814 sum += *buf++;
815
816 sum = (sum & 0xffffffff) + (sum >> 32);
817
818 return ~sum;
819}
820
821static inline int
822qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
823{
824 return qla27xx_template_checksum(tmp, tmp->template_size) == 0;
825}
826
827static inline int
828qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
829{
830 return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
831}
832
833static void
834qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
835{
836 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
837 ulong len;
838
839 if (qla27xx_fwdt_template_valid(tmp)) {
840 len = tmp->template_size;
841 tmp = memcpy(vha->hw->fw_dump, tmp, len);
842 ql27xx_edit_template(vha, tmp);
843 qla27xx_walk_template(vha, tmp, tmp, &len);
844 vha->hw->fw_dump_len = len;
845 vha->hw->fw_dumped = 1;
846 }
847}
848
849ulong
850qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
851{
852 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
853 ulong len = 0;
854
855 if (qla27xx_fwdt_template_valid(tmp)) {
856 len = tmp->template_size;
857 qla27xx_walk_template(vha, tmp, NULL, &len);
858 }
859
860 return len;
861}
862
863ulong
864qla27xx_fwdt_template_size(void *p)
865{
866 struct qla27xx_fwdt_template *tmp = p;
867
868 return tmp->template_size;
869}
870
871ulong
872qla27xx_fwdt_template_default_size(void)
873{
874 return sizeof(ql27xx_fwdt_default_template);
875}
876
877const void *
878qla27xx_fwdt_template_default(void)
879{
880 return ql27xx_fwdt_default_template;
881}
882
883int
884qla27xx_fwdt_template_valid(void *p)
885{
886 struct qla27xx_fwdt_template *tmp = p;
887
888 if (!qla27xx_verify_template_header(tmp)) {
889 ql_log(ql_log_warn, NULL, 0xd01c,
890 "%s: template type %x\n", __func__, tmp->template_type);
891 return false;
892 }
893
894 if (!qla27xx_verify_template_checksum(tmp)) {
895 ql_log(ql_log_warn, NULL, 0xd01d,
896 "%s: failed template checksum\n", __func__);
897 return false;
898 }
899
900 return true;
901}
902
903void
904qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
905{
906 ulong flags = 0;
907
908 if (!hardware_locked)
909 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
910
911 if (!vha->hw->fw_dump)
912 ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
913 else if (!vha->hw->fw_dump_template)
914 ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
915 else
916 qla27xx_execute_fwdt_template(vha);
917
918 if (!hardware_locked)
919 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
920}
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