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qla2xxx: Disable Interrupt handshake for ISP27XX.
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / qla2xxx / qla_tmpl.c
CommitLineData
f73cb695
CD		 1/*
2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
f73cb695
CD		 4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7#include "qla_def.h"
8#include "qla_tmpl.h"
9
10/* note default template is in big endian */
11static const uint32_t ql27xx_fwdt_default_template[] = {
12 0x63000000, 0xa4000000, 0x7c050000, 0x00000000,
13 0x30000000, 0x01000000, 0x00000000, 0xc0406eb4,
14 0x00000000, 0x00000000, 0x00000000, 0x00000000,
15 0x00000000, 0x00000000, 0x00000000, 0x00000000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000,
17 0x00000000, 0x00000000, 0x00000000, 0x00000000,
18 0x00000000, 0x00000000, 0x00000000, 0x00000000,
19 0x00000000, 0x00000000, 0x00000000, 0x00000000,
20 0x00000000, 0x00000000, 0x00000000, 0x00000000,
21 0x00000000, 0x00000000, 0x00000000, 0x00000000,
22 0x00000000, 0x04010000, 0x14000000, 0x00000000,
23 0x02000000, 0x44000000, 0x09010000, 0x10000000,
24 0x00000000, 0x02000000, 0x01010000, 0x1c000000,
25 0x00000000, 0x02000000, 0x00600000, 0x00000000,
26 0xc0000000, 0x01010000, 0x1c000000, 0x00000000,
27 0x02000000, 0x00600000, 0x00000000, 0xcc000000,
28 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
29 0x10600000, 0x00000000, 0xd4000000, 0x01010000,
30 0x1c000000, 0x00000000, 0x02000000, 0x700f0000,
31 0x00000060, 0xf0000000, 0x00010000, 0x18000000,
32 0x00000000, 0x02000000, 0x00700000, 0x041000c0,
33 0x00010000, 0x18000000, 0x00000000, 0x02000000,
34 0x10700000, 0x041000c0, 0x00010000, 0x18000000,
35 0x00000000, 0x02000000, 0x40700000, 0x041000c0,
36 0x01010000, 0x1c000000, 0x00000000, 0x02000000,
37 0x007c0000, 0x01000000, 0xc0000000, 0x00010000,
38 0x18000000, 0x00000000, 0x02000000, 0x007c0000,
39 0x040300c4, 0x00010000, 0x18000000, 0x00000000,
40 0x02000000, 0x007c0000, 0x040100c0, 0x01010000,
41 0x1c000000, 0x00000000, 0x02000000, 0x007c0000,
42 0x00000000, 0xc0000000, 0x00010000, 0x18000000,
43 0x00000000, 0x02000000, 0x007c0000, 0x04200000,
44 0x0b010000, 0x18000000, 0x00000000, 0x02000000,
45 0x0c000000, 0x00000000, 0x02010000, 0x20000000,
46 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
47 0xf0000000, 0x000000b0, 0x02010000, 0x20000000,
48 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
49 0xf0000000, 0x000010b0, 0x02010000, 0x20000000,
50 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
51 0xf0000000, 0x000020b0, 0x02010000, 0x20000000,
52 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
53 0xf0000000, 0x000030b0, 0x02010000, 0x20000000,
54 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
55 0xf0000000, 0x000040b0, 0x02010000, 0x20000000,
56 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
57 0xf0000000, 0x000050b0, 0x02010000, 0x20000000,
58 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
59 0xf0000000, 0x000060b0, 0x02010000, 0x20000000,
60 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
61 0xf0000000, 0x000070b0, 0x02010000, 0x20000000,
62 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
63 0xf0000000, 0x000080b0, 0x02010000, 0x20000000,
64 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
65 0xf0000000, 0x000090b0, 0x02010000, 0x20000000,
66 0x00000000, 0x02000000, 0x700f0000, 0x040100fc,
67 0xf0000000, 0x0000a0b0, 0x00010000, 0x18000000,
68 0x00000000, 0x02000000, 0x0a000000, 0x040100c0,
69 0x00010000, 0x18000000, 0x00000000, 0x02000000,
70 0x0a000000, 0x04200080, 0x00010000, 0x18000000,
71 0x00000000, 0x02000000, 0x00be0000, 0x041000c0,
72 0x00010000, 0x18000000, 0x00000000, 0x02000000,
73 0x10be0000, 0x041000c0, 0x00010000, 0x18000000,
74 0x00000000, 0x02000000, 0x20be0000, 0x041000c0,
75 0x00010000, 0x18000000, 0x00000000, 0x02000000,
76 0x30be0000, 0x041000c0, 0x00010000, 0x18000000,
77 0x00000000, 0x02000000, 0x00b00000, 0x041000c0,
78 0x00010000, 0x18000000, 0x00000000, 0x02000000,
79 0x10b00000, 0x041000c0, 0x00010000, 0x18000000,
80 0x00000000, 0x02000000, 0x20b00000, 0x041000c0,
81 0x00010000, 0x18000000, 0x00000000, 0x02000000,
82 0x30b00000, 0x041000c0, 0x00010000, 0x18000000,
83 0x00000000, 0x02000000, 0x00300000, 0x041000c0,
84 0x00010000, 0x18000000, 0x00000000, 0x02000000,
85 0x10300000, 0x041000c0, 0x00010000, 0x18000000,
86 0x00000000, 0x02000000, 0x20300000, 0x041000c0,
87 0x00010000, 0x18000000, 0x00000000, 0x02000000,
88 0x30300000, 0x041000c0, 0x0a010000, 0x10000000,
89 0x00000000, 0x02000000, 0x06010000, 0x1c000000,
90 0x00000000, 0x02000000, 0x01000000, 0x00000200,
91 0xff230200, 0x06010000, 0x1c000000, 0x00000000,
92 0x02000000, 0x02000000, 0x00001000, 0x00000000,
93 0x07010000, 0x18000000, 0x00000000, 0x02000000,
94 0x00000000, 0x01000000, 0x07010000, 0x18000000,
95 0x00000000, 0x02000000, 0x00000000, 0x02000000,
96 0x07010000, 0x18000000, 0x00000000, 0x02000000,
97 0x00000000, 0x03000000, 0x0d010000, 0x14000000,
98 0x00000000, 0x02000000, 0x00000000, 0xff000000,
99 0x10000000, 0x00000000, 0x00000080,
100};
101
102static inline void __iomem *
103qla27xx_isp_reg(struct scsi_qla_host *vha)
104{
105 return &vha->hw->iobase->isp24;
106}
107
108static inline void
109qla27xx_insert16(uint16_t value, void *buf, ulong *len)
110{
111 if (buf) {
112 buf += *len;
113 *(__le16 *)buf = cpu_to_le16(value);
114 }
115 *len += sizeof(value);
116}
117
118static inline void
119qla27xx_insert32(uint32_t value, void *buf, ulong *len)
120{
121 if (buf) {
122 buf += *len;
123 *(__le32 *)buf = cpu_to_le32(value);
124 }
125 *len += sizeof(value);
126}
127
128static inline void
129qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
130{
f73cb695 131
ce9b9b08 132 if (buf && mem && size) {
f73cb695 133 buf += *len;
ce9b9b08 134 memcpy(buf, mem, size);
f73cb695
CD		 135 }
136 *len += size;
137}
138
139static inline void
140qla27xx_read8(void *window, void *buf, ulong *len)
141{
142 uint8_t value = ~0;
143
144 if (buf) {
145 value = RD_REG_BYTE((__iomem void *)window);
f73cb695
CD		 146 }
147 qla27xx_insert32(value, buf, len);
148}
149
150static inline void
151qla27xx_read16(void *window, void *buf, ulong *len)
152{
153 uint16_t value = ~0;
154
155 if (buf) {
156 value = RD_REG_WORD((__iomem void *)window);
f73cb695
CD		 157 }
158 qla27xx_insert32(value, buf, len);
159}
160
161static inline void
162qla27xx_read32(void *window, void *buf, ulong *len)
163{
164 uint32_t value = ~0;
165
166 if (buf) {
167 value = RD_REG_DWORD((__iomem void *)window);
f73cb695
CD		 168 }
169 qla27xx_insert32(value, buf, len);
170}
171
172static inline void (*qla27xx_read_vector(uint width))(void *, void *, ulong *)
173{
174 return
175 (width == 1) ? qla27xx_read8 :
176 (width == 2) ? qla27xx_read16 :
177 qla27xx_read32;
178}
179
180static inline void
181qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
182 uint offset, void *buf, ulong *len)
183{
184 void *window = (void *)reg + offset;
185
f73cb695
CD		 186 qla27xx_read32(window, buf, len);
187}
188
189static inline void
190qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
191 uint offset, uint32_t data, void *buf)
192{
6cbfb1eb 193 __iomem void *window = (void __iomem *)reg + offset;
f73cb695
CD		 194
195 if (buf) {
f73cb695
CD		 196 WRT_REG_DWORD(window, data);
197 }
198}
199
200static inline void
201qla27xx_read_window(__iomem struct device_reg_24xx *reg,
c0496401 202 uint32_t addr, uint offset, uint count, uint width, void *buf,
f73cb695
CD		 203 ulong *len)
204{
205 void *window = (void *)reg + offset;
206 void (*readn)(void *, void *, ulong *) = qla27xx_read_vector(width);
207
c0496401 208 qla27xx_write_reg(reg, IOBASE_ADDR, addr, buf);
f73cb695 209 while (count--) {
c0496401 210 qla27xx_insert32(addr, buf, len);
f73cb695
CD		 211 readn(window, buf, len);
212 window += width;
c0496401 213 addr++;
f73cb695
CD		 214 }
215}
216
217static inline void
218qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
219{
220 if (buf)
221 ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
f4bf5e3c
HM		 222 ql_dbg(ql_dbg_misc + ql_dbg_verbose, NULL, 0xd011,
223 "Skipping entry %d\n", ent->hdr.entry_type);
f73cb695
CD		 224}
225
226static int
227qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
228 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
229{
230 ql_dbg(ql_dbg_misc, vha, 0xd100,
231 "%s: nop [%lx]\n", __func__, *len);
232 qla27xx_skip_entry(ent, buf);
233
234 return false;
235}
236
237static int
238qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
239 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
240{
241 ql_dbg(ql_dbg_misc, vha, 0xd1ff,
242 "%s: end [%lx]\n", __func__, *len);
243 qla27xx_skip_entry(ent, buf);
244
245 /* terminate */
246 return true;
247}
248
249static int
250qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
251 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
252{
253 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
254
255 ql_dbg(ql_dbg_misc, vha, 0xd200,
256 "%s: rdio t1 [%lx]\n", __func__, *len);
257 qla27xx_read_window(reg, ent->t256.base_addr, ent->t256.pci_offset,
258 ent->t256.reg_count, ent->t256.reg_width, buf, len);
259
260 return false;
261}
262
263static int
264qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
265 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
266{
267 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
268
269 ql_dbg(ql_dbg_misc, vha, 0xd201,
270 "%s: wrio t1 [%lx]\n", __func__, *len);
271 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t257.base_addr, buf);
272 qla27xx_write_reg(reg, ent->t257.pci_offset, ent->t257.write_data, buf);
273
274 return false;
275}
276
277static int
278qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
279 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
280{
281 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
282
283 ql_dbg(ql_dbg_misc, vha, 0xd202,
284 "%s: rdio t2 [%lx]\n", __func__, *len);
285 qla27xx_write_reg(reg, ent->t258.banksel_offset, ent->t258.bank, buf);
286 qla27xx_read_window(reg, ent->t258.base_addr, ent->t258.pci_offset,
287 ent->t258.reg_count, ent->t258.reg_width, buf, len);
288
289 return false;
290}
291
292static int
293qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
294 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
295{
296 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
297
298 ql_dbg(ql_dbg_misc, vha, 0xd203,
299 "%s: wrio t2 [%lx]\n", __func__, *len);
300 qla27xx_write_reg(reg, IOBASE_ADDR, ent->t259.base_addr, buf);
301 qla27xx_write_reg(reg, ent->t259.banksel_offset, ent->t259.bank, buf);
302 qla27xx_write_reg(reg, ent->t259.pci_offset, ent->t259.write_data, buf);
303
304 return false;
305}
306
307static int
308qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
309 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
310{
311 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
312
313 ql_dbg(ql_dbg_misc, vha, 0xd204,
314 "%s: rdpci [%lx]\n", __func__, *len);
c0496401
JC		 315 qla27xx_insert32(ent->t260.pci_offset, buf, len);
316 qla27xx_read_reg(reg, ent->t260.pci_offset, buf, len);
f73cb695
CD		 317
318 return false;
319}
320
321static int
322qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
323 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
324{
325 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
326
327 ql_dbg(ql_dbg_misc, vha, 0xd205,
328 "%s: wrpci [%lx]\n", __func__, *len);
c0496401 329 qla27xx_write_reg(reg, ent->t261.pci_offset, ent->t261.write_data, buf);
f73cb695
CD		 330
331 return false;
332}
333
334static int
335qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
336 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
337{
338 ulong dwords;
339 ulong start;
340 ulong end;
341
342 ql_dbg(ql_dbg_misc, vha, 0xd206,
343 "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
344 start = ent->t262.start_addr;
345 end = ent->t262.end_addr;
346
347 if (ent->t262.ram_area == T262_RAM_AREA_CRITICAL_RAM) {
348 ;
349 } else if (ent->t262.ram_area == T262_RAM_AREA_EXTERNAL_RAM) {
350 end = vha->hw->fw_memory_size;
351 if (buf)
352 ent->t262.end_addr = end;
353 } else if (ent->t262.ram_area == T262_RAM_AREA_SHARED_RAM) {
354 start = vha->hw->fw_shared_ram_start;
355 end = vha->hw->fw_shared_ram_end;
356 if (buf) {
357 ent->t262.start_addr = start;
358 ent->t262.end_addr = end;
359 }
f73cb695
CD		 360 } else {
361 ql_dbg(ql_dbg_misc, vha, 0xd022,
349c390f 362 "%s: unknown area %x\n", __func__, ent->t262.ram_area);
f73cb695
CD		 363 qla27xx_skip_entry(ent, buf);
364 goto done;
365 }
366
c0496401 367 if (end < start || end == 0) {
f73cb695 368 ql_dbg(ql_dbg_misc, vha, 0xd023,
c0496401 369 "%s: unusable range (start=%x end=%x)\n", __func__,
f73cb695
CD		 370 ent->t262.end_addr, ent->t262.start_addr);
371 qla27xx_skip_entry(ent, buf);
372 goto done;
373 }
374
375 dwords = end - start + 1;
376 if (buf) {
f73cb695
CD		 377 buf += *len;
378 qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
379 }
380 *len += dwords * sizeof(uint32_t);
381done:
382 return false;
383}
384
385static int
386qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
387 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
388{
389 uint count = 0;
390 uint i;
391 uint length;
392
393 ql_dbg(ql_dbg_misc, vha, 0xd207,
394 "%s: getq(%x) [%lx]\n", __func__, ent->t263.queue_type, *len);
395 if (ent->t263.queue_type == T263_QUEUE_TYPE_REQ) {
396 for (i = 0; i < vha->hw->max_req_queues; i++) {
397 struct req_que *req = vha->hw->req_q_map[i];
398 if (req || !buf) {
399 length = req ?
400 req->length : REQUEST_ENTRY_CNT_24XX;
401 qla27xx_insert16(i, buf, len);
402 qla27xx_insert16(length, buf, len);
403 qla27xx_insertbuf(req ? req->ring : NULL,
404 length * sizeof(*req->ring), buf, len);
405 count++;
406 }
407 }
408 } else if (ent->t263.queue_type == T263_QUEUE_TYPE_RSP) {
409 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
410 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
411 if (rsp || !buf) {
412 length = rsp ?
413 rsp->length : RESPONSE_ENTRY_CNT_MQ;
414 qla27xx_insert16(i, buf, len);
415 qla27xx_insert16(length, buf, len);
416 qla27xx_insertbuf(rsp ? rsp->ring : NULL,
417 length * sizeof(*rsp->ring), buf, len);
418 count++;
419 }
420 }
f73cb695
CD		 421 } else {
422 ql_dbg(ql_dbg_misc, vha, 0xd026,
349c390f 423 "%s: unknown queue %x\n", __func__, ent->t263.queue_type);
f73cb695 424 qla27xx_skip_entry(ent, buf);
f73cb695
CD		 425 }
426
427 if (buf)
428 ent->t263.num_queues = count;
c0496401 429
f73cb695
CD		 430 return false;
431}
432
433static int
434qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
435 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
436{
437 ql_dbg(ql_dbg_misc, vha, 0xd208,
438 "%s: getfce [%lx]\n", __func__, *len);
439 if (vha->hw->fce) {
440 if (buf) {
441 ent->t264.fce_trace_size = FCE_SIZE;
442 ent->t264.write_pointer = vha->hw->fce_wr;
443 ent->t264.base_pointer = vha->hw->fce_dma;
444 ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
445 ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
446 ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
447 ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
448 ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
449 ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
450 }
451 qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
452 } else {
453 ql_dbg(ql_dbg_misc, vha, 0xd027,
454 "%s: missing fce\n", __func__);
455 qla27xx_skip_entry(ent, buf);
456 }
457
458 return false;
459}
460
461static int
462qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
463 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
464{
465 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
466
467 ql_dbg(ql_dbg_misc, vha, 0xd209,
468 "%s: pause risc [%lx]\n", __func__, *len);
469 if (buf)
61f098dd 470 qla24xx_pause_risc(reg, vha->hw);
f73cb695
CD		 471
472 return false;
473}
474
475static int
476qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
477 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
478{
479 ql_dbg(ql_dbg_misc, vha, 0xd20a,
480 "%s: reset risc [%lx]\n", __func__, *len);
481 if (buf)
482 qla24xx_soft_reset(vha->hw);
483
484 return false;
485}
486
487static int
488qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
489 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
490{
491 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
492
493 ql_dbg(ql_dbg_misc, vha, 0xd20b,
494 "%s: dis intr [%lx]\n", __func__, *len);
495 qla27xx_write_reg(reg, ent->t267.pci_offset, ent->t267.data, buf);
496
497 return false;
498}
499
500static int
501qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
502 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
503{
504 ql_dbg(ql_dbg_misc, vha, 0xd20c,
505 "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
506 if (ent->t268.buf_type == T268_BUF_TYPE_EXTD_TRACE) {
507 if (vha->hw->eft) {
508 if (buf) {
509 ent->t268.buf_size = EFT_SIZE;
510 ent->t268.start_addr = vha->hw->eft_dma;
511 }
512 qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
513 } else {
514 ql_dbg(ql_dbg_misc, vha, 0xd028,
515 "%s: missing eft\n", __func__);
516 qla27xx_skip_entry(ent, buf);
517 }
f73cb695
CD		 518 } else {
519 ql_dbg(ql_dbg_misc, vha, 0xd02b,
349c390f 520 "%s: unknown buffer %x\n", __func__, ent->t268.buf_type);
f73cb695
CD		 521 qla27xx_skip_entry(ent, buf);
522 }
523
524 return false;
525}
526
527static int
528qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
529 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
530{
531 ql_dbg(ql_dbg_misc, vha, 0xd20d,
532 "%s: scratch [%lx]\n", __func__, *len);
533 qla27xx_insert32(0xaaaaaaaa, buf, len);
534 qla27xx_insert32(0xbbbbbbbb, buf, len);
535 qla27xx_insert32(0xcccccccc, buf, len);
536 qla27xx_insert32(0xdddddddd, buf, len);
537 qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
538 if (buf)
539 ent->t269.scratch_size = 5 * sizeof(uint32_t);
540
541 return false;
542}
543
544static int
545qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
546 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
547{
548 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
f73cb695
CD		 549 ulong dwords = ent->t270.count;
550 ulong addr = ent->t270.addr;
551
552 ql_dbg(ql_dbg_misc, vha, 0xd20e,
553 "%s: rdremreg [%lx]\n", __func__, *len);
554 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
555 while (dwords--) {
556 qla27xx_write_reg(reg, 0xc0, addr|0x80000000, buf);
f73cb695 557 qla27xx_insert32(addr, buf, len);
c0496401 558 qla27xx_read_reg(reg, 0xc4, buf, len);
fbce4f49 559 addr += sizeof(uint32_t);
f73cb695
CD		 560 }
561
562 return false;
563}
564
565static int
566qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
567 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
568{
569 struct device_reg_24xx __iomem *reg = qla27xx_isp_reg(vha);
570 ulong addr = ent->t271.addr;
0d90c34c 571 ulong data = ent->t271.data;
f73cb695
CD		 572
573 ql_dbg(ql_dbg_misc, vha, 0xd20f,
574 "%s: wrremreg [%lx]\n", __func__, *len);
575 qla27xx_write_reg(reg, IOBASE_ADDR, 0x40, buf);
0d90c34c 576 qla27xx_write_reg(reg, 0xc4, data, buf);
f73cb695
CD		 577 qla27xx_write_reg(reg, 0xc0, addr, buf);
578
579 return false;
580}
581
582static int
583qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
584 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
585{
586 ulong dwords = ent->t272.count;
587 ulong start = ent->t272.addr;
588
589 ql_dbg(ql_dbg_misc, vha, 0xd210,
590 "%s: rdremram [%lx]\n", __func__, *len);
591 if (buf) {
592 ql_dbg(ql_dbg_misc, vha, 0xd02c,
593 "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
594 buf += *len;
595 qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
596 }
597 *len += dwords * sizeof(uint32_t);
598
599 return false;
600}
601
602static int
603qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
604 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
605{
606 ulong dwords = ent->t273.count;
607 ulong addr = ent->t273.addr;
608 uint32_t value;
609
610 ql_dbg(ql_dbg_misc, vha, 0xd211,
611 "%s: pcicfg [%lx]\n", __func__, *len);
612 while (dwords--) {
613 value = ~0;
614 if (pci_read_config_dword(vha->hw->pdev, addr, &value))
615 ql_dbg(ql_dbg_misc, vha, 0xd02d,
616 "%s: failed pcicfg read at %lx\n", __func__, addr);
617 qla27xx_insert32(addr, buf, len);
618 qla27xx_insert32(value, buf, len);
c0496401
JC		 619 addr += sizeof(uint32_t);
620 }
621
622 return false;
623}
624
625static int
626qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
627 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
628{
629 uint count = 0;
630 uint i;
631
632 ql_dbg(ql_dbg_misc, vha, 0xd212,
633 "%s: getqsh(%x) [%lx]\n", __func__, ent->t274.queue_type, *len);
634 if (ent->t274.queue_type == T274_QUEUE_TYPE_REQ_SHAD) {
635 for (i = 0; i < vha->hw->max_req_queues; i++) {
636 struct req_que *req = vha->hw->req_q_map[i];
637 if (req || !buf) {
638 qla27xx_insert16(i, buf, len);
639 qla27xx_insert16(1, buf, len);
7c6300e3
JC		 640 qla27xx_insert32(req && req->out_ptr ?
641 *req->out_ptr : 0, buf, len);
c0496401
JC		 642 count++;
643 }
644 }
645 } else if (ent->t274.queue_type == T274_QUEUE_TYPE_RSP_SHAD) {
646 for (i = 0; i < vha->hw->max_rsp_queues; i++) {
647 struct rsp_que *rsp = vha->hw->rsp_q_map[i];
648 if (rsp || !buf) {
649 qla27xx_insert16(i, buf, len);
650 qla27xx_insert16(1, buf, len);
7c6300e3
JC		 651 qla27xx_insert32(rsp && rsp->in_ptr ?
652 *rsp->in_ptr : 0, buf, len);
c0496401
JC		 653 count++;
654 }
655 }
c0496401
JC		 656 } else {
657 ql_dbg(ql_dbg_misc, vha, 0xd02f,
349c390f 658 "%s: unknown queue %x\n", __func__, ent->t274.queue_type);
c0496401 659 qla27xx_skip_entry(ent, buf);
f73cb695
CD		 660 }
661
c0496401
JC		 662 if (buf)
663 ent->t274.num_queues = count;
664
665 if (!count)
666 qla27xx_skip_entry(ent, buf);
667
f73cb695
CD		 668 return false;
669}
670
2ac224bc
JC		 671static int
672qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
673 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
674{
675 ulong offset = offsetof(typeof(*ent), t275.buffer);
676
677 ql_dbg(ql_dbg_misc, vha, 0xd213,
678 "%s: buffer(%x) [%lx]\n", __func__, ent->t275.length, *len);
679 if (!ent->t275.length) {
680 ql_dbg(ql_dbg_misc, vha, 0xd020,
681 "%s: buffer zero length\n", __func__);
682 qla27xx_skip_entry(ent, buf);
683 goto done;
684 }
685 if (offset + ent->t275.length > ent->hdr.entry_size) {
686 ql_dbg(ql_dbg_misc, vha, 0xd030,
687 "%s: buffer overflow\n", __func__);
688 qla27xx_skip_entry(ent, buf);
689 goto done;
690 }
691
692 qla27xx_insertbuf(ent->t275.buffer, ent->t275.length, buf, len);
693done:
694 return false;
695}
696
f73cb695
CD		 697static int
698qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
699 struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
700{
701 ql_dbg(ql_dbg_misc, vha, 0xd2ff,
702 "%s: type %x [%lx]\n", __func__, ent->hdr.entry_type, *len);
703 qla27xx_skip_entry(ent, buf);
704
705 return false;
706}
707
708struct qla27xx_fwdt_entry_call {
aa2dc372 709 uint type;
f73cb695
CD		 710 int (*call)(
711 struct scsi_qla_host *,
712 struct qla27xx_fwdt_entry *,
713 void *,
714 ulong *);
715};
716
717static struct qla27xx_fwdt_entry_call ql27xx_fwdt_entry_call_list[] = {
718 { ENTRY_TYPE_NOP , qla27xx_fwdt_entry_t0 } ,
719 { ENTRY_TYPE_TMP_END , qla27xx_fwdt_entry_t255 } ,
720 { ENTRY_TYPE_RD_IOB_T1 , qla27xx_fwdt_entry_t256 } ,
721 { ENTRY_TYPE_WR_IOB_T1 , qla27xx_fwdt_entry_t257 } ,
722 { ENTRY_TYPE_RD_IOB_T2 , qla27xx_fwdt_entry_t258 } ,
723 { ENTRY_TYPE_WR_IOB_T2 , qla27xx_fwdt_entry_t259 } ,
724 { ENTRY_TYPE_RD_PCI , qla27xx_fwdt_entry_t260 } ,
725 { ENTRY_TYPE_WR_PCI , qla27xx_fwdt_entry_t261 } ,
726 { ENTRY_TYPE_RD_RAM , qla27xx_fwdt_entry_t262 } ,
727 { ENTRY_TYPE_GET_QUEUE , qla27xx_fwdt_entry_t263 } ,
728 { ENTRY_TYPE_GET_FCE , qla27xx_fwdt_entry_t264 } ,
729 { ENTRY_TYPE_PSE_RISC , qla27xx_fwdt_entry_t265 } ,
730 { ENTRY_TYPE_RST_RISC , qla27xx_fwdt_entry_t266 } ,
731 { ENTRY_TYPE_DIS_INTR , qla27xx_fwdt_entry_t267 } ,
732 { ENTRY_TYPE_GET_HBUF , qla27xx_fwdt_entry_t268 } ,
733 { ENTRY_TYPE_SCRATCH , qla27xx_fwdt_entry_t269 } ,
734 { ENTRY_TYPE_RDREMREG , qla27xx_fwdt_entry_t270 } ,
735 { ENTRY_TYPE_WRREMREG , qla27xx_fwdt_entry_t271 } ,
736 { ENTRY_TYPE_RDREMRAM , qla27xx_fwdt_entry_t272 } ,
737 { ENTRY_TYPE_PCICFG , qla27xx_fwdt_entry_t273 } ,
c0496401 738 { ENTRY_TYPE_GET_SHADOW , qla27xx_fwdt_entry_t274 } ,
2ac224bc 739 { ENTRY_TYPE_WRITE_BUF , qla27xx_fwdt_entry_t275 } ,
f73cb695
CD		 740 { -1 , qla27xx_fwdt_entry_other }
741};
742
aa2dc372 743static inline int (*qla27xx_find_entry(uint type))
f73cb695
CD		 744 (struct scsi_qla_host *, struct qla27xx_fwdt_entry *, void *, ulong *)
745{
746 struct qla27xx_fwdt_entry_call *list = ql27xx_fwdt_entry_call_list;
747
aa2dc372 748 while (list->type < type)
f73cb695
CD		 749 list++;
750
aa2dc372
JC		 751 if (list->type == type)
752 return list->call;
753 return qla27xx_fwdt_entry_other;
f73cb695
CD		 754}
755
756static inline void *
757qla27xx_next_entry(void *p)
758{
759 struct qla27xx_fwdt_entry *ent = p;
760
761 return p + ent->hdr.entry_size;
762}
763
764static void
765qla27xx_walk_template(struct scsi_qla_host *vha,
766 struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
767{
768 struct qla27xx_fwdt_entry *ent = (void *)tmp + tmp->entry_offset;
769 ulong count = tmp->entry_count;
770
771 ql_dbg(ql_dbg_misc, vha, 0xd01a,
772 "%s: entry count %lx\n", __func__, count);
773 while (count--) {
774 if (qla27xx_find_entry(ent->hdr.entry_type)(vha, ent, buf, len))
775 break;
776 ent = qla27xx_next_entry(ent);
777 }
299f5e27
JC		 778
779 if (count)
780 ql_dbg(ql_dbg_misc, vha, 0xd018,
781 "%s: residual count (%lx)\n", __func__, count);
782
783 if (ent->hdr.entry_type != ENTRY_TYPE_TMP_END)
784 ql_dbg(ql_dbg_misc, vha, 0xd019,
785 "%s: missing end (%lx)\n", __func__, count);
786
f73cb695
CD		 787 ql_dbg(ql_dbg_misc, vha, 0xd01b,
788 "%s: len=%lx\n", __func__, *len);
f4bf5e3c 789
0137e59e 790 if (buf) {
f4bf5e3c
HM		 791 ql_log(ql_log_warn, vha, 0xd015,
792 "Firmware dump saved to temp buffer (%ld/%p)\n",
793 vha->host_no, vha->hw->fw_dump);
0137e59e
HM		 794 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
795 }
f73cb695
CD		 796}
797
798static void
799qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
800{
801 tmp->capture_timestamp = jiffies;
802}
803
804static void
805qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
806{
807 uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
808 int rval = 0;
809
810 rval = sscanf(qla2x00_version_str, "%hhu.%hhu.%hhu.%hhu.%hhu.%hhu",
811 v+0, v+1, v+2, v+3, v+4, v+5);
812
813 tmp->driver_info[0] = v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0];
814 tmp->driver_info[1] = v[5] << 8 | v[4];
815 tmp->driver_info[2] = 0x12345678;
816}
817
818static void
819qla27xx_firmware_info(struct qla27xx_fwdt_template *tmp,
820 struct scsi_qla_host *vha)
821{
822 tmp->firmware_version[0] = vha->hw->fw_major_version;
823 tmp->firmware_version[1] = vha->hw->fw_minor_version;
824 tmp->firmware_version[2] = vha->hw->fw_subminor_version;
825 tmp->firmware_version[3] =
826 vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes;
827 tmp->firmware_version[4] =
828 vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0];
829}
830
831static void
832ql27xx_edit_template(struct scsi_qla_host *vha,
833 struct qla27xx_fwdt_template *tmp)
834{
835 qla27xx_time_stamp(tmp);
836 qla27xx_driver_info(tmp);
837 qla27xx_firmware_info(tmp, vha);
838}
839
840static inline uint32_t
841qla27xx_template_checksum(void *p, ulong size)
842{
843 uint32_t *buf = p;
844 uint64_t sum = 0;
845
846 size /= sizeof(*buf);
847
848 while (size--)
849 sum += *buf++;
850
851 sum = (sum & 0xffffffff) + (sum >> 32);
852
853 return ~sum;
854}
855
856static inline int
857qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
858{
859 return qla27xx_template_checksum(tmp, tmp->template_size) == 0;
860}
861
862static inline int
863qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
864{
865 return tmp->template_type == TEMPLATE_TYPE_FWDUMP;
866}
867
868static void
869qla27xx_execute_fwdt_template(struct scsi_qla_host *vha)
870{
871 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
872 ulong len;
873
874 if (qla27xx_fwdt_template_valid(tmp)) {
875 len = tmp->template_size;
876 tmp = memcpy(vha->hw->fw_dump, tmp, len);
877 ql27xx_edit_template(vha, tmp);
878 qla27xx_walk_template(vha, tmp, tmp, &len);
879 vha->hw->fw_dump_len = len;
880 vha->hw->fw_dumped = 1;
881 }
882}
883
884ulong
885qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha)
886{
887 struct qla27xx_fwdt_template *tmp = vha->hw->fw_dump_template;
888 ulong len = 0;
889
890 if (qla27xx_fwdt_template_valid(tmp)) {
891 len = tmp->template_size;
892 qla27xx_walk_template(vha, tmp, NULL, &len);
893 }
894
895 return len;
896}
897
898ulong
899qla27xx_fwdt_template_size(void *p)
900{
901 struct qla27xx_fwdt_template *tmp = p;
902
903 return tmp->template_size;
904}
905
906ulong
907qla27xx_fwdt_template_default_size(void)
908{
909 return sizeof(ql27xx_fwdt_default_template);
910}
911
912const void *
913qla27xx_fwdt_template_default(void)
914{
915 return ql27xx_fwdt_default_template;
916}
917
918int
919qla27xx_fwdt_template_valid(void *p)
920{
921 struct qla27xx_fwdt_template *tmp = p;
922
923 if (!qla27xx_verify_template_header(tmp)) {
924 ql_log(ql_log_warn, NULL, 0xd01c,
925 "%s: template type %x\n", __func__, tmp->template_type);
926 return false;
927 }
928
929 if (!qla27xx_verify_template_checksum(tmp)) {
930 ql_log(ql_log_warn, NULL, 0xd01d,
931 "%s: failed template checksum\n", __func__);
932 return false;
933 }
934
935 return true;
936}
937
938void
939qla27xx_fwdump(scsi_qla_host_t *vha, int hardware_locked)
940{
941 ulong flags = 0;
942
943 if (!hardware_locked)
944 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
945
946 if (!vha->hw->fw_dump)
947 ql_log(ql_log_warn, vha, 0xd01e, "fwdump buffer missing.\n");
948 else if (!vha->hw->fw_dump_template)
949 ql_log(ql_log_warn, vha, 0xd01f, "fwdump template missing.\n");
950 else
951 qla27xx_execute_fwdt_template(vha);
952
953 if (!hardware_locked)
954 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
955}
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