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20f733e7 BR |
1 | /* |
2 | * sata_mv.c - Marvell SATA support | |
3 | * | |
8b260248 | 4 | * Copyright 2005: EMC Corporation, all rights reserved. |
e2b1be56 | 5 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
20f733e7 BR |
6 | * |
7 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/blkdev.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/dma-mapping.h> | |
a9524a76 | 33 | #include <linux/device.h> |
20f733e7 | 34 | #include <scsi/scsi_host.h> |
193515d5 | 35 | #include <scsi/scsi_cmnd.h> |
20f733e7 BR |
36 | #include <linux/libata.h> |
37 | #include <asm/io.h> | |
38 | ||
39 | #define DRV_NAME "sata_mv" | |
e4e7b892 | 40 | #define DRV_VERSION "0.6" |
20f733e7 BR |
41 | |
42 | enum { | |
43 | /* BAR's are enumerated in terms of pci_resource_start() terms */ | |
44 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ | |
45 | MV_IO_BAR = 2, /* offset 0x18: IO space */ | |
46 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ | |
47 | ||
48 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ | |
49 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ | |
50 | ||
51 | MV_PCI_REG_BASE = 0, | |
52 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ | |
53 | MV_SATAHC0_REG_BASE = 0x20000, | |
522479fb | 54 | MV_FLASH_CTL = 0x1046c, |
bca1c4eb JG |
55 | MV_GPIO_PORT_CTL = 0x104f0, |
56 | MV_RESET_CFG = 0x180d8, | |
20f733e7 BR |
57 | |
58 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
59 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
60 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ | |
61 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, | |
62 | ||
31961943 | 63 | MV_USE_Q_DEPTH = ATA_DEF_QUEUE, |
20f733e7 | 64 | |
31961943 BR |
65 | MV_MAX_Q_DEPTH = 32, |
66 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, | |
67 | ||
68 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB | |
69 | * CRPB needs alignment on a 256B boundary. Size == 256B | |
70 | * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB | |
71 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B | |
72 | */ | |
73 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), | |
74 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), | |
75 | MV_MAX_SG_CT = 176, | |
76 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), | |
77 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), | |
78 | ||
20f733e7 BR |
79 | MV_PORTS_PER_HC = 4, |
80 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ | |
81 | MV_PORT_HC_SHIFT = 2, | |
31961943 | 82 | /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ |
20f733e7 BR |
83 | MV_PORT_MASK = 3, |
84 | ||
85 | /* Host Flags */ | |
86 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ | |
87 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ | |
31961943 | 88 | MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
50630195 JG |
89 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | |
90 | ATA_FLAG_NO_ATAPI), | |
47c2b677 | 91 | MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, |
20f733e7 | 92 | |
31961943 BR |
93 | CRQB_FLAG_READ = (1 << 0), |
94 | CRQB_TAG_SHIFT = 1, | |
95 | CRQB_CMD_ADDR_SHIFT = 8, | |
96 | CRQB_CMD_CS = (0x2 << 11), | |
97 | CRQB_CMD_LAST = (1 << 15), | |
98 | ||
99 | CRPB_FLAG_STATUS_SHIFT = 8, | |
100 | ||
101 | EPRD_FLAG_END_OF_TBL = (1 << 31), | |
102 | ||
20f733e7 BR |
103 | /* PCI interface registers */ |
104 | ||
31961943 BR |
105 | PCI_COMMAND_OFS = 0xc00, |
106 | ||
20f733e7 BR |
107 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
108 | STOP_PCI_MASTER = (1 << 2), | |
109 | PCI_MASTER_EMPTY = (1 << 3), | |
110 | GLOB_SFT_RST = (1 << 4), | |
111 | ||
522479fb JG |
112 | MV_PCI_MODE = 0xd00, |
113 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, | |
114 | MV_PCI_DISC_TIMER = 0xd04, | |
115 | MV_PCI_MSI_TRIGGER = 0xc38, | |
116 | MV_PCI_SERR_MASK = 0xc28, | |
117 | MV_PCI_XBAR_TMOUT = 0x1d04, | |
118 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, | |
119 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, | |
120 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, | |
121 | MV_PCI_ERR_COMMAND = 0x1d50, | |
122 | ||
123 | PCI_IRQ_CAUSE_OFS = 0x1d58, | |
124 | PCI_IRQ_MASK_OFS = 0x1d5c, | |
20f733e7 BR |
125 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
126 | ||
127 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, | |
128 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, | |
129 | PORT0_ERR = (1 << 0), /* shift by port # */ | |
130 | PORT0_DONE = (1 << 1), /* shift by port # */ | |
131 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ | |
132 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ | |
133 | PCI_ERR = (1 << 18), | |
134 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ | |
135 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ | |
136 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ | |
137 | GPIO_INT = (1 << 22), | |
138 | SELF_INT = (1 << 23), | |
139 | TWSI_INT = (1 << 24), | |
140 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ | |
8b260248 | 141 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | |
20f733e7 BR |
142 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | |
143 | HC_MAIN_RSVD), | |
144 | ||
145 | /* SATAHC registers */ | |
146 | HC_CFG_OFS = 0, | |
147 | ||
148 | HC_IRQ_CAUSE_OFS = 0x14, | |
31961943 | 149 | CRPB_DMA_DONE = (1 << 0), /* shift by port # */ |
20f733e7 BR |
150 | HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ |
151 | DEV_IRQ = (1 << 8), /* shift by port # */ | |
152 | ||
153 | /* Shadow block registers */ | |
31961943 BR |
154 | SHD_BLK_OFS = 0x100, |
155 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ | |
20f733e7 BR |
156 | |
157 | /* SATA registers */ | |
158 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ | |
159 | SATA_ACTIVE_OFS = 0x350, | |
47c2b677 | 160 | PHY_MODE3 = 0x310, |
bca1c4eb JG |
161 | PHY_MODE4 = 0x314, |
162 | PHY_MODE2 = 0x330, | |
c9d39130 JG |
163 | MV5_PHY_MODE = 0x74, |
164 | MV5_LT_MODE = 0x30, | |
165 | MV5_PHY_CTL = 0x0C, | |
bca1c4eb JG |
166 | SATA_INTERFACE_CTL = 0x050, |
167 | ||
168 | MV_M2_PREAMP_MASK = 0x7e0, | |
20f733e7 BR |
169 | |
170 | /* Port registers */ | |
171 | EDMA_CFG_OFS = 0, | |
31961943 BR |
172 | EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */ |
173 | EDMA_CFG_NCQ = (1 << 5), | |
174 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ | |
175 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ | |
176 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ | |
20f733e7 BR |
177 | |
178 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, | |
179 | EDMA_ERR_IRQ_MASK_OFS = 0xc, | |
180 | EDMA_ERR_D_PAR = (1 << 0), | |
181 | EDMA_ERR_PRD_PAR = (1 << 1), | |
182 | EDMA_ERR_DEV = (1 << 2), | |
183 | EDMA_ERR_DEV_DCON = (1 << 3), | |
184 | EDMA_ERR_DEV_CON = (1 << 4), | |
185 | EDMA_ERR_SERR = (1 << 5), | |
186 | EDMA_ERR_SELF_DIS = (1 << 7), | |
187 | EDMA_ERR_BIST_ASYNC = (1 << 8), | |
188 | EDMA_ERR_CRBQ_PAR = (1 << 9), | |
189 | EDMA_ERR_CRPB_PAR = (1 << 10), | |
190 | EDMA_ERR_INTRL_PAR = (1 << 11), | |
191 | EDMA_ERR_IORDY = (1 << 12), | |
192 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), | |
193 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), | |
194 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), | |
195 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), | |
196 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), | |
197 | EDMA_ERR_TRANS_PROTO = (1 << 31), | |
8b260248 | 198 | EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
20f733e7 BR |
199 | EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | |
200 | EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | | |
8b260248 | 201 | EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | |
20f733e7 | 202 | EDMA_ERR_LNK_DATA_RX | |
8b260248 | 203 | EDMA_ERR_LNK_DATA_TX | |
20f733e7 BR |
204 | EDMA_ERR_TRANS_PROTO), |
205 | ||
31961943 BR |
206 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
207 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ | |
31961943 BR |
208 | |
209 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, | |
210 | EDMA_REQ_Q_PTR_SHIFT = 5, | |
211 | ||
212 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, | |
213 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, | |
214 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ | |
31961943 BR |
215 | EDMA_RSP_Q_PTR_SHIFT = 3, |
216 | ||
20f733e7 BR |
217 | EDMA_CMD_OFS = 0x28, |
218 | EDMA_EN = (1 << 0), | |
219 | EDMA_DS = (1 << 1), | |
220 | ATA_RST = (1 << 2), | |
221 | ||
c9d39130 | 222 | EDMA_IORDY_TMOUT = 0x34, |
bca1c4eb | 223 | EDMA_ARB_CFG = 0x38, |
bca1c4eb | 224 | |
31961943 BR |
225 | /* Host private flags (hp_flags) */ |
226 | MV_HP_FLAG_MSI = (1 << 0), | |
47c2b677 JG |
227 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
228 | MV_HP_ERRATA_50XXB2 = (1 << 2), | |
229 | MV_HP_ERRATA_60X1B2 = (1 << 3), | |
230 | MV_HP_ERRATA_60X1C0 = (1 << 4), | |
e4e7b892 JG |
231 | MV_HP_ERRATA_XX42A0 = (1 << 5), |
232 | MV_HP_50XX = (1 << 6), | |
233 | MV_HP_GEN_IIE = (1 << 7), | |
20f733e7 | 234 | |
31961943 BR |
235 | /* Port private flags (pp_flags) */ |
236 | MV_PP_FLAG_EDMA_EN = (1 << 0), | |
237 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), | |
20f733e7 BR |
238 | }; |
239 | ||
c9d39130 | 240 | #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX) |
bca1c4eb | 241 | #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0) |
e4e7b892 JG |
242 | #define IS_GEN_I(hpriv) IS_50XX(hpriv) |
243 | #define IS_GEN_II(hpriv) IS_60XX(hpriv) | |
244 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) | |
bca1c4eb | 245 | |
095fec88 JG |
246 | enum { |
247 | /* Our DMA boundary is determined by an ePRD being unable to handle | |
248 | * anything larger than 64KB | |
249 | */ | |
250 | MV_DMA_BOUNDARY = 0xffffU, | |
251 | ||
252 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, | |
253 | ||
254 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, | |
255 | }; | |
256 | ||
522479fb JG |
257 | enum chip_type { |
258 | chip_504x, | |
259 | chip_508x, | |
260 | chip_5080, | |
261 | chip_604x, | |
262 | chip_608x, | |
e4e7b892 JG |
263 | chip_6042, |
264 | chip_7042, | |
522479fb JG |
265 | }; |
266 | ||
31961943 BR |
267 | /* Command ReQuest Block: 32B */ |
268 | struct mv_crqb { | |
269 | u32 sg_addr; | |
270 | u32 sg_addr_hi; | |
271 | u16 ctrl_flags; | |
272 | u16 ata_cmd[11]; | |
273 | }; | |
20f733e7 | 274 | |
e4e7b892 JG |
275 | struct mv_crqb_iie { |
276 | u32 addr; | |
277 | u32 addr_hi; | |
278 | u32 flags; | |
279 | u32 len; | |
280 | u32 ata_cmd[4]; | |
281 | }; | |
282 | ||
31961943 BR |
283 | /* Command ResPonse Block: 8B */ |
284 | struct mv_crpb { | |
285 | u16 id; | |
286 | u16 flags; | |
287 | u32 tmstmp; | |
20f733e7 BR |
288 | }; |
289 | ||
31961943 BR |
290 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
291 | struct mv_sg { | |
292 | u32 addr; | |
293 | u32 flags_size; | |
294 | u32 addr_hi; | |
295 | u32 reserved; | |
296 | }; | |
20f733e7 | 297 | |
31961943 BR |
298 | struct mv_port_priv { |
299 | struct mv_crqb *crqb; | |
300 | dma_addr_t crqb_dma; | |
301 | struct mv_crpb *crpb; | |
302 | dma_addr_t crpb_dma; | |
303 | struct mv_sg *sg_tbl; | |
304 | dma_addr_t sg_tbl_dma; | |
305 | ||
306 | unsigned req_producer; /* cp of req_in_ptr */ | |
307 | unsigned rsp_consumer; /* cp of rsp_out_ptr */ | |
308 | u32 pp_flags; | |
309 | }; | |
310 | ||
bca1c4eb JG |
311 | struct mv_port_signal { |
312 | u32 amps; | |
313 | u32 pre; | |
314 | }; | |
315 | ||
47c2b677 JG |
316 | struct mv_host_priv; |
317 | struct mv_hw_ops { | |
2a47ce06 JG |
318 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
319 | unsigned int port); | |
47c2b677 JG |
320 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
321 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, | |
322 | void __iomem *mmio); | |
c9d39130 JG |
323 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
324 | unsigned int n_hc); | |
522479fb JG |
325 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
326 | void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); | |
47c2b677 JG |
327 | }; |
328 | ||
31961943 BR |
329 | struct mv_host_priv { |
330 | u32 hp_flags; | |
bca1c4eb | 331 | struct mv_port_signal signal[8]; |
47c2b677 | 332 | const struct mv_hw_ops *ops; |
20f733e7 BR |
333 | }; |
334 | ||
335 | static void mv_irq_clear(struct ata_port *ap); | |
336 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); | |
337 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | |
c9d39130 JG |
338 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in); |
339 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | |
20f733e7 | 340 | static void mv_phy_reset(struct ata_port *ap); |
22374677 | 341 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep); |
31961943 BR |
342 | static void mv_host_stop(struct ata_host_set *host_set); |
343 | static int mv_port_start(struct ata_port *ap); | |
344 | static void mv_port_stop(struct ata_port *ap); | |
345 | static void mv_qc_prep(struct ata_queued_cmd *qc); | |
e4e7b892 | 346 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
9a3d9eb0 | 347 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
20f733e7 BR |
348 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, |
349 | struct pt_regs *regs); | |
31961943 | 350 | static void mv_eng_timeout(struct ata_port *ap); |
20f733e7 BR |
351 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
352 | ||
2a47ce06 JG |
353 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
354 | unsigned int port); | |
47c2b677 JG |
355 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
356 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, | |
357 | void __iomem *mmio); | |
c9d39130 JG |
358 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
359 | unsigned int n_hc); | |
522479fb JG |
360 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
361 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio); | |
47c2b677 | 362 | |
2a47ce06 JG |
363 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
364 | unsigned int port); | |
47c2b677 JG |
365 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
366 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, | |
367 | void __iomem *mmio); | |
c9d39130 JG |
368 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
369 | unsigned int n_hc); | |
522479fb JG |
370 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
371 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio); | |
c9d39130 JG |
372 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
373 | unsigned int port_no); | |
374 | static void mv_stop_and_reset(struct ata_port *ap); | |
47c2b677 | 375 | |
193515d5 | 376 | static struct scsi_host_template mv_sht = { |
20f733e7 BR |
377 | .module = THIS_MODULE, |
378 | .name = DRV_NAME, | |
379 | .ioctl = ata_scsi_ioctl, | |
380 | .queuecommand = ata_scsi_queuecmd, | |
1b723734 | 381 | .can_queue = MV_USE_Q_DEPTH, |
20f733e7 | 382 | .this_id = ATA_SHT_THIS_ID, |
22374677 | 383 | .sg_tablesize = MV_MAX_SG_CT / 2, |
20f733e7 BR |
384 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
385 | .emulated = ATA_SHT_EMULATED, | |
31961943 | 386 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
20f733e7 BR |
387 | .proc_name = DRV_NAME, |
388 | .dma_boundary = MV_DMA_BOUNDARY, | |
389 | .slave_configure = ata_scsi_slave_config, | |
390 | .bios_param = ata_std_bios_param, | |
20f733e7 BR |
391 | }; |
392 | ||
c9d39130 JG |
393 | static const struct ata_port_operations mv5_ops = { |
394 | .port_disable = ata_port_disable, | |
395 | ||
396 | .tf_load = ata_tf_load, | |
397 | .tf_read = ata_tf_read, | |
398 | .check_status = ata_check_status, | |
399 | .exec_command = ata_exec_command, | |
400 | .dev_select = ata_std_dev_select, | |
401 | ||
402 | .phy_reset = mv_phy_reset, | |
403 | ||
404 | .qc_prep = mv_qc_prep, | |
405 | .qc_issue = mv_qc_issue, | |
406 | ||
407 | .eng_timeout = mv_eng_timeout, | |
408 | ||
409 | .irq_handler = mv_interrupt, | |
410 | .irq_clear = mv_irq_clear, | |
411 | ||
412 | .scr_read = mv5_scr_read, | |
413 | .scr_write = mv5_scr_write, | |
414 | ||
415 | .port_start = mv_port_start, | |
416 | .port_stop = mv_port_stop, | |
417 | .host_stop = mv_host_stop, | |
418 | }; | |
419 | ||
420 | static const struct ata_port_operations mv6_ops = { | |
20f733e7 BR |
421 | .port_disable = ata_port_disable, |
422 | ||
423 | .tf_load = ata_tf_load, | |
424 | .tf_read = ata_tf_read, | |
425 | .check_status = ata_check_status, | |
426 | .exec_command = ata_exec_command, | |
427 | .dev_select = ata_std_dev_select, | |
428 | ||
429 | .phy_reset = mv_phy_reset, | |
430 | ||
31961943 BR |
431 | .qc_prep = mv_qc_prep, |
432 | .qc_issue = mv_qc_issue, | |
20f733e7 | 433 | |
31961943 | 434 | .eng_timeout = mv_eng_timeout, |
20f733e7 BR |
435 | |
436 | .irq_handler = mv_interrupt, | |
437 | .irq_clear = mv_irq_clear, | |
438 | ||
439 | .scr_read = mv_scr_read, | |
440 | .scr_write = mv_scr_write, | |
441 | ||
31961943 BR |
442 | .port_start = mv_port_start, |
443 | .port_stop = mv_port_stop, | |
444 | .host_stop = mv_host_stop, | |
20f733e7 BR |
445 | }; |
446 | ||
e4e7b892 JG |
447 | static const struct ata_port_operations mv_iie_ops = { |
448 | .port_disable = ata_port_disable, | |
449 | ||
450 | .tf_load = ata_tf_load, | |
451 | .tf_read = ata_tf_read, | |
452 | .check_status = ata_check_status, | |
453 | .exec_command = ata_exec_command, | |
454 | .dev_select = ata_std_dev_select, | |
455 | ||
456 | .phy_reset = mv_phy_reset, | |
457 | ||
458 | .qc_prep = mv_qc_prep_iie, | |
459 | .qc_issue = mv_qc_issue, | |
460 | ||
461 | .eng_timeout = mv_eng_timeout, | |
462 | ||
463 | .irq_handler = mv_interrupt, | |
464 | .irq_clear = mv_irq_clear, | |
465 | ||
466 | .scr_read = mv_scr_read, | |
467 | .scr_write = mv_scr_write, | |
468 | ||
469 | .port_start = mv_port_start, | |
470 | .port_stop = mv_port_stop, | |
471 | .host_stop = mv_host_stop, | |
472 | }; | |
473 | ||
98ac62de | 474 | static const struct ata_port_info mv_port_info[] = { |
20f733e7 BR |
475 | { /* chip_504x */ |
476 | .sht = &mv_sht, | |
31961943 BR |
477 | .host_flags = MV_COMMON_FLAGS, |
478 | .pio_mask = 0x1f, /* pio0-4 */ | |
c9d39130 JG |
479 | .udma_mask = 0x7f, /* udma0-6 */ |
480 | .port_ops = &mv5_ops, | |
20f733e7 BR |
481 | }, |
482 | { /* chip_508x */ | |
483 | .sht = &mv_sht, | |
31961943 BR |
484 | .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), |
485 | .pio_mask = 0x1f, /* pio0-4 */ | |
c9d39130 JG |
486 | .udma_mask = 0x7f, /* udma0-6 */ |
487 | .port_ops = &mv5_ops, | |
20f733e7 | 488 | }, |
47c2b677 JG |
489 | { /* chip_5080 */ |
490 | .sht = &mv_sht, | |
491 | .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), | |
492 | .pio_mask = 0x1f, /* pio0-4 */ | |
c9d39130 JG |
493 | .udma_mask = 0x7f, /* udma0-6 */ |
494 | .port_ops = &mv5_ops, | |
47c2b677 | 495 | }, |
20f733e7 BR |
496 | { /* chip_604x */ |
497 | .sht = &mv_sht, | |
31961943 BR |
498 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), |
499 | .pio_mask = 0x1f, /* pio0-4 */ | |
500 | .udma_mask = 0x7f, /* udma0-6 */ | |
c9d39130 | 501 | .port_ops = &mv6_ops, |
20f733e7 BR |
502 | }, |
503 | { /* chip_608x */ | |
504 | .sht = &mv_sht, | |
8b260248 | 505 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
31961943 BR |
506 | MV_FLAG_DUAL_HC), |
507 | .pio_mask = 0x1f, /* pio0-4 */ | |
508 | .udma_mask = 0x7f, /* udma0-6 */ | |
c9d39130 | 509 | .port_ops = &mv6_ops, |
20f733e7 | 510 | }, |
e4e7b892 JG |
511 | { /* chip_6042 */ |
512 | .sht = &mv_sht, | |
513 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), | |
514 | .pio_mask = 0x1f, /* pio0-4 */ | |
515 | .udma_mask = 0x7f, /* udma0-6 */ | |
516 | .port_ops = &mv_iie_ops, | |
517 | }, | |
518 | { /* chip_7042 */ | |
519 | .sht = &mv_sht, | |
520 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | | |
521 | MV_FLAG_DUAL_HC), | |
522 | .pio_mask = 0x1f, /* pio0-4 */ | |
523 | .udma_mask = 0x7f, /* udma0-6 */ | |
524 | .port_ops = &mv_iie_ops, | |
525 | }, | |
20f733e7 BR |
526 | }; |
527 | ||
3b7d697d | 528 | static const struct pci_device_id mv_pci_tbl[] = { |
20f733e7 BR |
529 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x}, |
530 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x}, | |
47c2b677 | 531 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080}, |
20f733e7 BR |
532 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x}, |
533 | ||
534 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x}, | |
535 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x}, | |
e4e7b892 | 536 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042}, |
20f733e7 BR |
537 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x}, |
538 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x}, | |
29179539 JG |
539 | |
540 | {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x}, | |
20f733e7 BR |
541 | {} /* terminate list */ |
542 | }; | |
543 | ||
544 | static struct pci_driver mv_pci_driver = { | |
545 | .name = DRV_NAME, | |
546 | .id_table = mv_pci_tbl, | |
547 | .probe = mv_init_one, | |
548 | .remove = ata_pci_remove_one, | |
549 | }; | |
550 | ||
47c2b677 JG |
551 | static const struct mv_hw_ops mv5xxx_ops = { |
552 | .phy_errata = mv5_phy_errata, | |
553 | .enable_leds = mv5_enable_leds, | |
554 | .read_preamp = mv5_read_preamp, | |
555 | .reset_hc = mv5_reset_hc, | |
522479fb JG |
556 | .reset_flash = mv5_reset_flash, |
557 | .reset_bus = mv5_reset_bus, | |
47c2b677 JG |
558 | }; |
559 | ||
560 | static const struct mv_hw_ops mv6xxx_ops = { | |
561 | .phy_errata = mv6_phy_errata, | |
562 | .enable_leds = mv6_enable_leds, | |
563 | .read_preamp = mv6_read_preamp, | |
564 | .reset_hc = mv6_reset_hc, | |
522479fb JG |
565 | .reset_flash = mv6_reset_flash, |
566 | .reset_bus = mv_reset_pci_bus, | |
47c2b677 JG |
567 | }; |
568 | ||
ddef9bb3 JG |
569 | /* |
570 | * module options | |
571 | */ | |
572 | static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ | |
573 | ||
574 | ||
20f733e7 BR |
575 | /* |
576 | * Functions | |
577 | */ | |
578 | ||
579 | static inline void writelfl(unsigned long data, void __iomem *addr) | |
580 | { | |
581 | writel(data, addr); | |
582 | (void) readl(addr); /* flush to avoid PCI posted write */ | |
583 | } | |
584 | ||
20f733e7 BR |
585 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
586 | { | |
587 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); | |
588 | } | |
589 | ||
c9d39130 JG |
590 | static inline unsigned int mv_hc_from_port(unsigned int port) |
591 | { | |
592 | return port >> MV_PORT_HC_SHIFT; | |
593 | } | |
594 | ||
595 | static inline unsigned int mv_hardport_from_port(unsigned int port) | |
596 | { | |
597 | return port & MV_PORT_MASK; | |
598 | } | |
599 | ||
600 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, | |
601 | unsigned int port) | |
602 | { | |
603 | return mv_hc_base(base, mv_hc_from_port(port)); | |
604 | } | |
605 | ||
20f733e7 BR |
606 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
607 | { | |
c9d39130 | 608 | return mv_hc_base_from_port(base, port) + |
8b260248 | 609 | MV_SATAHC_ARBTR_REG_SZ + |
c9d39130 | 610 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
20f733e7 BR |
611 | } |
612 | ||
613 | static inline void __iomem *mv_ap_base(struct ata_port *ap) | |
614 | { | |
615 | return mv_port_base(ap->host_set->mmio_base, ap->port_no); | |
616 | } | |
617 | ||
bca1c4eb | 618 | static inline int mv_get_hc_count(unsigned long host_flags) |
31961943 | 619 | { |
bca1c4eb | 620 | return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
31961943 BR |
621 | } |
622 | ||
623 | static void mv_irq_clear(struct ata_port *ap) | |
20f733e7 | 624 | { |
20f733e7 BR |
625 | } |
626 | ||
05b308e1 BR |
627 | /** |
628 | * mv_start_dma - Enable eDMA engine | |
629 | * @base: port base address | |
630 | * @pp: port private data | |
631 | * | |
beec7dbc TH |
632 | * Verify the local cache of the eDMA state is accurate with a |
633 | * WARN_ON. | |
05b308e1 BR |
634 | * |
635 | * LOCKING: | |
636 | * Inherited from caller. | |
637 | */ | |
afb0edd9 | 638 | static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp) |
20f733e7 | 639 | { |
afb0edd9 BR |
640 | if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) { |
641 | writelfl(EDMA_EN, base + EDMA_CMD_OFS); | |
642 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; | |
643 | } | |
beec7dbc | 644 | WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS))); |
20f733e7 BR |
645 | } |
646 | ||
05b308e1 BR |
647 | /** |
648 | * mv_stop_dma - Disable eDMA engine | |
649 | * @ap: ATA channel to manipulate | |
650 | * | |
beec7dbc TH |
651 | * Verify the local cache of the eDMA state is accurate with a |
652 | * WARN_ON. | |
05b308e1 BR |
653 | * |
654 | * LOCKING: | |
655 | * Inherited from caller. | |
656 | */ | |
31961943 | 657 | static void mv_stop_dma(struct ata_port *ap) |
20f733e7 | 658 | { |
31961943 BR |
659 | void __iomem *port_mmio = mv_ap_base(ap); |
660 | struct mv_port_priv *pp = ap->private_data; | |
31961943 BR |
661 | u32 reg; |
662 | int i; | |
663 | ||
afb0edd9 BR |
664 | if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) { |
665 | /* Disable EDMA if active. The disable bit auto clears. | |
31961943 | 666 | */ |
31961943 BR |
667 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
668 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
afb0edd9 | 669 | } else { |
beec7dbc | 670 | WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)); |
afb0edd9 | 671 | } |
8b260248 | 672 | |
31961943 BR |
673 | /* now properly wait for the eDMA to stop */ |
674 | for (i = 1000; i > 0; i--) { | |
675 | reg = readl(port_mmio + EDMA_CMD_OFS); | |
676 | if (!(EDMA_EN & reg)) { | |
677 | break; | |
678 | } | |
679 | udelay(100); | |
680 | } | |
681 | ||
31961943 BR |
682 | if (EDMA_EN & reg) { |
683 | printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id); | |
afb0edd9 | 684 | /* FIXME: Consider doing a reset here to recover */ |
31961943 | 685 | } |
20f733e7 BR |
686 | } |
687 | ||
8a70f8dc | 688 | #ifdef ATA_DEBUG |
31961943 | 689 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
20f733e7 | 690 | { |
31961943 BR |
691 | int b, w; |
692 | for (b = 0; b < bytes; ) { | |
693 | DPRINTK("%p: ", start + b); | |
694 | for (w = 0; b < bytes && w < 4; w++) { | |
695 | printk("%08x ",readl(start + b)); | |
696 | b += sizeof(u32); | |
697 | } | |
698 | printk("\n"); | |
699 | } | |
31961943 | 700 | } |
8a70f8dc JG |
701 | #endif |
702 | ||
31961943 BR |
703 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
704 | { | |
705 | #ifdef ATA_DEBUG | |
706 | int b, w; | |
707 | u32 dw; | |
708 | for (b = 0; b < bytes; ) { | |
709 | DPRINTK("%02x: ", b); | |
710 | for (w = 0; b < bytes && w < 4; w++) { | |
711 | (void) pci_read_config_dword(pdev,b,&dw); | |
712 | printk("%08x ",dw); | |
713 | b += sizeof(u32); | |
714 | } | |
715 | printk("\n"); | |
716 | } | |
717 | #endif | |
718 | } | |
719 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, | |
720 | struct pci_dev *pdev) | |
721 | { | |
722 | #ifdef ATA_DEBUG | |
8b260248 | 723 | void __iomem *hc_base = mv_hc_base(mmio_base, |
31961943 BR |
724 | port >> MV_PORT_HC_SHIFT); |
725 | void __iomem *port_base; | |
726 | int start_port, num_ports, p, start_hc, num_hcs, hc; | |
727 | ||
728 | if (0 > port) { | |
729 | start_hc = start_port = 0; | |
730 | num_ports = 8; /* shld be benign for 4 port devs */ | |
731 | num_hcs = 2; | |
732 | } else { | |
733 | start_hc = port >> MV_PORT_HC_SHIFT; | |
734 | start_port = port; | |
735 | num_ports = num_hcs = 1; | |
736 | } | |
8b260248 | 737 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
31961943 BR |
738 | num_ports > 1 ? num_ports - 1 : start_port); |
739 | ||
740 | if (NULL != pdev) { | |
741 | DPRINTK("PCI config space regs:\n"); | |
742 | mv_dump_pci_cfg(pdev, 0x68); | |
743 | } | |
744 | DPRINTK("PCI regs:\n"); | |
745 | mv_dump_mem(mmio_base+0xc00, 0x3c); | |
746 | mv_dump_mem(mmio_base+0xd00, 0x34); | |
747 | mv_dump_mem(mmio_base+0xf00, 0x4); | |
748 | mv_dump_mem(mmio_base+0x1d00, 0x6c); | |
749 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { | |
750 | hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT); | |
751 | DPRINTK("HC regs (HC %i):\n", hc); | |
752 | mv_dump_mem(hc_base, 0x1c); | |
753 | } | |
754 | for (p = start_port; p < start_port + num_ports; p++) { | |
755 | port_base = mv_port_base(mmio_base, p); | |
756 | DPRINTK("EDMA regs (port %i):\n",p); | |
757 | mv_dump_mem(port_base, 0x54); | |
758 | DPRINTK("SATA regs (port %i):\n",p); | |
759 | mv_dump_mem(port_base+0x300, 0x60); | |
760 | } | |
761 | #endif | |
20f733e7 BR |
762 | } |
763 | ||
764 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) | |
765 | { | |
766 | unsigned int ofs; | |
767 | ||
768 | switch (sc_reg_in) { | |
769 | case SCR_STATUS: | |
770 | case SCR_CONTROL: | |
771 | case SCR_ERROR: | |
772 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); | |
773 | break; | |
774 | case SCR_ACTIVE: | |
775 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ | |
776 | break; | |
777 | default: | |
778 | ofs = 0xffffffffU; | |
779 | break; | |
780 | } | |
781 | return ofs; | |
782 | } | |
783 | ||
784 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | |
785 | { | |
786 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
787 | ||
788 | if (0xffffffffU != ofs) { | |
789 | return readl(mv_ap_base(ap) + ofs); | |
790 | } else { | |
791 | return (u32) ofs; | |
792 | } | |
793 | } | |
794 | ||
795 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | |
796 | { | |
797 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
798 | ||
799 | if (0xffffffffU != ofs) { | |
800 | writelfl(val, mv_ap_base(ap) + ofs); | |
801 | } | |
802 | } | |
803 | ||
05b308e1 BR |
804 | /** |
805 | * mv_host_stop - Host specific cleanup/stop routine. | |
806 | * @host_set: host data structure | |
807 | * | |
808 | * Disable ints, cleanup host memory, call general purpose | |
809 | * host_stop. | |
810 | * | |
811 | * LOCKING: | |
812 | * Inherited from caller. | |
813 | */ | |
31961943 | 814 | static void mv_host_stop(struct ata_host_set *host_set) |
20f733e7 | 815 | { |
31961943 BR |
816 | struct mv_host_priv *hpriv = host_set->private_data; |
817 | struct pci_dev *pdev = to_pci_dev(host_set->dev); | |
818 | ||
819 | if (hpriv->hp_flags & MV_HP_FLAG_MSI) { | |
820 | pci_disable_msi(pdev); | |
821 | } else { | |
822 | pci_intx(pdev, 0); | |
823 | } | |
824 | kfree(hpriv); | |
825 | ata_host_stop(host_set); | |
826 | } | |
827 | ||
6037d6bb JG |
828 | static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev) |
829 | { | |
830 | dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma); | |
831 | } | |
832 | ||
e4e7b892 JG |
833 | static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio) |
834 | { | |
835 | u32 cfg = readl(port_mmio + EDMA_CFG_OFS); | |
836 | ||
837 | /* set up non-NCQ EDMA configuration */ | |
838 | cfg &= ~0x1f; /* clear queue depth */ | |
839 | cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */ | |
840 | cfg &= ~(1 << 9); /* disable equeue */ | |
841 | ||
842 | if (IS_GEN_I(hpriv)) | |
843 | cfg |= (1 << 8); /* enab config burst size mask */ | |
844 | ||
845 | else if (IS_GEN_II(hpriv)) | |
846 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; | |
847 | ||
848 | else if (IS_GEN_IIE(hpriv)) { | |
849 | cfg |= (1 << 23); /* dis RX PM port mask */ | |
850 | cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */ | |
851 | cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */ | |
852 | cfg |= (1 << 18); /* enab early completion */ | |
853 | cfg |= (1 << 17); /* enab host q cache */ | |
854 | cfg |= (1 << 22); /* enab cutthrough */ | |
855 | } | |
856 | ||
857 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); | |
858 | } | |
859 | ||
05b308e1 BR |
860 | /** |
861 | * mv_port_start - Port specific init/start routine. | |
862 | * @ap: ATA channel to manipulate | |
863 | * | |
864 | * Allocate and point to DMA memory, init port private memory, | |
865 | * zero indices. | |
866 | * | |
867 | * LOCKING: | |
868 | * Inherited from caller. | |
869 | */ | |
31961943 BR |
870 | static int mv_port_start(struct ata_port *ap) |
871 | { | |
872 | struct device *dev = ap->host_set->dev; | |
e4e7b892 | 873 | struct mv_host_priv *hpriv = ap->host_set->private_data; |
31961943 BR |
874 | struct mv_port_priv *pp; |
875 | void __iomem *port_mmio = mv_ap_base(ap); | |
876 | void *mem; | |
877 | dma_addr_t mem_dma; | |
6037d6bb | 878 | int rc = -ENOMEM; |
31961943 BR |
879 | |
880 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
6037d6bb JG |
881 | if (!pp) |
882 | goto err_out; | |
31961943 BR |
883 | memset(pp, 0, sizeof(*pp)); |
884 | ||
8b260248 | 885 | mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, |
31961943 | 886 | GFP_KERNEL); |
6037d6bb JG |
887 | if (!mem) |
888 | goto err_out_pp; | |
31961943 BR |
889 | memset(mem, 0, MV_PORT_PRIV_DMA_SZ); |
890 | ||
6037d6bb JG |
891 | rc = ata_pad_alloc(ap, dev); |
892 | if (rc) | |
893 | goto err_out_priv; | |
894 | ||
8b260248 | 895 | /* First item in chunk of DMA memory: |
31961943 BR |
896 | * 32-slot command request table (CRQB), 32 bytes each in size |
897 | */ | |
898 | pp->crqb = mem; | |
899 | pp->crqb_dma = mem_dma; | |
900 | mem += MV_CRQB_Q_SZ; | |
901 | mem_dma += MV_CRQB_Q_SZ; | |
902 | ||
8b260248 | 903 | /* Second item: |
31961943 BR |
904 | * 32-slot command response table (CRPB), 8 bytes each in size |
905 | */ | |
906 | pp->crpb = mem; | |
907 | pp->crpb_dma = mem_dma; | |
908 | mem += MV_CRPB_Q_SZ; | |
909 | mem_dma += MV_CRPB_Q_SZ; | |
910 | ||
911 | /* Third item: | |
912 | * Table of scatter-gather descriptors (ePRD), 16 bytes each | |
913 | */ | |
914 | pp->sg_tbl = mem; | |
915 | pp->sg_tbl_dma = mem_dma; | |
916 | ||
e4e7b892 | 917 | mv_edma_cfg(hpriv, port_mmio); |
31961943 BR |
918 | |
919 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); | |
8b260248 | 920 | writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, |
31961943 BR |
921 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
922 | ||
e4e7b892 JG |
923 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
924 | writelfl(pp->crqb_dma & 0xffffffff, | |
925 | port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); | |
926 | else | |
927 | writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); | |
31961943 BR |
928 | |
929 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); | |
e4e7b892 JG |
930 | |
931 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) | |
932 | writelfl(pp->crpb_dma & 0xffffffff, | |
933 | port_mmio + EDMA_RSP_Q_IN_PTR_OFS); | |
934 | else | |
935 | writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); | |
936 | ||
8b260248 | 937 | writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, |
31961943 BR |
938 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
939 | ||
940 | pp->req_producer = pp->rsp_consumer = 0; | |
941 | ||
942 | /* Don't turn on EDMA here...do it before DMA commands only. Else | |
943 | * we'll be unable to send non-data, PIO, etc due to restricted access | |
944 | * to shadow regs. | |
945 | */ | |
946 | ap->private_data = pp; | |
947 | return 0; | |
6037d6bb JG |
948 | |
949 | err_out_priv: | |
950 | mv_priv_free(pp, dev); | |
951 | err_out_pp: | |
952 | kfree(pp); | |
953 | err_out: | |
954 | return rc; | |
31961943 BR |
955 | } |
956 | ||
05b308e1 BR |
957 | /** |
958 | * mv_port_stop - Port specific cleanup/stop routine. | |
959 | * @ap: ATA channel to manipulate | |
960 | * | |
961 | * Stop DMA, cleanup port memory. | |
962 | * | |
963 | * LOCKING: | |
964 | * This routine uses the host_set lock to protect the DMA stop. | |
965 | */ | |
31961943 BR |
966 | static void mv_port_stop(struct ata_port *ap) |
967 | { | |
968 | struct device *dev = ap->host_set->dev; | |
969 | struct mv_port_priv *pp = ap->private_data; | |
afb0edd9 | 970 | unsigned long flags; |
31961943 | 971 | |
afb0edd9 | 972 | spin_lock_irqsave(&ap->host_set->lock, flags); |
31961943 | 973 | mv_stop_dma(ap); |
afb0edd9 | 974 | spin_unlock_irqrestore(&ap->host_set->lock, flags); |
31961943 BR |
975 | |
976 | ap->private_data = NULL; | |
6037d6bb JG |
977 | ata_pad_free(ap, dev); |
978 | mv_priv_free(pp, dev); | |
31961943 BR |
979 | kfree(pp); |
980 | } | |
981 | ||
05b308e1 BR |
982 | /** |
983 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries | |
984 | * @qc: queued command whose SG list to source from | |
985 | * | |
986 | * Populate the SG list and mark the last entry. | |
987 | * | |
988 | * LOCKING: | |
989 | * Inherited from caller. | |
990 | */ | |
31961943 BR |
991 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
992 | { | |
993 | struct mv_port_priv *pp = qc->ap->private_data; | |
972c26bd JG |
994 | unsigned int i = 0; |
995 | struct scatterlist *sg; | |
31961943 | 996 | |
972c26bd | 997 | ata_for_each_sg(sg, qc) { |
31961943 | 998 | dma_addr_t addr; |
22374677 | 999 | u32 sg_len, len, offset; |
31961943 | 1000 | |
972c26bd JG |
1001 | addr = sg_dma_address(sg); |
1002 | sg_len = sg_dma_len(sg); | |
31961943 | 1003 | |
22374677 JG |
1004 | while (sg_len) { |
1005 | offset = addr & MV_DMA_BOUNDARY; | |
1006 | len = sg_len; | |
1007 | if ((offset + sg_len) > 0x10000) | |
1008 | len = 0x10000 - offset; | |
972c26bd | 1009 | |
22374677 JG |
1010 | pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); |
1011 | pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
63af2a5c | 1012 | pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff); |
22374677 JG |
1013 | |
1014 | sg_len -= len; | |
1015 | addr += len; | |
1016 | ||
1017 | if (!sg_len && ata_sg_is_last(sg, qc)) | |
1018 | pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); | |
1019 | ||
1020 | i++; | |
1021 | } | |
31961943 BR |
1022 | } |
1023 | } | |
1024 | ||
1025 | static inline unsigned mv_inc_q_index(unsigned *index) | |
1026 | { | |
1027 | *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK; | |
1028 | return *index; | |
1029 | } | |
1030 | ||
1031 | static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last) | |
1032 | { | |
1033 | *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | | |
1034 | (last ? CRQB_CMD_LAST : 0); | |
1035 | } | |
1036 | ||
05b308e1 BR |
1037 | /** |
1038 | * mv_qc_prep - Host specific command preparation. | |
1039 | * @qc: queued command to prepare | |
1040 | * | |
1041 | * This routine simply redirects to the general purpose routine | |
1042 | * if command is not DMA. Else, it handles prep of the CRQB | |
1043 | * (command request block), does some sanity checking, and calls | |
1044 | * the SG load routine. | |
1045 | * | |
1046 | * LOCKING: | |
1047 | * Inherited from caller. | |
1048 | */ | |
31961943 BR |
1049 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
1050 | { | |
1051 | struct ata_port *ap = qc->ap; | |
1052 | struct mv_port_priv *pp = ap->private_data; | |
1053 | u16 *cw; | |
1054 | struct ata_taskfile *tf; | |
1055 | u16 flags = 0; | |
1056 | ||
e4e7b892 | 1057 | if (ATA_PROT_DMA != qc->tf.protocol) |
31961943 | 1058 | return; |
20f733e7 | 1059 | |
31961943 | 1060 | /* the req producer index should be the same as we remember it */ |
beec7dbc TH |
1061 | WARN_ON(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> |
1062 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) != | |
1063 | pp->req_producer); | |
31961943 BR |
1064 | |
1065 | /* Fill in command request block | |
1066 | */ | |
e4e7b892 | 1067 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
31961943 | 1068 | flags |= CRQB_FLAG_READ; |
beec7dbc | 1069 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
31961943 BR |
1070 | flags |= qc->tag << CRQB_TAG_SHIFT; |
1071 | ||
8b260248 | 1072 | pp->crqb[pp->req_producer].sg_addr = |
31961943 | 1073 | cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); |
8b260248 | 1074 | pp->crqb[pp->req_producer].sg_addr_hi = |
31961943 BR |
1075 | cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); |
1076 | pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags); | |
1077 | ||
1078 | cw = &pp->crqb[pp->req_producer].ata_cmd[0]; | |
1079 | tf = &qc->tf; | |
1080 | ||
1081 | /* Sadly, the CRQB cannot accomodate all registers--there are | |
1082 | * only 11 bytes...so we must pick and choose required | |
1083 | * registers based on the command. So, we drop feature and | |
1084 | * hob_feature for [RW] DMA commands, but they are needed for | |
1085 | * NCQ. NCQ will drop hob_nsect. | |
20f733e7 | 1086 | */ |
31961943 BR |
1087 | switch (tf->command) { |
1088 | case ATA_CMD_READ: | |
1089 | case ATA_CMD_READ_EXT: | |
1090 | case ATA_CMD_WRITE: | |
1091 | case ATA_CMD_WRITE_EXT: | |
c15d85c8 | 1092 | case ATA_CMD_WRITE_FUA_EXT: |
31961943 BR |
1093 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
1094 | break; | |
1095 | #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ | |
1096 | case ATA_CMD_FPDMA_READ: | |
1097 | case ATA_CMD_FPDMA_WRITE: | |
8b260248 | 1098 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
31961943 BR |
1099 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
1100 | break; | |
1101 | #endif /* FIXME: remove this line when NCQ added */ | |
1102 | default: | |
1103 | /* The only other commands EDMA supports in non-queued and | |
1104 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none | |
1105 | * of which are defined/used by Linux. If we get here, this | |
1106 | * driver needs work. | |
1107 | * | |
1108 | * FIXME: modify libata to give qc_prep a return value and | |
1109 | * return error here. | |
1110 | */ | |
1111 | BUG_ON(tf->command); | |
1112 | break; | |
1113 | } | |
1114 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); | |
1115 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); | |
1116 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); | |
1117 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); | |
1118 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); | |
1119 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); | |
1120 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); | |
1121 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); | |
1122 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ | |
1123 | ||
e4e7b892 JG |
1124 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
1125 | return; | |
1126 | mv_fill_sg(qc); | |
1127 | } | |
1128 | ||
1129 | /** | |
1130 | * mv_qc_prep_iie - Host specific command preparation. | |
1131 | * @qc: queued command to prepare | |
1132 | * | |
1133 | * This routine simply redirects to the general purpose routine | |
1134 | * if command is not DMA. Else, it handles prep of the CRQB | |
1135 | * (command request block), does some sanity checking, and calls | |
1136 | * the SG load routine. | |
1137 | * | |
1138 | * LOCKING: | |
1139 | * Inherited from caller. | |
1140 | */ | |
1141 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) | |
1142 | { | |
1143 | struct ata_port *ap = qc->ap; | |
1144 | struct mv_port_priv *pp = ap->private_data; | |
1145 | struct mv_crqb_iie *crqb; | |
1146 | struct ata_taskfile *tf; | |
1147 | u32 flags = 0; | |
1148 | ||
1149 | if (ATA_PROT_DMA != qc->tf.protocol) | |
1150 | return; | |
1151 | ||
1152 | /* the req producer index should be the same as we remember it */ | |
beec7dbc TH |
1153 | WARN_ON(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> |
1154 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) != | |
1155 | pp->req_producer); | |
e4e7b892 JG |
1156 | |
1157 | /* Fill in Gen IIE command request block | |
1158 | */ | |
1159 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
1160 | flags |= CRQB_FLAG_READ; | |
1161 | ||
beec7dbc | 1162 | WARN_ON(MV_MAX_Q_DEPTH <= qc->tag); |
e4e7b892 JG |
1163 | flags |= qc->tag << CRQB_TAG_SHIFT; |
1164 | ||
1165 | crqb = (struct mv_crqb_iie *) &pp->crqb[pp->req_producer]; | |
1166 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); | |
1167 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); | |
1168 | crqb->flags = cpu_to_le32(flags); | |
1169 | ||
1170 | tf = &qc->tf; | |
1171 | crqb->ata_cmd[0] = cpu_to_le32( | |
1172 | (tf->command << 16) | | |
1173 | (tf->feature << 24) | |
1174 | ); | |
1175 | crqb->ata_cmd[1] = cpu_to_le32( | |
1176 | (tf->lbal << 0) | | |
1177 | (tf->lbam << 8) | | |
1178 | (tf->lbah << 16) | | |
1179 | (tf->device << 24) | |
1180 | ); | |
1181 | crqb->ata_cmd[2] = cpu_to_le32( | |
1182 | (tf->hob_lbal << 0) | | |
1183 | (tf->hob_lbam << 8) | | |
1184 | (tf->hob_lbah << 16) | | |
1185 | (tf->hob_feature << 24) | |
1186 | ); | |
1187 | crqb->ata_cmd[3] = cpu_to_le32( | |
1188 | (tf->nsect << 0) | | |
1189 | (tf->hob_nsect << 8) | |
1190 | ); | |
1191 | ||
1192 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
31961943 | 1193 | return; |
31961943 BR |
1194 | mv_fill_sg(qc); |
1195 | } | |
1196 | ||
05b308e1 BR |
1197 | /** |
1198 | * mv_qc_issue - Initiate a command to the host | |
1199 | * @qc: queued command to start | |
1200 | * | |
1201 | * This routine simply redirects to the general purpose routine | |
1202 | * if command is not DMA. Else, it sanity checks our local | |
1203 | * caches of the request producer/consumer indices then enables | |
1204 | * DMA and bumps the request producer index. | |
1205 | * | |
1206 | * LOCKING: | |
1207 | * Inherited from caller. | |
1208 | */ | |
9a3d9eb0 | 1209 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
31961943 BR |
1210 | { |
1211 | void __iomem *port_mmio = mv_ap_base(qc->ap); | |
1212 | struct mv_port_priv *pp = qc->ap->private_data; | |
1213 | u32 in_ptr; | |
1214 | ||
1215 | if (ATA_PROT_DMA != qc->tf.protocol) { | |
1216 | /* We're about to send a non-EDMA capable command to the | |
1217 | * port. Turn off EDMA so there won't be problems accessing | |
1218 | * shadow block, etc registers. | |
1219 | */ | |
1220 | mv_stop_dma(qc->ap); | |
1221 | return ata_qc_issue_prot(qc); | |
1222 | } | |
1223 | ||
1224 | in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | |
1225 | ||
1226 | /* the req producer index should be the same as we remember it */ | |
beec7dbc TH |
1227 | WARN_ON(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) != |
1228 | pp->req_producer); | |
31961943 | 1229 | /* until we do queuing, the queue should be empty at this point */ |
beec7dbc TH |
1230 | WARN_ON(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) != |
1231 | ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >> | |
1232 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); | |
31961943 BR |
1233 | |
1234 | mv_inc_q_index(&pp->req_producer); /* now incr producer index */ | |
1235 | ||
afb0edd9 | 1236 | mv_start_dma(port_mmio, pp); |
31961943 BR |
1237 | |
1238 | /* and write the request in pointer to kick the EDMA to life */ | |
1239 | in_ptr &= EDMA_REQ_Q_BASE_LO_MASK; | |
1240 | in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT; | |
1241 | writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | |
1242 | ||
1243 | return 0; | |
1244 | } | |
1245 | ||
05b308e1 BR |
1246 | /** |
1247 | * mv_get_crpb_status - get status from most recently completed cmd | |
1248 | * @ap: ATA channel to manipulate | |
1249 | * | |
1250 | * This routine is for use when the port is in DMA mode, when it | |
1251 | * will be using the CRPB (command response block) method of | |
beec7dbc | 1252 | * returning command completion information. We check indices |
05b308e1 BR |
1253 | * are good, grab status, and bump the response consumer index to |
1254 | * prove that we're up to date. | |
1255 | * | |
1256 | * LOCKING: | |
1257 | * Inherited from caller. | |
1258 | */ | |
31961943 BR |
1259 | static u8 mv_get_crpb_status(struct ata_port *ap) |
1260 | { | |
1261 | void __iomem *port_mmio = mv_ap_base(ap); | |
1262 | struct mv_port_priv *pp = ap->private_data; | |
1263 | u32 out_ptr; | |
806a6e7a | 1264 | u8 ata_status; |
31961943 BR |
1265 | |
1266 | out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | |
1267 | ||
1268 | /* the response consumer index should be the same as we remember it */ | |
beec7dbc TH |
1269 | WARN_ON(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) != |
1270 | pp->rsp_consumer); | |
31961943 | 1271 | |
806a6e7a ML |
1272 | ata_status = pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT; |
1273 | ||
31961943 BR |
1274 | /* increment our consumer index... */ |
1275 | pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer); | |
8b260248 | 1276 | |
31961943 | 1277 | /* and, until we do NCQ, there should only be 1 CRPB waiting */ |
beec7dbc TH |
1278 | WARN_ON(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >> |
1279 | EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) != | |
1280 | pp->rsp_consumer); | |
31961943 BR |
1281 | |
1282 | /* write out our inc'd consumer index so EDMA knows we're caught up */ | |
1283 | out_ptr &= EDMA_RSP_Q_BASE_LO_MASK; | |
1284 | out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT; | |
1285 | writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | |
1286 | ||
1287 | /* Return ATA status register for completed CRPB */ | |
806a6e7a | 1288 | return ata_status; |
31961943 BR |
1289 | } |
1290 | ||
05b308e1 BR |
1291 | /** |
1292 | * mv_err_intr - Handle error interrupts on the port | |
1293 | * @ap: ATA channel to manipulate | |
1294 | * | |
1295 | * In most cases, just clear the interrupt and move on. However, | |
1296 | * some cases require an eDMA reset, which is done right before | |
1297 | * the COMRESET in mv_phy_reset(). The SERR case requires a | |
1298 | * clear of pending errors in the SATA SERROR register. Finally, | |
1299 | * if the port disabled DMA, update our cached copy to match. | |
1300 | * | |
1301 | * LOCKING: | |
1302 | * Inherited from caller. | |
1303 | */ | |
31961943 BR |
1304 | static void mv_err_intr(struct ata_port *ap) |
1305 | { | |
1306 | void __iomem *port_mmio = mv_ap_base(ap); | |
1307 | u32 edma_err_cause, serr = 0; | |
20f733e7 BR |
1308 | |
1309 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1310 | ||
1311 | if (EDMA_ERR_SERR & edma_err_cause) { | |
1312 | serr = scr_read(ap, SCR_ERROR); | |
1313 | scr_write_flush(ap, SCR_ERROR, serr); | |
1314 | } | |
afb0edd9 BR |
1315 | if (EDMA_ERR_SELF_DIS & edma_err_cause) { |
1316 | struct mv_port_priv *pp = ap->private_data; | |
1317 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
1318 | } | |
1319 | DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x " | |
1320 | "SERR: 0x%08x\n", ap->id, edma_err_cause, serr); | |
20f733e7 BR |
1321 | |
1322 | /* Clear EDMA now that SERR cleanup done */ | |
1323 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1324 | ||
1325 | /* check for fatal here and recover if needed */ | |
1326 | if (EDMA_ERR_FATAL & edma_err_cause) { | |
c9d39130 | 1327 | mv_stop_and_reset(ap); |
20f733e7 BR |
1328 | } |
1329 | } | |
1330 | ||
05b308e1 BR |
1331 | /** |
1332 | * mv_host_intr - Handle all interrupts on the given host controller | |
1333 | * @host_set: host specific structure | |
1334 | * @relevant: port error bits relevant to this host controller | |
1335 | * @hc: which host controller we're to look at | |
1336 | * | |
1337 | * Read then write clear the HC interrupt status then walk each | |
1338 | * port connected to the HC and see if it needs servicing. Port | |
1339 | * success ints are reported in the HC interrupt status reg, the | |
1340 | * port error ints are reported in the higher level main | |
1341 | * interrupt status register and thus are passed in via the | |
1342 | * 'relevant' argument. | |
1343 | * | |
1344 | * LOCKING: | |
1345 | * Inherited from caller. | |
1346 | */ | |
20f733e7 BR |
1347 | static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, |
1348 | unsigned int hc) | |
1349 | { | |
1350 | void __iomem *mmio = host_set->mmio_base; | |
1351 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); | |
20f733e7 BR |
1352 | struct ata_queued_cmd *qc; |
1353 | u32 hc_irq_cause; | |
31961943 | 1354 | int shift, port, port0, hard_port, handled; |
a7dac447 | 1355 | unsigned int err_mask; |
20f733e7 BR |
1356 | |
1357 | if (hc == 0) { | |
1358 | port0 = 0; | |
1359 | } else { | |
1360 | port0 = MV_PORTS_PER_HC; | |
1361 | } | |
1362 | ||
1363 | /* we'll need the HC success int register in most cases */ | |
1364 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); | |
1365 | if (hc_irq_cause) { | |
31961943 | 1366 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
20f733e7 BR |
1367 | } |
1368 | ||
1369 | VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", | |
1370 | hc,relevant,hc_irq_cause); | |
1371 | ||
1372 | for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) { | |
cd85f6e2 | 1373 | u8 ata_status = 0; |
63af2a5c ML |
1374 | struct ata_port *ap = host_set->ports[port]; |
1375 | struct mv_port_priv *pp = ap->private_data; | |
55d8ca4f | 1376 | |
20f733e7 | 1377 | hard_port = port & MV_PORT_MASK; /* range 0-3 */ |
31961943 | 1378 | handled = 0; /* ensure ata_status is set if handled++ */ |
20f733e7 | 1379 | |
63af2a5c ML |
1380 | /* Note that DEV_IRQ might happen spuriously during EDMA, |
1381 | * and should be ignored in such cases. We could mask it, | |
1382 | * but it's pretty rare and may not be worth the overhead. | |
1383 | */ | |
1384 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { | |
1385 | /* EDMA: check for response queue interrupt */ | |
1386 | if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) { | |
1387 | ata_status = mv_get_crpb_status(ap); | |
1388 | handled = 1; | |
1389 | } | |
1390 | } else { | |
1391 | /* PIO: check for device (drive) interrupt */ | |
1392 | if ((DEV_IRQ << hard_port) & hc_irq_cause) { | |
1393 | ata_status = readb((void __iomem *) | |
20f733e7 | 1394 | ap->ioaddr.status_addr); |
63af2a5c ML |
1395 | handled = 1; |
1396 | } | |
20f733e7 BR |
1397 | } |
1398 | ||
63af2a5c | 1399 | if (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)) |
a2c91a88 JG |
1400 | continue; |
1401 | ||
a7dac447 JG |
1402 | err_mask = ac_err_mask(ata_status); |
1403 | ||
31961943 | 1404 | shift = port << 1; /* (port * 2) */ |
20f733e7 BR |
1405 | if (port >= MV_PORTS_PER_HC) { |
1406 | shift++; /* skip bit 8 in the HC Main IRQ reg */ | |
1407 | } | |
1408 | if ((PORT0_ERR << shift) & relevant) { | |
1409 | mv_err_intr(ap); | |
a7dac447 | 1410 | err_mask |= AC_ERR_OTHER; |
63af2a5c | 1411 | handled = 1; |
20f733e7 | 1412 | } |
8b260248 | 1413 | |
63af2a5c | 1414 | if (handled) { |
20f733e7 | 1415 | qc = ata_qc_from_tag(ap, ap->active_tag); |
63af2a5c | 1416 | if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) { |
20f733e7 BR |
1417 | VPRINTK("port %u IRQ found for qc, " |
1418 | "ata_status 0x%x\n", port,ata_status); | |
20f733e7 | 1419 | /* mark qc status appropriately */ |
a22e2eb0 AL |
1420 | if (!(qc->tf.ctl & ATA_NIEN)) { |
1421 | qc->err_mask |= err_mask; | |
1422 | ata_qc_complete(qc); | |
1423 | } | |
20f733e7 BR |
1424 | } |
1425 | } | |
1426 | } | |
1427 | VPRINTK("EXIT\n"); | |
1428 | } | |
1429 | ||
05b308e1 | 1430 | /** |
8b260248 | 1431 | * mv_interrupt - |
05b308e1 BR |
1432 | * @irq: unused |
1433 | * @dev_instance: private data; in this case the host structure | |
1434 | * @regs: unused | |
1435 | * | |
1436 | * Read the read only register to determine if any host | |
1437 | * controllers have pending interrupts. If so, call lower level | |
1438 | * routine to handle. Also check for PCI errors which are only | |
1439 | * reported here. | |
1440 | * | |
8b260248 | 1441 | * LOCKING: |
05b308e1 BR |
1442 | * This routine holds the host_set lock while processing pending |
1443 | * interrupts. | |
1444 | */ | |
20f733e7 BR |
1445 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, |
1446 | struct pt_regs *regs) | |
1447 | { | |
1448 | struct ata_host_set *host_set = dev_instance; | |
1449 | unsigned int hc, handled = 0, n_hcs; | |
31961943 | 1450 | void __iomem *mmio = host_set->mmio_base; |
20f733e7 BR |
1451 | u32 irq_stat; |
1452 | ||
20f733e7 | 1453 | irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS); |
20f733e7 BR |
1454 | |
1455 | /* check the cases where we either have nothing pending or have read | |
1456 | * a bogus register value which can indicate HW removal or PCI fault | |
1457 | */ | |
1458 | if (!irq_stat || (0xffffffffU == irq_stat)) { | |
1459 | return IRQ_NONE; | |
1460 | } | |
1461 | ||
31961943 | 1462 | n_hcs = mv_get_hc_count(host_set->ports[0]->flags); |
20f733e7 BR |
1463 | spin_lock(&host_set->lock); |
1464 | ||
1465 | for (hc = 0; hc < n_hcs; hc++) { | |
1466 | u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); | |
1467 | if (relevant) { | |
1468 | mv_host_intr(host_set, relevant, hc); | |
31961943 | 1469 | handled++; |
20f733e7 BR |
1470 | } |
1471 | } | |
1472 | if (PCI_ERR & irq_stat) { | |
31961943 BR |
1473 | printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n", |
1474 | readl(mmio + PCI_IRQ_CAUSE_OFS)); | |
1475 | ||
afb0edd9 | 1476 | DPRINTK("All regs @ PCI error\n"); |
31961943 | 1477 | mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev)); |
20f733e7 | 1478 | |
31961943 BR |
1479 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); |
1480 | handled++; | |
1481 | } | |
20f733e7 BR |
1482 | spin_unlock(&host_set->lock); |
1483 | ||
1484 | return IRQ_RETVAL(handled); | |
1485 | } | |
1486 | ||
c9d39130 JG |
1487 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
1488 | { | |
1489 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); | |
1490 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; | |
1491 | ||
1492 | return hc_mmio + ofs; | |
1493 | } | |
1494 | ||
1495 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) | |
1496 | { | |
1497 | unsigned int ofs; | |
1498 | ||
1499 | switch (sc_reg_in) { | |
1500 | case SCR_STATUS: | |
1501 | case SCR_ERROR: | |
1502 | case SCR_CONTROL: | |
1503 | ofs = sc_reg_in * sizeof(u32); | |
1504 | break; | |
1505 | default: | |
1506 | ofs = 0xffffffffU; | |
1507 | break; | |
1508 | } | |
1509 | return ofs; | |
1510 | } | |
1511 | ||
1512 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | |
1513 | { | |
1514 | void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); | |
1515 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | |
1516 | ||
1517 | if (ofs != 0xffffffffU) | |
1518 | return readl(mmio + ofs); | |
1519 | else | |
1520 | return (u32) ofs; | |
1521 | } | |
1522 | ||
1523 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | |
1524 | { | |
1525 | void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); | |
1526 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | |
1527 | ||
1528 | if (ofs != 0xffffffffU) | |
1529 | writelfl(val, mmio + ofs); | |
1530 | } | |
1531 | ||
522479fb JG |
1532 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) |
1533 | { | |
1534 | u8 rev_id; | |
1535 | int early_5080; | |
1536 | ||
1537 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
1538 | ||
1539 | early_5080 = (pdev->device == 0x5080) && (rev_id == 0); | |
1540 | ||
1541 | if (!early_5080) { | |
1542 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
1543 | tmp |= (1 << 0); | |
1544 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
1545 | } | |
1546 | ||
1547 | mv_reset_pci_bus(pdev, mmio); | |
1548 | } | |
1549 | ||
1550 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
1551 | { | |
1552 | writel(0x0fcfffff, mmio + MV_FLASH_CTL); | |
1553 | } | |
1554 | ||
47c2b677 | 1555 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
1556 | void __iomem *mmio) |
1557 | { | |
c9d39130 JG |
1558 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
1559 | u32 tmp; | |
1560 | ||
1561 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
1562 | ||
1563 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ | |
1564 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ | |
ba3fe8fb JG |
1565 | } |
1566 | ||
47c2b677 | 1567 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 1568 | { |
522479fb JG |
1569 | u32 tmp; |
1570 | ||
1571 | writel(0, mmio + MV_GPIO_PORT_CTL); | |
1572 | ||
1573 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ | |
1574 | ||
1575 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
1576 | tmp |= ~(1 << 0); | |
1577 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
ba3fe8fb JG |
1578 | } |
1579 | ||
2a47ce06 JG |
1580 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
1581 | unsigned int port) | |
bca1c4eb | 1582 | { |
c9d39130 JG |
1583 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
1584 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); | |
1585 | u32 tmp; | |
1586 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); | |
1587 | ||
1588 | if (fix_apm_sq) { | |
1589 | tmp = readl(phy_mmio + MV5_LT_MODE); | |
1590 | tmp |= (1 << 19); | |
1591 | writel(tmp, phy_mmio + MV5_LT_MODE); | |
1592 | ||
1593 | tmp = readl(phy_mmio + MV5_PHY_CTL); | |
1594 | tmp &= ~0x3; | |
1595 | tmp |= 0x1; | |
1596 | writel(tmp, phy_mmio + MV5_PHY_CTL); | |
1597 | } | |
1598 | ||
1599 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
1600 | tmp &= ~mask; | |
1601 | tmp |= hpriv->signal[port].pre; | |
1602 | tmp |= hpriv->signal[port].amps; | |
1603 | writel(tmp, phy_mmio + MV5_PHY_MODE); | |
bca1c4eb JG |
1604 | } |
1605 | ||
c9d39130 JG |
1606 | |
1607 | #undef ZERO | |
1608 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
1609 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, | |
1610 | unsigned int port) | |
1611 | { | |
1612 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
1613 | ||
1614 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); | |
1615 | ||
1616 | mv_channel_reset(hpriv, mmio, port); | |
1617 | ||
1618 | ZERO(0x028); /* command */ | |
1619 | writel(0x11f, port_mmio + EDMA_CFG_OFS); | |
1620 | ZERO(0x004); /* timer */ | |
1621 | ZERO(0x008); /* irq err cause */ | |
1622 | ZERO(0x00c); /* irq err mask */ | |
1623 | ZERO(0x010); /* rq bah */ | |
1624 | ZERO(0x014); /* rq inp */ | |
1625 | ZERO(0x018); /* rq outp */ | |
1626 | ZERO(0x01c); /* respq bah */ | |
1627 | ZERO(0x024); /* respq outp */ | |
1628 | ZERO(0x020); /* respq inp */ | |
1629 | ZERO(0x02c); /* test control */ | |
1630 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); | |
1631 | } | |
1632 | #undef ZERO | |
1633 | ||
1634 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
1635 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
1636 | unsigned int hc) | |
47c2b677 | 1637 | { |
c9d39130 JG |
1638 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
1639 | u32 tmp; | |
1640 | ||
1641 | ZERO(0x00c); | |
1642 | ZERO(0x010); | |
1643 | ZERO(0x014); | |
1644 | ZERO(0x018); | |
1645 | ||
1646 | tmp = readl(hc_mmio + 0x20); | |
1647 | tmp &= 0x1c1c1c1c; | |
1648 | tmp |= 0x03030303; | |
1649 | writel(tmp, hc_mmio + 0x20); | |
1650 | } | |
1651 | #undef ZERO | |
1652 | ||
1653 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
1654 | unsigned int n_hc) | |
1655 | { | |
1656 | unsigned int hc, port; | |
1657 | ||
1658 | for (hc = 0; hc < n_hc; hc++) { | |
1659 | for (port = 0; port < MV_PORTS_PER_HC; port++) | |
1660 | mv5_reset_hc_port(hpriv, mmio, | |
1661 | (hc * MV_PORTS_PER_HC) + port); | |
1662 | ||
1663 | mv5_reset_one_hc(hpriv, mmio, hc); | |
1664 | } | |
1665 | ||
1666 | return 0; | |
47c2b677 JG |
1667 | } |
1668 | ||
101ffae2 JG |
1669 | #undef ZERO |
1670 | #define ZERO(reg) writel(0, mmio + (reg)) | |
1671 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) | |
1672 | { | |
1673 | u32 tmp; | |
1674 | ||
1675 | tmp = readl(mmio + MV_PCI_MODE); | |
1676 | tmp &= 0xff00ffff; | |
1677 | writel(tmp, mmio + MV_PCI_MODE); | |
1678 | ||
1679 | ZERO(MV_PCI_DISC_TIMER); | |
1680 | ZERO(MV_PCI_MSI_TRIGGER); | |
1681 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); | |
1682 | ZERO(HC_MAIN_IRQ_MASK_OFS); | |
1683 | ZERO(MV_PCI_SERR_MASK); | |
1684 | ZERO(PCI_IRQ_CAUSE_OFS); | |
1685 | ZERO(PCI_IRQ_MASK_OFS); | |
1686 | ZERO(MV_PCI_ERR_LOW_ADDRESS); | |
1687 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); | |
1688 | ZERO(MV_PCI_ERR_ATTRIBUTE); | |
1689 | ZERO(MV_PCI_ERR_COMMAND); | |
1690 | } | |
1691 | #undef ZERO | |
1692 | ||
1693 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
1694 | { | |
1695 | u32 tmp; | |
1696 | ||
1697 | mv5_reset_flash(hpriv, mmio); | |
1698 | ||
1699 | tmp = readl(mmio + MV_GPIO_PORT_CTL); | |
1700 | tmp &= 0x3; | |
1701 | tmp |= (1 << 5) | (1 << 6); | |
1702 | writel(tmp, mmio + MV_GPIO_PORT_CTL); | |
1703 | } | |
1704 | ||
1705 | /** | |
1706 | * mv6_reset_hc - Perform the 6xxx global soft reset | |
1707 | * @mmio: base address of the HBA | |
1708 | * | |
1709 | * This routine only applies to 6xxx parts. | |
1710 | * | |
1711 | * LOCKING: | |
1712 | * Inherited from caller. | |
1713 | */ | |
c9d39130 JG |
1714 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
1715 | unsigned int n_hc) | |
101ffae2 JG |
1716 | { |
1717 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; | |
1718 | int i, rc = 0; | |
1719 | u32 t; | |
1720 | ||
1721 | /* Following procedure defined in PCI "main command and status | |
1722 | * register" table. | |
1723 | */ | |
1724 | t = readl(reg); | |
1725 | writel(t | STOP_PCI_MASTER, reg); | |
1726 | ||
1727 | for (i = 0; i < 1000; i++) { | |
1728 | udelay(1); | |
1729 | t = readl(reg); | |
1730 | if (PCI_MASTER_EMPTY & t) { | |
1731 | break; | |
1732 | } | |
1733 | } | |
1734 | if (!(PCI_MASTER_EMPTY & t)) { | |
1735 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); | |
1736 | rc = 1; | |
1737 | goto done; | |
1738 | } | |
1739 | ||
1740 | /* set reset */ | |
1741 | i = 5; | |
1742 | do { | |
1743 | writel(t | GLOB_SFT_RST, reg); | |
1744 | t = readl(reg); | |
1745 | udelay(1); | |
1746 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); | |
1747 | ||
1748 | if (!(GLOB_SFT_RST & t)) { | |
1749 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); | |
1750 | rc = 1; | |
1751 | goto done; | |
1752 | } | |
1753 | ||
1754 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ | |
1755 | i = 5; | |
1756 | do { | |
1757 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); | |
1758 | t = readl(reg); | |
1759 | udelay(1); | |
1760 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); | |
1761 | ||
1762 | if (GLOB_SFT_RST & t) { | |
1763 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); | |
1764 | rc = 1; | |
1765 | } | |
1766 | done: | |
1767 | return rc; | |
1768 | } | |
1769 | ||
47c2b677 | 1770 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
1771 | void __iomem *mmio) |
1772 | { | |
1773 | void __iomem *port_mmio; | |
1774 | u32 tmp; | |
1775 | ||
ba3fe8fb JG |
1776 | tmp = readl(mmio + MV_RESET_CFG); |
1777 | if ((tmp & (1 << 0)) == 0) { | |
47c2b677 | 1778 | hpriv->signal[idx].amps = 0x7 << 8; |
ba3fe8fb JG |
1779 | hpriv->signal[idx].pre = 0x1 << 5; |
1780 | return; | |
1781 | } | |
1782 | ||
1783 | port_mmio = mv_port_base(mmio, idx); | |
1784 | tmp = readl(port_mmio + PHY_MODE2); | |
1785 | ||
1786 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
1787 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
1788 | } | |
1789 | ||
47c2b677 | 1790 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 1791 | { |
47c2b677 | 1792 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); |
ba3fe8fb JG |
1793 | } |
1794 | ||
c9d39130 | 1795 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
2a47ce06 | 1796 | unsigned int port) |
bca1c4eb | 1797 | { |
c9d39130 JG |
1798 | void __iomem *port_mmio = mv_port_base(mmio, port); |
1799 | ||
bca1c4eb | 1800 | u32 hp_flags = hpriv->hp_flags; |
47c2b677 JG |
1801 | int fix_phy_mode2 = |
1802 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); | |
bca1c4eb | 1803 | int fix_phy_mode4 = |
47c2b677 JG |
1804 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
1805 | u32 m2, tmp; | |
1806 | ||
1807 | if (fix_phy_mode2) { | |
1808 | m2 = readl(port_mmio + PHY_MODE2); | |
1809 | m2 &= ~(1 << 16); | |
1810 | m2 |= (1 << 31); | |
1811 | writel(m2, port_mmio + PHY_MODE2); | |
1812 | ||
1813 | udelay(200); | |
1814 | ||
1815 | m2 = readl(port_mmio + PHY_MODE2); | |
1816 | m2 &= ~((1 << 16) | (1 << 31)); | |
1817 | writel(m2, port_mmio + PHY_MODE2); | |
1818 | ||
1819 | udelay(200); | |
1820 | } | |
1821 | ||
1822 | /* who knows what this magic does */ | |
1823 | tmp = readl(port_mmio + PHY_MODE3); | |
1824 | tmp &= ~0x7F800000; | |
1825 | tmp |= 0x2A800000; | |
1826 | writel(tmp, port_mmio + PHY_MODE3); | |
bca1c4eb JG |
1827 | |
1828 | if (fix_phy_mode4) { | |
47c2b677 | 1829 | u32 m4; |
bca1c4eb JG |
1830 | |
1831 | m4 = readl(port_mmio + PHY_MODE4); | |
47c2b677 JG |
1832 | |
1833 | if (hp_flags & MV_HP_ERRATA_60X1B2) | |
1834 | tmp = readl(port_mmio + 0x310); | |
bca1c4eb JG |
1835 | |
1836 | m4 = (m4 & ~(1 << 1)) | (1 << 0); | |
1837 | ||
1838 | writel(m4, port_mmio + PHY_MODE4); | |
47c2b677 JG |
1839 | |
1840 | if (hp_flags & MV_HP_ERRATA_60X1B2) | |
1841 | writel(tmp, port_mmio + 0x310); | |
bca1c4eb JG |
1842 | } |
1843 | ||
1844 | /* Revert values of pre-emphasis and signal amps to the saved ones */ | |
1845 | m2 = readl(port_mmio + PHY_MODE2); | |
1846 | ||
1847 | m2 &= ~MV_M2_PREAMP_MASK; | |
2a47ce06 JG |
1848 | m2 |= hpriv->signal[port].amps; |
1849 | m2 |= hpriv->signal[port].pre; | |
47c2b677 | 1850 | m2 &= ~(1 << 16); |
bca1c4eb | 1851 | |
e4e7b892 JG |
1852 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
1853 | if (IS_GEN_IIE(hpriv)) { | |
1854 | m2 &= ~0xC30FF01F; | |
1855 | m2 |= 0x0000900F; | |
1856 | } | |
1857 | ||
bca1c4eb JG |
1858 | writel(m2, port_mmio + PHY_MODE2); |
1859 | } | |
1860 | ||
c9d39130 JG |
1861 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
1862 | unsigned int port_no) | |
1863 | { | |
1864 | void __iomem *port_mmio = mv_port_base(mmio, port_no); | |
1865 | ||
1866 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); | |
1867 | ||
1868 | if (IS_60XX(hpriv)) { | |
1869 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); | |
1870 | ifctl |= (1 << 12) | (1 << 7); | |
1871 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); | |
1872 | } | |
1873 | ||
1874 | udelay(25); /* allow reset propagation */ | |
1875 | ||
1876 | /* Spec never mentions clearing the bit. Marvell's driver does | |
1877 | * clear the bit, however. | |
1878 | */ | |
1879 | writelfl(0, port_mmio + EDMA_CMD_OFS); | |
1880 | ||
1881 | hpriv->ops->phy_errata(hpriv, mmio, port_no); | |
1882 | ||
1883 | if (IS_50XX(hpriv)) | |
1884 | mdelay(1); | |
1885 | } | |
1886 | ||
1887 | static void mv_stop_and_reset(struct ata_port *ap) | |
1888 | { | |
1889 | struct mv_host_priv *hpriv = ap->host_set->private_data; | |
1890 | void __iomem *mmio = ap->host_set->mmio_base; | |
1891 | ||
1892 | mv_stop_dma(ap); | |
1893 | ||
1894 | mv_channel_reset(hpriv, mmio, ap->port_no); | |
1895 | ||
22374677 JG |
1896 | __mv_phy_reset(ap, 0); |
1897 | } | |
1898 | ||
1899 | static inline void __msleep(unsigned int msec, int can_sleep) | |
1900 | { | |
1901 | if (can_sleep) | |
1902 | msleep(msec); | |
1903 | else | |
1904 | mdelay(msec); | |
c9d39130 JG |
1905 | } |
1906 | ||
05b308e1 | 1907 | /** |
22374677 | 1908 | * __mv_phy_reset - Perform eDMA reset followed by COMRESET |
05b308e1 BR |
1909 | * @ap: ATA channel to manipulate |
1910 | * | |
1911 | * Part of this is taken from __sata_phy_reset and modified to | |
1912 | * not sleep since this routine gets called from interrupt level. | |
1913 | * | |
1914 | * LOCKING: | |
1915 | * Inherited from caller. This is coded to safe to call at | |
1916 | * interrupt level, i.e. it does not sleep. | |
31961943 | 1917 | */ |
22374677 | 1918 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep) |
20f733e7 | 1919 | { |
095fec88 | 1920 | struct mv_port_priv *pp = ap->private_data; |
22374677 | 1921 | struct mv_host_priv *hpriv = ap->host_set->private_data; |
20f733e7 BR |
1922 | void __iomem *port_mmio = mv_ap_base(ap); |
1923 | struct ata_taskfile tf; | |
1924 | struct ata_device *dev = &ap->device[0]; | |
31961943 | 1925 | unsigned long timeout; |
22374677 JG |
1926 | int retry = 5; |
1927 | u32 sstatus; | |
20f733e7 BR |
1928 | |
1929 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); | |
1930 | ||
095fec88 | 1931 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " |
31961943 BR |
1932 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1933 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | |
20f733e7 | 1934 | |
22374677 JG |
1935 | /* Issue COMRESET via SControl */ |
1936 | comreset_retry: | |
31961943 | 1937 | scr_write_flush(ap, SCR_CONTROL, 0x301); |
22374677 JG |
1938 | __msleep(1, can_sleep); |
1939 | ||
31961943 | 1940 | scr_write_flush(ap, SCR_CONTROL, 0x300); |
22374677 JG |
1941 | __msleep(20, can_sleep); |
1942 | ||
1943 | timeout = jiffies + msecs_to_jiffies(200); | |
31961943 | 1944 | do { |
22374677 JG |
1945 | sstatus = scr_read(ap, SCR_STATUS) & 0x3; |
1946 | if ((sstatus == 3) || (sstatus == 0)) | |
31961943 | 1947 | break; |
22374677 JG |
1948 | |
1949 | __msleep(1, can_sleep); | |
31961943 | 1950 | } while (time_before(jiffies, timeout)); |
20f733e7 | 1951 | |
22374677 JG |
1952 | /* work around errata */ |
1953 | if (IS_60XX(hpriv) && | |
1954 | (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && | |
1955 | (retry-- > 0)) | |
1956 | goto comreset_retry; | |
095fec88 JG |
1957 | |
1958 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | |
31961943 BR |
1959 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1960 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | |
1961 | ||
1962 | if (sata_dev_present(ap)) { | |
1963 | ata_port_probe(ap); | |
1964 | } else { | |
1965 | printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n", | |
1966 | ap->id, scr_read(ap, SCR_STATUS)); | |
1967 | ata_port_disable(ap); | |
20f733e7 BR |
1968 | return; |
1969 | } | |
31961943 | 1970 | ap->cbl = ATA_CBL_SATA; |
20f733e7 | 1971 | |
22374677 JG |
1972 | /* even after SStatus reflects that device is ready, |
1973 | * it seems to take a while for link to be fully | |
1974 | * established (and thus Status no longer 0x80/0x7F), | |
1975 | * so we poll a bit for that, here. | |
1976 | */ | |
1977 | retry = 20; | |
1978 | while (1) { | |
1979 | u8 drv_stat = ata_check_status(ap); | |
1980 | if ((drv_stat != 0x80) && (drv_stat != 0x7f)) | |
1981 | break; | |
1982 | __msleep(500, can_sleep); | |
1983 | if (retry-- <= 0) | |
1984 | break; | |
1985 | } | |
1986 | ||
20f733e7 BR |
1987 | tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); |
1988 | tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); | |
1989 | tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); | |
1990 | tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr); | |
1991 | ||
1992 | dev->class = ata_dev_classify(&tf); | |
1993 | if (!ata_dev_present(dev)) { | |
1994 | VPRINTK("Port disabled post-sig: No device present.\n"); | |
1995 | ata_port_disable(ap); | |
1996 | } | |
095fec88 JG |
1997 | |
1998 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1999 | ||
2000 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
2001 | ||
bca1c4eb | 2002 | VPRINTK("EXIT\n"); |
20f733e7 BR |
2003 | } |
2004 | ||
22374677 JG |
2005 | static void mv_phy_reset(struct ata_port *ap) |
2006 | { | |
2007 | __mv_phy_reset(ap, 1); | |
2008 | } | |
2009 | ||
05b308e1 BR |
2010 | /** |
2011 | * mv_eng_timeout - Routine called by libata when SCSI times out I/O | |
2012 | * @ap: ATA channel to manipulate | |
2013 | * | |
2014 | * Intent is to clear all pending error conditions, reset the | |
2015 | * chip/bus, fail the command, and move on. | |
2016 | * | |
2017 | * LOCKING: | |
2018 | * This routine holds the host_set lock while failing the command. | |
2019 | */ | |
31961943 BR |
2020 | static void mv_eng_timeout(struct ata_port *ap) |
2021 | { | |
2022 | struct ata_queued_cmd *qc; | |
31961943 BR |
2023 | |
2024 | printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id); | |
2025 | DPRINTK("All regs @ start of eng_timeout\n"); | |
8b260248 | 2026 | mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, |
31961943 BR |
2027 | to_pci_dev(ap->host_set->dev)); |
2028 | ||
2029 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
2030 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", | |
8b260248 | 2031 | ap->host_set->mmio_base, ap, qc, qc->scsicmd, |
31961943 BR |
2032 | &qc->scsicmd->cmnd); |
2033 | ||
2034 | mv_err_intr(ap); | |
c9d39130 | 2035 | mv_stop_and_reset(ap); |
31961943 | 2036 | |
f6379020 TH |
2037 | qc->err_mask |= AC_ERR_TIMEOUT; |
2038 | ata_eh_qc_complete(qc); | |
31961943 BR |
2039 | } |
2040 | ||
05b308e1 BR |
2041 | /** |
2042 | * mv_port_init - Perform some early initialization on a single port. | |
2043 | * @port: libata data structure storing shadow register addresses | |
2044 | * @port_mmio: base address of the port | |
2045 | * | |
2046 | * Initialize shadow register mmio addresses, clear outstanding | |
2047 | * interrupts on the port, and unmask interrupts for the future | |
2048 | * start of the port. | |
2049 | * | |
2050 | * LOCKING: | |
2051 | * Inherited from caller. | |
2052 | */ | |
31961943 | 2053 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
20f733e7 | 2054 | { |
31961943 BR |
2055 | unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; |
2056 | unsigned serr_ofs; | |
2057 | ||
8b260248 | 2058 | /* PIO related setup |
31961943 BR |
2059 | */ |
2060 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); | |
8b260248 | 2061 | port->error_addr = |
31961943 BR |
2062 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
2063 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); | |
2064 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); | |
2065 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); | |
2066 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); | |
2067 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); | |
8b260248 | 2068 | port->status_addr = |
31961943 BR |
2069 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
2070 | /* special case: control/altstatus doesn't have ATA_REG_ address */ | |
2071 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; | |
2072 | ||
2073 | /* unused: */ | |
20f733e7 BR |
2074 | port->cmd_addr = port->bmdma_addr = port->scr_addr = 0; |
2075 | ||
31961943 BR |
2076 | /* Clear any currently outstanding port interrupt conditions */ |
2077 | serr_ofs = mv_scr_offset(SCR_ERROR); | |
2078 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); | |
2079 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
2080 | ||
20f733e7 | 2081 | /* unmask all EDMA error interrupts */ |
31961943 | 2082 | writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); |
20f733e7 | 2083 | |
8b260248 | 2084 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
31961943 BR |
2085 | readl(port_mmio + EDMA_CFG_OFS), |
2086 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), | |
2087 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); | |
20f733e7 BR |
2088 | } |
2089 | ||
47c2b677 | 2090 | static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv, |
522479fb | 2091 | unsigned int board_idx) |
bca1c4eb JG |
2092 | { |
2093 | u8 rev_id; | |
2094 | u32 hp_flags = hpriv->hp_flags; | |
2095 | ||
2096 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
2097 | ||
2098 | switch(board_idx) { | |
47c2b677 JG |
2099 | case chip_5080: |
2100 | hpriv->ops = &mv5xxx_ops; | |
2101 | hp_flags |= MV_HP_50XX; | |
2102 | ||
2103 | switch (rev_id) { | |
2104 | case 0x1: | |
2105 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
2106 | break; | |
2107 | case 0x3: | |
2108 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2109 | break; | |
2110 | default: | |
2111 | dev_printk(KERN_WARNING, &pdev->dev, | |
2112 | "Applying 50XXB2 workarounds to unknown rev\n"); | |
2113 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2114 | break; | |
2115 | } | |
2116 | break; | |
2117 | ||
bca1c4eb JG |
2118 | case chip_504x: |
2119 | case chip_508x: | |
47c2b677 | 2120 | hpriv->ops = &mv5xxx_ops; |
bca1c4eb JG |
2121 | hp_flags |= MV_HP_50XX; |
2122 | ||
47c2b677 JG |
2123 | switch (rev_id) { |
2124 | case 0x0: | |
2125 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
2126 | break; | |
2127 | case 0x3: | |
2128 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2129 | break; | |
2130 | default: | |
2131 | dev_printk(KERN_WARNING, &pdev->dev, | |
2132 | "Applying B2 workarounds to unknown rev\n"); | |
2133 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2134 | break; | |
bca1c4eb JG |
2135 | } |
2136 | break; | |
2137 | ||
2138 | case chip_604x: | |
2139 | case chip_608x: | |
47c2b677 JG |
2140 | hpriv->ops = &mv6xxx_ops; |
2141 | ||
bca1c4eb | 2142 | switch (rev_id) { |
47c2b677 JG |
2143 | case 0x7: |
2144 | hp_flags |= MV_HP_ERRATA_60X1B2; | |
2145 | break; | |
2146 | case 0x9: | |
2147 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
bca1c4eb JG |
2148 | break; |
2149 | default: | |
2150 | dev_printk(KERN_WARNING, &pdev->dev, | |
47c2b677 JG |
2151 | "Applying B2 workarounds to unknown rev\n"); |
2152 | hp_flags |= MV_HP_ERRATA_60X1B2; | |
bca1c4eb JG |
2153 | break; |
2154 | } | |
2155 | break; | |
2156 | ||
e4e7b892 JG |
2157 | case chip_7042: |
2158 | case chip_6042: | |
2159 | hpriv->ops = &mv6xxx_ops; | |
2160 | ||
2161 | hp_flags |= MV_HP_GEN_IIE; | |
2162 | ||
2163 | switch (rev_id) { | |
2164 | case 0x0: | |
2165 | hp_flags |= MV_HP_ERRATA_XX42A0; | |
2166 | break; | |
2167 | case 0x1: | |
2168 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
2169 | break; | |
2170 | default: | |
2171 | dev_printk(KERN_WARNING, &pdev->dev, | |
2172 | "Applying 60X1C0 workarounds to unknown rev\n"); | |
2173 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
2174 | break; | |
2175 | } | |
2176 | break; | |
2177 | ||
bca1c4eb JG |
2178 | default: |
2179 | printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx); | |
2180 | return 1; | |
2181 | } | |
2182 | ||
2183 | hpriv->hp_flags = hp_flags; | |
2184 | ||
2185 | return 0; | |
2186 | } | |
2187 | ||
05b308e1 | 2188 | /** |
47c2b677 | 2189 | * mv_init_host - Perform some early initialization of the host. |
bca1c4eb | 2190 | * @pdev: host PCI device |
05b308e1 BR |
2191 | * @probe_ent: early data struct representing the host |
2192 | * | |
2193 | * If possible, do an early global reset of the host. Then do | |
2194 | * our port init and clear/unmask all/relevant host interrupts. | |
2195 | * | |
2196 | * LOCKING: | |
2197 | * Inherited from caller. | |
2198 | */ | |
47c2b677 | 2199 | static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, |
bca1c4eb | 2200 | unsigned int board_idx) |
20f733e7 BR |
2201 | { |
2202 | int rc = 0, n_hc, port, hc; | |
2203 | void __iomem *mmio = probe_ent->mmio_base; | |
bca1c4eb JG |
2204 | struct mv_host_priv *hpriv = probe_ent->private_data; |
2205 | ||
47c2b677 JG |
2206 | /* global interrupt mask */ |
2207 | writel(0, mmio + HC_MAIN_IRQ_MASK_OFS); | |
2208 | ||
2209 | rc = mv_chip_id(pdev, hpriv, board_idx); | |
bca1c4eb JG |
2210 | if (rc) |
2211 | goto done; | |
2212 | ||
2213 | n_hc = mv_get_hc_count(probe_ent->host_flags); | |
2214 | probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; | |
2215 | ||
47c2b677 JG |
2216 | for (port = 0; port < probe_ent->n_ports; port++) |
2217 | hpriv->ops->read_preamp(hpriv, port, mmio); | |
20f733e7 | 2218 | |
c9d39130 | 2219 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
47c2b677 | 2220 | if (rc) |
20f733e7 | 2221 | goto done; |
20f733e7 | 2222 | |
522479fb JG |
2223 | hpriv->ops->reset_flash(hpriv, mmio); |
2224 | hpriv->ops->reset_bus(pdev, mmio); | |
47c2b677 | 2225 | hpriv->ops->enable_leds(hpriv, mmio); |
20f733e7 BR |
2226 | |
2227 | for (port = 0; port < probe_ent->n_ports; port++) { | |
2a47ce06 | 2228 | if (IS_60XX(hpriv)) { |
c9d39130 JG |
2229 | void __iomem *port_mmio = mv_port_base(mmio, port); |
2230 | ||
2a47ce06 JG |
2231 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); |
2232 | ifctl |= (1 << 12); | |
2233 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); | |
2234 | } | |
2235 | ||
c9d39130 | 2236 | hpriv->ops->phy_errata(hpriv, mmio, port); |
2a47ce06 JG |
2237 | } |
2238 | ||
2239 | for (port = 0; port < probe_ent->n_ports; port++) { | |
2240 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
31961943 | 2241 | mv_port_init(&probe_ent->port[port], port_mmio); |
20f733e7 BR |
2242 | } |
2243 | ||
2244 | for (hc = 0; hc < n_hc; hc++) { | |
31961943 BR |
2245 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
2246 | ||
2247 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " | |
2248 | "(before clear)=0x%08x\n", hc, | |
2249 | readl(hc_mmio + HC_CFG_OFS), | |
2250 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); | |
2251 | ||
2252 | /* Clear any currently outstanding hc interrupt conditions */ | |
2253 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); | |
20f733e7 BR |
2254 | } |
2255 | ||
31961943 BR |
2256 | /* Clear any currently outstanding host interrupt conditions */ |
2257 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); | |
2258 | ||
2259 | /* and unmask interrupt generation for host regs */ | |
2260 | writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); | |
2261 | writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); | |
20f733e7 BR |
2262 | |
2263 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " | |
8b260248 | 2264 | "PCI int cause/mask=0x%08x/0x%08x\n", |
20f733e7 BR |
2265 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), |
2266 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), | |
2267 | readl(mmio + PCI_IRQ_CAUSE_OFS), | |
2268 | readl(mmio + PCI_IRQ_MASK_OFS)); | |
bca1c4eb | 2269 | |
31961943 | 2270 | done: |
20f733e7 BR |
2271 | return rc; |
2272 | } | |
2273 | ||
05b308e1 BR |
2274 | /** |
2275 | * mv_print_info - Dump key info to kernel log for perusal. | |
2276 | * @probe_ent: early data struct representing the host | |
2277 | * | |
2278 | * FIXME: complete this. | |
2279 | * | |
2280 | * LOCKING: | |
2281 | * Inherited from caller. | |
2282 | */ | |
31961943 BR |
2283 | static void mv_print_info(struct ata_probe_ent *probe_ent) |
2284 | { | |
2285 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
2286 | struct mv_host_priv *hpriv = probe_ent->private_data; | |
2287 | u8 rev_id, scc; | |
2288 | const char *scc_s; | |
2289 | ||
2290 | /* Use this to determine the HW stepping of the chip so we know | |
2291 | * what errata to workaround | |
2292 | */ | |
2293 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
2294 | ||
2295 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); | |
2296 | if (scc == 0) | |
2297 | scc_s = "SCSI"; | |
2298 | else if (scc == 0x01) | |
2299 | scc_s = "RAID"; | |
2300 | else | |
2301 | scc_s = "unknown"; | |
2302 | ||
a9524a76 JG |
2303 | dev_printk(KERN_INFO, &pdev->dev, |
2304 | "%u slots %u ports %s mode IRQ via %s\n", | |
8b260248 | 2305 | (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, |
31961943 BR |
2306 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
2307 | } | |
2308 | ||
05b308e1 BR |
2309 | /** |
2310 | * mv_init_one - handle a positive probe of a Marvell host | |
2311 | * @pdev: PCI device found | |
2312 | * @ent: PCI device ID entry for the matched host | |
2313 | * | |
2314 | * LOCKING: | |
2315 | * Inherited from caller. | |
2316 | */ | |
20f733e7 BR |
2317 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
2318 | { | |
2319 | static int printed_version = 0; | |
2320 | struct ata_probe_ent *probe_ent = NULL; | |
2321 | struct mv_host_priv *hpriv; | |
2322 | unsigned int board_idx = (unsigned int)ent->driver_data; | |
2323 | void __iomem *mmio_base; | |
31961943 | 2324 | int pci_dev_busy = 0, rc; |
20f733e7 | 2325 | |
a9524a76 JG |
2326 | if (!printed_version++) |
2327 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
20f733e7 | 2328 | |
20f733e7 BR |
2329 | rc = pci_enable_device(pdev); |
2330 | if (rc) { | |
2331 | return rc; | |
2332 | } | |
2333 | ||
2334 | rc = pci_request_regions(pdev, DRV_NAME); | |
2335 | if (rc) { | |
2336 | pci_dev_busy = 1; | |
2337 | goto err_out; | |
2338 | } | |
2339 | ||
20f733e7 BR |
2340 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); |
2341 | if (probe_ent == NULL) { | |
2342 | rc = -ENOMEM; | |
2343 | goto err_out_regions; | |
2344 | } | |
2345 | ||
2346 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
2347 | probe_ent->dev = pci_dev_to_dev(pdev); | |
2348 | INIT_LIST_HEAD(&probe_ent->node); | |
2349 | ||
31961943 | 2350 | mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0); |
20f733e7 BR |
2351 | if (mmio_base == NULL) { |
2352 | rc = -ENOMEM; | |
2353 | goto err_out_free_ent; | |
2354 | } | |
2355 | ||
2356 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
2357 | if (!hpriv) { | |
2358 | rc = -ENOMEM; | |
2359 | goto err_out_iounmap; | |
2360 | } | |
2361 | memset(hpriv, 0, sizeof(*hpriv)); | |
2362 | ||
2363 | probe_ent->sht = mv_port_info[board_idx].sht; | |
2364 | probe_ent->host_flags = mv_port_info[board_idx].host_flags; | |
2365 | probe_ent->pio_mask = mv_port_info[board_idx].pio_mask; | |
2366 | probe_ent->udma_mask = mv_port_info[board_idx].udma_mask; | |
2367 | probe_ent->port_ops = mv_port_info[board_idx].port_ops; | |
2368 | ||
2369 | probe_ent->irq = pdev->irq; | |
2370 | probe_ent->irq_flags = SA_SHIRQ; | |
2371 | probe_ent->mmio_base = mmio_base; | |
2372 | probe_ent->private_data = hpriv; | |
2373 | ||
2374 | /* initialize adapter */ | |
47c2b677 | 2375 | rc = mv_init_host(pdev, probe_ent, board_idx); |
20f733e7 BR |
2376 | if (rc) { |
2377 | goto err_out_hpriv; | |
2378 | } | |
20f733e7 | 2379 | |
31961943 | 2380 | /* Enable interrupts */ |
ddef9bb3 | 2381 | if (msi && pci_enable_msi(pdev) == 0) { |
31961943 BR |
2382 | hpriv->hp_flags |= MV_HP_FLAG_MSI; |
2383 | } else { | |
2384 | pci_intx(pdev, 1); | |
20f733e7 BR |
2385 | } |
2386 | ||
31961943 BR |
2387 | mv_dump_pci_cfg(pdev, 0x68); |
2388 | mv_print_info(probe_ent); | |
2389 | ||
2390 | if (ata_device_add(probe_ent) == 0) { | |
2391 | rc = -ENODEV; /* No devices discovered */ | |
2392 | goto err_out_dev_add; | |
2393 | } | |
20f733e7 | 2394 | |
31961943 | 2395 | kfree(probe_ent); |
20f733e7 BR |
2396 | return 0; |
2397 | ||
31961943 BR |
2398 | err_out_dev_add: |
2399 | if (MV_HP_FLAG_MSI & hpriv->hp_flags) { | |
2400 | pci_disable_msi(pdev); | |
2401 | } else { | |
2402 | pci_intx(pdev, 0); | |
2403 | } | |
2404 | err_out_hpriv: | |
20f733e7 | 2405 | kfree(hpriv); |
31961943 BR |
2406 | err_out_iounmap: |
2407 | pci_iounmap(pdev, mmio_base); | |
2408 | err_out_free_ent: | |
20f733e7 | 2409 | kfree(probe_ent); |
31961943 | 2410 | err_out_regions: |
20f733e7 | 2411 | pci_release_regions(pdev); |
31961943 | 2412 | err_out: |
20f733e7 BR |
2413 | if (!pci_dev_busy) { |
2414 | pci_disable_device(pdev); | |
2415 | } | |
2416 | ||
2417 | return rc; | |
2418 | } | |
2419 | ||
2420 | static int __init mv_init(void) | |
2421 | { | |
2422 | return pci_module_init(&mv_pci_driver); | |
2423 | } | |
2424 | ||
2425 | static void __exit mv_exit(void) | |
2426 | { | |
2427 | pci_unregister_driver(&mv_pci_driver); | |
2428 | } | |
2429 | ||
2430 | MODULE_AUTHOR("Brett Russ"); | |
2431 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); | |
2432 | MODULE_LICENSE("GPL"); | |
2433 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); | |
2434 | MODULE_VERSION(DRV_VERSION); | |
2435 | ||
ddef9bb3 JG |
2436 | module_param(msi, int, 0444); |
2437 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); | |
2438 | ||
20f733e7 BR |
2439 | module_init(mv_init); |
2440 | module_exit(mv_exit); |