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20f733e7 BR |
1 | /* |
2 | * sata_mv.c - Marvell SATA support | |
3 | * | |
8b260248 | 4 | * Copyright 2005: EMC Corporation, all rights reserved. |
e2b1be56 | 5 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
20f733e7 BR |
6 | * |
7 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; version 2 of the License. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/pci.h> | |
27 | #include <linux/init.h> | |
28 | #include <linux/blkdev.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/sched.h> | |
32 | #include <linux/dma-mapping.h> | |
a9524a76 | 33 | #include <linux/device.h> |
20f733e7 | 34 | #include <scsi/scsi_host.h> |
193515d5 | 35 | #include <scsi/scsi_cmnd.h> |
20f733e7 BR |
36 | #include <linux/libata.h> |
37 | #include <asm/io.h> | |
38 | ||
39 | #define DRV_NAME "sata_mv" | |
e4e7b892 | 40 | #define DRV_VERSION "0.6" |
20f733e7 BR |
41 | |
42 | enum { | |
43 | /* BAR's are enumerated in terms of pci_resource_start() terms */ | |
44 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ | |
45 | MV_IO_BAR = 2, /* offset 0x18: IO space */ | |
46 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ | |
47 | ||
48 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ | |
49 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ | |
50 | ||
51 | MV_PCI_REG_BASE = 0, | |
52 | MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */ | |
53 | MV_SATAHC0_REG_BASE = 0x20000, | |
522479fb | 54 | MV_FLASH_CTL = 0x1046c, |
bca1c4eb JG |
55 | MV_GPIO_PORT_CTL = 0x104f0, |
56 | MV_RESET_CFG = 0x180d8, | |
20f733e7 BR |
57 | |
58 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
59 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
60 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ | |
61 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, | |
62 | ||
31961943 | 63 | MV_USE_Q_DEPTH = ATA_DEF_QUEUE, |
20f733e7 | 64 | |
31961943 BR |
65 | MV_MAX_Q_DEPTH = 32, |
66 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, | |
67 | ||
68 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB | |
69 | * CRPB needs alignment on a 256B boundary. Size == 256B | |
70 | * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB | |
71 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B | |
72 | */ | |
73 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), | |
74 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), | |
75 | MV_MAX_SG_CT = 176, | |
76 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), | |
77 | MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ), | |
78 | ||
20f733e7 BR |
79 | MV_PORTS_PER_HC = 4, |
80 | /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */ | |
81 | MV_PORT_HC_SHIFT = 2, | |
31961943 | 82 | /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */ |
20f733e7 BR |
83 | MV_PORT_MASK = 3, |
84 | ||
85 | /* Host Flags */ | |
86 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ | |
87 | MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ | |
31961943 | 88 | MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
50630195 JG |
89 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | |
90 | ATA_FLAG_NO_ATAPI), | |
47c2b677 | 91 | MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE, |
20f733e7 | 92 | |
31961943 BR |
93 | CRQB_FLAG_READ = (1 << 0), |
94 | CRQB_TAG_SHIFT = 1, | |
95 | CRQB_CMD_ADDR_SHIFT = 8, | |
96 | CRQB_CMD_CS = (0x2 << 11), | |
97 | CRQB_CMD_LAST = (1 << 15), | |
98 | ||
99 | CRPB_FLAG_STATUS_SHIFT = 8, | |
100 | ||
101 | EPRD_FLAG_END_OF_TBL = (1 << 31), | |
102 | ||
20f733e7 BR |
103 | /* PCI interface registers */ |
104 | ||
31961943 BR |
105 | PCI_COMMAND_OFS = 0xc00, |
106 | ||
20f733e7 BR |
107 | PCI_MAIN_CMD_STS_OFS = 0xd30, |
108 | STOP_PCI_MASTER = (1 << 2), | |
109 | PCI_MASTER_EMPTY = (1 << 3), | |
110 | GLOB_SFT_RST = (1 << 4), | |
111 | ||
522479fb JG |
112 | MV_PCI_MODE = 0xd00, |
113 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, | |
114 | MV_PCI_DISC_TIMER = 0xd04, | |
115 | MV_PCI_MSI_TRIGGER = 0xc38, | |
116 | MV_PCI_SERR_MASK = 0xc28, | |
117 | MV_PCI_XBAR_TMOUT = 0x1d04, | |
118 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, | |
119 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, | |
120 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, | |
121 | MV_PCI_ERR_COMMAND = 0x1d50, | |
122 | ||
123 | PCI_IRQ_CAUSE_OFS = 0x1d58, | |
124 | PCI_IRQ_MASK_OFS = 0x1d5c, | |
20f733e7 BR |
125 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
126 | ||
127 | HC_MAIN_IRQ_CAUSE_OFS = 0x1d60, | |
128 | HC_MAIN_IRQ_MASK_OFS = 0x1d64, | |
129 | PORT0_ERR = (1 << 0), /* shift by port # */ | |
130 | PORT0_DONE = (1 << 1), /* shift by port # */ | |
131 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ | |
132 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ | |
133 | PCI_ERR = (1 << 18), | |
134 | TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */ | |
135 | TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */ | |
136 | PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */ | |
137 | GPIO_INT = (1 << 22), | |
138 | SELF_INT = (1 << 23), | |
139 | TWSI_INT = (1 << 24), | |
140 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ | |
8b260248 | 141 | HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE | |
20f733e7 BR |
142 | PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT | |
143 | HC_MAIN_RSVD), | |
144 | ||
145 | /* SATAHC registers */ | |
146 | HC_CFG_OFS = 0, | |
147 | ||
148 | HC_IRQ_CAUSE_OFS = 0x14, | |
31961943 | 149 | CRPB_DMA_DONE = (1 << 0), /* shift by port # */ |
20f733e7 BR |
150 | HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */ |
151 | DEV_IRQ = (1 << 8), /* shift by port # */ | |
152 | ||
153 | /* Shadow block registers */ | |
31961943 BR |
154 | SHD_BLK_OFS = 0x100, |
155 | SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */ | |
20f733e7 BR |
156 | |
157 | /* SATA registers */ | |
158 | SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */ | |
159 | SATA_ACTIVE_OFS = 0x350, | |
47c2b677 | 160 | PHY_MODE3 = 0x310, |
bca1c4eb JG |
161 | PHY_MODE4 = 0x314, |
162 | PHY_MODE2 = 0x330, | |
c9d39130 JG |
163 | MV5_PHY_MODE = 0x74, |
164 | MV5_LT_MODE = 0x30, | |
165 | MV5_PHY_CTL = 0x0C, | |
bca1c4eb JG |
166 | SATA_INTERFACE_CTL = 0x050, |
167 | ||
168 | MV_M2_PREAMP_MASK = 0x7e0, | |
20f733e7 BR |
169 | |
170 | /* Port registers */ | |
171 | EDMA_CFG_OFS = 0, | |
31961943 BR |
172 | EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */ |
173 | EDMA_CFG_NCQ = (1 << 5), | |
174 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ | |
175 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ | |
176 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ | |
20f733e7 BR |
177 | |
178 | EDMA_ERR_IRQ_CAUSE_OFS = 0x8, | |
179 | EDMA_ERR_IRQ_MASK_OFS = 0xc, | |
180 | EDMA_ERR_D_PAR = (1 << 0), | |
181 | EDMA_ERR_PRD_PAR = (1 << 1), | |
182 | EDMA_ERR_DEV = (1 << 2), | |
183 | EDMA_ERR_DEV_DCON = (1 << 3), | |
184 | EDMA_ERR_DEV_CON = (1 << 4), | |
185 | EDMA_ERR_SERR = (1 << 5), | |
186 | EDMA_ERR_SELF_DIS = (1 << 7), | |
187 | EDMA_ERR_BIST_ASYNC = (1 << 8), | |
188 | EDMA_ERR_CRBQ_PAR = (1 << 9), | |
189 | EDMA_ERR_CRPB_PAR = (1 << 10), | |
190 | EDMA_ERR_INTRL_PAR = (1 << 11), | |
191 | EDMA_ERR_IORDY = (1 << 12), | |
192 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), | |
193 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), | |
194 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), | |
195 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), | |
196 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), | |
197 | EDMA_ERR_TRANS_PROTO = (1 << 31), | |
8b260248 | 198 | EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
20f733e7 BR |
199 | EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR | |
200 | EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR | | |
8b260248 | 201 | EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 | |
20f733e7 | 202 | EDMA_ERR_LNK_DATA_RX | |
8b260248 | 203 | EDMA_ERR_LNK_DATA_TX | |
20f733e7 BR |
204 | EDMA_ERR_TRANS_PROTO), |
205 | ||
31961943 BR |
206 | EDMA_REQ_Q_BASE_HI_OFS = 0x10, |
207 | EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */ | |
31961943 BR |
208 | |
209 | EDMA_REQ_Q_OUT_PTR_OFS = 0x18, | |
210 | EDMA_REQ_Q_PTR_SHIFT = 5, | |
211 | ||
212 | EDMA_RSP_Q_BASE_HI_OFS = 0x1c, | |
213 | EDMA_RSP_Q_IN_PTR_OFS = 0x20, | |
214 | EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */ | |
31961943 BR |
215 | EDMA_RSP_Q_PTR_SHIFT = 3, |
216 | ||
20f733e7 BR |
217 | EDMA_CMD_OFS = 0x28, |
218 | EDMA_EN = (1 << 0), | |
219 | EDMA_DS = (1 << 1), | |
220 | ATA_RST = (1 << 2), | |
221 | ||
c9d39130 | 222 | EDMA_IORDY_TMOUT = 0x34, |
bca1c4eb | 223 | EDMA_ARB_CFG = 0x38, |
bca1c4eb | 224 | |
31961943 BR |
225 | /* Host private flags (hp_flags) */ |
226 | MV_HP_FLAG_MSI = (1 << 0), | |
47c2b677 JG |
227 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
228 | MV_HP_ERRATA_50XXB2 = (1 << 2), | |
229 | MV_HP_ERRATA_60X1B2 = (1 << 3), | |
230 | MV_HP_ERRATA_60X1C0 = (1 << 4), | |
e4e7b892 JG |
231 | MV_HP_ERRATA_XX42A0 = (1 << 5), |
232 | MV_HP_50XX = (1 << 6), | |
233 | MV_HP_GEN_IIE = (1 << 7), | |
20f733e7 | 234 | |
31961943 BR |
235 | /* Port private flags (pp_flags) */ |
236 | MV_PP_FLAG_EDMA_EN = (1 << 0), | |
237 | MV_PP_FLAG_EDMA_DS_ACT = (1 << 1), | |
20f733e7 BR |
238 | }; |
239 | ||
c9d39130 | 240 | #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX) |
bca1c4eb | 241 | #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0) |
e4e7b892 JG |
242 | #define IS_GEN_I(hpriv) IS_50XX(hpriv) |
243 | #define IS_GEN_II(hpriv) IS_60XX(hpriv) | |
244 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) | |
bca1c4eb | 245 | |
095fec88 JG |
246 | enum { |
247 | /* Our DMA boundary is determined by an ePRD being unable to handle | |
248 | * anything larger than 64KB | |
249 | */ | |
250 | MV_DMA_BOUNDARY = 0xffffU, | |
251 | ||
252 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, | |
253 | ||
254 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, | |
255 | }; | |
256 | ||
522479fb JG |
257 | enum chip_type { |
258 | chip_504x, | |
259 | chip_508x, | |
260 | chip_5080, | |
261 | chip_604x, | |
262 | chip_608x, | |
e4e7b892 JG |
263 | chip_6042, |
264 | chip_7042, | |
522479fb JG |
265 | }; |
266 | ||
31961943 BR |
267 | /* Command ReQuest Block: 32B */ |
268 | struct mv_crqb { | |
269 | u32 sg_addr; | |
270 | u32 sg_addr_hi; | |
271 | u16 ctrl_flags; | |
272 | u16 ata_cmd[11]; | |
273 | }; | |
20f733e7 | 274 | |
e4e7b892 JG |
275 | struct mv_crqb_iie { |
276 | u32 addr; | |
277 | u32 addr_hi; | |
278 | u32 flags; | |
279 | u32 len; | |
280 | u32 ata_cmd[4]; | |
281 | }; | |
282 | ||
31961943 BR |
283 | /* Command ResPonse Block: 8B */ |
284 | struct mv_crpb { | |
285 | u16 id; | |
286 | u16 flags; | |
287 | u32 tmstmp; | |
20f733e7 BR |
288 | }; |
289 | ||
31961943 BR |
290 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
291 | struct mv_sg { | |
292 | u32 addr; | |
293 | u32 flags_size; | |
294 | u32 addr_hi; | |
295 | u32 reserved; | |
296 | }; | |
20f733e7 | 297 | |
31961943 BR |
298 | struct mv_port_priv { |
299 | struct mv_crqb *crqb; | |
300 | dma_addr_t crqb_dma; | |
301 | struct mv_crpb *crpb; | |
302 | dma_addr_t crpb_dma; | |
303 | struct mv_sg *sg_tbl; | |
304 | dma_addr_t sg_tbl_dma; | |
305 | ||
306 | unsigned req_producer; /* cp of req_in_ptr */ | |
307 | unsigned rsp_consumer; /* cp of rsp_out_ptr */ | |
308 | u32 pp_flags; | |
309 | }; | |
310 | ||
bca1c4eb JG |
311 | struct mv_port_signal { |
312 | u32 amps; | |
313 | u32 pre; | |
314 | }; | |
315 | ||
47c2b677 JG |
316 | struct mv_host_priv; |
317 | struct mv_hw_ops { | |
2a47ce06 JG |
318 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
319 | unsigned int port); | |
47c2b677 JG |
320 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
321 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, | |
322 | void __iomem *mmio); | |
c9d39130 JG |
323 | int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio, |
324 | unsigned int n_hc); | |
522479fb JG |
325 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
326 | void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio); | |
47c2b677 JG |
327 | }; |
328 | ||
31961943 BR |
329 | struct mv_host_priv { |
330 | u32 hp_flags; | |
bca1c4eb | 331 | struct mv_port_signal signal[8]; |
47c2b677 | 332 | const struct mv_hw_ops *ops; |
20f733e7 BR |
333 | }; |
334 | ||
335 | static void mv_irq_clear(struct ata_port *ap); | |
336 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in); | |
337 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | |
c9d39130 JG |
338 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in); |
339 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val); | |
20f733e7 | 340 | static void mv_phy_reset(struct ata_port *ap); |
22374677 | 341 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep); |
31961943 BR |
342 | static void mv_host_stop(struct ata_host_set *host_set); |
343 | static int mv_port_start(struct ata_port *ap); | |
344 | static void mv_port_stop(struct ata_port *ap); | |
345 | static void mv_qc_prep(struct ata_queued_cmd *qc); | |
e4e7b892 | 346 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc); |
9a3d9eb0 | 347 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
20f733e7 BR |
348 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, |
349 | struct pt_regs *regs); | |
31961943 | 350 | static void mv_eng_timeout(struct ata_port *ap); |
20f733e7 BR |
351 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
352 | ||
2a47ce06 JG |
353 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
354 | unsigned int port); | |
47c2b677 JG |
355 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
356 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, | |
357 | void __iomem *mmio); | |
c9d39130 JG |
358 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
359 | unsigned int n_hc); | |
522479fb JG |
360 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
361 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio); | |
47c2b677 | 362 | |
2a47ce06 JG |
363 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
364 | unsigned int port); | |
47c2b677 JG |
365 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
366 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, | |
367 | void __iomem *mmio); | |
c9d39130 JG |
368 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
369 | unsigned int n_hc); | |
522479fb JG |
370 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
371 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio); | |
c9d39130 JG |
372 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
373 | unsigned int port_no); | |
374 | static void mv_stop_and_reset(struct ata_port *ap); | |
47c2b677 | 375 | |
193515d5 | 376 | static struct scsi_host_template mv_sht = { |
20f733e7 BR |
377 | .module = THIS_MODULE, |
378 | .name = DRV_NAME, | |
379 | .ioctl = ata_scsi_ioctl, | |
380 | .queuecommand = ata_scsi_queuecmd, | |
35daeb8f | 381 | .eh_timed_out = ata_scsi_timed_out, |
20f733e7 | 382 | .eh_strategy_handler = ata_scsi_error, |
31961943 | 383 | .can_queue = MV_USE_Q_DEPTH, |
20f733e7 | 384 | .this_id = ATA_SHT_THIS_ID, |
22374677 | 385 | .sg_tablesize = MV_MAX_SG_CT / 2, |
20f733e7 BR |
386 | .max_sectors = ATA_MAX_SECTORS, |
387 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
388 | .emulated = ATA_SHT_EMULATED, | |
31961943 | 389 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
20f733e7 BR |
390 | .proc_name = DRV_NAME, |
391 | .dma_boundary = MV_DMA_BOUNDARY, | |
392 | .slave_configure = ata_scsi_slave_config, | |
393 | .bios_param = ata_std_bios_param, | |
20f733e7 BR |
394 | }; |
395 | ||
c9d39130 JG |
396 | static const struct ata_port_operations mv5_ops = { |
397 | .port_disable = ata_port_disable, | |
398 | ||
399 | .tf_load = ata_tf_load, | |
400 | .tf_read = ata_tf_read, | |
401 | .check_status = ata_check_status, | |
402 | .exec_command = ata_exec_command, | |
403 | .dev_select = ata_std_dev_select, | |
404 | ||
405 | .phy_reset = mv_phy_reset, | |
406 | ||
407 | .qc_prep = mv_qc_prep, | |
408 | .qc_issue = mv_qc_issue, | |
409 | ||
410 | .eng_timeout = mv_eng_timeout, | |
411 | ||
412 | .irq_handler = mv_interrupt, | |
413 | .irq_clear = mv_irq_clear, | |
414 | ||
415 | .scr_read = mv5_scr_read, | |
416 | .scr_write = mv5_scr_write, | |
417 | ||
418 | .port_start = mv_port_start, | |
419 | .port_stop = mv_port_stop, | |
420 | .host_stop = mv_host_stop, | |
421 | }; | |
422 | ||
423 | static const struct ata_port_operations mv6_ops = { | |
20f733e7 BR |
424 | .port_disable = ata_port_disable, |
425 | ||
426 | .tf_load = ata_tf_load, | |
427 | .tf_read = ata_tf_read, | |
428 | .check_status = ata_check_status, | |
429 | .exec_command = ata_exec_command, | |
430 | .dev_select = ata_std_dev_select, | |
431 | ||
432 | .phy_reset = mv_phy_reset, | |
433 | ||
31961943 BR |
434 | .qc_prep = mv_qc_prep, |
435 | .qc_issue = mv_qc_issue, | |
20f733e7 | 436 | |
31961943 | 437 | .eng_timeout = mv_eng_timeout, |
20f733e7 BR |
438 | |
439 | .irq_handler = mv_interrupt, | |
440 | .irq_clear = mv_irq_clear, | |
441 | ||
442 | .scr_read = mv_scr_read, | |
443 | .scr_write = mv_scr_write, | |
444 | ||
31961943 BR |
445 | .port_start = mv_port_start, |
446 | .port_stop = mv_port_stop, | |
447 | .host_stop = mv_host_stop, | |
20f733e7 BR |
448 | }; |
449 | ||
e4e7b892 JG |
450 | static const struct ata_port_operations mv_iie_ops = { |
451 | .port_disable = ata_port_disable, | |
452 | ||
453 | .tf_load = ata_tf_load, | |
454 | .tf_read = ata_tf_read, | |
455 | .check_status = ata_check_status, | |
456 | .exec_command = ata_exec_command, | |
457 | .dev_select = ata_std_dev_select, | |
458 | ||
459 | .phy_reset = mv_phy_reset, | |
460 | ||
461 | .qc_prep = mv_qc_prep_iie, | |
462 | .qc_issue = mv_qc_issue, | |
463 | ||
464 | .eng_timeout = mv_eng_timeout, | |
465 | ||
466 | .irq_handler = mv_interrupt, | |
467 | .irq_clear = mv_irq_clear, | |
468 | ||
469 | .scr_read = mv_scr_read, | |
470 | .scr_write = mv_scr_write, | |
471 | ||
472 | .port_start = mv_port_start, | |
473 | .port_stop = mv_port_stop, | |
474 | .host_stop = mv_host_stop, | |
475 | }; | |
476 | ||
98ac62de | 477 | static const struct ata_port_info mv_port_info[] = { |
20f733e7 BR |
478 | { /* chip_504x */ |
479 | .sht = &mv_sht, | |
31961943 BR |
480 | .host_flags = MV_COMMON_FLAGS, |
481 | .pio_mask = 0x1f, /* pio0-4 */ | |
c9d39130 JG |
482 | .udma_mask = 0x7f, /* udma0-6 */ |
483 | .port_ops = &mv5_ops, | |
20f733e7 BR |
484 | }, |
485 | { /* chip_508x */ | |
486 | .sht = &mv_sht, | |
31961943 BR |
487 | .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), |
488 | .pio_mask = 0x1f, /* pio0-4 */ | |
c9d39130 JG |
489 | .udma_mask = 0x7f, /* udma0-6 */ |
490 | .port_ops = &mv5_ops, | |
20f733e7 | 491 | }, |
47c2b677 JG |
492 | { /* chip_5080 */ |
493 | .sht = &mv_sht, | |
494 | .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC), | |
495 | .pio_mask = 0x1f, /* pio0-4 */ | |
c9d39130 JG |
496 | .udma_mask = 0x7f, /* udma0-6 */ |
497 | .port_ops = &mv5_ops, | |
47c2b677 | 498 | }, |
20f733e7 BR |
499 | { /* chip_604x */ |
500 | .sht = &mv_sht, | |
31961943 BR |
501 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), |
502 | .pio_mask = 0x1f, /* pio0-4 */ | |
503 | .udma_mask = 0x7f, /* udma0-6 */ | |
c9d39130 | 504 | .port_ops = &mv6_ops, |
20f733e7 BR |
505 | }, |
506 | { /* chip_608x */ | |
507 | .sht = &mv_sht, | |
8b260248 | 508 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | |
31961943 BR |
509 | MV_FLAG_DUAL_HC), |
510 | .pio_mask = 0x1f, /* pio0-4 */ | |
511 | .udma_mask = 0x7f, /* udma0-6 */ | |
c9d39130 | 512 | .port_ops = &mv6_ops, |
20f733e7 | 513 | }, |
e4e7b892 JG |
514 | { /* chip_6042 */ |
515 | .sht = &mv_sht, | |
516 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS), | |
517 | .pio_mask = 0x1f, /* pio0-4 */ | |
518 | .udma_mask = 0x7f, /* udma0-6 */ | |
519 | .port_ops = &mv_iie_ops, | |
520 | }, | |
521 | { /* chip_7042 */ | |
522 | .sht = &mv_sht, | |
523 | .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS | | |
524 | MV_FLAG_DUAL_HC), | |
525 | .pio_mask = 0x1f, /* pio0-4 */ | |
526 | .udma_mask = 0x7f, /* udma0-6 */ | |
527 | .port_ops = &mv_iie_ops, | |
528 | }, | |
20f733e7 BR |
529 | }; |
530 | ||
3b7d697d | 531 | static const struct pci_device_id mv_pci_tbl[] = { |
20f733e7 BR |
532 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x}, |
533 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x}, | |
47c2b677 | 534 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080}, |
20f733e7 BR |
535 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x}, |
536 | ||
537 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x}, | |
538 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x}, | |
e4e7b892 | 539 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6042), 0, 0, chip_6042}, |
20f733e7 BR |
540 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x}, |
541 | {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x}, | |
29179539 JG |
542 | |
543 | {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x}, | |
20f733e7 BR |
544 | {} /* terminate list */ |
545 | }; | |
546 | ||
547 | static struct pci_driver mv_pci_driver = { | |
548 | .name = DRV_NAME, | |
549 | .id_table = mv_pci_tbl, | |
550 | .probe = mv_init_one, | |
551 | .remove = ata_pci_remove_one, | |
552 | }; | |
553 | ||
47c2b677 JG |
554 | static const struct mv_hw_ops mv5xxx_ops = { |
555 | .phy_errata = mv5_phy_errata, | |
556 | .enable_leds = mv5_enable_leds, | |
557 | .read_preamp = mv5_read_preamp, | |
558 | .reset_hc = mv5_reset_hc, | |
522479fb JG |
559 | .reset_flash = mv5_reset_flash, |
560 | .reset_bus = mv5_reset_bus, | |
47c2b677 JG |
561 | }; |
562 | ||
563 | static const struct mv_hw_ops mv6xxx_ops = { | |
564 | .phy_errata = mv6_phy_errata, | |
565 | .enable_leds = mv6_enable_leds, | |
566 | .read_preamp = mv6_read_preamp, | |
567 | .reset_hc = mv6_reset_hc, | |
522479fb JG |
568 | .reset_flash = mv6_reset_flash, |
569 | .reset_bus = mv_reset_pci_bus, | |
47c2b677 JG |
570 | }; |
571 | ||
ddef9bb3 JG |
572 | /* |
573 | * module options | |
574 | */ | |
575 | static int msi; /* Use PCI msi; either zero (off, default) or non-zero */ | |
576 | ||
577 | ||
20f733e7 BR |
578 | /* |
579 | * Functions | |
580 | */ | |
581 | ||
582 | static inline void writelfl(unsigned long data, void __iomem *addr) | |
583 | { | |
584 | writel(data, addr); | |
585 | (void) readl(addr); /* flush to avoid PCI posted write */ | |
586 | } | |
587 | ||
20f733e7 BR |
588 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
589 | { | |
590 | return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); | |
591 | } | |
592 | ||
c9d39130 JG |
593 | static inline unsigned int mv_hc_from_port(unsigned int port) |
594 | { | |
595 | return port >> MV_PORT_HC_SHIFT; | |
596 | } | |
597 | ||
598 | static inline unsigned int mv_hardport_from_port(unsigned int port) | |
599 | { | |
600 | return port & MV_PORT_MASK; | |
601 | } | |
602 | ||
603 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, | |
604 | unsigned int port) | |
605 | { | |
606 | return mv_hc_base(base, mv_hc_from_port(port)); | |
607 | } | |
608 | ||
20f733e7 BR |
609 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
610 | { | |
c9d39130 | 611 | return mv_hc_base_from_port(base, port) + |
8b260248 | 612 | MV_SATAHC_ARBTR_REG_SZ + |
c9d39130 | 613 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
20f733e7 BR |
614 | } |
615 | ||
616 | static inline void __iomem *mv_ap_base(struct ata_port *ap) | |
617 | { | |
618 | return mv_port_base(ap->host_set->mmio_base, ap->port_no); | |
619 | } | |
620 | ||
bca1c4eb | 621 | static inline int mv_get_hc_count(unsigned long host_flags) |
31961943 | 622 | { |
bca1c4eb | 623 | return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
31961943 BR |
624 | } |
625 | ||
626 | static void mv_irq_clear(struct ata_port *ap) | |
20f733e7 | 627 | { |
20f733e7 BR |
628 | } |
629 | ||
05b308e1 BR |
630 | /** |
631 | * mv_start_dma - Enable eDMA engine | |
632 | * @base: port base address | |
633 | * @pp: port private data | |
634 | * | |
635 | * Verify the local cache of the eDMA state is accurate with an | |
636 | * assert. | |
637 | * | |
638 | * LOCKING: | |
639 | * Inherited from caller. | |
640 | */ | |
afb0edd9 | 641 | static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp) |
20f733e7 | 642 | { |
afb0edd9 BR |
643 | if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) { |
644 | writelfl(EDMA_EN, base + EDMA_CMD_OFS); | |
645 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; | |
646 | } | |
647 | assert(EDMA_EN & readl(base + EDMA_CMD_OFS)); | |
20f733e7 BR |
648 | } |
649 | ||
05b308e1 BR |
650 | /** |
651 | * mv_stop_dma - Disable eDMA engine | |
652 | * @ap: ATA channel to manipulate | |
653 | * | |
654 | * Verify the local cache of the eDMA state is accurate with an | |
655 | * assert. | |
656 | * | |
657 | * LOCKING: | |
658 | * Inherited from caller. | |
659 | */ | |
31961943 | 660 | static void mv_stop_dma(struct ata_port *ap) |
20f733e7 | 661 | { |
31961943 BR |
662 | void __iomem *port_mmio = mv_ap_base(ap); |
663 | struct mv_port_priv *pp = ap->private_data; | |
31961943 BR |
664 | u32 reg; |
665 | int i; | |
666 | ||
afb0edd9 BR |
667 | if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) { |
668 | /* Disable EDMA if active. The disable bit auto clears. | |
31961943 | 669 | */ |
31961943 BR |
670 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); |
671 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
afb0edd9 BR |
672 | } else { |
673 | assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS))); | |
674 | } | |
8b260248 | 675 | |
31961943 BR |
676 | /* now properly wait for the eDMA to stop */ |
677 | for (i = 1000; i > 0; i--) { | |
678 | reg = readl(port_mmio + EDMA_CMD_OFS); | |
679 | if (!(EDMA_EN & reg)) { | |
680 | break; | |
681 | } | |
682 | udelay(100); | |
683 | } | |
684 | ||
31961943 BR |
685 | if (EDMA_EN & reg) { |
686 | printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id); | |
afb0edd9 | 687 | /* FIXME: Consider doing a reset here to recover */ |
31961943 | 688 | } |
20f733e7 BR |
689 | } |
690 | ||
8a70f8dc | 691 | #ifdef ATA_DEBUG |
31961943 | 692 | static void mv_dump_mem(void __iomem *start, unsigned bytes) |
20f733e7 | 693 | { |
31961943 BR |
694 | int b, w; |
695 | for (b = 0; b < bytes; ) { | |
696 | DPRINTK("%p: ", start + b); | |
697 | for (w = 0; b < bytes && w < 4; w++) { | |
698 | printk("%08x ",readl(start + b)); | |
699 | b += sizeof(u32); | |
700 | } | |
701 | printk("\n"); | |
702 | } | |
31961943 | 703 | } |
8a70f8dc JG |
704 | #endif |
705 | ||
31961943 BR |
706 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
707 | { | |
708 | #ifdef ATA_DEBUG | |
709 | int b, w; | |
710 | u32 dw; | |
711 | for (b = 0; b < bytes; ) { | |
712 | DPRINTK("%02x: ", b); | |
713 | for (w = 0; b < bytes && w < 4; w++) { | |
714 | (void) pci_read_config_dword(pdev,b,&dw); | |
715 | printk("%08x ",dw); | |
716 | b += sizeof(u32); | |
717 | } | |
718 | printk("\n"); | |
719 | } | |
720 | #endif | |
721 | } | |
722 | static void mv_dump_all_regs(void __iomem *mmio_base, int port, | |
723 | struct pci_dev *pdev) | |
724 | { | |
725 | #ifdef ATA_DEBUG | |
8b260248 | 726 | void __iomem *hc_base = mv_hc_base(mmio_base, |
31961943 BR |
727 | port >> MV_PORT_HC_SHIFT); |
728 | void __iomem *port_base; | |
729 | int start_port, num_ports, p, start_hc, num_hcs, hc; | |
730 | ||
731 | if (0 > port) { | |
732 | start_hc = start_port = 0; | |
733 | num_ports = 8; /* shld be benign for 4 port devs */ | |
734 | num_hcs = 2; | |
735 | } else { | |
736 | start_hc = port >> MV_PORT_HC_SHIFT; | |
737 | start_port = port; | |
738 | num_ports = num_hcs = 1; | |
739 | } | |
8b260248 | 740 | DPRINTK("All registers for port(s) %u-%u:\n", start_port, |
31961943 BR |
741 | num_ports > 1 ? num_ports - 1 : start_port); |
742 | ||
743 | if (NULL != pdev) { | |
744 | DPRINTK("PCI config space regs:\n"); | |
745 | mv_dump_pci_cfg(pdev, 0x68); | |
746 | } | |
747 | DPRINTK("PCI regs:\n"); | |
748 | mv_dump_mem(mmio_base+0xc00, 0x3c); | |
749 | mv_dump_mem(mmio_base+0xd00, 0x34); | |
750 | mv_dump_mem(mmio_base+0xf00, 0x4); | |
751 | mv_dump_mem(mmio_base+0x1d00, 0x6c); | |
752 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { | |
753 | hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT); | |
754 | DPRINTK("HC regs (HC %i):\n", hc); | |
755 | mv_dump_mem(hc_base, 0x1c); | |
756 | } | |
757 | for (p = start_port; p < start_port + num_ports; p++) { | |
758 | port_base = mv_port_base(mmio_base, p); | |
759 | DPRINTK("EDMA regs (port %i):\n",p); | |
760 | mv_dump_mem(port_base, 0x54); | |
761 | DPRINTK("SATA regs (port %i):\n",p); | |
762 | mv_dump_mem(port_base+0x300, 0x60); | |
763 | } | |
764 | #endif | |
20f733e7 BR |
765 | } |
766 | ||
767 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) | |
768 | { | |
769 | unsigned int ofs; | |
770 | ||
771 | switch (sc_reg_in) { | |
772 | case SCR_STATUS: | |
773 | case SCR_CONTROL: | |
774 | case SCR_ERROR: | |
775 | ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32)); | |
776 | break; | |
777 | case SCR_ACTIVE: | |
778 | ofs = SATA_ACTIVE_OFS; /* active is not with the others */ | |
779 | break; | |
780 | default: | |
781 | ofs = 0xffffffffU; | |
782 | break; | |
783 | } | |
784 | return ofs; | |
785 | } | |
786 | ||
787 | static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | |
788 | { | |
789 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
790 | ||
791 | if (0xffffffffU != ofs) { | |
792 | return readl(mv_ap_base(ap) + ofs); | |
793 | } else { | |
794 | return (u32) ofs; | |
795 | } | |
796 | } | |
797 | ||
798 | static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | |
799 | { | |
800 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
801 | ||
802 | if (0xffffffffU != ofs) { | |
803 | writelfl(val, mv_ap_base(ap) + ofs); | |
804 | } | |
805 | } | |
806 | ||
05b308e1 BR |
807 | /** |
808 | * mv_host_stop - Host specific cleanup/stop routine. | |
809 | * @host_set: host data structure | |
810 | * | |
811 | * Disable ints, cleanup host memory, call general purpose | |
812 | * host_stop. | |
813 | * | |
814 | * LOCKING: | |
815 | * Inherited from caller. | |
816 | */ | |
31961943 | 817 | static void mv_host_stop(struct ata_host_set *host_set) |
20f733e7 | 818 | { |
31961943 BR |
819 | struct mv_host_priv *hpriv = host_set->private_data; |
820 | struct pci_dev *pdev = to_pci_dev(host_set->dev); | |
821 | ||
822 | if (hpriv->hp_flags & MV_HP_FLAG_MSI) { | |
823 | pci_disable_msi(pdev); | |
824 | } else { | |
825 | pci_intx(pdev, 0); | |
826 | } | |
827 | kfree(hpriv); | |
828 | ata_host_stop(host_set); | |
829 | } | |
830 | ||
6037d6bb JG |
831 | static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev) |
832 | { | |
833 | dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma); | |
834 | } | |
835 | ||
e4e7b892 JG |
836 | static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio) |
837 | { | |
838 | u32 cfg = readl(port_mmio + EDMA_CFG_OFS); | |
839 | ||
840 | /* set up non-NCQ EDMA configuration */ | |
841 | cfg &= ~0x1f; /* clear queue depth */ | |
842 | cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */ | |
843 | cfg &= ~(1 << 9); /* disable equeue */ | |
844 | ||
845 | if (IS_GEN_I(hpriv)) | |
846 | cfg |= (1 << 8); /* enab config burst size mask */ | |
847 | ||
848 | else if (IS_GEN_II(hpriv)) | |
849 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; | |
850 | ||
851 | else if (IS_GEN_IIE(hpriv)) { | |
852 | cfg |= (1 << 23); /* dis RX PM port mask */ | |
853 | cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */ | |
854 | cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */ | |
855 | cfg |= (1 << 18); /* enab early completion */ | |
856 | cfg |= (1 << 17); /* enab host q cache */ | |
857 | cfg |= (1 << 22); /* enab cutthrough */ | |
858 | } | |
859 | ||
860 | writelfl(cfg, port_mmio + EDMA_CFG_OFS); | |
861 | } | |
862 | ||
05b308e1 BR |
863 | /** |
864 | * mv_port_start - Port specific init/start routine. | |
865 | * @ap: ATA channel to manipulate | |
866 | * | |
867 | * Allocate and point to DMA memory, init port private memory, | |
868 | * zero indices. | |
869 | * | |
870 | * LOCKING: | |
871 | * Inherited from caller. | |
872 | */ | |
31961943 BR |
873 | static int mv_port_start(struct ata_port *ap) |
874 | { | |
875 | struct device *dev = ap->host_set->dev; | |
e4e7b892 | 876 | struct mv_host_priv *hpriv = ap->host_set->private_data; |
31961943 BR |
877 | struct mv_port_priv *pp; |
878 | void __iomem *port_mmio = mv_ap_base(ap); | |
879 | void *mem; | |
880 | dma_addr_t mem_dma; | |
6037d6bb | 881 | int rc = -ENOMEM; |
31961943 BR |
882 | |
883 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
6037d6bb JG |
884 | if (!pp) |
885 | goto err_out; | |
31961943 BR |
886 | memset(pp, 0, sizeof(*pp)); |
887 | ||
8b260248 | 888 | mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma, |
31961943 | 889 | GFP_KERNEL); |
6037d6bb JG |
890 | if (!mem) |
891 | goto err_out_pp; | |
31961943 BR |
892 | memset(mem, 0, MV_PORT_PRIV_DMA_SZ); |
893 | ||
6037d6bb JG |
894 | rc = ata_pad_alloc(ap, dev); |
895 | if (rc) | |
896 | goto err_out_priv; | |
897 | ||
8b260248 | 898 | /* First item in chunk of DMA memory: |
31961943 BR |
899 | * 32-slot command request table (CRQB), 32 bytes each in size |
900 | */ | |
901 | pp->crqb = mem; | |
902 | pp->crqb_dma = mem_dma; | |
903 | mem += MV_CRQB_Q_SZ; | |
904 | mem_dma += MV_CRQB_Q_SZ; | |
905 | ||
8b260248 | 906 | /* Second item: |
31961943 BR |
907 | * 32-slot command response table (CRPB), 8 bytes each in size |
908 | */ | |
909 | pp->crpb = mem; | |
910 | pp->crpb_dma = mem_dma; | |
911 | mem += MV_CRPB_Q_SZ; | |
912 | mem_dma += MV_CRPB_Q_SZ; | |
913 | ||
914 | /* Third item: | |
915 | * Table of scatter-gather descriptors (ePRD), 16 bytes each | |
916 | */ | |
917 | pp->sg_tbl = mem; | |
918 | pp->sg_tbl_dma = mem_dma; | |
919 | ||
e4e7b892 | 920 | mv_edma_cfg(hpriv, port_mmio); |
31961943 BR |
921 | |
922 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); | |
8b260248 | 923 | writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK, |
31961943 BR |
924 | port_mmio + EDMA_REQ_Q_IN_PTR_OFS); |
925 | ||
e4e7b892 JG |
926 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) |
927 | writelfl(pp->crqb_dma & 0xffffffff, | |
928 | port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); | |
929 | else | |
930 | writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); | |
31961943 BR |
931 | |
932 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); | |
e4e7b892 JG |
933 | |
934 | if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) | |
935 | writelfl(pp->crpb_dma & 0xffffffff, | |
936 | port_mmio + EDMA_RSP_Q_IN_PTR_OFS); | |
937 | else | |
938 | writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); | |
939 | ||
8b260248 | 940 | writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK, |
31961943 BR |
941 | port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); |
942 | ||
943 | pp->req_producer = pp->rsp_consumer = 0; | |
944 | ||
945 | /* Don't turn on EDMA here...do it before DMA commands only. Else | |
946 | * we'll be unable to send non-data, PIO, etc due to restricted access | |
947 | * to shadow regs. | |
948 | */ | |
949 | ap->private_data = pp; | |
950 | return 0; | |
6037d6bb JG |
951 | |
952 | err_out_priv: | |
953 | mv_priv_free(pp, dev); | |
954 | err_out_pp: | |
955 | kfree(pp); | |
956 | err_out: | |
957 | return rc; | |
31961943 BR |
958 | } |
959 | ||
05b308e1 BR |
960 | /** |
961 | * mv_port_stop - Port specific cleanup/stop routine. | |
962 | * @ap: ATA channel to manipulate | |
963 | * | |
964 | * Stop DMA, cleanup port memory. | |
965 | * | |
966 | * LOCKING: | |
967 | * This routine uses the host_set lock to protect the DMA stop. | |
968 | */ | |
31961943 BR |
969 | static void mv_port_stop(struct ata_port *ap) |
970 | { | |
971 | struct device *dev = ap->host_set->dev; | |
972 | struct mv_port_priv *pp = ap->private_data; | |
afb0edd9 | 973 | unsigned long flags; |
31961943 | 974 | |
afb0edd9 | 975 | spin_lock_irqsave(&ap->host_set->lock, flags); |
31961943 | 976 | mv_stop_dma(ap); |
afb0edd9 | 977 | spin_unlock_irqrestore(&ap->host_set->lock, flags); |
31961943 BR |
978 | |
979 | ap->private_data = NULL; | |
6037d6bb JG |
980 | ata_pad_free(ap, dev); |
981 | mv_priv_free(pp, dev); | |
31961943 BR |
982 | kfree(pp); |
983 | } | |
984 | ||
05b308e1 BR |
985 | /** |
986 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries | |
987 | * @qc: queued command whose SG list to source from | |
988 | * | |
989 | * Populate the SG list and mark the last entry. | |
990 | * | |
991 | * LOCKING: | |
992 | * Inherited from caller. | |
993 | */ | |
31961943 BR |
994 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
995 | { | |
996 | struct mv_port_priv *pp = qc->ap->private_data; | |
972c26bd JG |
997 | unsigned int i = 0; |
998 | struct scatterlist *sg; | |
31961943 | 999 | |
972c26bd | 1000 | ata_for_each_sg(sg, qc) { |
31961943 | 1001 | dma_addr_t addr; |
22374677 | 1002 | u32 sg_len, len, offset; |
31961943 | 1003 | |
972c26bd JG |
1004 | addr = sg_dma_address(sg); |
1005 | sg_len = sg_dma_len(sg); | |
31961943 | 1006 | |
22374677 JG |
1007 | while (sg_len) { |
1008 | offset = addr & MV_DMA_BOUNDARY; | |
1009 | len = sg_len; | |
1010 | if ((offset + sg_len) > 0x10000) | |
1011 | len = 0x10000 - offset; | |
972c26bd | 1012 | |
22374677 JG |
1013 | pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff); |
1014 | pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
1015 | pp->sg_tbl[i].flags_size = cpu_to_le32(len); | |
1016 | ||
1017 | sg_len -= len; | |
1018 | addr += len; | |
1019 | ||
1020 | if (!sg_len && ata_sg_is_last(sg, qc)) | |
1021 | pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); | |
1022 | ||
1023 | i++; | |
1024 | } | |
31961943 BR |
1025 | } |
1026 | } | |
1027 | ||
1028 | static inline unsigned mv_inc_q_index(unsigned *index) | |
1029 | { | |
1030 | *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK; | |
1031 | return *index; | |
1032 | } | |
1033 | ||
1034 | static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last) | |
1035 | { | |
1036 | *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | | |
1037 | (last ? CRQB_CMD_LAST : 0); | |
1038 | } | |
1039 | ||
05b308e1 BR |
1040 | /** |
1041 | * mv_qc_prep - Host specific command preparation. | |
1042 | * @qc: queued command to prepare | |
1043 | * | |
1044 | * This routine simply redirects to the general purpose routine | |
1045 | * if command is not DMA. Else, it handles prep of the CRQB | |
1046 | * (command request block), does some sanity checking, and calls | |
1047 | * the SG load routine. | |
1048 | * | |
1049 | * LOCKING: | |
1050 | * Inherited from caller. | |
1051 | */ | |
31961943 BR |
1052 | static void mv_qc_prep(struct ata_queued_cmd *qc) |
1053 | { | |
1054 | struct ata_port *ap = qc->ap; | |
1055 | struct mv_port_priv *pp = ap->private_data; | |
1056 | u16 *cw; | |
1057 | struct ata_taskfile *tf; | |
1058 | u16 flags = 0; | |
1059 | ||
e4e7b892 | 1060 | if (ATA_PROT_DMA != qc->tf.protocol) |
31961943 | 1061 | return; |
20f733e7 | 1062 | |
31961943 | 1063 | /* the req producer index should be the same as we remember it */ |
8b260248 | 1064 | assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> |
31961943 BR |
1065 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == |
1066 | pp->req_producer); | |
1067 | ||
1068 | /* Fill in command request block | |
1069 | */ | |
e4e7b892 | 1070 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) |
31961943 | 1071 | flags |= CRQB_FLAG_READ; |
31961943 BR |
1072 | assert(MV_MAX_Q_DEPTH > qc->tag); |
1073 | flags |= qc->tag << CRQB_TAG_SHIFT; | |
1074 | ||
8b260248 | 1075 | pp->crqb[pp->req_producer].sg_addr = |
31961943 | 1076 | cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); |
8b260248 | 1077 | pp->crqb[pp->req_producer].sg_addr_hi = |
31961943 BR |
1078 | cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); |
1079 | pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags); | |
1080 | ||
1081 | cw = &pp->crqb[pp->req_producer].ata_cmd[0]; | |
1082 | tf = &qc->tf; | |
1083 | ||
1084 | /* Sadly, the CRQB cannot accomodate all registers--there are | |
1085 | * only 11 bytes...so we must pick and choose required | |
1086 | * registers based on the command. So, we drop feature and | |
1087 | * hob_feature for [RW] DMA commands, but they are needed for | |
1088 | * NCQ. NCQ will drop hob_nsect. | |
20f733e7 | 1089 | */ |
31961943 BR |
1090 | switch (tf->command) { |
1091 | case ATA_CMD_READ: | |
1092 | case ATA_CMD_READ_EXT: | |
1093 | case ATA_CMD_WRITE: | |
1094 | case ATA_CMD_WRITE_EXT: | |
1095 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); | |
1096 | break; | |
1097 | #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */ | |
1098 | case ATA_CMD_FPDMA_READ: | |
1099 | case ATA_CMD_FPDMA_WRITE: | |
8b260248 | 1100 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
31961943 BR |
1101 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
1102 | break; | |
1103 | #endif /* FIXME: remove this line when NCQ added */ | |
1104 | default: | |
1105 | /* The only other commands EDMA supports in non-queued and | |
1106 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none | |
1107 | * of which are defined/used by Linux. If we get here, this | |
1108 | * driver needs work. | |
1109 | * | |
1110 | * FIXME: modify libata to give qc_prep a return value and | |
1111 | * return error here. | |
1112 | */ | |
1113 | BUG_ON(tf->command); | |
1114 | break; | |
1115 | } | |
1116 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); | |
1117 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); | |
1118 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); | |
1119 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); | |
1120 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); | |
1121 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); | |
1122 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); | |
1123 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); | |
1124 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ | |
1125 | ||
e4e7b892 JG |
1126 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
1127 | return; | |
1128 | mv_fill_sg(qc); | |
1129 | } | |
1130 | ||
1131 | /** | |
1132 | * mv_qc_prep_iie - Host specific command preparation. | |
1133 | * @qc: queued command to prepare | |
1134 | * | |
1135 | * This routine simply redirects to the general purpose routine | |
1136 | * if command is not DMA. Else, it handles prep of the CRQB | |
1137 | * (command request block), does some sanity checking, and calls | |
1138 | * the SG load routine. | |
1139 | * | |
1140 | * LOCKING: | |
1141 | * Inherited from caller. | |
1142 | */ | |
1143 | static void mv_qc_prep_iie(struct ata_queued_cmd *qc) | |
1144 | { | |
1145 | struct ata_port *ap = qc->ap; | |
1146 | struct mv_port_priv *pp = ap->private_data; | |
1147 | struct mv_crqb_iie *crqb; | |
1148 | struct ata_taskfile *tf; | |
1149 | u32 flags = 0; | |
1150 | ||
1151 | if (ATA_PROT_DMA != qc->tf.protocol) | |
1152 | return; | |
1153 | ||
1154 | /* the req producer index should be the same as we remember it */ | |
1155 | assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >> | |
1156 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == | |
1157 | pp->req_producer); | |
1158 | ||
1159 | /* Fill in Gen IIE command request block | |
1160 | */ | |
1161 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
1162 | flags |= CRQB_FLAG_READ; | |
1163 | ||
1164 | assert(MV_MAX_Q_DEPTH > qc->tag); | |
1165 | flags |= qc->tag << CRQB_TAG_SHIFT; | |
1166 | ||
1167 | crqb = (struct mv_crqb_iie *) &pp->crqb[pp->req_producer]; | |
1168 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff); | |
1169 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16); | |
1170 | crqb->flags = cpu_to_le32(flags); | |
1171 | ||
1172 | tf = &qc->tf; | |
1173 | crqb->ata_cmd[0] = cpu_to_le32( | |
1174 | (tf->command << 16) | | |
1175 | (tf->feature << 24) | |
1176 | ); | |
1177 | crqb->ata_cmd[1] = cpu_to_le32( | |
1178 | (tf->lbal << 0) | | |
1179 | (tf->lbam << 8) | | |
1180 | (tf->lbah << 16) | | |
1181 | (tf->device << 24) | |
1182 | ); | |
1183 | crqb->ata_cmd[2] = cpu_to_le32( | |
1184 | (tf->hob_lbal << 0) | | |
1185 | (tf->hob_lbam << 8) | | |
1186 | (tf->hob_lbah << 16) | | |
1187 | (tf->hob_feature << 24) | |
1188 | ); | |
1189 | crqb->ata_cmd[3] = cpu_to_le32( | |
1190 | (tf->nsect << 0) | | |
1191 | (tf->hob_nsect << 8) | |
1192 | ); | |
1193 | ||
1194 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
31961943 | 1195 | return; |
31961943 BR |
1196 | mv_fill_sg(qc); |
1197 | } | |
1198 | ||
05b308e1 BR |
1199 | /** |
1200 | * mv_qc_issue - Initiate a command to the host | |
1201 | * @qc: queued command to start | |
1202 | * | |
1203 | * This routine simply redirects to the general purpose routine | |
1204 | * if command is not DMA. Else, it sanity checks our local | |
1205 | * caches of the request producer/consumer indices then enables | |
1206 | * DMA and bumps the request producer index. | |
1207 | * | |
1208 | * LOCKING: | |
1209 | * Inherited from caller. | |
1210 | */ | |
9a3d9eb0 | 1211 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
31961943 BR |
1212 | { |
1213 | void __iomem *port_mmio = mv_ap_base(qc->ap); | |
1214 | struct mv_port_priv *pp = qc->ap->private_data; | |
1215 | u32 in_ptr; | |
1216 | ||
1217 | if (ATA_PROT_DMA != qc->tf.protocol) { | |
1218 | /* We're about to send a non-EDMA capable command to the | |
1219 | * port. Turn off EDMA so there won't be problems accessing | |
1220 | * shadow block, etc registers. | |
1221 | */ | |
1222 | mv_stop_dma(qc->ap); | |
1223 | return ata_qc_issue_prot(qc); | |
1224 | } | |
1225 | ||
1226 | in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | |
1227 | ||
1228 | /* the req producer index should be the same as we remember it */ | |
1229 | assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == | |
1230 | pp->req_producer); | |
1231 | /* until we do queuing, the queue should be empty at this point */ | |
1232 | assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == | |
8b260248 | 1233 | ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >> |
31961943 BR |
1234 | EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK)); |
1235 | ||
1236 | mv_inc_q_index(&pp->req_producer); /* now incr producer index */ | |
1237 | ||
afb0edd9 | 1238 | mv_start_dma(port_mmio, pp); |
31961943 BR |
1239 | |
1240 | /* and write the request in pointer to kick the EDMA to life */ | |
1241 | in_ptr &= EDMA_REQ_Q_BASE_LO_MASK; | |
1242 | in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT; | |
1243 | writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | ||
05b308e1 BR |
1248 | /** |
1249 | * mv_get_crpb_status - get status from most recently completed cmd | |
1250 | * @ap: ATA channel to manipulate | |
1251 | * | |
1252 | * This routine is for use when the port is in DMA mode, when it | |
1253 | * will be using the CRPB (command response block) method of | |
1254 | * returning command completion information. We assert indices | |
1255 | * are good, grab status, and bump the response consumer index to | |
1256 | * prove that we're up to date. | |
1257 | * | |
1258 | * LOCKING: | |
1259 | * Inherited from caller. | |
1260 | */ | |
31961943 BR |
1261 | static u8 mv_get_crpb_status(struct ata_port *ap) |
1262 | { | |
1263 | void __iomem *port_mmio = mv_ap_base(ap); | |
1264 | struct mv_port_priv *pp = ap->private_data; | |
1265 | u32 out_ptr; | |
1266 | ||
1267 | out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | |
1268 | ||
1269 | /* the response consumer index should be the same as we remember it */ | |
8b260248 | 1270 | assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == |
31961943 BR |
1271 | pp->rsp_consumer); |
1272 | ||
1273 | /* increment our consumer index... */ | |
1274 | pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer); | |
8b260248 | 1275 | |
31961943 | 1276 | /* and, until we do NCQ, there should only be 1 CRPB waiting */ |
8b260248 JG |
1277 | assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >> |
1278 | EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) == | |
31961943 BR |
1279 | pp->rsp_consumer); |
1280 | ||
1281 | /* write out our inc'd consumer index so EDMA knows we're caught up */ | |
1282 | out_ptr &= EDMA_RSP_Q_BASE_LO_MASK; | |
1283 | out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT; | |
1284 | writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); | |
1285 | ||
1286 | /* Return ATA status register for completed CRPB */ | |
1287 | return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT); | |
1288 | } | |
1289 | ||
05b308e1 BR |
1290 | /** |
1291 | * mv_err_intr - Handle error interrupts on the port | |
1292 | * @ap: ATA channel to manipulate | |
1293 | * | |
1294 | * In most cases, just clear the interrupt and move on. However, | |
1295 | * some cases require an eDMA reset, which is done right before | |
1296 | * the COMRESET in mv_phy_reset(). The SERR case requires a | |
1297 | * clear of pending errors in the SATA SERROR register. Finally, | |
1298 | * if the port disabled DMA, update our cached copy to match. | |
1299 | * | |
1300 | * LOCKING: | |
1301 | * Inherited from caller. | |
1302 | */ | |
31961943 BR |
1303 | static void mv_err_intr(struct ata_port *ap) |
1304 | { | |
1305 | void __iomem *port_mmio = mv_ap_base(ap); | |
1306 | u32 edma_err_cause, serr = 0; | |
20f733e7 BR |
1307 | |
1308 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1309 | ||
1310 | if (EDMA_ERR_SERR & edma_err_cause) { | |
1311 | serr = scr_read(ap, SCR_ERROR); | |
1312 | scr_write_flush(ap, SCR_ERROR, serr); | |
1313 | } | |
afb0edd9 BR |
1314 | if (EDMA_ERR_SELF_DIS & edma_err_cause) { |
1315 | struct mv_port_priv *pp = ap->private_data; | |
1316 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
1317 | } | |
1318 | DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x " | |
1319 | "SERR: 0x%08x\n", ap->id, edma_err_cause, serr); | |
20f733e7 BR |
1320 | |
1321 | /* Clear EDMA now that SERR cleanup done */ | |
1322 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1323 | ||
1324 | /* check for fatal here and recover if needed */ | |
1325 | if (EDMA_ERR_FATAL & edma_err_cause) { | |
c9d39130 | 1326 | mv_stop_and_reset(ap); |
20f733e7 BR |
1327 | } |
1328 | } | |
1329 | ||
05b308e1 BR |
1330 | /** |
1331 | * mv_host_intr - Handle all interrupts on the given host controller | |
1332 | * @host_set: host specific structure | |
1333 | * @relevant: port error bits relevant to this host controller | |
1334 | * @hc: which host controller we're to look at | |
1335 | * | |
1336 | * Read then write clear the HC interrupt status then walk each | |
1337 | * port connected to the HC and see if it needs servicing. Port | |
1338 | * success ints are reported in the HC interrupt status reg, the | |
1339 | * port error ints are reported in the higher level main | |
1340 | * interrupt status register and thus are passed in via the | |
1341 | * 'relevant' argument. | |
1342 | * | |
1343 | * LOCKING: | |
1344 | * Inherited from caller. | |
1345 | */ | |
20f733e7 BR |
1346 | static void mv_host_intr(struct ata_host_set *host_set, u32 relevant, |
1347 | unsigned int hc) | |
1348 | { | |
1349 | void __iomem *mmio = host_set->mmio_base; | |
1350 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); | |
1351 | struct ata_port *ap; | |
1352 | struct ata_queued_cmd *qc; | |
1353 | u32 hc_irq_cause; | |
31961943 | 1354 | int shift, port, port0, hard_port, handled; |
a7dac447 | 1355 | unsigned int err_mask; |
31961943 | 1356 | u8 ata_status = 0; |
20f733e7 BR |
1357 | |
1358 | if (hc == 0) { | |
1359 | port0 = 0; | |
1360 | } else { | |
1361 | port0 = MV_PORTS_PER_HC; | |
1362 | } | |
1363 | ||
1364 | /* we'll need the HC success int register in most cases */ | |
1365 | hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS); | |
1366 | if (hc_irq_cause) { | |
31961943 | 1367 | writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS); |
20f733e7 BR |
1368 | } |
1369 | ||
1370 | VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n", | |
1371 | hc,relevant,hc_irq_cause); | |
1372 | ||
1373 | for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) { | |
1374 | ap = host_set->ports[port]; | |
1375 | hard_port = port & MV_PORT_MASK; /* range 0-3 */ | |
31961943 | 1376 | handled = 0; /* ensure ata_status is set if handled++ */ |
20f733e7 | 1377 | |
31961943 BR |
1378 | if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) { |
1379 | /* new CRPB on the queue; just one at a time until NCQ | |
1380 | */ | |
1381 | ata_status = mv_get_crpb_status(ap); | |
1382 | handled++; | |
1383 | } else if ((DEV_IRQ << hard_port) & hc_irq_cause) { | |
1384 | /* received ATA IRQ; read the status reg to clear INTRQ | |
20f733e7 BR |
1385 | */ |
1386 | ata_status = readb((void __iomem *) | |
1387 | ap->ioaddr.status_addr); | |
31961943 | 1388 | handled++; |
20f733e7 BR |
1389 | } |
1390 | ||
a2c91a88 JG |
1391 | if (ap && |
1392 | (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) | |
1393 | continue; | |
1394 | ||
a7dac447 JG |
1395 | err_mask = ac_err_mask(ata_status); |
1396 | ||
31961943 | 1397 | shift = port << 1; /* (port * 2) */ |
20f733e7 BR |
1398 | if (port >= MV_PORTS_PER_HC) { |
1399 | shift++; /* skip bit 8 in the HC Main IRQ reg */ | |
1400 | } | |
1401 | if ((PORT0_ERR << shift) & relevant) { | |
1402 | mv_err_intr(ap); | |
a7dac447 | 1403 | err_mask |= AC_ERR_OTHER; |
31961943 | 1404 | handled++; |
20f733e7 | 1405 | } |
8b260248 | 1406 | |
31961943 | 1407 | if (handled && ap) { |
20f733e7 BR |
1408 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1409 | if (NULL != qc) { | |
1410 | VPRINTK("port %u IRQ found for qc, " | |
1411 | "ata_status 0x%x\n", port,ata_status); | |
20f733e7 | 1412 | /* mark qc status appropriately */ |
a22e2eb0 AL |
1413 | if (!(qc->tf.ctl & ATA_NIEN)) { |
1414 | qc->err_mask |= err_mask; | |
1415 | ata_qc_complete(qc); | |
1416 | } | |
20f733e7 BR |
1417 | } |
1418 | } | |
1419 | } | |
1420 | VPRINTK("EXIT\n"); | |
1421 | } | |
1422 | ||
05b308e1 | 1423 | /** |
8b260248 | 1424 | * mv_interrupt - |
05b308e1 BR |
1425 | * @irq: unused |
1426 | * @dev_instance: private data; in this case the host structure | |
1427 | * @regs: unused | |
1428 | * | |
1429 | * Read the read only register to determine if any host | |
1430 | * controllers have pending interrupts. If so, call lower level | |
1431 | * routine to handle. Also check for PCI errors which are only | |
1432 | * reported here. | |
1433 | * | |
8b260248 | 1434 | * LOCKING: |
05b308e1 BR |
1435 | * This routine holds the host_set lock while processing pending |
1436 | * interrupts. | |
1437 | */ | |
20f733e7 BR |
1438 | static irqreturn_t mv_interrupt(int irq, void *dev_instance, |
1439 | struct pt_regs *regs) | |
1440 | { | |
1441 | struct ata_host_set *host_set = dev_instance; | |
1442 | unsigned int hc, handled = 0, n_hcs; | |
31961943 | 1443 | void __iomem *mmio = host_set->mmio_base; |
20f733e7 BR |
1444 | u32 irq_stat; |
1445 | ||
20f733e7 | 1446 | irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS); |
20f733e7 BR |
1447 | |
1448 | /* check the cases where we either have nothing pending or have read | |
1449 | * a bogus register value which can indicate HW removal or PCI fault | |
1450 | */ | |
1451 | if (!irq_stat || (0xffffffffU == irq_stat)) { | |
1452 | return IRQ_NONE; | |
1453 | } | |
1454 | ||
31961943 | 1455 | n_hcs = mv_get_hc_count(host_set->ports[0]->flags); |
20f733e7 BR |
1456 | spin_lock(&host_set->lock); |
1457 | ||
1458 | for (hc = 0; hc < n_hcs; hc++) { | |
1459 | u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT)); | |
1460 | if (relevant) { | |
1461 | mv_host_intr(host_set, relevant, hc); | |
31961943 | 1462 | handled++; |
20f733e7 BR |
1463 | } |
1464 | } | |
1465 | if (PCI_ERR & irq_stat) { | |
31961943 BR |
1466 | printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n", |
1467 | readl(mmio + PCI_IRQ_CAUSE_OFS)); | |
1468 | ||
afb0edd9 | 1469 | DPRINTK("All regs @ PCI error\n"); |
31961943 | 1470 | mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev)); |
20f733e7 | 1471 | |
31961943 BR |
1472 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); |
1473 | handled++; | |
1474 | } | |
20f733e7 BR |
1475 | spin_unlock(&host_set->lock); |
1476 | ||
1477 | return IRQ_RETVAL(handled); | |
1478 | } | |
1479 | ||
c9d39130 JG |
1480 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
1481 | { | |
1482 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); | |
1483 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; | |
1484 | ||
1485 | return hc_mmio + ofs; | |
1486 | } | |
1487 | ||
1488 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) | |
1489 | { | |
1490 | unsigned int ofs; | |
1491 | ||
1492 | switch (sc_reg_in) { | |
1493 | case SCR_STATUS: | |
1494 | case SCR_ERROR: | |
1495 | case SCR_CONTROL: | |
1496 | ofs = sc_reg_in * sizeof(u32); | |
1497 | break; | |
1498 | default: | |
1499 | ofs = 0xffffffffU; | |
1500 | break; | |
1501 | } | |
1502 | return ofs; | |
1503 | } | |
1504 | ||
1505 | static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in) | |
1506 | { | |
1507 | void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); | |
1508 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | |
1509 | ||
1510 | if (ofs != 0xffffffffU) | |
1511 | return readl(mmio + ofs); | |
1512 | else | |
1513 | return (u32) ofs; | |
1514 | } | |
1515 | ||
1516 | static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val) | |
1517 | { | |
1518 | void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no); | |
1519 | unsigned int ofs = mv5_scr_offset(sc_reg_in); | |
1520 | ||
1521 | if (ofs != 0xffffffffU) | |
1522 | writelfl(val, mmio + ofs); | |
1523 | } | |
1524 | ||
522479fb JG |
1525 | static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio) |
1526 | { | |
1527 | u8 rev_id; | |
1528 | int early_5080; | |
1529 | ||
1530 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
1531 | ||
1532 | early_5080 = (pdev->device == 0x5080) && (rev_id == 0); | |
1533 | ||
1534 | if (!early_5080) { | |
1535 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
1536 | tmp |= (1 << 0); | |
1537 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
1538 | } | |
1539 | ||
1540 | mv_reset_pci_bus(pdev, mmio); | |
1541 | } | |
1542 | ||
1543 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
1544 | { | |
1545 | writel(0x0fcfffff, mmio + MV_FLASH_CTL); | |
1546 | } | |
1547 | ||
47c2b677 | 1548 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
1549 | void __iomem *mmio) |
1550 | { | |
c9d39130 JG |
1551 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
1552 | u32 tmp; | |
1553 | ||
1554 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
1555 | ||
1556 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ | |
1557 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ | |
ba3fe8fb JG |
1558 | } |
1559 | ||
47c2b677 | 1560 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 1561 | { |
522479fb JG |
1562 | u32 tmp; |
1563 | ||
1564 | writel(0, mmio + MV_GPIO_PORT_CTL); | |
1565 | ||
1566 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ | |
1567 | ||
1568 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
1569 | tmp |= ~(1 << 0); | |
1570 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
ba3fe8fb JG |
1571 | } |
1572 | ||
2a47ce06 JG |
1573 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
1574 | unsigned int port) | |
bca1c4eb | 1575 | { |
c9d39130 JG |
1576 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
1577 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); | |
1578 | u32 tmp; | |
1579 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); | |
1580 | ||
1581 | if (fix_apm_sq) { | |
1582 | tmp = readl(phy_mmio + MV5_LT_MODE); | |
1583 | tmp |= (1 << 19); | |
1584 | writel(tmp, phy_mmio + MV5_LT_MODE); | |
1585 | ||
1586 | tmp = readl(phy_mmio + MV5_PHY_CTL); | |
1587 | tmp &= ~0x3; | |
1588 | tmp |= 0x1; | |
1589 | writel(tmp, phy_mmio + MV5_PHY_CTL); | |
1590 | } | |
1591 | ||
1592 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
1593 | tmp &= ~mask; | |
1594 | tmp |= hpriv->signal[port].pre; | |
1595 | tmp |= hpriv->signal[port].amps; | |
1596 | writel(tmp, phy_mmio + MV5_PHY_MODE); | |
bca1c4eb JG |
1597 | } |
1598 | ||
c9d39130 JG |
1599 | |
1600 | #undef ZERO | |
1601 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
1602 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, | |
1603 | unsigned int port) | |
1604 | { | |
1605 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
1606 | ||
1607 | writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS); | |
1608 | ||
1609 | mv_channel_reset(hpriv, mmio, port); | |
1610 | ||
1611 | ZERO(0x028); /* command */ | |
1612 | writel(0x11f, port_mmio + EDMA_CFG_OFS); | |
1613 | ZERO(0x004); /* timer */ | |
1614 | ZERO(0x008); /* irq err cause */ | |
1615 | ZERO(0x00c); /* irq err mask */ | |
1616 | ZERO(0x010); /* rq bah */ | |
1617 | ZERO(0x014); /* rq inp */ | |
1618 | ZERO(0x018); /* rq outp */ | |
1619 | ZERO(0x01c); /* respq bah */ | |
1620 | ZERO(0x024); /* respq outp */ | |
1621 | ZERO(0x020); /* respq inp */ | |
1622 | ZERO(0x02c); /* test control */ | |
1623 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); | |
1624 | } | |
1625 | #undef ZERO | |
1626 | ||
1627 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
1628 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
1629 | unsigned int hc) | |
47c2b677 | 1630 | { |
c9d39130 JG |
1631 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
1632 | u32 tmp; | |
1633 | ||
1634 | ZERO(0x00c); | |
1635 | ZERO(0x010); | |
1636 | ZERO(0x014); | |
1637 | ZERO(0x018); | |
1638 | ||
1639 | tmp = readl(hc_mmio + 0x20); | |
1640 | tmp &= 0x1c1c1c1c; | |
1641 | tmp |= 0x03030303; | |
1642 | writel(tmp, hc_mmio + 0x20); | |
1643 | } | |
1644 | #undef ZERO | |
1645 | ||
1646 | static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
1647 | unsigned int n_hc) | |
1648 | { | |
1649 | unsigned int hc, port; | |
1650 | ||
1651 | for (hc = 0; hc < n_hc; hc++) { | |
1652 | for (port = 0; port < MV_PORTS_PER_HC; port++) | |
1653 | mv5_reset_hc_port(hpriv, mmio, | |
1654 | (hc * MV_PORTS_PER_HC) + port); | |
1655 | ||
1656 | mv5_reset_one_hc(hpriv, mmio, hc); | |
1657 | } | |
1658 | ||
1659 | return 0; | |
47c2b677 JG |
1660 | } |
1661 | ||
101ffae2 JG |
1662 | #undef ZERO |
1663 | #define ZERO(reg) writel(0, mmio + (reg)) | |
1664 | static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio) | |
1665 | { | |
1666 | u32 tmp; | |
1667 | ||
1668 | tmp = readl(mmio + MV_PCI_MODE); | |
1669 | tmp &= 0xff00ffff; | |
1670 | writel(tmp, mmio + MV_PCI_MODE); | |
1671 | ||
1672 | ZERO(MV_PCI_DISC_TIMER); | |
1673 | ZERO(MV_PCI_MSI_TRIGGER); | |
1674 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); | |
1675 | ZERO(HC_MAIN_IRQ_MASK_OFS); | |
1676 | ZERO(MV_PCI_SERR_MASK); | |
1677 | ZERO(PCI_IRQ_CAUSE_OFS); | |
1678 | ZERO(PCI_IRQ_MASK_OFS); | |
1679 | ZERO(MV_PCI_ERR_LOW_ADDRESS); | |
1680 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); | |
1681 | ZERO(MV_PCI_ERR_ATTRIBUTE); | |
1682 | ZERO(MV_PCI_ERR_COMMAND); | |
1683 | } | |
1684 | #undef ZERO | |
1685 | ||
1686 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
1687 | { | |
1688 | u32 tmp; | |
1689 | ||
1690 | mv5_reset_flash(hpriv, mmio); | |
1691 | ||
1692 | tmp = readl(mmio + MV_GPIO_PORT_CTL); | |
1693 | tmp &= 0x3; | |
1694 | tmp |= (1 << 5) | (1 << 6); | |
1695 | writel(tmp, mmio + MV_GPIO_PORT_CTL); | |
1696 | } | |
1697 | ||
1698 | /** | |
1699 | * mv6_reset_hc - Perform the 6xxx global soft reset | |
1700 | * @mmio: base address of the HBA | |
1701 | * | |
1702 | * This routine only applies to 6xxx parts. | |
1703 | * | |
1704 | * LOCKING: | |
1705 | * Inherited from caller. | |
1706 | */ | |
c9d39130 JG |
1707 | static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio, |
1708 | unsigned int n_hc) | |
101ffae2 JG |
1709 | { |
1710 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS; | |
1711 | int i, rc = 0; | |
1712 | u32 t; | |
1713 | ||
1714 | /* Following procedure defined in PCI "main command and status | |
1715 | * register" table. | |
1716 | */ | |
1717 | t = readl(reg); | |
1718 | writel(t | STOP_PCI_MASTER, reg); | |
1719 | ||
1720 | for (i = 0; i < 1000; i++) { | |
1721 | udelay(1); | |
1722 | t = readl(reg); | |
1723 | if (PCI_MASTER_EMPTY & t) { | |
1724 | break; | |
1725 | } | |
1726 | } | |
1727 | if (!(PCI_MASTER_EMPTY & t)) { | |
1728 | printk(KERN_ERR DRV_NAME ": PCI master won't flush\n"); | |
1729 | rc = 1; | |
1730 | goto done; | |
1731 | } | |
1732 | ||
1733 | /* set reset */ | |
1734 | i = 5; | |
1735 | do { | |
1736 | writel(t | GLOB_SFT_RST, reg); | |
1737 | t = readl(reg); | |
1738 | udelay(1); | |
1739 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); | |
1740 | ||
1741 | if (!(GLOB_SFT_RST & t)) { | |
1742 | printk(KERN_ERR DRV_NAME ": can't set global reset\n"); | |
1743 | rc = 1; | |
1744 | goto done; | |
1745 | } | |
1746 | ||
1747 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ | |
1748 | i = 5; | |
1749 | do { | |
1750 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); | |
1751 | t = readl(reg); | |
1752 | udelay(1); | |
1753 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); | |
1754 | ||
1755 | if (GLOB_SFT_RST & t) { | |
1756 | printk(KERN_ERR DRV_NAME ": can't clear global reset\n"); | |
1757 | rc = 1; | |
1758 | } | |
1759 | done: | |
1760 | return rc; | |
1761 | } | |
1762 | ||
47c2b677 | 1763 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
1764 | void __iomem *mmio) |
1765 | { | |
1766 | void __iomem *port_mmio; | |
1767 | u32 tmp; | |
1768 | ||
ba3fe8fb JG |
1769 | tmp = readl(mmio + MV_RESET_CFG); |
1770 | if ((tmp & (1 << 0)) == 0) { | |
47c2b677 | 1771 | hpriv->signal[idx].amps = 0x7 << 8; |
ba3fe8fb JG |
1772 | hpriv->signal[idx].pre = 0x1 << 5; |
1773 | return; | |
1774 | } | |
1775 | ||
1776 | port_mmio = mv_port_base(mmio, idx); | |
1777 | tmp = readl(port_mmio + PHY_MODE2); | |
1778 | ||
1779 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
1780 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
1781 | } | |
1782 | ||
47c2b677 | 1783 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 1784 | { |
47c2b677 | 1785 | writel(0x00000060, mmio + MV_GPIO_PORT_CTL); |
ba3fe8fb JG |
1786 | } |
1787 | ||
c9d39130 | 1788 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
2a47ce06 | 1789 | unsigned int port) |
bca1c4eb | 1790 | { |
c9d39130 JG |
1791 | void __iomem *port_mmio = mv_port_base(mmio, port); |
1792 | ||
bca1c4eb | 1793 | u32 hp_flags = hpriv->hp_flags; |
47c2b677 JG |
1794 | int fix_phy_mode2 = |
1795 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); | |
bca1c4eb | 1796 | int fix_phy_mode4 = |
47c2b677 JG |
1797 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
1798 | u32 m2, tmp; | |
1799 | ||
1800 | if (fix_phy_mode2) { | |
1801 | m2 = readl(port_mmio + PHY_MODE2); | |
1802 | m2 &= ~(1 << 16); | |
1803 | m2 |= (1 << 31); | |
1804 | writel(m2, port_mmio + PHY_MODE2); | |
1805 | ||
1806 | udelay(200); | |
1807 | ||
1808 | m2 = readl(port_mmio + PHY_MODE2); | |
1809 | m2 &= ~((1 << 16) | (1 << 31)); | |
1810 | writel(m2, port_mmio + PHY_MODE2); | |
1811 | ||
1812 | udelay(200); | |
1813 | } | |
1814 | ||
1815 | /* who knows what this magic does */ | |
1816 | tmp = readl(port_mmio + PHY_MODE3); | |
1817 | tmp &= ~0x7F800000; | |
1818 | tmp |= 0x2A800000; | |
1819 | writel(tmp, port_mmio + PHY_MODE3); | |
bca1c4eb JG |
1820 | |
1821 | if (fix_phy_mode4) { | |
47c2b677 | 1822 | u32 m4; |
bca1c4eb JG |
1823 | |
1824 | m4 = readl(port_mmio + PHY_MODE4); | |
47c2b677 JG |
1825 | |
1826 | if (hp_flags & MV_HP_ERRATA_60X1B2) | |
1827 | tmp = readl(port_mmio + 0x310); | |
bca1c4eb JG |
1828 | |
1829 | m4 = (m4 & ~(1 << 1)) | (1 << 0); | |
1830 | ||
1831 | writel(m4, port_mmio + PHY_MODE4); | |
47c2b677 JG |
1832 | |
1833 | if (hp_flags & MV_HP_ERRATA_60X1B2) | |
1834 | writel(tmp, port_mmio + 0x310); | |
bca1c4eb JG |
1835 | } |
1836 | ||
1837 | /* Revert values of pre-emphasis and signal amps to the saved ones */ | |
1838 | m2 = readl(port_mmio + PHY_MODE2); | |
1839 | ||
1840 | m2 &= ~MV_M2_PREAMP_MASK; | |
2a47ce06 JG |
1841 | m2 |= hpriv->signal[port].amps; |
1842 | m2 |= hpriv->signal[port].pre; | |
47c2b677 | 1843 | m2 &= ~(1 << 16); |
bca1c4eb | 1844 | |
e4e7b892 JG |
1845 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
1846 | if (IS_GEN_IIE(hpriv)) { | |
1847 | m2 &= ~0xC30FF01F; | |
1848 | m2 |= 0x0000900F; | |
1849 | } | |
1850 | ||
bca1c4eb JG |
1851 | writel(m2, port_mmio + PHY_MODE2); |
1852 | } | |
1853 | ||
c9d39130 JG |
1854 | static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio, |
1855 | unsigned int port_no) | |
1856 | { | |
1857 | void __iomem *port_mmio = mv_port_base(mmio, port_no); | |
1858 | ||
1859 | writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS); | |
1860 | ||
1861 | if (IS_60XX(hpriv)) { | |
1862 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); | |
1863 | ifctl |= (1 << 12) | (1 << 7); | |
1864 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); | |
1865 | } | |
1866 | ||
1867 | udelay(25); /* allow reset propagation */ | |
1868 | ||
1869 | /* Spec never mentions clearing the bit. Marvell's driver does | |
1870 | * clear the bit, however. | |
1871 | */ | |
1872 | writelfl(0, port_mmio + EDMA_CMD_OFS); | |
1873 | ||
1874 | hpriv->ops->phy_errata(hpriv, mmio, port_no); | |
1875 | ||
1876 | if (IS_50XX(hpriv)) | |
1877 | mdelay(1); | |
1878 | } | |
1879 | ||
1880 | static void mv_stop_and_reset(struct ata_port *ap) | |
1881 | { | |
1882 | struct mv_host_priv *hpriv = ap->host_set->private_data; | |
1883 | void __iomem *mmio = ap->host_set->mmio_base; | |
1884 | ||
1885 | mv_stop_dma(ap); | |
1886 | ||
1887 | mv_channel_reset(hpriv, mmio, ap->port_no); | |
1888 | ||
22374677 JG |
1889 | __mv_phy_reset(ap, 0); |
1890 | } | |
1891 | ||
1892 | static inline void __msleep(unsigned int msec, int can_sleep) | |
1893 | { | |
1894 | if (can_sleep) | |
1895 | msleep(msec); | |
1896 | else | |
1897 | mdelay(msec); | |
c9d39130 JG |
1898 | } |
1899 | ||
05b308e1 | 1900 | /** |
22374677 | 1901 | * __mv_phy_reset - Perform eDMA reset followed by COMRESET |
05b308e1 BR |
1902 | * @ap: ATA channel to manipulate |
1903 | * | |
1904 | * Part of this is taken from __sata_phy_reset and modified to | |
1905 | * not sleep since this routine gets called from interrupt level. | |
1906 | * | |
1907 | * LOCKING: | |
1908 | * Inherited from caller. This is coded to safe to call at | |
1909 | * interrupt level, i.e. it does not sleep. | |
31961943 | 1910 | */ |
22374677 | 1911 | static void __mv_phy_reset(struct ata_port *ap, int can_sleep) |
20f733e7 | 1912 | { |
095fec88 | 1913 | struct mv_port_priv *pp = ap->private_data; |
22374677 | 1914 | struct mv_host_priv *hpriv = ap->host_set->private_data; |
20f733e7 BR |
1915 | void __iomem *port_mmio = mv_ap_base(ap); |
1916 | struct ata_taskfile tf; | |
1917 | struct ata_device *dev = &ap->device[0]; | |
31961943 | 1918 | unsigned long timeout; |
22374677 JG |
1919 | int retry = 5; |
1920 | u32 sstatus; | |
20f733e7 BR |
1921 | |
1922 | VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio); | |
1923 | ||
095fec88 | 1924 | DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x " |
31961943 BR |
1925 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1926 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | |
20f733e7 | 1927 | |
22374677 JG |
1928 | /* Issue COMRESET via SControl */ |
1929 | comreset_retry: | |
31961943 | 1930 | scr_write_flush(ap, SCR_CONTROL, 0x301); |
22374677 JG |
1931 | __msleep(1, can_sleep); |
1932 | ||
31961943 | 1933 | scr_write_flush(ap, SCR_CONTROL, 0x300); |
22374677 JG |
1934 | __msleep(20, can_sleep); |
1935 | ||
1936 | timeout = jiffies + msecs_to_jiffies(200); | |
31961943 | 1937 | do { |
22374677 JG |
1938 | sstatus = scr_read(ap, SCR_STATUS) & 0x3; |
1939 | if ((sstatus == 3) || (sstatus == 0)) | |
31961943 | 1940 | break; |
22374677 JG |
1941 | |
1942 | __msleep(1, can_sleep); | |
31961943 | 1943 | } while (time_before(jiffies, timeout)); |
20f733e7 | 1944 | |
22374677 JG |
1945 | /* work around errata */ |
1946 | if (IS_60XX(hpriv) && | |
1947 | (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) && | |
1948 | (retry-- > 0)) | |
1949 | goto comreset_retry; | |
095fec88 JG |
1950 | |
1951 | DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x " | |
31961943 BR |
1952 | "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS), |
1953 | mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL)); | |
1954 | ||
1955 | if (sata_dev_present(ap)) { | |
1956 | ata_port_probe(ap); | |
1957 | } else { | |
1958 | printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n", | |
1959 | ap->id, scr_read(ap, SCR_STATUS)); | |
1960 | ata_port_disable(ap); | |
20f733e7 BR |
1961 | return; |
1962 | } | |
31961943 | 1963 | ap->cbl = ATA_CBL_SATA; |
20f733e7 | 1964 | |
22374677 JG |
1965 | /* even after SStatus reflects that device is ready, |
1966 | * it seems to take a while for link to be fully | |
1967 | * established (and thus Status no longer 0x80/0x7F), | |
1968 | * so we poll a bit for that, here. | |
1969 | */ | |
1970 | retry = 20; | |
1971 | while (1) { | |
1972 | u8 drv_stat = ata_check_status(ap); | |
1973 | if ((drv_stat != 0x80) && (drv_stat != 0x7f)) | |
1974 | break; | |
1975 | __msleep(500, can_sleep); | |
1976 | if (retry-- <= 0) | |
1977 | break; | |
1978 | } | |
1979 | ||
20f733e7 BR |
1980 | tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr); |
1981 | tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr); | |
1982 | tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr); | |
1983 | tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr); | |
1984 | ||
1985 | dev->class = ata_dev_classify(&tf); | |
1986 | if (!ata_dev_present(dev)) { | |
1987 | VPRINTK("Port disabled post-sig: No device present.\n"); | |
1988 | ata_port_disable(ap); | |
1989 | } | |
095fec88 JG |
1990 | |
1991 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
1992 | ||
1993 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
1994 | ||
bca1c4eb | 1995 | VPRINTK("EXIT\n"); |
20f733e7 BR |
1996 | } |
1997 | ||
22374677 JG |
1998 | static void mv_phy_reset(struct ata_port *ap) |
1999 | { | |
2000 | __mv_phy_reset(ap, 1); | |
2001 | } | |
2002 | ||
05b308e1 BR |
2003 | /** |
2004 | * mv_eng_timeout - Routine called by libata when SCSI times out I/O | |
2005 | * @ap: ATA channel to manipulate | |
2006 | * | |
2007 | * Intent is to clear all pending error conditions, reset the | |
2008 | * chip/bus, fail the command, and move on. | |
2009 | * | |
2010 | * LOCKING: | |
2011 | * This routine holds the host_set lock while failing the command. | |
2012 | */ | |
31961943 BR |
2013 | static void mv_eng_timeout(struct ata_port *ap) |
2014 | { | |
2015 | struct ata_queued_cmd *qc; | |
31961943 BR |
2016 | |
2017 | printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id); | |
2018 | DPRINTK("All regs @ start of eng_timeout\n"); | |
8b260248 | 2019 | mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no, |
31961943 BR |
2020 | to_pci_dev(ap->host_set->dev)); |
2021 | ||
2022 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
2023 | printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n", | |
8b260248 | 2024 | ap->host_set->mmio_base, ap, qc, qc->scsicmd, |
31961943 BR |
2025 | &qc->scsicmd->cmnd); |
2026 | ||
2027 | mv_err_intr(ap); | |
c9d39130 | 2028 | mv_stop_and_reset(ap); |
31961943 | 2029 | |
f6379020 TH |
2030 | qc->err_mask |= AC_ERR_TIMEOUT; |
2031 | ata_eh_qc_complete(qc); | |
31961943 BR |
2032 | } |
2033 | ||
05b308e1 BR |
2034 | /** |
2035 | * mv_port_init - Perform some early initialization on a single port. | |
2036 | * @port: libata data structure storing shadow register addresses | |
2037 | * @port_mmio: base address of the port | |
2038 | * | |
2039 | * Initialize shadow register mmio addresses, clear outstanding | |
2040 | * interrupts on the port, and unmask interrupts for the future | |
2041 | * start of the port. | |
2042 | * | |
2043 | * LOCKING: | |
2044 | * Inherited from caller. | |
2045 | */ | |
31961943 | 2046 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
20f733e7 | 2047 | { |
31961943 BR |
2048 | unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS; |
2049 | unsigned serr_ofs; | |
2050 | ||
8b260248 | 2051 | /* PIO related setup |
31961943 BR |
2052 | */ |
2053 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); | |
8b260248 | 2054 | port->error_addr = |
31961943 BR |
2055 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
2056 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); | |
2057 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); | |
2058 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); | |
2059 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); | |
2060 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); | |
8b260248 | 2061 | port->status_addr = |
31961943 BR |
2062 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
2063 | /* special case: control/altstatus doesn't have ATA_REG_ address */ | |
2064 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS; | |
2065 | ||
2066 | /* unused: */ | |
20f733e7 BR |
2067 | port->cmd_addr = port->bmdma_addr = port->scr_addr = 0; |
2068 | ||
31961943 BR |
2069 | /* Clear any currently outstanding port interrupt conditions */ |
2070 | serr_ofs = mv_scr_offset(SCR_ERROR); | |
2071 | writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs); | |
2072 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS); | |
2073 | ||
20f733e7 | 2074 | /* unmask all EDMA error interrupts */ |
31961943 | 2075 | writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS); |
20f733e7 | 2076 | |
8b260248 | 2077 | VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n", |
31961943 BR |
2078 | readl(port_mmio + EDMA_CFG_OFS), |
2079 | readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS), | |
2080 | readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS)); | |
20f733e7 BR |
2081 | } |
2082 | ||
47c2b677 | 2083 | static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv, |
522479fb | 2084 | unsigned int board_idx) |
bca1c4eb JG |
2085 | { |
2086 | u8 rev_id; | |
2087 | u32 hp_flags = hpriv->hp_flags; | |
2088 | ||
2089 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
2090 | ||
2091 | switch(board_idx) { | |
47c2b677 JG |
2092 | case chip_5080: |
2093 | hpriv->ops = &mv5xxx_ops; | |
2094 | hp_flags |= MV_HP_50XX; | |
2095 | ||
2096 | switch (rev_id) { | |
2097 | case 0x1: | |
2098 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
2099 | break; | |
2100 | case 0x3: | |
2101 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2102 | break; | |
2103 | default: | |
2104 | dev_printk(KERN_WARNING, &pdev->dev, | |
2105 | "Applying 50XXB2 workarounds to unknown rev\n"); | |
2106 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2107 | break; | |
2108 | } | |
2109 | break; | |
2110 | ||
bca1c4eb JG |
2111 | case chip_504x: |
2112 | case chip_508x: | |
47c2b677 | 2113 | hpriv->ops = &mv5xxx_ops; |
bca1c4eb JG |
2114 | hp_flags |= MV_HP_50XX; |
2115 | ||
47c2b677 JG |
2116 | switch (rev_id) { |
2117 | case 0x0: | |
2118 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
2119 | break; | |
2120 | case 0x3: | |
2121 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2122 | break; | |
2123 | default: | |
2124 | dev_printk(KERN_WARNING, &pdev->dev, | |
2125 | "Applying B2 workarounds to unknown rev\n"); | |
2126 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
2127 | break; | |
bca1c4eb JG |
2128 | } |
2129 | break; | |
2130 | ||
2131 | case chip_604x: | |
2132 | case chip_608x: | |
47c2b677 JG |
2133 | hpriv->ops = &mv6xxx_ops; |
2134 | ||
bca1c4eb | 2135 | switch (rev_id) { |
47c2b677 JG |
2136 | case 0x7: |
2137 | hp_flags |= MV_HP_ERRATA_60X1B2; | |
2138 | break; | |
2139 | case 0x9: | |
2140 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
bca1c4eb JG |
2141 | break; |
2142 | default: | |
2143 | dev_printk(KERN_WARNING, &pdev->dev, | |
47c2b677 JG |
2144 | "Applying B2 workarounds to unknown rev\n"); |
2145 | hp_flags |= MV_HP_ERRATA_60X1B2; | |
bca1c4eb JG |
2146 | break; |
2147 | } | |
2148 | break; | |
2149 | ||
e4e7b892 JG |
2150 | case chip_7042: |
2151 | case chip_6042: | |
2152 | hpriv->ops = &mv6xxx_ops; | |
2153 | ||
2154 | hp_flags |= MV_HP_GEN_IIE; | |
2155 | ||
2156 | switch (rev_id) { | |
2157 | case 0x0: | |
2158 | hp_flags |= MV_HP_ERRATA_XX42A0; | |
2159 | break; | |
2160 | case 0x1: | |
2161 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
2162 | break; | |
2163 | default: | |
2164 | dev_printk(KERN_WARNING, &pdev->dev, | |
2165 | "Applying 60X1C0 workarounds to unknown rev\n"); | |
2166 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
2167 | break; | |
2168 | } | |
2169 | break; | |
2170 | ||
bca1c4eb JG |
2171 | default: |
2172 | printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx); | |
2173 | return 1; | |
2174 | } | |
2175 | ||
2176 | hpriv->hp_flags = hp_flags; | |
2177 | ||
2178 | return 0; | |
2179 | } | |
2180 | ||
05b308e1 | 2181 | /** |
47c2b677 | 2182 | * mv_init_host - Perform some early initialization of the host. |
bca1c4eb | 2183 | * @pdev: host PCI device |
05b308e1 BR |
2184 | * @probe_ent: early data struct representing the host |
2185 | * | |
2186 | * If possible, do an early global reset of the host. Then do | |
2187 | * our port init and clear/unmask all/relevant host interrupts. | |
2188 | * | |
2189 | * LOCKING: | |
2190 | * Inherited from caller. | |
2191 | */ | |
47c2b677 | 2192 | static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent, |
bca1c4eb | 2193 | unsigned int board_idx) |
20f733e7 BR |
2194 | { |
2195 | int rc = 0, n_hc, port, hc; | |
2196 | void __iomem *mmio = probe_ent->mmio_base; | |
bca1c4eb JG |
2197 | struct mv_host_priv *hpriv = probe_ent->private_data; |
2198 | ||
47c2b677 JG |
2199 | /* global interrupt mask */ |
2200 | writel(0, mmio + HC_MAIN_IRQ_MASK_OFS); | |
2201 | ||
2202 | rc = mv_chip_id(pdev, hpriv, board_idx); | |
bca1c4eb JG |
2203 | if (rc) |
2204 | goto done; | |
2205 | ||
2206 | n_hc = mv_get_hc_count(probe_ent->host_flags); | |
2207 | probe_ent->n_ports = MV_PORTS_PER_HC * n_hc; | |
2208 | ||
47c2b677 JG |
2209 | for (port = 0; port < probe_ent->n_ports; port++) |
2210 | hpriv->ops->read_preamp(hpriv, port, mmio); | |
20f733e7 | 2211 | |
c9d39130 | 2212 | rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc); |
47c2b677 | 2213 | if (rc) |
20f733e7 | 2214 | goto done; |
20f733e7 | 2215 | |
522479fb JG |
2216 | hpriv->ops->reset_flash(hpriv, mmio); |
2217 | hpriv->ops->reset_bus(pdev, mmio); | |
47c2b677 | 2218 | hpriv->ops->enable_leds(hpriv, mmio); |
20f733e7 BR |
2219 | |
2220 | for (port = 0; port < probe_ent->n_ports; port++) { | |
2a47ce06 | 2221 | if (IS_60XX(hpriv)) { |
c9d39130 JG |
2222 | void __iomem *port_mmio = mv_port_base(mmio, port); |
2223 | ||
2a47ce06 JG |
2224 | u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL); |
2225 | ifctl |= (1 << 12); | |
2226 | writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL); | |
2227 | } | |
2228 | ||
c9d39130 | 2229 | hpriv->ops->phy_errata(hpriv, mmio, port); |
2a47ce06 JG |
2230 | } |
2231 | ||
2232 | for (port = 0; port < probe_ent->n_ports; port++) { | |
2233 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
31961943 | 2234 | mv_port_init(&probe_ent->port[port], port_mmio); |
20f733e7 BR |
2235 | } |
2236 | ||
2237 | for (hc = 0; hc < n_hc; hc++) { | |
31961943 BR |
2238 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
2239 | ||
2240 | VPRINTK("HC%i: HC config=0x%08x HC IRQ cause " | |
2241 | "(before clear)=0x%08x\n", hc, | |
2242 | readl(hc_mmio + HC_CFG_OFS), | |
2243 | readl(hc_mmio + HC_IRQ_CAUSE_OFS)); | |
2244 | ||
2245 | /* Clear any currently outstanding hc interrupt conditions */ | |
2246 | writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); | |
20f733e7 BR |
2247 | } |
2248 | ||
31961943 BR |
2249 | /* Clear any currently outstanding host interrupt conditions */ |
2250 | writelfl(0, mmio + PCI_IRQ_CAUSE_OFS); | |
2251 | ||
2252 | /* and unmask interrupt generation for host regs */ | |
2253 | writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS); | |
2254 | writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS); | |
20f733e7 BR |
2255 | |
2256 | VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x " | |
8b260248 | 2257 | "PCI int cause/mask=0x%08x/0x%08x\n", |
20f733e7 BR |
2258 | readl(mmio + HC_MAIN_IRQ_CAUSE_OFS), |
2259 | readl(mmio + HC_MAIN_IRQ_MASK_OFS), | |
2260 | readl(mmio + PCI_IRQ_CAUSE_OFS), | |
2261 | readl(mmio + PCI_IRQ_MASK_OFS)); | |
bca1c4eb | 2262 | |
31961943 | 2263 | done: |
20f733e7 BR |
2264 | return rc; |
2265 | } | |
2266 | ||
05b308e1 BR |
2267 | /** |
2268 | * mv_print_info - Dump key info to kernel log for perusal. | |
2269 | * @probe_ent: early data struct representing the host | |
2270 | * | |
2271 | * FIXME: complete this. | |
2272 | * | |
2273 | * LOCKING: | |
2274 | * Inherited from caller. | |
2275 | */ | |
31961943 BR |
2276 | static void mv_print_info(struct ata_probe_ent *probe_ent) |
2277 | { | |
2278 | struct pci_dev *pdev = to_pci_dev(probe_ent->dev); | |
2279 | struct mv_host_priv *hpriv = probe_ent->private_data; | |
2280 | u8 rev_id, scc; | |
2281 | const char *scc_s; | |
2282 | ||
2283 | /* Use this to determine the HW stepping of the chip so we know | |
2284 | * what errata to workaround | |
2285 | */ | |
2286 | pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); | |
2287 | ||
2288 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); | |
2289 | if (scc == 0) | |
2290 | scc_s = "SCSI"; | |
2291 | else if (scc == 0x01) | |
2292 | scc_s = "RAID"; | |
2293 | else | |
2294 | scc_s = "unknown"; | |
2295 | ||
a9524a76 JG |
2296 | dev_printk(KERN_INFO, &pdev->dev, |
2297 | "%u slots %u ports %s mode IRQ via %s\n", | |
8b260248 | 2298 | (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports, |
31961943 BR |
2299 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); |
2300 | } | |
2301 | ||
05b308e1 BR |
2302 | /** |
2303 | * mv_init_one - handle a positive probe of a Marvell host | |
2304 | * @pdev: PCI device found | |
2305 | * @ent: PCI device ID entry for the matched host | |
2306 | * | |
2307 | * LOCKING: | |
2308 | * Inherited from caller. | |
2309 | */ | |
20f733e7 BR |
2310 | static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
2311 | { | |
2312 | static int printed_version = 0; | |
2313 | struct ata_probe_ent *probe_ent = NULL; | |
2314 | struct mv_host_priv *hpriv; | |
2315 | unsigned int board_idx = (unsigned int)ent->driver_data; | |
2316 | void __iomem *mmio_base; | |
31961943 | 2317 | int pci_dev_busy = 0, rc; |
20f733e7 | 2318 | |
a9524a76 JG |
2319 | if (!printed_version++) |
2320 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
20f733e7 | 2321 | |
20f733e7 BR |
2322 | rc = pci_enable_device(pdev); |
2323 | if (rc) { | |
2324 | return rc; | |
2325 | } | |
2326 | ||
2327 | rc = pci_request_regions(pdev, DRV_NAME); | |
2328 | if (rc) { | |
2329 | pci_dev_busy = 1; | |
2330 | goto err_out; | |
2331 | } | |
2332 | ||
20f733e7 BR |
2333 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); |
2334 | if (probe_ent == NULL) { | |
2335 | rc = -ENOMEM; | |
2336 | goto err_out_regions; | |
2337 | } | |
2338 | ||
2339 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
2340 | probe_ent->dev = pci_dev_to_dev(pdev); | |
2341 | INIT_LIST_HEAD(&probe_ent->node); | |
2342 | ||
31961943 | 2343 | mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0); |
20f733e7 BR |
2344 | if (mmio_base == NULL) { |
2345 | rc = -ENOMEM; | |
2346 | goto err_out_free_ent; | |
2347 | } | |
2348 | ||
2349 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
2350 | if (!hpriv) { | |
2351 | rc = -ENOMEM; | |
2352 | goto err_out_iounmap; | |
2353 | } | |
2354 | memset(hpriv, 0, sizeof(*hpriv)); | |
2355 | ||
2356 | probe_ent->sht = mv_port_info[board_idx].sht; | |
2357 | probe_ent->host_flags = mv_port_info[board_idx].host_flags; | |
2358 | probe_ent->pio_mask = mv_port_info[board_idx].pio_mask; | |
2359 | probe_ent->udma_mask = mv_port_info[board_idx].udma_mask; | |
2360 | probe_ent->port_ops = mv_port_info[board_idx].port_ops; | |
2361 | ||
2362 | probe_ent->irq = pdev->irq; | |
2363 | probe_ent->irq_flags = SA_SHIRQ; | |
2364 | probe_ent->mmio_base = mmio_base; | |
2365 | probe_ent->private_data = hpriv; | |
2366 | ||
2367 | /* initialize adapter */ | |
47c2b677 | 2368 | rc = mv_init_host(pdev, probe_ent, board_idx); |
20f733e7 BR |
2369 | if (rc) { |
2370 | goto err_out_hpriv; | |
2371 | } | |
20f733e7 | 2372 | |
31961943 | 2373 | /* Enable interrupts */ |
ddef9bb3 | 2374 | if (msi && pci_enable_msi(pdev) == 0) { |
31961943 BR |
2375 | hpriv->hp_flags |= MV_HP_FLAG_MSI; |
2376 | } else { | |
2377 | pci_intx(pdev, 1); | |
20f733e7 BR |
2378 | } |
2379 | ||
31961943 BR |
2380 | mv_dump_pci_cfg(pdev, 0x68); |
2381 | mv_print_info(probe_ent); | |
2382 | ||
2383 | if (ata_device_add(probe_ent) == 0) { | |
2384 | rc = -ENODEV; /* No devices discovered */ | |
2385 | goto err_out_dev_add; | |
2386 | } | |
20f733e7 | 2387 | |
31961943 | 2388 | kfree(probe_ent); |
20f733e7 BR |
2389 | return 0; |
2390 | ||
31961943 BR |
2391 | err_out_dev_add: |
2392 | if (MV_HP_FLAG_MSI & hpriv->hp_flags) { | |
2393 | pci_disable_msi(pdev); | |
2394 | } else { | |
2395 | pci_intx(pdev, 0); | |
2396 | } | |
2397 | err_out_hpriv: | |
20f733e7 | 2398 | kfree(hpriv); |
31961943 BR |
2399 | err_out_iounmap: |
2400 | pci_iounmap(pdev, mmio_base); | |
2401 | err_out_free_ent: | |
20f733e7 | 2402 | kfree(probe_ent); |
31961943 | 2403 | err_out_regions: |
20f733e7 | 2404 | pci_release_regions(pdev); |
31961943 | 2405 | err_out: |
20f733e7 BR |
2406 | if (!pci_dev_busy) { |
2407 | pci_disable_device(pdev); | |
2408 | } | |
2409 | ||
2410 | return rc; | |
2411 | } | |
2412 | ||
2413 | static int __init mv_init(void) | |
2414 | { | |
2415 | return pci_module_init(&mv_pci_driver); | |
2416 | } | |
2417 | ||
2418 | static void __exit mv_exit(void) | |
2419 | { | |
2420 | pci_unregister_driver(&mv_pci_driver); | |
2421 | } | |
2422 | ||
2423 | MODULE_AUTHOR("Brett Russ"); | |
2424 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); | |
2425 | MODULE_LICENSE("GPL"); | |
2426 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); | |
2427 | MODULE_VERSION(DRV_VERSION); | |
2428 | ||
ddef9bb3 JG |
2429 | module_param(msi, int, 0444); |
2430 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); | |
2431 | ||
20f733e7 BR |
2432 | module_init(mv_init); |
2433 | module_exit(mv_exit); |