]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/scsi/sata_nv.c
[SCSI] remove Scsi_Host_Template typedef
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / sata_nv.c
CommitLineData
1da177e4
LT
1/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
aa7e16d6
JG
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
1da177e4 21 *
af36d7f0
JG
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
e710245b
AC
32 * 0.09
33 * - Fixed bug introduced by 0.08's MCP51 and MCP55 support.
af36d7f0 34 *
541134cf
DD
35 * 0.08
36 * - Added support for MCP51 and MCP55.
37 *
38 * 0.07
39 * - Added support for RAID class code.
40 *
1da177e4
LT
41 * 0.06
42 * - Added generic SATA support by using a pci_device_id that filters on
43 * the IDE storage class code.
44 *
45 * 0.03
46 * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
47 * mmio_base, which is only set for the CK804/MCP04 case.
48 *
49 * 0.02
50 * - Added support for CK804 SATA controller.
51 *
52 * 0.01
53 * - Initial revision.
54 */
55
56#include <linux/config.h>
57#include <linux/kernel.h>
58#include <linux/module.h>
59#include <linux/pci.h>
60#include <linux/init.h>
61#include <linux/blkdev.h>
62#include <linux/delay.h>
63#include <linux/interrupt.h>
a9524a76 64#include <linux/device.h>
1da177e4
LT
65#include "scsi.h"
66#include <scsi/scsi_host.h>
67#include <linux/libata.h>
68
69#define DRV_NAME "sata_nv"
541134cf 70#define DRV_VERSION "0.8"
1da177e4
LT
71
72#define NV_PORTS 2
73#define NV_PIO_MASK 0x1f
74#define NV_MWDMA_MASK 0x07
75#define NV_UDMA_MASK 0x7f
76#define NV_PORT0_SCR_REG_OFFSET 0x00
77#define NV_PORT1_SCR_REG_OFFSET 0x40
78
79#define NV_INT_STATUS 0x10
80#define NV_INT_STATUS_CK804 0x440
81#define NV_INT_STATUS_PDEV_INT 0x01
82#define NV_INT_STATUS_PDEV_PM 0x02
83#define NV_INT_STATUS_PDEV_ADDED 0x04
84#define NV_INT_STATUS_PDEV_REMOVED 0x08
85#define NV_INT_STATUS_SDEV_INT 0x10
86#define NV_INT_STATUS_SDEV_PM 0x20
87#define NV_INT_STATUS_SDEV_ADDED 0x40
88#define NV_INT_STATUS_SDEV_REMOVED 0x80
89#define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
90 NV_INT_STATUS_PDEV_REMOVED)
91#define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
92 NV_INT_STATUS_SDEV_REMOVED)
93#define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
94 NV_INT_STATUS_SDEV_HOTPLUG)
95
96#define NV_INT_ENABLE 0x11
97#define NV_INT_ENABLE_CK804 0x441
98#define NV_INT_ENABLE_PDEV_MASK 0x01
99#define NV_INT_ENABLE_PDEV_PM 0x02
100#define NV_INT_ENABLE_PDEV_ADDED 0x04
101#define NV_INT_ENABLE_PDEV_REMOVED 0x08
102#define NV_INT_ENABLE_SDEV_MASK 0x10
103#define NV_INT_ENABLE_SDEV_PM 0x20
104#define NV_INT_ENABLE_SDEV_ADDED 0x40
105#define NV_INT_ENABLE_SDEV_REMOVED 0x80
106#define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
107 NV_INT_ENABLE_PDEV_REMOVED)
108#define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
109 NV_INT_ENABLE_SDEV_REMOVED)
110#define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
111 NV_INT_ENABLE_SDEV_HOTPLUG)
112
113#define NV_INT_CONFIG 0x12
114#define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
115
116// For PCI config register 20
117#define NV_MCP_SATA_CFG_20 0x50
118#define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
119
120static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121static irqreturn_t nv_interrupt (int irq, void *dev_instance,
122 struct pt_regs *regs);
123static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
124static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
125static void nv_host_stop (struct ata_host_set *host_set);
126static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
127static void nv_disable_hotplug(struct ata_host_set *host_set);
128static void nv_check_hotplug(struct ata_host_set *host_set);
129static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
130static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
131static void nv_check_hotplug_ck804(struct ata_host_set *host_set);
132
133enum nv_host_type
134{
135 GENERIC,
136 NFORCE2,
137 NFORCE3,
e710245b 138 CK804
1da177e4
LT
139};
140
141static struct pci_device_id nv_pci_tbl[] = {
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
152 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
154 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
541134cf 156 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
e710245b 157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf 158 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
e710245b 159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
541134cf 160 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
e710245b 161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
e86ee668 162 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
e710245b 163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
1da177e4
LT
164 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
165 PCI_ANY_ID, PCI_ANY_ID,
166 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
541134cf
DD
167 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
168 PCI_ANY_ID, PCI_ANY_ID,
169 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
1da177e4
LT
170 { 0, } /* terminate list */
171};
172
173#define NV_HOST_FLAGS_SCR_MMIO 0x00000001
174
175struct nv_host_desc
176{
177 enum nv_host_type host_type;
178 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
179 void (*disable_hotplug)(struct ata_host_set *host_set);
180 void (*check_hotplug)(struct ata_host_set *host_set);
181
182};
183static struct nv_host_desc nv_device_tbl[] = {
184 {
185 .host_type = GENERIC,
186 .enable_hotplug = NULL,
187 .disable_hotplug= NULL,
188 .check_hotplug = NULL,
189 },
190 {
191 .host_type = NFORCE2,
192 .enable_hotplug = nv_enable_hotplug,
193 .disable_hotplug= nv_disable_hotplug,
194 .check_hotplug = nv_check_hotplug,
195 },
196 {
197 .host_type = NFORCE3,
198 .enable_hotplug = nv_enable_hotplug,
199 .disable_hotplug= nv_disable_hotplug,
200 .check_hotplug = nv_check_hotplug,
201 },
202 { .host_type = CK804,
203 .enable_hotplug = nv_enable_hotplug_ck804,
204 .disable_hotplug= nv_disable_hotplug_ck804,
205 .check_hotplug = nv_check_hotplug_ck804,
206 },
207};
208
209struct nv_host
210{
211 struct nv_host_desc *host_desc;
212 unsigned long host_flags;
213};
214
215static struct pci_driver nv_pci_driver = {
216 .name = DRV_NAME,
217 .id_table = nv_pci_tbl,
218 .probe = nv_init_one,
219 .remove = ata_pci_remove_one,
220};
221
d0be4a7d 222static struct scsi_host_template nv_sht = {
1da177e4
LT
223 .module = THIS_MODULE,
224 .name = DRV_NAME,
225 .ioctl = ata_scsi_ioctl,
226 .queuecommand = ata_scsi_queuecmd,
227 .eh_strategy_handler = ata_scsi_error,
228 .can_queue = ATA_DEF_QUEUE,
229 .this_id = ATA_SHT_THIS_ID,
230 .sg_tablesize = LIBATA_MAX_PRD,
231 .max_sectors = ATA_MAX_SECTORS,
232 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
233 .emulated = ATA_SHT_EMULATED,
234 .use_clustering = ATA_SHT_USE_CLUSTERING,
235 .proc_name = DRV_NAME,
236 .dma_boundary = ATA_DMA_BOUNDARY,
237 .slave_configure = ata_scsi_slave_config,
238 .bios_param = ata_std_bios_param,
239 .ordered_flush = 1,
240};
241
057ace5e 242static const struct ata_port_operations nv_ops = {
1da177e4
LT
243 .port_disable = ata_port_disable,
244 .tf_load = ata_tf_load,
245 .tf_read = ata_tf_read,
246 .exec_command = ata_exec_command,
247 .check_status = ata_check_status,
248 .dev_select = ata_std_dev_select,
249 .phy_reset = sata_phy_reset,
250 .bmdma_setup = ata_bmdma_setup,
251 .bmdma_start = ata_bmdma_start,
252 .bmdma_stop = ata_bmdma_stop,
253 .bmdma_status = ata_bmdma_status,
254 .qc_prep = ata_qc_prep,
255 .qc_issue = ata_qc_issue_prot,
256 .eng_timeout = ata_eng_timeout,
257 .irq_handler = nv_interrupt,
258 .irq_clear = ata_bmdma_irq_clear,
259 .scr_read = nv_scr_read,
260 .scr_write = nv_scr_write,
261 .port_start = ata_port_start,
262 .port_stop = ata_port_stop,
263 .host_stop = nv_host_stop,
264};
265
266/* FIXME: The hardware provides the necessary SATA PHY controls
267 * to support ATA_FLAG_SATA_RESET. However, it is currently
268 * necessary to disable that flag, to solve misdetection problems.
269 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
270 *
271 * This problem really needs to be investigated further. But in the
272 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
273 */
274static struct ata_port_info nv_port_info = {
275 .sht = &nv_sht,
276 .host_flags = ATA_FLAG_SATA |
277 /* ATA_FLAG_SATA_RESET | */
278 ATA_FLAG_SRST |
279 ATA_FLAG_NO_LEGACY,
280 .pio_mask = NV_PIO_MASK,
281 .mwdma_mask = NV_MWDMA_MASK,
282 .udma_mask = NV_UDMA_MASK,
283 .port_ops = &nv_ops,
284};
285
286MODULE_AUTHOR("NVIDIA");
287MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
288MODULE_LICENSE("GPL");
289MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
290MODULE_VERSION(DRV_VERSION);
291
292static irqreturn_t nv_interrupt (int irq, void *dev_instance,
293 struct pt_regs *regs)
294{
295 struct ata_host_set *host_set = dev_instance;
296 struct nv_host *host = host_set->private_data;
297 unsigned int i;
298 unsigned int handled = 0;
299 unsigned long flags;
300
301 spin_lock_irqsave(&host_set->lock, flags);
302
303 for (i = 0; i < host_set->n_ports; i++) {
304 struct ata_port *ap;
305
306 ap = host_set->ports[i];
c1389503
TH
307 if (ap &&
308 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT
309 struct ata_queued_cmd *qc;
310
311 qc = ata_qc_from_tag(ap, ap->active_tag);
312 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
313 handled += ata_host_intr(ap, qc);
314 }
315
316 }
317
318 if (host->host_desc->check_hotplug)
319 host->host_desc->check_hotplug(host_set);
320
321 spin_unlock_irqrestore(&host_set->lock, flags);
322
323 return IRQ_RETVAL(handled);
324}
325
326static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
327{
328 struct ata_host_set *host_set = ap->host_set;
329 struct nv_host *host = host_set->private_data;
330
331 if (sc_reg > SCR_CONTROL)
332 return 0xffffffffU;
333
334 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
9ee0c0a2 335 return readl((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT
336 else
337 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
338}
339
340static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
341{
342 struct ata_host_set *host_set = ap->host_set;
343 struct nv_host *host = host_set->private_data;
344
345 if (sc_reg > SCR_CONTROL)
346 return;
347
348 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
9ee0c0a2 349 writel(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT
350 else
351 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
352}
353
354static void nv_host_stop (struct ata_host_set *host_set)
355{
356 struct nv_host *host = host_set->private_data;
374b1873 357 struct pci_dev *pdev = to_pci_dev(host_set->dev);
1da177e4
LT
358
359 // Disable hotplug event interrupts.
360 if (host->host_desc->disable_hotplug)
361 host->host_desc->disable_hotplug(host_set);
362
363 kfree(host);
aa8f0dc6 364
374b1873
JG
365 if (host_set->mmio_base)
366 pci_iounmap(pdev, host_set->mmio_base);
1da177e4
LT
367}
368
369static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
370{
371 static int printed_version = 0;
372 struct nv_host *host;
373 struct ata_port_info *ppi;
374 struct ata_probe_ent *probe_ent;
375 int pci_dev_busy = 0;
376 int rc;
377 u32 bar;
378
379 // Make sure this is a SATA controller by counting the number of bars
380 // (NVIDIA SATA controllers will always have six bars). Otherwise,
381 // it's an IDE controller and we ignore it.
382 for (bar=0; bar<6; bar++)
383 if (pci_resource_start(pdev, bar) == 0)
384 return -ENODEV;
385
386 if (!printed_version++)
a9524a76 387 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT
388
389 rc = pci_enable_device(pdev);
390 if (rc)
391 goto err_out;
392
393 rc = pci_request_regions(pdev, DRV_NAME);
394 if (rc) {
395 pci_dev_busy = 1;
396 goto err_out_disable;
397 }
398
399 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
400 if (rc)
401 goto err_out_regions;
402 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
403 if (rc)
404 goto err_out_regions;
405
406 rc = -ENOMEM;
407
408 ppi = &nv_port_info;
47a86593 409 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
1da177e4
LT
410 if (!probe_ent)
411 goto err_out_regions;
412
413 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
414 if (!host)
415 goto err_out_free_ent;
416
417 memset(host, 0, sizeof(struct nv_host));
418 host->host_desc = &nv_device_tbl[ent->driver_data];
419
420 probe_ent->private_data = host;
421
422 if (pci_resource_flags(pdev, 5) & IORESOURCE_MEM)
423 host->host_flags |= NV_HOST_FLAGS_SCR_MMIO;
424
425 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) {
426 unsigned long base;
427
374b1873 428 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
1da177e4
LT
429 if (probe_ent->mmio_base == NULL) {
430 rc = -EIO;
431 goto err_out_free_host;
432 }
433
434 base = (unsigned long)probe_ent->mmio_base;
435
436 probe_ent->port[0].scr_addr =
437 base + NV_PORT0_SCR_REG_OFFSET;
438 probe_ent->port[1].scr_addr =
439 base + NV_PORT1_SCR_REG_OFFSET;
440 } else {
441
442 probe_ent->port[0].scr_addr =
443 pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
444 probe_ent->port[1].scr_addr =
445 pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
446 }
447
448 pci_set_master(pdev);
449
450 rc = ata_device_add(probe_ent);
451 if (rc != NV_PORTS)
452 goto err_out_iounmap;
453
454 // Enable hotplug event interrupts.
455 if (host->host_desc->enable_hotplug)
456 host->host_desc->enable_hotplug(probe_ent);
457
458 kfree(probe_ent);
459
460 return 0;
461
462err_out_iounmap:
463 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
374b1873 464 pci_iounmap(pdev, probe_ent->mmio_base);
1da177e4
LT
465err_out_free_host:
466 kfree(host);
467err_out_free_ent:
468 kfree(probe_ent);
469err_out_regions:
470 pci_release_regions(pdev);
471err_out_disable:
472 if (!pci_dev_busy)
473 pci_disable_device(pdev);
474err_out:
475 return rc;
476}
477
478static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
479{
480 u8 intr_mask;
481
482 outb(NV_INT_STATUS_HOTPLUG,
483 probe_ent->port[0].scr_addr + NV_INT_STATUS);
484
485 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
486 intr_mask |= NV_INT_ENABLE_HOTPLUG;
487
488 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
489}
490
491static void nv_disable_hotplug(struct ata_host_set *host_set)
492{
493 u8 intr_mask;
494
495 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
496
497 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
498
499 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
500}
501
502static void nv_check_hotplug(struct ata_host_set *host_set)
503{
504 u8 intr_status;
505
506 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
507
508 // Clear interrupt status.
509 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
510
511 if (intr_status & NV_INT_STATUS_HOTPLUG) {
512 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
513 printk(KERN_WARNING "nv_sata: "
514 "Primary device added\n");
515
516 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
517 printk(KERN_WARNING "nv_sata: "
518 "Primary device removed\n");
519
520 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
521 printk(KERN_WARNING "nv_sata: "
522 "Secondary device added\n");
523
524 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
525 printk(KERN_WARNING "nv_sata: "
526 "Secondary device removed\n");
527 }
528}
529
530static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
531{
532 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
533 u8 intr_mask;
534 u8 regval;
535
536 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
537 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
538 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
539
540 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
541
542 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
543 intr_mask |= NV_INT_ENABLE_HOTPLUG;
544
545 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
546}
547
548static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
549{
550 struct pci_dev *pdev = to_pci_dev(host_set->dev);
551 u8 intr_mask;
552 u8 regval;
553
554 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
555
556 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
557
558 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
559
560 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
561 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
562 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
563}
564
565static void nv_check_hotplug_ck804(struct ata_host_set *host_set)
566{
567 u8 intr_status;
568
569 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
570
571 // Clear interrupt status.
572 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
573
574 if (intr_status & NV_INT_STATUS_HOTPLUG) {
575 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
576 printk(KERN_WARNING "nv_sata: "
577 "Primary device added\n");
578
579 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
580 printk(KERN_WARNING "nv_sata: "
581 "Primary device removed\n");
582
583 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
584 printk(KERN_WARNING "nv_sata: "
585 "Secondary device added\n");
586
587 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
588 printk(KERN_WARNING "nv_sata: "
589 "Secondary device removed\n");
590 }
591}
592
593static int __init nv_init(void)
594{
595 return pci_module_init(&nv_pci_driver);
596}
597
598static void __exit nv_exit(void)
599{
600 pci_unregister_driver(&nv_pci_driver);
601}
602
603module_init(nv_init);
604module_exit(nv_exit);