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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
44 | #include <linux/libata.h> |
45 | #include <asm/io.h> | |
46 | #include "sata_promise.h" | |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
7bdd7208 | 49 | #define DRV_VERSION "1.03" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
54 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
55 | PDC_TBG_MODE = 0x41, /* TBG mode */ | |
56 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
57 | PDC_PCI_CTL = 0x48, /* PCI control and status register */ | |
58 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ | |
59 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
60 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
61 | PDC_SLEW_CTL = 0x470, /* slew rate control reg */ | |
62 | ||
63 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
64 | (1<<8) | (1<<9) | (1<<10), | |
65 | ||
66 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
67 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 68 | board_20619 = 2, /* FastTrak TX4000 */ |
5a46fe89 | 69 | board_20771 = 3, /* FastTrak TX2300 */ |
1da177e4 LT |
70 | |
71 | PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */ | |
72 | ||
73 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
50630195 JG |
74 | |
75 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | | |
76 | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI, | |
1da177e4 LT |
77 | }; |
78 | ||
79 | ||
80 | struct pdc_port_priv { | |
81 | u8 *pkt; | |
82 | dma_addr_t pkt_dma; | |
83 | }; | |
84 | ||
85 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
86 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
87 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
88 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
89 | static void pdc_eng_timeout(struct ata_port *ap); | |
90 | static int pdc_port_start(struct ata_port *ap); | |
91 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a JG |
92 | static void pdc_pata_phy_reset(struct ata_port *ap); |
93 | static void pdc_sata_phy_reset(struct ata_port *ap); | |
1da177e4 | 94 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
95 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
96 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
1da177e4 LT |
97 | static void pdc_irq_clear(struct ata_port *ap); |
98 | static int pdc_qc_issue_prot(struct ata_queued_cmd *qc); | |
99 | ||
374b1873 | 100 | |
193515d5 | 101 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
102 | .module = THIS_MODULE, |
103 | .name = DRV_NAME, | |
104 | .ioctl = ata_scsi_ioctl, | |
105 | .queuecommand = ata_scsi_queuecmd, | |
106 | .eh_strategy_handler = ata_scsi_error, | |
107 | .can_queue = ATA_DEF_QUEUE, | |
108 | .this_id = ATA_SHT_THIS_ID, | |
109 | .sg_tablesize = LIBATA_MAX_PRD, | |
110 | .max_sectors = ATA_MAX_SECTORS, | |
111 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
112 | .emulated = ATA_SHT_EMULATED, | |
113 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
114 | .proc_name = DRV_NAME, | |
115 | .dma_boundary = ATA_DMA_BOUNDARY, | |
116 | .slave_configure = ata_scsi_slave_config, | |
117 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
118 | }; |
119 | ||
057ace5e | 120 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
121 | .port_disable = ata_port_disable, |
122 | .tf_load = pdc_tf_load_mmio, | |
123 | .tf_read = ata_tf_read, | |
124 | .check_status = ata_check_status, | |
125 | .exec_command = pdc_exec_command_mmio, | |
126 | .dev_select = ata_std_dev_select, | |
2cba582a JG |
127 | |
128 | .phy_reset = pdc_sata_phy_reset, | |
129 | ||
1da177e4 LT |
130 | .qc_prep = pdc_qc_prep, |
131 | .qc_issue = pdc_qc_issue_prot, | |
132 | .eng_timeout = pdc_eng_timeout, | |
133 | .irq_handler = pdc_interrupt, | |
134 | .irq_clear = pdc_irq_clear, | |
2cba582a | 135 | |
1da177e4 LT |
136 | .scr_read = pdc_sata_scr_read, |
137 | .scr_write = pdc_sata_scr_write, | |
138 | .port_start = pdc_port_start, | |
139 | .port_stop = pdc_port_stop, | |
374b1873 | 140 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
141 | }; |
142 | ||
057ace5e | 143 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
144 | .port_disable = ata_port_disable, |
145 | .tf_load = pdc_tf_load_mmio, | |
146 | .tf_read = ata_tf_read, | |
147 | .check_status = ata_check_status, | |
148 | .exec_command = pdc_exec_command_mmio, | |
149 | .dev_select = ata_std_dev_select, | |
150 | ||
151 | .phy_reset = pdc_pata_phy_reset, | |
152 | ||
153 | .qc_prep = pdc_qc_prep, | |
154 | .qc_issue = pdc_qc_issue_prot, | |
155 | .eng_timeout = pdc_eng_timeout, | |
156 | .irq_handler = pdc_interrupt, | |
157 | .irq_clear = pdc_irq_clear, | |
158 | ||
159 | .port_start = pdc_port_start, | |
160 | .port_stop = pdc_port_stop, | |
374b1873 | 161 | .host_stop = ata_pci_host_stop, |
2cba582a JG |
162 | }; |
163 | ||
98ac62de | 164 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
165 | /* board_2037x */ |
166 | { | |
167 | .sht = &pdc_ata_sht, | |
50630195 | 168 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
169 | .pio_mask = 0x1f, /* pio0-4 */ |
170 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
171 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 172 | .port_ops = &pdc_sata_ops, |
1da177e4 LT |
173 | }, |
174 | ||
175 | /* board_20319 */ | |
176 | { | |
177 | .sht = &pdc_ata_sht, | |
50630195 | 178 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
179 | .pio_mask = 0x1f, /* pio0-4 */ |
180 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
181 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 182 | .port_ops = &pdc_sata_ops, |
1da177e4 | 183 | }, |
f497ba73 TL |
184 | |
185 | /* board_20619 */ | |
186 | { | |
187 | .sht = &pdc_ata_sht, | |
50630195 | 188 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
189 | .pio_mask = 0x1f, /* pio0-4 */ |
190 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
191 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 192 | .port_ops = &pdc_pata_ops, |
f497ba73 | 193 | }, |
5a46fe89 YI |
194 | |
195 | /* board_20771 */ | |
196 | { | |
197 | .sht = &pdc_ata_sht, | |
198 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, | |
199 | .pio_mask = 0x1f, /* pio0-4 */ | |
200 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
201 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
202 | .port_ops = &pdc_sata_ops, | |
203 | }, | |
1da177e4 LT |
204 | }; |
205 | ||
3b7d697d | 206 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
1da177e4 LT |
207 | { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
208 | board_2037x }, | |
07c1da23 JG |
209 | { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
210 | board_2037x }, | |
4c3a53d4 FJ |
211 | { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
212 | board_2037x }, | |
1da177e4 LT |
213 | { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
214 | board_2037x }, | |
215 | { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
216 | board_2037x }, | |
217 | { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
218 | board_2037x }, | |
219 | { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
220 | board_2037x }, | |
221 | { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
222 | board_2037x }, | |
c45154a3 EK |
223 | { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
224 | board_2037x }, | |
1da177e4 LT |
225 | |
226 | { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
227 | board_20319 }, | |
228 | { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
229 | board_20319 }, | |
93090495 DD |
230 | { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
231 | board_20319 }, | |
08b791c0 OM |
232 | { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
233 | board_20319 }, | |
1da177e4 LT |
234 | { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
235 | board_20319 }, | |
236 | ||
f497ba73 TL |
237 | { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
238 | board_20619 }, | |
239 | ||
5a46fe89 YI |
240 | { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
241 | board_20771 }, | |
1da177e4 LT |
242 | { } /* terminate list */ |
243 | }; | |
244 | ||
245 | ||
246 | static struct pci_driver pdc_ata_pci_driver = { | |
247 | .name = DRV_NAME, | |
248 | .id_table = pdc_ata_pci_tbl, | |
249 | .probe = pdc_ata_init_one, | |
250 | .remove = ata_pci_remove_one, | |
251 | }; | |
252 | ||
253 | ||
254 | static int pdc_port_start(struct ata_port *ap) | |
255 | { | |
256 | struct device *dev = ap->host_set->dev; | |
257 | struct pdc_port_priv *pp; | |
258 | int rc; | |
259 | ||
260 | rc = ata_port_start(ap); | |
261 | if (rc) | |
262 | return rc; | |
263 | ||
264 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
265 | if (!pp) { | |
266 | rc = -ENOMEM; | |
267 | goto err_out; | |
268 | } | |
269 | memset(pp, 0, sizeof(*pp)); | |
270 | ||
271 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
272 | if (!pp->pkt) { | |
273 | rc = -ENOMEM; | |
274 | goto err_out_kfree; | |
275 | } | |
276 | ||
277 | ap->private_data = pp; | |
278 | ||
279 | return 0; | |
280 | ||
281 | err_out_kfree: | |
282 | kfree(pp); | |
283 | err_out: | |
284 | ata_port_stop(ap); | |
285 | return rc; | |
286 | } | |
287 | ||
288 | ||
289 | static void pdc_port_stop(struct ata_port *ap) | |
290 | { | |
291 | struct device *dev = ap->host_set->dev; | |
292 | struct pdc_port_priv *pp = ap->private_data; | |
293 | ||
294 | ap->private_data = NULL; | |
295 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
296 | kfree(pp); | |
297 | ata_port_stop(ap); | |
298 | } | |
299 | ||
300 | ||
301 | static void pdc_reset_port(struct ata_port *ap) | |
302 | { | |
ea6ba10b | 303 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
304 | unsigned int i; |
305 | u32 tmp; | |
306 | ||
307 | for (i = 11; i > 0; i--) { | |
308 | tmp = readl(mmio); | |
309 | if (tmp & PDC_RESET) | |
310 | break; | |
311 | ||
312 | udelay(100); | |
313 | ||
314 | tmp |= PDC_RESET; | |
315 | writel(tmp, mmio); | |
316 | } | |
317 | ||
318 | tmp &= ~PDC_RESET; | |
319 | writel(tmp, mmio); | |
320 | readl(mmio); /* flush */ | |
321 | } | |
322 | ||
2cba582a | 323 | static void pdc_sata_phy_reset(struct ata_port *ap) |
1da177e4 LT |
324 | { |
325 | pdc_reset_port(ap); | |
326 | sata_phy_reset(ap); | |
327 | } | |
328 | ||
2cba582a JG |
329 | static void pdc_pata_phy_reset(struct ata_port *ap) |
330 | { | |
331 | /* FIXME: add cable detect. Don't assume 40-pin cable */ | |
332 | ap->cbl = ATA_CBL_PATA40; | |
333 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
334 | ||
335 | pdc_reset_port(ap); | |
336 | ata_port_probe(ap); | |
337 | ata_bus_reset(ap); | |
338 | } | |
339 | ||
1da177e4 LT |
340 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
341 | { | |
342 | if (sc_reg > SCR_CONTROL) | |
343 | return 0xffffffffU; | |
b181d3b0 | 344 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
345 | } |
346 | ||
347 | ||
348 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
349 | u32 val) | |
350 | { | |
351 | if (sc_reg > SCR_CONTROL) | |
352 | return; | |
b181d3b0 | 353 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
354 | } |
355 | ||
356 | static void pdc_qc_prep(struct ata_queued_cmd *qc) | |
357 | { | |
358 | struct pdc_port_priv *pp = qc->ap->private_data; | |
359 | unsigned int i; | |
360 | ||
361 | VPRINTK("ENTER\n"); | |
362 | ||
363 | switch (qc->tf.protocol) { | |
364 | case ATA_PROT_DMA: | |
365 | ata_qc_prep(qc); | |
366 | /* fall through */ | |
367 | ||
368 | case ATA_PROT_NODATA: | |
369 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
370 | qc->dev->devno, pp->pkt); | |
371 | ||
372 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
373 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
374 | else | |
375 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
376 | ||
377 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
378 | break; | |
379 | ||
380 | default: | |
381 | break; | |
382 | } | |
383 | } | |
384 | ||
385 | static void pdc_eng_timeout(struct ata_port *ap) | |
386 | { | |
b8f6153e | 387 | struct ata_host_set *host_set = ap->host_set; |
1da177e4 LT |
388 | u8 drv_stat; |
389 | struct ata_queued_cmd *qc; | |
b8f6153e | 390 | unsigned long flags; |
1da177e4 LT |
391 | |
392 | DPRINTK("ENTER\n"); | |
393 | ||
b8f6153e JG |
394 | spin_lock_irqsave(&host_set->lock, flags); |
395 | ||
1da177e4 LT |
396 | qc = ata_qc_from_tag(ap, ap->active_tag); |
397 | if (!qc) { | |
398 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
399 | ap->id); | |
400 | goto out; | |
401 | } | |
402 | ||
403 | /* hack alert! We cannot use the supplied completion | |
404 | * function from inside the ->eh_strategy_handler() thread. | |
405 | * libata is the only user of ->eh_strategy_handler() in | |
406 | * any kernel, so the default scsi_done() assumes it is | |
407 | * not being called from the SCSI EH. | |
408 | */ | |
409 | qc->scsidone = scsi_finish_command; | |
410 | ||
411 | switch (qc->tf.protocol) { | |
412 | case ATA_PROT_DMA: | |
413 | case ATA_PROT_NODATA: | |
414 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
a7dac447 | 415 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 AL |
416 | qc->err_mask |= __ac_err_mask(drv_stat); |
417 | ata_qc_complete(qc); | |
1da177e4 LT |
418 | break; |
419 | ||
420 | default: | |
421 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
422 | ||
423 | printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n", | |
424 | ap->id, qc->tf.command, drv_stat); | |
425 | ||
a22e2eb0 AL |
426 | qc->err_mask |= ac_err_mask(drv_stat); |
427 | ata_qc_complete(qc); | |
1da177e4 LT |
428 | break; |
429 | } | |
430 | ||
431 | out: | |
b8f6153e | 432 | spin_unlock_irqrestore(&host_set->lock, flags); |
1da177e4 LT |
433 | DPRINTK("EXIT\n"); |
434 | } | |
435 | ||
436 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
437 | struct ata_queued_cmd *qc) | |
438 | { | |
a22e2eb0 | 439 | unsigned int handled = 0; |
1da177e4 | 440 | u32 tmp; |
ea6ba10b | 441 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
442 | |
443 | tmp = readl(mmio); | |
444 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 445 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
446 | pdc_reset_port(ap); |
447 | } | |
448 | ||
449 | switch (qc->tf.protocol) { | |
450 | case ATA_PROT_DMA: | |
451 | case ATA_PROT_NODATA: | |
a22e2eb0 AL |
452 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
453 | ata_qc_complete(qc); | |
1da177e4 LT |
454 | handled = 1; |
455 | break; | |
456 | ||
457 | default: | |
ee500aab AL |
458 | ap->stats.idle_irq++; |
459 | break; | |
1da177e4 LT |
460 | } |
461 | ||
ee500aab | 462 | return handled; |
1da177e4 LT |
463 | } |
464 | ||
465 | static void pdc_irq_clear(struct ata_port *ap) | |
466 | { | |
467 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 468 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
469 | |
470 | readl(mmio + PDC_INT_SEQMASK); | |
471 | } | |
472 | ||
473 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
474 | { | |
475 | struct ata_host_set *host_set = dev_instance; | |
476 | struct ata_port *ap; | |
477 | u32 mask = 0; | |
478 | unsigned int i, tmp; | |
479 | unsigned int handled = 0; | |
ea6ba10b | 480 | void __iomem *mmio_base; |
1da177e4 LT |
481 | |
482 | VPRINTK("ENTER\n"); | |
483 | ||
484 | if (!host_set || !host_set->mmio_base) { | |
485 | VPRINTK("QUICK EXIT\n"); | |
486 | return IRQ_NONE; | |
487 | } | |
488 | ||
489 | mmio_base = host_set->mmio_base; | |
490 | ||
491 | /* reading should also clear interrupts */ | |
492 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
493 | ||
494 | if (mask == 0xffffffff) { | |
495 | VPRINTK("QUICK EXIT 2\n"); | |
496 | return IRQ_NONE; | |
497 | } | |
498 | mask &= 0xffff; /* only 16 tags possible */ | |
499 | if (!mask) { | |
500 | VPRINTK("QUICK EXIT 3\n"); | |
501 | return IRQ_NONE; | |
502 | } | |
503 | ||
504 | spin_lock(&host_set->lock); | |
505 | ||
506 | writel(mask, mmio_base + PDC_INT_SEQMASK); | |
507 | ||
508 | for (i = 0; i < host_set->n_ports; i++) { | |
509 | VPRINTK("port %u\n", i); | |
510 | ap = host_set->ports[i]; | |
511 | tmp = mask & (1 << (i + 1)); | |
c1389503 TH |
512 | if (tmp && ap && |
513 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
514 | struct ata_queued_cmd *qc; |
515 | ||
516 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
517 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) | |
518 | handled += pdc_host_intr(ap, qc); | |
519 | } | |
520 | } | |
521 | ||
522 | spin_unlock(&host_set->lock); | |
523 | ||
524 | VPRINTK("EXIT\n"); | |
525 | ||
526 | return IRQ_RETVAL(handled); | |
527 | } | |
528 | ||
529 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
530 | { | |
531 | struct ata_port *ap = qc->ap; | |
532 | struct pdc_port_priv *pp = ap->private_data; | |
533 | unsigned int port_no = ap->port_no; | |
534 | u8 seq = (u8) (port_no + 1); | |
535 | ||
536 | VPRINTK("ENTER, ap %p\n", ap); | |
537 | ||
538 | writel(0x00000001, ap->host_set->mmio_base + (seq * 4)); | |
539 | readl(ap->host_set->mmio_base + (seq * 4)); /* flush */ | |
540 | ||
541 | pp->pkt[2] = seq; | |
542 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
543 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
544 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
545 | } |
546 | ||
547 | static int pdc_qc_issue_prot(struct ata_queued_cmd *qc) | |
548 | { | |
549 | switch (qc->tf.protocol) { | |
550 | case ATA_PROT_DMA: | |
551 | case ATA_PROT_NODATA: | |
552 | pdc_packet_start(qc); | |
553 | return 0; | |
554 | ||
555 | case ATA_PROT_ATAPI_DMA: | |
556 | BUG(); | |
557 | break; | |
558 | ||
559 | default: | |
560 | break; | |
561 | } | |
562 | ||
563 | return ata_qc_issue_prot(qc); | |
564 | } | |
565 | ||
057ace5e | 566 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
567 | { |
568 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
569 | tf->protocol == ATA_PROT_NODATA); | |
570 | ata_tf_load(ap, tf); | |
571 | } | |
572 | ||
573 | ||
057ace5e | 574 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
575 | { |
576 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
577 | tf->protocol == ATA_PROT_NODATA); | |
578 | ata_exec_command(ap, tf); | |
579 | } | |
580 | ||
581 | ||
582 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
583 | { | |
584 | port->cmd_addr = base; | |
585 | port->data_addr = base; | |
586 | port->feature_addr = | |
587 | port->error_addr = base + 0x4; | |
588 | port->nsect_addr = base + 0x8; | |
589 | port->lbal_addr = base + 0xc; | |
590 | port->lbam_addr = base + 0x10; | |
591 | port->lbah_addr = base + 0x14; | |
592 | port->device_addr = base + 0x18; | |
593 | port->command_addr = | |
594 | port->status_addr = base + 0x1c; | |
595 | port->altstatus_addr = | |
596 | port->ctl_addr = base + 0x38; | |
597 | } | |
598 | ||
599 | ||
600 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
601 | { | |
ea6ba10b | 602 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
603 | u32 tmp; |
604 | ||
605 | /* | |
606 | * Except for the hotplug stuff, this is voodoo from the | |
607 | * Promise driver. Label this entire section | |
608 | * "TODO: figure out why we do this" | |
609 | */ | |
610 | ||
611 | /* change FIFO_SHD to 8 dwords, enable BMR_BURST */ | |
612 | tmp = readl(mmio + PDC_FLASH_CTL); | |
613 | tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */ | |
614 | writel(tmp, mmio + PDC_FLASH_CTL); | |
615 | ||
616 | /* clear plug/unplug flags for all ports */ | |
617 | tmp = readl(mmio + PDC_SATA_PLUG_CSR); | |
618 | writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR); | |
619 | ||
620 | /* mask plug/unplug ints */ | |
621 | tmp = readl(mmio + PDC_SATA_PLUG_CSR); | |
622 | writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR); | |
623 | ||
624 | /* reduce TBG clock to 133 Mhz. */ | |
625 | tmp = readl(mmio + PDC_TBG_MODE); | |
626 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
627 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
628 | writel(tmp, mmio + PDC_TBG_MODE); | |
629 | ||
630 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
631 | msleep(10); | |
632 | ||
633 | /* adjust slew rate control register. */ | |
634 | tmp = readl(mmio + PDC_SLEW_CTL); | |
635 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
636 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
637 | writel(tmp, mmio + PDC_SLEW_CTL); | |
638 | } | |
639 | ||
640 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
641 | { | |
642 | static int printed_version; | |
643 | struct ata_probe_ent *probe_ent = NULL; | |
644 | unsigned long base; | |
ea6ba10b | 645 | void __iomem *mmio_base; |
1da177e4 LT |
646 | unsigned int board_idx = (unsigned int) ent->driver_data; |
647 | int pci_dev_busy = 0; | |
648 | int rc; | |
649 | ||
650 | if (!printed_version++) | |
a9524a76 | 651 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
652 | |
653 | /* | |
654 | * If this driver happens to only be useful on Apple's K2, then | |
655 | * we should check that here as it has a normal Serverworks ID | |
656 | */ | |
657 | rc = pci_enable_device(pdev); | |
658 | if (rc) | |
659 | return rc; | |
660 | ||
661 | rc = pci_request_regions(pdev, DRV_NAME); | |
662 | if (rc) { | |
663 | pci_dev_busy = 1; | |
664 | goto err_out; | |
665 | } | |
666 | ||
667 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
668 | if (rc) | |
669 | goto err_out_regions; | |
670 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
671 | if (rc) | |
672 | goto err_out_regions; | |
673 | ||
674 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
675 | if (probe_ent == NULL) { | |
676 | rc = -ENOMEM; | |
677 | goto err_out_regions; | |
678 | } | |
679 | ||
680 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
681 | probe_ent->dev = pci_dev_to_dev(pdev); | |
682 | INIT_LIST_HEAD(&probe_ent->node); | |
683 | ||
374b1873 | 684 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
685 | if (mmio_base == NULL) { |
686 | rc = -ENOMEM; | |
687 | goto err_out_free_ent; | |
688 | } | |
689 | base = (unsigned long) mmio_base; | |
690 | ||
691 | probe_ent->sht = pdc_port_info[board_idx].sht; | |
692 | probe_ent->host_flags = pdc_port_info[board_idx].host_flags; | |
693 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | |
694 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
695 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
696 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
697 | ||
698 | probe_ent->irq = pdev->irq; | |
699 | probe_ent->irq_flags = SA_SHIRQ; | |
700 | probe_ent->mmio_base = mmio_base; | |
701 | ||
702 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
703 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
704 | ||
705 | probe_ent->port[0].scr_addr = base + 0x400; | |
706 | probe_ent->port[1].scr_addr = base + 0x500; | |
707 | ||
708 | /* notice 4-port boards */ | |
709 | switch (board_idx) { | |
710 | case board_20319: | |
711 | probe_ent->n_ports = 4; | |
712 | ||
713 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
714 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
715 | ||
716 | probe_ent->port[2].scr_addr = base + 0x600; | |
717 | probe_ent->port[3].scr_addr = base + 0x700; | |
718 | break; | |
719 | case board_2037x: | |
6c9e5eb5 | 720 | probe_ent->n_ports = 2; |
1da177e4 | 721 | break; |
5a46fe89 YI |
722 | case board_20771: |
723 | probe_ent->n_ports = 2; | |
724 | break; | |
f497ba73 TL |
725 | case board_20619: |
726 | probe_ent->n_ports = 4; | |
727 | ||
728 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
729 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
730 | ||
731 | probe_ent->port[2].scr_addr = base + 0x600; | |
732 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 733 | break; |
1da177e4 LT |
734 | default: |
735 | BUG(); | |
736 | break; | |
737 | } | |
738 | ||
739 | pci_set_master(pdev); | |
740 | ||
741 | /* initialize adapter */ | |
742 | pdc_host_init(board_idx, probe_ent); | |
743 | ||
744 | /* FIXME: check ata_device_add return value */ | |
745 | ata_device_add(probe_ent); | |
746 | kfree(probe_ent); | |
747 | ||
748 | return 0; | |
749 | ||
750 | err_out_free_ent: | |
751 | kfree(probe_ent); | |
752 | err_out_regions: | |
753 | pci_release_regions(pdev); | |
754 | err_out: | |
755 | if (!pci_dev_busy) | |
756 | pci_disable_device(pdev); | |
757 | return rc; | |
758 | } | |
759 | ||
760 | ||
761 | static int __init pdc_ata_init(void) | |
762 | { | |
763 | return pci_module_init(&pdc_ata_pci_driver); | |
764 | } | |
765 | ||
766 | ||
767 | static void __exit pdc_ata_exit(void) | |
768 | { | |
769 | pci_unregister_driver(&pdc_ata_pci_driver); | |
770 | } | |
771 | ||
772 | ||
773 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 774 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
775 | MODULE_LICENSE("GPL"); |
776 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
777 | MODULE_VERSION(DRV_VERSION); | |
778 | ||
779 | module_init(pdc_ata_init); | |
780 | module_exit(pdc_ata_exit); |