]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
44 | #include <linux/libata.h> |
45 | #include <asm/io.h> | |
46 | #include "sata_promise.h" | |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
6340f019 | 49 | #define DRV_VERSION "1.04" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
54 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
55 | PDC_TBG_MODE = 0x41, /* TBG mode */ | |
56 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
57 | PDC_PCI_CTL = 0x48, /* PCI control and status register */ | |
58 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ | |
59 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
60 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 61 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
1da177e4 LT |
62 | PDC_SLEW_CTL = 0x470, /* slew rate control reg */ |
63 | ||
64 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
65 | (1<<8) | (1<<9) | (1<<10), | |
66 | ||
67 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
68 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 69 | board_20619 = 2, /* FastTrak TX4000 */ |
5a46fe89 | 70 | board_20771 = 3, /* FastTrak TX2300 */ |
6340f019 LK |
71 | board_2057x = 4, /* SATAII150 Tx2plus */ |
72 | board_40518 = 5, /* SATAII150 Tx4 */ | |
1da177e4 | 73 | |
6340f019 | 74 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 LT |
75 | |
76 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
50630195 JG |
77 | |
78 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | | |
79 | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI, | |
1da177e4 LT |
80 | }; |
81 | ||
82 | ||
83 | struct pdc_port_priv { | |
84 | u8 *pkt; | |
85 | dma_addr_t pkt_dma; | |
86 | }; | |
87 | ||
6340f019 LK |
88 | struct pdc_host_priv { |
89 | int hotplug_offset; | |
90 | }; | |
91 | ||
1da177e4 LT |
92 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
93 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
94 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
95 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
96 | static void pdc_eng_timeout(struct ata_port *ap); | |
97 | static int pdc_port_start(struct ata_port *ap); | |
98 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a JG |
99 | static void pdc_pata_phy_reset(struct ata_port *ap); |
100 | static void pdc_sata_phy_reset(struct ata_port *ap); | |
1da177e4 | 101 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
102 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
103 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
1da177e4 | 104 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 105 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
6340f019 | 106 | static void pdc_host_stop(struct ata_host_set *host_set); |
1da177e4 | 107 | |
374b1873 | 108 | |
193515d5 | 109 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
110 | .module = THIS_MODULE, |
111 | .name = DRV_NAME, | |
112 | .ioctl = ata_scsi_ioctl, | |
113 | .queuecommand = ata_scsi_queuecmd, | |
35daeb8f | 114 | .eh_timed_out = ata_scsi_timed_out, |
1da177e4 LT |
115 | .eh_strategy_handler = ata_scsi_error, |
116 | .can_queue = ATA_DEF_QUEUE, | |
117 | .this_id = ATA_SHT_THIS_ID, | |
118 | .sg_tablesize = LIBATA_MAX_PRD, | |
119 | .max_sectors = ATA_MAX_SECTORS, | |
120 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
121 | .emulated = ATA_SHT_EMULATED, | |
122 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
123 | .proc_name = DRV_NAME, | |
124 | .dma_boundary = ATA_DMA_BOUNDARY, | |
125 | .slave_configure = ata_scsi_slave_config, | |
126 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
127 | }; |
128 | ||
057ace5e | 129 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
130 | .port_disable = ata_port_disable, |
131 | .tf_load = pdc_tf_load_mmio, | |
132 | .tf_read = ata_tf_read, | |
133 | .check_status = ata_check_status, | |
134 | .exec_command = pdc_exec_command_mmio, | |
135 | .dev_select = ata_std_dev_select, | |
2cba582a JG |
136 | |
137 | .phy_reset = pdc_sata_phy_reset, | |
138 | ||
1da177e4 LT |
139 | .qc_prep = pdc_qc_prep, |
140 | .qc_issue = pdc_qc_issue_prot, | |
141 | .eng_timeout = pdc_eng_timeout, | |
142 | .irq_handler = pdc_interrupt, | |
143 | .irq_clear = pdc_irq_clear, | |
2cba582a | 144 | |
1da177e4 LT |
145 | .scr_read = pdc_sata_scr_read, |
146 | .scr_write = pdc_sata_scr_write, | |
147 | .port_start = pdc_port_start, | |
148 | .port_stop = pdc_port_stop, | |
6340f019 | 149 | .host_stop = pdc_host_stop, |
1da177e4 LT |
150 | }; |
151 | ||
057ace5e | 152 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
153 | .port_disable = ata_port_disable, |
154 | .tf_load = pdc_tf_load_mmio, | |
155 | .tf_read = ata_tf_read, | |
156 | .check_status = ata_check_status, | |
157 | .exec_command = pdc_exec_command_mmio, | |
158 | .dev_select = ata_std_dev_select, | |
159 | ||
160 | .phy_reset = pdc_pata_phy_reset, | |
161 | ||
162 | .qc_prep = pdc_qc_prep, | |
163 | .qc_issue = pdc_qc_issue_prot, | |
164 | .eng_timeout = pdc_eng_timeout, | |
165 | .irq_handler = pdc_interrupt, | |
166 | .irq_clear = pdc_irq_clear, | |
167 | ||
168 | .port_start = pdc_port_start, | |
169 | .port_stop = pdc_port_stop, | |
6340f019 | 170 | .host_stop = pdc_host_stop, |
2cba582a JG |
171 | }; |
172 | ||
98ac62de | 173 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
174 | /* board_2037x */ |
175 | { | |
176 | .sht = &pdc_ata_sht, | |
50630195 | 177 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
178 | .pio_mask = 0x1f, /* pio0-4 */ |
179 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
180 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 181 | .port_ops = &pdc_sata_ops, |
1da177e4 LT |
182 | }, |
183 | ||
184 | /* board_20319 */ | |
185 | { | |
186 | .sht = &pdc_ata_sht, | |
50630195 | 187 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
188 | .pio_mask = 0x1f, /* pio0-4 */ |
189 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
190 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 191 | .port_ops = &pdc_sata_ops, |
1da177e4 | 192 | }, |
f497ba73 TL |
193 | |
194 | /* board_20619 */ | |
195 | { | |
196 | .sht = &pdc_ata_sht, | |
50630195 | 197 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
198 | .pio_mask = 0x1f, /* pio0-4 */ |
199 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
200 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 201 | .port_ops = &pdc_pata_ops, |
f497ba73 | 202 | }, |
5a46fe89 YI |
203 | |
204 | /* board_20771 */ | |
205 | { | |
206 | .sht = &pdc_ata_sht, | |
207 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, | |
208 | .pio_mask = 0x1f, /* pio0-4 */ | |
209 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
210 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
211 | .port_ops = &pdc_sata_ops, | |
212 | }, | |
6340f019 LK |
213 | |
214 | /* board_2057x */ | |
215 | { | |
216 | .sht = &pdc_ata_sht, | |
217 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, | |
218 | .pio_mask = 0x1f, /* pio0-4 */ | |
219 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
220 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
221 | .port_ops = &pdc_sata_ops, | |
222 | }, | |
223 | ||
224 | /* board_40518 */ | |
225 | { | |
226 | .sht = &pdc_ata_sht, | |
227 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, | |
228 | .pio_mask = 0x1f, /* pio0-4 */ | |
229 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
230 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
231 | .port_ops = &pdc_sata_ops, | |
232 | }, | |
1da177e4 LT |
233 | }; |
234 | ||
3b7d697d | 235 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
1da177e4 LT |
236 | { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
237 | board_2037x }, | |
07c1da23 JG |
238 | { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
239 | board_2037x }, | |
4c3a53d4 FJ |
240 | { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
241 | board_2037x }, | |
1da177e4 LT |
242 | { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
243 | board_2037x }, | |
244 | { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
245 | board_2037x }, | |
246 | { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
247 | board_2037x }, | |
248 | { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
6340f019 | 249 | board_2057x }, |
1da177e4 | 250 | { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
6340f019 | 251 | board_2057x }, |
c45154a3 EK |
252 | { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
253 | board_2037x }, | |
1da177e4 LT |
254 | |
255 | { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
256 | board_20319 }, | |
257 | { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
258 | board_20319 }, | |
93090495 DD |
259 | { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
260 | board_20319 }, | |
08b791c0 OM |
261 | { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
262 | board_20319 }, | |
1da177e4 | 263 | { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
6340f019 | 264 | board_40518 }, |
1da177e4 | 265 | |
f497ba73 TL |
266 | { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
267 | board_20619 }, | |
268 | ||
5a46fe89 YI |
269 | { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
270 | board_20771 }, | |
1da177e4 LT |
271 | { } /* terminate list */ |
272 | }; | |
273 | ||
274 | ||
275 | static struct pci_driver pdc_ata_pci_driver = { | |
276 | .name = DRV_NAME, | |
277 | .id_table = pdc_ata_pci_tbl, | |
278 | .probe = pdc_ata_init_one, | |
279 | .remove = ata_pci_remove_one, | |
280 | }; | |
281 | ||
282 | ||
283 | static int pdc_port_start(struct ata_port *ap) | |
284 | { | |
285 | struct device *dev = ap->host_set->dev; | |
286 | struct pdc_port_priv *pp; | |
287 | int rc; | |
288 | ||
289 | rc = ata_port_start(ap); | |
290 | if (rc) | |
291 | return rc; | |
292 | ||
6340f019 | 293 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
294 | if (!pp) { |
295 | rc = -ENOMEM; | |
296 | goto err_out; | |
297 | } | |
1da177e4 LT |
298 | |
299 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
300 | if (!pp->pkt) { | |
301 | rc = -ENOMEM; | |
302 | goto err_out_kfree; | |
303 | } | |
304 | ||
305 | ap->private_data = pp; | |
306 | ||
307 | return 0; | |
308 | ||
309 | err_out_kfree: | |
310 | kfree(pp); | |
311 | err_out: | |
312 | ata_port_stop(ap); | |
313 | return rc; | |
314 | } | |
315 | ||
316 | ||
317 | static void pdc_port_stop(struct ata_port *ap) | |
318 | { | |
319 | struct device *dev = ap->host_set->dev; | |
320 | struct pdc_port_priv *pp = ap->private_data; | |
321 | ||
322 | ap->private_data = NULL; | |
323 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
324 | kfree(pp); | |
325 | ata_port_stop(ap); | |
326 | } | |
327 | ||
328 | ||
6340f019 LK |
329 | static void pdc_host_stop(struct ata_host_set *host_set) |
330 | { | |
331 | struct pdc_host_priv *hp = host_set->private_data; | |
332 | ||
333 | ata_pci_host_stop(host_set); | |
334 | ||
335 | kfree(hp); | |
336 | } | |
337 | ||
338 | ||
1da177e4 LT |
339 | static void pdc_reset_port(struct ata_port *ap) |
340 | { | |
ea6ba10b | 341 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
342 | unsigned int i; |
343 | u32 tmp; | |
344 | ||
345 | for (i = 11; i > 0; i--) { | |
346 | tmp = readl(mmio); | |
347 | if (tmp & PDC_RESET) | |
348 | break; | |
349 | ||
350 | udelay(100); | |
351 | ||
352 | tmp |= PDC_RESET; | |
353 | writel(tmp, mmio); | |
354 | } | |
355 | ||
356 | tmp &= ~PDC_RESET; | |
357 | writel(tmp, mmio); | |
358 | readl(mmio); /* flush */ | |
359 | } | |
360 | ||
2cba582a | 361 | static void pdc_sata_phy_reset(struct ata_port *ap) |
1da177e4 LT |
362 | { |
363 | pdc_reset_port(ap); | |
364 | sata_phy_reset(ap); | |
365 | } | |
366 | ||
2cba582a JG |
367 | static void pdc_pata_phy_reset(struct ata_port *ap) |
368 | { | |
369 | /* FIXME: add cable detect. Don't assume 40-pin cable */ | |
370 | ap->cbl = ATA_CBL_PATA40; | |
371 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
372 | ||
373 | pdc_reset_port(ap); | |
374 | ata_port_probe(ap); | |
375 | ata_bus_reset(ap); | |
376 | } | |
377 | ||
1da177e4 LT |
378 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
379 | { | |
380 | if (sc_reg > SCR_CONTROL) | |
381 | return 0xffffffffU; | |
b181d3b0 | 382 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
383 | } |
384 | ||
385 | ||
386 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
387 | u32 val) | |
388 | { | |
389 | if (sc_reg > SCR_CONTROL) | |
390 | return; | |
b181d3b0 | 391 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
392 | } |
393 | ||
394 | static void pdc_qc_prep(struct ata_queued_cmd *qc) | |
395 | { | |
396 | struct pdc_port_priv *pp = qc->ap->private_data; | |
397 | unsigned int i; | |
398 | ||
399 | VPRINTK("ENTER\n"); | |
400 | ||
401 | switch (qc->tf.protocol) { | |
402 | case ATA_PROT_DMA: | |
403 | ata_qc_prep(qc); | |
404 | /* fall through */ | |
405 | ||
406 | case ATA_PROT_NODATA: | |
407 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
408 | qc->dev->devno, pp->pkt); | |
409 | ||
410 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
411 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
412 | else | |
413 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
414 | ||
415 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
416 | break; | |
417 | ||
418 | default: | |
419 | break; | |
420 | } | |
421 | } | |
422 | ||
423 | static void pdc_eng_timeout(struct ata_port *ap) | |
424 | { | |
b8f6153e | 425 | struct ata_host_set *host_set = ap->host_set; |
1da177e4 LT |
426 | u8 drv_stat; |
427 | struct ata_queued_cmd *qc; | |
b8f6153e | 428 | unsigned long flags; |
1da177e4 LT |
429 | |
430 | DPRINTK("ENTER\n"); | |
431 | ||
b8f6153e JG |
432 | spin_lock_irqsave(&host_set->lock, flags); |
433 | ||
1da177e4 LT |
434 | qc = ata_qc_from_tag(ap, ap->active_tag); |
435 | if (!qc) { | |
436 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
437 | ap->id); | |
438 | goto out; | |
439 | } | |
440 | ||
1da177e4 LT |
441 | switch (qc->tf.protocol) { |
442 | case ATA_PROT_DMA: | |
443 | case ATA_PROT_NODATA: | |
444 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
a7dac447 | 445 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 446 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
447 | break; |
448 | ||
449 | default: | |
450 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
451 | ||
452 | printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n", | |
453 | ap->id, qc->tf.command, drv_stat); | |
454 | ||
a22e2eb0 | 455 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
456 | break; |
457 | } | |
458 | ||
459 | out: | |
b8f6153e | 460 | spin_unlock_irqrestore(&host_set->lock, flags); |
a72ec4ce TH |
461 | if (qc) |
462 | ata_eh_qc_complete(qc); | |
1da177e4 LT |
463 | DPRINTK("EXIT\n"); |
464 | } | |
465 | ||
466 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
467 | struct ata_queued_cmd *qc) | |
468 | { | |
a22e2eb0 | 469 | unsigned int handled = 0; |
1da177e4 | 470 | u32 tmp; |
ea6ba10b | 471 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
472 | |
473 | tmp = readl(mmio); | |
474 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 475 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
476 | pdc_reset_port(ap); |
477 | } | |
478 | ||
479 | switch (qc->tf.protocol) { | |
480 | case ATA_PROT_DMA: | |
481 | case ATA_PROT_NODATA: | |
a22e2eb0 AL |
482 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
483 | ata_qc_complete(qc); | |
1da177e4 LT |
484 | handled = 1; |
485 | break; | |
486 | ||
487 | default: | |
ee500aab AL |
488 | ap->stats.idle_irq++; |
489 | break; | |
1da177e4 LT |
490 | } |
491 | ||
ee500aab | 492 | return handled; |
1da177e4 LT |
493 | } |
494 | ||
495 | static void pdc_irq_clear(struct ata_port *ap) | |
496 | { | |
497 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 498 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
499 | |
500 | readl(mmio + PDC_INT_SEQMASK); | |
501 | } | |
502 | ||
503 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
504 | { | |
505 | struct ata_host_set *host_set = dev_instance; | |
506 | struct ata_port *ap; | |
507 | u32 mask = 0; | |
508 | unsigned int i, tmp; | |
509 | unsigned int handled = 0; | |
ea6ba10b | 510 | void __iomem *mmio_base; |
1da177e4 LT |
511 | |
512 | VPRINTK("ENTER\n"); | |
513 | ||
514 | if (!host_set || !host_set->mmio_base) { | |
515 | VPRINTK("QUICK EXIT\n"); | |
516 | return IRQ_NONE; | |
517 | } | |
518 | ||
519 | mmio_base = host_set->mmio_base; | |
520 | ||
521 | /* reading should also clear interrupts */ | |
522 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
523 | ||
524 | if (mask == 0xffffffff) { | |
525 | VPRINTK("QUICK EXIT 2\n"); | |
526 | return IRQ_NONE; | |
527 | } | |
6340f019 LK |
528 | |
529 | spin_lock(&host_set->lock); | |
530 | ||
1da177e4 LT |
531 | mask &= 0xffff; /* only 16 tags possible */ |
532 | if (!mask) { | |
533 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 534 | goto done_irq; |
1da177e4 LT |
535 | } |
536 | ||
1da177e4 LT |
537 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
538 | ||
539 | for (i = 0; i < host_set->n_ports; i++) { | |
540 | VPRINTK("port %u\n", i); | |
541 | ap = host_set->ports[i]; | |
542 | tmp = mask & (1 << (i + 1)); | |
c1389503 TH |
543 | if (tmp && ap && |
544 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
545 | struct ata_queued_cmd *qc; |
546 | ||
547 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
548 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) | |
549 | handled += pdc_host_intr(ap, qc); | |
550 | } | |
551 | } | |
552 | ||
1da177e4 LT |
553 | VPRINTK("EXIT\n"); |
554 | ||
6340f019 LK |
555 | done_irq: |
556 | spin_unlock(&host_set->lock); | |
1da177e4 LT |
557 | return IRQ_RETVAL(handled); |
558 | } | |
559 | ||
560 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
561 | { | |
562 | struct ata_port *ap = qc->ap; | |
563 | struct pdc_port_priv *pp = ap->private_data; | |
564 | unsigned int port_no = ap->port_no; | |
565 | u8 seq = (u8) (port_no + 1); | |
566 | ||
567 | VPRINTK("ENTER, ap %p\n", ap); | |
568 | ||
569 | writel(0x00000001, ap->host_set->mmio_base + (seq * 4)); | |
570 | readl(ap->host_set->mmio_base + (seq * 4)); /* flush */ | |
571 | ||
572 | pp->pkt[2] = seq; | |
573 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
574 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
575 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
576 | } |
577 | ||
9a3d9eb0 | 578 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
579 | { |
580 | switch (qc->tf.protocol) { | |
581 | case ATA_PROT_DMA: | |
582 | case ATA_PROT_NODATA: | |
583 | pdc_packet_start(qc); | |
584 | return 0; | |
585 | ||
586 | case ATA_PROT_ATAPI_DMA: | |
587 | BUG(); | |
588 | break; | |
589 | ||
590 | default: | |
591 | break; | |
592 | } | |
593 | ||
594 | return ata_qc_issue_prot(qc); | |
595 | } | |
596 | ||
057ace5e | 597 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
598 | { |
599 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
600 | tf->protocol == ATA_PROT_NODATA); | |
601 | ata_tf_load(ap, tf); | |
602 | } | |
603 | ||
604 | ||
057ace5e | 605 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
606 | { |
607 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
608 | tf->protocol == ATA_PROT_NODATA); | |
609 | ata_exec_command(ap, tf); | |
610 | } | |
611 | ||
612 | ||
613 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
614 | { | |
615 | port->cmd_addr = base; | |
616 | port->data_addr = base; | |
617 | port->feature_addr = | |
618 | port->error_addr = base + 0x4; | |
619 | port->nsect_addr = base + 0x8; | |
620 | port->lbal_addr = base + 0xc; | |
621 | port->lbam_addr = base + 0x10; | |
622 | port->lbah_addr = base + 0x14; | |
623 | port->device_addr = base + 0x18; | |
624 | port->command_addr = | |
625 | port->status_addr = base + 0x1c; | |
626 | port->altstatus_addr = | |
627 | port->ctl_addr = base + 0x38; | |
628 | } | |
629 | ||
630 | ||
631 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
632 | { | |
ea6ba10b | 633 | void __iomem *mmio = pe->mmio_base; |
6340f019 LK |
634 | struct pdc_host_priv *hp = pe->private_data; |
635 | int hotplug_offset = hp->hotplug_offset; | |
1da177e4 LT |
636 | u32 tmp; |
637 | ||
638 | /* | |
639 | * Except for the hotplug stuff, this is voodoo from the | |
640 | * Promise driver. Label this entire section | |
641 | * "TODO: figure out why we do this" | |
642 | */ | |
643 | ||
644 | /* change FIFO_SHD to 8 dwords, enable BMR_BURST */ | |
645 | tmp = readl(mmio + PDC_FLASH_CTL); | |
646 | tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */ | |
647 | writel(tmp, mmio + PDC_FLASH_CTL); | |
648 | ||
649 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
650 | tmp = readl(mmio + hotplug_offset); |
651 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
652 | |
653 | /* mask plug/unplug ints */ | |
6340f019 LK |
654 | tmp = readl(mmio + hotplug_offset); |
655 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 LT |
656 | |
657 | /* reduce TBG clock to 133 Mhz. */ | |
658 | tmp = readl(mmio + PDC_TBG_MODE); | |
659 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
660 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
661 | writel(tmp, mmio + PDC_TBG_MODE); | |
662 | ||
663 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
664 | msleep(10); | |
665 | ||
666 | /* adjust slew rate control register. */ | |
667 | tmp = readl(mmio + PDC_SLEW_CTL); | |
668 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
669 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
670 | writel(tmp, mmio + PDC_SLEW_CTL); | |
671 | } | |
672 | ||
673 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
674 | { | |
675 | static int printed_version; | |
676 | struct ata_probe_ent *probe_ent = NULL; | |
6340f019 | 677 | struct pdc_host_priv *hp; |
1da177e4 | 678 | unsigned long base; |
ea6ba10b | 679 | void __iomem *mmio_base; |
1da177e4 LT |
680 | unsigned int board_idx = (unsigned int) ent->driver_data; |
681 | int pci_dev_busy = 0; | |
682 | int rc; | |
683 | ||
684 | if (!printed_version++) | |
a9524a76 | 685 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
686 | |
687 | /* | |
688 | * If this driver happens to only be useful on Apple's K2, then | |
689 | * we should check that here as it has a normal Serverworks ID | |
690 | */ | |
691 | rc = pci_enable_device(pdev); | |
692 | if (rc) | |
693 | return rc; | |
694 | ||
695 | rc = pci_request_regions(pdev, DRV_NAME); | |
696 | if (rc) { | |
697 | pci_dev_busy = 1; | |
698 | goto err_out; | |
699 | } | |
700 | ||
701 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
702 | if (rc) | |
703 | goto err_out_regions; | |
704 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
705 | if (rc) | |
706 | goto err_out_regions; | |
707 | ||
6340f019 | 708 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
709 | if (probe_ent == NULL) { |
710 | rc = -ENOMEM; | |
711 | goto err_out_regions; | |
712 | } | |
713 | ||
1da177e4 LT |
714 | probe_ent->dev = pci_dev_to_dev(pdev); |
715 | INIT_LIST_HEAD(&probe_ent->node); | |
716 | ||
374b1873 | 717 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
718 | if (mmio_base == NULL) { |
719 | rc = -ENOMEM; | |
720 | goto err_out_free_ent; | |
721 | } | |
722 | base = (unsigned long) mmio_base; | |
723 | ||
6340f019 LK |
724 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); |
725 | if (hp == NULL) { | |
726 | rc = -ENOMEM; | |
727 | goto err_out_free_ent; | |
728 | } | |
729 | ||
730 | /* Set default hotplug offset */ | |
731 | hp->hotplug_offset = PDC_SATA_PLUG_CSR; | |
732 | probe_ent->private_data = hp; | |
733 | ||
1da177e4 LT |
734 | probe_ent->sht = pdc_port_info[board_idx].sht; |
735 | probe_ent->host_flags = pdc_port_info[board_idx].host_flags; | |
736 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | |
737 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
738 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
739 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
740 | ||
741 | probe_ent->irq = pdev->irq; | |
742 | probe_ent->irq_flags = SA_SHIRQ; | |
743 | probe_ent->mmio_base = mmio_base; | |
744 | ||
745 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
746 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
747 | ||
748 | probe_ent->port[0].scr_addr = base + 0x400; | |
749 | probe_ent->port[1].scr_addr = base + 0x500; | |
750 | ||
751 | /* notice 4-port boards */ | |
752 | switch (board_idx) { | |
6340f019 LK |
753 | case board_40518: |
754 | /* Override hotplug offset for SATAII150 */ | |
755 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
756 | /* Fall through */ | |
1da177e4 LT |
757 | case board_20319: |
758 | probe_ent->n_ports = 4; | |
759 | ||
760 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
761 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
762 | ||
763 | probe_ent->port[2].scr_addr = base + 0x600; | |
764 | probe_ent->port[3].scr_addr = base + 0x700; | |
765 | break; | |
6340f019 LK |
766 | case board_2057x: |
767 | /* Override hotplug offset for SATAII150 */ | |
768 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
769 | /* Fall through */ | |
1da177e4 | 770 | case board_2037x: |
6c9e5eb5 | 771 | probe_ent->n_ports = 2; |
1da177e4 | 772 | break; |
5a46fe89 YI |
773 | case board_20771: |
774 | probe_ent->n_ports = 2; | |
775 | break; | |
f497ba73 TL |
776 | case board_20619: |
777 | probe_ent->n_ports = 4; | |
778 | ||
779 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
780 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
781 | ||
782 | probe_ent->port[2].scr_addr = base + 0x600; | |
783 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 784 | break; |
1da177e4 LT |
785 | default: |
786 | BUG(); | |
787 | break; | |
788 | } | |
789 | ||
790 | pci_set_master(pdev); | |
791 | ||
792 | /* initialize adapter */ | |
793 | pdc_host_init(board_idx, probe_ent); | |
794 | ||
6340f019 LK |
795 | /* FIXME: Need any other frees than hp? */ |
796 | if (!ata_device_add(probe_ent)) | |
797 | kfree(hp); | |
798 | ||
1da177e4 LT |
799 | kfree(probe_ent); |
800 | ||
801 | return 0; | |
802 | ||
803 | err_out_free_ent: | |
804 | kfree(probe_ent); | |
805 | err_out_regions: | |
806 | pci_release_regions(pdev); | |
807 | err_out: | |
808 | if (!pci_dev_busy) | |
809 | pci_disable_device(pdev); | |
810 | return rc; | |
811 | } | |
812 | ||
813 | ||
814 | static int __init pdc_ata_init(void) | |
815 | { | |
816 | return pci_module_init(&pdc_ata_pci_driver); | |
817 | } | |
818 | ||
819 | ||
820 | static void __exit pdc_ata_exit(void) | |
821 | { | |
822 | pci_unregister_driver(&pdc_ata_pci_driver); | |
823 | } | |
824 | ||
825 | ||
826 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 827 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
828 | MODULE_LICENSE("GPL"); |
829 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
830 | MODULE_VERSION(DRV_VERSION); | |
831 | ||
832 | module_init(pdc_ata_init); | |
833 | module_exit(pdc_ata_exit); |