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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 | 42 | #include <scsi/scsi_host.h> |
193515d5 | 43 | #include <scsi/scsi_cmnd.h> |
1da177e4 LT |
44 | #include <linux/libata.h> |
45 | #include <asm/io.h> | |
46 | #include "sata_promise.h" | |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
6340f019 | 49 | #define DRV_VERSION "1.04" |
1da177e4 LT |
50 | |
51 | ||
52 | enum { | |
53 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
54 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
55 | PDC_TBG_MODE = 0x41, /* TBG mode */ | |
56 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
57 | PDC_PCI_CTL = 0x48, /* PCI control and status register */ | |
58 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ | |
59 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
60 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 61 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
1da177e4 LT |
62 | PDC_SLEW_CTL = 0x470, /* slew rate control reg */ |
63 | ||
64 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
65 | (1<<8) | (1<<9) | (1<<10), | |
66 | ||
67 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
68 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 69 | board_20619 = 2, /* FastTrak TX4000 */ |
5a46fe89 | 70 | board_20771 = 3, /* FastTrak TX2300 */ |
6340f019 LK |
71 | board_2057x = 4, /* SATAII150 Tx2plus */ |
72 | board_40518 = 5, /* SATAII150 Tx4 */ | |
1da177e4 | 73 | |
6340f019 | 74 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 LT |
75 | |
76 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
50630195 JG |
77 | |
78 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | | |
3d0a59c0 JG |
79 | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | |
80 | ATA_FLAG_PIO_POLLING, | |
1da177e4 LT |
81 | }; |
82 | ||
83 | ||
84 | struct pdc_port_priv { | |
85 | u8 *pkt; | |
86 | dma_addr_t pkt_dma; | |
87 | }; | |
88 | ||
6340f019 LK |
89 | struct pdc_host_priv { |
90 | int hotplug_offset; | |
91 | }; | |
92 | ||
1da177e4 LT |
93 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); |
94 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
95 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
96 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
97 | static void pdc_eng_timeout(struct ata_port *ap); | |
98 | static int pdc_port_start(struct ata_port *ap); | |
99 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a JG |
100 | static void pdc_pata_phy_reset(struct ata_port *ap); |
101 | static void pdc_sata_phy_reset(struct ata_port *ap); | |
1da177e4 | 102 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
103 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
104 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
1da177e4 | 105 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 106 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
6340f019 | 107 | static void pdc_host_stop(struct ata_host_set *host_set); |
1da177e4 | 108 | |
374b1873 | 109 | |
193515d5 | 110 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
111 | .module = THIS_MODULE, |
112 | .name = DRV_NAME, | |
113 | .ioctl = ata_scsi_ioctl, | |
114 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
115 | .can_queue = ATA_DEF_QUEUE, |
116 | .this_id = ATA_SHT_THIS_ID, | |
117 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
118 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
119 | .emulated = ATA_SHT_EMULATED, | |
120 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
121 | .proc_name = DRV_NAME, | |
122 | .dma_boundary = ATA_DMA_BOUNDARY, | |
123 | .slave_configure = ata_scsi_slave_config, | |
124 | .bios_param = ata_std_bios_param, | |
1da177e4 LT |
125 | }; |
126 | ||
057ace5e | 127 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
128 | .port_disable = ata_port_disable, |
129 | .tf_load = pdc_tf_load_mmio, | |
130 | .tf_read = ata_tf_read, | |
131 | .check_status = ata_check_status, | |
132 | .exec_command = pdc_exec_command_mmio, | |
133 | .dev_select = ata_std_dev_select, | |
2cba582a JG |
134 | |
135 | .phy_reset = pdc_sata_phy_reset, | |
136 | ||
1da177e4 LT |
137 | .qc_prep = pdc_qc_prep, |
138 | .qc_issue = pdc_qc_issue_prot, | |
139 | .eng_timeout = pdc_eng_timeout, | |
a6b2c5d4 | 140 | .data_xfer = ata_mmio_data_xfer, |
1da177e4 LT |
141 | .irq_handler = pdc_interrupt, |
142 | .irq_clear = pdc_irq_clear, | |
2cba582a | 143 | |
1da177e4 LT |
144 | .scr_read = pdc_sata_scr_read, |
145 | .scr_write = pdc_sata_scr_write, | |
146 | .port_start = pdc_port_start, | |
147 | .port_stop = pdc_port_stop, | |
6340f019 | 148 | .host_stop = pdc_host_stop, |
1da177e4 LT |
149 | }; |
150 | ||
057ace5e | 151 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
152 | .port_disable = ata_port_disable, |
153 | .tf_load = pdc_tf_load_mmio, | |
154 | .tf_read = ata_tf_read, | |
155 | .check_status = ata_check_status, | |
156 | .exec_command = pdc_exec_command_mmio, | |
157 | .dev_select = ata_std_dev_select, | |
158 | ||
159 | .phy_reset = pdc_pata_phy_reset, | |
160 | ||
161 | .qc_prep = pdc_qc_prep, | |
162 | .qc_issue = pdc_qc_issue_prot, | |
a6b2c5d4 | 163 | .data_xfer = ata_mmio_data_xfer, |
2cba582a JG |
164 | .eng_timeout = pdc_eng_timeout, |
165 | .irq_handler = pdc_interrupt, | |
166 | .irq_clear = pdc_irq_clear, | |
167 | ||
168 | .port_start = pdc_port_start, | |
169 | .port_stop = pdc_port_stop, | |
6340f019 | 170 | .host_stop = pdc_host_stop, |
2cba582a JG |
171 | }; |
172 | ||
98ac62de | 173 | static const struct ata_port_info pdc_port_info[] = { |
1da177e4 LT |
174 | /* board_2037x */ |
175 | { | |
176 | .sht = &pdc_ata_sht, | |
50630195 | 177 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
178 | .pio_mask = 0x1f, /* pio0-4 */ |
179 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
180 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 181 | .port_ops = &pdc_sata_ops, |
1da177e4 LT |
182 | }, |
183 | ||
184 | /* board_20319 */ | |
185 | { | |
186 | .sht = &pdc_ata_sht, | |
50630195 | 187 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, |
1da177e4 LT |
188 | .pio_mask = 0x1f, /* pio0-4 */ |
189 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
190 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 191 | .port_ops = &pdc_sata_ops, |
1da177e4 | 192 | }, |
f497ba73 TL |
193 | |
194 | /* board_20619 */ | |
195 | { | |
196 | .sht = &pdc_ata_sht, | |
50630195 | 197 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, |
f497ba73 TL |
198 | .pio_mask = 0x1f, /* pio0-4 */ |
199 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
200 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 201 | .port_ops = &pdc_pata_ops, |
f497ba73 | 202 | }, |
5a46fe89 YI |
203 | |
204 | /* board_20771 */ | |
205 | { | |
206 | .sht = &pdc_ata_sht, | |
207 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, | |
208 | .pio_mask = 0x1f, /* pio0-4 */ | |
209 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
210 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
211 | .port_ops = &pdc_sata_ops, | |
212 | }, | |
6340f019 LK |
213 | |
214 | /* board_2057x */ | |
215 | { | |
216 | .sht = &pdc_ata_sht, | |
217 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, | |
218 | .pio_mask = 0x1f, /* pio0-4 */ | |
219 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
220 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
221 | .port_ops = &pdc_sata_ops, | |
222 | }, | |
223 | ||
224 | /* board_40518 */ | |
225 | { | |
226 | .sht = &pdc_ata_sht, | |
227 | .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA, | |
228 | .pio_mask = 0x1f, /* pio0-4 */ | |
229 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
230 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
231 | .port_ops = &pdc_sata_ops, | |
232 | }, | |
1da177e4 LT |
233 | }; |
234 | ||
3b7d697d | 235 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
1da177e4 LT |
236 | { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
237 | board_2037x }, | |
07c1da23 JG |
238 | { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
239 | board_2037x }, | |
4c3a53d4 FJ |
240 | { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
241 | board_2037x }, | |
1da177e4 LT |
242 | { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
243 | board_2037x }, | |
244 | { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
245 | board_2037x }, | |
246 | { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
247 | board_2037x }, | |
248 | { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
6340f019 | 249 | board_2057x }, |
1da177e4 | 250 | { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
6340f019 | 251 | board_2057x }, |
c45154a3 EK |
252 | { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
253 | board_2037x }, | |
1da177e4 LT |
254 | |
255 | { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
256 | board_20319 }, | |
257 | { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
258 | board_20319 }, | |
e1fd263c DD |
259 | { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
260 | board_20319 }, | |
93090495 DD |
261 | { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
262 | board_20319 }, | |
08b791c0 OM |
263 | { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
264 | board_20319 }, | |
1da177e4 | 265 | { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
6340f019 | 266 | board_40518 }, |
1da177e4 | 267 | |
f497ba73 TL |
268 | { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
269 | board_20619 }, | |
270 | ||
5a46fe89 YI |
271 | { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
272 | board_20771 }, | |
1da177e4 LT |
273 | { } /* terminate list */ |
274 | }; | |
275 | ||
276 | ||
277 | static struct pci_driver pdc_ata_pci_driver = { | |
278 | .name = DRV_NAME, | |
279 | .id_table = pdc_ata_pci_tbl, | |
280 | .probe = pdc_ata_init_one, | |
281 | .remove = ata_pci_remove_one, | |
282 | }; | |
283 | ||
284 | ||
285 | static int pdc_port_start(struct ata_port *ap) | |
286 | { | |
287 | struct device *dev = ap->host_set->dev; | |
288 | struct pdc_port_priv *pp; | |
289 | int rc; | |
290 | ||
291 | rc = ata_port_start(ap); | |
292 | if (rc) | |
293 | return rc; | |
294 | ||
6340f019 | 295 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
1da177e4 LT |
296 | if (!pp) { |
297 | rc = -ENOMEM; | |
298 | goto err_out; | |
299 | } | |
1da177e4 LT |
300 | |
301 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
302 | if (!pp->pkt) { | |
303 | rc = -ENOMEM; | |
304 | goto err_out_kfree; | |
305 | } | |
306 | ||
307 | ap->private_data = pp; | |
308 | ||
309 | return 0; | |
310 | ||
311 | err_out_kfree: | |
312 | kfree(pp); | |
313 | err_out: | |
314 | ata_port_stop(ap); | |
315 | return rc; | |
316 | } | |
317 | ||
318 | ||
319 | static void pdc_port_stop(struct ata_port *ap) | |
320 | { | |
321 | struct device *dev = ap->host_set->dev; | |
322 | struct pdc_port_priv *pp = ap->private_data; | |
323 | ||
324 | ap->private_data = NULL; | |
325 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
326 | kfree(pp); | |
327 | ata_port_stop(ap); | |
328 | } | |
329 | ||
330 | ||
6340f019 LK |
331 | static void pdc_host_stop(struct ata_host_set *host_set) |
332 | { | |
333 | struct pdc_host_priv *hp = host_set->private_data; | |
334 | ||
335 | ata_pci_host_stop(host_set); | |
336 | ||
337 | kfree(hp); | |
338 | } | |
339 | ||
340 | ||
1da177e4 LT |
341 | static void pdc_reset_port(struct ata_port *ap) |
342 | { | |
ea6ba10b | 343 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
344 | unsigned int i; |
345 | u32 tmp; | |
346 | ||
347 | for (i = 11; i > 0; i--) { | |
348 | tmp = readl(mmio); | |
349 | if (tmp & PDC_RESET) | |
350 | break; | |
351 | ||
352 | udelay(100); | |
353 | ||
354 | tmp |= PDC_RESET; | |
355 | writel(tmp, mmio); | |
356 | } | |
357 | ||
358 | tmp &= ~PDC_RESET; | |
359 | writel(tmp, mmio); | |
360 | readl(mmio); /* flush */ | |
361 | } | |
362 | ||
2cba582a | 363 | static void pdc_sata_phy_reset(struct ata_port *ap) |
1da177e4 LT |
364 | { |
365 | pdc_reset_port(ap); | |
366 | sata_phy_reset(ap); | |
367 | } | |
368 | ||
d3fb4e8d | 369 | static void pdc_pata_cbl_detect(struct ata_port *ap) |
2cba582a | 370 | { |
d3fb4e8d JG |
371 | u8 tmp; |
372 | void __iomem *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; | |
373 | ||
374 | tmp = readb(mmio); | |
375 | ||
376 | if (tmp & 0x01) { | |
377 | ap->cbl = ATA_CBL_PATA40; | |
378 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
379 | } else | |
380 | ap->cbl = ATA_CBL_PATA80; | |
381 | } | |
2cba582a | 382 | |
d3fb4e8d JG |
383 | static void pdc_pata_phy_reset(struct ata_port *ap) |
384 | { | |
385 | pdc_pata_cbl_detect(ap); | |
2cba582a JG |
386 | pdc_reset_port(ap); |
387 | ata_port_probe(ap); | |
388 | ata_bus_reset(ap); | |
389 | } | |
390 | ||
1da177e4 LT |
391 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
392 | { | |
393 | if (sc_reg > SCR_CONTROL) | |
394 | return 0xffffffffU; | |
b181d3b0 | 395 | return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
396 | } |
397 | ||
398 | ||
399 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
400 | u32 val) | |
401 | { | |
402 | if (sc_reg > SCR_CONTROL) | |
403 | return; | |
b181d3b0 | 404 | writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
405 | } |
406 | ||
407 | static void pdc_qc_prep(struct ata_queued_cmd *qc) | |
408 | { | |
409 | struct pdc_port_priv *pp = qc->ap->private_data; | |
410 | unsigned int i; | |
411 | ||
412 | VPRINTK("ENTER\n"); | |
413 | ||
414 | switch (qc->tf.protocol) { | |
415 | case ATA_PROT_DMA: | |
416 | ata_qc_prep(qc); | |
417 | /* fall through */ | |
418 | ||
419 | case ATA_PROT_NODATA: | |
420 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
421 | qc->dev->devno, pp->pkt); | |
422 | ||
423 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
424 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
425 | else | |
426 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
427 | ||
428 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
429 | break; | |
430 | ||
431 | default: | |
432 | break; | |
433 | } | |
434 | } | |
435 | ||
436 | static void pdc_eng_timeout(struct ata_port *ap) | |
437 | { | |
b8f6153e | 438 | struct ata_host_set *host_set = ap->host_set; |
1da177e4 LT |
439 | u8 drv_stat; |
440 | struct ata_queued_cmd *qc; | |
b8f6153e | 441 | unsigned long flags; |
1da177e4 LT |
442 | |
443 | DPRINTK("ENTER\n"); | |
444 | ||
b8f6153e JG |
445 | spin_lock_irqsave(&host_set->lock, flags); |
446 | ||
1da177e4 | 447 | qc = ata_qc_from_tag(ap, ap->active_tag); |
1da177e4 | 448 | |
1da177e4 LT |
449 | switch (qc->tf.protocol) { |
450 | case ATA_PROT_DMA: | |
451 | case ATA_PROT_NODATA: | |
f15a1daf | 452 | ata_port_printk(ap, KERN_ERR, "command timeout\n"); |
a7dac447 | 453 | drv_stat = ata_wait_idle(ap); |
a22e2eb0 | 454 | qc->err_mask |= __ac_err_mask(drv_stat); |
1da177e4 LT |
455 | break; |
456 | ||
457 | default: | |
458 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
459 | ||
f15a1daf TH |
460 | ata_port_printk(ap, KERN_ERR, |
461 | "unknown timeout, cmd 0x%x stat 0x%x\n", | |
462 | qc->tf.command, drv_stat); | |
1da177e4 | 463 | |
a22e2eb0 | 464 | qc->err_mask |= ac_err_mask(drv_stat); |
1da177e4 LT |
465 | break; |
466 | } | |
467 | ||
b8f6153e | 468 | spin_unlock_irqrestore(&host_set->lock, flags); |
f6379020 | 469 | ata_eh_qc_complete(qc); |
1da177e4 LT |
470 | DPRINTK("EXIT\n"); |
471 | } | |
472 | ||
473 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
474 | struct ata_queued_cmd *qc) | |
475 | { | |
a22e2eb0 | 476 | unsigned int handled = 0; |
1da177e4 | 477 | u32 tmp; |
ea6ba10b | 478 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
479 | |
480 | tmp = readl(mmio); | |
481 | if (tmp & PDC_ERR_MASK) { | |
a22e2eb0 | 482 | qc->err_mask |= AC_ERR_DEV; |
1da177e4 LT |
483 | pdc_reset_port(ap); |
484 | } | |
485 | ||
486 | switch (qc->tf.protocol) { | |
487 | case ATA_PROT_DMA: | |
488 | case ATA_PROT_NODATA: | |
a22e2eb0 AL |
489 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
490 | ata_qc_complete(qc); | |
1da177e4 LT |
491 | handled = 1; |
492 | break; | |
493 | ||
494 | default: | |
ee500aab AL |
495 | ap->stats.idle_irq++; |
496 | break; | |
1da177e4 LT |
497 | } |
498 | ||
ee500aab | 499 | return handled; |
1da177e4 LT |
500 | } |
501 | ||
502 | static void pdc_irq_clear(struct ata_port *ap) | |
503 | { | |
504 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 505 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
506 | |
507 | readl(mmio + PDC_INT_SEQMASK); | |
508 | } | |
509 | ||
510 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
511 | { | |
512 | struct ata_host_set *host_set = dev_instance; | |
513 | struct ata_port *ap; | |
514 | u32 mask = 0; | |
515 | unsigned int i, tmp; | |
516 | unsigned int handled = 0; | |
ea6ba10b | 517 | void __iomem *mmio_base; |
1da177e4 LT |
518 | |
519 | VPRINTK("ENTER\n"); | |
520 | ||
521 | if (!host_set || !host_set->mmio_base) { | |
522 | VPRINTK("QUICK EXIT\n"); | |
523 | return IRQ_NONE; | |
524 | } | |
525 | ||
526 | mmio_base = host_set->mmio_base; | |
527 | ||
528 | /* reading should also clear interrupts */ | |
529 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
530 | ||
531 | if (mask == 0xffffffff) { | |
532 | VPRINTK("QUICK EXIT 2\n"); | |
533 | return IRQ_NONE; | |
534 | } | |
6340f019 LK |
535 | |
536 | spin_lock(&host_set->lock); | |
537 | ||
1da177e4 LT |
538 | mask &= 0xffff; /* only 16 tags possible */ |
539 | if (!mask) { | |
540 | VPRINTK("QUICK EXIT 3\n"); | |
6340f019 | 541 | goto done_irq; |
1da177e4 LT |
542 | } |
543 | ||
1da177e4 LT |
544 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
545 | ||
546 | for (i = 0; i < host_set->n_ports; i++) { | |
547 | VPRINTK("port %u\n", i); | |
548 | ap = host_set->ports[i]; | |
549 | tmp = mask & (1 << (i + 1)); | |
c1389503 | 550 | if (tmp && ap && |
029f5468 | 551 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
552 | struct ata_queued_cmd *qc; |
553 | ||
554 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 555 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
556 | handled += pdc_host_intr(ap, qc); |
557 | } | |
558 | } | |
559 | ||
1da177e4 LT |
560 | VPRINTK("EXIT\n"); |
561 | ||
6340f019 LK |
562 | done_irq: |
563 | spin_unlock(&host_set->lock); | |
1da177e4 LT |
564 | return IRQ_RETVAL(handled); |
565 | } | |
566 | ||
567 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
568 | { | |
569 | struct ata_port *ap = qc->ap; | |
570 | struct pdc_port_priv *pp = ap->private_data; | |
571 | unsigned int port_no = ap->port_no; | |
572 | u8 seq = (u8) (port_no + 1); | |
573 | ||
574 | VPRINTK("ENTER, ap %p\n", ap); | |
575 | ||
576 | writel(0x00000001, ap->host_set->mmio_base + (seq * 4)); | |
577 | readl(ap->host_set->mmio_base + (seq * 4)); /* flush */ | |
578 | ||
579 | pp->pkt[2] = seq; | |
580 | wmb(); /* flush PRD, pkt writes */ | |
b181d3b0 AV |
581 | writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
582 | readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
583 | } |
584 | ||
9a3d9eb0 | 585 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
586 | { |
587 | switch (qc->tf.protocol) { | |
588 | case ATA_PROT_DMA: | |
589 | case ATA_PROT_NODATA: | |
590 | pdc_packet_start(qc); | |
591 | return 0; | |
592 | ||
593 | case ATA_PROT_ATAPI_DMA: | |
594 | BUG(); | |
595 | break; | |
596 | ||
597 | default: | |
598 | break; | |
599 | } | |
600 | ||
601 | return ata_qc_issue_prot(qc); | |
602 | } | |
603 | ||
057ace5e | 604 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
605 | { |
606 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
607 | tf->protocol == ATA_PROT_NODATA); | |
608 | ata_tf_load(ap, tf); | |
609 | } | |
610 | ||
611 | ||
057ace5e | 612 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 LT |
613 | { |
614 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
615 | tf->protocol == ATA_PROT_NODATA); | |
616 | ata_exec_command(ap, tf); | |
617 | } | |
618 | ||
619 | ||
620 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
621 | { | |
622 | port->cmd_addr = base; | |
623 | port->data_addr = base; | |
624 | port->feature_addr = | |
625 | port->error_addr = base + 0x4; | |
626 | port->nsect_addr = base + 0x8; | |
627 | port->lbal_addr = base + 0xc; | |
628 | port->lbam_addr = base + 0x10; | |
629 | port->lbah_addr = base + 0x14; | |
630 | port->device_addr = base + 0x18; | |
631 | port->command_addr = | |
632 | port->status_addr = base + 0x1c; | |
633 | port->altstatus_addr = | |
634 | port->ctl_addr = base + 0x38; | |
635 | } | |
636 | ||
637 | ||
638 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
639 | { | |
ea6ba10b | 640 | void __iomem *mmio = pe->mmio_base; |
6340f019 LK |
641 | struct pdc_host_priv *hp = pe->private_data; |
642 | int hotplug_offset = hp->hotplug_offset; | |
1da177e4 LT |
643 | u32 tmp; |
644 | ||
645 | /* | |
646 | * Except for the hotplug stuff, this is voodoo from the | |
647 | * Promise driver. Label this entire section | |
648 | * "TODO: figure out why we do this" | |
649 | */ | |
650 | ||
651 | /* change FIFO_SHD to 8 dwords, enable BMR_BURST */ | |
652 | tmp = readl(mmio + PDC_FLASH_CTL); | |
653 | tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */ | |
654 | writel(tmp, mmio + PDC_FLASH_CTL); | |
655 | ||
656 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
657 | tmp = readl(mmio + hotplug_offset); |
658 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 LT |
659 | |
660 | /* mask plug/unplug ints */ | |
6340f019 LK |
661 | tmp = readl(mmio + hotplug_offset); |
662 | writel(tmp | 0xff0000, mmio + hotplug_offset); | |
1da177e4 LT |
663 | |
664 | /* reduce TBG clock to 133 Mhz. */ | |
665 | tmp = readl(mmio + PDC_TBG_MODE); | |
666 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
667 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
668 | writel(tmp, mmio + PDC_TBG_MODE); | |
669 | ||
670 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
671 | msleep(10); | |
672 | ||
673 | /* adjust slew rate control register. */ | |
674 | tmp = readl(mmio + PDC_SLEW_CTL); | |
675 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
676 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
677 | writel(tmp, mmio + PDC_SLEW_CTL); | |
678 | } | |
679 | ||
680 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
681 | { | |
682 | static int printed_version; | |
683 | struct ata_probe_ent *probe_ent = NULL; | |
6340f019 | 684 | struct pdc_host_priv *hp; |
1da177e4 | 685 | unsigned long base; |
ea6ba10b | 686 | void __iomem *mmio_base; |
1da177e4 LT |
687 | unsigned int board_idx = (unsigned int) ent->driver_data; |
688 | int pci_dev_busy = 0; | |
689 | int rc; | |
690 | ||
691 | if (!printed_version++) | |
a9524a76 | 692 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 693 | |
1da177e4 LT |
694 | rc = pci_enable_device(pdev); |
695 | if (rc) | |
696 | return rc; | |
697 | ||
698 | rc = pci_request_regions(pdev, DRV_NAME); | |
699 | if (rc) { | |
700 | pci_dev_busy = 1; | |
701 | goto err_out; | |
702 | } | |
703 | ||
704 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
705 | if (rc) | |
706 | goto err_out_regions; | |
707 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
708 | if (rc) | |
709 | goto err_out_regions; | |
710 | ||
6340f019 | 711 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
712 | if (probe_ent == NULL) { |
713 | rc = -ENOMEM; | |
714 | goto err_out_regions; | |
715 | } | |
716 | ||
1da177e4 LT |
717 | probe_ent->dev = pci_dev_to_dev(pdev); |
718 | INIT_LIST_HEAD(&probe_ent->node); | |
719 | ||
374b1873 | 720 | mmio_base = pci_iomap(pdev, 3, 0); |
1da177e4 LT |
721 | if (mmio_base == NULL) { |
722 | rc = -ENOMEM; | |
723 | goto err_out_free_ent; | |
724 | } | |
725 | base = (unsigned long) mmio_base; | |
726 | ||
6340f019 LK |
727 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); |
728 | if (hp == NULL) { | |
729 | rc = -ENOMEM; | |
730 | goto err_out_free_ent; | |
731 | } | |
732 | ||
733 | /* Set default hotplug offset */ | |
734 | hp->hotplug_offset = PDC_SATA_PLUG_CSR; | |
735 | probe_ent->private_data = hp; | |
736 | ||
1da177e4 LT |
737 | probe_ent->sht = pdc_port_info[board_idx].sht; |
738 | probe_ent->host_flags = pdc_port_info[board_idx].host_flags; | |
739 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | |
740 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
741 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
742 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
743 | ||
744 | probe_ent->irq = pdev->irq; | |
745 | probe_ent->irq_flags = SA_SHIRQ; | |
746 | probe_ent->mmio_base = mmio_base; | |
747 | ||
748 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
749 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
750 | ||
751 | probe_ent->port[0].scr_addr = base + 0x400; | |
752 | probe_ent->port[1].scr_addr = base + 0x500; | |
753 | ||
754 | /* notice 4-port boards */ | |
755 | switch (board_idx) { | |
6340f019 LK |
756 | case board_40518: |
757 | /* Override hotplug offset for SATAII150 */ | |
758 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
759 | /* Fall through */ | |
1da177e4 LT |
760 | case board_20319: |
761 | probe_ent->n_ports = 4; | |
762 | ||
763 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
764 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
765 | ||
766 | probe_ent->port[2].scr_addr = base + 0x600; | |
767 | probe_ent->port[3].scr_addr = base + 0x700; | |
768 | break; | |
6340f019 LK |
769 | case board_2057x: |
770 | /* Override hotplug offset for SATAII150 */ | |
771 | hp->hotplug_offset = PDC2_SATA_PLUG_CSR; | |
772 | /* Fall through */ | |
1da177e4 | 773 | case board_2037x: |
6c9e5eb5 | 774 | probe_ent->n_ports = 2; |
1da177e4 | 775 | break; |
5a46fe89 YI |
776 | case board_20771: |
777 | probe_ent->n_ports = 2; | |
778 | break; | |
f497ba73 TL |
779 | case board_20619: |
780 | probe_ent->n_ports = 4; | |
781 | ||
782 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
783 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
784 | ||
785 | probe_ent->port[2].scr_addr = base + 0x600; | |
786 | probe_ent->port[3].scr_addr = base + 0x700; | |
6c9e5eb5 | 787 | break; |
1da177e4 LT |
788 | default: |
789 | BUG(); | |
790 | break; | |
791 | } | |
792 | ||
793 | pci_set_master(pdev); | |
794 | ||
795 | /* initialize adapter */ | |
796 | pdc_host_init(board_idx, probe_ent); | |
797 | ||
6340f019 LK |
798 | /* FIXME: Need any other frees than hp? */ |
799 | if (!ata_device_add(probe_ent)) | |
800 | kfree(hp); | |
801 | ||
1da177e4 LT |
802 | kfree(probe_ent); |
803 | ||
804 | return 0; | |
805 | ||
806 | err_out_free_ent: | |
807 | kfree(probe_ent); | |
808 | err_out_regions: | |
809 | pci_release_regions(pdev); | |
810 | err_out: | |
811 | if (!pci_dev_busy) | |
812 | pci_disable_device(pdev); | |
813 | return rc; | |
814 | } | |
815 | ||
816 | ||
817 | static int __init pdc_ata_init(void) | |
818 | { | |
819 | return pci_module_init(&pdc_ata_pci_driver); | |
820 | } | |
821 | ||
822 | ||
823 | static void __exit pdc_ata_exit(void) | |
824 | { | |
825 | pci_unregister_driver(&pdc_ata_pci_driver); | |
826 | } | |
827 | ||
828 | ||
829 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 830 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
831 | MODULE_LICENSE("GPL"); |
832 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
833 | MODULE_VERSION(DRV_VERSION); | |
834 | ||
835 | module_init(pdc_ata_init); | |
836 | module_exit(pdc_ata_exit); |