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1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2003-2004 Red Hat, Inc. | |
9 | * | |
1da177e4 | 10 | * |
af36d7f0 JG |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware information only available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
41 | #include "scsi.h" | |
42 | #include <scsi/scsi_host.h> | |
43 | #include <linux/libata.h> | |
44 | #include <asm/io.h> | |
45 | #include "sata_promise.h" | |
46 | ||
47 | #define DRV_NAME "sata_promise" | |
6885433c | 48 | #define DRV_VERSION "1.02" |
1da177e4 LT |
49 | |
50 | ||
51 | enum { | |
52 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ | |
53 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
54 | PDC_TBG_MODE = 0x41, /* TBG mode */ | |
55 | PDC_FLASH_CTL = 0x44, /* Flash control register */ | |
56 | PDC_PCI_CTL = 0x48, /* PCI control and status register */ | |
57 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ | |
58 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
59 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
60 | PDC_SLEW_CTL = 0x470, /* slew rate control reg */ | |
61 | ||
62 | PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) | | |
63 | (1<<8) | (1<<9) | (1<<10), | |
64 | ||
65 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
66 | board_20319 = 1, /* FastTrak S150 TX4 */ | |
f497ba73 | 67 | board_20619 = 2, /* FastTrak TX4000 */ |
1da177e4 LT |
68 | |
69 | PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */ | |
70 | ||
71 | PDC_RESET = (1 << 11), /* HDMA reset */ | |
72 | }; | |
73 | ||
74 | ||
75 | struct pdc_port_priv { | |
76 | u8 *pkt; | |
77 | dma_addr_t pkt_dma; | |
78 | }; | |
79 | ||
80 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
81 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
82 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
83 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs); | |
84 | static void pdc_eng_timeout(struct ata_port *ap); | |
85 | static int pdc_port_start(struct ata_port *ap); | |
86 | static void pdc_port_stop(struct ata_port *ap); | |
2cba582a JG |
87 | static void pdc_pata_phy_reset(struct ata_port *ap); |
88 | static void pdc_sata_phy_reset(struct ata_port *ap); | |
1da177e4 LT |
89 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
90 | static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf); | |
91 | static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf); | |
92 | static void pdc_irq_clear(struct ata_port *ap); | |
93 | static int pdc_qc_issue_prot(struct ata_queued_cmd *qc); | |
94 | ||
95 | static Scsi_Host_Template pdc_ata_sht = { | |
96 | .module = THIS_MODULE, | |
97 | .name = DRV_NAME, | |
98 | .ioctl = ata_scsi_ioctl, | |
99 | .queuecommand = ata_scsi_queuecmd, | |
100 | .eh_strategy_handler = ata_scsi_error, | |
101 | .can_queue = ATA_DEF_QUEUE, | |
102 | .this_id = ATA_SHT_THIS_ID, | |
103 | .sg_tablesize = LIBATA_MAX_PRD, | |
104 | .max_sectors = ATA_MAX_SECTORS, | |
105 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
106 | .emulated = ATA_SHT_EMULATED, | |
107 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
108 | .proc_name = DRV_NAME, | |
109 | .dma_boundary = ATA_DMA_BOUNDARY, | |
110 | .slave_configure = ata_scsi_slave_config, | |
111 | .bios_param = ata_std_bios_param, | |
112 | .ordered_flush = 1, | |
113 | }; | |
114 | ||
2cba582a | 115 | static struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
116 | .port_disable = ata_port_disable, |
117 | .tf_load = pdc_tf_load_mmio, | |
118 | .tf_read = ata_tf_read, | |
119 | .check_status = ata_check_status, | |
120 | .exec_command = pdc_exec_command_mmio, | |
121 | .dev_select = ata_std_dev_select, | |
2cba582a JG |
122 | |
123 | .phy_reset = pdc_sata_phy_reset, | |
124 | ||
1da177e4 LT |
125 | .qc_prep = pdc_qc_prep, |
126 | .qc_issue = pdc_qc_issue_prot, | |
127 | .eng_timeout = pdc_eng_timeout, | |
128 | .irq_handler = pdc_interrupt, | |
129 | .irq_clear = pdc_irq_clear, | |
2cba582a | 130 | |
1da177e4 LT |
131 | .scr_read = pdc_sata_scr_read, |
132 | .scr_write = pdc_sata_scr_write, | |
133 | .port_start = pdc_port_start, | |
134 | .port_stop = pdc_port_stop, | |
aa8f0dc6 | 135 | .host_stop = ata_host_stop, |
1da177e4 LT |
136 | }; |
137 | ||
2cba582a JG |
138 | static struct ata_port_operations pdc_pata_ops = { |
139 | .port_disable = ata_port_disable, | |
140 | .tf_load = pdc_tf_load_mmio, | |
141 | .tf_read = ata_tf_read, | |
142 | .check_status = ata_check_status, | |
143 | .exec_command = pdc_exec_command_mmio, | |
144 | .dev_select = ata_std_dev_select, | |
145 | ||
146 | .phy_reset = pdc_pata_phy_reset, | |
147 | ||
148 | .qc_prep = pdc_qc_prep, | |
149 | .qc_issue = pdc_qc_issue_prot, | |
150 | .eng_timeout = pdc_eng_timeout, | |
151 | .irq_handler = pdc_interrupt, | |
152 | .irq_clear = pdc_irq_clear, | |
153 | ||
154 | .port_start = pdc_port_start, | |
155 | .port_stop = pdc_port_stop, | |
156 | .host_stop = ata_host_stop, | |
157 | }; | |
158 | ||
1da177e4 LT |
159 | static struct ata_port_info pdc_port_info[] = { |
160 | /* board_2037x */ | |
161 | { | |
162 | .sht = &pdc_ata_sht, | |
163 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
164 | ATA_FLAG_SRST | ATA_FLAG_MMIO, | |
165 | .pio_mask = 0x1f, /* pio0-4 */ | |
166 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
167 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 168 | .port_ops = &pdc_sata_ops, |
1da177e4 LT |
169 | }, |
170 | ||
171 | /* board_20319 */ | |
172 | { | |
173 | .sht = &pdc_ata_sht, | |
174 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
175 | ATA_FLAG_SRST | ATA_FLAG_MMIO, | |
176 | .pio_mask = 0x1f, /* pio0-4 */ | |
177 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
178 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 179 | .port_ops = &pdc_sata_ops, |
1da177e4 | 180 | }, |
f497ba73 TL |
181 | |
182 | /* board_20619 */ | |
183 | { | |
184 | .sht = &pdc_ata_sht, | |
185 | .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST | | |
186 | ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS, | |
187 | .pio_mask = 0x1f, /* pio0-4 */ | |
188 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
189 | .udma_mask = 0x7f, /* udma0-6 ; FIXME */ | |
2cba582a | 190 | .port_ops = &pdc_pata_ops, |
f497ba73 | 191 | }, |
1da177e4 LT |
192 | }; |
193 | ||
194 | static struct pci_device_id pdc_ata_pci_tbl[] = { | |
195 | { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
196 | board_2037x }, | |
4c3a53d4 FJ |
197 | { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
198 | board_2037x }, | |
1da177e4 LT |
199 | { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
200 | board_2037x }, | |
201 | { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
202 | board_2037x }, | |
203 | { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
204 | board_2037x }, | |
205 | { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
206 | board_2037x }, | |
207 | { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
208 | board_2037x }, | |
209 | ||
210 | { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
211 | board_20319 }, | |
212 | { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
213 | board_20319 }, | |
93090495 DD |
214 | { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
215 | board_20319 }, | |
08b791c0 OM |
216 | { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
217 | board_20319 }, | |
1da177e4 LT |
218 | { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
219 | board_20319 }, | |
220 | ||
f497ba73 TL |
221 | { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
222 | board_20619 }, | |
223 | ||
1da177e4 LT |
224 | { } /* terminate list */ |
225 | }; | |
226 | ||
227 | ||
228 | static struct pci_driver pdc_ata_pci_driver = { | |
229 | .name = DRV_NAME, | |
230 | .id_table = pdc_ata_pci_tbl, | |
231 | .probe = pdc_ata_init_one, | |
232 | .remove = ata_pci_remove_one, | |
233 | }; | |
234 | ||
235 | ||
236 | static int pdc_port_start(struct ata_port *ap) | |
237 | { | |
238 | struct device *dev = ap->host_set->dev; | |
239 | struct pdc_port_priv *pp; | |
240 | int rc; | |
241 | ||
242 | rc = ata_port_start(ap); | |
243 | if (rc) | |
244 | return rc; | |
245 | ||
246 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
247 | if (!pp) { | |
248 | rc = -ENOMEM; | |
249 | goto err_out; | |
250 | } | |
251 | memset(pp, 0, sizeof(*pp)); | |
252 | ||
253 | pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); | |
254 | if (!pp->pkt) { | |
255 | rc = -ENOMEM; | |
256 | goto err_out_kfree; | |
257 | } | |
258 | ||
259 | ap->private_data = pp; | |
260 | ||
261 | return 0; | |
262 | ||
263 | err_out_kfree: | |
264 | kfree(pp); | |
265 | err_out: | |
266 | ata_port_stop(ap); | |
267 | return rc; | |
268 | } | |
269 | ||
270 | ||
271 | static void pdc_port_stop(struct ata_port *ap) | |
272 | { | |
273 | struct device *dev = ap->host_set->dev; | |
274 | struct pdc_port_priv *pp = ap->private_data; | |
275 | ||
276 | ap->private_data = NULL; | |
277 | dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma); | |
278 | kfree(pp); | |
279 | ata_port_stop(ap); | |
280 | } | |
281 | ||
282 | ||
283 | static void pdc_reset_port(struct ata_port *ap) | |
284 | { | |
ea6ba10b | 285 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
286 | unsigned int i; |
287 | u32 tmp; | |
288 | ||
289 | for (i = 11; i > 0; i--) { | |
290 | tmp = readl(mmio); | |
291 | if (tmp & PDC_RESET) | |
292 | break; | |
293 | ||
294 | udelay(100); | |
295 | ||
296 | tmp |= PDC_RESET; | |
297 | writel(tmp, mmio); | |
298 | } | |
299 | ||
300 | tmp &= ~PDC_RESET; | |
301 | writel(tmp, mmio); | |
302 | readl(mmio); /* flush */ | |
303 | } | |
304 | ||
2cba582a | 305 | static void pdc_sata_phy_reset(struct ata_port *ap) |
1da177e4 LT |
306 | { |
307 | pdc_reset_port(ap); | |
308 | sata_phy_reset(ap); | |
309 | } | |
310 | ||
2cba582a JG |
311 | static void pdc_pata_phy_reset(struct ata_port *ap) |
312 | { | |
313 | /* FIXME: add cable detect. Don't assume 40-pin cable */ | |
314 | ap->cbl = ATA_CBL_PATA40; | |
315 | ap->udma_mask &= ATA_UDMA_MASK_40C; | |
316 | ||
317 | pdc_reset_port(ap); | |
318 | ata_port_probe(ap); | |
319 | ata_bus_reset(ap); | |
320 | } | |
321 | ||
1da177e4 LT |
322 | static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
323 | { | |
324 | if (sc_reg > SCR_CONTROL) | |
325 | return 0xffffffffU; | |
326 | return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4)); | |
327 | } | |
328 | ||
329 | ||
330 | static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, | |
331 | u32 val) | |
332 | { | |
333 | if (sc_reg > SCR_CONTROL) | |
334 | return; | |
335 | writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4)); | |
336 | } | |
337 | ||
338 | static void pdc_qc_prep(struct ata_queued_cmd *qc) | |
339 | { | |
340 | struct pdc_port_priv *pp = qc->ap->private_data; | |
341 | unsigned int i; | |
342 | ||
343 | VPRINTK("ENTER\n"); | |
344 | ||
345 | switch (qc->tf.protocol) { | |
346 | case ATA_PROT_DMA: | |
347 | ata_qc_prep(qc); | |
348 | /* fall through */ | |
349 | ||
350 | case ATA_PROT_NODATA: | |
351 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
352 | qc->dev->devno, pp->pkt); | |
353 | ||
354 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
355 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
356 | else | |
357 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
358 | ||
359 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
360 | break; | |
361 | ||
362 | default: | |
363 | break; | |
364 | } | |
365 | } | |
366 | ||
367 | static void pdc_eng_timeout(struct ata_port *ap) | |
368 | { | |
b8f6153e | 369 | struct ata_host_set *host_set = ap->host_set; |
1da177e4 LT |
370 | u8 drv_stat; |
371 | struct ata_queued_cmd *qc; | |
b8f6153e | 372 | unsigned long flags; |
1da177e4 LT |
373 | |
374 | DPRINTK("ENTER\n"); | |
375 | ||
b8f6153e JG |
376 | spin_lock_irqsave(&host_set->lock, flags); |
377 | ||
1da177e4 LT |
378 | qc = ata_qc_from_tag(ap, ap->active_tag); |
379 | if (!qc) { | |
380 | printk(KERN_ERR "ata%u: BUG: timeout without command\n", | |
381 | ap->id); | |
382 | goto out; | |
383 | } | |
384 | ||
385 | /* hack alert! We cannot use the supplied completion | |
386 | * function from inside the ->eh_strategy_handler() thread. | |
387 | * libata is the only user of ->eh_strategy_handler() in | |
388 | * any kernel, so the default scsi_done() assumes it is | |
389 | * not being called from the SCSI EH. | |
390 | */ | |
391 | qc->scsidone = scsi_finish_command; | |
392 | ||
393 | switch (qc->tf.protocol) { | |
394 | case ATA_PROT_DMA: | |
395 | case ATA_PROT_NODATA: | |
396 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
397 | ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR); | |
398 | break; | |
399 | ||
400 | default: | |
401 | drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); | |
402 | ||
403 | printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n", | |
404 | ap->id, qc->tf.command, drv_stat); | |
405 | ||
406 | ata_qc_complete(qc, drv_stat); | |
407 | break; | |
408 | } | |
409 | ||
410 | out: | |
b8f6153e | 411 | spin_unlock_irqrestore(&host_set->lock, flags); |
1da177e4 LT |
412 | DPRINTK("EXIT\n"); |
413 | } | |
414 | ||
415 | static inline unsigned int pdc_host_intr( struct ata_port *ap, | |
416 | struct ata_queued_cmd *qc) | |
417 | { | |
418 | u8 status; | |
419 | unsigned int handled = 0, have_err = 0; | |
420 | u32 tmp; | |
ea6ba10b | 421 | void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL; |
1da177e4 LT |
422 | |
423 | tmp = readl(mmio); | |
424 | if (tmp & PDC_ERR_MASK) { | |
425 | have_err = 1; | |
426 | pdc_reset_port(ap); | |
427 | } | |
428 | ||
429 | switch (qc->tf.protocol) { | |
430 | case ATA_PROT_DMA: | |
431 | case ATA_PROT_NODATA: | |
432 | status = ata_wait_idle(ap); | |
433 | if (have_err) | |
434 | status |= ATA_ERR; | |
435 | ata_qc_complete(qc, status); | |
436 | handled = 1; | |
437 | break; | |
438 | ||
439 | default: | |
440 | ap->stats.idle_irq++; | |
441 | break; | |
442 | } | |
443 | ||
444 | return handled; | |
445 | } | |
446 | ||
447 | static void pdc_irq_clear(struct ata_port *ap) | |
448 | { | |
449 | struct ata_host_set *host_set = ap->host_set; | |
ea6ba10b | 450 | void __iomem *mmio = host_set->mmio_base; |
1da177e4 LT |
451 | |
452 | readl(mmio + PDC_INT_SEQMASK); | |
453 | } | |
454 | ||
455 | static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs) | |
456 | { | |
457 | struct ata_host_set *host_set = dev_instance; | |
458 | struct ata_port *ap; | |
459 | u32 mask = 0; | |
460 | unsigned int i, tmp; | |
461 | unsigned int handled = 0; | |
ea6ba10b | 462 | void __iomem *mmio_base; |
1da177e4 LT |
463 | |
464 | VPRINTK("ENTER\n"); | |
465 | ||
466 | if (!host_set || !host_set->mmio_base) { | |
467 | VPRINTK("QUICK EXIT\n"); | |
468 | return IRQ_NONE; | |
469 | } | |
470 | ||
471 | mmio_base = host_set->mmio_base; | |
472 | ||
473 | /* reading should also clear interrupts */ | |
474 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
475 | ||
476 | if (mask == 0xffffffff) { | |
477 | VPRINTK("QUICK EXIT 2\n"); | |
478 | return IRQ_NONE; | |
479 | } | |
480 | mask &= 0xffff; /* only 16 tags possible */ | |
481 | if (!mask) { | |
482 | VPRINTK("QUICK EXIT 3\n"); | |
483 | return IRQ_NONE; | |
484 | } | |
485 | ||
486 | spin_lock(&host_set->lock); | |
487 | ||
488 | writel(mask, mmio_base + PDC_INT_SEQMASK); | |
489 | ||
490 | for (i = 0; i < host_set->n_ports; i++) { | |
491 | VPRINTK("port %u\n", i); | |
492 | ap = host_set->ports[i]; | |
493 | tmp = mask & (1 << (i + 1)); | |
c1389503 TH |
494 | if (tmp && ap && |
495 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
496 | struct ata_queued_cmd *qc; |
497 | ||
498 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
499 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) | |
500 | handled += pdc_host_intr(ap, qc); | |
501 | } | |
502 | } | |
503 | ||
504 | spin_unlock(&host_set->lock); | |
505 | ||
506 | VPRINTK("EXIT\n"); | |
507 | ||
508 | return IRQ_RETVAL(handled); | |
509 | } | |
510 | ||
511 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
512 | { | |
513 | struct ata_port *ap = qc->ap; | |
514 | struct pdc_port_priv *pp = ap->private_data; | |
515 | unsigned int port_no = ap->port_no; | |
516 | u8 seq = (u8) (port_no + 1); | |
517 | ||
518 | VPRINTK("ENTER, ap %p\n", ap); | |
519 | ||
520 | writel(0x00000001, ap->host_set->mmio_base + (seq * 4)); | |
521 | readl(ap->host_set->mmio_base + (seq * 4)); /* flush */ | |
522 | ||
523 | pp->pkt[2] = seq; | |
524 | wmb(); /* flush PRD, pkt writes */ | |
525 | writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); | |
526 | readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
527 | } | |
528 | ||
529 | static int pdc_qc_issue_prot(struct ata_queued_cmd *qc) | |
530 | { | |
531 | switch (qc->tf.protocol) { | |
532 | case ATA_PROT_DMA: | |
533 | case ATA_PROT_NODATA: | |
534 | pdc_packet_start(qc); | |
535 | return 0; | |
536 | ||
537 | case ATA_PROT_ATAPI_DMA: | |
538 | BUG(); | |
539 | break; | |
540 | ||
541 | default: | |
542 | break; | |
543 | } | |
544 | ||
545 | return ata_qc_issue_prot(qc); | |
546 | } | |
547 | ||
548 | static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf) | |
549 | { | |
550 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
551 | tf->protocol == ATA_PROT_NODATA); | |
552 | ata_tf_load(ap, tf); | |
553 | } | |
554 | ||
555 | ||
556 | static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf) | |
557 | { | |
558 | WARN_ON (tf->protocol == ATA_PROT_DMA || | |
559 | tf->protocol == ATA_PROT_NODATA); | |
560 | ata_exec_command(ap, tf); | |
561 | } | |
562 | ||
563 | ||
564 | static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
565 | { | |
566 | port->cmd_addr = base; | |
567 | port->data_addr = base; | |
568 | port->feature_addr = | |
569 | port->error_addr = base + 0x4; | |
570 | port->nsect_addr = base + 0x8; | |
571 | port->lbal_addr = base + 0xc; | |
572 | port->lbam_addr = base + 0x10; | |
573 | port->lbah_addr = base + 0x14; | |
574 | port->device_addr = base + 0x18; | |
575 | port->command_addr = | |
576 | port->status_addr = base + 0x1c; | |
577 | port->altstatus_addr = | |
578 | port->ctl_addr = base + 0x38; | |
579 | } | |
580 | ||
581 | ||
582 | static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
583 | { | |
ea6ba10b | 584 | void __iomem *mmio = pe->mmio_base; |
1da177e4 LT |
585 | u32 tmp; |
586 | ||
587 | /* | |
588 | * Except for the hotplug stuff, this is voodoo from the | |
589 | * Promise driver. Label this entire section | |
590 | * "TODO: figure out why we do this" | |
591 | */ | |
592 | ||
593 | /* change FIFO_SHD to 8 dwords, enable BMR_BURST */ | |
594 | tmp = readl(mmio + PDC_FLASH_CTL); | |
595 | tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */ | |
596 | writel(tmp, mmio + PDC_FLASH_CTL); | |
597 | ||
598 | /* clear plug/unplug flags for all ports */ | |
599 | tmp = readl(mmio + PDC_SATA_PLUG_CSR); | |
600 | writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR); | |
601 | ||
602 | /* mask plug/unplug ints */ | |
603 | tmp = readl(mmio + PDC_SATA_PLUG_CSR); | |
604 | writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR); | |
605 | ||
606 | /* reduce TBG clock to 133 Mhz. */ | |
607 | tmp = readl(mmio + PDC_TBG_MODE); | |
608 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
609 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
610 | writel(tmp, mmio + PDC_TBG_MODE); | |
611 | ||
612 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
613 | msleep(10); | |
614 | ||
615 | /* adjust slew rate control register. */ | |
616 | tmp = readl(mmio + PDC_SLEW_CTL); | |
617 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
618 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
619 | writel(tmp, mmio + PDC_SLEW_CTL); | |
620 | } | |
621 | ||
622 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
623 | { | |
624 | static int printed_version; | |
625 | struct ata_probe_ent *probe_ent = NULL; | |
626 | unsigned long base; | |
ea6ba10b | 627 | void __iomem *mmio_base; |
1da177e4 LT |
628 | unsigned int board_idx = (unsigned int) ent->driver_data; |
629 | int pci_dev_busy = 0; | |
630 | int rc; | |
631 | ||
632 | if (!printed_version++) | |
633 | printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); | |
634 | ||
635 | /* | |
636 | * If this driver happens to only be useful on Apple's K2, then | |
637 | * we should check that here as it has a normal Serverworks ID | |
638 | */ | |
639 | rc = pci_enable_device(pdev); | |
640 | if (rc) | |
641 | return rc; | |
642 | ||
643 | rc = pci_request_regions(pdev, DRV_NAME); | |
644 | if (rc) { | |
645 | pci_dev_busy = 1; | |
646 | goto err_out; | |
647 | } | |
648 | ||
649 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
650 | if (rc) | |
651 | goto err_out_regions; | |
652 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
653 | if (rc) | |
654 | goto err_out_regions; | |
655 | ||
656 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
657 | if (probe_ent == NULL) { | |
658 | rc = -ENOMEM; | |
659 | goto err_out_regions; | |
660 | } | |
661 | ||
662 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
663 | probe_ent->dev = pci_dev_to_dev(pdev); | |
664 | INIT_LIST_HEAD(&probe_ent->node); | |
665 | ||
666 | mmio_base = ioremap(pci_resource_start(pdev, 3), | |
667 | pci_resource_len(pdev, 3)); | |
668 | if (mmio_base == NULL) { | |
669 | rc = -ENOMEM; | |
670 | goto err_out_free_ent; | |
671 | } | |
672 | base = (unsigned long) mmio_base; | |
673 | ||
674 | probe_ent->sht = pdc_port_info[board_idx].sht; | |
675 | probe_ent->host_flags = pdc_port_info[board_idx].host_flags; | |
676 | probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask; | |
677 | probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask; | |
678 | probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask; | |
679 | probe_ent->port_ops = pdc_port_info[board_idx].port_ops; | |
680 | ||
681 | probe_ent->irq = pdev->irq; | |
682 | probe_ent->irq_flags = SA_SHIRQ; | |
683 | probe_ent->mmio_base = mmio_base; | |
684 | ||
685 | pdc_ata_setup_port(&probe_ent->port[0], base + 0x200); | |
686 | pdc_ata_setup_port(&probe_ent->port[1], base + 0x280); | |
687 | ||
688 | probe_ent->port[0].scr_addr = base + 0x400; | |
689 | probe_ent->port[1].scr_addr = base + 0x500; | |
690 | ||
691 | /* notice 4-port boards */ | |
692 | switch (board_idx) { | |
693 | case board_20319: | |
694 | probe_ent->n_ports = 4; | |
695 | ||
696 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
697 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
698 | ||
699 | probe_ent->port[2].scr_addr = base + 0x600; | |
700 | probe_ent->port[3].scr_addr = base + 0x700; | |
701 | break; | |
702 | case board_2037x: | |
703 | probe_ent->n_ports = 2; | |
704 | break; | |
f497ba73 TL |
705 | case board_20619: |
706 | probe_ent->n_ports = 4; | |
707 | ||
708 | pdc_ata_setup_port(&probe_ent->port[2], base + 0x300); | |
709 | pdc_ata_setup_port(&probe_ent->port[3], base + 0x380); | |
710 | ||
711 | probe_ent->port[2].scr_addr = base + 0x600; | |
712 | probe_ent->port[3].scr_addr = base + 0x700; | |
713 | break; | |
1da177e4 LT |
714 | default: |
715 | BUG(); | |
716 | break; | |
717 | } | |
718 | ||
719 | pci_set_master(pdev); | |
720 | ||
721 | /* initialize adapter */ | |
722 | pdc_host_init(board_idx, probe_ent); | |
723 | ||
724 | /* FIXME: check ata_device_add return value */ | |
725 | ata_device_add(probe_ent); | |
726 | kfree(probe_ent); | |
727 | ||
728 | return 0; | |
729 | ||
730 | err_out_free_ent: | |
731 | kfree(probe_ent); | |
732 | err_out_regions: | |
733 | pci_release_regions(pdev); | |
734 | err_out: | |
735 | if (!pci_dev_busy) | |
736 | pci_disable_device(pdev); | |
737 | return rc; | |
738 | } | |
739 | ||
740 | ||
741 | static int __init pdc_ata_init(void) | |
742 | { | |
743 | return pci_module_init(&pdc_ata_pci_driver); | |
744 | } | |
745 | ||
746 | ||
747 | static void __exit pdc_ata_exit(void) | |
748 | { | |
749 | pci_unregister_driver(&pdc_ata_pci_driver); | |
750 | } | |
751 | ||
752 | ||
753 | MODULE_AUTHOR("Jeff Garzik"); | |
f497ba73 | 754 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
755 | MODULE_LICENSE("GPL"); |
756 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
757 | MODULE_VERSION(DRV_VERSION); | |
758 | ||
759 | module_init(pdc_ata_init); | |
760 | module_exit(pdc_ata_exit); |