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1da177e4 LT |
1 | /* |
2 | * sata_qstor.c - Pacific Digital Corporation QStor SATA | |
3 | * | |
4 | * Maintained by: Mark Lord <mlord@pobox.com> | |
5 | * | |
6 | * Copyright 2005 Pacific Digital Corporation. | |
7 | * (OSL/GPL code release authorized by Jalil Fadavi). | |
8 | * | |
af36d7f0 JG |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2, or (at your option) | |
13 | * any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; see the file COPYING. If not, write to | |
22 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | * | |
24 | * | |
25 | * libata documentation is available via 'make {ps|pdf}docs', | |
26 | * as Documentation/DocBook/libata.* | |
1da177e4 LT |
27 | * |
28 | */ | |
29 | ||
30 | #include <linux/kernel.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/blkdev.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/sched.h> | |
38 | #include "scsi.h" | |
39 | #include <scsi/scsi_host.h> | |
40 | #include <asm/io.h> | |
41 | #include <linux/libata.h> | |
42 | ||
43 | #define DRV_NAME "sata_qstor" | |
44 | #define DRV_VERSION "0.04" | |
45 | ||
46 | enum { | |
47 | QS_PORTS = 4, | |
48 | QS_MAX_PRD = LIBATA_MAX_PRD, | |
49 | QS_CPB_ORDER = 6, | |
50 | QS_CPB_BYTES = (1 << QS_CPB_ORDER), | |
51 | QS_PRD_BYTES = QS_MAX_PRD * 16, | |
52 | QS_PKT_BYTES = QS_CPB_BYTES + QS_PRD_BYTES, | |
53 | ||
54 | QS_DMA_BOUNDARY = ~0UL, | |
55 | ||
56 | /* global register offsets */ | |
57 | QS_HCF_CNFG3 = 0x0003, /* host configuration offset */ | |
58 | QS_HID_HPHY = 0x0004, /* host physical interface info */ | |
59 | QS_HCT_CTRL = 0x00e4, /* global interrupt mask offset */ | |
60 | QS_HST_SFF = 0x0100, /* host status fifo offset */ | |
61 | QS_HVS_SERD3 = 0x0393, /* PHY enable offset */ | |
62 | ||
63 | /* global control bits */ | |
64 | QS_HPHY_64BIT = (1 << 1), /* 64-bit bus detected */ | |
65 | QS_CNFG3_GSRST = 0x01, /* global chip reset */ | |
66 | QS_SERD3_PHY_ENA = 0xf0, /* PHY detection ENAble*/ | |
67 | ||
68 | /* per-channel register offsets */ | |
69 | QS_CCF_CPBA = 0x0710, /* chan CPB base address */ | |
70 | QS_CCF_CSEP = 0x0718, /* chan CPB separation factor */ | |
71 | QS_CFC_HUFT = 0x0800, /* host upstream fifo threshold */ | |
72 | QS_CFC_HDFT = 0x0804, /* host downstream fifo threshold */ | |
73 | QS_CFC_DUFT = 0x0808, /* dev upstream fifo threshold */ | |
74 | QS_CFC_DDFT = 0x080c, /* dev downstream fifo threshold */ | |
75 | QS_CCT_CTR0 = 0x0900, /* chan control-0 offset */ | |
76 | QS_CCT_CTR1 = 0x0901, /* chan control-1 offset */ | |
77 | QS_CCT_CFF = 0x0a00, /* chan command fifo offset */ | |
78 | ||
79 | /* channel control bits */ | |
80 | QS_CTR0_REG = (1 << 1), /* register mode (vs. pkt mode) */ | |
81 | QS_CTR0_CLER = (1 << 2), /* clear channel errors */ | |
82 | QS_CTR1_RDEV = (1 << 1), /* sata phy/comms reset */ | |
83 | QS_CTR1_RCHN = (1 << 4), /* reset channel logic */ | |
84 | QS_CCF_RUN_PKT = 0x107, /* RUN a new dma PKT */ | |
85 | ||
86 | /* pkt sub-field headers */ | |
87 | QS_HCB_HDR = 0x01, /* Host Control Block header */ | |
88 | QS_DCB_HDR = 0x02, /* Device Control Block header */ | |
89 | ||
90 | /* pkt HCB flag bits */ | |
91 | QS_HF_DIRO = (1 << 0), /* data DIRection Out */ | |
92 | QS_HF_DAT = (1 << 3), /* DATa pkt */ | |
93 | QS_HF_IEN = (1 << 4), /* Interrupt ENable */ | |
94 | QS_HF_VLD = (1 << 5), /* VaLiD pkt */ | |
95 | ||
96 | /* pkt DCB flag bits */ | |
97 | QS_DF_PORD = (1 << 2), /* Pio OR Dma */ | |
98 | QS_DF_ELBA = (1 << 3), /* Extended LBA (lba48) */ | |
99 | ||
100 | /* PCI device IDs */ | |
101 | board_2068_idx = 0, /* QStor 4-port SATA/RAID */ | |
102 | }; | |
103 | ||
104 | typedef enum { qs_state_idle, qs_state_pkt, qs_state_mmio } qs_state_t; | |
105 | ||
106 | struct qs_port_priv { | |
107 | u8 *pkt; | |
108 | dma_addr_t pkt_dma; | |
109 | qs_state_t state; | |
110 | }; | |
111 | ||
112 | static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
113 | static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
114 | static int qs_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
115 | static irqreturn_t qs_intr (int irq, void *dev_instance, struct pt_regs *regs); | |
116 | static int qs_port_start(struct ata_port *ap); | |
117 | static void qs_host_stop(struct ata_host_set *host_set); | |
118 | static void qs_port_stop(struct ata_port *ap); | |
119 | static void qs_phy_reset(struct ata_port *ap); | |
120 | static void qs_qc_prep(struct ata_queued_cmd *qc); | |
121 | static int qs_qc_issue(struct ata_queued_cmd *qc); | |
122 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc); | |
b73fc89f | 123 | static void qs_bmdma_stop(struct ata_queued_cmd *qc); |
1da177e4 LT |
124 | static u8 qs_bmdma_status(struct ata_port *ap); |
125 | static void qs_irq_clear(struct ata_port *ap); | |
126 | static void qs_eng_timeout(struct ata_port *ap); | |
127 | ||
128 | static Scsi_Host_Template qs_ata_sht = { | |
129 | .module = THIS_MODULE, | |
130 | .name = DRV_NAME, | |
131 | .ioctl = ata_scsi_ioctl, | |
132 | .queuecommand = ata_scsi_queuecmd, | |
133 | .eh_strategy_handler = ata_scsi_error, | |
134 | .can_queue = ATA_DEF_QUEUE, | |
135 | .this_id = ATA_SHT_THIS_ID, | |
136 | .sg_tablesize = QS_MAX_PRD, | |
137 | .max_sectors = ATA_MAX_SECTORS, | |
138 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
139 | .emulated = ATA_SHT_EMULATED, | |
140 | //FIXME .use_clustering = ATA_SHT_USE_CLUSTERING, | |
141 | .use_clustering = ENABLE_CLUSTERING, | |
142 | .proc_name = DRV_NAME, | |
143 | .dma_boundary = QS_DMA_BOUNDARY, | |
144 | .slave_configure = ata_scsi_slave_config, | |
145 | .bios_param = ata_std_bios_param, | |
146 | }; | |
147 | ||
148 | static struct ata_port_operations qs_ata_ops = { | |
149 | .port_disable = ata_port_disable, | |
150 | .tf_load = ata_tf_load, | |
151 | .tf_read = ata_tf_read, | |
152 | .check_status = ata_check_status, | |
153 | .check_atapi_dma = qs_check_atapi_dma, | |
154 | .exec_command = ata_exec_command, | |
155 | .dev_select = ata_std_dev_select, | |
156 | .phy_reset = qs_phy_reset, | |
157 | .qc_prep = qs_qc_prep, | |
158 | .qc_issue = qs_qc_issue, | |
159 | .eng_timeout = qs_eng_timeout, | |
160 | .irq_handler = qs_intr, | |
161 | .irq_clear = qs_irq_clear, | |
162 | .scr_read = qs_scr_read, | |
163 | .scr_write = qs_scr_write, | |
164 | .port_start = qs_port_start, | |
165 | .port_stop = qs_port_stop, | |
166 | .host_stop = qs_host_stop, | |
167 | .bmdma_stop = qs_bmdma_stop, | |
168 | .bmdma_status = qs_bmdma_status, | |
169 | }; | |
170 | ||
171 | static struct ata_port_info qs_port_info[] = { | |
172 | /* board_2068_idx */ | |
173 | { | |
174 | .sht = &qs_ata_sht, | |
175 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
176 | ATA_FLAG_SATA_RESET | | |
177 | //FIXME ATA_FLAG_SRST | | |
178 | ATA_FLAG_MMIO, | |
179 | .pio_mask = 0x10, /* pio4 */ | |
180 | .udma_mask = 0x7f, /* udma0-6 */ | |
181 | .port_ops = &qs_ata_ops, | |
182 | }, | |
183 | }; | |
184 | ||
185 | static struct pci_device_id qs_ata_pci_tbl[] = { | |
186 | { PCI_VENDOR_ID_PDC, 0x2068, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
187 | board_2068_idx }, | |
188 | ||
189 | { } /* terminate list */ | |
190 | }; | |
191 | ||
192 | static struct pci_driver qs_ata_pci_driver = { | |
193 | .name = DRV_NAME, | |
194 | .id_table = qs_ata_pci_tbl, | |
195 | .probe = qs_ata_init_one, | |
196 | .remove = ata_pci_remove_one, | |
197 | }; | |
198 | ||
199 | static int qs_check_atapi_dma(struct ata_queued_cmd *qc) | |
200 | { | |
201 | return 1; /* ATAPI DMA not supported */ | |
202 | } | |
203 | ||
d18d36b4 | 204 | static void qs_bmdma_stop(struct ata_queued_cmd *qc) |
1da177e4 LT |
205 | { |
206 | /* nothing */ | |
207 | } | |
208 | ||
209 | static u8 qs_bmdma_status(struct ata_port *ap) | |
210 | { | |
211 | return 0; | |
212 | } | |
213 | ||
214 | static void qs_irq_clear(struct ata_port *ap) | |
215 | { | |
216 | /* nothing */ | |
217 | } | |
218 | ||
219 | static inline void qs_enter_reg_mode(struct ata_port *ap) | |
220 | { | |
221 | u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000); | |
222 | ||
223 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); | |
224 | readb(chan + QS_CCT_CTR0); /* flush */ | |
225 | } | |
226 | ||
227 | static inline void qs_reset_channel_logic(struct ata_port *ap) | |
228 | { | |
229 | u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000); | |
230 | ||
231 | writeb(QS_CTR1_RCHN, chan + QS_CCT_CTR1); | |
232 | readb(chan + QS_CCT_CTR0); /* flush */ | |
233 | qs_enter_reg_mode(ap); | |
234 | } | |
235 | ||
236 | static void qs_phy_reset(struct ata_port *ap) | |
237 | { | |
238 | struct qs_port_priv *pp = ap->private_data; | |
239 | ||
240 | pp->state = qs_state_idle; | |
241 | qs_reset_channel_logic(ap); | |
242 | sata_phy_reset(ap); | |
243 | } | |
244 | ||
245 | static void qs_eng_timeout(struct ata_port *ap) | |
246 | { | |
247 | struct qs_port_priv *pp = ap->private_data; | |
248 | ||
249 | if (pp->state != qs_state_idle) /* healthy paranoia */ | |
250 | pp->state = qs_state_mmio; | |
251 | qs_reset_channel_logic(ap); | |
252 | ata_eng_timeout(ap); | |
253 | } | |
254 | ||
255 | static u32 qs_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
256 | { | |
257 | if (sc_reg > SCR_CONTROL) | |
258 | return ~0U; | |
259 | return readl((void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8))); | |
260 | } | |
261 | ||
262 | static void qs_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
263 | { | |
264 | if (sc_reg > SCR_CONTROL) | |
265 | return; | |
266 | writel(val, (void __iomem *)(ap->ioaddr.scr_addr + (sc_reg * 8))); | |
267 | } | |
268 | ||
269 | static void qs_fill_sg(struct ata_queued_cmd *qc) | |
270 | { | |
271 | struct scatterlist *sg = qc->sg; | |
272 | struct ata_port *ap = qc->ap; | |
273 | struct qs_port_priv *pp = ap->private_data; | |
274 | unsigned int nelem; | |
275 | u8 *prd = pp->pkt + QS_CPB_BYTES; | |
276 | ||
277 | assert(sg != NULL); | |
278 | assert(qc->n_elem > 0); | |
279 | ||
280 | for (nelem = 0; nelem < qc->n_elem; nelem++,sg++) { | |
281 | u64 addr; | |
282 | u32 len; | |
283 | ||
284 | addr = sg_dma_address(sg); | |
285 | *(__le64 *)prd = cpu_to_le64(addr); | |
286 | prd += sizeof(u64); | |
287 | ||
288 | len = sg_dma_len(sg); | |
289 | *(__le32 *)prd = cpu_to_le32(len); | |
290 | prd += sizeof(u64); | |
291 | ||
292 | VPRINTK("PRD[%u] = (0x%llX, 0x%X)\n", nelem, | |
293 | (unsigned long long)addr, len); | |
294 | } | |
295 | } | |
296 | ||
297 | static void qs_qc_prep(struct ata_queued_cmd *qc) | |
298 | { | |
299 | struct qs_port_priv *pp = qc->ap->private_data; | |
300 | u8 dflags = QS_DF_PORD, *buf = pp->pkt; | |
301 | u8 hflags = QS_HF_DAT | QS_HF_IEN | QS_HF_VLD; | |
302 | u64 addr; | |
303 | ||
304 | VPRINTK("ENTER\n"); | |
305 | ||
306 | qs_enter_reg_mode(qc->ap); | |
307 | if (qc->tf.protocol != ATA_PROT_DMA) { | |
308 | ata_qc_prep(qc); | |
309 | return; | |
310 | } | |
311 | ||
312 | qs_fill_sg(qc); | |
313 | ||
314 | if ((qc->tf.flags & ATA_TFLAG_WRITE)) | |
315 | hflags |= QS_HF_DIRO; | |
316 | if ((qc->tf.flags & ATA_TFLAG_LBA48)) | |
317 | dflags |= QS_DF_ELBA; | |
318 | ||
319 | /* host control block (HCB) */ | |
320 | buf[ 0] = QS_HCB_HDR; | |
321 | buf[ 1] = hflags; | |
322 | *(__le32 *)(&buf[ 4]) = cpu_to_le32(qc->nsect * ATA_SECT_SIZE); | |
323 | *(__le32 *)(&buf[ 8]) = cpu_to_le32(qc->n_elem); | |
324 | addr = ((u64)pp->pkt_dma) + QS_CPB_BYTES; | |
325 | *(__le64 *)(&buf[16]) = cpu_to_le64(addr); | |
326 | ||
327 | /* device control block (DCB) */ | |
328 | buf[24] = QS_DCB_HDR; | |
329 | buf[28] = dflags; | |
330 | ||
331 | /* frame information structure (FIS) */ | |
332 | ata_tf_to_fis(&qc->tf, &buf[32], 0); | |
333 | } | |
334 | ||
335 | static inline void qs_packet_start(struct ata_queued_cmd *qc) | |
336 | { | |
337 | struct ata_port *ap = qc->ap; | |
338 | u8 __iomem *chan = ap->host_set->mmio_base + (ap->port_no * 0x4000); | |
339 | ||
340 | VPRINTK("ENTER, ap %p\n", ap); | |
341 | ||
342 | writeb(QS_CTR0_CLER, chan + QS_CCT_CTR0); | |
343 | wmb(); /* flush PRDs and pkt to memory */ | |
344 | writel(QS_CCF_RUN_PKT, chan + QS_CCT_CFF); | |
345 | readl(chan + QS_CCT_CFF); /* flush */ | |
346 | } | |
347 | ||
348 | static int qs_qc_issue(struct ata_queued_cmd *qc) | |
349 | { | |
350 | struct qs_port_priv *pp = qc->ap->private_data; | |
351 | ||
352 | switch (qc->tf.protocol) { | |
353 | case ATA_PROT_DMA: | |
354 | ||
355 | pp->state = qs_state_pkt; | |
356 | qs_packet_start(qc); | |
357 | return 0; | |
358 | ||
359 | case ATA_PROT_ATAPI_DMA: | |
360 | BUG(); | |
361 | break; | |
362 | ||
363 | default: | |
364 | break; | |
365 | } | |
366 | ||
367 | pp->state = qs_state_mmio; | |
368 | return ata_qc_issue_prot(qc); | |
369 | } | |
370 | ||
371 | static inline unsigned int qs_intr_pkt(struct ata_host_set *host_set) | |
372 | { | |
373 | unsigned int handled = 0; | |
374 | u8 sFFE; | |
375 | u8 __iomem *mmio_base = host_set->mmio_base; | |
376 | ||
377 | do { | |
378 | u32 sff0 = readl(mmio_base + QS_HST_SFF); | |
379 | u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); | |
380 | u8 sEVLD = (sff1 >> 30) & 0x01; /* valid flag */ | |
381 | sFFE = sff1 >> 31; /* empty flag */ | |
382 | ||
383 | if (sEVLD) { | |
384 | u8 sDST = sff0 >> 16; /* dev status */ | |
385 | u8 sHST = sff1 & 0x3f; /* host status */ | |
386 | unsigned int port_no = (sff1 >> 8) & 0x03; | |
387 | struct ata_port *ap = host_set->ports[port_no]; | |
388 | ||
389 | DPRINTK("SFF=%08x%08x: sCHAN=%u sHST=%d sDST=%02x\n", | |
390 | sff1, sff0, port_no, sHST, sDST); | |
391 | handled = 1; | |
c1389503 TH |
392 | if (ap && !(ap->flags & |
393 | (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
394 | struct ata_queued_cmd *qc; |
395 | struct qs_port_priv *pp = ap->private_data; | |
396 | if (!pp || pp->state != qs_state_pkt) | |
397 | continue; | |
398 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
399 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) { | |
400 | switch (sHST) { | |
401 | case 0: /* sucessful CPB */ | |
402 | case 3: /* device error */ | |
403 | pp->state = qs_state_idle; | |
404 | qs_enter_reg_mode(qc->ap); | |
405 | ata_qc_complete(qc, sDST); | |
406 | break; | |
407 | default: | |
408 | break; | |
409 | } | |
410 | } | |
411 | } | |
412 | } | |
413 | } while (!sFFE); | |
414 | return handled; | |
415 | } | |
416 | ||
417 | static inline unsigned int qs_intr_mmio(struct ata_host_set *host_set) | |
418 | { | |
419 | unsigned int handled = 0, port_no; | |
420 | ||
421 | for (port_no = 0; port_no < host_set->n_ports; ++port_no) { | |
422 | struct ata_port *ap; | |
423 | ap = host_set->ports[port_no]; | |
c1389503 TH |
424 | if (ap && |
425 | !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) { | |
1da177e4 LT |
426 | struct ata_queued_cmd *qc; |
427 | struct qs_port_priv *pp = ap->private_data; | |
428 | if (!pp || pp->state != qs_state_mmio) | |
429 | continue; | |
430 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
431 | if (qc && (!(qc->tf.ctl & ATA_NIEN))) { | |
432 | ||
433 | /* check main status, clearing INTRQ */ | |
434 | u8 status = ata_chk_status(ap); | |
435 | if ((status & ATA_BUSY)) | |
436 | continue; | |
437 | DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n", | |
438 | ap->id, qc->tf.protocol, status); | |
8a60a071 | 439 | |
1da177e4 LT |
440 | /* complete taskfile transaction */ |
441 | pp->state = qs_state_idle; | |
442 | ata_qc_complete(qc, status); | |
443 | handled = 1; | |
444 | } | |
445 | } | |
446 | } | |
447 | return handled; | |
448 | } | |
449 | ||
450 | static irqreturn_t qs_intr(int irq, void *dev_instance, struct pt_regs *regs) | |
451 | { | |
452 | struct ata_host_set *host_set = dev_instance; | |
453 | unsigned int handled = 0; | |
454 | ||
455 | VPRINTK("ENTER\n"); | |
456 | ||
457 | spin_lock(&host_set->lock); | |
458 | handled = qs_intr_pkt(host_set) | qs_intr_mmio(host_set); | |
459 | spin_unlock(&host_set->lock); | |
460 | ||
461 | VPRINTK("EXIT\n"); | |
462 | ||
463 | return IRQ_RETVAL(handled); | |
464 | } | |
465 | ||
466 | static void qs_ata_setup_port(struct ata_ioports *port, unsigned long base) | |
467 | { | |
468 | port->cmd_addr = | |
469 | port->data_addr = base + 0x400; | |
470 | port->error_addr = | |
471 | port->feature_addr = base + 0x408; /* hob_feature = 0x409 */ | |
472 | port->nsect_addr = base + 0x410; /* hob_nsect = 0x411 */ | |
473 | port->lbal_addr = base + 0x418; /* hob_lbal = 0x419 */ | |
474 | port->lbam_addr = base + 0x420; /* hob_lbam = 0x421 */ | |
475 | port->lbah_addr = base + 0x428; /* hob_lbah = 0x429 */ | |
476 | port->device_addr = base + 0x430; | |
477 | port->status_addr = | |
478 | port->command_addr = base + 0x438; | |
479 | port->altstatus_addr = | |
480 | port->ctl_addr = base + 0x440; | |
481 | port->scr_addr = base + 0xc00; | |
482 | } | |
483 | ||
484 | static int qs_port_start(struct ata_port *ap) | |
485 | { | |
486 | struct device *dev = ap->host_set->dev; | |
487 | struct qs_port_priv *pp; | |
488 | void __iomem *mmio_base = ap->host_set->mmio_base; | |
489 | void __iomem *chan = mmio_base + (ap->port_no * 0x4000); | |
490 | u64 addr; | |
491 | int rc; | |
492 | ||
493 | rc = ata_port_start(ap); | |
494 | if (rc) | |
495 | return rc; | |
496 | qs_enter_reg_mode(ap); | |
497 | pp = kcalloc(1, sizeof(*pp), GFP_KERNEL); | |
498 | if (!pp) { | |
499 | rc = -ENOMEM; | |
500 | goto err_out; | |
501 | } | |
502 | pp->pkt = dma_alloc_coherent(dev, QS_PKT_BYTES, &pp->pkt_dma, | |
503 | GFP_KERNEL); | |
504 | if (!pp->pkt) { | |
505 | rc = -ENOMEM; | |
506 | goto err_out_kfree; | |
507 | } | |
508 | memset(pp->pkt, 0, QS_PKT_BYTES); | |
509 | ap->private_data = pp; | |
510 | ||
511 | addr = (u64)pp->pkt_dma; | |
512 | writel((u32) addr, chan + QS_CCF_CPBA); | |
513 | writel((u32)(addr >> 32), chan + QS_CCF_CPBA + 4); | |
514 | return 0; | |
515 | ||
516 | err_out_kfree: | |
517 | kfree(pp); | |
518 | err_out: | |
519 | ata_port_stop(ap); | |
520 | return rc; | |
521 | } | |
522 | ||
523 | static void qs_port_stop(struct ata_port *ap) | |
524 | { | |
525 | struct device *dev = ap->host_set->dev; | |
526 | struct qs_port_priv *pp = ap->private_data; | |
527 | ||
528 | if (pp != NULL) { | |
529 | ap->private_data = NULL; | |
530 | if (pp->pkt != NULL) | |
531 | dma_free_coherent(dev, QS_PKT_BYTES, pp->pkt, | |
532 | pp->pkt_dma); | |
533 | kfree(pp); | |
534 | } | |
535 | ata_port_stop(ap); | |
536 | } | |
537 | ||
538 | static void qs_host_stop(struct ata_host_set *host_set) | |
539 | { | |
540 | void __iomem *mmio_base = host_set->mmio_base; | |
541 | ||
542 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | |
543 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ | |
aa8f0dc6 JG |
544 | |
545 | ata_host_stop(host_set); | |
1da177e4 LT |
546 | } |
547 | ||
548 | static void qs_host_init(unsigned int chip_id, struct ata_probe_ent *pe) | |
549 | { | |
550 | void __iomem *mmio_base = pe->mmio_base; | |
551 | unsigned int port_no; | |
552 | ||
553 | writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ | |
554 | writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */ | |
555 | ||
556 | /* reset each channel in turn */ | |
557 | for (port_no = 0; port_no < pe->n_ports; ++port_no) { | |
558 | u8 __iomem *chan = mmio_base + (port_no * 0x4000); | |
559 | writeb(QS_CTR1_RDEV|QS_CTR1_RCHN, chan + QS_CCT_CTR1); | |
560 | writeb(QS_CTR0_REG, chan + QS_CCT_CTR0); | |
561 | readb(chan + QS_CCT_CTR0); /* flush */ | |
562 | } | |
563 | writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */ | |
564 | ||
565 | for (port_no = 0; port_no < pe->n_ports; ++port_no) { | |
566 | u8 __iomem *chan = mmio_base + (port_no * 0x4000); | |
567 | /* set FIFO depths to same settings as Windows driver */ | |
568 | writew(32, chan + QS_CFC_HUFT); | |
569 | writew(32, chan + QS_CFC_HDFT); | |
570 | writew(10, chan + QS_CFC_DUFT); | |
571 | writew( 8, chan + QS_CFC_DDFT); | |
572 | /* set CPB size in bytes, as a power of two */ | |
573 | writeb(QS_CPB_ORDER, chan + QS_CCF_CSEP); | |
574 | } | |
575 | writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ | |
576 | } | |
577 | ||
578 | /* | |
579 | * The QStor understands 64-bit buses, and uses 64-bit fields | |
580 | * for DMA pointers regardless of bus width. We just have to | |
581 | * make sure our DMA masks are set appropriately for whatever | |
582 | * bridge lies between us and the QStor, and then the DMA mapping | |
583 | * code will ensure we only ever "see" appropriate buffer addresses. | |
584 | * If we're 32-bit limited somewhere, then our 64-bit fields will | |
585 | * just end up with zeros in the upper 32-bits, without any special | |
586 | * logic required outside of this routine (below). | |
587 | */ | |
588 | static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base) | |
589 | { | |
590 | u32 bus_info = readl(mmio_base + QS_HID_HPHY); | |
591 | int rc, have_64bit_bus = (bus_info & QS_HPHY_64BIT); | |
592 | ||
593 | if (have_64bit_bus && | |
594 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
595 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
596 | if (rc) { | |
597 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
598 | if (rc) { | |
599 | printk(KERN_ERR DRV_NAME | |
600 | "(%s): 64-bit DMA enable failed\n", | |
601 | pci_name(pdev)); | |
602 | return rc; | |
603 | } | |
604 | } | |
605 | } else { | |
606 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
607 | if (rc) { | |
608 | printk(KERN_ERR DRV_NAME | |
609 | "(%s): 32-bit DMA enable failed\n", | |
610 | pci_name(pdev)); | |
611 | return rc; | |
612 | } | |
613 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
614 | if (rc) { | |
615 | printk(KERN_ERR DRV_NAME | |
616 | "(%s): 32-bit consistent DMA enable failed\n", | |
617 | pci_name(pdev)); | |
618 | return rc; | |
619 | } | |
620 | } | |
621 | return 0; | |
622 | } | |
623 | ||
624 | static int qs_ata_init_one(struct pci_dev *pdev, | |
625 | const struct pci_device_id *ent) | |
626 | { | |
627 | static int printed_version; | |
628 | struct ata_probe_ent *probe_ent = NULL; | |
629 | void __iomem *mmio_base; | |
630 | unsigned int board_idx = (unsigned int) ent->driver_data; | |
631 | int rc, port_no; | |
632 | ||
633 | if (!printed_version++) | |
634 | printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); | |
635 | ||
636 | rc = pci_enable_device(pdev); | |
637 | if (rc) | |
638 | return rc; | |
639 | ||
640 | rc = pci_request_regions(pdev, DRV_NAME); | |
641 | if (rc) | |
642 | goto err_out; | |
643 | ||
644 | if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0) { | |
645 | rc = -ENODEV; | |
646 | goto err_out_regions; | |
647 | } | |
648 | ||
649 | mmio_base = ioremap(pci_resource_start(pdev, 4), | |
650 | pci_resource_len(pdev, 4)); | |
651 | if (mmio_base == NULL) { | |
652 | rc = -ENOMEM; | |
653 | goto err_out_regions; | |
654 | } | |
655 | ||
656 | rc = qs_set_dma_masks(pdev, mmio_base); | |
657 | if (rc) | |
658 | goto err_out_iounmap; | |
659 | ||
660 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
661 | if (probe_ent == NULL) { | |
662 | rc = -ENOMEM; | |
663 | goto err_out_iounmap; | |
664 | } | |
665 | ||
666 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
667 | probe_ent->dev = pci_dev_to_dev(pdev); | |
668 | INIT_LIST_HEAD(&probe_ent->node); | |
669 | ||
670 | probe_ent->sht = qs_port_info[board_idx].sht; | |
671 | probe_ent->host_flags = qs_port_info[board_idx].host_flags; | |
672 | probe_ent->pio_mask = qs_port_info[board_idx].pio_mask; | |
673 | probe_ent->mwdma_mask = qs_port_info[board_idx].mwdma_mask; | |
674 | probe_ent->udma_mask = qs_port_info[board_idx].udma_mask; | |
675 | probe_ent->port_ops = qs_port_info[board_idx].port_ops; | |
676 | ||
677 | probe_ent->irq = pdev->irq; | |
678 | probe_ent->irq_flags = SA_SHIRQ; | |
679 | probe_ent->mmio_base = mmio_base; | |
680 | probe_ent->n_ports = QS_PORTS; | |
681 | ||
682 | for (port_no = 0; port_no < probe_ent->n_ports; ++port_no) { | |
683 | unsigned long chan = (unsigned long)mmio_base + | |
684 | (port_no * 0x4000); | |
685 | qs_ata_setup_port(&probe_ent->port[port_no], chan); | |
686 | } | |
687 | ||
688 | pci_set_master(pdev); | |
689 | ||
690 | /* initialize adapter */ | |
691 | qs_host_init(board_idx, probe_ent); | |
692 | ||
693 | rc = ata_device_add(probe_ent); | |
694 | kfree(probe_ent); | |
695 | if (rc != QS_PORTS) | |
696 | goto err_out_iounmap; | |
697 | return 0; | |
698 | ||
699 | err_out_iounmap: | |
700 | iounmap(mmio_base); | |
701 | err_out_regions: | |
702 | pci_release_regions(pdev); | |
703 | err_out: | |
704 | pci_disable_device(pdev); | |
705 | return rc; | |
706 | } | |
707 | ||
708 | static int __init qs_ata_init(void) | |
709 | { | |
710 | return pci_module_init(&qs_ata_pci_driver); | |
711 | } | |
712 | ||
713 | static void __exit qs_ata_exit(void) | |
714 | { | |
715 | pci_unregister_driver(&qs_ata_pci_driver); | |
716 | } | |
717 | ||
718 | MODULE_AUTHOR("Mark Lord"); | |
719 | MODULE_DESCRIPTION("Pacific Digital Corporation QStor SATA low-level driver"); | |
720 | MODULE_LICENSE("GPL"); | |
721 | MODULE_DEVICE_TABLE(pci, qs_ata_pci_tbl); | |
722 | MODULE_VERSION(DRV_VERSION); | |
723 | ||
724 | module_init(qs_ata_init); | |
725 | module_exit(qs_ata_exit); |