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1da177e4 LT |
1 | /* |
2 | * sata_sil.c - Silicon Image SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
af36d7f0 | 8 | * Copyright 2003-2005 Red Hat, Inc. |
1da177e4 LT |
9 | * Copyright 2003 Benjamin Herrenschmidt |
10 | * | |
af36d7f0 JG |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
1da177e4 | 29 | * |
953d1137 JG |
30 | * Documentation for SiI 3112: |
31 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
32 | * | |
33 | * Other errata and documentation available under NDA. | |
34 | * | |
1da177e4 LT |
35 | */ |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/blkdev.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/interrupt.h> | |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 LT |
45 | #include <scsi/scsi_host.h> |
46 | #include <linux/libata.h> | |
47 | ||
48 | #define DRV_NAME "sata_sil" | |
8676ce07 | 49 | #define DRV_VERSION "2.0" |
1da177e4 LT |
50 | |
51 | enum { | |
e653a1e6 TH |
52 | /* |
53 | * host flags | |
54 | */ | |
201ce859 | 55 | SIL_FLAG_NO_SATA_IRQ = (1 << 28), |
e4e10e3e | 56 | SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), |
e4deec63 | 57 | SIL_FLAG_MOD15WRITE = (1 << 30), |
20888d83 | 58 | |
e653a1e6 | 59 | SIL_DFL_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
e573890b | 60 | ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME, |
e4deec63 | 61 | |
e653a1e6 TH |
62 | /* |
63 | * Controller IDs | |
64 | */ | |
1da177e4 | 65 | sil_3112 = 0, |
201ce859 TH |
66 | sil_3112_no_sata_irq = 1, |
67 | sil_3512 = 2, | |
68 | sil_3114 = 3, | |
1da177e4 | 69 | |
e653a1e6 TH |
70 | /* |
71 | * Register offsets | |
72 | */ | |
1da177e4 | 73 | SIL_SYSCFG = 0x48, |
e653a1e6 TH |
74 | |
75 | /* | |
76 | * Register bits | |
77 | */ | |
78 | /* SYSCFG */ | |
1da177e4 LT |
79 | SIL_MASK_IDE0_INT = (1 << 22), |
80 | SIL_MASK_IDE1_INT = (1 << 23), | |
81 | SIL_MASK_IDE2_INT = (1 << 24), | |
82 | SIL_MASK_IDE3_INT = (1 << 25), | |
83 | SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, | |
84 | SIL_MASK_4PORT = SIL_MASK_2PORT | | |
85 | SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, | |
86 | ||
e653a1e6 | 87 | /* BMDMA/BMDMA2 */ |
1da177e4 | 88 | SIL_INTR_STEERING = (1 << 1), |
e653a1e6 | 89 | |
20888d83 TH |
90 | SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ |
91 | SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ | |
92 | SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ | |
93 | SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ | |
94 | SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ | |
95 | SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ | |
96 | SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ | |
97 | SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ | |
98 | SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ | |
99 | SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ | |
100 | ||
101 | /* SIEN */ | |
102 | SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ | |
103 | ||
e653a1e6 TH |
104 | /* |
105 | * Others | |
106 | */ | |
1da177e4 LT |
107 | SIL_QUIRK_MOD15WRITE = (1 << 0), |
108 | SIL_QUIRK_UDMA5MAX = (1 << 1), | |
109 | }; | |
110 | ||
111 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
afb5a7cb | 112 | static int sil_pci_device_resume(struct pci_dev *pdev); |
1da177e4 LT |
113 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev); |
114 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
115 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
116 | static void sil_post_set_mode (struct ata_port *ap); | |
cbe88fbc TH |
117 | static irqreturn_t sil_interrupt(int irq, void *dev_instance, |
118 | struct pt_regs *regs); | |
f6aae27e TH |
119 | static void sil_freeze(struct ata_port *ap); |
120 | static void sil_thaw(struct ata_port *ap); | |
1da177e4 | 121 | |
374b1873 | 122 | |
3b7d697d | 123 | static const struct pci_device_id sil_pci_tbl[] = { |
81c2af35 TH |
124 | { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
125 | { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, | |
0ee304d5 | 126 | { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 }, |
1da177e4 | 127 | { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 }, |
81c2af35 | 128 | { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
201ce859 TH |
129 | { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_no_sata_irq }, |
130 | { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112_no_sata_irq }, | |
1da177e4 LT |
131 | { } /* terminate list */ |
132 | }; | |
133 | ||
134 | ||
135 | /* TODO firmware versions should be added - eric */ | |
136 | static const struct sil_drivelist { | |
137 | const char * product; | |
138 | unsigned int quirk; | |
139 | } sil_blacklist [] = { | |
140 | { "ST320012AS", SIL_QUIRK_MOD15WRITE }, | |
141 | { "ST330013AS", SIL_QUIRK_MOD15WRITE }, | |
142 | { "ST340017AS", SIL_QUIRK_MOD15WRITE }, | |
143 | { "ST360015AS", SIL_QUIRK_MOD15WRITE }, | |
1da177e4 LT |
144 | { "ST380023AS", SIL_QUIRK_MOD15WRITE }, |
145 | { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, | |
1da177e4 LT |
146 | { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, |
147 | { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, | |
148 | { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, | |
149 | { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, | |
150 | { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, | |
151 | { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, | |
152 | { } | |
153 | }; | |
154 | ||
155 | static struct pci_driver sil_pci_driver = { | |
156 | .name = DRV_NAME, | |
157 | .id_table = sil_pci_tbl, | |
158 | .probe = sil_init_one, | |
159 | .remove = ata_pci_remove_one, | |
afb5a7cb TH |
160 | .suspend = ata_pci_device_suspend, |
161 | .resume = sil_pci_device_resume, | |
1da177e4 LT |
162 | }; |
163 | ||
193515d5 | 164 | static struct scsi_host_template sil_sht = { |
1da177e4 LT |
165 | .module = THIS_MODULE, |
166 | .name = DRV_NAME, | |
167 | .ioctl = ata_scsi_ioctl, | |
168 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
169 | .can_queue = ATA_DEF_QUEUE, |
170 | .this_id = ATA_SHT_THIS_ID, | |
171 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
172 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
173 | .emulated = ATA_SHT_EMULATED, | |
174 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
175 | .proc_name = DRV_NAME, | |
176 | .dma_boundary = ATA_DMA_BOUNDARY, | |
177 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 178 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 179 | .bios_param = ata_std_bios_param, |
afb5a7cb TH |
180 | .suspend = ata_scsi_device_suspend, |
181 | .resume = ata_scsi_device_resume, | |
1da177e4 LT |
182 | }; |
183 | ||
057ace5e | 184 | static const struct ata_port_operations sil_ops = { |
1da177e4 LT |
185 | .port_disable = ata_port_disable, |
186 | .dev_config = sil_dev_config, | |
187 | .tf_load = ata_tf_load, | |
188 | .tf_read = ata_tf_read, | |
189 | .check_status = ata_check_status, | |
190 | .exec_command = ata_exec_command, | |
191 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
192 | .post_set_mode = sil_post_set_mode, |
193 | .bmdma_setup = ata_bmdma_setup, | |
194 | .bmdma_start = ata_bmdma_start, | |
195 | .bmdma_stop = ata_bmdma_stop, | |
196 | .bmdma_status = ata_bmdma_status, | |
197 | .qc_prep = ata_qc_prep, | |
198 | .qc_issue = ata_qc_issue_prot, | |
a6b2c5d4 | 199 | .data_xfer = ata_mmio_data_xfer, |
f6aae27e TH |
200 | .freeze = sil_freeze, |
201 | .thaw = sil_thaw, | |
202 | .error_handler = ata_bmdma_error_handler, | |
203 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
cbe88fbc | 204 | .irq_handler = sil_interrupt, |
1da177e4 LT |
205 | .irq_clear = ata_bmdma_irq_clear, |
206 | .scr_read = sil_scr_read, | |
207 | .scr_write = sil_scr_write, | |
208 | .port_start = ata_port_start, | |
209 | .port_stop = ata_port_stop, | |
374b1873 | 210 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
211 | }; |
212 | ||
98ac62de | 213 | static const struct ata_port_info sil_port_info[] = { |
1da177e4 | 214 | /* sil_3112 */ |
e4deec63 TH |
215 | { |
216 | .sht = &sil_sht, | |
e653a1e6 | 217 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE, |
e4deec63 TH |
218 | .pio_mask = 0x1f, /* pio0-4 */ |
219 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
220 | .udma_mask = 0x3f, /* udma0-5 */ | |
221 | .port_ops = &sil_ops, | |
0ee304d5 | 222 | }, |
201ce859 TH |
223 | /* sil_3112_no_sata_irq */ |
224 | { | |
225 | .sht = &sil_sht, | |
226 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE | | |
227 | SIL_FLAG_NO_SATA_IRQ, | |
228 | .pio_mask = 0x1f, /* pio0-4 */ | |
229 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
230 | .udma_mask = 0x3f, /* udma0-5 */ | |
231 | .port_ops = &sil_ops, | |
232 | }, | |
0ee304d5 | 233 | /* sil_3512 */ |
1da177e4 LT |
234 | { |
235 | .sht = &sil_sht, | |
e653a1e6 | 236 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
0ee304d5 TH |
237 | .pio_mask = 0x1f, /* pio0-4 */ |
238 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
239 | .udma_mask = 0x3f, /* udma0-5 */ | |
240 | .port_ops = &sil_ops, | |
241 | }, | |
242 | /* sil_3114 */ | |
1da177e4 LT |
243 | { |
244 | .sht = &sil_sht, | |
e653a1e6 | 245 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
1da177e4 LT |
246 | .pio_mask = 0x1f, /* pio0-4 */ |
247 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
248 | .udma_mask = 0x3f, /* udma0-5 */ | |
249 | .port_ops = &sil_ops, | |
250 | }, | |
251 | }; | |
252 | ||
253 | /* per-port register offsets */ | |
254 | /* TODO: we can probably calculate rather than use a table */ | |
255 | static const struct { | |
256 | unsigned long tf; /* ATA taskfile register block */ | |
257 | unsigned long ctl; /* ATA control/altstatus register block */ | |
258 | unsigned long bmdma; /* DMA register block */ | |
20888d83 | 259 | unsigned long bmdma2; /* DMA register block #2 */ |
48d4ef2a | 260 | unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ |
1da177e4 LT |
261 | unsigned long scr; /* SATA control register block */ |
262 | unsigned long sien; /* SATA Interrupt Enable register */ | |
263 | unsigned long xfer_mode;/* data transfer mode register */ | |
e4e10e3e | 264 | unsigned long sfis_cfg; /* SATA FIS reception config register */ |
1da177e4 LT |
265 | } sil_port[] = { |
266 | /* port 0 ... */ | |
20888d83 TH |
267 | { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, |
268 | { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, | |
269 | { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, | |
270 | { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, | |
1da177e4 LT |
271 | /* ... port 3 */ |
272 | }; | |
273 | ||
274 | MODULE_AUTHOR("Jeff Garzik"); | |
275 | MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); | |
276 | MODULE_LICENSE("GPL"); | |
277 | MODULE_DEVICE_TABLE(pci, sil_pci_tbl); | |
278 | MODULE_VERSION(DRV_VERSION); | |
279 | ||
51e9f2ff JG |
280 | static int slow_down = 0; |
281 | module_param(slow_down, int, 0444); | |
282 | MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); | |
283 | ||
374b1873 | 284 | |
1da177e4 LT |
285 | static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) |
286 | { | |
287 | u8 cache_line = 0; | |
288 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); | |
289 | return cache_line; | |
290 | } | |
291 | ||
292 | static void sil_post_set_mode (struct ata_port *ap) | |
293 | { | |
294 | struct ata_host_set *host_set = ap->host_set; | |
295 | struct ata_device *dev; | |
ea6ba10b JG |
296 | void __iomem *addr = |
297 | host_set->mmio_base + sil_port[ap->port_no].xfer_mode; | |
1da177e4 LT |
298 | u32 tmp, dev_mode[2]; |
299 | unsigned int i; | |
300 | ||
301 | for (i = 0; i < 2; i++) { | |
302 | dev = &ap->device[i]; | |
e1211e3f | 303 | if (!ata_dev_enabled(dev)) |
1da177e4 LT |
304 | dev_mode[i] = 0; /* PIO0/1/2 */ |
305 | else if (dev->flags & ATA_DFLAG_PIO) | |
306 | dev_mode[i] = 1; /* PIO3/4 */ | |
307 | else | |
308 | dev_mode[i] = 3; /* UDMA */ | |
309 | /* value 2 indicates MDMA */ | |
310 | } | |
311 | ||
312 | tmp = readl(addr); | |
313 | tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); | |
314 | tmp |= dev_mode[0]; | |
315 | tmp |= (dev_mode[1] << 4); | |
316 | writel(tmp, addr); | |
317 | readl(addr); /* flush */ | |
318 | } | |
319 | ||
320 | static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) | |
321 | { | |
322 | unsigned long offset = ap->ioaddr.scr_addr; | |
323 | ||
324 | switch (sc_reg) { | |
325 | case SCR_STATUS: | |
326 | return offset + 4; | |
327 | case SCR_ERROR: | |
328 | return offset + 8; | |
329 | case SCR_CONTROL: | |
330 | return offset; | |
331 | default: | |
332 | /* do nothing */ | |
333 | break; | |
334 | } | |
335 | ||
336 | return 0; | |
337 | } | |
338 | ||
339 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
340 | { | |
9aa36e89 | 341 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
1da177e4 LT |
342 | if (mmio) |
343 | return readl(mmio); | |
344 | return 0xffffffffU; | |
345 | } | |
346 | ||
347 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
348 | { | |
9aa36e89 | 349 | void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
1da177e4 LT |
350 | if (mmio) |
351 | writel(val, mmio); | |
352 | } | |
353 | ||
cbe88fbc TH |
354 | static void sil_host_intr(struct ata_port *ap, u32 bmdma2) |
355 | { | |
356 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
357 | u8 status; | |
358 | ||
e573890b | 359 | if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { |
d4c85325 TH |
360 | u32 serror; |
361 | ||
362 | /* SIEN doesn't mask SATA IRQs on some 3112s. Those | |
363 | * controllers continue to assert IRQ as long as | |
364 | * SError bits are pending. Clear SError immediately. | |
365 | */ | |
366 | serror = sil_scr_read(ap, SCR_ERROR); | |
367 | sil_scr_write(ap, SCR_ERROR, serror); | |
368 | ||
369 | /* Trigger hotplug and accumulate SError only if the | |
370 | * port isn't already frozen. Otherwise, PHY events | |
371 | * during hardreset makes controllers with broken SIEN | |
372 | * repeat probing needlessly. | |
373 | */ | |
b51e9e5d | 374 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) { |
d4c85325 TH |
375 | ata_ehi_hotplugged(&ap->eh_info); |
376 | ap->eh_info.serror |= serror; | |
377 | } | |
378 | ||
e573890b TH |
379 | goto freeze; |
380 | } | |
381 | ||
cbe88fbc TH |
382 | if (unlikely(!qc || qc->tf.ctl & ATA_NIEN)) |
383 | goto freeze; | |
384 | ||
385 | /* Check whether we are expecting interrupt in this state */ | |
386 | switch (ap->hsm_task_state) { | |
387 | case HSM_ST_FIRST: | |
388 | /* Some pre-ATAPI-4 devices assert INTRQ | |
389 | * at this state when ready to receive CDB. | |
390 | */ | |
391 | ||
392 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
393 | * The flag was turned on only for atapi devices. | |
394 | * No need to check is_atapi_taskfile(&qc->tf) again. | |
395 | */ | |
396 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
397 | goto err_hsm; | |
398 | break; | |
399 | case HSM_ST_LAST: | |
400 | if (qc->tf.protocol == ATA_PROT_DMA || | |
401 | qc->tf.protocol == ATA_PROT_ATAPI_DMA) { | |
402 | /* clear DMA-Start bit */ | |
403 | ap->ops->bmdma_stop(qc); | |
404 | ||
405 | if (bmdma2 & SIL_DMA_ERROR) { | |
406 | qc->err_mask |= AC_ERR_HOST_BUS; | |
407 | ap->hsm_task_state = HSM_ST_ERR; | |
408 | } | |
409 | } | |
410 | break; | |
411 | case HSM_ST: | |
412 | break; | |
413 | default: | |
414 | goto err_hsm; | |
415 | } | |
416 | ||
417 | /* check main status, clearing INTRQ */ | |
418 | status = ata_chk_status(ap); | |
419 | if (unlikely(status & ATA_BUSY)) | |
420 | goto err_hsm; | |
421 | ||
422 | /* ack bmdma irq events */ | |
423 | ata_bmdma_irq_clear(ap); | |
424 | ||
425 | /* kick HSM in the ass */ | |
426 | ata_hsm_move(ap, qc, status, 0); | |
427 | ||
428 | return; | |
429 | ||
430 | err_hsm: | |
431 | qc->err_mask |= AC_ERR_HSM; | |
432 | freeze: | |
433 | ata_port_freeze(ap); | |
434 | } | |
435 | ||
436 | static irqreturn_t sil_interrupt(int irq, void *dev_instance, | |
437 | struct pt_regs *regs) | |
438 | { | |
439 | struct ata_host_set *host_set = dev_instance; | |
440 | void __iomem *mmio_base = host_set->mmio_base; | |
441 | int handled = 0; | |
442 | int i; | |
443 | ||
444 | spin_lock(&host_set->lock); | |
445 | ||
446 | for (i = 0; i < host_set->n_ports; i++) { | |
447 | struct ata_port *ap = host_set->ports[i]; | |
448 | u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); | |
449 | ||
450 | if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) | |
451 | continue; | |
452 | ||
201ce859 TH |
453 | /* turn off SATA_IRQ if not supported */ |
454 | if (ap->flags & SIL_FLAG_NO_SATA_IRQ) | |
455 | bmdma2 &= ~SIL_DMA_SATA_IRQ; | |
456 | ||
23fa9618 TH |
457 | if (bmdma2 == 0xffffffff || |
458 | !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) | |
cbe88fbc TH |
459 | continue; |
460 | ||
461 | sil_host_intr(ap, bmdma2); | |
462 | handled = 1; | |
463 | } | |
464 | ||
465 | spin_unlock(&host_set->lock); | |
466 | ||
467 | return IRQ_RETVAL(handled); | |
468 | } | |
469 | ||
f6aae27e TH |
470 | static void sil_freeze(struct ata_port *ap) |
471 | { | |
472 | void __iomem *mmio_base = ap->host_set->mmio_base; | |
473 | u32 tmp; | |
474 | ||
e573890b TH |
475 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ |
476 | writel(0, mmio_base + sil_port[ap->port_no].sien); | |
477 | ||
f6aae27e TH |
478 | /* plug IRQ */ |
479 | tmp = readl(mmio_base + SIL_SYSCFG); | |
480 | tmp |= SIL_MASK_IDE0_INT << ap->port_no; | |
481 | writel(tmp, mmio_base + SIL_SYSCFG); | |
482 | readl(mmio_base + SIL_SYSCFG); /* flush */ | |
483 | } | |
484 | ||
485 | static void sil_thaw(struct ata_port *ap) | |
486 | { | |
487 | void __iomem *mmio_base = ap->host_set->mmio_base; | |
488 | u32 tmp; | |
489 | ||
490 | /* clear IRQ */ | |
491 | ata_chk_status(ap); | |
492 | ata_bmdma_irq_clear(ap); | |
493 | ||
201ce859 TH |
494 | /* turn on SATA IRQ if supported */ |
495 | if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) | |
496 | writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); | |
e573890b | 497 | |
f6aae27e TH |
498 | /* turn on IRQ */ |
499 | tmp = readl(mmio_base + SIL_SYSCFG); | |
500 | tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); | |
501 | writel(tmp, mmio_base + SIL_SYSCFG); | |
502 | } | |
503 | ||
1da177e4 LT |
504 | /** |
505 | * sil_dev_config - Apply device/host-specific errata fixups | |
506 | * @ap: Port containing device to be examined | |
507 | * @dev: Device to be examined | |
508 | * | |
509 | * After the IDENTIFY [PACKET] DEVICE step is complete, and a | |
510 | * device is known to be present, this function is called. | |
511 | * We apply two errata fixups which are specific to Silicon Image, | |
512 | * a Seagate and a Maxtor fixup. | |
513 | * | |
514 | * For certain Seagate devices, we must limit the maximum sectors | |
515 | * to under 8K. | |
516 | * | |
517 | * For certain Maxtor devices, we must not program the drive | |
518 | * beyond udma5. | |
519 | * | |
520 | * Both fixups are unfairly pessimistic. As soon as I get more | |
521 | * information on these errata, I will create a more exhaustive | |
522 | * list, and apply the fixups to only the specific | |
523 | * devices/hosts/firmwares that need it. | |
524 | * | |
525 | * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted | |
526 | * The Maxtor quirk is in the blacklist, but I'm keeping the original | |
527 | * pessimistic fix for the following reasons... | |
528 | * - There seems to be less info on it, only one device gleaned off the | |
529 | * Windows driver, maybe only one is affected. More info would be greatly | |
530 | * appreciated. | |
531 | * - But then again UDMA5 is hardly anything to complain about | |
532 | */ | |
533 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) | |
534 | { | |
535 | unsigned int n, quirks = 0; | |
2e02671d | 536 | unsigned char model_num[41]; |
1da177e4 | 537 | |
6a62a04d | 538 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num)); |
1da177e4 | 539 | |
8a60a071 | 540 | for (n = 0; sil_blacklist[n].product; n++) |
2e02671d | 541 | if (!strcmp(sil_blacklist[n].product, model_num)) { |
1da177e4 LT |
542 | quirks = sil_blacklist[n].quirk; |
543 | break; | |
544 | } | |
8a60a071 | 545 | |
1da177e4 | 546 | /* limit requests to 15 sectors */ |
51e9f2ff JG |
547 | if (slow_down || |
548 | ((ap->flags & SIL_FLAG_MOD15WRITE) && | |
549 | (quirks & SIL_QUIRK_MOD15WRITE))) { | |
f15a1daf TH |
550 | ata_dev_printk(dev, KERN_INFO, "applying Seagate errata fix " |
551 | "(mod15write workaround)\n"); | |
b00eec1d | 552 | dev->max_sectors = 15; |
1da177e4 LT |
553 | return; |
554 | } | |
555 | ||
556 | /* limit to udma5 */ | |
557 | if (quirks & SIL_QUIRK_UDMA5MAX) { | |
f15a1daf TH |
558 | ata_dev_printk(dev, KERN_INFO, |
559 | "applying Maxtor errata fix %s\n", model_num); | |
5a529139 | 560 | dev->udma_mask &= ATA_UDMA5; |
1da177e4 LT |
561 | return; |
562 | } | |
563 | } | |
564 | ||
3d8ec913 TH |
565 | static void sil_init_controller(struct pci_dev *pdev, |
566 | int n_ports, unsigned long host_flags, | |
567 | void __iomem *mmio_base) | |
568 | { | |
569 | u8 cls; | |
570 | u32 tmp; | |
571 | int i; | |
572 | ||
573 | /* Initialize FIFO PCI bus arbitration */ | |
574 | cls = sil_get_device_cache_line(pdev); | |
575 | if (cls) { | |
576 | cls >>= 3; | |
577 | cls++; /* cls = (line_size/8)+1 */ | |
578 | for (i = 0; i < n_ports; i++) | |
579 | writew(cls << 8 | cls, | |
580 | mmio_base + sil_port[i].fifo_cfg); | |
581 | } else | |
582 | dev_printk(KERN_WARNING, &pdev->dev, | |
583 | "cache line size not set. Driver may not function\n"); | |
584 | ||
585 | /* Apply R_ERR on DMA activate FIS errata workaround */ | |
586 | if (host_flags & SIL_FLAG_RERR_ON_DMA_ACT) { | |
587 | int cnt; | |
588 | ||
589 | for (i = 0, cnt = 0; i < n_ports; i++) { | |
590 | tmp = readl(mmio_base + sil_port[i].sfis_cfg); | |
591 | if ((tmp & 0x3) != 0x01) | |
592 | continue; | |
593 | if (!cnt) | |
594 | dev_printk(KERN_INFO, &pdev->dev, | |
595 | "Applying R_ERR on DMA activate " | |
596 | "FIS errata fix\n"); | |
597 | writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); | |
598 | cnt++; | |
599 | } | |
600 | } | |
601 | ||
602 | if (n_ports == 4) { | |
603 | /* flip the magic "make 4 ports work" bit */ | |
604 | tmp = readl(mmio_base + sil_port[2].bmdma); | |
605 | if ((tmp & SIL_INTR_STEERING) == 0) | |
606 | writel(tmp | SIL_INTR_STEERING, | |
607 | mmio_base + sil_port[2].bmdma); | |
608 | } | |
609 | } | |
610 | ||
1da177e4 LT |
611 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
612 | { | |
613 | static int printed_version; | |
614 | struct ata_probe_ent *probe_ent = NULL; | |
615 | unsigned long base; | |
ea6ba10b | 616 | void __iomem *mmio_base; |
1da177e4 LT |
617 | int rc; |
618 | unsigned int i; | |
619 | int pci_dev_busy = 0; | |
1da177e4 LT |
620 | |
621 | if (!printed_version++) | |
a9524a76 | 622 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 623 | |
1da177e4 LT |
624 | rc = pci_enable_device(pdev); |
625 | if (rc) | |
626 | return rc; | |
627 | ||
628 | rc = pci_request_regions(pdev, DRV_NAME); | |
629 | if (rc) { | |
630 | pci_dev_busy = 1; | |
631 | goto err_out; | |
632 | } | |
633 | ||
634 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
635 | if (rc) | |
636 | goto err_out_regions; | |
637 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
638 | if (rc) | |
639 | goto err_out_regions; | |
640 | ||
9a531443 | 641 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
642 | if (probe_ent == NULL) { |
643 | rc = -ENOMEM; | |
644 | goto err_out_regions; | |
645 | } | |
646 | ||
1da177e4 LT |
647 | INIT_LIST_HEAD(&probe_ent->node); |
648 | probe_ent->dev = pci_dev_to_dev(pdev); | |
649 | probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; | |
650 | probe_ent->sht = sil_port_info[ent->driver_data].sht; | |
651 | probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2; | |
652 | probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; | |
653 | probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask; | |
654 | probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; | |
655 | probe_ent->irq = pdev->irq; | |
1d6f359a | 656 | probe_ent->irq_flags = IRQF_SHARED; |
1da177e4 LT |
657 | probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags; |
658 | ||
374b1873 | 659 | mmio_base = pci_iomap(pdev, 5, 0); |
1da177e4 LT |
660 | if (mmio_base == NULL) { |
661 | rc = -ENOMEM; | |
662 | goto err_out_free_ent; | |
663 | } | |
664 | ||
665 | probe_ent->mmio_base = mmio_base; | |
666 | ||
667 | base = (unsigned long) mmio_base; | |
668 | ||
669 | for (i = 0; i < probe_ent->n_ports; i++) { | |
670 | probe_ent->port[i].cmd_addr = base + sil_port[i].tf; | |
671 | probe_ent->port[i].altstatus_addr = | |
672 | probe_ent->port[i].ctl_addr = base + sil_port[i].ctl; | |
673 | probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma; | |
674 | probe_ent->port[i].scr_addr = base + sil_port[i].scr; | |
675 | ata_std_ports(&probe_ent->port[i]); | |
676 | } | |
677 | ||
3d8ec913 TH |
678 | sil_init_controller(pdev, probe_ent->n_ports, probe_ent->host_flags, |
679 | mmio_base); | |
1da177e4 | 680 | |
1da177e4 LT |
681 | pci_set_master(pdev); |
682 | ||
683 | /* FIXME: check ata_device_add return value */ | |
684 | ata_device_add(probe_ent); | |
685 | kfree(probe_ent); | |
686 | ||
687 | return 0; | |
688 | ||
689 | err_out_free_ent: | |
690 | kfree(probe_ent); | |
691 | err_out_regions: | |
692 | pci_release_regions(pdev); | |
693 | err_out: | |
694 | if (!pci_dev_busy) | |
695 | pci_disable_device(pdev); | |
696 | return rc; | |
697 | } | |
698 | ||
afb5a7cb TH |
699 | static int sil_pci_device_resume(struct pci_dev *pdev) |
700 | { | |
701 | struct ata_host_set *host_set = dev_get_drvdata(&pdev->dev); | |
702 | ||
703 | ata_pci_device_do_resume(pdev); | |
704 | sil_init_controller(pdev, host_set->n_ports, host_set->ports[0]->flags, | |
705 | host_set->mmio_base); | |
706 | ata_host_set_resume(host_set); | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
1da177e4 LT |
711 | static int __init sil_init(void) |
712 | { | |
b7887196 | 713 | return pci_register_driver(&sil_pci_driver); |
1da177e4 LT |
714 | } |
715 | ||
716 | static void __exit sil_exit(void) | |
717 | { | |
718 | pci_unregister_driver(&sil_pci_driver); | |
719 | } | |
720 | ||
721 | ||
722 | module_init(sil_init); | |
723 | module_exit(sil_exit); |