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1da177e4 LT |
1 | /* |
2 | * sata_sil.c - Silicon Image SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
af36d7f0 | 8 | * Copyright 2003-2005 Red Hat, Inc. |
1da177e4 LT |
9 | * Copyright 2003 Benjamin Herrenschmidt |
10 | * | |
af36d7f0 JG |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
1da177e4 | 29 | * |
953d1137 JG |
30 | * Documentation for SiI 3112: |
31 | * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 | |
32 | * | |
33 | * Other errata and documentation available under NDA. | |
34 | * | |
1da177e4 LT |
35 | */ |
36 | ||
37 | #include <linux/kernel.h> | |
38 | #include <linux/module.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/blkdev.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/interrupt.h> | |
a9524a76 | 44 | #include <linux/device.h> |
1da177e4 LT |
45 | #include <scsi/scsi_host.h> |
46 | #include <linux/libata.h> | |
47 | ||
48 | #define DRV_NAME "sata_sil" | |
8676ce07 | 49 | #define DRV_VERSION "2.0" |
1da177e4 LT |
50 | |
51 | enum { | |
e653a1e6 TH |
52 | /* |
53 | * host flags | |
54 | */ | |
e4e10e3e | 55 | SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), |
e4deec63 | 56 | SIL_FLAG_MOD15WRITE = (1 << 30), |
20888d83 | 57 | |
e653a1e6 | 58 | SIL_DFL_HOST_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
e573890b | 59 | ATA_FLAG_MMIO | ATA_FLAG_HRST_TO_RESUME, |
e4deec63 | 60 | |
e653a1e6 TH |
61 | /* |
62 | * Controller IDs | |
63 | */ | |
1da177e4 | 64 | sil_3112 = 0, |
81c2af35 TH |
65 | sil_3512 = 1, |
66 | sil_3114 = 2, | |
1da177e4 | 67 | |
e653a1e6 TH |
68 | /* |
69 | * Register offsets | |
70 | */ | |
1da177e4 | 71 | SIL_SYSCFG = 0x48, |
e653a1e6 TH |
72 | |
73 | /* | |
74 | * Register bits | |
75 | */ | |
76 | /* SYSCFG */ | |
1da177e4 LT |
77 | SIL_MASK_IDE0_INT = (1 << 22), |
78 | SIL_MASK_IDE1_INT = (1 << 23), | |
79 | SIL_MASK_IDE2_INT = (1 << 24), | |
80 | SIL_MASK_IDE3_INT = (1 << 25), | |
81 | SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, | |
82 | SIL_MASK_4PORT = SIL_MASK_2PORT | | |
83 | SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, | |
84 | ||
e653a1e6 | 85 | /* BMDMA/BMDMA2 */ |
1da177e4 | 86 | SIL_INTR_STEERING = (1 << 1), |
e653a1e6 | 87 | |
20888d83 TH |
88 | SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ |
89 | SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ | |
90 | SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ | |
91 | SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ | |
92 | SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ | |
93 | SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ | |
94 | SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ | |
95 | SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ | |
96 | SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ | |
97 | SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ | |
98 | ||
99 | /* SIEN */ | |
100 | SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ | |
101 | ||
e653a1e6 TH |
102 | /* |
103 | * Others | |
104 | */ | |
1da177e4 LT |
105 | SIL_QUIRK_MOD15WRITE = (1 << 0), |
106 | SIL_QUIRK_UDMA5MAX = (1 << 1), | |
107 | }; | |
108 | ||
109 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
110 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev); | |
111 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
112 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
113 | static void sil_post_set_mode (struct ata_port *ap); | |
cbe88fbc TH |
114 | static irqreturn_t sil_interrupt(int irq, void *dev_instance, |
115 | struct pt_regs *regs); | |
f6aae27e TH |
116 | static void sil_freeze(struct ata_port *ap); |
117 | static void sil_thaw(struct ata_port *ap); | |
1da177e4 | 118 | |
374b1873 | 119 | |
3b7d697d | 120 | static const struct pci_device_id sil_pci_tbl[] = { |
81c2af35 TH |
121 | { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
122 | { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, | |
0ee304d5 | 123 | { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 }, |
1da177e4 | 124 | { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 }, |
81c2af35 TH |
125 | { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, |
126 | { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, | |
127 | { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 }, | |
1da177e4 LT |
128 | { } /* terminate list */ |
129 | }; | |
130 | ||
131 | ||
132 | /* TODO firmware versions should be added - eric */ | |
133 | static const struct sil_drivelist { | |
134 | const char * product; | |
135 | unsigned int quirk; | |
136 | } sil_blacklist [] = { | |
137 | { "ST320012AS", SIL_QUIRK_MOD15WRITE }, | |
138 | { "ST330013AS", SIL_QUIRK_MOD15WRITE }, | |
139 | { "ST340017AS", SIL_QUIRK_MOD15WRITE }, | |
140 | { "ST360015AS", SIL_QUIRK_MOD15WRITE }, | |
141 | { "ST380013AS", SIL_QUIRK_MOD15WRITE }, | |
142 | { "ST380023AS", SIL_QUIRK_MOD15WRITE }, | |
143 | { "ST3120023AS", SIL_QUIRK_MOD15WRITE }, | |
144 | { "ST3160023AS", SIL_QUIRK_MOD15WRITE }, | |
145 | { "ST3120026AS", SIL_QUIRK_MOD15WRITE }, | |
146 | { "ST3200822AS", SIL_QUIRK_MOD15WRITE }, | |
147 | { "ST340014ASL", SIL_QUIRK_MOD15WRITE }, | |
148 | { "ST360014ASL", SIL_QUIRK_MOD15WRITE }, | |
149 | { "ST380011ASL", SIL_QUIRK_MOD15WRITE }, | |
150 | { "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, | |
151 | { "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, | |
152 | { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, | |
153 | { } | |
154 | }; | |
155 | ||
156 | static struct pci_driver sil_pci_driver = { | |
157 | .name = DRV_NAME, | |
158 | .id_table = sil_pci_tbl, | |
159 | .probe = sil_init_one, | |
160 | .remove = ata_pci_remove_one, | |
161 | }; | |
162 | ||
193515d5 | 163 | static struct scsi_host_template sil_sht = { |
1da177e4 LT |
164 | .module = THIS_MODULE, |
165 | .name = DRV_NAME, | |
166 | .ioctl = ata_scsi_ioctl, | |
167 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
168 | .can_queue = ATA_DEF_QUEUE, |
169 | .this_id = ATA_SHT_THIS_ID, | |
170 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
171 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
172 | .emulated = ATA_SHT_EMULATED, | |
173 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
174 | .proc_name = DRV_NAME, | |
175 | .dma_boundary = ATA_DMA_BOUNDARY, | |
176 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 177 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 178 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
179 | }; |
180 | ||
057ace5e | 181 | static const struct ata_port_operations sil_ops = { |
1da177e4 LT |
182 | .port_disable = ata_port_disable, |
183 | .dev_config = sil_dev_config, | |
184 | .tf_load = ata_tf_load, | |
185 | .tf_read = ata_tf_read, | |
186 | .check_status = ata_check_status, | |
187 | .exec_command = ata_exec_command, | |
188 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
189 | .post_set_mode = sil_post_set_mode, |
190 | .bmdma_setup = ata_bmdma_setup, | |
191 | .bmdma_start = ata_bmdma_start, | |
192 | .bmdma_stop = ata_bmdma_stop, | |
193 | .bmdma_status = ata_bmdma_status, | |
194 | .qc_prep = ata_qc_prep, | |
195 | .qc_issue = ata_qc_issue_prot, | |
a6b2c5d4 | 196 | .data_xfer = ata_mmio_data_xfer, |
f6aae27e TH |
197 | .freeze = sil_freeze, |
198 | .thaw = sil_thaw, | |
199 | .error_handler = ata_bmdma_error_handler, | |
200 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
cbe88fbc | 201 | .irq_handler = sil_interrupt, |
1da177e4 LT |
202 | .irq_clear = ata_bmdma_irq_clear, |
203 | .scr_read = sil_scr_read, | |
204 | .scr_write = sil_scr_write, | |
205 | .port_start = ata_port_start, | |
206 | .port_stop = ata_port_stop, | |
374b1873 | 207 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
208 | }; |
209 | ||
98ac62de | 210 | static const struct ata_port_info sil_port_info[] = { |
1da177e4 | 211 | /* sil_3112 */ |
e4deec63 TH |
212 | { |
213 | .sht = &sil_sht, | |
e653a1e6 | 214 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE, |
e4deec63 TH |
215 | .pio_mask = 0x1f, /* pio0-4 */ |
216 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
217 | .udma_mask = 0x3f, /* udma0-5 */ | |
218 | .port_ops = &sil_ops, | |
0ee304d5 TH |
219 | }, |
220 | /* sil_3512 */ | |
1da177e4 LT |
221 | { |
222 | .sht = &sil_sht, | |
e653a1e6 | 223 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
0ee304d5 TH |
224 | .pio_mask = 0x1f, /* pio0-4 */ |
225 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
226 | .udma_mask = 0x3f, /* udma0-5 */ | |
227 | .port_ops = &sil_ops, | |
228 | }, | |
229 | /* sil_3114 */ | |
1da177e4 LT |
230 | { |
231 | .sht = &sil_sht, | |
e653a1e6 | 232 | .host_flags = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
1da177e4 LT |
233 | .pio_mask = 0x1f, /* pio0-4 */ |
234 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
235 | .udma_mask = 0x3f, /* udma0-5 */ | |
236 | .port_ops = &sil_ops, | |
237 | }, | |
238 | }; | |
239 | ||
240 | /* per-port register offsets */ | |
241 | /* TODO: we can probably calculate rather than use a table */ | |
242 | static const struct { | |
243 | unsigned long tf; /* ATA taskfile register block */ | |
244 | unsigned long ctl; /* ATA control/altstatus register block */ | |
245 | unsigned long bmdma; /* DMA register block */ | |
20888d83 | 246 | unsigned long bmdma2; /* DMA register block #2 */ |
48d4ef2a | 247 | unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ |
1da177e4 LT |
248 | unsigned long scr; /* SATA control register block */ |
249 | unsigned long sien; /* SATA Interrupt Enable register */ | |
250 | unsigned long xfer_mode;/* data transfer mode register */ | |
e4e10e3e | 251 | unsigned long sfis_cfg; /* SATA FIS reception config register */ |
1da177e4 LT |
252 | } sil_port[] = { |
253 | /* port 0 ... */ | |
20888d83 TH |
254 | { 0x80, 0x8A, 0x00, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, |
255 | { 0xC0, 0xCA, 0x08, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, | |
256 | { 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, | |
257 | { 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, | |
1da177e4 LT |
258 | /* ... port 3 */ |
259 | }; | |
260 | ||
261 | MODULE_AUTHOR("Jeff Garzik"); | |
262 | MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); | |
263 | MODULE_LICENSE("GPL"); | |
264 | MODULE_DEVICE_TABLE(pci, sil_pci_tbl); | |
265 | MODULE_VERSION(DRV_VERSION); | |
266 | ||
51e9f2ff JG |
267 | static int slow_down = 0; |
268 | module_param(slow_down, int, 0444); | |
269 | MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); | |
270 | ||
374b1873 | 271 | |
1da177e4 LT |
272 | static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) |
273 | { | |
274 | u8 cache_line = 0; | |
275 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); | |
276 | return cache_line; | |
277 | } | |
278 | ||
279 | static void sil_post_set_mode (struct ata_port *ap) | |
280 | { | |
281 | struct ata_host_set *host_set = ap->host_set; | |
282 | struct ata_device *dev; | |
ea6ba10b JG |
283 | void __iomem *addr = |
284 | host_set->mmio_base + sil_port[ap->port_no].xfer_mode; | |
1da177e4 LT |
285 | u32 tmp, dev_mode[2]; |
286 | unsigned int i; | |
287 | ||
288 | for (i = 0; i < 2; i++) { | |
289 | dev = &ap->device[i]; | |
e1211e3f | 290 | if (!ata_dev_enabled(dev)) |
1da177e4 LT |
291 | dev_mode[i] = 0; /* PIO0/1/2 */ |
292 | else if (dev->flags & ATA_DFLAG_PIO) | |
293 | dev_mode[i] = 1; /* PIO3/4 */ | |
294 | else | |
295 | dev_mode[i] = 3; /* UDMA */ | |
296 | /* value 2 indicates MDMA */ | |
297 | } | |
298 | ||
299 | tmp = readl(addr); | |
300 | tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); | |
301 | tmp |= dev_mode[0]; | |
302 | tmp |= (dev_mode[1] << 4); | |
303 | writel(tmp, addr); | |
304 | readl(addr); /* flush */ | |
305 | } | |
306 | ||
307 | static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg) | |
308 | { | |
309 | unsigned long offset = ap->ioaddr.scr_addr; | |
310 | ||
311 | switch (sc_reg) { | |
312 | case SCR_STATUS: | |
313 | return offset + 4; | |
314 | case SCR_ERROR: | |
315 | return offset + 8; | |
316 | case SCR_CONTROL: | |
317 | return offset; | |
318 | default: | |
319 | /* do nothing */ | |
320 | break; | |
321 | } | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
327 | { | |
9aa36e89 | 328 | void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
1da177e4 LT |
329 | if (mmio) |
330 | return readl(mmio); | |
331 | return 0xffffffffU; | |
332 | } | |
333 | ||
334 | static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
335 | { | |
9aa36e89 | 336 | void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg); |
1da177e4 LT |
337 | if (mmio) |
338 | writel(val, mmio); | |
339 | } | |
340 | ||
cbe88fbc TH |
341 | static void sil_host_intr(struct ata_port *ap, u32 bmdma2) |
342 | { | |
343 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
344 | u8 status; | |
345 | ||
e573890b | 346 | if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { |
d4c85325 TH |
347 | u32 serror; |
348 | ||
349 | /* SIEN doesn't mask SATA IRQs on some 3112s. Those | |
350 | * controllers continue to assert IRQ as long as | |
351 | * SError bits are pending. Clear SError immediately. | |
352 | */ | |
353 | serror = sil_scr_read(ap, SCR_ERROR); | |
354 | sil_scr_write(ap, SCR_ERROR, serror); | |
355 | ||
356 | /* Trigger hotplug and accumulate SError only if the | |
357 | * port isn't already frozen. Otherwise, PHY events | |
358 | * during hardreset makes controllers with broken SIEN | |
359 | * repeat probing needlessly. | |
360 | */ | |
361 | if (!(ap->flags & ATA_FLAG_FROZEN)) { | |
362 | ata_ehi_hotplugged(&ap->eh_info); | |
363 | ap->eh_info.serror |= serror; | |
364 | } | |
365 | ||
e573890b TH |
366 | goto freeze; |
367 | } | |
368 | ||
cbe88fbc TH |
369 | if (unlikely(!qc || qc->tf.ctl & ATA_NIEN)) |
370 | goto freeze; | |
371 | ||
372 | /* Check whether we are expecting interrupt in this state */ | |
373 | switch (ap->hsm_task_state) { | |
374 | case HSM_ST_FIRST: | |
375 | /* Some pre-ATAPI-4 devices assert INTRQ | |
376 | * at this state when ready to receive CDB. | |
377 | */ | |
378 | ||
379 | /* Check the ATA_DFLAG_CDB_INTR flag is enough here. | |
380 | * The flag was turned on only for atapi devices. | |
381 | * No need to check is_atapi_taskfile(&qc->tf) again. | |
382 | */ | |
383 | if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) | |
384 | goto err_hsm; | |
385 | break; | |
386 | case HSM_ST_LAST: | |
387 | if (qc->tf.protocol == ATA_PROT_DMA || | |
388 | qc->tf.protocol == ATA_PROT_ATAPI_DMA) { | |
389 | /* clear DMA-Start bit */ | |
390 | ap->ops->bmdma_stop(qc); | |
391 | ||
392 | if (bmdma2 & SIL_DMA_ERROR) { | |
393 | qc->err_mask |= AC_ERR_HOST_BUS; | |
394 | ap->hsm_task_state = HSM_ST_ERR; | |
395 | } | |
396 | } | |
397 | break; | |
398 | case HSM_ST: | |
399 | break; | |
400 | default: | |
401 | goto err_hsm; | |
402 | } | |
403 | ||
404 | /* check main status, clearing INTRQ */ | |
405 | status = ata_chk_status(ap); | |
406 | if (unlikely(status & ATA_BUSY)) | |
407 | goto err_hsm; | |
408 | ||
409 | /* ack bmdma irq events */ | |
410 | ata_bmdma_irq_clear(ap); | |
411 | ||
412 | /* kick HSM in the ass */ | |
413 | ata_hsm_move(ap, qc, status, 0); | |
414 | ||
415 | return; | |
416 | ||
417 | err_hsm: | |
418 | qc->err_mask |= AC_ERR_HSM; | |
419 | freeze: | |
420 | ata_port_freeze(ap); | |
421 | } | |
422 | ||
423 | static irqreturn_t sil_interrupt(int irq, void *dev_instance, | |
424 | struct pt_regs *regs) | |
425 | { | |
426 | struct ata_host_set *host_set = dev_instance; | |
427 | void __iomem *mmio_base = host_set->mmio_base; | |
428 | int handled = 0; | |
429 | int i; | |
430 | ||
431 | spin_lock(&host_set->lock); | |
432 | ||
433 | for (i = 0; i < host_set->n_ports; i++) { | |
434 | struct ata_port *ap = host_set->ports[i]; | |
435 | u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); | |
436 | ||
437 | if (unlikely(!ap || ap->flags & ATA_FLAG_DISABLED)) | |
438 | continue; | |
439 | ||
23fa9618 TH |
440 | if (bmdma2 == 0xffffffff || |
441 | !(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) | |
cbe88fbc TH |
442 | continue; |
443 | ||
444 | sil_host_intr(ap, bmdma2); | |
445 | handled = 1; | |
446 | } | |
447 | ||
448 | spin_unlock(&host_set->lock); | |
449 | ||
450 | return IRQ_RETVAL(handled); | |
451 | } | |
452 | ||
f6aae27e TH |
453 | static void sil_freeze(struct ata_port *ap) |
454 | { | |
455 | void __iomem *mmio_base = ap->host_set->mmio_base; | |
456 | u32 tmp; | |
457 | ||
e573890b TH |
458 | /* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ |
459 | writel(0, mmio_base + sil_port[ap->port_no].sien); | |
460 | ||
f6aae27e TH |
461 | /* plug IRQ */ |
462 | tmp = readl(mmio_base + SIL_SYSCFG); | |
463 | tmp |= SIL_MASK_IDE0_INT << ap->port_no; | |
464 | writel(tmp, mmio_base + SIL_SYSCFG); | |
465 | readl(mmio_base + SIL_SYSCFG); /* flush */ | |
466 | } | |
467 | ||
468 | static void sil_thaw(struct ata_port *ap) | |
469 | { | |
470 | void __iomem *mmio_base = ap->host_set->mmio_base; | |
471 | u32 tmp; | |
472 | ||
473 | /* clear IRQ */ | |
474 | ata_chk_status(ap); | |
475 | ata_bmdma_irq_clear(ap); | |
476 | ||
e573890b TH |
477 | /* turn on SATA IRQ */ |
478 | writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); | |
479 | ||
f6aae27e TH |
480 | /* turn on IRQ */ |
481 | tmp = readl(mmio_base + SIL_SYSCFG); | |
482 | tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); | |
483 | writel(tmp, mmio_base + SIL_SYSCFG); | |
484 | } | |
485 | ||
1da177e4 LT |
486 | /** |
487 | * sil_dev_config - Apply device/host-specific errata fixups | |
488 | * @ap: Port containing device to be examined | |
489 | * @dev: Device to be examined | |
490 | * | |
491 | * After the IDENTIFY [PACKET] DEVICE step is complete, and a | |
492 | * device is known to be present, this function is called. | |
493 | * We apply two errata fixups which are specific to Silicon Image, | |
494 | * a Seagate and a Maxtor fixup. | |
495 | * | |
496 | * For certain Seagate devices, we must limit the maximum sectors | |
497 | * to under 8K. | |
498 | * | |
499 | * For certain Maxtor devices, we must not program the drive | |
500 | * beyond udma5. | |
501 | * | |
502 | * Both fixups are unfairly pessimistic. As soon as I get more | |
503 | * information on these errata, I will create a more exhaustive | |
504 | * list, and apply the fixups to only the specific | |
505 | * devices/hosts/firmwares that need it. | |
506 | * | |
507 | * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted | |
508 | * The Maxtor quirk is in the blacklist, but I'm keeping the original | |
509 | * pessimistic fix for the following reasons... | |
510 | * - There seems to be less info on it, only one device gleaned off the | |
511 | * Windows driver, maybe only one is affected. More info would be greatly | |
512 | * appreciated. | |
513 | * - But then again UDMA5 is hardly anything to complain about | |
514 | */ | |
515 | static void sil_dev_config(struct ata_port *ap, struct ata_device *dev) | |
516 | { | |
517 | unsigned int n, quirks = 0; | |
2e02671d | 518 | unsigned char model_num[41]; |
1da177e4 | 519 | |
6a62a04d | 520 | ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num)); |
1da177e4 | 521 | |
8a60a071 | 522 | for (n = 0; sil_blacklist[n].product; n++) |
2e02671d | 523 | if (!strcmp(sil_blacklist[n].product, model_num)) { |
1da177e4 LT |
524 | quirks = sil_blacklist[n].quirk; |
525 | break; | |
526 | } | |
8a60a071 | 527 | |
1da177e4 | 528 | /* limit requests to 15 sectors */ |
51e9f2ff JG |
529 | if (slow_down || |
530 | ((ap->flags & SIL_FLAG_MOD15WRITE) && | |
531 | (quirks & SIL_QUIRK_MOD15WRITE))) { | |
f15a1daf TH |
532 | ata_dev_printk(dev, KERN_INFO, "applying Seagate errata fix " |
533 | "(mod15write workaround)\n"); | |
b00eec1d | 534 | dev->max_sectors = 15; |
1da177e4 LT |
535 | return; |
536 | } | |
537 | ||
538 | /* limit to udma5 */ | |
539 | if (quirks & SIL_QUIRK_UDMA5MAX) { | |
f15a1daf TH |
540 | ata_dev_printk(dev, KERN_INFO, |
541 | "applying Maxtor errata fix %s\n", model_num); | |
5a529139 | 542 | dev->udma_mask &= ATA_UDMA5; |
1da177e4 LT |
543 | return; |
544 | } | |
545 | } | |
546 | ||
547 | static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
548 | { | |
549 | static int printed_version; | |
550 | struct ata_probe_ent *probe_ent = NULL; | |
551 | unsigned long base; | |
ea6ba10b | 552 | void __iomem *mmio_base; |
1da177e4 LT |
553 | int rc; |
554 | unsigned int i; | |
555 | int pci_dev_busy = 0; | |
f6aae27e | 556 | u32 tmp; |
1da177e4 LT |
557 | u8 cls; |
558 | ||
559 | if (!printed_version++) | |
a9524a76 | 560 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 561 | |
1da177e4 LT |
562 | rc = pci_enable_device(pdev); |
563 | if (rc) | |
564 | return rc; | |
565 | ||
566 | rc = pci_request_regions(pdev, DRV_NAME); | |
567 | if (rc) { | |
568 | pci_dev_busy = 1; | |
569 | goto err_out; | |
570 | } | |
571 | ||
572 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
573 | if (rc) | |
574 | goto err_out_regions; | |
575 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
576 | if (rc) | |
577 | goto err_out_regions; | |
578 | ||
9a531443 | 579 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
1da177e4 LT |
580 | if (probe_ent == NULL) { |
581 | rc = -ENOMEM; | |
582 | goto err_out_regions; | |
583 | } | |
584 | ||
1da177e4 LT |
585 | INIT_LIST_HEAD(&probe_ent->node); |
586 | probe_ent->dev = pci_dev_to_dev(pdev); | |
587 | probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops; | |
588 | probe_ent->sht = sil_port_info[ent->driver_data].sht; | |
589 | probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2; | |
590 | probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask; | |
591 | probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask; | |
592 | probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask; | |
593 | probe_ent->irq = pdev->irq; | |
594 | probe_ent->irq_flags = SA_SHIRQ; | |
595 | probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags; | |
596 | ||
374b1873 | 597 | mmio_base = pci_iomap(pdev, 5, 0); |
1da177e4 LT |
598 | if (mmio_base == NULL) { |
599 | rc = -ENOMEM; | |
600 | goto err_out_free_ent; | |
601 | } | |
602 | ||
603 | probe_ent->mmio_base = mmio_base; | |
604 | ||
605 | base = (unsigned long) mmio_base; | |
606 | ||
607 | for (i = 0; i < probe_ent->n_ports; i++) { | |
608 | probe_ent->port[i].cmd_addr = base + sil_port[i].tf; | |
609 | probe_ent->port[i].altstatus_addr = | |
610 | probe_ent->port[i].ctl_addr = base + sil_port[i].ctl; | |
611 | probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma; | |
612 | probe_ent->port[i].scr_addr = base + sil_port[i].scr; | |
613 | ata_std_ports(&probe_ent->port[i]); | |
614 | } | |
615 | ||
616 | /* Initialize FIFO PCI bus arbitration */ | |
617 | cls = sil_get_device_cache_line(pdev); | |
618 | if (cls) { | |
619 | cls >>= 3; | |
620 | cls++; /* cls = (line_size/8)+1 */ | |
48d4ef2a TH |
621 | for (i = 0; i < probe_ent->n_ports; i++) |
622 | writew(cls << 8 | cls, | |
623 | mmio_base + sil_port[i].fifo_cfg); | |
1da177e4 | 624 | } else |
a9524a76 | 625 | dev_printk(KERN_WARNING, &pdev->dev, |
48d4ef2a | 626 | "cache line size not set. Driver may not function\n"); |
1da177e4 | 627 | |
e4e10e3e TH |
628 | /* Apply R_ERR on DMA activate FIS errata workaround */ |
629 | if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) { | |
630 | int cnt; | |
631 | ||
632 | for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) { | |
633 | tmp = readl(mmio_base + sil_port[i].sfis_cfg); | |
634 | if ((tmp & 0x3) != 0x01) | |
635 | continue; | |
636 | if (!cnt) | |
637 | dev_printk(KERN_INFO, &pdev->dev, | |
638 | "Applying R_ERR on DMA activate " | |
639 | "FIS errata fix\n"); | |
640 | writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); | |
641 | cnt++; | |
642 | } | |
643 | } | |
644 | ||
1da177e4 | 645 | if (ent->driver_data == sil_3114) { |
1da177e4 | 646 | /* flip the magic "make 4 ports work" bit */ |
48d4ef2a | 647 | tmp = readl(mmio_base + sil_port[2].bmdma); |
1da177e4 LT |
648 | if ((tmp & SIL_INTR_STEERING) == 0) |
649 | writel(tmp | SIL_INTR_STEERING, | |
48d4ef2a | 650 | mmio_base + sil_port[2].bmdma); |
1da177e4 LT |
651 | } |
652 | ||
1da177e4 LT |
653 | pci_set_master(pdev); |
654 | ||
655 | /* FIXME: check ata_device_add return value */ | |
656 | ata_device_add(probe_ent); | |
657 | kfree(probe_ent); | |
658 | ||
659 | return 0; | |
660 | ||
661 | err_out_free_ent: | |
662 | kfree(probe_ent); | |
663 | err_out_regions: | |
664 | pci_release_regions(pdev); | |
665 | err_out: | |
666 | if (!pci_dev_busy) | |
667 | pci_disable_device(pdev); | |
668 | return rc; | |
669 | } | |
670 | ||
671 | static int __init sil_init(void) | |
672 | { | |
673 | return pci_module_init(&sil_pci_driver); | |
674 | } | |
675 | ||
676 | static void __exit sil_exit(void) | |
677 | { | |
678 | pci_unregister_driver(&sil_pci_driver); | |
679 | } | |
680 | ||
681 | ||
682 | module_init(sil_init); | |
683 | module_exit(sil_exit); |