[mirror_ubuntu-hirsute-kernel.git] / drivers / scsi / sata_sil.c

/*
 *  sata_sil.c - Silicon Image SATA
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003-2005 Red Hat, Inc.
 *  Copyright 2003 Benjamin Herrenschmidt
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Documentation for SiI 3112:
 *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
 *
 *  Other errata and documentation available under NDA.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_sil"
#define DRV_VERSION	"1.0"

enum {
	/*
	 * host flags
	 */
	SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
	SIL_FLAG_MOD15WRITE	= (1 << 30),
	SIL_DFL_HOST_FLAGS	= ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				  ATA_FLAG_MMIO,

	/*
	 * Controller IDs
	 */
	sil_3112		= 0,
	sil_3512		= 1,
	sil_3114		= 2,

	/*
	 * Register offsets
	 */
	SIL_SYSCFG		= 0x48,

	/*
	 * Register bits
	 */
	/* SYSCFG */
	SIL_MASK_IDE0_INT	= (1 << 22),
	SIL_MASK_IDE1_INT	= (1 << 23),
	SIL_MASK_IDE2_INT	= (1 << 24),
	SIL_MASK_IDE3_INT	= (1 << 25),
	SIL_MASK_2PORT		= SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
	SIL_MASK_4PORT		= SIL_MASK_2PORT |
				  SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,

	/* BMDMA/BMDMA2 */
	SIL_INTR_STEERING	= (1 << 1),

	/*
	 * Others
	 */
	SIL_QUIRK_MOD15WRITE	= (1 << 0),
	SIL_QUIRK_UDMA5MAX	= (1 << 1),
};

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static void sil_post_set_mode (struct ata_port *ap);
static void sil_freeze(struct ata_port *ap);
static void sil_thaw(struct ata_port *ap);


static const struct pci_device_id sil_pci_tbl[] = {
	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 },
	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	{ }	/* terminate list */
};


/* TODO firmware versions should be added - eric */
static const struct sil_drivelist {
	const char * product;
	unsigned int quirk;
} sil_blacklist [] = {
	{ "ST320012AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST330013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST340017AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST360015AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380013AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST380023AS",		SIL_QUIRK_MOD15WRITE },
	{ "ST3120023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160023AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120026AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST3200822AS",	SIL_QUIRK_MOD15WRITE },
	{ "ST340014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST360014ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST380011ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3120022ASL",	SIL_QUIRK_MOD15WRITE },
	{ "ST3160021ASL",	SIL_QUIRK_MOD15WRITE },
	{ "Maxtor 4D060H3",	SIL_QUIRK_UDMA5MAX },
	{ }
};

static struct pci_driver sil_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sil_pci_tbl,
	.probe			= sil_init_one,
	.remove			= ata_pci_remove_one,
};

static struct scsi_host_template sil_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
};

static const struct ata_port_operations sil_ops = {
	.port_disable		= ata_port_disable,
	.dev_config		= sil_dev_config,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.probe_reset		= ata_std_probe_reset,
	.post_set_mode		= sil_post_set_mode,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_mmio_data_xfer,
	.freeze			= sil_freeze,
	.thaw			= sil_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= sil_scr_read,
	.scr_write		= sil_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_pci_host_stop,
};

static const struct ata_port_info sil_port_info[] = {
	/* sil_3112 */
	{
		.sht		= &sil_sht,
		.host_flags	= SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
	/* sil_3512 */
	{
		.sht		= &sil_sht,
		.host_flags	= SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
	/* sil_3114 */
	{
		.sht		= &sil_sht,
		.host_flags	= SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
		.pio_mask	= 0x1f,			/* pio0-4 */
		.mwdma_mask	= 0x07,			/* mwdma0-2 */
		.udma_mask	= 0x3f,			/* udma0-5 */
		.port_ops	= &sil_ops,
	},
};

/* per-port register offsets */
/* TODO: we can probably calculate rather than use a table */
static const struct {
	unsigned long tf;	/* ATA taskfile register block */
	unsigned long ctl;	/* ATA control/altstatus register block */
	unsigned long bmdma;	/* DMA register block */
	unsigned long fifo_cfg;	/* FIFO Valid Byte Count and Control */
	unsigned long scr;	/* SATA control register block */
	unsigned long sien;	/* SATA Interrupt Enable register */
	unsigned long xfer_mode;/* data transfer mode register */
	unsigned long sfis_cfg;	/* SATA FIS reception config register */
} sil_port[] = {
	/* port 0 ... */
	{ 0x80, 0x8A, 0x00, 0x40, 0x100, 0x148, 0xb4, 0x14c },
	{ 0xC0, 0xCA, 0x08, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
	{ 0x280, 0x28A, 0x200, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
	{ 0x2C0, 0x2CA, 0x208, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
	/* ... port 3 */
};

MODULE_AUTHOR("Jeff Garzik");
MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static int slow_down = 0;
module_param(slow_down, int, 0444);
MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");


static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
{
	u8 cache_line = 0;
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	return cache_line;
}

static void sil_post_set_mode (struct ata_port *ap)
{
	struct ata_host_set *host_set = ap->host_set;
	struct ata_device *dev;
	void __iomem *addr =
		host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
	u32 tmp, dev_mode[2];
	unsigned int i;

	for (i = 0; i < 2; i++) {
		dev = &ap->device[i];
		if (!ata_dev_enabled(dev))
			dev_mode[i] = 0;	/* PIO0/1/2 */
		else if (dev->flags & ATA_DFLAG_PIO)
			dev_mode[i] = 1;	/* PIO3/4 */
		else
			dev_mode[i] = 3;	/* UDMA */
		/* value 2 indicates MDMA */
	}

	tmp = readl(addr);
	tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
	tmp |= dev_mode[0];
	tmp |= (dev_mode[1] << 4);
	writel(tmp, addr);
	readl(addr);	/* flush */
}

static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
{
	unsigned long offset = ap->ioaddr.scr_addr;

	switch (sc_reg) {
	case SCR_STATUS:
		return offset + 4;
	case SCR_ERROR:
		return offset + 8;
	case SCR_CONTROL:
		return offset;
	default:
		/* do nothing */
		break;
	}

	return 0;
}

static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		return readl(mmio);
	return 0xffffffffU;
}

static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
	if (mmio)
		writel(val, mmio);
}

static void sil_freeze(struct ata_port *ap)
{
	void __iomem *mmio_base = ap->host_set->mmio_base;
	u32 tmp;

	/* plug IRQ */
	tmp = readl(mmio_base + SIL_SYSCFG);
	tmp |= SIL_MASK_IDE0_INT << ap->port_no;
	writel(tmp, mmio_base + SIL_SYSCFG);
	readl(mmio_base + SIL_SYSCFG);	/* flush */
}

static void sil_thaw(struct ata_port *ap)
{
	void __iomem *mmio_base = ap->host_set->mmio_base;
	u32 tmp;

	/* clear IRQ */
	ata_chk_status(ap);
	ata_bmdma_irq_clear(ap);

	/* turn on IRQ */
	tmp = readl(mmio_base + SIL_SYSCFG);
	tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
	writel(tmp, mmio_base + SIL_SYSCFG);
}

/**
 *	sil_dev_config - Apply device/host-specific errata fixups
 *	@ap: Port containing device to be examined
 *	@dev: Device to be examined
 *
 *	After the IDENTIFY [PACKET] DEVICE step is complete, and a
 *	device is known to be present, this function is called.
 *	We apply two errata fixups which are specific to Silicon Image,
 *	a Seagate and a Maxtor fixup.
 *
 *	For certain Seagate devices, we must limit the maximum sectors
 *	to under 8K.
 *
 *	For certain Maxtor devices, we must not program the drive
 *	beyond udma5.
 *
 *	Both fixups are unfairly pessimistic.  As soon as I get more
 *	information on these errata, I will create a more exhaustive
 *	list, and apply the fixups to only the specific
 *	devices/hosts/firmwares that need it.
 *
 *	20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
 *	The Maxtor quirk is in the blacklist, but I'm keeping the original
 *	pessimistic fix for the following reasons...
 *	- There seems to be less info on it, only one device gleaned off the
 *	Windows	driver, maybe only one is affected.  More info would be greatly
 *	appreciated.
 *	- But then again UDMA5 is hardly anything to complain about
 */
static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
{
	unsigned int n, quirks = 0;
	unsigned char model_num[41];

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));

	for (n = 0; sil_blacklist[n].product; n++)
		if (!strcmp(sil_blacklist[n].product, model_num)) {
			quirks = sil_blacklist[n].quirk;
			break;
		}

	/* limit requests to 15 sectors */
	if (slow_down ||
	    ((ap->flags & SIL_FLAG_MOD15WRITE) &&
	     (quirks & SIL_QUIRK_MOD15WRITE))) {
		ata_dev_printk(dev, KERN_INFO, "applying Seagate errata fix "
			       "(mod15write workaround)\n");
		dev->max_sectors = 15;
		return;
	}

	/* limit to udma5 */
	if (quirks & SIL_QUIRK_UDMA5MAX) {
		ata_dev_printk(dev, KERN_INFO,
			       "applying Maxtor errata fix %s\n", model_num);
		dev->udma_mask &= ATA_UDMA5;
		return;
	}
}

static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void __iomem *mmio_base;
	int rc;
	unsigned int i;
	int pci_dev_busy = 0;
	u32 tmp;
	u8 cls;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	INIT_LIST_HEAD(&probe_ent->node);
	probe_ent->dev = pci_dev_to_dev(pdev);
	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
       	probe_ent->irq = pdev->irq;
       	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;

	mmio_base = pci_iomap(pdev, 5, 0);
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}

	probe_ent->mmio_base = mmio_base;

	base = (unsigned long) mmio_base;

	for (i = 0; i < probe_ent->n_ports; i++) {
		probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
		probe_ent->port[i].altstatus_addr =
		probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
		probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
		probe_ent->port[i].scr_addr = base + sil_port[i].scr;
		ata_std_ports(&probe_ent->port[i]);
	}

	/* Initialize FIFO PCI bus arbitration */
	cls = sil_get_device_cache_line(pdev);
	if (cls) {
		cls >>= 3;
		cls++;  /* cls = (line_size/8)+1 */
		for (i = 0; i < probe_ent->n_ports; i++)
			writew(cls << 8 | cls,
			       mmio_base + sil_port[i].fifo_cfg);
	} else
		dev_printk(KERN_WARNING, &pdev->dev,
			   "cache line size not set.  Driver may not function\n");

	/* Apply R_ERR on DMA activate FIS errata workaround */
	if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
		int cnt;

		for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) {
			tmp = readl(mmio_base + sil_port[i].sfis_cfg);
			if ((tmp & 0x3) != 0x01)
				continue;
			if (!cnt)
				dev_printk(KERN_INFO, &pdev->dev,
					   "Applying R_ERR on DMA activate "
					   "FIS errata fix\n");
			writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
			cnt++;
		}
	}

	if (ent->driver_data == sil_3114) {
		/* flip the magic "make 4 ports work" bit */
		tmp = readl(mmio_base + sil_port[2].bmdma);
		if ((tmp & SIL_INTR_STEERING) == 0)
			writel(tmp | SIL_INTR_STEERING,
			       mmio_base + sil_port[2].bmdma);
	}

	/* mask all SATA phy-related interrupts */
	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	for (i = 0; i < probe_ent->n_ports; i++)
		writel(0, mmio_base + sil_port[i].sien);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

static int __init sil_init(void)
{
	return pci_module_init(&sil_pci_driver);
}

static void __exit sil_exit(void)
{
	pci_unregister_driver(&sil_pci_driver);
}


module_init(sil_init);
module_exit(sil_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sil.c - Silicon Image SATA
	3	*
	4	* Maintained by: Jeff Garzik <jgarzik@pobox.com>
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
af36d7f0	8	* Copyright 2003-2005 Red Hat, Inc.
1da177e4 LT	9	* Copyright 2003 Benjamin Herrenschmidt
1da177e4 LT	10	*
af36d7f0 JG	11	*
	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License as published by
	14	* the Free Software Foundation; either version 2, or (at your option)
	15	* any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; see the file COPYING. If not, write to
	24	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	25	*
	26	*
	27	* libata documentation is available via 'make {ps\|pdf}docs',
	28	* as Documentation/DocBook/libata.*
1da177e4	29	*
953d1137 JG	30	* Documentation for SiI 3112:
	31	* http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
	32	*
	33	* Other errata and documentation available under NDA.
	34	*
1da177e4 LT	35	*/
	36
	37	#include <linux/kernel.h>
	38	#include <linux/module.h>
	39	#include <linux/pci.h>
	40	#include <linux/init.h>
	41	#include <linux/blkdev.h>
	42	#include <linux/delay.h>
	43	#include <linux/interrupt.h>
a9524a76	44	#include <linux/device.h>
1da177e4 LT	45	#include <scsi/scsi_host.h>
	46	#include <linux/libata.h>
	47
	48	#define DRV_NAME "sata_sil"
af64371a	49	#define DRV_VERSION "1.0"
1da177e4 LT	50
1da177e4 LT	51	enum {
e653a1e6 TH	52	/*
	53	* host flags
	54	*/
e4e10e3e	55	SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
e4deec63	56	SIL_FLAG_MOD15WRITE = (1 << 30),
e653a1e6 TH	57	SIL_DFL_HOST_FLAGS = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
e653a1e6 TH	58	ATA_FLAG_MMIO,
e4deec63	59
e653a1e6 TH	60	/*
	61	* Controller IDs
	62	*/
1da177e4	63	sil_3112 = 0,
81c2af35 TH	64	sil_3512 = 1,
81c2af35 TH	65	sil_3114 = 2,
1da177e4	66
e653a1e6 TH	67	/*
	68	* Register offsets
	69	*/
1da177e4	70	SIL_SYSCFG = 0x48,
e653a1e6 TH	71
	72	/*
	73	* Register bits
	74	*/
	75	/* SYSCFG */
1da177e4 LT	76	SIL_MASK_IDE0_INT = (1 << 22),
	77	SIL_MASK_IDE1_INT = (1 << 23),
	78	SIL_MASK_IDE2_INT = (1 << 24),
	79	SIL_MASK_IDE3_INT = (1 << 25),
	80	SIL_MASK_2PORT = SIL_MASK_IDE0_INT \| SIL_MASK_IDE1_INT,
	81	SIL_MASK_4PORT = SIL_MASK_2PORT \|
	82	SIL_MASK_IDE2_INT \| SIL_MASK_IDE3_INT,
	83
e653a1e6	84	/* BMDMA/BMDMA2 */
1da177e4	85	SIL_INTR_STEERING = (1 << 1),
e653a1e6 TH	86
	87	/*
	88	* Others
	89	*/
1da177e4 LT	90	SIL_QUIRK_MOD15WRITE = (1 << 0),
	91	SIL_QUIRK_UDMA5MAX = (1 << 1),
	92	};
	93
	94	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	95	static void sil_dev_config(struct ata_port ap, struct ata_device dev);
	96	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
	97	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	98	static void sil_post_set_mode (struct ata_port *ap);
f6aae27e TH	99	static void sil_freeze(struct ata_port *ap);
f6aae27e TH	100	static void sil_thaw(struct ata_port *ap);
1da177e4	101
374b1873	102
3b7d697d	103	static const struct pci_device_id sil_pci_tbl[] = {
81c2af35 TH	104	{ 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
81c2af35 TH	105	{ 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
0ee304d5	106	{ 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 },
1da177e4	107	{ 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
81c2af35 TH	108	{ 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	109	{ 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
	110	{ 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
1da177e4 LT	111	{ } /* terminate list */
	112	};
	113
	114
	115	/* TODO firmware versions should be added - eric */
	116	static const struct sil_drivelist {
	117	const char * product;
	118	unsigned int quirk;
	119	} sil_blacklist [] = {
	120	{ "ST320012AS", SIL_QUIRK_MOD15WRITE },
	121	{ "ST330013AS", SIL_QUIRK_MOD15WRITE },
	122	{ "ST340017AS", SIL_QUIRK_MOD15WRITE },
	123	{ "ST360015AS", SIL_QUIRK_MOD15WRITE },
	124	{ "ST380013AS", SIL_QUIRK_MOD15WRITE },
	125	{ "ST380023AS", SIL_QUIRK_MOD15WRITE },
	126	{ "ST3120023AS", SIL_QUIRK_MOD15WRITE },
	127	{ "ST3160023AS", SIL_QUIRK_MOD15WRITE },
	128	{ "ST3120026AS", SIL_QUIRK_MOD15WRITE },
	129	{ "ST3200822AS", SIL_QUIRK_MOD15WRITE },
	130	{ "ST340014ASL", SIL_QUIRK_MOD15WRITE },
	131	{ "ST360014ASL", SIL_QUIRK_MOD15WRITE },
	132	{ "ST380011ASL", SIL_QUIRK_MOD15WRITE },
	133	{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE },
	134	{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE },
	135	{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX },
	136	{ }
	137	};
	138
	139	static struct pci_driver sil_pci_driver = {
	140	.name = DRV_NAME,
	141	.id_table = sil_pci_tbl,
	142	.probe = sil_init_one,
	143	.remove = ata_pci_remove_one,
	144	};
	145
193515d5	146	static struct scsi_host_template sil_sht = {
1da177e4 LT	147	.module = THIS_MODULE,
	148	.name = DRV_NAME,
	149	.ioctl = ata_scsi_ioctl,
	150	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	151	.can_queue = ATA_DEF_QUEUE,
	152	.this_id = ATA_SHT_THIS_ID,
	153	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	154	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	155	.emulated = ATA_SHT_EMULATED,
	156	.use_clustering = ATA_SHT_USE_CLUSTERING,
	157	.proc_name = DRV_NAME,
	158	.dma_boundary = ATA_DMA_BOUNDARY,
	159	.slave_configure = ata_scsi_slave_config,
	160	.bios_param = ata_std_bios_param,
1da177e4 LT	161	};
1da177e4 LT	162
057ace5e	163	static const struct ata_port_operations sil_ops = {
1da177e4 LT	164	.port_disable = ata_port_disable,
	165	.dev_config = sil_dev_config,
	166	.tf_load = ata_tf_load,
	167	.tf_read = ata_tf_read,
	168	.check_status = ata_check_status,
	169	.exec_command = ata_exec_command,
	170	.dev_select = ata_std_dev_select,
531db7aa	171	.probe_reset = ata_std_probe_reset,
1da177e4 LT	172	.post_set_mode = sil_post_set_mode,
	173	.bmdma_setup = ata_bmdma_setup,
	174	.bmdma_start = ata_bmdma_start,
	175	.bmdma_stop = ata_bmdma_stop,
	176	.bmdma_status = ata_bmdma_status,
	177	.qc_prep = ata_qc_prep,
	178	.qc_issue = ata_qc_issue_prot,
a6b2c5d4	179	.data_xfer = ata_mmio_data_xfer,
f6aae27e TH	180	.freeze = sil_freeze,
	181	.thaw = sil_thaw,
	182	.error_handler = ata_bmdma_error_handler,
	183	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 LT	184	.irq_handler = ata_interrupt,
	185	.irq_clear = ata_bmdma_irq_clear,
	186	.scr_read = sil_scr_read,
	187	.scr_write = sil_scr_write,
	188	.port_start = ata_port_start,
	189	.port_stop = ata_port_stop,
374b1873	190	.host_stop = ata_pci_host_stop,
1da177e4 LT	191	};
1da177e4 LT	192
98ac62de	193	static const struct ata_port_info sil_port_info[] = {
1da177e4	194	/* sil_3112 */
e4deec63 TH	195	{
e4deec63 TH	196	.sht = &sil_sht,
e653a1e6	197	.host_flags = SIL_DFL_HOST_FLAGS \| SIL_FLAG_MOD15WRITE,
e4deec63 TH	198	.pio_mask = 0x1f, /* pio0-4 */
	199	.mwdma_mask = 0x07, /* mwdma0-2 */
	200	.udma_mask = 0x3f, /* udma0-5 */
	201	.port_ops = &sil_ops,
0ee304d5 TH	202	},
0ee304d5 TH	203	/* sil_3512 */
1da177e4 LT	204	{
1da177e4 LT	205	.sht = &sil_sht,
e653a1e6	206	.host_flags = SIL_DFL_HOST_FLAGS \| SIL_FLAG_RERR_ON_DMA_ACT,
0ee304d5 TH	207	.pio_mask = 0x1f, /* pio0-4 */
	208	.mwdma_mask = 0x07, /* mwdma0-2 */
	209	.udma_mask = 0x3f, /* udma0-5 */
	210	.port_ops = &sil_ops,
	211	},
	212	/* sil_3114 */
1da177e4 LT	213	{
1da177e4 LT	214	.sht = &sil_sht,
e653a1e6	215	.host_flags = SIL_DFL_HOST_FLAGS \| SIL_FLAG_RERR_ON_DMA_ACT,
1da177e4 LT	216	.pio_mask = 0x1f, /* pio0-4 */
	217	.mwdma_mask = 0x07, /* mwdma0-2 */
	218	.udma_mask = 0x3f, /* udma0-5 */
	219	.port_ops = &sil_ops,
	220	},
	221	};
	222
	223	/* per-port register offsets */
	224	/* TODO: we can probably calculate rather than use a table */
	225	static const struct {
	226	unsigned long tf; /* ATA taskfile register block */
	227	unsigned long ctl; /* ATA control/altstatus register block */
	228	unsigned long bmdma; /* DMA register block */
48d4ef2a	229	unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
1da177e4 LT	230	unsigned long scr; /* SATA control register block */
	231	unsigned long sien; /* SATA Interrupt Enable register */
	232	unsigned long xfer_mode;/* data transfer mode register */
e4e10e3e	233	unsigned long sfis_cfg; /* SATA FIS reception config register */
1da177e4 LT	234	} sil_port[] = {
1da177e4 LT	235	/* port 0 ... */
48d4ef2a TH	236	{ 0x80, 0x8A, 0x00, 0x40, 0x100, 0x148, 0xb4, 0x14c },
	237	{ 0xC0, 0xCA, 0x08, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
	238	{ 0x280, 0x28A, 0x200, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
	239	{ 0x2C0, 0x2CA, 0x208, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
1da177e4 LT	240	/* ... port 3 */
	241	};
	242
	243	MODULE_AUTHOR("Jeff Garzik");
	244	MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
	245	MODULE_LICENSE("GPL");
	246	MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
	247	MODULE_VERSION(DRV_VERSION);
	248
51e9f2ff JG	249	static int slow_down = 0;
	250	module_param(slow_down, int, 0444);
	251	MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
	252
374b1873	253
1da177e4 LT	254	static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
	255	{
	256	u8 cache_line = 0;
	257	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
	258	return cache_line;
	259	}
	260
	261	static void sil_post_set_mode (struct ata_port *ap)
	262	{
	263	struct ata_host_set *host_set = ap->host_set;
	264	struct ata_device *dev;
ea6ba10b JG	265	void __iomem *addr =
ea6ba10b JG	266	host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
1da177e4 LT	267	u32 tmp, dev_mode[2];
	268	unsigned int i;
	269
	270	for (i = 0; i < 2; i++) {
	271	dev = &ap->device[i];
e1211e3f	272	if (!ata_dev_enabled(dev))
1da177e4 LT	273	dev_mode[i] = 0; /* PIO0/1/2 */
	274	else if (dev->flags & ATA_DFLAG_PIO)
	275	dev_mode[i] = 1; /* PIO3/4 */
	276	else
	277	dev_mode[i] = 3; /* UDMA */
	278	/* value 2 indicates MDMA */
	279	}
	280
	281	tmp = readl(addr);
	282	tmp &= ~((1<<5) \| (1<<4) \| (1<<1) \| (1<<0));
	283	tmp \|= dev_mode[0];
	284	tmp \|= (dev_mode[1] << 4);
	285	writel(tmp, addr);
	286	readl(addr); /* flush */
	287	}
	288
	289	static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
	290	{
	291	unsigned long offset = ap->ioaddr.scr_addr;
	292
	293	switch (sc_reg) {
	294	case SCR_STATUS:
	295	return offset + 4;
	296	case SCR_ERROR:
	297	return offset + 8;
	298	case SCR_CONTROL:
	299	return offset;
	300	default:
	301	/* do nothing */
	302	break;
	303	}
	304
	305	return 0;
	306	}
	307
	308	static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
	309	{
9aa36e89	310	void __iomem mmio = (void __iomem ) sil_scr_addr(ap, sc_reg);
1da177e4 LT	311	if (mmio)
	312	return readl(mmio);
	313	return 0xffffffffU;
	314	}
	315
	316	static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	317	{
9aa36e89	318	void mmio = (void __iomem ) sil_scr_addr(ap, sc_reg);
1da177e4 LT	319	if (mmio)
	320	writel(val, mmio);
	321	}
	322
f6aae27e TH	323	static void sil_freeze(struct ata_port *ap)
	324	{
	325	void __iomem *mmio_base = ap->host_set->mmio_base;
	326	u32 tmp;
	327
	328	/* plug IRQ */
	329	tmp = readl(mmio_base + SIL_SYSCFG);
	330	tmp \|= SIL_MASK_IDE0_INT << ap->port_no;
	331	writel(tmp, mmio_base + SIL_SYSCFG);
	332	readl(mmio_base + SIL_SYSCFG); /* flush */
	333	}
	334
	335	static void sil_thaw(struct ata_port *ap)
	336	{
	337	void __iomem *mmio_base = ap->host_set->mmio_base;
	338	u32 tmp;
	339
	340	/* clear IRQ */
	341	ata_chk_status(ap);
	342	ata_bmdma_irq_clear(ap);
	343
	344	/* turn on IRQ */
	345	tmp = readl(mmio_base + SIL_SYSCFG);
	346	tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no);
	347	writel(tmp, mmio_base + SIL_SYSCFG);
	348	}
	349
1da177e4 LT	350	/**
	351	* sil_dev_config - Apply device/host-specific errata fixups
	352	* @ap: Port containing device to be examined
	353	* @dev: Device to be examined
	354	*
	355	* After the IDENTIFY [PACKET] DEVICE step is complete, and a
	356	* device is known to be present, this function is called.
	357	* We apply two errata fixups which are specific to Silicon Image,
	358	* a Seagate and a Maxtor fixup.
	359	*
	360	* For certain Seagate devices, we must limit the maximum sectors
	361	* to under 8K.
	362	*
	363	* For certain Maxtor devices, we must not program the drive
	364	* beyond udma5.
	365	*
	366	* Both fixups are unfairly pessimistic. As soon as I get more
	367	* information on these errata, I will create a more exhaustive
	368	* list, and apply the fixups to only the specific
	369	* devices/hosts/firmwares that need it.
	370	*
	371	* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
	372	* The Maxtor quirk is in the blacklist, but I'm keeping the original
	373	* pessimistic fix for the following reasons...
	374	* - There seems to be less info on it, only one device gleaned off the
	375	* Windows driver, maybe only one is affected. More info would be greatly
	376	* appreciated.
	377	* - But then again UDMA5 is hardly anything to complain about
	378	*/
	379	static void sil_dev_config(struct ata_port ap, struct ata_device dev)
	380	{
	381	unsigned int n, quirks = 0;
2e02671d	382	unsigned char model_num[41];
1da177e4	383
6a62a04d	384	ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
1da177e4	385
8a60a071	386	for (n = 0; sil_blacklist[n].product; n++)
2e02671d	387	if (!strcmp(sil_blacklist[n].product, model_num)) {
1da177e4 LT	388	quirks = sil_blacklist[n].quirk;
	389	break;
	390	}
8a60a071	391
1da177e4	392	/* limit requests to 15 sectors */
51e9f2ff JG	393	if (slow_down \|\|
	394	((ap->flags & SIL_FLAG_MOD15WRITE) &&
	395	(quirks & SIL_QUIRK_MOD15WRITE))) {
f15a1daf TH	396	ata_dev_printk(dev, KERN_INFO, "applying Seagate errata fix "
f15a1daf TH	397	"(mod15write workaround)\n");
b00eec1d	398	dev->max_sectors = 15;
1da177e4 LT	399	return;
	400	}
	401
	402	/* limit to udma5 */
	403	if (quirks & SIL_QUIRK_UDMA5MAX) {
f15a1daf TH	404	ata_dev_printk(dev, KERN_INFO,
f15a1daf TH	405	"applying Maxtor errata fix %s\n", model_num);
5a529139	406	dev->udma_mask &= ATA_UDMA5;
1da177e4 LT	407	return;
	408	}
	409	}
	410
	411	static int sil_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	412	{
	413	static int printed_version;
	414	struct ata_probe_ent *probe_ent = NULL;
	415	unsigned long base;
ea6ba10b	416	void __iomem *mmio_base;
1da177e4 LT	417	int rc;
	418	unsigned int i;
	419	int pci_dev_busy = 0;
f6aae27e	420	u32 tmp;
1da177e4 LT	421	u8 cls;
	422
	423	if (!printed_version++)
a9524a76	424	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4	425
1da177e4 LT	426	rc = pci_enable_device(pdev);
	427	if (rc)
	428	return rc;
	429
	430	rc = pci_request_regions(pdev, DRV_NAME);
	431	if (rc) {
	432	pci_dev_busy = 1;
	433	goto err_out;
	434	}
	435
	436	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	437	if (rc)
	438	goto err_out_regions;
	439	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	440	if (rc)
	441	goto err_out_regions;
	442
9a531443	443	probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1da177e4 LT	444	if (probe_ent == NULL) {
	445	rc = -ENOMEM;
	446	goto err_out_regions;
	447	}
	448
1da177e4 LT	449	INIT_LIST_HEAD(&probe_ent->node);
	450	probe_ent->dev = pci_dev_to_dev(pdev);
	451	probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
	452	probe_ent->sht = sil_port_info[ent->driver_data].sht;
	453	probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
	454	probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
	455	probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
	456	probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
	457	probe_ent->irq = pdev->irq;
	458	probe_ent->irq_flags = SA_SHIRQ;
	459	probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
	460
374b1873	461	mmio_base = pci_iomap(pdev, 5, 0);
1da177e4 LT	462	if (mmio_base == NULL) {
	463	rc = -ENOMEM;
	464	goto err_out_free_ent;
	465	}
	466
	467	probe_ent->mmio_base = mmio_base;
	468
	469	base = (unsigned long) mmio_base;
	470
	471	for (i = 0; i < probe_ent->n_ports; i++) {
	472	probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
	473	probe_ent->port[i].altstatus_addr =
	474	probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
	475	probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
	476	probe_ent->port[i].scr_addr = base + sil_port[i].scr;
	477	ata_std_ports(&probe_ent->port[i]);
	478	}
	479
	480	/* Initialize FIFO PCI bus arbitration */
	481	cls = sil_get_device_cache_line(pdev);
	482	if (cls) {
	483	cls >>= 3;
	484	cls++; /* cls = (line_size/8)+1 */
48d4ef2a TH	485	for (i = 0; i < probe_ent->n_ports; i++)
	486	writew(cls << 8 \| cls,
	487	mmio_base + sil_port[i].fifo_cfg);
1da177e4	488	} else
a9524a76	489	dev_printk(KERN_WARNING, &pdev->dev,
48d4ef2a	490	"cache line size not set. Driver may not function\n");
1da177e4	491
e4e10e3e TH	492	/* Apply R_ERR on DMA activate FIS errata workaround */
	493	if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
	494	int cnt;
	495
	496	for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) {
	497	tmp = readl(mmio_base + sil_port[i].sfis_cfg);
	498	if ((tmp & 0x3) != 0x01)
	499	continue;
	500	if (!cnt)
	501	dev_printk(KERN_INFO, &pdev->dev,
	502	"Applying R_ERR on DMA activate "
	503	"FIS errata fix\n");
	504	writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
	505	cnt++;
	506	}
	507	}
	508
1da177e4	509	if (ent->driver_data == sil_3114) {
1da177e4	510	/* flip the magic "make 4 ports work" bit */
48d4ef2a	511	tmp = readl(mmio_base + sil_port[2].bmdma);
1da177e4 LT	512	if ((tmp & SIL_INTR_STEERING) == 0)
1da177e4 LT	513	writel(tmp \| SIL_INTR_STEERING,
48d4ef2a	514	mmio_base + sil_port[2].bmdma);
1da177e4 LT	515	}
	516
	517	/* mask all SATA phy-related interrupts */
	518	/* TODO: unmask bit 6 (SError N bit) for hotplug */
	519	for (i = 0; i < probe_ent->n_ports; i++)
	520	writel(0, mmio_base + sil_port[i].sien);
	521
	522	pci_set_master(pdev);
	523
	524	/* FIXME: check ata_device_add return value */
	525	ata_device_add(probe_ent);
	526	kfree(probe_ent);
	527
	528	return 0;
	529
	530	err_out_free_ent:
	531	kfree(probe_ent);
	532	err_out_regions:
	533	pci_release_regions(pdev);
	534	err_out:
	535	if (!pci_dev_busy)
	536	pci_disable_device(pdev);
	537	return rc;
	538	}
	539
	540	static int __init sil_init(void)
	541	{
	542	return pci_module_init(&sil_pci_driver);
	543	}
	544
	545	static void __exit sil_exit(void)
	546	{
	547	pci_unregister_driver(&sil_pci_driver);
	548	}
	549
	550
	551	module_init(sil_init);
	552	module_exit(sil_exit);