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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/dma-mapping.h> | |
a9524a76 | 27 | #include <linux/device.h> |
edb33667 | 28 | #include <scsi/scsi_host.h> |
193515d5 | 29 | #include <scsi/scsi_cmnd.h> |
edb33667 TH |
30 | #include <linux/libata.h> |
31 | #include <asm/io.h> | |
32 | ||
33 | #define DRV_NAME "sata_sil24" | |
af64371a | 34 | #define DRV_VERSION "0.24" |
edb33667 | 35 | |
edb33667 TH |
36 | /* |
37 | * Port request block (PRB) 32 bytes | |
38 | */ | |
39 | struct sil24_prb { | |
40 | u16 ctrl; | |
41 | u16 prot; | |
42 | u32 rx_cnt; | |
43 | u8 fis[6 * 4]; | |
44 | }; | |
45 | ||
46 | /* | |
47 | * Scatter gather entry (SGE) 16 bytes | |
48 | */ | |
49 | struct sil24_sge { | |
50 | u64 addr; | |
51 | u32 cnt; | |
52 | u32 flags; | |
53 | }; | |
54 | ||
55 | /* | |
56 | * Port multiplier | |
57 | */ | |
58 | struct sil24_port_multiplier { | |
59 | u32 diag; | |
60 | u32 sactive; | |
61 | }; | |
62 | ||
63 | enum { | |
64 | /* | |
65 | * Global controller registers (128 bytes @ BAR0) | |
66 | */ | |
67 | /* 32 bit regs */ | |
68 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
69 | HOST_CTRL = 0x40, | |
70 | HOST_IRQ_STAT = 0x44, | |
71 | HOST_PHY_CFG = 0x48, | |
72 | HOST_BIST_CTRL = 0x50, | |
73 | HOST_BIST_PTRN = 0x54, | |
74 | HOST_BIST_STAT = 0x58, | |
75 | HOST_MEM_BIST_STAT = 0x5c, | |
76 | HOST_FLASH_CMD = 0x70, | |
77 | /* 8 bit regs */ | |
78 | HOST_FLASH_DATA = 0x74, | |
79 | HOST_TRANSITION_DETECT = 0x75, | |
80 | HOST_GPIO_CTRL = 0x76, | |
81 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
82 | HOST_I2C_DATA = 0x7c, | |
83 | HOST_I2C_XFER_CNT = 0x7e, | |
84 | HOST_I2C_CTRL = 0x7f, | |
85 | ||
86 | /* HOST_SLOT_STAT bits */ | |
87 | HOST_SSTAT_ATTN = (1 << 31), | |
88 | ||
7dafc3fd TH |
89 | /* HOST_CTRL bits */ |
90 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ | |
91 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ | |
92 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ | |
93 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ | |
94 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ | |
95 | ||
edb33667 TH |
96 | /* |
97 | * Port registers | |
98 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
99 | */ | |
100 | PORT_REGS_SIZE = 0x2000, | |
101 | PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */ | |
edb33667 TH |
102 | |
103 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ | |
104 | /* 32 bit regs */ | |
83bbecc9 TH |
105 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
106 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
107 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
108 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
109 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 110 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
111 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
112 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
113 | PORT_FIS_CFG = 0x1028, |
114 | PORT_FIFO_THRES = 0x102c, | |
115 | /* 16 bit regs */ | |
116 | PORT_DECODE_ERR_CNT = 0x1040, | |
117 | PORT_DECODE_ERR_THRESH = 0x1042, | |
118 | PORT_CRC_ERR_CNT = 0x1044, | |
119 | PORT_CRC_ERR_THRESH = 0x1046, | |
120 | PORT_HSHK_ERR_CNT = 0x1048, | |
121 | PORT_HSHK_ERR_THRESH = 0x104a, | |
122 | /* 32 bit regs */ | |
123 | PORT_PHY_CFG = 0x1050, | |
124 | PORT_SLOT_STAT = 0x1800, | |
125 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
126 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ | |
127 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
128 | PORT_SCONTROL = 0x1f00, | |
129 | PORT_SSTATUS = 0x1f04, | |
130 | PORT_SERROR = 0x1f08, | |
131 | PORT_SACTIVE = 0x1f0c, | |
132 | ||
133 | /* PORT_CTRL_STAT bits */ | |
134 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
135 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
136 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
137 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 138 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
e382eb1d TH |
139 | PORT_CS_RESUME = (1 << 6), /* port resume */ |
140 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ | |
141 | PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ | |
142 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ | |
edb33667 TH |
143 | |
144 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
145 | /* bits[11:0] are masked */ | |
146 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
147 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
148 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
149 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
150 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
151 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
7dafc3fd TH |
152 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
153 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ | |
154 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ | |
155 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ | |
156 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ | |
3b9f1d0f | 157 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
edb33667 TH |
158 | |
159 | /* bits[27:16] are unmasked (raw) */ | |
160 | PORT_IRQ_RAW_SHIFT = 16, | |
161 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
162 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
163 | ||
164 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
165 | PORT_IRQ_STEER_SHIFT = 30, | |
166 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
167 | ||
168 | /* PORT_CMD_ERR constants */ | |
169 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
170 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
171 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
172 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
173 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
174 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
175 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
176 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
177 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
178 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
179 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
180 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
181 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
182 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
183 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
184 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
185 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
186 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
187 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
64008802 | 188 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
edb33667 | 189 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
83bbecc9 | 190 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 191 | |
d10cb35a TH |
192 | /* bits of PRB control field */ |
193 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
194 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
195 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
196 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
197 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
198 | ||
199 | /* PRB protocol field */ | |
200 | PRB_PROT_PACKET = (1 << 0), | |
201 | PRB_PROT_TCQ = (1 << 1), | |
202 | PRB_PROT_NCQ = (1 << 2), | |
203 | PRB_PROT_READ = (1 << 3), | |
204 | PRB_PROT_WRITE = (1 << 4), | |
205 | PRB_PROT_TRANSPARENT = (1 << 5), | |
206 | ||
edb33667 TH |
207 | /* |
208 | * Other constants | |
209 | */ | |
210 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
211 | SGE_LNK = (1 << 30), /* linked list |
212 | Points to SGT, not SGE */ | |
213 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
214 | data address ignored */ | |
edb33667 TH |
215 | |
216 | /* board id */ | |
217 | BID_SIL3124 = 0, | |
218 | BID_SIL3132 = 1, | |
042c21fd | 219 | BID_SIL3131 = 2, |
edb33667 | 220 | |
9466d85b TH |
221 | /* host flags */ |
222 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
223 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA, | |
37024e8e | 224 | SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ |
9466d85b | 225 | |
edb33667 TH |
226 | IRQ_STAT_4PORTS = 0xf, |
227 | }; | |
228 | ||
69ad185f | 229 | struct sil24_ata_block { |
edb33667 TH |
230 | struct sil24_prb prb; |
231 | struct sil24_sge sge[LIBATA_MAX_PRD]; | |
232 | }; | |
233 | ||
69ad185f TH |
234 | struct sil24_atapi_block { |
235 | struct sil24_prb prb; | |
236 | u8 cdb[16]; | |
237 | struct sil24_sge sge[LIBATA_MAX_PRD - 1]; | |
238 | }; | |
239 | ||
240 | union sil24_cmd_block { | |
241 | struct sil24_ata_block ata; | |
242 | struct sil24_atapi_block atapi; | |
243 | }; | |
244 | ||
edb33667 TH |
245 | /* |
246 | * ap->private_data | |
247 | * | |
248 | * The preview driver always returned 0 for status. We emulate it | |
249 | * here from the previous interrupt. | |
250 | */ | |
251 | struct sil24_port_priv { | |
69ad185f | 252 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 253 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
6a575fa9 | 254 | struct ata_taskfile tf; /* Cached taskfile registers */ |
edb33667 TH |
255 | }; |
256 | ||
257 | /* ap->host_set->private_data */ | |
258 | struct sil24_host_priv { | |
4b4a5eae AV |
259 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ |
260 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ | |
edb33667 TH |
261 | }; |
262 | ||
69ad185f | 263 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
edb33667 | 264 | static u8 sil24_check_status(struct ata_port *ap); |
edb33667 TH |
265 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
266 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); | |
7f726d12 | 267 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
07b73470 | 268 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes); |
edb33667 | 269 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 270 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
edb33667 TH |
271 | static void sil24_irq_clear(struct ata_port *ap); |
272 | static void sil24_eng_timeout(struct ata_port *ap); | |
273 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs); | |
274 | static int sil24_port_start(struct ata_port *ap); | |
275 | static void sil24_port_stop(struct ata_port *ap); | |
276 | static void sil24_host_stop(struct ata_host_set *host_set); | |
277 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
278 | ||
3b7d697d | 279 | static const struct pci_device_id sil24_pci_tbl[] = { |
edb33667 | 280 | { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
4b9d7e04 | 281 | { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
edb33667 | 282 | { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 }, |
042c21fd TH |
283 | { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
284 | { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, | |
1fcce839 | 285 | { } /* terminate list */ |
edb33667 TH |
286 | }; |
287 | ||
288 | static struct pci_driver sil24_pci_driver = { | |
289 | .name = DRV_NAME, | |
290 | .id_table = sil24_pci_tbl, | |
291 | .probe = sil24_init_one, | |
292 | .remove = ata_pci_remove_one, /* safe? */ | |
293 | }; | |
294 | ||
193515d5 | 295 | static struct scsi_host_template sil24_sht = { |
edb33667 TH |
296 | .module = THIS_MODULE, |
297 | .name = DRV_NAME, | |
298 | .ioctl = ata_scsi_ioctl, | |
299 | .queuecommand = ata_scsi_queuecmd, | |
edb33667 TH |
300 | .can_queue = ATA_DEF_QUEUE, |
301 | .this_id = ATA_SHT_THIS_ID, | |
302 | .sg_tablesize = LIBATA_MAX_PRD, | |
edb33667 TH |
303 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
304 | .emulated = ATA_SHT_EMULATED, | |
305 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
306 | .proc_name = DRV_NAME, | |
307 | .dma_boundary = ATA_DMA_BOUNDARY, | |
308 | .slave_configure = ata_scsi_slave_config, | |
309 | .bios_param = ata_std_bios_param, | |
edb33667 TH |
310 | }; |
311 | ||
057ace5e | 312 | static const struct ata_port_operations sil24_ops = { |
edb33667 TH |
313 | .port_disable = ata_port_disable, |
314 | ||
69ad185f TH |
315 | .dev_config = sil24_dev_config, |
316 | ||
edb33667 TH |
317 | .check_status = sil24_check_status, |
318 | .check_altstatus = sil24_check_status, | |
edb33667 TH |
319 | .dev_select = ata_noop_dev_select, |
320 | ||
7f726d12 TH |
321 | .tf_read = sil24_tf_read, |
322 | ||
07b73470 | 323 | .probe_reset = sil24_probe_reset, |
edb33667 TH |
324 | |
325 | .qc_prep = sil24_qc_prep, | |
326 | .qc_issue = sil24_qc_issue, | |
327 | ||
328 | .eng_timeout = sil24_eng_timeout, | |
329 | ||
330 | .irq_handler = sil24_interrupt, | |
331 | .irq_clear = sil24_irq_clear, | |
332 | ||
333 | .scr_read = sil24_scr_read, | |
334 | .scr_write = sil24_scr_write, | |
335 | ||
336 | .port_start = sil24_port_start, | |
337 | .port_stop = sil24_port_stop, | |
338 | .host_stop = sil24_host_stop, | |
339 | }; | |
340 | ||
042c21fd TH |
341 | /* |
342 | * Use bits 30-31 of host_flags to encode available port numbers. | |
343 | * Current maxium is 4. | |
344 | */ | |
345 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
346 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
347 | ||
edb33667 TH |
348 | static struct ata_port_info sil24_port_info[] = { |
349 | /* sil_3124 */ | |
350 | { | |
351 | .sht = &sil24_sht, | |
37024e8e TH |
352 | .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | |
353 | SIL24_FLAG_PCIX_IRQ_WOC, | |
edb33667 TH |
354 | .pio_mask = 0x1f, /* pio0-4 */ |
355 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
356 | .udma_mask = 0x3f, /* udma0-5 */ | |
357 | .port_ops = &sil24_ops, | |
358 | }, | |
2e9edbf8 | 359 | /* sil_3132 */ |
edb33667 TH |
360 | { |
361 | .sht = &sil24_sht, | |
9466d85b | 362 | .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
042c21fd TH |
363 | .pio_mask = 0x1f, /* pio0-4 */ |
364 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
365 | .udma_mask = 0x3f, /* udma0-5 */ | |
366 | .port_ops = &sil24_ops, | |
367 | }, | |
368 | /* sil_3131/sil_3531 */ | |
369 | { | |
370 | .sht = &sil24_sht, | |
9466d85b | 371 | .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
edb33667 TH |
372 | .pio_mask = 0x1f, /* pio0-4 */ |
373 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
374 | .udma_mask = 0x3f, /* udma0-5 */ | |
375 | .port_ops = &sil24_ops, | |
376 | }, | |
377 | }; | |
378 | ||
69ad185f TH |
379 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
380 | { | |
381 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | |
382 | ||
6e7846e9 | 383 | if (dev->cdb_len == 16) |
69ad185f TH |
384 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
385 | else | |
386 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
387 | } | |
388 | ||
6a575fa9 TH |
389 | static inline void sil24_update_tf(struct ata_port *ap) |
390 | { | |
391 | struct sil24_port_priv *pp = ap->private_data; | |
4b4a5eae AV |
392 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
393 | struct sil24_prb __iomem *prb = port; | |
394 | u8 fis[6 * 4]; | |
6a575fa9 | 395 | |
4b4a5eae AV |
396 | memcpy_fromio(fis, prb->fis, 6 * 4); |
397 | ata_tf_from_fis(fis, &pp->tf); | |
6a575fa9 TH |
398 | } |
399 | ||
edb33667 TH |
400 | static u8 sil24_check_status(struct ata_port *ap) |
401 | { | |
6a575fa9 TH |
402 | struct sil24_port_priv *pp = ap->private_data; |
403 | return pp->tf.command; | |
edb33667 TH |
404 | } |
405 | ||
edb33667 TH |
406 | static int sil24_scr_map[] = { |
407 | [SCR_CONTROL] = 0, | |
408 | [SCR_STATUS] = 1, | |
409 | [SCR_ERROR] = 2, | |
410 | [SCR_ACTIVE] = 3, | |
411 | }; | |
412 | ||
413 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |
414 | { | |
4b4a5eae | 415 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 416 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 417 | void __iomem *addr; |
edb33667 TH |
418 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
419 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); | |
420 | } | |
421 | return 0xffffffffU; | |
422 | } | |
423 | ||
424 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | |
425 | { | |
4b4a5eae | 426 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 427 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 428 | void __iomem *addr; |
edb33667 TH |
429 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
430 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
431 | } | |
432 | } | |
433 | ||
7f726d12 TH |
434 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
435 | { | |
436 | struct sil24_port_priv *pp = ap->private_data; | |
437 | *tf = pp->tf; | |
438 | } | |
439 | ||
b5bc421c TH |
440 | static int sil24_init_port(struct ata_port *ap) |
441 | { | |
442 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | |
443 | u32 tmp; | |
444 | ||
445 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); | |
446 | ata_wait_register(port + PORT_CTRL_STAT, | |
447 | PORT_CS_INIT, PORT_CS_INIT, 10, 100); | |
448 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
449 | PORT_CS_RDY, 0, 10, 100); | |
450 | ||
451 | if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) | |
452 | return -EIO; | |
453 | return 0; | |
454 | } | |
455 | ||
2bf2cb26 | 456 | static int sil24_softreset(struct ata_port *ap, unsigned int *class) |
edb33667 | 457 | { |
ca45160d TH |
458 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
459 | struct sil24_port_priv *pp = ap->private_data; | |
69ad185f | 460 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d | 461 | dma_addr_t paddr = pp->cmd_block_dma; |
7dd29dd6 | 462 | u32 mask, irq_enable, irq_stat; |
643be977 | 463 | const char *reason; |
ca45160d | 464 | |
07b73470 TH |
465 | DPRINTK("ENTER\n"); |
466 | ||
10d996ad TH |
467 | if (!sata_dev_present(ap)) { |
468 | DPRINTK("PHY reports no device\n"); | |
469 | *class = ATA_DEV_NONE; | |
470 | goto out; | |
471 | } | |
472 | ||
ca45160d TH |
473 | /* temporarily turn off IRQs during SRST */ |
474 | irq_enable = readl(port + PORT_IRQ_ENABLE_SET); | |
475 | writel(irq_enable, port + PORT_IRQ_ENABLE_CLR); | |
476 | ||
2555d6c2 TH |
477 | /* put the port into known state */ |
478 | if (sil24_init_port(ap)) { | |
479 | reason ="port not ready"; | |
480 | goto err; | |
481 | } | |
482 | ||
edb33667 | 483 | /* |
ca45160d TH |
484 | * XXX: Not sure whether the following sleep is needed or not. |
485 | * The original driver had it. So.... | |
edb33667 | 486 | */ |
ca45160d TH |
487 | msleep(10); |
488 | ||
489 | prb->ctrl = PRB_CTRL_SRST; | |
490 | prb->fis[1] = 0; /* no PM yet */ | |
491 | ||
492 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); | |
493 | ||
7dd29dd6 TH |
494 | mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; |
495 | irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0, | |
496 | 100, ATA_TMOUT_BOOT / HZ * 1000); | |
ca45160d | 497 | |
7dd29dd6 TH |
498 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */ |
499 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
ca45160d TH |
500 | |
501 | /* restore IRQs */ | |
502 | writel(irq_enable, port + PORT_IRQ_ENABLE_SET); | |
503 | ||
10d996ad | 504 | if (!(irq_stat & PORT_IRQ_COMPLETE)) { |
643be977 TH |
505 | if (irq_stat & PORT_IRQ_ERROR) |
506 | reason = "SRST command error"; | |
507 | else | |
508 | reason = "timeout"; | |
509 | goto err; | |
07b73470 | 510 | } |
10d996ad TH |
511 | |
512 | sil24_update_tf(ap); | |
513 | *class = ata_dev_classify(&pp->tf); | |
514 | ||
07b73470 TH |
515 | if (*class == ATA_DEV_UNKNOWN) |
516 | *class = ATA_DEV_NONE; | |
ca45160d | 517 | |
10d996ad | 518 | out: |
07b73470 | 519 | DPRINTK("EXIT, class=%u\n", *class); |
ca45160d | 520 | return 0; |
643be977 TH |
521 | |
522 | err: | |
523 | printk(KERN_ERR "ata%u: softreset failed (%s)\n", ap->id, reason); | |
524 | return -EIO; | |
ca45160d TH |
525 | } |
526 | ||
2bf2cb26 | 527 | static int sil24_hardreset(struct ata_port *ap, unsigned int *class) |
489ff4c7 TH |
528 | { |
529 | unsigned int dummy_class; | |
530 | ||
531 | /* sil24 doesn't report device signature after hard reset */ | |
2bf2cb26 | 532 | return sata_std_hardreset(ap, &dummy_class); |
489ff4c7 TH |
533 | } |
534 | ||
07b73470 | 535 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes) |
ca45160d | 536 | { |
07b73470 | 537 | return ata_drive_probe_reset(ap, ata_std_probeinit, |
489ff4c7 | 538 | sil24_softreset, sil24_hardreset, |
07b73470 | 539 | ata_std_postreset, classes); |
edb33667 TH |
540 | } |
541 | ||
542 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, | |
69ad185f | 543 | struct sil24_sge *sge) |
edb33667 | 544 | { |
972c26bd JG |
545 | struct scatterlist *sg; |
546 | unsigned int idx = 0; | |
edb33667 | 547 | |
972c26bd | 548 | ata_for_each_sg(sg, qc) { |
edb33667 TH |
549 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
550 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
972c26bd JG |
551 | if (ata_sg_is_last(sg, qc)) |
552 | sge->flags = cpu_to_le32(SGE_TRM); | |
553 | else | |
554 | sge->flags = 0; | |
555 | ||
556 | sge++; | |
557 | idx++; | |
edb33667 TH |
558 | } |
559 | } | |
560 | ||
561 | static void sil24_qc_prep(struct ata_queued_cmd *qc) | |
562 | { | |
563 | struct ata_port *ap = qc->ap; | |
564 | struct sil24_port_priv *pp = ap->private_data; | |
69ad185f TH |
565 | union sil24_cmd_block *cb = pp->cmd_block + qc->tag; |
566 | struct sil24_prb *prb; | |
567 | struct sil24_sge *sge; | |
edb33667 TH |
568 | |
569 | switch (qc->tf.protocol) { | |
570 | case ATA_PROT_PIO: | |
571 | case ATA_PROT_DMA: | |
572 | case ATA_PROT_NODATA: | |
69ad185f TH |
573 | prb = &cb->ata.prb; |
574 | sge = cb->ata.sge; | |
575 | prb->ctrl = 0; | |
edb33667 | 576 | break; |
69ad185f TH |
577 | |
578 | case ATA_PROT_ATAPI: | |
579 | case ATA_PROT_ATAPI_DMA: | |
580 | case ATA_PROT_ATAPI_NODATA: | |
581 | prb = &cb->atapi.prb; | |
582 | sge = cb->atapi.sge; | |
583 | memset(cb->atapi.cdb, 0, 32); | |
6e7846e9 | 584 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
69ad185f TH |
585 | |
586 | if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { | |
587 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
588 | prb->ctrl = PRB_CTRL_PACKET_WRITE; | |
589 | else | |
590 | prb->ctrl = PRB_CTRL_PACKET_READ; | |
591 | } else | |
592 | prb->ctrl = 0; | |
593 | ||
594 | break; | |
595 | ||
edb33667 | 596 | default: |
69ad185f TH |
597 | prb = NULL; /* shut up, gcc */ |
598 | sge = NULL; | |
edb33667 TH |
599 | BUG(); |
600 | } | |
601 | ||
602 | ata_tf_to_fis(&qc->tf, prb->fis, 0); | |
603 | ||
604 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 605 | sil24_fill_sg(qc, sge); |
edb33667 TH |
606 | } |
607 | ||
9a3d9eb0 | 608 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
609 | { |
610 | struct ata_port *ap = qc->ap; | |
4b4a5eae | 611 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
612 | struct sil24_port_priv *pp = ap->private_data; |
613 | dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block); | |
614 | ||
4f50c3cb | 615 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
edb33667 TH |
616 | return 0; |
617 | } | |
618 | ||
619 | static void sil24_irq_clear(struct ata_port *ap) | |
620 | { | |
621 | /* unused */ | |
622 | } | |
623 | ||
7d1ce682 TH |
624 | static int __sil24_restart_controller(void __iomem *port) |
625 | { | |
626 | u32 tmp; | |
627 | int cnt; | |
628 | ||
629 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); | |
630 | ||
631 | /* Max ~10ms */ | |
632 | for (cnt = 0; cnt < 10000; cnt++) { | |
633 | tmp = readl(port + PORT_CTRL_STAT); | |
634 | if (tmp & PORT_CS_RDY) | |
635 | return 0; | |
636 | udelay(1); | |
637 | } | |
638 | ||
639 | return -1; | |
640 | } | |
641 | ||
642 | static void sil24_restart_controller(struct ata_port *ap) | |
643 | { | |
644 | if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr)) | |
645 | printk(KERN_ERR DRV_NAME | |
646 | " ata%u: failed to restart controller\n", ap->id); | |
647 | } | |
648 | ||
4b4a5eae | 649 | static int __sil24_reset_controller(void __iomem *port) |
edb33667 | 650 | { |
edb33667 TH |
651 | int cnt; |
652 | u32 tmp; | |
653 | ||
edb33667 TH |
654 | /* Reset controller state. Is this correct? */ |
655 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
656 | readl(port + PORT_CTRL_STAT); /* sync */ | |
657 | ||
658 | /* Max ~100ms */ | |
659 | for (cnt = 0; cnt < 1000; cnt++) { | |
660 | udelay(100); | |
661 | tmp = readl(port + PORT_CTRL_STAT); | |
662 | if (!(tmp & PORT_CS_DEV_RST)) | |
663 | break; | |
664 | } | |
923f1225 | 665 | |
edb33667 | 666 | if (tmp & PORT_CS_DEV_RST) |
923f1225 | 667 | return -1; |
7d1ce682 TH |
668 | |
669 | if (tmp & PORT_CS_RDY) | |
670 | return 0; | |
671 | ||
672 | return __sil24_restart_controller(port); | |
923f1225 TH |
673 | } |
674 | ||
675 | static void sil24_reset_controller(struct ata_port *ap) | |
676 | { | |
677 | printk(KERN_NOTICE DRV_NAME | |
678 | " ata%u: resetting controller...\n", ap->id); | |
4b4a5eae | 679 | if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
923f1225 TH |
680 | printk(KERN_ERR DRV_NAME |
681 | " ata%u: failed to reset controller\n", ap->id); | |
edb33667 TH |
682 | } |
683 | ||
684 | static void sil24_eng_timeout(struct ata_port *ap) | |
685 | { | |
686 | struct ata_queued_cmd *qc; | |
687 | ||
688 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
edb33667 | 689 | |
edb33667 | 690 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); |
11a56d24 | 691 | qc->err_mask |= AC_ERR_TIMEOUT; |
a72ec4ce | 692 | ata_eh_qc_complete(qc); |
edb33667 TH |
693 | |
694 | sil24_reset_controller(ap); | |
695 | } | |
696 | ||
8746618d TH |
697 | static void sil24_error_intr(struct ata_port *ap, u32 slot_stat) |
698 | { | |
699 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
6a575fa9 | 700 | struct sil24_port_priv *pp = ap->private_data; |
4b4a5eae | 701 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
8746618d | 702 | u32 irq_stat, cmd_err, sstatus, serror; |
a7dac447 | 703 | unsigned int err_mask; |
8746618d TH |
704 | |
705 | irq_stat = readl(port + PORT_IRQ_STAT); | |
ad6e90f6 TH |
706 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ |
707 | ||
708 | if (!(irq_stat & PORT_IRQ_ERROR)) { | |
709 | /* ignore non-completion, non-error irqs for now */ | |
710 | printk(KERN_WARNING DRV_NAME | |
711 | "ata%u: non-error exception irq (irq_stat %x)\n", | |
712 | ap->id, irq_stat); | |
713 | return; | |
714 | } | |
715 | ||
8746618d TH |
716 | cmd_err = readl(port + PORT_CMD_ERR); |
717 | sstatus = readl(port + PORT_SSTATUS); | |
718 | serror = readl(port + PORT_SERROR); | |
8746618d TH |
719 | if (serror) |
720 | writel(serror, port + PORT_SERROR); | |
721 | ||
c0ab4242 TH |
722 | /* |
723 | * Don't log ATAPI device errors. They're supposed to happen | |
724 | * and any serious errors will be logged using sense data by | |
725 | * the SCSI layer. | |
726 | */ | |
727 | if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB) | |
728 | printk("ata%u: error interrupt on port%d\n" | |
729 | " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", | |
730 | ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); | |
8746618d | 731 | |
6a575fa9 TH |
732 | if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) { |
733 | /* | |
734 | * Device is reporting error, tf registers are valid. | |
735 | */ | |
736 | sil24_update_tf(ap); | |
a7dac447 | 737 | err_mask = ac_err_mask(pp->tf.command); |
7d1ce682 | 738 | sil24_restart_controller(ap); |
6a575fa9 TH |
739 | } else { |
740 | /* | |
741 | * Other errors. libata currently doesn't have any | |
742 | * mechanism to report these errors. Just turn on | |
743 | * ATA_ERR. | |
744 | */ | |
a7dac447 | 745 | err_mask = AC_ERR_OTHER; |
7d1ce682 | 746 | sil24_reset_controller(ap); |
6a575fa9 TH |
747 | } |
748 | ||
a22e2eb0 AL |
749 | if (qc) { |
750 | qc->err_mask |= err_mask; | |
751 | ata_qc_complete(qc); | |
752 | } | |
8746618d TH |
753 | } |
754 | ||
edb33667 TH |
755 | static inline void sil24_host_intr(struct ata_port *ap) |
756 | { | |
757 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
4b4a5eae | 758 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
759 | u32 slot_stat; |
760 | ||
761 | slot_stat = readl(port + PORT_SLOT_STAT); | |
762 | if (!(slot_stat & HOST_SSTAT_ATTN)) { | |
6a575fa9 | 763 | struct sil24_port_priv *pp = ap->private_data; |
37024e8e TH |
764 | |
765 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
766 | writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); | |
767 | ||
6a575fa9 TH |
768 | /* |
769 | * !HOST_SSAT_ATTN guarantees successful completion, | |
770 | * so reading back tf registers is unnecessary for | |
771 | * most commands. TODO: read tf registers for | |
772 | * commands which require these values on successful | |
773 | * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER, | |
774 | * DEVICE RESET and READ PORT MULTIPLIER (any more?). | |
775 | */ | |
776 | sil24_update_tf(ap); | |
777 | ||
a22e2eb0 AL |
778 | if (qc) { |
779 | qc->err_mask |= ac_err_mask(pp->tf.command); | |
780 | ata_qc_complete(qc); | |
781 | } | |
8746618d TH |
782 | } else |
783 | sil24_error_intr(ap, slot_stat); | |
edb33667 TH |
784 | } |
785 | ||
786 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
787 | { | |
788 | struct ata_host_set *host_set = dev_instance; | |
789 | struct sil24_host_priv *hpriv = host_set->private_data; | |
790 | unsigned handled = 0; | |
791 | u32 status; | |
792 | int i; | |
793 | ||
794 | status = readl(hpriv->host_base + HOST_IRQ_STAT); | |
795 | ||
06460aea TH |
796 | if (status == 0xffffffff) { |
797 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
798 | "PCI fault or device removal?\n"); | |
799 | goto out; | |
800 | } | |
801 | ||
edb33667 TH |
802 | if (!(status & IRQ_STAT_4PORTS)) |
803 | goto out; | |
804 | ||
805 | spin_lock(&host_set->lock); | |
806 | ||
807 | for (i = 0; i < host_set->n_ports; i++) | |
808 | if (status & (1 << i)) { | |
809 | struct ata_port *ap = host_set->ports[i]; | |
198e0fed | 810 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
edb33667 | 811 | sil24_host_intr(host_set->ports[i]); |
3cc4571c TH |
812 | handled++; |
813 | } else | |
814 | printk(KERN_ERR DRV_NAME | |
815 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
816 | } |
817 | ||
818 | spin_unlock(&host_set->lock); | |
819 | out: | |
820 | return IRQ_RETVAL(handled); | |
821 | } | |
822 | ||
6037d6bb JG |
823 | static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev) |
824 | { | |
825 | const size_t cb_size = sizeof(*pp->cmd_block); | |
826 | ||
827 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); | |
828 | } | |
829 | ||
edb33667 TH |
830 | static int sil24_port_start(struct ata_port *ap) |
831 | { | |
832 | struct device *dev = ap->host_set->dev; | |
edb33667 | 833 | struct sil24_port_priv *pp; |
69ad185f | 834 | union sil24_cmd_block *cb; |
edb33667 TH |
835 | size_t cb_size = sizeof(*cb); |
836 | dma_addr_t cb_dma; | |
6037d6bb | 837 | int rc = -ENOMEM; |
edb33667 | 838 | |
6037d6bb | 839 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
edb33667 | 840 | if (!pp) |
6037d6bb | 841 | goto err_out; |
edb33667 | 842 | |
6a575fa9 TH |
843 | pp->tf.command = ATA_DRDY; |
844 | ||
edb33667 | 845 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb JG |
846 | if (!cb) |
847 | goto err_out_pp; | |
edb33667 TH |
848 | memset(cb, 0, cb_size); |
849 | ||
6037d6bb JG |
850 | rc = ata_pad_alloc(ap, dev); |
851 | if (rc) | |
852 | goto err_out_pad; | |
853 | ||
edb33667 TH |
854 | pp->cmd_block = cb; |
855 | pp->cmd_block_dma = cb_dma; | |
856 | ||
857 | ap->private_data = pp; | |
858 | ||
859 | return 0; | |
6037d6bb JG |
860 | |
861 | err_out_pad: | |
862 | sil24_cblk_free(pp, dev); | |
863 | err_out_pp: | |
864 | kfree(pp); | |
865 | err_out: | |
866 | return rc; | |
edb33667 TH |
867 | } |
868 | ||
869 | static void sil24_port_stop(struct ata_port *ap) | |
870 | { | |
871 | struct device *dev = ap->host_set->dev; | |
872 | struct sil24_port_priv *pp = ap->private_data; | |
edb33667 | 873 | |
6037d6bb | 874 | sil24_cblk_free(pp, dev); |
e9c05afa | 875 | ata_pad_free(ap, dev); |
edb33667 TH |
876 | kfree(pp); |
877 | } | |
878 | ||
879 | static void sil24_host_stop(struct ata_host_set *host_set) | |
880 | { | |
881 | struct sil24_host_priv *hpriv = host_set->private_data; | |
142877b0 | 882 | struct pci_dev *pdev = to_pci_dev(host_set->dev); |
edb33667 | 883 | |
142877b0 JG |
884 | pci_iounmap(pdev, hpriv->host_base); |
885 | pci_iounmap(pdev, hpriv->port_base); | |
edb33667 TH |
886 | kfree(hpriv); |
887 | } | |
888 | ||
889 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
890 | { | |
891 | static int printed_version = 0; | |
892 | unsigned int board_id = (unsigned int)ent->driver_data; | |
042c21fd | 893 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
edb33667 TH |
894 | struct ata_probe_ent *probe_ent = NULL; |
895 | struct sil24_host_priv *hpriv = NULL; | |
4b4a5eae AV |
896 | void __iomem *host_base = NULL; |
897 | void __iomem *port_base = NULL; | |
edb33667 | 898 | int i, rc; |
37024e8e | 899 | u32 tmp; |
edb33667 TH |
900 | |
901 | if (!printed_version++) | |
a9524a76 | 902 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edb33667 TH |
903 | |
904 | rc = pci_enable_device(pdev); | |
905 | if (rc) | |
906 | return rc; | |
907 | ||
908 | rc = pci_request_regions(pdev, DRV_NAME); | |
909 | if (rc) | |
910 | goto out_disable; | |
911 | ||
912 | rc = -ENOMEM; | |
142877b0 JG |
913 | /* map mmio registers */ |
914 | host_base = pci_iomap(pdev, 0, 0); | |
edb33667 TH |
915 | if (!host_base) |
916 | goto out_free; | |
142877b0 | 917 | port_base = pci_iomap(pdev, 2, 0); |
edb33667 TH |
918 | if (!port_base) |
919 | goto out_free; | |
920 | ||
921 | /* allocate & init probe_ent and hpriv */ | |
142877b0 | 922 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
edb33667 TH |
923 | if (!probe_ent) |
924 | goto out_free; | |
925 | ||
142877b0 | 926 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
edb33667 TH |
927 | if (!hpriv) |
928 | goto out_free; | |
929 | ||
edb33667 TH |
930 | probe_ent->dev = pci_dev_to_dev(pdev); |
931 | INIT_LIST_HEAD(&probe_ent->node); | |
932 | ||
042c21fd TH |
933 | probe_ent->sht = pinfo->sht; |
934 | probe_ent->host_flags = pinfo->host_flags; | |
935 | probe_ent->pio_mask = pinfo->pio_mask; | |
fbfda6e7 | 936 | probe_ent->mwdma_mask = pinfo->mwdma_mask; |
042c21fd TH |
937 | probe_ent->udma_mask = pinfo->udma_mask; |
938 | probe_ent->port_ops = pinfo->port_ops; | |
939 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags); | |
edb33667 TH |
940 | |
941 | probe_ent->irq = pdev->irq; | |
942 | probe_ent->irq_flags = SA_SHIRQ; | |
943 | probe_ent->mmio_base = port_base; | |
944 | probe_ent->private_data = hpriv; | |
945 | ||
edb33667 TH |
946 | hpriv->host_base = host_base; |
947 | hpriv->port_base = port_base; | |
948 | ||
949 | /* | |
950 | * Configure the device | |
951 | */ | |
952 | /* | |
953 | * FIXME: This device is certainly 64-bit capable. We just | |
954 | * don't know how to use it. After fixing 32bit activation in | |
955 | * this function, enable 64bit masks here. | |
956 | */ | |
957 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
958 | if (rc) { | |
a9524a76 JG |
959 | dev_printk(KERN_ERR, &pdev->dev, |
960 | "32-bit DMA enable failed\n"); | |
edb33667 TH |
961 | goto out_free; |
962 | } | |
963 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
964 | if (rc) { | |
a9524a76 JG |
965 | dev_printk(KERN_ERR, &pdev->dev, |
966 | "32-bit consistent DMA enable failed\n"); | |
edb33667 TH |
967 | goto out_free; |
968 | } | |
969 | ||
970 | /* GPIO off */ | |
971 | writel(0, host_base + HOST_FLASH_CMD); | |
972 | ||
37024e8e TH |
973 | /* Apply workaround for completion IRQ loss on PCI-X errata */ |
974 | if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) { | |
975 | tmp = readl(host_base + HOST_CTRL); | |
976 | if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) | |
977 | dev_printk(KERN_INFO, &pdev->dev, | |
978 | "Applying completion IRQ loss on PCI-X " | |
979 | "errata fix\n"); | |
980 | else | |
981 | probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; | |
982 | } | |
983 | ||
7dd29dd6 | 984 | /* clear global reset & mask interrupts during initialization */ |
edb33667 TH |
985 | writel(0, host_base + HOST_CTRL); |
986 | ||
987 | for (i = 0; i < probe_ent->n_ports; i++) { | |
4b4a5eae | 988 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
edb33667 | 989 | unsigned long portu = (unsigned long)port; |
edb33667 | 990 | |
4f50c3cb | 991 | probe_ent->port[i].cmd_addr = portu + PORT_PRB; |
edb33667 TH |
992 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
993 | ||
994 | ata_std_ports(&probe_ent->port[i]); | |
995 | ||
996 | /* Initial PHY setting */ | |
997 | writel(0x20c, port + PORT_PHY_CFG); | |
998 | ||
999 | /* Clear port RST */ | |
1000 | tmp = readl(port + PORT_CTRL_STAT); | |
1001 | if (tmp & PORT_CS_PORT_RST) { | |
1002 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
7dd29dd6 TH |
1003 | tmp = ata_wait_register(port + PORT_CTRL_STAT, |
1004 | PORT_CS_PORT_RST, | |
1005 | PORT_CS_PORT_RST, 10, 100); | |
edb33667 | 1006 | if (tmp & PORT_CS_PORT_RST) |
a9524a76 JG |
1007 | dev_printk(KERN_ERR, &pdev->dev, |
1008 | "failed to clear port RST\n"); | |
edb33667 TH |
1009 | } |
1010 | ||
37024e8e TH |
1011 | /* Configure IRQ WoC */ |
1012 | if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
1013 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); | |
1014 | else | |
1015 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
1016 | ||
edb33667 TH |
1017 | /* Zero error counters. */ |
1018 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
1019 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
1020 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
1021 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
1022 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
1023 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
1024 | ||
1025 | /* FIXME: 32bit activation? */ | |
1026 | writel(0, port + PORT_ACTIVATE_UPPER_ADDR); | |
1027 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT); | |
1028 | ||
1029 | /* Configure interrupts */ | |
1030 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
3b9f1d0f TH |
1031 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
1032 | PORT_IRQ_SDB_NOTIFY, port + PORT_IRQ_ENABLE_SET); | |
edb33667 TH |
1033 | |
1034 | /* Clear interrupts */ | |
1035 | writel(0x0fff0fff, port + PORT_IRQ_STAT); | |
1036 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
923f1225 TH |
1037 | |
1038 | /* Clear port multiplier enable and resume bits */ | |
1039 | writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR); | |
1040 | ||
1041 | /* Reset itself */ | |
1042 | if (__sil24_reset_controller(port)) | |
a9524a76 JG |
1043 | dev_printk(KERN_ERR, &pdev->dev, |
1044 | "failed to reset controller\n"); | |
edb33667 TH |
1045 | } |
1046 | ||
1047 | /* Turn on interrupts */ | |
1048 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
1049 | ||
1050 | pci_set_master(pdev); | |
1051 | ||
1483467f | 1052 | /* FIXME: check ata_device_add return value */ |
edb33667 TH |
1053 | ata_device_add(probe_ent); |
1054 | ||
1055 | kfree(probe_ent); | |
1056 | return 0; | |
1057 | ||
1058 | out_free: | |
1059 | if (host_base) | |
142877b0 | 1060 | pci_iounmap(pdev, host_base); |
edb33667 | 1061 | if (port_base) |
142877b0 | 1062 | pci_iounmap(pdev, port_base); |
edb33667 TH |
1063 | kfree(probe_ent); |
1064 | kfree(hpriv); | |
1065 | pci_release_regions(pdev); | |
1066 | out_disable: | |
1067 | pci_disable_device(pdev); | |
1068 | return rc; | |
1069 | } | |
1070 | ||
1071 | static int __init sil24_init(void) | |
1072 | { | |
1073 | return pci_module_init(&sil24_pci_driver); | |
1074 | } | |
1075 | ||
1076 | static void __exit sil24_exit(void) | |
1077 | { | |
1078 | pci_unregister_driver(&sil24_pci_driver); | |
1079 | } | |
1080 | ||
1081 | MODULE_AUTHOR("Tejun Heo"); | |
1082 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1083 | MODULE_LICENSE("GPL"); | |
1084 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
1085 | ||
1086 | module_init(sil24_init); | |
1087 | module_exit(sil24_exit); |