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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
8 | * NOTE: No NCQ/ATAPI support yet. The preview driver didn't support | |
9 | * NCQ nor ATAPI, and, unfortunately, I couldn't find out how to make | |
10 | * those work. Enabling those shouldn't be difficult. Basic | |
11 | * structure is all there (in libata-dev tree). If you have any | |
12 | * information about this hardware, please contact me or linux-ide. | |
13 | * Info is needed on... | |
14 | * | |
15 | * - How to issue tagged commands and turn on sactive on issue accordingly. | |
16 | * - Where to put an ATAPI command and how to tell the device to send it. | |
17 | * - How to enable/use 64bit. | |
18 | * | |
19 | * This program is free software; you can redistribute it and/or modify it | |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2, or (at your option) any | |
22 | * later version. | |
23 | * | |
24 | * This program is distributed in the hope that it will be useful, but | |
25 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
26 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
27 | * General Public License for more details. | |
28 | * | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/pci.h> | |
34 | #include <linux/blkdev.h> | |
35 | #include <linux/delay.h> | |
36 | #include <linux/interrupt.h> | |
37 | #include <linux/dma-mapping.h> | |
38 | #include <scsi/scsi_host.h> | |
39 | #include "scsi.h" | |
40 | #include <linux/libata.h> | |
41 | #include <asm/io.h> | |
42 | ||
43 | #define DRV_NAME "sata_sil24" | |
44 | #define DRV_VERSION "0.20" /* Silicon Image's preview driver was 0.10 */ | |
45 | ||
46 | #define NR_PORTS 4 | |
47 | ||
48 | /* | |
49 | * Port request block (PRB) 32 bytes | |
50 | */ | |
51 | struct sil24_prb { | |
52 | u16 ctrl; | |
53 | u16 prot; | |
54 | u32 rx_cnt; | |
55 | u8 fis[6 * 4]; | |
56 | }; | |
57 | ||
58 | /* | |
59 | * Scatter gather entry (SGE) 16 bytes | |
60 | */ | |
61 | struct sil24_sge { | |
62 | u64 addr; | |
63 | u32 cnt; | |
64 | u32 flags; | |
65 | }; | |
66 | ||
67 | /* | |
68 | * Port multiplier | |
69 | */ | |
70 | struct sil24_port_multiplier { | |
71 | u32 diag; | |
72 | u32 sactive; | |
73 | }; | |
74 | ||
75 | enum { | |
76 | /* | |
77 | * Global controller registers (128 bytes @ BAR0) | |
78 | */ | |
79 | /* 32 bit regs */ | |
80 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
81 | HOST_CTRL = 0x40, | |
82 | HOST_IRQ_STAT = 0x44, | |
83 | HOST_PHY_CFG = 0x48, | |
84 | HOST_BIST_CTRL = 0x50, | |
85 | HOST_BIST_PTRN = 0x54, | |
86 | HOST_BIST_STAT = 0x58, | |
87 | HOST_MEM_BIST_STAT = 0x5c, | |
88 | HOST_FLASH_CMD = 0x70, | |
89 | /* 8 bit regs */ | |
90 | HOST_FLASH_DATA = 0x74, | |
91 | HOST_TRANSITION_DETECT = 0x75, | |
92 | HOST_GPIO_CTRL = 0x76, | |
93 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
94 | HOST_I2C_DATA = 0x7c, | |
95 | HOST_I2C_XFER_CNT = 0x7e, | |
96 | HOST_I2C_CTRL = 0x7f, | |
97 | ||
98 | /* HOST_SLOT_STAT bits */ | |
99 | HOST_SSTAT_ATTN = (1 << 31), | |
100 | ||
101 | /* | |
102 | * Port registers | |
103 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
104 | */ | |
105 | PORT_REGS_SIZE = 0x2000, | |
106 | PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */ | |
edb33667 TH |
107 | |
108 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ | |
109 | /* 32 bit regs */ | |
83bbecc9 TH |
110 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
111 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
112 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
113 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
114 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 115 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
116 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
117 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
118 | PORT_FIS_CFG = 0x1028, |
119 | PORT_FIFO_THRES = 0x102c, | |
120 | /* 16 bit regs */ | |
121 | PORT_DECODE_ERR_CNT = 0x1040, | |
122 | PORT_DECODE_ERR_THRESH = 0x1042, | |
123 | PORT_CRC_ERR_CNT = 0x1044, | |
124 | PORT_CRC_ERR_THRESH = 0x1046, | |
125 | PORT_HSHK_ERR_CNT = 0x1048, | |
126 | PORT_HSHK_ERR_THRESH = 0x104a, | |
127 | /* 32 bit regs */ | |
128 | PORT_PHY_CFG = 0x1050, | |
129 | PORT_SLOT_STAT = 0x1800, | |
130 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
131 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ | |
132 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
133 | PORT_SCONTROL = 0x1f00, | |
134 | PORT_SSTATUS = 0x1f04, | |
135 | PORT_SERROR = 0x1f08, | |
136 | PORT_SACTIVE = 0x1f0c, | |
137 | ||
138 | /* PORT_CTRL_STAT bits */ | |
139 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
140 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
141 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
142 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
e382eb1d TH |
143 | PORT_CS_RESUME = (1 << 6), /* port resume */ |
144 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ | |
145 | PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ | |
146 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ | |
edb33667 TH |
147 | |
148 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
149 | /* bits[11:0] are masked */ | |
150 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
151 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
152 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
153 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
154 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
155 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
156 | PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */ | |
157 | PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */ | |
158 | ||
159 | /* bits[27:16] are unmasked (raw) */ | |
160 | PORT_IRQ_RAW_SHIFT = 16, | |
161 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
162 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
163 | ||
164 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
165 | PORT_IRQ_STEER_SHIFT = 30, | |
166 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
167 | ||
168 | /* PORT_CMD_ERR constants */ | |
169 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
170 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
171 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
172 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
173 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
174 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
175 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
176 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
177 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
178 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
179 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
180 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
181 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
182 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
183 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
184 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
185 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
186 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
187 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
188 | PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */ | |
189 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ | |
83bbecc9 | 190 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 TH |
191 | |
192 | /* | |
193 | * Other constants | |
194 | */ | |
195 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
196 | PRB_SOFT_RST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
197 | ||
198 | /* board id */ | |
199 | BID_SIL3124 = 0, | |
200 | BID_SIL3132 = 1, | |
201 | ||
202 | IRQ_STAT_4PORTS = 0xf, | |
203 | }; | |
204 | ||
205 | struct sil24_cmd_block { | |
206 | struct sil24_prb prb; | |
207 | struct sil24_sge sge[LIBATA_MAX_PRD]; | |
208 | }; | |
209 | ||
210 | /* | |
211 | * ap->private_data | |
212 | * | |
213 | * The preview driver always returned 0 for status. We emulate it | |
214 | * here from the previous interrupt. | |
215 | */ | |
216 | struct sil24_port_priv { | |
edb33667 TH |
217 | struct sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
218 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ | |
219 | }; | |
220 | ||
221 | /* ap->host_set->private_data */ | |
222 | struct sil24_host_priv { | |
223 | void *host_base; /* global controller control (128 bytes @BAR0) */ | |
224 | void *port_base; /* port registers (4 * 8192 bytes @BAR2) */ | |
225 | }; | |
226 | ||
227 | static u8 sil24_check_status(struct ata_port *ap); | |
228 | static u8 sil24_check_err(struct ata_port *ap); | |
229 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); | |
230 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); | |
231 | static void sil24_phy_reset(struct ata_port *ap); | |
232 | static void sil24_qc_prep(struct ata_queued_cmd *qc); | |
233 | static int sil24_qc_issue(struct ata_queued_cmd *qc); | |
234 | static void sil24_irq_clear(struct ata_port *ap); | |
235 | static void sil24_eng_timeout(struct ata_port *ap); | |
236 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs); | |
237 | static int sil24_port_start(struct ata_port *ap); | |
238 | static void sil24_port_stop(struct ata_port *ap); | |
239 | static void sil24_host_stop(struct ata_host_set *host_set); | |
240 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
241 | ||
242 | static struct pci_device_id sil24_pci_tbl[] = { | |
243 | { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, | |
244 | { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 }, | |
245 | }; | |
246 | ||
247 | static struct pci_driver sil24_pci_driver = { | |
248 | .name = DRV_NAME, | |
249 | .id_table = sil24_pci_tbl, | |
250 | .probe = sil24_init_one, | |
251 | .remove = ata_pci_remove_one, /* safe? */ | |
252 | }; | |
253 | ||
254 | static Scsi_Host_Template sil24_sht = { | |
255 | .module = THIS_MODULE, | |
256 | .name = DRV_NAME, | |
257 | .ioctl = ata_scsi_ioctl, | |
258 | .queuecommand = ata_scsi_queuecmd, | |
259 | .eh_strategy_handler = ata_scsi_error, | |
260 | .can_queue = ATA_DEF_QUEUE, | |
261 | .this_id = ATA_SHT_THIS_ID, | |
262 | .sg_tablesize = LIBATA_MAX_PRD, | |
263 | .max_sectors = ATA_MAX_SECTORS, | |
264 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
265 | .emulated = ATA_SHT_EMULATED, | |
266 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
267 | .proc_name = DRV_NAME, | |
268 | .dma_boundary = ATA_DMA_BOUNDARY, | |
269 | .slave_configure = ata_scsi_slave_config, | |
270 | .bios_param = ata_std_bios_param, | |
271 | .ordered_flush = 1, /* NCQ not supported yet */ | |
272 | }; | |
273 | ||
274 | static struct ata_port_operations sil24_ops = { | |
275 | .port_disable = ata_port_disable, | |
276 | ||
277 | .check_status = sil24_check_status, | |
278 | .check_altstatus = sil24_check_status, | |
279 | .check_err = sil24_check_err, | |
280 | .dev_select = ata_noop_dev_select, | |
281 | ||
282 | .phy_reset = sil24_phy_reset, | |
283 | ||
284 | .qc_prep = sil24_qc_prep, | |
285 | .qc_issue = sil24_qc_issue, | |
286 | ||
287 | .eng_timeout = sil24_eng_timeout, | |
288 | ||
289 | .irq_handler = sil24_interrupt, | |
290 | .irq_clear = sil24_irq_clear, | |
291 | ||
292 | .scr_read = sil24_scr_read, | |
293 | .scr_write = sil24_scr_write, | |
294 | ||
295 | .port_start = sil24_port_start, | |
296 | .port_stop = sil24_port_stop, | |
297 | .host_stop = sil24_host_stop, | |
298 | }; | |
299 | ||
300 | static struct ata_port_info sil24_port_info[] = { | |
301 | /* sil_3124 */ | |
302 | { | |
303 | .sht = &sil24_sht, | |
304 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
305 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | | |
306 | ATA_FLAG_PIO_DMA, | |
307 | .pio_mask = 0x1f, /* pio0-4 */ | |
308 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
309 | .udma_mask = 0x3f, /* udma0-5 */ | |
310 | .port_ops = &sil24_ops, | |
311 | }, | |
312 | /* sil_3132 */ | |
313 | { | |
314 | .sht = &sil24_sht, | |
315 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
316 | ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO | | |
317 | ATA_FLAG_PIO_DMA, | |
318 | .pio_mask = 0x1f, /* pio0-4 */ | |
319 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
320 | .udma_mask = 0x3f, /* udma0-5 */ | |
321 | .port_ops = &sil24_ops, | |
322 | }, | |
323 | }; | |
324 | ||
325 | static u8 sil24_check_status(struct ata_port *ap) | |
326 | { | |
327 | return ATA_DRDY; | |
328 | } | |
329 | ||
330 | static u8 sil24_check_err(struct ata_port *ap) | |
331 | { | |
332 | return 0; | |
333 | } | |
334 | ||
335 | static int sil24_scr_map[] = { | |
336 | [SCR_CONTROL] = 0, | |
337 | [SCR_STATUS] = 1, | |
338 | [SCR_ERROR] = 2, | |
339 | [SCR_ACTIVE] = 3, | |
340 | }; | |
341 | ||
342 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |
343 | { | |
344 | void *scr_addr = (void *)ap->ioaddr.scr_addr; | |
345 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { | |
346 | void *addr; | |
347 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; | |
348 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); | |
349 | } | |
350 | return 0xffffffffU; | |
351 | } | |
352 | ||
353 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | |
354 | { | |
355 | void *scr_addr = (void *)ap->ioaddr.scr_addr; | |
356 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { | |
357 | void *addr; | |
358 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; | |
359 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
360 | } | |
361 | } | |
362 | ||
363 | static void sil24_phy_reset(struct ata_port *ap) | |
364 | { | |
365 | __sata_phy_reset(ap); | |
366 | /* | |
367 | * No ATAPI yet. Just unconditionally indicate ATA device. | |
368 | * If ATAPI device is attached, it will fail ATA_CMD_ID_ATA | |
369 | * and libata core will ignore the device. | |
370 | */ | |
371 | if (!(ap->flags & ATA_FLAG_PORT_DISABLED)) | |
372 | ap->device[0].class = ATA_DEV_ATA; | |
373 | } | |
374 | ||
375 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, | |
376 | struct sil24_cmd_block *cb) | |
377 | { | |
378 | struct scatterlist *sg = qc->sg; | |
379 | struct sil24_sge *sge = cb->sge; | |
380 | unsigned i; | |
381 | ||
382 | for (i = 0; i < qc->n_elem; i++, sg++, sge++) { | |
383 | sge->addr = cpu_to_le64(sg_dma_address(sg)); | |
384 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
385 | sge->flags = 0; | |
386 | sge->flags = i < qc->n_elem - 1 ? 0 : cpu_to_le32(SGE_TRM); | |
387 | } | |
388 | } | |
389 | ||
390 | static void sil24_qc_prep(struct ata_queued_cmd *qc) | |
391 | { | |
392 | struct ata_port *ap = qc->ap; | |
393 | struct sil24_port_priv *pp = ap->private_data; | |
394 | struct sil24_cmd_block *cb = pp->cmd_block + qc->tag; | |
395 | struct sil24_prb *prb = &cb->prb; | |
396 | ||
397 | switch (qc->tf.protocol) { | |
398 | case ATA_PROT_PIO: | |
399 | case ATA_PROT_DMA: | |
400 | case ATA_PROT_NODATA: | |
401 | break; | |
402 | default: | |
403 | /* ATAPI isn't supported yet */ | |
404 | BUG(); | |
405 | } | |
406 | ||
407 | ata_tf_to_fis(&qc->tf, prb->fis, 0); | |
408 | ||
409 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
410 | sil24_fill_sg(qc, cb); | |
411 | } | |
412 | ||
413 | static int sil24_qc_issue(struct ata_queued_cmd *qc) | |
414 | { | |
415 | struct ata_port *ap = qc->ap; | |
4f50c3cb | 416 | void *port = (void *)ap->ioaddr.cmd_addr; |
edb33667 TH |
417 | struct sil24_port_priv *pp = ap->private_data; |
418 | dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block); | |
419 | ||
4f50c3cb | 420 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
edb33667 TH |
421 | return 0; |
422 | } | |
423 | ||
424 | static void sil24_irq_clear(struct ata_port *ap) | |
425 | { | |
426 | /* unused */ | |
427 | } | |
428 | ||
429 | static void sil24_reset_controller(struct ata_port *ap) | |
430 | { | |
4f50c3cb | 431 | void *port = (void *)ap->ioaddr.cmd_addr; |
edb33667 TH |
432 | int cnt; |
433 | u32 tmp; | |
434 | ||
435 | printk(KERN_NOTICE DRV_NAME | |
436 | " ata%u: resetting controller...\n", ap->id); | |
437 | ||
438 | /* Reset controller state. Is this correct? */ | |
439 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
440 | readl(port + PORT_CTRL_STAT); /* sync */ | |
441 | ||
442 | /* Max ~100ms */ | |
443 | for (cnt = 0; cnt < 1000; cnt++) { | |
444 | udelay(100); | |
445 | tmp = readl(port + PORT_CTRL_STAT); | |
446 | if (!(tmp & PORT_CS_DEV_RST)) | |
447 | break; | |
448 | } | |
449 | if (tmp & PORT_CS_DEV_RST) | |
450 | printk(KERN_ERR DRV_NAME | |
451 | " ata%u: failed to reset controller\n", ap->id); | |
452 | } | |
453 | ||
454 | static void sil24_eng_timeout(struct ata_port *ap) | |
455 | { | |
456 | struct ata_queued_cmd *qc; | |
457 | ||
458 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
459 | if (!qc) { | |
460 | printk(KERN_ERR "ata%u: BUG: tiemout without command\n", | |
461 | ap->id); | |
462 | return; | |
463 | } | |
464 | ||
465 | /* | |
466 | * hack alert! We cannot use the supplied completion | |
467 | * function from inside the ->eh_strategy_handler() thread. | |
468 | * libata is the only user of ->eh_strategy_handler() in | |
469 | * any kernel, so the default scsi_done() assumes it is | |
470 | * not being called from the SCSI EH. | |
471 | */ | |
472 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); | |
473 | qc->scsidone = scsi_finish_command; | |
474 | ata_qc_complete(qc, ATA_ERR); | |
475 | ||
476 | sil24_reset_controller(ap); | |
477 | } | |
478 | ||
8746618d TH |
479 | static void sil24_error_intr(struct ata_port *ap, u32 slot_stat) |
480 | { | |
481 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
4f50c3cb | 482 | void *port = (void *)ap->ioaddr.cmd_addr; |
8746618d TH |
483 | u32 irq_stat, cmd_err, sstatus, serror; |
484 | ||
485 | irq_stat = readl(port + PORT_IRQ_STAT); | |
486 | cmd_err = readl(port + PORT_CMD_ERR); | |
487 | sstatus = readl(port + PORT_SSTATUS); | |
488 | serror = readl(port + PORT_SERROR); | |
489 | ||
490 | /* Clear IRQ/errors */ | |
491 | writel(irq_stat, port + PORT_IRQ_STAT); | |
492 | if (cmd_err) | |
493 | writel(cmd_err, port + PORT_CMD_ERR); | |
494 | if (serror) | |
495 | writel(serror, port + PORT_SERROR); | |
496 | ||
497 | printk(KERN_ERR DRV_NAME " ata%u: error interrupt on port%d\n" | |
498 | " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", | |
499 | ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); | |
500 | ||
501 | if (qc) | |
502 | ata_qc_complete(qc, ATA_ERR); | |
503 | ||
504 | sil24_reset_controller(ap); | |
505 | } | |
506 | ||
edb33667 TH |
507 | static inline void sil24_host_intr(struct ata_port *ap) |
508 | { | |
509 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
4f50c3cb | 510 | void *port = (void *)ap->ioaddr.cmd_addr; |
edb33667 TH |
511 | u32 slot_stat; |
512 | ||
513 | slot_stat = readl(port + PORT_SLOT_STAT); | |
514 | if (!(slot_stat & HOST_SSTAT_ATTN)) { | |
515 | if (qc) | |
516 | ata_qc_complete(qc, 0); | |
8746618d TH |
517 | } else |
518 | sil24_error_intr(ap, slot_stat); | |
edb33667 TH |
519 | } |
520 | ||
521 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
522 | { | |
523 | struct ata_host_set *host_set = dev_instance; | |
524 | struct sil24_host_priv *hpriv = host_set->private_data; | |
525 | unsigned handled = 0; | |
526 | u32 status; | |
527 | int i; | |
528 | ||
529 | status = readl(hpriv->host_base + HOST_IRQ_STAT); | |
530 | ||
06460aea TH |
531 | if (status == 0xffffffff) { |
532 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
533 | "PCI fault or device removal?\n"); | |
534 | goto out; | |
535 | } | |
536 | ||
edb33667 TH |
537 | if (!(status & IRQ_STAT_4PORTS)) |
538 | goto out; | |
539 | ||
540 | spin_lock(&host_set->lock); | |
541 | ||
542 | for (i = 0; i < host_set->n_ports; i++) | |
543 | if (status & (1 << i)) { | |
544 | struct ata_port *ap = host_set->ports[i]; | |
3cc4571c | 545 | if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) { |
edb33667 | 546 | sil24_host_intr(host_set->ports[i]); |
3cc4571c TH |
547 | handled++; |
548 | } else | |
549 | printk(KERN_ERR DRV_NAME | |
550 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
551 | } |
552 | ||
553 | spin_unlock(&host_set->lock); | |
554 | out: | |
555 | return IRQ_RETVAL(handled); | |
556 | } | |
557 | ||
558 | static int sil24_port_start(struct ata_port *ap) | |
559 | { | |
560 | struct device *dev = ap->host_set->dev; | |
edb33667 TH |
561 | struct sil24_port_priv *pp; |
562 | struct sil24_cmd_block *cb; | |
563 | size_t cb_size = sizeof(*cb); | |
564 | dma_addr_t cb_dma; | |
565 | ||
566 | pp = kmalloc(sizeof(*pp), GFP_KERNEL); | |
567 | if (!pp) | |
568 | return -ENOMEM; | |
569 | memset(pp, 0, sizeof(*pp)); | |
570 | ||
571 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); | |
572 | if (!cb) { | |
573 | kfree(pp); | |
574 | return -ENOMEM; | |
575 | } | |
576 | memset(cb, 0, cb_size); | |
577 | ||
edb33667 TH |
578 | pp->cmd_block = cb; |
579 | pp->cmd_block_dma = cb_dma; | |
580 | ||
581 | ap->private_data = pp; | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | static void sil24_port_stop(struct ata_port *ap) | |
587 | { | |
588 | struct device *dev = ap->host_set->dev; | |
589 | struct sil24_port_priv *pp = ap->private_data; | |
590 | size_t cb_size = sizeof(*pp->cmd_block); | |
591 | ||
592 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); | |
593 | kfree(pp); | |
594 | } | |
595 | ||
596 | static void sil24_host_stop(struct ata_host_set *host_set) | |
597 | { | |
598 | struct sil24_host_priv *hpriv = host_set->private_data; | |
599 | ||
600 | iounmap(hpriv->host_base); | |
601 | iounmap(hpriv->port_base); | |
602 | kfree(hpriv); | |
603 | } | |
604 | ||
605 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
606 | { | |
607 | static int printed_version = 0; | |
608 | unsigned int board_id = (unsigned int)ent->driver_data; | |
609 | struct ata_probe_ent *probe_ent = NULL; | |
610 | struct sil24_host_priv *hpriv = NULL; | |
611 | void *host_base = NULL, *port_base = NULL; | |
612 | int i, rc; | |
613 | ||
614 | if (!printed_version++) | |
615 | printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); | |
616 | ||
617 | rc = pci_enable_device(pdev); | |
618 | if (rc) | |
619 | return rc; | |
620 | ||
621 | rc = pci_request_regions(pdev, DRV_NAME); | |
622 | if (rc) | |
623 | goto out_disable; | |
624 | ||
625 | rc = -ENOMEM; | |
626 | /* ioremap mmio registers */ | |
627 | host_base = ioremap(pci_resource_start(pdev, 0), | |
628 | pci_resource_len(pdev, 0)); | |
629 | if (!host_base) | |
630 | goto out_free; | |
631 | port_base = ioremap(pci_resource_start(pdev, 2), | |
632 | pci_resource_len(pdev, 2)); | |
633 | if (!port_base) | |
634 | goto out_free; | |
635 | ||
636 | /* allocate & init probe_ent and hpriv */ | |
637 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
638 | if (!probe_ent) | |
639 | goto out_free; | |
640 | ||
641 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
642 | if (!hpriv) | |
643 | goto out_free; | |
644 | ||
645 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
646 | probe_ent->dev = pci_dev_to_dev(pdev); | |
647 | INIT_LIST_HEAD(&probe_ent->node); | |
648 | ||
649 | probe_ent->sht = sil24_port_info[board_id].sht; | |
650 | probe_ent->host_flags = sil24_port_info[board_id].host_flags; | |
651 | probe_ent->pio_mask = sil24_port_info[board_id].pio_mask; | |
652 | probe_ent->udma_mask = sil24_port_info[board_id].udma_mask; | |
653 | probe_ent->port_ops = sil24_port_info[board_id].port_ops; | |
654 | probe_ent->n_ports = (board_id == BID_SIL3124) ? 4 : 2; | |
655 | ||
656 | probe_ent->irq = pdev->irq; | |
657 | probe_ent->irq_flags = SA_SHIRQ; | |
658 | probe_ent->mmio_base = port_base; | |
659 | probe_ent->private_data = hpriv; | |
660 | ||
661 | memset(hpriv, 0, sizeof(*hpriv)); | |
662 | hpriv->host_base = host_base; | |
663 | hpriv->port_base = port_base; | |
664 | ||
665 | /* | |
666 | * Configure the device | |
667 | */ | |
668 | /* | |
669 | * FIXME: This device is certainly 64-bit capable. We just | |
670 | * don't know how to use it. After fixing 32bit activation in | |
671 | * this function, enable 64bit masks here. | |
672 | */ | |
673 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
674 | if (rc) { | |
675 | printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n", | |
676 | pci_name(pdev)); | |
677 | goto out_free; | |
678 | } | |
679 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
680 | if (rc) { | |
681 | printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n", | |
682 | pci_name(pdev)); | |
683 | goto out_free; | |
684 | } | |
685 | ||
686 | /* GPIO off */ | |
687 | writel(0, host_base + HOST_FLASH_CMD); | |
688 | ||
689 | /* Mask interrupts during initialization */ | |
690 | writel(0, host_base + HOST_CTRL); | |
691 | ||
692 | for (i = 0; i < probe_ent->n_ports; i++) { | |
693 | void *port = port_base + i * PORT_REGS_SIZE; | |
694 | unsigned long portu = (unsigned long)port; | |
695 | u32 tmp; | |
696 | int cnt; | |
697 | ||
4f50c3cb | 698 | probe_ent->port[i].cmd_addr = portu + PORT_PRB; |
edb33667 TH |
699 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
700 | ||
701 | ata_std_ports(&probe_ent->port[i]); | |
702 | ||
703 | /* Initial PHY setting */ | |
704 | writel(0x20c, port + PORT_PHY_CFG); | |
705 | ||
706 | /* Clear port RST */ | |
707 | tmp = readl(port + PORT_CTRL_STAT); | |
708 | if (tmp & PORT_CS_PORT_RST) { | |
709 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
710 | readl(port + PORT_CTRL_STAT); /* sync */ | |
711 | for (cnt = 0; cnt < 10; cnt++) { | |
712 | msleep(10); | |
713 | tmp = readl(port + PORT_CTRL_STAT); | |
714 | if (!(tmp & PORT_CS_PORT_RST)) | |
715 | break; | |
716 | } | |
717 | if (tmp & PORT_CS_PORT_RST) | |
718 | printk(KERN_ERR DRV_NAME | |
719 | "(%s): failed to clear port RST\n", | |
720 | pci_name(pdev)); | |
721 | } | |
722 | ||
723 | /* Zero error counters. */ | |
724 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
725 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
726 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
727 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
728 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
729 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
730 | ||
731 | /* FIXME: 32bit activation? */ | |
732 | writel(0, port + PORT_ACTIVATE_UPPER_ADDR); | |
733 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT); | |
734 | ||
735 | /* Configure interrupts */ | |
736 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
737 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS, | |
738 | port + PORT_IRQ_ENABLE_SET); | |
739 | ||
740 | /* Clear interrupts */ | |
741 | writel(0x0fff0fff, port + PORT_IRQ_STAT); | |
742 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
743 | } | |
744 | ||
745 | /* Turn on interrupts */ | |
746 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
747 | ||
748 | pci_set_master(pdev); | |
749 | ||
1483467f | 750 | /* FIXME: check ata_device_add return value */ |
edb33667 TH |
751 | ata_device_add(probe_ent); |
752 | ||
753 | kfree(probe_ent); | |
754 | return 0; | |
755 | ||
756 | out_free: | |
757 | if (host_base) | |
758 | iounmap(host_base); | |
759 | if (port_base) | |
760 | iounmap(port_base); | |
761 | kfree(probe_ent); | |
762 | kfree(hpriv); | |
763 | pci_release_regions(pdev); | |
764 | out_disable: | |
765 | pci_disable_device(pdev); | |
766 | return rc; | |
767 | } | |
768 | ||
769 | static int __init sil24_init(void) | |
770 | { | |
771 | return pci_module_init(&sil24_pci_driver); | |
772 | } | |
773 | ||
774 | static void __exit sil24_exit(void) | |
775 | { | |
776 | pci_unregister_driver(&sil24_pci_driver); | |
777 | } | |
778 | ||
779 | MODULE_AUTHOR("Tejun Heo"); | |
780 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
781 | MODULE_LICENSE("GPL"); | |
782 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
783 | ||
784 | module_init(sil24_init); | |
785 | module_exit(sil24_exit); |