[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / sata_svw.c

/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
 *		   Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#ifdef CONFIG_PPC_OF
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#endif /* CONFIG_PPC_OF */

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"1.8"

enum {
	/* Taskfile registers offsets */
	K2_SATA_TF_CMD_OFFSET		= 0x00,
	K2_SATA_TF_DATA_OFFSET		= 0x00,
	K2_SATA_TF_ERROR_OFFSET		= 0x04,
	K2_SATA_TF_NSECT_OFFSET		= 0x08,
	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
	K2_SATA_TF_LBAM_OFFSET		= 0x10,
	K2_SATA_TF_LBAH_OFFSET		= 0x14,
	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
	K2_SATA_TF_CTL_OFFSET		= 0x20,

	/* DMA base */
	K2_SATA_DMA_CMD_OFFSET		= 0x30,

	/* SCRs base */
	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,

	/* Others */
	K2_SATA_SICR1_OFFSET		= 0x80,
	K2_SATA_SICR2_OFFSET		= 0x84,
	K2_SATA_SIM_OFFSET		= 0x88,

	/* Port stride */
	K2_SATA_PORT_OFFSET		= 0x100,
};

static u8 k2_stat_check_status(struct ata_port *ap);


static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;
	return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
			       u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;
	writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
}


static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, feature;

	tf->command = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	feature = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->feature = feature;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = feature >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
        }
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host_set lock)
 */

static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void *mmio = (void *) ap->ioaddr.bmdma_addr;
	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host_set lock)
 */

static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void *mmio = (void *) ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* There is a race condition in certain SATA controllers that can
	   be seen when the r/w command is given to the controller before the
	   host DMA is started. On a Read command, the controller would initiate
	   the command to the drive even before it sees the DMA start. When there
	   are very fast drives connected to the controller, or when the data request
	   hits in the drive cache, there is the possibility that the drive returns a part
	   or all of the requested data to the controller before the DMA start is issued.
	   In this case, the controller would become confused as to what to do with the data.
	   In the worst case when all the data is returned back to the controller, the
	   controller could hang. In other cases it could return partial data returning
	   in data corruption. This problem has been seen in PPC systems and can also appear
	   on an system with very fast disks, where the SATA controller is sitting behind a
	   number of bridges, and hence there is significant latency between the r/w command
	   and the start command. */
	/* issue r/w command if the access is to ATA*/
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
       	return readl((void *) ap->ioaddr.status_addr);
}

#ifdef CONFIG_PPC_OF
/*
 * k2_sata_proc_info
 * inout : decides on the direction of the dataflow and the meaning of the
 *	   variables
 * buffer: If inout==FALSE data is being written to it else read from it
 * *start: If inout==FALSE start of the valid data in the buffer
 * offset: If inout==FALSE offset from the beginning of the imaginary file
 *	   from which we start writing into the buffer
 * length: If inout==FALSE max number of bytes to be written into the buffer
 *	   else number of bytes in the buffer
 */
static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
			     off_t offset, int count, int inout)
{
	struct ata_port *ap;
	struct device_node *np;
	int len, index;

	/* Find  the ata_port */
	ap = ata_shost_to_port(shost);
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host_set->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		u32 *reg = (u32 *)get_property(np, "reg", NULL);
		if (!reg)
			continue;
		if (index == *reg)
			break;
	}
	if (np == NULL)
		return 0;

	len = sprintf(page, "devspec: %s\n", np->full_name);

	return len;
}
#endif /* CONFIG_PPC_OF */


static struct scsi_host_template k2_sata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
#ifdef CONFIG_PPC_OF
	.proc_info		= k2_sata_proc_info,
#endif
	.bios_param		= ata_std_bios_param,
};


static const struct ata_port_operations k2_sata_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= k2_sata_tf_load,
	.tf_read		= k2_sata_tf_read,
	.check_status		= k2_stat_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_mmio_data_xfer,
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= ata_bmdma_error_handler,
	.post_internal_cmd	= ata_bmdma_post_internal_cmd,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_pci_host_stop,
};

static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
	struct ata_probe_ent *probe_ent = NULL;
	unsigned long base;
	void __iomem *mmio_base;
	int pci_dev_busy = 0;
	int rc;
	int i;

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pci_enable_device(pdev);
	if (rc)
		return rc;
	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, 5) == 0)
		return -ENODEV;

	/* Request PCI regions */
	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	if (probe_ent == NULL) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	memset(probe_ent, 0, sizeof(*probe_ent));
	probe_ent->dev = pci_dev_to_dev(pdev);
	INIT_LIST_HEAD(&probe_ent->node);

	mmio_base = pci_iomap(pdev, 5, 0);
	if (mmio_base == NULL) {
		rc = -ENOMEM;
		goto err_out_free_ent;
	}
	base = (unsigned long) mmio_base;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	probe_ent->sht = &k2_sata_sht;
	probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
				ATA_FLAG_MMIO;
	probe_ent->port_ops = &k2_sata_ops;
	probe_ent->n_ports = 4;
	probe_ent->irq = pdev->irq;
	probe_ent->irq_flags = SA_SHIRQ;
	probe_ent->mmio_base = mmio_base;

	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	 * if we don't fill these
	 */
	probe_ent->pio_mask = 0x1f;
	probe_ent->mwdma_mask = 0x7;
	probe_ent->udma_mask = 0x7f;

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < ent->driver_data; i++)
		k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);

	pci_set_master(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_free_ent:
	kfree(probe_ent);
err_out_regions:
	pci_release_regions(pdev);
err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
	{ 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ 0x1166, 0x024b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	{ }
};


static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};


static int __init k2_sata_init(void)
{
	return pci_module_init(&k2_sata_pci_driver);
}


static void __exit k2_sata_exit(void)
{
	pci_unregister_driver(&k2_sata_pci_driver);
}


MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(k2_sata_init);
module_exit(k2_sata_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_svw.c - ServerWorks / Apple K2 SATA
	3	*
	4	* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
	5	* Jeff Garzik <jgarzik@pobox.com>
	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
	13	* This driver probably works with non-Apple versions of the
	14	* Broadcom chipset...
	15	*
af36d7f0 JG	16	*
	17	* This program is free software; you can redistribute it and/or modify
	18	* it under the terms of the GNU General Public License as published by
	19	* the Free Software Foundation; either version 2, or (at your option)
	20	* any later version.
	21	*
	22	* This program is distributed in the hope that it will be useful,
	23	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	24	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	25	* GNU General Public License for more details.
	26	*
	27	* You should have received a copy of the GNU General Public License
	28	* along with this program; see the file COPYING. If not, write to
	29	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	30	*
	31	*
	32	* libata documentation is available via 'make {ps\|pdf}docs',
	33	* as Documentation/DocBook/libata.*
	34	*
	35	* Hardware documentation available under NDA.
1da177e4 LT	36	*
	37	*/
	38
	39	#include <linux/config.h>
	40	#include <linux/kernel.h>
	41	#include <linux/module.h>
	42	#include <linux/pci.h>
	43	#include <linux/init.h>
	44	#include <linux/blkdev.h>
	45	#include <linux/delay.h>
	46	#include <linux/interrupt.h>
a9524a76	47	#include <linux/device.h>
1da177e4 LT	48	#include <scsi/scsi_host.h>
	49	#include <linux/libata.h>
	50
	51	#ifdef CONFIG_PPC_OF
	52	#include <asm/prom.h>
	53	#include <asm/pci-bridge.h>
	54	#endif /* CONFIG_PPC_OF */
	55
	56	#define DRV_NAME "sata_svw"
af64371a	57	#define DRV_VERSION "1.8"
1da177e4	58
55cca65e JG	59	enum {
	60	/* Taskfile registers offsets */
	61	K2_SATA_TF_CMD_OFFSET = 0x00,
	62	K2_SATA_TF_DATA_OFFSET = 0x00,
	63	K2_SATA_TF_ERROR_OFFSET = 0x04,
	64	K2_SATA_TF_NSECT_OFFSET = 0x08,
	65	K2_SATA_TF_LBAL_OFFSET = 0x0c,
	66	K2_SATA_TF_LBAM_OFFSET = 0x10,
	67	K2_SATA_TF_LBAH_OFFSET = 0x14,
	68	K2_SATA_TF_DEVICE_OFFSET = 0x18,
	69	K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
	70	K2_SATA_TF_CTL_OFFSET = 0x20,
1da177e4	71
55cca65e JG	72	/* DMA base */
55cca65e JG	73	K2_SATA_DMA_CMD_OFFSET = 0x30,
1da177e4	74
55cca65e JG	75	/* SCRs base */
	76	K2_SATA_SCR_STATUS_OFFSET = 0x40,
	77	K2_SATA_SCR_ERROR_OFFSET = 0x44,
	78	K2_SATA_SCR_CONTROL_OFFSET = 0x48,
1da177e4	79
55cca65e JG	80	/* Others */
	81	K2_SATA_SICR1_OFFSET = 0x80,
	82	K2_SATA_SICR2_OFFSET = 0x84,
	83	K2_SATA_SIM_OFFSET = 0x88,
1da177e4	84
55cca65e JG	85	/* Port stride */
	86	K2_SATA_PORT_OFFSET = 0x100,
	87	};
1da177e4	88
ac19bff2 JG	89	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	90
1da177e4 LT	91
	92	static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
	93	{
	94	if (sc_reg > SCR_CONTROL)
	95	return 0xffffffffU;
	96	return readl((void ) ap->ioaddr.scr_addr + (sc_reg 4));
	97	}
	98
	99
	100	static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
	101	u32 val)
	102	{
	103	if (sc_reg > SCR_CONTROL)
	104	return;
	105	writel(val, (void ) ap->ioaddr.scr_addr + (sc_reg 4));
	106	}
	107
	108
057ace5e	109	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	110	{
	111	struct ata_ioports *ioaddr = &ap->ioaddr;
	112	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	113
	114	if (tf->ctl != ap->last_ctl) {
	115	writeb(tf->ctl, ioaddr->ctl_addr);
	116	ap->last_ctl = tf->ctl;
	117	ata_wait_idle(ap);
	118	}
	119	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
	120	writew(tf->feature \| (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
	121	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
	122	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
	123	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
	124	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
	125	} else if (is_addr) {
	126	writew(tf->feature, ioaddr->feature_addr);
	127	writew(tf->nsect, ioaddr->nsect_addr);
	128	writew(tf->lbal, ioaddr->lbal_addr);
	129	writew(tf->lbam, ioaddr->lbam_addr);
	130	writew(tf->lbah, ioaddr->lbah_addr);
	131	}
	132
	133	if (tf->flags & ATA_TFLAG_DEVICE)
	134	writeb(tf->device, ioaddr->device_addr);
	135
	136	ata_wait_idle(ap);
	137	}
	138
	139
	140	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	141	{
	142	struct ata_ioports *ioaddr = &ap->ioaddr;
ac19bff2	143	u16 nsect, lbal, lbam, lbah, feature;
1da177e4	144
ac19bff2	145	tf->command = k2_stat_check_status(ap);
1da177e4	146	tf->device = readw(ioaddr->device_addr);
ac19bff2 JG	147	feature = readw(ioaddr->error_addr);
	148	nsect = readw(ioaddr->nsect_addr);
	149	lbal = readw(ioaddr->lbal_addr);
	150	lbam = readw(ioaddr->lbam_addr);
	151	lbah = readw(ioaddr->lbah_addr);
	152
	153	tf->feature = feature;
	154	tf->nsect = nsect;
	155	tf->lbal = lbal;
	156	tf->lbam = lbam;
	157	tf->lbah = lbah;
1da177e4 LT	158
1da177e4 LT	159	if (tf->flags & ATA_TFLAG_LBA48) {
ac19bff2	160	tf->hob_feature = feature >> 8;
1da177e4 LT	161	tf->hob_nsect = nsect >> 8;
	162	tf->hob_lbal = lbal >> 8;
	163	tf->hob_lbam = lbam >> 8;
	164	tf->hob_lbah = lbah >> 8;
	165	}
	166	}
	167
	168	/**
	169	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	170	* @qc: Info associated with this ATA transaction.
	171	*
	172	* LOCKING:
	173	* spin_lock_irqsave(host_set lock)
	174	*/
	175
	176	static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
	177	{
	178	struct ata_port *ap = qc->ap;
	179	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	180	u8 dmactl;
	181	void mmio = (void ) ap->ioaddr.bmdma_addr;
	182	/* load PRD table addr. */
	183	mb(); /* make sure PRD table writes are visible to controller */
	184	writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
	185
	186	/* specify data direction, triple-check start bit is clear */
	187	dmactl = readb(mmio + ATA_DMA_CMD);
	188	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	189	if (!rw)
	190	dmactl \|= ATA_DMA_WR;
	191	writeb(dmactl, mmio + ATA_DMA_CMD);
	192
	193	/* issue r/w command if this is not a ATA DMA command*/
	194	if (qc->tf.protocol != ATA_PROT_DMA)
	195	ap->ops->exec_command(ap, &qc->tf);
	196	}
	197
	198	/**
	199	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	200	* @qc: Info associated with this ATA transaction.
	201	*
	202	* LOCKING:
	203	* spin_lock_irqsave(host_set lock)
	204	*/
	205
	206	static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
	207	{
	208	struct ata_port *ap = qc->ap;
	209	void mmio = (void ) ap->ioaddr.bmdma_addr;
	210	u8 dmactl;
	211
	212	/* start host DMA transaction */
	213	dmactl = readb(mmio + ATA_DMA_CMD);
	214	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
8a60a071 JG	215	/* There is a race condition in certain SATA controllers that can
8a60a071 JG	216	be seen when the r/w command is given to the controller before the
1da177e4 LT	217	host DMA is started. On a Read command, the controller would initiate
1da177e4 LT	218	the command to the drive even before it sees the DMA start. When there
8a60a071	219	are very fast drives connected to the controller, or when the data request
1da177e4 LT	220	hits in the drive cache, there is the possibility that the drive returns a part
	221	or all of the requested data to the controller before the DMA start is issued.
	222	In this case, the controller would become confused as to what to do with the data.
	223	In the worst case when all the data is returned back to the controller, the
	224	controller could hang. In other cases it could return partial data returning
	225	in data corruption. This problem has been seen in PPC systems and can also appear
8a60a071	226	on an system with very fast disks, where the SATA controller is sitting behind a
1da177e4 LT	227	number of bridges, and hence there is significant latency between the r/w command
	228	and the start command. */
	229	/* issue r/w command if the access is to ATA*/
	230	if (qc->tf.protocol == ATA_PROT_DMA)
	231	ap->ops->exec_command(ap, &qc->tf);
	232	}
	233
8a60a071	234
1da177e4 LT	235	static u8 k2_stat_check_status(struct ata_port *ap)
	236	{
	237	return readl((void *) ap->ioaddr.status_addr);
	238	}
	239
	240	#ifdef CONFIG_PPC_OF
	241	/*
	242	* k2_sata_proc_info
	243	* inout : decides on the direction of the dataflow and the meaning of the
	244	* variables
	245	* buffer: If inout==FALSE data is being written to it else read from it
	246	* *start: If inout==FALSE start of the valid data in the buffer
	247	* offset: If inout==FALSE offset from the beginning of the imaginary file
	248	* from which we start writing into the buffer
	249	* length: If inout==FALSE max number of bytes to be written into the buffer
	250	* else number of bytes in the buffer
	251	*/
	252	static int k2_sata_proc_info(struct Scsi_Host shost, char page, char **start,
	253	off_t offset, int count, int inout)
	254	{
	255	struct ata_port *ap;
	256	struct device_node *np;
	257	int len, index;
	258
	259	/* Find the ata_port */
35bb94b1	260	ap = ata_shost_to_port(shost);
1da177e4 LT	261	if (ap == NULL)
	262	return 0;
	263
	264	/* Find the OF node for the PCI device proper */
	265	np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
	266	if (np == NULL)
	267	return 0;
	268
	269	/* Match it to a port node */
	270	index = (ap == ap->host_set->ports[0]) ? 0 : 1;
	271	for (np = np->child; np != NULL; np = np->sibling) {
	272	u32 reg = (u32 )get_property(np, "reg", NULL);
	273	if (!reg)
	274	continue;
	275	if (index == *reg)
	276	break;
	277	}
	278	if (np == NULL)
	279	return 0;
	280
	281	len = sprintf(page, "devspec: %s\n", np->full_name);
	282
	283	return len;
	284	}
	285	#endif /* CONFIG_PPC_OF */
	286
	287
193515d5	288	static struct scsi_host_template k2_sata_sht = {
1da177e4 LT	289	.module = THIS_MODULE,
	290	.name = DRV_NAME,
	291	.ioctl = ata_scsi_ioctl,
	292	.queuecommand = ata_scsi_queuecmd,
1da177e4 LT	293	.can_queue = ATA_DEF_QUEUE,
	294	.this_id = ATA_SHT_THIS_ID,
	295	.sg_tablesize = LIBATA_MAX_PRD,
1da177e4 LT	296	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	297	.emulated = ATA_SHT_EMULATED,
	298	.use_clustering = ATA_SHT_USE_CLUSTERING,
	299	.proc_name = DRV_NAME,
	300	.dma_boundary = ATA_DMA_BOUNDARY,
	301	.slave_configure = ata_scsi_slave_config,
ccf68c34	302	.slave_destroy = ata_scsi_slave_destroy,
1da177e4 LT	303	#ifdef CONFIG_PPC_OF
	304	.proc_info = k2_sata_proc_info,
	305	#endif
	306	.bios_param = ata_std_bios_param,
1da177e4 LT	307	};
	308
	309
057ace5e	310	static const struct ata_port_operations k2_sata_ops = {
1da177e4 LT	311	.port_disable = ata_port_disable,
	312	.tf_load = k2_sata_tf_load,
	313	.tf_read = k2_sata_tf_read,
	314	.check_status = k2_stat_check_status,
	315	.exec_command = ata_exec_command,
	316	.dev_select = ata_std_dev_select,
1da177e4 LT	317	.bmdma_setup = k2_bmdma_setup_mmio,
	318	.bmdma_start = k2_bmdma_start_mmio,
	319	.bmdma_stop = ata_bmdma_stop,
	320	.bmdma_status = ata_bmdma_status,
	321	.qc_prep = ata_qc_prep,
	322	.qc_issue = ata_qc_issue_prot,
a6b2c5d4	323	.data_xfer = ata_mmio_data_xfer,
d7a80dad TH	324	.freeze = ata_bmdma_freeze,
	325	.thaw = ata_bmdma_thaw,
	326	.error_handler = ata_bmdma_error_handler,
	327	.post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4 LT	328	.irq_handler = ata_interrupt,
	329	.irq_clear = ata_bmdma_irq_clear,
	330	.scr_read = k2_sata_scr_read,
	331	.scr_write = k2_sata_scr_write,
	332	.port_start = ata_port_start,
	333	.port_stop = ata_port_stop,
374b1873	334	.host_stop = ata_pci_host_stop,
1da177e4 LT	335	};
	336
	337	static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
	338	{
	339	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	340	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	341	port->feature_addr =
	342	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	343	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	344	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	345	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	346	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	347	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	348	port->command_addr =
	349	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	350	port->altstatus_addr =
	351	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	352	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	353	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	354	}
	355
	356
	357	static int k2_sata_init_one (struct pci_dev pdev, const struct pci_device_id ent)
	358	{
	359	static int printed_version;
	360	struct ata_probe_ent *probe_ent = NULL;
	361	unsigned long base;
ea6ba10b	362	void __iomem *mmio_base;
1da177e4 LT	363	int pci_dev_busy = 0;
1da177e4 LT	364	int rc;
60bf09a3	365	int i;
1da177e4 LT	366
1da177e4 LT	367	if (!printed_version++)
a9524a76	368	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4 LT	369
	370	/*
	371	* If this driver happens to only be useful on Apple's K2, then
	372	* we should check that here as it has a normal Serverworks ID
	373	*/
	374	rc = pci_enable_device(pdev);
	375	if (rc)
	376	return rc;
	377	/*
	378	* Check if we have resources mapped at all (second function may
	379	* have been disabled by firmware)
	380	*/
	381	if (pci_resource_len(pdev, 5) == 0)
	382	return -ENODEV;
	383
	384	/* Request PCI regions */
	385	rc = pci_request_regions(pdev, DRV_NAME);
	386	if (rc) {
	387	pci_dev_busy = 1;
	388	goto err_out;
	389	}
	390
	391	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	392	if (rc)
	393	goto err_out_regions;
	394	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	395	if (rc)
	396	goto err_out_regions;
	397
	398	probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
	399	if (probe_ent == NULL) {
	400	rc = -ENOMEM;
	401	goto err_out_regions;
	402	}
	403
	404	memset(probe_ent, 0, sizeof(*probe_ent));
	405	probe_ent->dev = pci_dev_to_dev(pdev);
	406	INIT_LIST_HEAD(&probe_ent->node);
	407
374b1873	408	mmio_base = pci_iomap(pdev, 5, 0);
1da177e4 LT	409	if (mmio_base == NULL) {
	410	rc = -ENOMEM;
	411	goto err_out_free_ent;
	412	}
	413	base = (unsigned long) mmio_base;
	414
	415	/* Clear a magic bit in SCR1 according to Darwin, those help
	416	* some funky seagate drives (though so far, those were already
104e5010	417	* set by the firmware on the machines I had access to)
1da177e4 LT	418	*/
	419	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	420	mmio_base + K2_SATA_SICR1_OFFSET);
	421
	422	/* Clear SATA error & interrupts we don't use */
	423	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	424	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
	425
	426	probe_ent->sht = &k2_sata_sht;
d7a80dad TH	427	probe_ent->host_flags = ATA_FLAG_SATA \| ATA_FLAG_NO_LEGACY \|
d7a80dad TH	428	ATA_FLAG_MMIO;
1da177e4 LT	429	probe_ent->port_ops = &k2_sata_ops;
	430	probe_ent->n_ports = 4;
	431	probe_ent->irq = pdev->irq;
	432	probe_ent->irq_flags = SA_SHIRQ;
	433	probe_ent->mmio_base = mmio_base;
	434
	435	/* We don't care much about the PIO/UDMA masks, but the core won't like us
	436	* if we don't fill these
	437	*/
	438	probe_ent->pio_mask = 0x1f;
	439	probe_ent->mwdma_mask = 0x7;
	440	probe_ent->udma_mask = 0x7f;
	441
60bf09a3 NS	442	/* different controllers have different number of ports - currently 4 or 8 */
	443	/* All ports are on the same function. Multi-function device is no
	444	* longer available. This should not be seen in any system. */
	445	for (i = 0; i < ent->driver_data; i++)
	446	k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);
1da177e4 LT	447
	448	pci_set_master(pdev);
	449
	450	/* FIXME: check ata_device_add return value */
	451	ata_device_add(probe_ent);
	452	kfree(probe_ent);
	453
	454	return 0;
	455
	456	err_out_free_ent:
	457	kfree(probe_ent);
	458	err_out_regions:
	459	pci_release_regions(pdev);
	460	err_out:
	461	if (!pci_dev_busy)
	462	pci_disable_device(pdev);
	463	return rc;
	464	}
	465
60bf09a3 NS	466	/* 0x240 is device ID for Apple K2 device
	467	* 0x241 is device ID for Serverworks Frodo4
	468	* 0x242 is device ID for Serverworks Frodo8
	469	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	470	* controller
	471	* */
3b7d697d	472	static const struct pci_device_id k2_sata_pci_tbl[] = {
60bf09a3 NS	473	{ 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	474	{ 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
	475	{ 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
	476	{ 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
88b52877	477	{ 0x1166, 0x024b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
1da177e4 LT	478	{ }
	479	};
	480
	481
	482	static struct pci_driver k2_sata_pci_driver = {
	483	.name = DRV_NAME,
	484	.id_table = k2_sata_pci_tbl,
	485	.probe = k2_sata_init_one,
	486	.remove = ata_pci_remove_one,
	487	};
	488
	489
	490	static int __init k2_sata_init(void)
	491	{
	492	return pci_module_init(&k2_sata_pci_driver);
	493	}
	494
	495
	496	static void __exit k2_sata_exit(void)
	497	{
	498	pci_unregister_driver(&k2_sata_pci_driver);
	499	}
	500
	501
	502	MODULE_AUTHOR("Benjamin Herrenschmidt");
	503	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	504	MODULE_LICENSE("GPL");
	505	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	506	MODULE_VERSION(DRV_VERSION);
	507
	508	module_init(k2_sata_init);
	509	module_exit(k2_sata_exit);