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1 | /* |
2 | * driver for Microsemi PQI-based storage controllers | |
b805dbfe | 3 | * Copyright (c) 2016-2017 Microsemi Corporation |
6c223761 KB |
4 | * Copyright (c) 2016 PMC-Sierra, Inc. |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
13 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
14 | * | |
15 | * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com | |
16 | * | |
17 | */ | |
18 | ||
ebaec8e3 CL |
19 | #include <linux/io-64-nonatomic-lo-hi.h> |
20 | ||
6c223761 KB |
21 | #if !defined(_SMARTPQI_H) |
22 | #define _SMARTPQI_H | |
23 | ||
24 | #pragma pack(1) | |
25 | ||
26 | #define PQI_DEVICE_SIGNATURE "PQI DREG" | |
27 | ||
28 | /* This structure is defined by the PQI specification. */ | |
29 | struct pqi_device_registers { | |
30 | __le64 signature; | |
31 | u8 function_and_status_code; | |
32 | u8 reserved[7]; | |
33 | u8 max_admin_iq_elements; | |
34 | u8 max_admin_oq_elements; | |
35 | u8 admin_iq_element_length; /* in 16-byte units */ | |
36 | u8 admin_oq_element_length; /* in 16-byte units */ | |
37 | __le16 max_reset_timeout; /* in 100-millisecond units */ | |
38 | u8 reserved1[2]; | |
39 | __le32 legacy_intx_status; | |
40 | __le32 legacy_intx_mask_set; | |
41 | __le32 legacy_intx_mask_clear; | |
42 | u8 reserved2[28]; | |
43 | __le32 device_status; | |
44 | u8 reserved3[4]; | |
45 | __le64 admin_iq_pi_offset; | |
46 | __le64 admin_oq_ci_offset; | |
47 | __le64 admin_iq_element_array_addr; | |
48 | __le64 admin_oq_element_array_addr; | |
49 | __le64 admin_iq_ci_addr; | |
50 | __le64 admin_oq_pi_addr; | |
51 | u8 admin_iq_num_elements; | |
52 | u8 admin_oq_num_elements; | |
53 | __le16 admin_queue_int_msg_num; | |
54 | u8 reserved4[4]; | |
55 | __le32 device_error; | |
56 | u8 reserved5[4]; | |
57 | __le64 error_details; | |
58 | __le32 device_reset; | |
59 | __le32 power_action; | |
60 | u8 reserved6[104]; | |
61 | }; | |
62 | ||
63 | /* | |
64 | * controller registers | |
65 | * | |
061ef06a | 66 | * These are defined by the Microsemi implementation. |
6c223761 KB |
67 | * |
68 | * Some registers (those named sis_*) are only used when in | |
69 | * legacy SIS mode before we transition the controller into | |
70 | * PQI mode. There are a number of other SIS mode registers, | |
71 | * but we don't use them, so only the SIS registers that we | |
72 | * care about are defined here. The offsets mentioned in the | |
73 | * comments are the offsets from the PCIe BAR 0. | |
74 | */ | |
75 | struct pqi_ctrl_registers { | |
76 | u8 reserved[0x20]; | |
77 | __le32 sis_host_to_ctrl_doorbell; /* 20h */ | |
78 | u8 reserved1[0x34 - (0x20 + sizeof(__le32))]; | |
79 | __le32 sis_interrupt_mask; /* 34h */ | |
80 | u8 reserved2[0x9c - (0x34 + sizeof(__le32))]; | |
81 | __le32 sis_ctrl_to_host_doorbell; /* 9Ch */ | |
82 | u8 reserved3[0xa0 - (0x9c + sizeof(__le32))]; | |
83 | __le32 sis_ctrl_to_host_doorbell_clear; /* A0h */ | |
ff6abb73 KB |
84 | u8 reserved4[0xb0 - (0xa0 + sizeof(__le32))]; |
85 | __le32 sis_driver_scratch; /* B0h */ | |
86 | u8 reserved5[0xbc - (0xb0 + sizeof(__le32))]; | |
6c223761 | 87 | __le32 sis_firmware_status; /* BCh */ |
ff6abb73 | 88 | u8 reserved6[0x1000 - (0xbc + sizeof(__le32))]; |
6c223761 | 89 | __le32 sis_mailbox[8]; /* 1000h */ |
ff6abb73 | 90 | u8 reserved7[0x4000 - (0x1000 + (sizeof(__le32) * 8))]; |
6c223761 KB |
91 | /* |
92 | * The PQI spec states that the PQI registers should be at | |
93 | * offset 0 from the PCIe BAR 0. However, we can't map | |
94 | * them at offset 0 because that would break compatibility | |
95 | * with the SIS registers. So we map them at offset 4000h. | |
96 | */ | |
97 | struct pqi_device_registers pqi_registers; /* 4000h */ | |
98 | }; | |
99 | ||
100 | #define PQI_DEVICE_REGISTERS_OFFSET 0x4000 | |
101 | ||
102 | enum pqi_io_path { | |
103 | RAID_PATH = 0, | |
104 | AIO_PATH = 1 | |
105 | }; | |
106 | ||
061ef06a KB |
107 | enum pqi_irq_mode { |
108 | IRQ_MODE_NONE, | |
109 | IRQ_MODE_INTX, | |
110 | IRQ_MODE_MSIX | |
111 | }; | |
112 | ||
6c223761 KB |
113 | struct pqi_sg_descriptor { |
114 | __le64 address; | |
115 | __le32 length; | |
116 | __le32 flags; | |
117 | }; | |
118 | ||
119 | /* manifest constants for the flags field of pqi_sg_descriptor */ | |
120 | #define CISS_SG_LAST 0x40000000 | |
121 | #define CISS_SG_CHAIN 0x80000000 | |
122 | ||
123 | struct pqi_iu_header { | |
124 | u8 iu_type; | |
125 | u8 reserved; | |
126 | __le16 iu_length; /* in bytes - does not include the length */ | |
127 | /* of this header */ | |
128 | __le16 response_queue_id; /* specifies the OQ where the */ | |
129 | /* response IU is to be delivered */ | |
130 | u8 work_area[2]; /* reserved for driver use */ | |
131 | }; | |
132 | ||
133 | /* | |
134 | * According to the PQI spec, the IU header is only the first 4 bytes of our | |
135 | * pqi_iu_header structure. | |
136 | */ | |
137 | #define PQI_REQUEST_HEADER_LENGTH 4 | |
138 | ||
139 | struct pqi_general_admin_request { | |
140 | struct pqi_iu_header header; | |
141 | __le16 request_id; | |
142 | u8 function_code; | |
143 | union { | |
144 | struct { | |
145 | u8 reserved[33]; | |
146 | __le32 buffer_length; | |
147 | struct pqi_sg_descriptor sg_descriptor; | |
148 | } report_device_capability; | |
149 | ||
150 | struct { | |
151 | u8 reserved; | |
152 | __le16 queue_id; | |
153 | u8 reserved1[2]; | |
154 | __le64 element_array_addr; | |
155 | __le64 ci_addr; | |
156 | __le16 num_elements; | |
157 | __le16 element_length; | |
158 | u8 queue_protocol; | |
159 | u8 reserved2[23]; | |
160 | __le32 vendor_specific; | |
161 | } create_operational_iq; | |
162 | ||
163 | struct { | |
164 | u8 reserved; | |
165 | __le16 queue_id; | |
166 | u8 reserved1[2]; | |
167 | __le64 element_array_addr; | |
168 | __le64 pi_addr; | |
169 | __le16 num_elements; | |
170 | __le16 element_length; | |
171 | u8 queue_protocol; | |
172 | u8 reserved2[3]; | |
173 | __le16 int_msg_num; | |
174 | __le16 coalescing_count; | |
175 | __le32 min_coalescing_time; | |
176 | __le32 max_coalescing_time; | |
177 | u8 reserved3[8]; | |
178 | __le32 vendor_specific; | |
179 | } create_operational_oq; | |
180 | ||
181 | struct { | |
182 | u8 reserved; | |
183 | __le16 queue_id; | |
184 | u8 reserved1[50]; | |
185 | } delete_operational_queue; | |
186 | ||
187 | struct { | |
188 | u8 reserved; | |
189 | __le16 queue_id; | |
190 | u8 reserved1[46]; | |
191 | __le32 vendor_specific; | |
192 | } change_operational_iq_properties; | |
193 | ||
194 | } data; | |
195 | }; | |
196 | ||
197 | struct pqi_general_admin_response { | |
198 | struct pqi_iu_header header; | |
199 | __le16 request_id; | |
200 | u8 function_code; | |
201 | u8 status; | |
202 | union { | |
203 | struct { | |
204 | u8 status_descriptor[4]; | |
205 | __le64 iq_pi_offset; | |
206 | u8 reserved[40]; | |
207 | } create_operational_iq; | |
208 | ||
209 | struct { | |
210 | u8 status_descriptor[4]; | |
211 | __le64 oq_ci_offset; | |
212 | u8 reserved[40]; | |
213 | } create_operational_oq; | |
214 | } data; | |
215 | }; | |
216 | ||
217 | struct pqi_iu_layer_descriptor { | |
218 | u8 inbound_spanning_supported : 1; | |
219 | u8 reserved : 7; | |
220 | u8 reserved1[5]; | |
221 | __le16 max_inbound_iu_length; | |
222 | u8 outbound_spanning_supported : 1; | |
223 | u8 reserved2 : 7; | |
224 | u8 reserved3[5]; | |
225 | __le16 max_outbound_iu_length; | |
226 | }; | |
227 | ||
228 | struct pqi_device_capability { | |
229 | __le16 data_length; | |
230 | u8 reserved[6]; | |
231 | u8 iq_arbitration_priority_support_bitmask; | |
232 | u8 maximum_aw_a; | |
233 | u8 maximum_aw_b; | |
234 | u8 maximum_aw_c; | |
235 | u8 max_arbitration_burst : 3; | |
236 | u8 reserved1 : 4; | |
237 | u8 iqa : 1; | |
238 | u8 reserved2[2]; | |
239 | u8 iq_freeze : 1; | |
240 | u8 reserved3 : 7; | |
241 | __le16 max_inbound_queues; | |
242 | __le16 max_elements_per_iq; | |
243 | u8 reserved4[4]; | |
244 | __le16 max_iq_element_length; | |
245 | __le16 min_iq_element_length; | |
246 | u8 reserved5[2]; | |
247 | __le16 max_outbound_queues; | |
248 | __le16 max_elements_per_oq; | |
249 | __le16 intr_coalescing_time_granularity; | |
250 | __le16 max_oq_element_length; | |
251 | __le16 min_oq_element_length; | |
252 | u8 reserved6[24]; | |
253 | struct pqi_iu_layer_descriptor iu_layer_descriptors[32]; | |
254 | }; | |
255 | ||
256 | #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS 4 | |
257 | ||
258 | struct pqi_raid_path_request { | |
259 | struct pqi_iu_header header; | |
260 | __le16 request_id; | |
261 | __le16 nexus_id; | |
262 | __le32 buffer_length; | |
263 | u8 lun_number[8]; | |
264 | __le16 protocol_specific; | |
265 | u8 data_direction : 2; | |
266 | u8 partial : 1; | |
267 | u8 reserved1 : 4; | |
268 | u8 fence : 1; | |
269 | __le16 error_index; | |
270 | u8 reserved2; | |
271 | u8 task_attribute : 3; | |
272 | u8 command_priority : 4; | |
273 | u8 reserved3 : 1; | |
274 | u8 reserved4 : 2; | |
275 | u8 additional_cdb_bytes_usage : 3; | |
276 | u8 reserved5 : 3; | |
277 | u8 cdb[32]; | |
278 | struct pqi_sg_descriptor | |
279 | sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; | |
280 | }; | |
281 | ||
282 | struct pqi_aio_path_request { | |
283 | struct pqi_iu_header header; | |
284 | __le16 request_id; | |
285 | u8 reserved1[2]; | |
286 | __le32 nexus_id; | |
287 | __le32 buffer_length; | |
288 | u8 data_direction : 2; | |
289 | u8 partial : 1; | |
290 | u8 memory_type : 1; | |
291 | u8 fence : 1; | |
292 | u8 encryption_enable : 1; | |
293 | u8 reserved2 : 2; | |
294 | u8 task_attribute : 3; | |
295 | u8 command_priority : 4; | |
296 | u8 reserved3 : 1; | |
297 | __le16 data_encryption_key_index; | |
298 | __le32 encrypt_tweak_lower; | |
299 | __le32 encrypt_tweak_upper; | |
300 | u8 cdb[16]; | |
301 | __le16 error_index; | |
302 | u8 num_sg_descriptors; | |
303 | u8 cdb_length; | |
304 | u8 lun_number[8]; | |
305 | u8 reserved4[4]; | |
306 | struct pqi_sg_descriptor | |
307 | sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS]; | |
308 | }; | |
309 | ||
310 | struct pqi_io_response { | |
311 | struct pqi_iu_header header; | |
312 | __le16 request_id; | |
313 | __le16 error_index; | |
314 | u8 reserved2[4]; | |
315 | }; | |
316 | ||
317 | struct pqi_general_management_request { | |
318 | struct pqi_iu_header header; | |
319 | __le16 request_id; | |
320 | union { | |
321 | struct { | |
322 | u8 reserved[2]; | |
323 | __le32 buffer_length; | |
324 | struct pqi_sg_descriptor sg_descriptors[3]; | |
325 | } report_event_configuration; | |
326 | ||
327 | struct { | |
328 | __le16 global_event_oq_id; | |
329 | __le32 buffer_length; | |
330 | struct pqi_sg_descriptor sg_descriptors[3]; | |
331 | } set_event_configuration; | |
332 | } data; | |
333 | }; | |
334 | ||
335 | struct pqi_event_descriptor { | |
336 | u8 event_type; | |
337 | u8 reserved; | |
338 | __le16 oq_id; | |
339 | }; | |
340 | ||
341 | struct pqi_event_config { | |
342 | u8 reserved[2]; | |
343 | u8 num_event_descriptors; | |
344 | u8 reserved1; | |
345 | struct pqi_event_descriptor descriptors[1]; | |
346 | }; | |
347 | ||
348 | #define PQI_MAX_EVENT_DESCRIPTORS 255 | |
349 | ||
350 | struct pqi_event_response { | |
351 | struct pqi_iu_header header; | |
352 | u8 event_type; | |
353 | u8 reserved2 : 7; | |
354 | u8 request_acknowlege : 1; | |
355 | __le16 event_id; | |
356 | __le32 additional_event_id; | |
357 | u8 data[16]; | |
358 | }; | |
359 | ||
360 | struct pqi_event_acknowledge_request { | |
361 | struct pqi_iu_header header; | |
362 | u8 event_type; | |
363 | u8 reserved2; | |
364 | __le16 event_id; | |
365 | __le32 additional_event_id; | |
366 | }; | |
367 | ||
368 | struct pqi_task_management_request { | |
369 | struct pqi_iu_header header; | |
370 | __le16 request_id; | |
371 | __le16 nexus_id; | |
372 | u8 reserved[4]; | |
373 | u8 lun_number[8]; | |
374 | __le16 protocol_specific; | |
375 | __le16 outbound_queue_id_to_manage; | |
376 | __le16 request_id_to_manage; | |
377 | u8 task_management_function; | |
378 | u8 reserved2 : 7; | |
379 | u8 fence : 1; | |
380 | }; | |
381 | ||
382 | #define SOP_TASK_MANAGEMENT_LUN_RESET 0x8 | |
6c223761 KB |
383 | |
384 | struct pqi_task_management_response { | |
385 | struct pqi_iu_header header; | |
386 | __le16 request_id; | |
387 | __le16 nexus_id; | |
388 | u8 additional_response_info[3]; | |
389 | u8 response_code; | |
390 | }; | |
391 | ||
392 | struct pqi_aio_error_info { | |
393 | u8 status; | |
394 | u8 service_response; | |
395 | u8 data_present; | |
396 | u8 reserved; | |
397 | __le32 residual_count; | |
398 | __le16 data_length; | |
399 | __le16 reserved1; | |
400 | u8 data[256]; | |
401 | }; | |
402 | ||
403 | struct pqi_raid_error_info { | |
404 | u8 data_in_result; | |
405 | u8 data_out_result; | |
406 | u8 reserved[3]; | |
407 | u8 status; | |
408 | __le16 status_qualifier; | |
409 | __le16 sense_data_length; | |
410 | __le16 response_data_length; | |
411 | __le32 data_in_transferred; | |
412 | __le32 data_out_transferred; | |
413 | u8 data[256]; | |
414 | }; | |
415 | ||
416 | #define PQI_REQUEST_IU_TASK_MANAGEMENT 0x13 | |
417 | #define PQI_REQUEST_IU_RAID_PATH_IO 0x14 | |
418 | #define PQI_REQUEST_IU_AIO_PATH_IO 0x15 | |
419 | #define PQI_REQUEST_IU_GENERAL_ADMIN 0x60 | |
420 | #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG 0x72 | |
421 | #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG 0x73 | |
422 | #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT 0xf6 | |
423 | ||
424 | #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT 0x81 | |
425 | #define PQI_RESPONSE_IU_TASK_MANAGEMENT 0x93 | |
426 | #define PQI_RESPONSE_IU_GENERAL_ADMIN 0xe0 | |
427 | #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS 0xf0 | |
428 | #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS 0xf1 | |
429 | #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR 0xf2 | |
430 | #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR 0xf3 | |
431 | #define PQI_RESPONSE_IU_AIO_PATH_DISABLED 0xf4 | |
432 | #define PQI_RESPONSE_IU_VENDOR_EVENT 0xf5 | |
433 | ||
434 | #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0 | |
435 | #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ 0x10 | |
436 | #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ 0x11 | |
437 | #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ 0x12 | |
438 | #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ 0x13 | |
439 | #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY 0x14 | |
440 | ||
441 | #define PQI_GENERAL_ADMIN_STATUS_SUCCESS 0x0 | |
442 | ||
443 | #define PQI_IQ_PROPERTY_IS_AIO_QUEUE 0x1 | |
444 | ||
445 | #define PQI_GENERAL_ADMIN_IU_LENGTH 0x3c | |
446 | #define PQI_PROTOCOL_SOP 0x0 | |
447 | ||
448 | #define PQI_DATA_IN_OUT_GOOD 0x0 | |
449 | #define PQI_DATA_IN_OUT_UNDERFLOW 0x1 | |
450 | #define PQI_DATA_IN_OUT_BUFFER_ERROR 0x40 | |
451 | #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW 0x41 | |
452 | #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA 0x42 | |
453 | #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE 0x43 | |
454 | #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR 0x60 | |
455 | #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT 0x61 | |
456 | #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED 0x62 | |
457 | #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED 0x63 | |
458 | #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED 0x64 | |
459 | #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST 0x65 | |
460 | #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION 0x66 | |
461 | #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED 0x67 | |
462 | #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ 0x6F | |
463 | #define PQI_DATA_IN_OUT_ERROR 0xf0 | |
464 | #define PQI_DATA_IN_OUT_PROTOCOL_ERROR 0xf1 | |
465 | #define PQI_DATA_IN_OUT_HARDWARE_ERROR 0xf2 | |
466 | #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT 0xf3 | |
467 | #define PQI_DATA_IN_OUT_ABORTED 0xf4 | |
468 | #define PQI_DATA_IN_OUT_TIMEOUT 0xf5 | |
469 | ||
470 | #define CISS_CMD_STATUS_SUCCESS 0x0 | |
471 | #define CISS_CMD_STATUS_TARGET_STATUS 0x1 | |
472 | #define CISS_CMD_STATUS_DATA_UNDERRUN 0x2 | |
473 | #define CISS_CMD_STATUS_DATA_OVERRUN 0x3 | |
474 | #define CISS_CMD_STATUS_INVALID 0x4 | |
475 | #define CISS_CMD_STATUS_PROTOCOL_ERROR 0x5 | |
476 | #define CISS_CMD_STATUS_HARDWARE_ERROR 0x6 | |
477 | #define CISS_CMD_STATUS_CONNECTION_LOST 0x7 | |
478 | #define CISS_CMD_STATUS_ABORTED 0x8 | |
479 | #define CISS_CMD_STATUS_ABORT_FAILED 0x9 | |
480 | #define CISS_CMD_STATUS_UNSOLICITED_ABORT 0xa | |
481 | #define CISS_CMD_STATUS_TIMEOUT 0xb | |
482 | #define CISS_CMD_STATUS_UNABORTABLE 0xc | |
483 | #define CISS_CMD_STATUS_TMF 0xd | |
484 | #define CISS_CMD_STATUS_AIO_DISABLED 0xe | |
485 | ||
486 | #define PQI_NUM_EVENT_QUEUE_ELEMENTS 32 | |
487 | #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response) | |
488 | ||
489 | #define PQI_EVENT_TYPE_HOTPLUG 0x1 | |
490 | #define PQI_EVENT_TYPE_HARDWARE 0x2 | |
491 | #define PQI_EVENT_TYPE_PHYSICAL_DEVICE 0x4 | |
492 | #define PQI_EVENT_TYPE_LOGICAL_DEVICE 0x5 | |
493 | #define PQI_EVENT_TYPE_AIO_STATE_CHANGE 0xfd | |
494 | #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE 0xfe | |
6c223761 KB |
495 | |
496 | #pragma pack() | |
497 | ||
498 | #define PQI_ERROR_BUFFER_ELEMENT_LENGTH \ | |
499 | sizeof(struct pqi_raid_error_info) | |
500 | ||
501 | /* these values are based on our implementation */ | |
502 | #define PQI_ADMIN_IQ_NUM_ELEMENTS 8 | |
503 | #define PQI_ADMIN_OQ_NUM_ELEMENTS 20 | |
504 | #define PQI_ADMIN_IQ_ELEMENT_LENGTH 64 | |
505 | #define PQI_ADMIN_OQ_ELEMENT_LENGTH 64 | |
506 | ||
507 | #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH 128 | |
508 | #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH 16 | |
509 | ||
510 | #define PQI_MIN_MSIX_VECTORS 1 | |
511 | #define PQI_MAX_MSIX_VECTORS 64 | |
512 | ||
513 | /* these values are defined by the PQI spec */ | |
514 | #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE 255 | |
515 | #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE 65535 | |
516 | #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT 64 | |
517 | #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT 16 | |
518 | #define PQI_ADMIN_INDEX_ALIGNMENT 64 | |
519 | #define PQI_OPERATIONAL_INDEX_ALIGNMENT 4 | |
520 | ||
521 | #define PQI_MIN_OPERATIONAL_QUEUE_ID 1 | |
522 | #define PQI_MAX_OPERATIONAL_QUEUE_ID 65535 | |
523 | ||
524 | #define PQI_AIO_SERV_RESPONSE_COMPLETE 0 | |
525 | #define PQI_AIO_SERV_RESPONSE_FAILURE 1 | |
526 | #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE 2 | |
527 | #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3 | |
528 | #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED 4 | |
529 | #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5 | |
530 | ||
531 | #define PQI_AIO_STATUS_IO_ERROR 0x1 | |
532 | #define PQI_AIO_STATUS_IO_ABORTED 0x2 | |
533 | #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE 0x3 | |
534 | #define PQI_AIO_STATUS_INVALID_DEVICE 0x4 | |
535 | #define PQI_AIO_STATUS_AIO_PATH_DISABLED 0xe | |
536 | #define PQI_AIO_STATUS_UNDERRUN 0x51 | |
537 | #define PQI_AIO_STATUS_OVERRUN 0x75 | |
538 | ||
539 | typedef u32 pqi_index_t; | |
540 | ||
541 | /* SOP data direction flags */ | |
542 | #define SOP_NO_DIRECTION_FLAG 0 | |
543 | #define SOP_WRITE_FLAG 1 /* host writes data to Data-Out */ | |
544 | /* buffer */ | |
545 | #define SOP_READ_FLAG 2 /* host receives data from Data-In */ | |
546 | /* buffer */ | |
547 | #define SOP_BIDIRECTIONAL 3 /* data is transferred from the */ | |
548 | /* Data-Out buffer and data is */ | |
549 | /* transferred to the Data-In buffer */ | |
550 | ||
551 | #define SOP_TASK_ATTRIBUTE_SIMPLE 0 | |
552 | #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE 1 | |
553 | #define SOP_TASK_ATTRIBUTE_ORDERED 2 | |
554 | #define SOP_TASK_ATTRIBUTE_ACA 4 | |
555 | ||
b17f0486 KB |
556 | #define SOP_TMF_COMPLETE 0x0 |
557 | #define SOP_TMF_FUNCTION_SUCCEEDED 0x8 | |
6c223761 KB |
558 | |
559 | /* additional CDB bytes usage field codes */ | |
560 | #define SOP_ADDITIONAL_CDB_BYTES_0 0 /* 16-byte CDB */ | |
561 | #define SOP_ADDITIONAL_CDB_BYTES_4 1 /* 20-byte CDB */ | |
562 | #define SOP_ADDITIONAL_CDB_BYTES_8 2 /* 24-byte CDB */ | |
563 | #define SOP_ADDITIONAL_CDB_BYTES_12 3 /* 28-byte CDB */ | |
564 | #define SOP_ADDITIONAL_CDB_BYTES_16 4 /* 32-byte CDB */ | |
565 | ||
566 | /* | |
567 | * The purpose of this structure is to obtain proper alignment of objects in | |
568 | * an admin queue pair. | |
569 | */ | |
570 | struct pqi_admin_queues_aligned { | |
571 | __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) | |
572 | u8 iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH] | |
573 | [PQI_ADMIN_IQ_NUM_ELEMENTS]; | |
574 | __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT) | |
575 | u8 oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH] | |
576 | [PQI_ADMIN_OQ_NUM_ELEMENTS]; | |
577 | __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci; | |
578 | __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi; | |
579 | }; | |
580 | ||
581 | struct pqi_admin_queues { | |
582 | void *iq_element_array; | |
583 | void *oq_element_array; | |
584 | volatile pqi_index_t *iq_ci; | |
585 | volatile pqi_index_t *oq_pi; | |
586 | dma_addr_t iq_element_array_bus_addr; | |
587 | dma_addr_t oq_element_array_bus_addr; | |
588 | dma_addr_t iq_ci_bus_addr; | |
589 | dma_addr_t oq_pi_bus_addr; | |
590 | __le32 __iomem *iq_pi; | |
591 | pqi_index_t iq_pi_copy; | |
592 | __le32 __iomem *oq_ci; | |
593 | pqi_index_t oq_ci_copy; | |
594 | struct task_struct *task; | |
595 | u16 int_msg_num; | |
596 | }; | |
597 | ||
598 | struct pqi_queue_group { | |
599 | struct pqi_ctrl_info *ctrl_info; /* backpointer */ | |
600 | u16 iq_id[2]; | |
601 | u16 oq_id; | |
602 | u16 int_msg_num; | |
603 | void *iq_element_array[2]; | |
604 | void *oq_element_array; | |
605 | dma_addr_t iq_element_array_bus_addr[2]; | |
606 | dma_addr_t oq_element_array_bus_addr; | |
607 | __le32 __iomem *iq_pi[2]; | |
608 | pqi_index_t iq_pi_copy[2]; | |
609 | volatile pqi_index_t *iq_ci[2]; | |
610 | volatile pqi_index_t *oq_pi; | |
611 | dma_addr_t iq_ci_bus_addr[2]; | |
612 | dma_addr_t oq_pi_bus_addr; | |
613 | __le32 __iomem *oq_ci; | |
614 | pqi_index_t oq_ci_copy; | |
615 | spinlock_t submit_lock[2]; /* protect submission queue */ | |
616 | struct list_head request_list[2]; | |
617 | }; | |
618 | ||
619 | struct pqi_event_queue { | |
620 | u16 oq_id; | |
621 | u16 int_msg_num; | |
622 | void *oq_element_array; | |
623 | volatile pqi_index_t *oq_pi; | |
624 | dma_addr_t oq_element_array_bus_addr; | |
625 | dma_addr_t oq_pi_bus_addr; | |
626 | __le32 __iomem *oq_ci; | |
627 | pqi_index_t oq_ci_copy; | |
628 | }; | |
629 | ||
630 | #define PQI_DEFAULT_QUEUE_GROUP 0 | |
631 | #define PQI_MAX_QUEUE_GROUPS PQI_MAX_MSIX_VECTORS | |
632 | ||
633 | struct pqi_encryption_info { | |
634 | u16 data_encryption_key_index; | |
635 | u32 encrypt_tweak_lower; | |
636 | u32 encrypt_tweak_upper; | |
637 | }; | |
638 | ||
98f87667 KB |
639 | #pragma pack(1) |
640 | ||
641 | #define PQI_CONFIG_TABLE_SIGNATURE "CFGTABLE" | |
642 | #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0) | |
643 | ||
644 | /* configuration table section IDs */ | |
645 | #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO 0 | |
646 | #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES 1 | |
647 | #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA 2 | |
648 | #define PQI_CONFIG_TABLE_SECTION_DEBUG 3 | |
649 | #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT 4 | |
650 | ||
651 | struct pqi_config_table { | |
652 | u8 signature[8]; /* "CFGTABLE" */ | |
653 | __le32 first_section_offset; /* offset in bytes from the base */ | |
654 | /* address of this table to the */ | |
655 | /* first section */ | |
656 | }; | |
657 | ||
658 | struct pqi_config_table_section_header { | |
659 | __le16 section_id; /* as defined by the */ | |
660 | /* PQI_CONFIG_TABLE_SECTION_* */ | |
661 | /* manifest constants above */ | |
662 | __le16 next_section_offset; /* offset in bytes from base */ | |
663 | /* address of the table of the */ | |
664 | /* next section or 0 if last entry */ | |
665 | }; | |
666 | ||
667 | struct pqi_config_table_general_info { | |
668 | struct pqi_config_table_section_header header; | |
669 | __le32 section_length; /* size of this section in bytes */ | |
670 | /* including the section header */ | |
671 | __le32 max_outstanding_requests; /* max. outstanding */ | |
672 | /* commands supported by */ | |
673 | /* the controller */ | |
674 | __le32 max_sg_size; /* max. transfer size of a single */ | |
675 | /* command */ | |
676 | __le32 max_sg_per_request; /* max. number of scatter-gather */ | |
677 | /* entries supported in a single */ | |
678 | /* command */ | |
679 | }; | |
680 | ||
681 | struct pqi_config_table_debug { | |
682 | struct pqi_config_table_section_header header; | |
683 | __le32 scratchpad; | |
684 | }; | |
685 | ||
686 | struct pqi_config_table_heartbeat { | |
687 | struct pqi_config_table_section_header header; | |
688 | __le32 heartbeat_counter; | |
689 | }; | |
690 | ||
d727a776 KB |
691 | #define PQI_MAX_OUTSTANDING_REQUESTS ((u32)~0) |
692 | #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP 32 | |
eeee4107 | 693 | #define PQI_MAX_TRANSFER_SIZE (1024U * 1024U) |
d727a776 | 694 | #define PQI_MAX_TRANSFER_SIZE_KDUMP (512 * 1024U) |
6c223761 KB |
695 | |
696 | #define RAID_MAP_MAX_ENTRIES 1024 | |
697 | ||
6c223761 KB |
698 | #define PQI_PHYSICAL_DEVICE_BUS 0 |
699 | #define PQI_RAID_VOLUME_BUS 1 | |
700 | #define PQI_HBA_BUS 2 | |
bd10cf0b KB |
701 | #define PQI_EXTERNAL_RAID_VOLUME_BUS 3 |
702 | #define PQI_MAX_BUS PQI_EXTERNAL_RAID_VOLUME_BUS | |
6c223761 | 703 | |
6c223761 KB |
704 | struct report_lun_header { |
705 | __be32 list_length; | |
706 | u8 extended_response; | |
707 | u8 reserved[3]; | |
708 | }; | |
709 | ||
710 | struct report_log_lun_extended_entry { | |
711 | u8 lunid[8]; | |
712 | u8 volume_id[16]; | |
713 | }; | |
714 | ||
715 | struct report_log_lun_extended { | |
716 | struct report_lun_header header; | |
717 | struct report_log_lun_extended_entry lun_entries[1]; | |
718 | }; | |
719 | ||
720 | struct report_phys_lun_extended_entry { | |
721 | u8 lunid[8]; | |
722 | __be64 wwid; | |
723 | u8 device_type; | |
724 | u8 device_flags; | |
725 | u8 lun_count; /* number of LUNs in a multi-LUN device */ | |
726 | u8 redundant_paths; | |
727 | u32 aio_handle; | |
728 | }; | |
729 | ||
730 | /* for device_flags field of struct report_phys_lun_extended_entry */ | |
6c223761 KB |
731 | #define REPORT_PHYS_LUN_DEV_FLAG_AIO_ENABLED 0x8 |
732 | ||
733 | struct report_phys_lun_extended { | |
734 | struct report_lun_header header; | |
735 | struct report_phys_lun_extended_entry lun_entries[1]; | |
736 | }; | |
737 | ||
738 | struct raid_map_disk_data { | |
739 | u32 aio_handle; | |
740 | u8 xor_mult[2]; | |
741 | u8 reserved[2]; | |
742 | }; | |
743 | ||
744 | /* constants for flags field of RAID map */ | |
745 | #define RAID_MAP_ENCRYPTION_ENABLED 0x1 | |
746 | ||
747 | struct raid_map { | |
748 | __le32 structure_size; /* size of entire structure in bytes */ | |
749 | __le32 volume_blk_size; /* bytes / block in the volume */ | |
750 | __le64 volume_blk_cnt; /* logical blocks on the volume */ | |
751 | u8 phys_blk_shift; /* shift factor to convert between */ | |
752 | /* units of logical blocks and */ | |
753 | /* physical disk blocks */ | |
754 | u8 parity_rotation_shift; /* shift factor to convert between */ | |
755 | /* units of logical stripes and */ | |
756 | /* physical stripes */ | |
757 | __le16 strip_size; /* blocks used on each disk / stripe */ | |
758 | __le64 disk_starting_blk; /* first disk block used in volume */ | |
759 | __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ | |
760 | __le16 data_disks_per_row; /* data disk entries / row in the map */ | |
761 | __le16 metadata_disks_per_row; /* mirror/parity disk entries / row */ | |
762 | /* in the map */ | |
763 | __le16 row_cnt; /* rows in each layout map */ | |
764 | __le16 layout_map_count; /* layout maps (1 map per */ | |
765 | /* mirror parity group) */ | |
766 | __le16 flags; | |
767 | __le16 data_encryption_key_index; | |
768 | u8 reserved[16]; | |
769 | struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES]; | |
770 | }; | |
771 | ||
772 | #pragma pack() | |
773 | ||
774 | #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" | |
775 | ||
776 | struct pqi_scsi_dev { | |
777 | int devtype; /* as reported by INQUIRY commmand */ | |
778 | u8 device_type; /* as reported by */ | |
779 | /* BMIC_IDENTIFY_PHYSICAL_DEVICE */ | |
780 | /* only valid for devtype = TYPE_DISK */ | |
781 | int bus; | |
782 | int target; | |
783 | int lun; | |
784 | u8 scsi3addr[8]; | |
785 | __be64 wwid; | |
786 | u8 volume_id[16]; | |
787 | u8 is_physical_device : 1; | |
bd10cf0b | 788 | u8 is_external_raid_device : 1; |
6c223761 | 789 | u8 target_lun_valid : 1; |
6c223761 KB |
790 | u8 device_gone : 1; |
791 | u8 new_device : 1; | |
792 | u8 keep_device : 1; | |
793 | u8 volume_offline : 1; | |
376fb880 | 794 | bool aio_enabled; /* only valid for physical disks */ |
7561a7e4 KB |
795 | bool in_reset; |
796 | bool device_offline; | |
6c223761 KB |
797 | u8 vendor[8]; /* bytes 8-15 of inquiry data */ |
798 | u8 model[16]; /* bytes 16-31 of inquiry data */ | |
799 | u64 sas_address; | |
800 | u8 raid_level; | |
801 | u16 queue_depth; /* max. queue_depth for this device */ | |
802 | u16 advertised_queue_depth; | |
803 | u32 aio_handle; | |
804 | u8 volume_status; | |
805 | u8 active_path_index; | |
806 | u8 path_map; | |
807 | u8 bay; | |
808 | u8 box[8]; | |
809 | u16 phys_connector[8]; | |
588a63fe KB |
810 | bool raid_bypass_configured; /* RAID bypass configured */ |
811 | bool raid_bypass_enabled; /* RAID bypass enabled */ | |
812 | int offload_to_mirror; /* Send next RAID bypass request */ | |
813 | /* to mirror drive. */ | |
814 | struct raid_map *raid_map; /* RAID bypass map */ | |
6c223761 KB |
815 | |
816 | struct pqi_sas_port *sas_port; | |
817 | struct scsi_device *sdev; | |
6c223761 KB |
818 | |
819 | struct list_head scsi_device_list_entry; | |
820 | struct list_head new_device_list_entry; | |
821 | struct list_head add_list_entry; | |
822 | struct list_head delete_list_entry; | |
7561a7e4 KB |
823 | |
824 | atomic_t scsi_cmds_outstanding; | |
6c223761 KB |
825 | }; |
826 | ||
827 | /* VPD inquiry pages */ | |
828 | #define SCSI_VPD_SUPPORTED_PAGES 0x0 /* standard page */ | |
829 | #define SCSI_VPD_DEVICE_ID 0x83 /* standard page */ | |
830 | #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1 /* vendor-specific page */ | |
588a63fe | 831 | #define CISS_VPD_LV_BYPASS_STATUS 0xc2 /* vendor-specific page */ |
6c223761 KB |
832 | #define CISS_VPD_LV_STATUS 0xc3 /* vendor-specific page */ |
833 | ||
834 | #define VPD_PAGE (1 << 8) | |
835 | ||
836 | #pragma pack(1) | |
837 | ||
838 | /* structure for CISS_VPD_LV_STATUS */ | |
839 | struct ciss_vpd_logical_volume_status { | |
840 | u8 peripheral_info; | |
841 | u8 page_code; | |
842 | u8 reserved; | |
843 | u8 page_length; | |
844 | u8 volume_status; | |
845 | u8 reserved2[3]; | |
846 | __be32 flags; | |
847 | }; | |
848 | ||
849 | #pragma pack() | |
850 | ||
851 | /* constants for volume_status field of ciss_vpd_logical_volume_status */ | |
852 | #define CISS_LV_OK 0 | |
853 | #define CISS_LV_FAILED 1 | |
854 | #define CISS_LV_NOT_CONFIGURED 2 | |
855 | #define CISS_LV_DEGRADED 3 | |
856 | #define CISS_LV_READY_FOR_RECOVERY 4 | |
857 | #define CISS_LV_UNDERGOING_RECOVERY 5 | |
858 | #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED 6 | |
859 | #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM 7 | |
860 | #define CISS_LV_HARDWARE_OVERHEATING 8 | |
861 | #define CISS_LV_HARDWARE_HAS_OVERHEATED 9 | |
862 | #define CISS_LV_UNDERGOING_EXPANSION 10 | |
863 | #define CISS_LV_NOT_AVAILABLE 11 | |
864 | #define CISS_LV_QUEUED_FOR_EXPANSION 12 | |
865 | #define CISS_LV_DISABLED_SCSI_ID_CONFLICT 13 | |
866 | #define CISS_LV_EJECTED 14 | |
867 | #define CISS_LV_UNDERGOING_ERASE 15 | |
868 | /* state 16 not used */ | |
869 | #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD 17 | |
870 | #define CISS_LV_UNDERGOING_RPI 18 | |
871 | #define CISS_LV_PENDING_RPI 19 | |
872 | #define CISS_LV_ENCRYPTED_NO_KEY 20 | |
873 | /* state 21 not used */ | |
874 | #define CISS_LV_UNDERGOING_ENCRYPTION 22 | |
875 | #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING 23 | |
876 | #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 24 | |
877 | #define CISS_LV_PENDING_ENCRYPTION 25 | |
878 | #define CISS_LV_PENDING_ENCRYPTION_REKEYING 26 | |
879 | #define CISS_LV_NOT_SUPPORTED 27 | |
880 | #define CISS_LV_STATUS_UNAVAILABLE 255 | |
881 | ||
882 | /* constants for flags field of ciss_vpd_logical_volume_status */ | |
883 | #define CISS_LV_FLAGS_NO_HOST_IO 0x1 /* volume not available for */ | |
884 | /* host I/O */ | |
885 | ||
886 | /* for SAS hosts and SAS expanders */ | |
887 | struct pqi_sas_node { | |
888 | struct device *parent_dev; | |
889 | struct list_head port_list_head; | |
890 | }; | |
891 | ||
892 | struct pqi_sas_port { | |
893 | struct list_head port_list_entry; | |
894 | u64 sas_address; | |
895 | struct sas_port *port; | |
896 | int next_phy_index; | |
897 | struct list_head phy_list_head; | |
898 | struct pqi_sas_node *parent_node; | |
899 | struct sas_rphy *rphy; | |
900 | }; | |
901 | ||
902 | struct pqi_sas_phy { | |
903 | struct list_head phy_list_entry; | |
904 | struct sas_phy *phy; | |
905 | struct pqi_sas_port *parent_port; | |
906 | bool added_to_port; | |
907 | }; | |
908 | ||
909 | struct pqi_io_request { | |
910 | atomic_t refcount; | |
911 | u16 index; | |
912 | void (*io_complete_callback)(struct pqi_io_request *io_request, | |
913 | void *context); | |
914 | void *context; | |
376fb880 | 915 | u8 raid_bypass : 1; |
6c223761 | 916 | int status; |
376fb880 | 917 | struct pqi_queue_group *queue_group; |
6c223761 KB |
918 | struct scsi_cmnd *scmd; |
919 | void *error_info; | |
920 | struct pqi_sg_descriptor *sg_chain_buffer; | |
921 | dma_addr_t sg_chain_buffer_dma_handle; | |
922 | void *iu; | |
923 | struct list_head request_list_entry; | |
924 | }; | |
925 | ||
6a50d6ad | 926 | #define PQI_NUM_SUPPORTED_EVENTS 6 |
6c223761 KB |
927 | |
928 | struct pqi_event { | |
929 | bool pending; | |
930 | u8 event_type; | |
931 | __le16 event_id; | |
932 | __le32 additional_event_id; | |
933 | }; | |
934 | ||
5e6429df KB |
935 | #define PQI_RESERVED_IO_SLOTS_LUN_RESET 1 |
936 | #define PQI_RESERVED_IO_SLOTS_EVENT_ACK PQI_NUM_SUPPORTED_EVENTS | |
937 | #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS 3 | |
938 | #define PQI_RESERVED_IO_SLOTS \ | |
939 | (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \ | |
940 | PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS) | |
941 | ||
6c223761 KB |
942 | struct pqi_ctrl_info { |
943 | unsigned int ctrl_id; | |
944 | struct pci_dev *pci_dev; | |
945 | char firmware_version[11]; | |
946 | void __iomem *iomem_base; | |
947 | struct pqi_ctrl_registers __iomem *registers; | |
948 | struct pqi_device_registers __iomem *pqi_registers; | |
949 | u32 max_sg_entries; | |
950 | u32 config_table_offset; | |
951 | u32 config_table_length; | |
952 | u16 max_inbound_queues; | |
953 | u16 max_elements_per_iq; | |
954 | u16 max_iq_element_length; | |
955 | u16 max_outbound_queues; | |
956 | u16 max_elements_per_oq; | |
957 | u16 max_oq_element_length; | |
958 | u32 max_transfer_size; | |
959 | u32 max_outstanding_requests; | |
960 | u32 max_io_slots; | |
961 | unsigned int scsi_ml_can_queue; | |
962 | unsigned short sg_tablesize; | |
963 | unsigned int max_sectors; | |
964 | u32 error_buffer_length; | |
965 | void *error_buffer; | |
966 | dma_addr_t error_buffer_dma_handle; | |
967 | size_t sg_chain_buffer_length; | |
968 | unsigned int num_queue_groups; | |
061ef06a | 969 | u16 max_hw_queue_index; |
6c223761 KB |
970 | u16 num_elements_per_iq; |
971 | u16 num_elements_per_oq; | |
972 | u16 max_inbound_iu_length_per_firmware; | |
973 | u16 max_inbound_iu_length; | |
974 | unsigned int max_sg_per_iu; | |
975 | void *admin_queue_memory_base; | |
976 | u32 admin_queue_memory_length; | |
977 | dma_addr_t admin_queue_memory_base_dma_handle; | |
978 | void *queue_memory_base; | |
979 | u32 queue_memory_length; | |
980 | dma_addr_t queue_memory_base_dma_handle; | |
981 | struct pqi_admin_queues admin_queues; | |
982 | struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS]; | |
983 | struct pqi_event_queue event_queue; | |
061ef06a | 984 | enum pqi_irq_mode irq_mode; |
6c223761 KB |
985 | int max_msix_vectors; |
986 | int num_msix_vectors_enabled; | |
987 | int num_msix_vectors_initialized; | |
6c223761 KB |
988 | int event_irq; |
989 | struct Scsi_Host *scsi_host; | |
990 | ||
991 | struct mutex scan_mutex; | |
7561a7e4 KB |
992 | struct mutex lun_reset_mutex; |
993 | bool controller_online; | |
994 | bool block_requests; | |
6c223761 KB |
995 | u8 inbound_spanning_supported : 1; |
996 | u8 outbound_spanning_supported : 1; | |
997 | u8 pqi_mode_enabled : 1; | |
6c223761 KB |
998 | |
999 | struct list_head scsi_device_list; | |
1000 | spinlock_t scsi_device_list_lock; | |
1001 | ||
1002 | struct delayed_work rescan_work; | |
1003 | struct delayed_work update_time_work; | |
1004 | ||
1005 | struct pqi_sas_node *sas_host; | |
1006 | u64 sas_address; | |
1007 | ||
1008 | struct pqi_io_request *io_request_pool; | |
1009 | u16 next_io_request_slot; | |
1010 | ||
6a50d6ad | 1011 | struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS]; |
6c223761 KB |
1012 | struct work_struct event_work; |
1013 | ||
1014 | atomic_t num_interrupts; | |
1015 | int previous_num_interrupts; | |
98f87667 KB |
1016 | u32 previous_heartbeat_count; |
1017 | __le32 __iomem *heartbeat_counter; | |
6c223761 | 1018 | struct timer_list heartbeat_timer; |
5f310425 | 1019 | struct work_struct ctrl_offline_work; |
6c223761 KB |
1020 | |
1021 | struct semaphore sync_request_sem; | |
7561a7e4 KB |
1022 | atomic_t num_busy_threads; |
1023 | atomic_t num_blocked_threads; | |
1024 | wait_queue_head_t block_requests_wait; | |
376fb880 KB |
1025 | |
1026 | struct list_head raid_bypass_retry_list; | |
1027 | spinlock_t raid_bypass_retry_list_lock; | |
1028 | struct work_struct raid_bypass_retry_work; | |
6c223761 KB |
1029 | }; |
1030 | ||
ff6abb73 | 1031 | enum pqi_ctrl_mode { |
162d7753 | 1032 | SIS_MODE = 0, |
ff6abb73 KB |
1033 | PQI_MODE |
1034 | }; | |
1035 | ||
6c223761 KB |
1036 | /* |
1037 | * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands | |
1038 | */ | |
1039 | #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH 27 | |
1040 | ||
6c223761 KB |
1041 | /* CISS commands */ |
1042 | #define CISS_READ 0xc0 | |
1043 | #define CISS_REPORT_LOG 0xc2 /* Report Logical LUNs */ | |
1044 | #define CISS_REPORT_PHYS 0xc3 /* Report Physical LUNs */ | |
1045 | #define CISS_GET_RAID_MAP 0xc8 | |
1046 | ||
1047 | /* constants for CISS_REPORT_LOG/CISS_REPORT_PHYS commands */ | |
1048 | #define CISS_REPORT_LOG_EXTENDED 0x1 | |
1049 | #define CISS_REPORT_PHYS_EXTENDED 0x2 | |
1050 | ||
1051 | /* BMIC commands */ | |
1052 | #define BMIC_IDENTIFY_CONTROLLER 0x11 | |
1053 | #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 | |
1054 | #define BMIC_READ 0x26 | |
1055 | #define BMIC_WRITE 0x27 | |
1056 | #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 | |
1057 | #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 | |
1058 | #define BMIC_WRITE_HOST_WELLNESS 0xa5 | |
1059 | #define BMIC_CACHE_FLUSH 0xc2 | |
1060 | ||
cbe0c7b1 | 1061 | #define SA_CACHE_FLUSH 0x1 |
6c223761 KB |
1062 | |
1063 | #define MASKED_DEVICE(lunid) ((lunid)[3] & 0xc0) | |
bd10cf0b | 1064 | #define CISS_GET_LEVEL_2_BUS(lunid) ((lunid)[7] & 0x3f) |
6c223761 KB |
1065 | #define CISS_GET_LEVEL_2_TARGET(lunid) ((lunid)[6]) |
1066 | #define CISS_GET_DRIVE_NUMBER(lunid) \ | |
bd10cf0b | 1067 | (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \ |
6c223761 KB |
1068 | CISS_GET_LEVEL_2_TARGET((lunid))) |
1069 | ||
1070 | #define NO_TIMEOUT ((unsigned long) -1) | |
1071 | ||
1072 | #pragma pack(1) | |
1073 | ||
1074 | struct bmic_identify_controller { | |
1075 | u8 configured_logical_drive_count; | |
1076 | __le32 configuration_signature; | |
1077 | u8 firmware_version[4]; | |
1078 | u8 reserved[145]; | |
1079 | __le16 extended_logical_unit_count; | |
1080 | u8 reserved1[34]; | |
1081 | __le16 firmware_build_number; | |
1082 | u8 reserved2[100]; | |
1083 | u8 controller_mode; | |
1084 | u8 reserved3[32]; | |
1085 | }; | |
1086 | ||
1087 | struct bmic_identify_physical_device { | |
1088 | u8 scsi_bus; /* SCSI Bus number on controller */ | |
1089 | u8 scsi_id; /* SCSI ID on this bus */ | |
1090 | __le16 block_size; /* sector size in bytes */ | |
1091 | __le32 total_blocks; /* number for sectors on drive */ | |
1092 | __le32 reserved_blocks; /* controller reserved (RIS) */ | |
1093 | u8 model[40]; /* Physical Drive Model */ | |
1094 | u8 serial_number[40]; /* Drive Serial Number */ | |
1095 | u8 firmware_revision[8]; /* drive firmware revision */ | |
1096 | u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ | |
1097 | u8 compaq_drive_stamp; /* 0 means drive not stamped */ | |
1098 | u8 last_failure_reason; | |
1099 | u8 flags; | |
1100 | u8 more_flags; | |
1101 | u8 scsi_lun; /* SCSI LUN for phys drive */ | |
1102 | u8 yet_more_flags; | |
1103 | u8 even_more_flags; | |
1104 | __le32 spi_speed_rules; | |
1105 | u8 phys_connector[2]; /* connector number on controller */ | |
1106 | u8 phys_box_on_bus; /* phys enclosure this drive resides */ | |
1107 | u8 phys_bay_in_box; /* phys drv bay this drive resides */ | |
1108 | __le32 rpm; /* drive rotational speed in RPM */ | |
1109 | u8 device_type; /* type of drive */ | |
1110 | u8 sata_version; /* only valid when device_type = */ | |
1111 | /* BMIC_DEVICE_TYPE_SATA */ | |
1112 | __le64 big_total_block_count; | |
1113 | __le64 ris_starting_lba; | |
1114 | __le32 ris_size; | |
1115 | u8 wwid[20]; | |
1116 | u8 controller_phy_map[32]; | |
1117 | __le16 phy_count; | |
1118 | u8 phy_connected_dev_type[256]; | |
1119 | u8 phy_to_drive_bay_num[256]; | |
1120 | __le16 phy_to_attached_dev_index[256]; | |
1121 | u8 box_index; | |
1122 | u8 reserved; | |
1123 | __le16 extra_physical_drive_flags; | |
1124 | u8 negotiated_link_rate[256]; | |
1125 | u8 phy_to_phy_map[256]; | |
1126 | u8 redundant_path_present_map; | |
1127 | u8 redundant_path_failure_map; | |
1128 | u8 active_path_number; | |
1129 | __le16 alternate_paths_phys_connector[8]; | |
1130 | u8 alternate_paths_phys_box_on_port[8]; | |
1131 | u8 multi_lun_device_lun_count; | |
1132 | u8 minimum_good_fw_revision[8]; | |
1133 | u8 unique_inquiry_bytes[20]; | |
1be42f46 KB |
1134 | u8 current_temperature_degrees; |
1135 | u8 temperature_threshold_degrees; | |
1136 | u8 max_temperature_degrees; | |
6c223761 KB |
1137 | u8 logical_blocks_per_phys_block_exp; |
1138 | __le16 current_queue_depth_limit; | |
1139 | u8 switch_name[10]; | |
1140 | __le16 switch_port; | |
1141 | u8 alternate_paths_switch_name[40]; | |
1142 | u8 alternate_paths_switch_port[8]; | |
1143 | __le16 power_on_hours; | |
1144 | __le16 percent_endurance_used; | |
1145 | u8 drive_authentication; | |
1146 | u8 smart_carrier_authentication; | |
1147 | u8 smart_carrier_app_fw_version; | |
1148 | u8 smart_carrier_bootloader_fw_version; | |
1be42f46 KB |
1149 | u8 sanitize_flags; |
1150 | u8 encryption_key_flags; | |
6c223761 KB |
1151 | u8 encryption_key_name[64]; |
1152 | __le32 misc_drive_flags; | |
1153 | __le16 dek_index; | |
1be42f46 KB |
1154 | __le16 hba_drive_encryption_flags; |
1155 | __le16 max_overwrite_time; | |
1156 | __le16 max_block_erase_time; | |
1157 | __le16 max_crypto_erase_time; | |
1158 | u8 connector_info[5]; | |
1159 | u8 connector_name[8][8]; | |
1160 | u8 page_83_identifier[16]; | |
1161 | u8 maximum_link_rate[256]; | |
1162 | u8 negotiated_physical_link_rate[256]; | |
1163 | u8 box_connector_name[8]; | |
1164 | u8 padding_to_multiple_of_512[9]; | |
6c223761 KB |
1165 | }; |
1166 | ||
1167 | #pragma pack() | |
1168 | ||
1169 | int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info); | |
1170 | void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info); | |
1171 | int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node, | |
1172 | struct pqi_scsi_dev *device); | |
1173 | void pqi_remove_sas_device(struct pqi_scsi_dev *device); | |
1174 | struct pqi_scsi_dev *pqi_find_device_by_sas_rphy( | |
1175 | struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy); | |
7561a7e4 | 1176 | void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd); |
6c223761 KB |
1177 | |
1178 | extern struct sas_function_template pqi_sas_transport_functions; | |
1179 | ||
6c223761 | 1180 | #endif /* _SMARTPQI_H */ |