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Commit | Line | Data |
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5a25ba16 JG |
1 | /* |
2 | * SuperTrak EX Series Storage Controller driver for Linux | |
3 | * | |
bd5cd9cd | 4 | * Copyright (C) 2005-2009 Promise Technology Inc. |
5a25ba16 JG |
5 | * |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * Written By: | |
12 | * Ed Lin <promise_linux@promise.com> | |
13 | * | |
5a25ba16 JG |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/delay.h> | |
5a25ba16 JG |
20 | #include <linux/time.h> |
21 | #include <linux/pci.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/spinlock.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/irq.h> | |
29 | #include <asm/byteorder.h> | |
30 | #include <scsi/scsi.h> | |
31 | #include <scsi/scsi_device.h> | |
32 | #include <scsi/scsi_cmnd.h> | |
33 | #include <scsi/scsi_host.h> | |
cf355883 | 34 | #include <scsi/scsi_tcq.h> |
c25da0af | 35 | #include <scsi/scsi_dbg.h> |
11002fbc | 36 | #include <scsi/scsi_eh.h> |
5a25ba16 JG |
37 | |
38 | #define DRV_NAME "stex" | |
05b4460b EL |
39 | #define ST_DRIVER_VERSION "4.6.0000.3" |
40 | #define ST_VER_MAJOR 4 | |
41 | #define ST_VER_MINOR 6 | |
42 | #define ST_OEM 0 | |
43 | #define ST_BUILD_VER 3 | |
5a25ba16 JG |
44 | |
45 | enum { | |
46 | /* MU register offset */ | |
47 | IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */ | |
48 | IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */ | |
49 | OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */ | |
50 | OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */ | |
51 | IDBL = 0x20, /* MU_INBOUND_DOORBELL */ | |
52 | IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */ | |
53 | IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */ | |
54 | ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */ | |
55 | OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */ | |
56 | OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */ | |
57 | ||
69cb4875 | 58 | YIOA_STATUS = 0x00, |
0f3f6ee6 EL |
59 | YH2I_INT = 0x20, |
60 | YINT_EN = 0x34, | |
61 | YI2H_INT = 0x9c, | |
62 | YI2H_INT_C = 0xa0, | |
63 | YH2I_REQ = 0xc0, | |
64 | YH2I_REQ_HI = 0xc4, | |
65 | ||
5a25ba16 | 66 | /* MU register value */ |
9eb46d2a EL |
67 | MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0), |
68 | MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1), | |
69 | MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2), | |
70 | MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3), | |
71 | MU_INBOUND_DOORBELL_RESET = (1 << 4), | |
72 | ||
73 | MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0), | |
74 | MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1), | |
75 | MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2), | |
76 | MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3), | |
77 | MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4), | |
78 | MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27), | |
5a25ba16 JG |
79 | |
80 | /* MU status code */ | |
81 | MU_STATE_STARTING = 1, | |
9eb46d2a EL |
82 | MU_STATE_STARTED = 2, |
83 | MU_STATE_RESETTING = 3, | |
84 | MU_STATE_FAILED = 4, | |
5a25ba16 | 85 | |
76fbf96f | 86 | MU_MAX_DELAY = 120, |
5a25ba16 | 87 | MU_HANDSHAKE_SIGNATURE = 0x55aaaa55, |
529e7a62 | 88 | MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000, |
76fbf96f | 89 | MU_HARD_RESET_WAIT = 30000, |
5a25ba16 JG |
90 | HMU_PARTNER_TYPE = 2, |
91 | ||
92 | /* firmware returned values */ | |
93 | SRB_STATUS_SUCCESS = 0x01, | |
94 | SRB_STATUS_ERROR = 0x04, | |
95 | SRB_STATUS_BUSY = 0x05, | |
96 | SRB_STATUS_INVALID_REQUEST = 0x06, | |
97 | SRB_STATUS_SELECTION_TIMEOUT = 0x0A, | |
98 | SRB_SEE_SENSE = 0x80, | |
99 | ||
100 | /* task attribute */ | |
101 | TASK_ATTRIBUTE_SIMPLE = 0x0, | |
102 | TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, | |
103 | TASK_ATTRIBUTE_ORDERED = 0x2, | |
104 | TASK_ATTRIBUTE_ACA = 0x4, | |
105 | ||
0f3f6ee6 EL |
106 | SS_STS_NORMAL = 0x80000000, |
107 | SS_STS_DONE = 0x40000000, | |
108 | SS_STS_HANDSHAKE = 0x20000000, | |
109 | ||
110 | SS_HEAD_HANDSHAKE = 0x80, | |
111 | ||
69cb4875 EL |
112 | SS_H2I_INT_RESET = 0x100, |
113 | ||
9eb46d2a EL |
114 | SS_I2H_REQUEST_RESET = 0x2000, |
115 | ||
69cb4875 EL |
116 | SS_MU_OPERATIONAL = 0x80000000, |
117 | ||
7cfe99a5 | 118 | STEX_CDB_LENGTH = 16, |
5a25ba16 | 119 | STATUS_VAR_LEN = 128, |
5a25ba16 JG |
120 | |
121 | /* sg flags */ | |
122 | SG_CF_EOT = 0x80, /* end of table */ | |
123 | SG_CF_64B = 0x40, /* 64 bit item */ | |
124 | SG_CF_HOST = 0x20, /* sg in host memory */ | |
7cfe99a5 ELP |
125 | MSG_DATA_DIR_ND = 0, |
126 | MSG_DATA_DIR_IN = 1, | |
127 | MSG_DATA_DIR_OUT = 2, | |
5a25ba16 | 128 | |
5a25ba16 JG |
129 | st_shasta = 0, |
130 | st_vsc = 1, | |
591a3a5f EL |
131 | st_yosemite = 2, |
132 | st_seq = 3, | |
0f3f6ee6 | 133 | st_yel = 4, |
5a25ba16 JG |
134 | |
135 | PASSTHRU_REQ_TYPE = 0x00000001, | |
136 | PASSTHRU_REQ_NO_WAKEUP = 0x00000100, | |
7cfe99a5 | 137 | ST_INTERNAL_TIMEOUT = 180, |
5a25ba16 | 138 | |
fb4f66be EL |
139 | ST_TO_CMD = 0, |
140 | ST_FROM_CMD = 1, | |
141 | ||
5a25ba16 | 142 | /* vendor specific commands of Promise */ |
fb4f66be EL |
143 | MGT_CMD = 0xd8, |
144 | SINBAND_MGT_CMD = 0xd9, | |
5a25ba16 JG |
145 | ARRAY_CMD = 0xe0, |
146 | CONTROLLER_CMD = 0xe1, | |
147 | DEBUGGING_CMD = 0xe2, | |
148 | PASSTHRU_CMD = 0xe3, | |
149 | ||
150 | PASSTHRU_GET_ADAPTER = 0x05, | |
151 | PASSTHRU_GET_DRVVER = 0x10, | |
fb4f66be EL |
152 | |
153 | CTLR_CONFIG_CMD = 0x03, | |
154 | CTLR_SHUTDOWN = 0x0d, | |
155 | ||
5a25ba16 JG |
156 | CTLR_POWER_STATE_CHANGE = 0x0e, |
157 | CTLR_POWER_SAVING = 0x01, | |
158 | ||
159 | PASSTHRU_SIGNATURE = 0x4e415041, | |
fb4f66be | 160 | MGT_CMD_SIGNATURE = 0xba, |
5a25ba16 JG |
161 | |
162 | INQUIRY_EVPD = 0x01, | |
94e9108b EL |
163 | |
164 | ST_ADDITIONAL_MEM = 0x200000, | |
cbacfb5f | 165 | ST_ADDITIONAL_MEM_MIN = 0x80000, |
5a25ba16 JG |
166 | }; |
167 | ||
168 | struct st_sgitem { | |
169 | u8 ctrl; /* SG_CF_xxx */ | |
170 | u8 reserved[3]; | |
171 | __le32 count; | |
f1498161 | 172 | __le64 addr; |
5a25ba16 JG |
173 | }; |
174 | ||
0f3f6ee6 EL |
175 | struct st_ss_sgitem { |
176 | __le32 addr; | |
177 | __le32 addr_hi; | |
178 | __le32 count; | |
179 | }; | |
180 | ||
5a25ba16 JG |
181 | struct st_sgtable { |
182 | __le16 sg_count; | |
183 | __le16 max_sg_count; | |
184 | __le32 sz_in_byte; | |
5a25ba16 JG |
185 | }; |
186 | ||
0f3f6ee6 EL |
187 | struct st_msg_header { |
188 | __le64 handle; | |
189 | u8 flag; | |
190 | u8 channel; | |
191 | __le16 timeout; | |
192 | u32 reserved; | |
193 | }; | |
194 | ||
5a25ba16 | 195 | struct handshake_frame { |
f1498161 | 196 | __le64 rb_phy; /* request payload queue physical address */ |
5a25ba16 JG |
197 | __le16 req_sz; /* size of each request payload */ |
198 | __le16 req_cnt; /* count of reqs the buffer can hold */ | |
199 | __le16 status_sz; /* size of each status payload */ | |
200 | __le16 status_cnt; /* count of status the buffer can hold */ | |
f1498161 | 201 | __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */ |
5a25ba16 JG |
202 | u8 partner_type; /* who sends this frame */ |
203 | u8 reserved0[7]; | |
204 | __le32 partner_ver_major; | |
205 | __le32 partner_ver_minor; | |
206 | __le32 partner_ver_oem; | |
207 | __le32 partner_ver_build; | |
94e9108b EL |
208 | __le32 extra_offset; /* NEW */ |
209 | __le32 extra_size; /* NEW */ | |
0f3f6ee6 EL |
210 | __le32 scratch_size; |
211 | u32 reserved1; | |
5a25ba16 JG |
212 | }; |
213 | ||
214 | struct req_msg { | |
215 | __le16 tag; | |
216 | u8 lun; | |
217 | u8 target; | |
218 | u8 task_attr; | |
219 | u8 task_manage; | |
7cfe99a5 | 220 | u8 data_dir; |
f903d7b7 | 221 | u8 payload_sz; /* payload size in 4-byte, not used */ |
5a25ba16 | 222 | u8 cdb[STEX_CDB_LENGTH]; |
591a3a5f | 223 | u32 variable[0]; |
5a25ba16 JG |
224 | }; |
225 | ||
226 | struct status_msg { | |
227 | __le16 tag; | |
228 | u8 lun; | |
229 | u8 target; | |
230 | u8 srb_status; | |
231 | u8 scsi_status; | |
232 | u8 reserved; | |
233 | u8 payload_sz; /* payload size in 4-byte */ | |
234 | u8 variable[STATUS_VAR_LEN]; | |
235 | }; | |
236 | ||
237 | struct ver_info { | |
238 | u32 major; | |
239 | u32 minor; | |
240 | u32 oem; | |
241 | u32 build; | |
242 | u32 reserved[2]; | |
243 | }; | |
244 | ||
245 | struct st_frame { | |
246 | u32 base[6]; | |
247 | u32 rom_addr; | |
248 | ||
249 | struct ver_info drv_ver; | |
250 | struct ver_info bios_ver; | |
251 | ||
252 | u32 bus; | |
253 | u32 slot; | |
254 | u32 irq_level; | |
255 | u32 irq_vec; | |
256 | u32 id; | |
257 | u32 subid; | |
258 | ||
259 | u32 dimm_size; | |
260 | u8 dimm_type; | |
261 | u8 reserved[3]; | |
262 | ||
263 | u32 channel; | |
264 | u32 reserved1; | |
265 | }; | |
266 | ||
267 | struct st_drvver { | |
268 | u32 major; | |
269 | u32 minor; | |
270 | u32 oem; | |
271 | u32 build; | |
272 | u32 signature[2]; | |
273 | u8 console_id; | |
274 | u8 host_no; | |
275 | u8 reserved0[2]; | |
276 | u32 reserved[3]; | |
277 | }; | |
278 | ||
5a25ba16 JG |
279 | struct st_ccb { |
280 | struct req_msg *req; | |
281 | struct scsi_cmnd *cmd; | |
282 | ||
283 | void *sense_buffer; | |
284 | unsigned int sense_bufflen; | |
285 | int sg_count; | |
286 | ||
287 | u32 req_type; | |
288 | u8 srb_status; | |
289 | u8 scsi_status; | |
f1498161 | 290 | u8 reserved[2]; |
5a25ba16 JG |
291 | }; |
292 | ||
293 | struct st_hba { | |
294 | void __iomem *mmio_base; /* iomapped PCI memory space */ | |
295 | void *dma_mem; | |
296 | dma_addr_t dma_handle; | |
94e9108b | 297 | size_t dma_size; |
5a25ba16 JG |
298 | |
299 | struct Scsi_Host *host; | |
300 | struct pci_dev *pdev; | |
301 | ||
0f3f6ee6 EL |
302 | struct req_msg * (*alloc_rq) (struct st_hba *); |
303 | int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); | |
304 | void (*send) (struct st_hba *, struct req_msg *, u16); | |
305 | ||
5a25ba16 JG |
306 | u32 req_head; |
307 | u32 req_tail; | |
308 | u32 status_head; | |
309 | u32 status_tail; | |
310 | ||
311 | struct status_msg *status_buffer; | |
312 | void *copy_buffer; /* temp buffer for driver-handled commands */ | |
591a3a5f | 313 | struct st_ccb *ccb; |
5a25ba16 | 314 | struct st_ccb *wait_ccb; |
0f3f6ee6 | 315 | __le32 *scratch; |
5a25ba16 | 316 | |
9eb46d2a EL |
317 | char work_q_name[20]; |
318 | struct workqueue_struct *work_q; | |
319 | struct work_struct reset_work; | |
320 | wait_queue_head_t reset_waitq; | |
5a25ba16 | 321 | unsigned int mu_status; |
5a25ba16 | 322 | unsigned int cardtype; |
99946f81 EL |
323 | int msi_enabled; |
324 | int out_req_cnt; | |
591a3a5f EL |
325 | u32 extra_offset; |
326 | u16 rq_count; | |
327 | u16 rq_size; | |
328 | u16 sts_count; | |
329 | }; | |
330 | ||
331 | struct st_card_info { | |
0f3f6ee6 EL |
332 | struct req_msg * (*alloc_rq) (struct st_hba *); |
333 | int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *); | |
334 | void (*send) (struct st_hba *, struct req_msg *, u16); | |
591a3a5f EL |
335 | unsigned int max_id; |
336 | unsigned int max_lun; | |
337 | unsigned int max_channel; | |
338 | u16 rq_count; | |
339 | u16 rq_size; | |
340 | u16 sts_count; | |
5a25ba16 JG |
341 | }; |
342 | ||
99946f81 EL |
343 | static int msi; |
344 | module_param(msi, int, 0); | |
345 | MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)"); | |
346 | ||
5a25ba16 JG |
347 | static const char console_inq_page[] = |
348 | { | |
349 | 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30, | |
350 | 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */ | |
351 | 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */ | |
352 | 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */ | |
353 | 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */ | |
354 | 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */ | |
355 | 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */ | |
356 | 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20 | |
357 | }; | |
358 | ||
359 | MODULE_AUTHOR("Ed Lin"); | |
360 | MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers"); | |
361 | MODULE_LICENSE("GPL"); | |
362 | MODULE_VERSION(ST_DRIVER_VERSION); | |
363 | ||
f1498161 | 364 | static void stex_gettime(__le64 *time) |
5a25ba16 JG |
365 | { |
366 | struct timeval tv; | |
5a25ba16 | 367 | |
7cfe99a5 | 368 | do_gettimeofday(&tv); |
f1498161 | 369 | *time = cpu_to_le64(tv.tv_sec); |
5a25ba16 JG |
370 | } |
371 | ||
5a25ba16 JG |
372 | static struct status_msg *stex_get_status(struct st_hba *hba) |
373 | { | |
f1498161 | 374 | struct status_msg *status = hba->status_buffer + hba->status_tail; |
5a25ba16 JG |
375 | |
376 | ++hba->status_tail; | |
591a3a5f | 377 | hba->status_tail %= hba->sts_count+1; |
5a25ba16 JG |
378 | |
379 | return status; | |
380 | } | |
381 | ||
5a25ba16 JG |
382 | static void stex_invalid_field(struct scsi_cmnd *cmd, |
383 | void (*done)(struct scsi_cmnd *)) | |
384 | { | |
11002fbc FT |
385 | cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION; |
386 | ||
7cfe99a5 | 387 | /* "Invalid field in cdb" */ |
11002fbc FT |
388 | scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24, |
389 | 0x0); | |
5a25ba16 JG |
390 | done(cmd); |
391 | } | |
392 | ||
393 | static struct req_msg *stex_alloc_req(struct st_hba *hba) | |
394 | { | |
591a3a5f | 395 | struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size; |
5a25ba16 JG |
396 | |
397 | ++hba->req_head; | |
591a3a5f | 398 | hba->req_head %= hba->rq_count+1; |
5a25ba16 JG |
399 | |
400 | return req; | |
401 | } | |
402 | ||
0f3f6ee6 EL |
403 | static struct req_msg *stex_ss_alloc_req(struct st_hba *hba) |
404 | { | |
405 | return (struct req_msg *)(hba->dma_mem + | |
406 | hba->req_head * hba->rq_size + sizeof(struct st_msg_header)); | |
407 | } | |
408 | ||
5a25ba16 JG |
409 | static int stex_map_sg(struct st_hba *hba, |
410 | struct req_msg *req, struct st_ccb *ccb) | |
411 | { | |
5a25ba16 | 412 | struct scsi_cmnd *cmd; |
d5587d5d | 413 | struct scatterlist *sg; |
5a25ba16 | 414 | struct st_sgtable *dst; |
f1498161 | 415 | struct st_sgitem *table; |
d5587d5d | 416 | int i, nseg; |
5a25ba16 JG |
417 | |
418 | cmd = ccb->cmd; | |
d5587d5d | 419 | nseg = scsi_dma_map(cmd); |
f1498161 | 420 | BUG_ON(nseg < 0); |
d5587d5d | 421 | if (nseg) { |
f1498161 EL |
422 | dst = (struct st_sgtable *)req->variable; |
423 | ||
d5587d5d FT |
424 | ccb->sg_count = nseg; |
425 | dst->sg_count = cpu_to_le16((u16)nseg); | |
f1498161 EL |
426 | dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); |
427 | dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); | |
5a25ba16 | 428 | |
f1498161 | 429 | table = (struct st_sgitem *)(dst + 1); |
d5587d5d | 430 | scsi_for_each_sg(cmd, sg, nseg, i) { |
f1498161 EL |
431 | table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); |
432 | table[i].addr = cpu_to_le64(sg_dma_address(sg)); | |
433 | table[i].ctrl = SG_CF_64B | SG_CF_HOST; | |
5a25ba16 | 434 | } |
f1498161 | 435 | table[--i].ctrl |= SG_CF_EOT; |
5a25ba16 JG |
436 | } |
437 | ||
f1498161 | 438 | return nseg; |
5a25ba16 JG |
439 | } |
440 | ||
0f3f6ee6 EL |
441 | static int stex_ss_map_sg(struct st_hba *hba, |
442 | struct req_msg *req, struct st_ccb *ccb) | |
443 | { | |
444 | struct scsi_cmnd *cmd; | |
445 | struct scatterlist *sg; | |
446 | struct st_sgtable *dst; | |
447 | struct st_ss_sgitem *table; | |
448 | int i, nseg; | |
449 | ||
450 | cmd = ccb->cmd; | |
451 | nseg = scsi_dma_map(cmd); | |
452 | BUG_ON(nseg < 0); | |
453 | if (nseg) { | |
454 | dst = (struct st_sgtable *)req->variable; | |
455 | ||
456 | ccb->sg_count = nseg; | |
457 | dst->sg_count = cpu_to_le16((u16)nseg); | |
458 | dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize); | |
459 | dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd)); | |
460 | ||
461 | table = (struct st_ss_sgitem *)(dst + 1); | |
462 | scsi_for_each_sg(cmd, sg, nseg, i) { | |
463 | table[i].count = cpu_to_le32((u32)sg_dma_len(sg)); | |
464 | table[i].addr = | |
465 | cpu_to_le32(sg_dma_address(sg) & 0xffffffff); | |
466 | table[i].addr_hi = | |
467 | cpu_to_le32((sg_dma_address(sg) >> 16) >> 16); | |
468 | } | |
469 | } | |
470 | ||
471 | return nseg; | |
472 | } | |
473 | ||
5a25ba16 JG |
474 | static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb) |
475 | { | |
476 | struct st_frame *p; | |
477 | size_t count = sizeof(struct st_frame); | |
478 | ||
479 | p = hba->copy_buffer; | |
f1498161 | 480 | scsi_sg_copy_to_buffer(ccb->cmd, p, count); |
5a25ba16 JG |
481 | memset(p->base, 0, sizeof(u32)*6); |
482 | *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0); | |
483 | p->rom_addr = 0; | |
484 | ||
485 | p->drv_ver.major = ST_VER_MAJOR; | |
486 | p->drv_ver.minor = ST_VER_MINOR; | |
487 | p->drv_ver.oem = ST_OEM; | |
488 | p->drv_ver.build = ST_BUILD_VER; | |
489 | ||
490 | p->bus = hba->pdev->bus->number; | |
491 | p->slot = hba->pdev->devfn; | |
492 | p->irq_level = 0; | |
493 | p->irq_vec = hba->pdev->irq; | |
494 | p->id = hba->pdev->vendor << 16 | hba->pdev->device; | |
495 | p->subid = | |
496 | hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device; | |
497 | ||
f1498161 | 498 | scsi_sg_copy_from_buffer(ccb->cmd, p, count); |
5a25ba16 JG |
499 | } |
500 | ||
501 | static void | |
502 | stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) | |
503 | { | |
504 | req->tag = cpu_to_le16(tag); | |
5a25ba16 JG |
505 | |
506 | hba->ccb[tag].req = req; | |
507 | hba->out_req_cnt++; | |
508 | ||
509 | writel(hba->req_head, hba->mmio_base + IMR0); | |
510 | writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL); | |
511 | readl(hba->mmio_base + IDBL); /* flush */ | |
512 | } | |
513 | ||
0f3f6ee6 EL |
514 | static void |
515 | stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag) | |
516 | { | |
517 | struct scsi_cmnd *cmd; | |
518 | struct st_msg_header *msg_h; | |
519 | dma_addr_t addr; | |
520 | ||
521 | req->tag = cpu_to_le16(tag); | |
522 | ||
523 | hba->ccb[tag].req = req; | |
524 | hba->out_req_cnt++; | |
525 | ||
526 | cmd = hba->ccb[tag].cmd; | |
527 | msg_h = (struct st_msg_header *)req - 1; | |
528 | if (likely(cmd)) { | |
529 | msg_h->channel = (u8)cmd->device->channel; | |
530 | msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ); | |
531 | } | |
532 | addr = hba->dma_handle + hba->req_head * hba->rq_size; | |
533 | addr += (hba->ccb[tag].sg_count+4)/11; | |
534 | msg_h->handle = cpu_to_le64(addr); | |
535 | ||
536 | ++hba->req_head; | |
537 | hba->req_head %= hba->rq_count+1; | |
538 | ||
539 | writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI); | |
540 | readl(hba->mmio_base + YH2I_REQ_HI); /* flush */ | |
541 | writel(addr, hba->mmio_base + YH2I_REQ); | |
542 | readl(hba->mmio_base + YH2I_REQ); /* flush */ | |
543 | } | |
544 | ||
cf355883 EL |
545 | static int |
546 | stex_slave_alloc(struct scsi_device *sdev) | |
547 | { | |
548 | /* Cheat: usually extracted from Inquiry data */ | |
549 | sdev->tagged_supported = 1; | |
550 | ||
f1498161 | 551 | scsi_activate_tcq(sdev, sdev->host->can_queue); |
cf355883 EL |
552 | |
553 | return 0; | |
554 | } | |
555 | ||
5a25ba16 JG |
556 | static int |
557 | stex_slave_config(struct scsi_device *sdev) | |
558 | { | |
559 | sdev->use_10_for_rw = 1; | |
560 | sdev->use_10_for_ms = 1; | |
dc5c49bf | 561 | blk_queue_rq_timeout(sdev->request_queue, 60 * HZ); |
cf355883 EL |
562 | sdev->tagged_supported = 1; |
563 | ||
5a25ba16 JG |
564 | return 0; |
565 | } | |
566 | ||
567 | static void | |
568 | stex_slave_destroy(struct scsi_device *sdev) | |
569 | { | |
cf355883 | 570 | scsi_deactivate_tcq(sdev, 1); |
5a25ba16 JG |
571 | } |
572 | ||
573 | static int | |
574 | stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *)) | |
575 | { | |
576 | struct st_hba *hba; | |
577 | struct Scsi_Host *host; | |
f1498161 | 578 | unsigned int id, lun; |
5a25ba16 JG |
579 | struct req_msg *req; |
580 | u16 tag; | |
7cfe99a5 | 581 | |
5a25ba16 JG |
582 | host = cmd->device->host; |
583 | id = cmd->device->id; | |
e0b2e597 | 584 | lun = cmd->device->lun; |
5a25ba16 JG |
585 | hba = (struct st_hba *) &host->hostdata[0]; |
586 | ||
9eb46d2a EL |
587 | if (unlikely(hba->mu_status == MU_STATE_RESETTING)) |
588 | return SCSI_MLQUEUE_HOST_BUSY; | |
589 | ||
5a25ba16 JG |
590 | switch (cmd->cmnd[0]) { |
591 | case MODE_SENSE_10: | |
592 | { | |
593 | static char ms10_caching_page[12] = | |
594 | { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 }; | |
595 | unsigned char page; | |
7cfe99a5 | 596 | |
5a25ba16 JG |
597 | page = cmd->cmnd[2] & 0x3f; |
598 | if (page == 0x8 || page == 0x3f) { | |
31fe47d4 FT |
599 | scsi_sg_copy_from_buffer(cmd, ms10_caching_page, |
600 | sizeof(ms10_caching_page)); | |
5a25ba16 JG |
601 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; |
602 | done(cmd); | |
603 | } else | |
604 | stex_invalid_field(cmd, done); | |
605 | return 0; | |
606 | } | |
e0b2e597 EL |
607 | case REPORT_LUNS: |
608 | /* | |
609 | * The shasta firmware does not report actual luns in the | |
610 | * target, so fail the command to force sequential lun scan. | |
611 | * Also, the console device does not support this command. | |
612 | */ | |
613 | if (hba->cardtype == st_shasta || id == host->max_id - 1) { | |
614 | stex_invalid_field(cmd, done); | |
615 | return 0; | |
616 | } | |
617 | break; | |
d116a7bc EL |
618 | case TEST_UNIT_READY: |
619 | if (id == host->max_id - 1) { | |
620 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; | |
621 | done(cmd); | |
622 | return 0; | |
623 | } | |
624 | break; | |
5a25ba16 | 625 | case INQUIRY: |
e0b2e597 | 626 | if (id != host->max_id - 1) |
5a25ba16 | 627 | break; |
0f3f6ee6 EL |
628 | if (!lun && !cmd->device->channel && |
629 | (cmd->cmnd[1] & INQUIRY_EVPD) == 0) { | |
31fe47d4 FT |
630 | scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page, |
631 | sizeof(console_inq_page)); | |
5a25ba16 JG |
632 | cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8; |
633 | done(cmd); | |
634 | } else | |
635 | stex_invalid_field(cmd, done); | |
636 | return 0; | |
637 | case PASSTHRU_CMD: | |
638 | if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) { | |
639 | struct st_drvver ver; | |
26106e3c | 640 | size_t cp_len = sizeof(ver); |
7cfe99a5 | 641 | |
5a25ba16 JG |
642 | ver.major = ST_VER_MAJOR; |
643 | ver.minor = ST_VER_MINOR; | |
644 | ver.oem = ST_OEM; | |
645 | ver.build = ST_BUILD_VER; | |
646 | ver.signature[0] = PASSTHRU_SIGNATURE; | |
e0b2e597 | 647 | ver.console_id = host->max_id - 1; |
5a25ba16 | 648 | ver.host_no = hba->host->host_no; |
31fe47d4 | 649 | cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len); |
26106e3c | 650 | cmd->result = sizeof(ver) == cp_len ? |
5a25ba16 JG |
651 | DID_OK << 16 | COMMAND_COMPLETE << 8 : |
652 | DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
653 | done(cmd); | |
654 | return 0; | |
655 | } | |
656 | default: | |
657 | break; | |
658 | } | |
659 | ||
660 | cmd->scsi_done = done; | |
661 | ||
cf355883 EL |
662 | tag = cmd->request->tag; |
663 | ||
664 | if (unlikely(tag >= host->can_queue)) | |
5a25ba16 JG |
665 | return SCSI_MLQUEUE_HOST_BUSY; |
666 | ||
0f3f6ee6 | 667 | req = hba->alloc_rq(hba); |
fb4f66be | 668 | |
e0b2e597 EL |
669 | req->lun = lun; |
670 | req->target = id; | |
5a25ba16 JG |
671 | |
672 | /* cdb */ | |
673 | memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH); | |
674 | ||
7cfe99a5 ELP |
675 | if (cmd->sc_data_direction == DMA_FROM_DEVICE) |
676 | req->data_dir = MSG_DATA_DIR_IN; | |
677 | else if (cmd->sc_data_direction == DMA_TO_DEVICE) | |
678 | req->data_dir = MSG_DATA_DIR_OUT; | |
679 | else | |
680 | req->data_dir = MSG_DATA_DIR_ND; | |
681 | ||
5a25ba16 JG |
682 | hba->ccb[tag].cmd = cmd; |
683 | hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE; | |
684 | hba->ccb[tag].sense_buffer = cmd->sense_buffer; | |
5a25ba16 | 685 | |
0f3f6ee6 EL |
686 | if (!hba->map_sg(hba, req, &hba->ccb[tag])) { |
687 | hba->ccb[tag].sg_count = 0; | |
688 | memset(&req->variable[0], 0, 8); | |
689 | } | |
5a25ba16 | 690 | |
0f3f6ee6 | 691 | hba->send(hba, req, tag); |
5a25ba16 JG |
692 | return 0; |
693 | } | |
694 | ||
5a25ba16 JG |
695 | static void stex_scsi_done(struct st_ccb *ccb) |
696 | { | |
697 | struct scsi_cmnd *cmd = ccb->cmd; | |
698 | int result; | |
699 | ||
f1498161 | 700 | if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) { |
5a25ba16 JG |
701 | result = ccb->scsi_status; |
702 | switch (ccb->scsi_status) { | |
703 | case SAM_STAT_GOOD: | |
704 | result |= DID_OK << 16 | COMMAND_COMPLETE << 8; | |
705 | break; | |
706 | case SAM_STAT_CHECK_CONDITION: | |
707 | result |= DRIVER_SENSE << 24; | |
708 | break; | |
709 | case SAM_STAT_BUSY: | |
710 | result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; | |
711 | break; | |
712 | default: | |
713 | result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
714 | break; | |
715 | } | |
716 | } | |
717 | else if (ccb->srb_status & SRB_SEE_SENSE) | |
718 | result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION; | |
719 | else switch (ccb->srb_status) { | |
720 | case SRB_STATUS_SELECTION_TIMEOUT: | |
721 | result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8; | |
722 | break; | |
723 | case SRB_STATUS_BUSY: | |
724 | result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8; | |
725 | break; | |
726 | case SRB_STATUS_INVALID_REQUEST: | |
727 | case SRB_STATUS_ERROR: | |
728 | default: | |
729 | result = DID_ERROR << 16 | COMMAND_COMPLETE << 8; | |
730 | break; | |
731 | } | |
732 | ||
733 | cmd->result = result; | |
734 | cmd->scsi_done(cmd); | |
735 | } | |
736 | ||
737 | static void stex_copy_data(struct st_ccb *ccb, | |
738 | struct status_msg *resp, unsigned int variable) | |
739 | { | |
5a25ba16 JG |
740 | if (resp->scsi_status != SAM_STAT_GOOD) { |
741 | if (ccb->sense_buffer != NULL) | |
742 | memcpy(ccb->sense_buffer, resp->variable, | |
743 | min(variable, ccb->sense_bufflen)); | |
744 | return; | |
745 | } | |
746 | ||
747 | if (ccb->cmd == NULL) | |
748 | return; | |
f1498161 | 749 | scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable); |
fb4f66be EL |
750 | } |
751 | ||
f1498161 | 752 | static void stex_check_cmd(struct st_hba *hba, |
fb4f66be EL |
753 | struct st_ccb *ccb, struct status_msg *resp) |
754 | { | |
fb4f66be | 755 | if (ccb->cmd->cmnd[0] == MGT_CMD && |
f1498161 | 756 | resp->scsi_status != SAM_STAT_CHECK_CONDITION) |
968a5763 EL |
757 | scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) - |
758 | le32_to_cpu(*(__le32 *)&resp->variable[0])); | |
5a25ba16 JG |
759 | } |
760 | ||
761 | static void stex_mu_intr(struct st_hba *hba, u32 doorbell) | |
762 | { | |
763 | void __iomem *base = hba->mmio_base; | |
764 | struct status_msg *resp; | |
765 | struct st_ccb *ccb; | |
766 | unsigned int size; | |
767 | u16 tag; | |
768 | ||
f1498161 | 769 | if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))) |
5a25ba16 JG |
770 | return; |
771 | ||
772 | /* status payloads */ | |
773 | hba->status_head = readl(base + OMR1); | |
591a3a5f | 774 | if (unlikely(hba->status_head > hba->sts_count)) { |
5a25ba16 JG |
775 | printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n", |
776 | pci_name(hba->pdev)); | |
777 | return; | |
778 | } | |
779 | ||
fb4f66be EL |
780 | /* |
781 | * it's not a valid status payload if: | |
782 | * 1. there are no pending requests(e.g. during init stage) | |
783 | * 2. there are some pending requests, but the controller is in | |
784 | * reset status, and its type is not st_yosemite | |
785 | * firmware of st_yosemite in reset status will return pending requests | |
786 | * to driver, so we allow it to pass | |
787 | */ | |
788 | if (unlikely(hba->out_req_cnt <= 0 || | |
789 | (hba->mu_status == MU_STATE_RESETTING && | |
790 | hba->cardtype != st_yosemite))) { | |
5a25ba16 JG |
791 | hba->status_tail = hba->status_head; |
792 | goto update_status; | |
793 | } | |
794 | ||
795 | while (hba->status_tail != hba->status_head) { | |
796 | resp = stex_get_status(hba); | |
797 | tag = le16_to_cpu(resp->tag); | |
cf355883 | 798 | if (unlikely(tag >= hba->host->can_queue)) { |
5a25ba16 JG |
799 | printk(KERN_WARNING DRV_NAME |
800 | "(%s): invalid tag\n", pci_name(hba->pdev)); | |
801 | continue; | |
802 | } | |
5a25ba16 | 803 | |
f1498161 | 804 | hba->out_req_cnt--; |
5a25ba16 | 805 | ccb = &hba->ccb[tag]; |
f1498161 | 806 | if (unlikely(hba->wait_ccb == ccb)) |
5a25ba16 JG |
807 | hba->wait_ccb = NULL; |
808 | if (unlikely(ccb->req == NULL)) { | |
809 | printk(KERN_WARNING DRV_NAME | |
810 | "(%s): lagging req\n", pci_name(hba->pdev)); | |
5a25ba16 JG |
811 | continue; |
812 | } | |
813 | ||
814 | size = resp->payload_sz * sizeof(u32); /* payload size */ | |
815 | if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || | |
816 | size > sizeof(*resp))) { | |
817 | printk(KERN_WARNING DRV_NAME "(%s): bad status size\n", | |
818 | pci_name(hba->pdev)); | |
819 | } else { | |
820 | size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */ | |
821 | if (size) | |
822 | stex_copy_data(ccb, resp, size); | |
823 | } | |
824 | ||
dd48ebf7 | 825 | ccb->req = NULL; |
5a25ba16 JG |
826 | ccb->srb_status = resp->srb_status; |
827 | ccb->scsi_status = resp->scsi_status; | |
828 | ||
cf355883 | 829 | if (likely(ccb->cmd != NULL)) { |
fb4f66be | 830 | if (hba->cardtype == st_yosemite) |
f1498161 | 831 | stex_check_cmd(hba, ccb, resp); |
fb4f66be | 832 | |
cf355883 EL |
833 | if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD && |
834 | ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER)) | |
835 | stex_controller_info(hba, ccb); | |
fb4f66be | 836 | |
d5587d5d | 837 | scsi_dma_unmap(ccb->cmd); |
cf355883 | 838 | stex_scsi_done(ccb); |
f1498161 | 839 | } else |
5a25ba16 | 840 | ccb->req_type = 0; |
5a25ba16 JG |
841 | } |
842 | ||
843 | update_status: | |
844 | writel(hba->status_head, base + IMR1); | |
845 | readl(base + IMR1); /* flush */ | |
846 | } | |
847 | ||
7d12e780 | 848 | static irqreturn_t stex_intr(int irq, void *__hba) |
5a25ba16 JG |
849 | { |
850 | struct st_hba *hba = __hba; | |
851 | void __iomem *base = hba->mmio_base; | |
852 | u32 data; | |
853 | unsigned long flags; | |
5a25ba16 JG |
854 | |
855 | spin_lock_irqsave(hba->host->host_lock, flags); | |
856 | ||
857 | data = readl(base + ODBL); | |
858 | ||
859 | if (data && data != 0xffffffff) { | |
860 | /* clear the interrupt */ | |
861 | writel(data, base + ODBL); | |
862 | readl(base + ODBL); /* flush */ | |
863 | stex_mu_intr(hba, data); | |
9eb46d2a EL |
864 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
865 | if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET && | |
866 | hba->cardtype == st_shasta)) | |
867 | queue_work(hba->work_q, &hba->reset_work); | |
868 | return IRQ_HANDLED; | |
5a25ba16 JG |
869 | } |
870 | ||
871 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
872 | ||
9eb46d2a | 873 | return IRQ_NONE; |
5a25ba16 JG |
874 | } |
875 | ||
0f3f6ee6 EL |
876 | static void stex_ss_mu_intr(struct st_hba *hba) |
877 | { | |
878 | struct status_msg *resp; | |
879 | struct st_ccb *ccb; | |
880 | __le32 *scratch; | |
881 | unsigned int size; | |
882 | int count = 0; | |
883 | u32 value; | |
884 | u16 tag; | |
885 | ||
886 | if (unlikely(hba->out_req_cnt <= 0 || | |
887 | hba->mu_status == MU_STATE_RESETTING)) | |
888 | return; | |
889 | ||
890 | while (count < hba->sts_count) { | |
891 | scratch = hba->scratch + hba->status_tail; | |
892 | value = le32_to_cpu(*scratch); | |
893 | if (unlikely(!(value & SS_STS_NORMAL))) | |
894 | return; | |
895 | ||
896 | resp = hba->status_buffer + hba->status_tail; | |
897 | *scratch = 0; | |
898 | ++count; | |
899 | ++hba->status_tail; | |
900 | hba->status_tail %= hba->sts_count+1; | |
901 | ||
902 | tag = (u16)value; | |
903 | if (unlikely(tag >= hba->host->can_queue)) { | |
904 | printk(KERN_WARNING DRV_NAME | |
69cb4875 | 905 | "(%s): invalid tag\n", pci_name(hba->pdev)); |
0f3f6ee6 EL |
906 | continue; |
907 | } | |
908 | ||
909 | hba->out_req_cnt--; | |
910 | ccb = &hba->ccb[tag]; | |
911 | if (unlikely(hba->wait_ccb == ccb)) | |
912 | hba->wait_ccb = NULL; | |
913 | if (unlikely(ccb->req == NULL)) { | |
914 | printk(KERN_WARNING DRV_NAME | |
915 | "(%s): lagging req\n", pci_name(hba->pdev)); | |
916 | continue; | |
917 | } | |
918 | ||
919 | ccb->req = NULL; | |
920 | if (likely(value & SS_STS_DONE)) { /* normal case */ | |
921 | ccb->srb_status = SRB_STATUS_SUCCESS; | |
922 | ccb->scsi_status = SAM_STAT_GOOD; | |
923 | } else { | |
924 | ccb->srb_status = resp->srb_status; | |
925 | ccb->scsi_status = resp->scsi_status; | |
926 | size = resp->payload_sz * sizeof(u32); | |
927 | if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN || | |
928 | size > sizeof(*resp))) { | |
929 | printk(KERN_WARNING DRV_NAME | |
930 | "(%s): bad status size\n", | |
931 | pci_name(hba->pdev)); | |
932 | } else { | |
933 | size -= sizeof(*resp) - STATUS_VAR_LEN; | |
934 | if (size) | |
935 | stex_copy_data(ccb, resp, size); | |
936 | } | |
937 | if (likely(ccb->cmd != NULL)) | |
938 | stex_check_cmd(hba, ccb, resp); | |
939 | } | |
940 | ||
941 | if (likely(ccb->cmd != NULL)) { | |
942 | scsi_dma_unmap(ccb->cmd); | |
943 | stex_scsi_done(ccb); | |
944 | } else | |
945 | ccb->req_type = 0; | |
946 | } | |
947 | } | |
948 | ||
949 | static irqreturn_t stex_ss_intr(int irq, void *__hba) | |
950 | { | |
951 | struct st_hba *hba = __hba; | |
952 | void __iomem *base = hba->mmio_base; | |
953 | u32 data; | |
954 | unsigned long flags; | |
0f3f6ee6 EL |
955 | |
956 | spin_lock_irqsave(hba->host->host_lock, flags); | |
957 | ||
958 | data = readl(base + YI2H_INT); | |
959 | if (data && data != 0xffffffff) { | |
960 | /* clear the interrupt */ | |
961 | writel(data, base + YI2H_INT_C); | |
962 | stex_ss_mu_intr(hba); | |
9eb46d2a EL |
963 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
964 | if (unlikely(data & SS_I2H_REQUEST_RESET)) | |
965 | queue_work(hba->work_q, &hba->reset_work); | |
966 | return IRQ_HANDLED; | |
0f3f6ee6 EL |
967 | } |
968 | ||
969 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
970 | ||
9eb46d2a | 971 | return IRQ_NONE; |
0f3f6ee6 EL |
972 | } |
973 | ||
974 | static int stex_common_handshake(struct st_hba *hba) | |
5a25ba16 JG |
975 | { |
976 | void __iomem *base = hba->mmio_base; | |
977 | struct handshake_frame *h; | |
978 | dma_addr_t status_phys; | |
529e7a62 | 979 | u32 data; |
76fbf96f | 980 | unsigned long before; |
5a25ba16 JG |
981 | |
982 | if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
983 | writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); | |
984 | readl(base + IDBL); | |
76fbf96f EL |
985 | before = jiffies; |
986 | while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
987 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
988 | printk(KERN_ERR DRV_NAME | |
989 | "(%s): no handshake signature\n", | |
990 | pci_name(hba->pdev)); | |
991 | return -1; | |
992 | } | |
5a25ba16 JG |
993 | rmb(); |
994 | msleep(1); | |
995 | } | |
5a25ba16 JG |
996 | } |
997 | ||
998 | udelay(10); | |
999 | ||
529e7a62 EL |
1000 | data = readl(base + OMR1); |
1001 | if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) { | |
1002 | data &= 0x0000ffff; | |
f1498161 | 1003 | if (hba->host->can_queue > data) { |
529e7a62 | 1004 | hba->host->can_queue = data; |
f1498161 EL |
1005 | hba->host->cmd_per_lun = data; |
1006 | } | |
529e7a62 EL |
1007 | } |
1008 | ||
f1498161 EL |
1009 | h = (struct handshake_frame *)hba->status_buffer; |
1010 | h->rb_phy = cpu_to_le64(hba->dma_handle); | |
591a3a5f EL |
1011 | h->req_sz = cpu_to_le16(hba->rq_size); |
1012 | h->req_cnt = cpu_to_le16(hba->rq_count+1); | |
5a25ba16 | 1013 | h->status_sz = cpu_to_le16(sizeof(struct status_msg)); |
591a3a5f | 1014 | h->status_cnt = cpu_to_le16(hba->sts_count+1); |
5a25ba16 JG |
1015 | stex_gettime(&h->hosttime); |
1016 | h->partner_type = HMU_PARTNER_TYPE; | |
591a3a5f EL |
1017 | if (hba->extra_offset) { |
1018 | h->extra_offset = cpu_to_le32(hba->extra_offset); | |
cbacfb5f | 1019 | h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset); |
94e9108b EL |
1020 | } else |
1021 | h->extra_offset = h->extra_size = 0; | |
5a25ba16 | 1022 | |
591a3a5f | 1023 | status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size; |
5a25ba16 JG |
1024 | writel(status_phys, base + IMR0); |
1025 | readl(base + IMR0); | |
1026 | writel((status_phys >> 16) >> 16, base + IMR1); | |
1027 | readl(base + IMR1); | |
1028 | ||
1029 | writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */ | |
1030 | readl(base + OMR0); | |
1031 | writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL); | |
1032 | readl(base + IDBL); /* flush */ | |
1033 | ||
1034 | udelay(10); | |
76fbf96f EL |
1035 | before = jiffies; |
1036 | while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) { | |
1037 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
1038 | printk(KERN_ERR DRV_NAME | |
1039 | "(%s): no signature after handshake frame\n", | |
1040 | pci_name(hba->pdev)); | |
1041 | return -1; | |
1042 | } | |
5a25ba16 JG |
1043 | rmb(); |
1044 | msleep(1); | |
1045 | } | |
1046 | ||
5a25ba16 JG |
1047 | writel(0, base + IMR0); |
1048 | readl(base + IMR0); | |
1049 | writel(0, base + OMR0); | |
1050 | readl(base + OMR0); | |
1051 | writel(0, base + IMR1); | |
1052 | readl(base + IMR1); | |
1053 | writel(0, base + OMR1); | |
1054 | readl(base + OMR1); /* flush */ | |
5a25ba16 JG |
1055 | return 0; |
1056 | } | |
1057 | ||
0f3f6ee6 EL |
1058 | static int stex_ss_handshake(struct st_hba *hba) |
1059 | { | |
1060 | void __iomem *base = hba->mmio_base; | |
1061 | struct st_msg_header *msg_h; | |
1062 | struct handshake_frame *h; | |
69cb4875 | 1063 | __le32 *scratch; |
9eb46d2a | 1064 | u32 data, scratch_size; |
0f3f6ee6 EL |
1065 | unsigned long before; |
1066 | int ret = 0; | |
1067 | ||
69cb4875 EL |
1068 | before = jiffies; |
1069 | while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) { | |
1070 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
1071 | printk(KERN_ERR DRV_NAME | |
1072 | "(%s): firmware not operational\n", | |
1073 | pci_name(hba->pdev)); | |
1074 | return -1; | |
1075 | } | |
1076 | msleep(1); | |
1077 | } | |
1078 | ||
1079 | msg_h = (struct st_msg_header *)hba->dma_mem; | |
0f3f6ee6 EL |
1080 | msg_h->handle = cpu_to_le64(hba->dma_handle); |
1081 | msg_h->flag = SS_HEAD_HANDSHAKE; | |
1082 | ||
69cb4875 | 1083 | h = (struct handshake_frame *)(msg_h + 1); |
0f3f6ee6 EL |
1084 | h->rb_phy = cpu_to_le64(hba->dma_handle); |
1085 | h->req_sz = cpu_to_le16(hba->rq_size); | |
1086 | h->req_cnt = cpu_to_le16(hba->rq_count+1); | |
1087 | h->status_sz = cpu_to_le16(sizeof(struct status_msg)); | |
1088 | h->status_cnt = cpu_to_le16(hba->sts_count+1); | |
1089 | stex_gettime(&h->hosttime); | |
1090 | h->partner_type = HMU_PARTNER_TYPE; | |
1091 | h->extra_offset = h->extra_size = 0; | |
9eb46d2a EL |
1092 | scratch_size = (hba->sts_count+1)*sizeof(u32); |
1093 | h->scratch_size = cpu_to_le32(scratch_size); | |
0f3f6ee6 EL |
1094 | |
1095 | data = readl(base + YINT_EN); | |
1096 | data &= ~4; | |
1097 | writel(data, base + YINT_EN); | |
1098 | writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI); | |
9eb46d2a | 1099 | readl(base + YH2I_REQ_HI); |
0f3f6ee6 | 1100 | writel(hba->dma_handle, base + YH2I_REQ); |
9eb46d2a | 1101 | readl(base + YH2I_REQ); /* flush */ |
0f3f6ee6 EL |
1102 | |
1103 | scratch = hba->scratch; | |
1104 | before = jiffies; | |
1105 | while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) { | |
1106 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | |
1107 | printk(KERN_ERR DRV_NAME | |
1108 | "(%s): no signature after handshake frame\n", | |
1109 | pci_name(hba->pdev)); | |
1110 | ret = -1; | |
1111 | break; | |
1112 | } | |
1113 | rmb(); | |
1114 | msleep(1); | |
1115 | } | |
1116 | ||
9eb46d2a | 1117 | memset(scratch, 0, scratch_size); |
0f3f6ee6 EL |
1118 | msg_h->flag = 0; |
1119 | return ret; | |
1120 | } | |
1121 | ||
1122 | static int stex_handshake(struct st_hba *hba) | |
1123 | { | |
1124 | int err; | |
1125 | unsigned long flags; | |
9eb46d2a | 1126 | unsigned int mu_status; |
0f3f6ee6 EL |
1127 | |
1128 | err = (hba->cardtype == st_yel) ? | |
1129 | stex_ss_handshake(hba) : stex_common_handshake(hba); | |
9eb46d2a EL |
1130 | spin_lock_irqsave(hba->host->host_lock, flags); |
1131 | mu_status = hba->mu_status; | |
0f3f6ee6 | 1132 | if (err == 0) { |
0f3f6ee6 EL |
1133 | hba->req_head = 0; |
1134 | hba->req_tail = 0; | |
1135 | hba->status_head = 0; | |
1136 | hba->status_tail = 0; | |
1137 | hba->out_req_cnt = 0; | |
1138 | hba->mu_status = MU_STATE_STARTED; | |
9eb46d2a EL |
1139 | } else |
1140 | hba->mu_status = MU_STATE_FAILED; | |
1141 | if (mu_status == MU_STATE_RESETTING) | |
1142 | wake_up_all(&hba->reset_waitq); | |
1143 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
0f3f6ee6 EL |
1144 | return err; |
1145 | } | |
1146 | ||
5a25ba16 JG |
1147 | static int stex_abort(struct scsi_cmnd *cmd) |
1148 | { | |
1149 | struct Scsi_Host *host = cmd->device->host; | |
1150 | struct st_hba *hba = (struct st_hba *)host->hostdata; | |
cf355883 | 1151 | u16 tag = cmd->request->tag; |
5a25ba16 JG |
1152 | void __iomem *base; |
1153 | u32 data; | |
1154 | int result = SUCCESS; | |
1155 | unsigned long flags; | |
c25da0af EL |
1156 | |
1157 | printk(KERN_INFO DRV_NAME | |
1158 | "(%s): aborting command\n", pci_name(hba->pdev)); | |
1159 | scsi_print_command(cmd); | |
1160 | ||
5a25ba16 JG |
1161 | base = hba->mmio_base; |
1162 | spin_lock_irqsave(host->host_lock, flags); | |
9eb46d2a EL |
1163 | if (tag < host->can_queue && |
1164 | hba->ccb[tag].req && hba->ccb[tag].cmd == cmd) | |
cf355883 | 1165 | hba->wait_ccb = &hba->ccb[tag]; |
9eb46d2a EL |
1166 | else |
1167 | goto out; | |
5a25ba16 | 1168 | |
0f3f6ee6 EL |
1169 | if (hba->cardtype == st_yel) { |
1170 | data = readl(base + YI2H_INT); | |
1171 | if (data == 0 || data == 0xffffffff) | |
1172 | goto fail_out; | |
5a25ba16 | 1173 | |
0f3f6ee6 EL |
1174 | writel(data, base + YI2H_INT_C); |
1175 | stex_ss_mu_intr(hba); | |
1176 | } else { | |
1177 | data = readl(base + ODBL); | |
1178 | if (data == 0 || data == 0xffffffff) | |
1179 | goto fail_out; | |
5a25ba16 | 1180 | |
0f3f6ee6 EL |
1181 | writel(data, base + ODBL); |
1182 | readl(base + ODBL); /* flush */ | |
5a25ba16 | 1183 | |
0f3f6ee6 EL |
1184 | stex_mu_intr(hba, data); |
1185 | } | |
5a25ba16 JG |
1186 | if (hba->wait_ccb == NULL) { |
1187 | printk(KERN_WARNING DRV_NAME | |
1188 | "(%s): lost interrupt\n", pci_name(hba->pdev)); | |
1189 | goto out; | |
1190 | } | |
1191 | ||
1192 | fail_out: | |
d5587d5d | 1193 | scsi_dma_unmap(cmd); |
5a25ba16 JG |
1194 | hba->wait_ccb->req = NULL; /* nullify the req's future return */ |
1195 | hba->wait_ccb = NULL; | |
1196 | result = FAILED; | |
1197 | out: | |
1198 | spin_unlock_irqrestore(host->host_lock, flags); | |
1199 | return result; | |
1200 | } | |
1201 | ||
1202 | static void stex_hard_reset(struct st_hba *hba) | |
1203 | { | |
1204 | struct pci_bus *bus; | |
1205 | int i; | |
1206 | u16 pci_cmd; | |
1207 | u8 pci_bctl; | |
1208 | ||
1209 | for (i = 0; i < 16; i++) | |
1210 | pci_read_config_dword(hba->pdev, i * 4, | |
1211 | &hba->pdev->saved_config_space[i]); | |
1212 | ||
1213 | /* Reset secondary bus. Our controller(MU/ATU) is the only device on | |
1214 | secondary bus. Consult Intel 80331/3 developer's manual for detail */ | |
1215 | bus = hba->pdev->bus; | |
1216 | pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl); | |
1217 | pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET; | |
1218 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | |
69f4a513 EL |
1219 | |
1220 | /* | |
1221 | * 1 ms may be enough for 8-port controllers. But 16-port controllers | |
1222 | * require more time to finish bus reset. Use 100 ms here for safety | |
1223 | */ | |
1224 | msleep(100); | |
5a25ba16 JG |
1225 | pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET; |
1226 | pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl); | |
1227 | ||
76fbf96f | 1228 | for (i = 0; i < MU_HARD_RESET_WAIT; i++) { |
5a25ba16 | 1229 | pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd); |
47c4f997 | 1230 | if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER)) |
5a25ba16 JG |
1231 | break; |
1232 | msleep(1); | |
1233 | } | |
1234 | ||
1235 | ssleep(5); | |
1236 | for (i = 0; i < 16; i++) | |
1237 | pci_write_config_dword(hba->pdev, i * 4, | |
1238 | hba->pdev->saved_config_space[i]); | |
1239 | } | |
1240 | ||
9eb46d2a EL |
1241 | static int stex_yos_reset(struct st_hba *hba) |
1242 | { | |
1243 | void __iomem *base; | |
1244 | unsigned long flags, before; | |
1245 | int ret = 0; | |
1246 | ||
1247 | base = hba->mmio_base; | |
1248 | writel(MU_INBOUND_DOORBELL_RESET, base + IDBL); | |
1249 | readl(base + IDBL); /* flush */ | |
1250 | before = jiffies; | |
1251 | while (hba->out_req_cnt > 0) { | |
1252 | if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { | |
1253 | printk(KERN_WARNING DRV_NAME | |
1254 | "(%s): reset timeout\n", pci_name(hba->pdev)); | |
1255 | ret = -1; | |
1256 | break; | |
1257 | } | |
1258 | msleep(1); | |
1259 | } | |
1260 | ||
1261 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1262 | if (ret == -1) | |
1263 | hba->mu_status = MU_STATE_FAILED; | |
1264 | else | |
1265 | hba->mu_status = MU_STATE_STARTED; | |
1266 | wake_up_all(&hba->reset_waitq); | |
1267 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1268 | ||
1269 | return ret; | |
1270 | } | |
1271 | ||
69cb4875 EL |
1272 | static void stex_ss_reset(struct st_hba *hba) |
1273 | { | |
1274 | writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT); | |
1275 | readl(hba->mmio_base + YH2I_INT); | |
1276 | ssleep(5); | |
1277 | } | |
1278 | ||
9eb46d2a | 1279 | static int stex_do_reset(struct st_hba *hba) |
5a25ba16 | 1280 | { |
9eb46d2a EL |
1281 | struct st_ccb *ccb; |
1282 | unsigned long flags; | |
1283 | unsigned int mu_status = MU_STATE_RESETTING; | |
1284 | u16 tag; | |
7cfe99a5 | 1285 | |
9eb46d2a EL |
1286 | spin_lock_irqsave(hba->host->host_lock, flags); |
1287 | if (hba->mu_status == MU_STATE_STARTING) { | |
1288 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1289 | printk(KERN_INFO DRV_NAME "(%s): request reset during init\n", | |
1290 | pci_name(hba->pdev)); | |
1291 | return 0; | |
1292 | } | |
1293 | while (hba->mu_status == MU_STATE_RESETTING) { | |
1294 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1295 | wait_event_timeout(hba->reset_waitq, | |
1296 | hba->mu_status != MU_STATE_RESETTING, | |
1297 | MU_MAX_DELAY * HZ); | |
1298 | spin_lock_irqsave(hba->host->host_lock, flags); | |
1299 | mu_status = hba->mu_status; | |
1300 | } | |
5a25ba16 | 1301 | |
9eb46d2a EL |
1302 | if (mu_status != MU_STATE_RESETTING) { |
1303 | spin_unlock_irqrestore(hba->host->host_lock, flags); | |
1304 | return (mu_status == MU_STATE_STARTED) ? 0 : -1; | |
1305 | } | |
c25da0af | 1306 | |
5a25ba16 | 1307 | hba->mu_status = MU_STATE_RESETTING; |
9eb46d2a EL |
1308 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
1309 | ||
1310 | if (hba->cardtype == st_yosemite) | |
1311 | return stex_yos_reset(hba); | |
5a25ba16 JG |
1312 | |
1313 | if (hba->cardtype == st_shasta) | |
1314 | stex_hard_reset(hba); | |
69cb4875 EL |
1315 | else if (hba->cardtype == st_yel) |
1316 | stex_ss_reset(hba); | |
5a25ba16 | 1317 | |
9eb46d2a EL |
1318 | spin_lock_irqsave(hba->host->host_lock, flags); |
1319 | for (tag = 0; tag < hba->host->can_queue; tag++) { | |
1320 | ccb = &hba->ccb[tag]; | |
1321 | if (ccb->req == NULL) | |
1322 | continue; | |
1323 | ccb->req = NULL; | |
1324 | if (ccb->cmd) { | |
1325 | scsi_dma_unmap(ccb->cmd); | |
1326 | ccb->cmd->result = DID_RESET << 16; | |
1327 | ccb->cmd->scsi_done(ccb->cmd); | |
1328 | ccb->cmd = NULL; | |
fb4f66be | 1329 | } |
5a25ba16 | 1330 | } |
9eb46d2a | 1331 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
5a25ba16 | 1332 | |
9eb46d2a EL |
1333 | if (stex_handshake(hba) == 0) |
1334 | return 0; | |
fb4f66be | 1335 | |
9eb46d2a EL |
1336 | printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n", |
1337 | pci_name(hba->pdev)); | |
1338 | return -1; | |
1339 | } | |
1340 | ||
1341 | static int stex_reset(struct scsi_cmnd *cmd) | |
1342 | { | |
1343 | struct st_hba *hba; | |
1344 | ||
1345 | hba = (struct st_hba *) &cmd->device->host->hostdata[0]; | |
1346 | ||
1347 | printk(KERN_INFO DRV_NAME | |
1348 | "(%s): resetting host\n", pci_name(hba->pdev)); | |
1349 | scsi_print_command(cmd); | |
1350 | ||
1351 | return stex_do_reset(hba) ? FAILED : SUCCESS; | |
1352 | } | |
1353 | ||
1354 | static void stex_reset_work(struct work_struct *work) | |
1355 | { | |
1356 | struct st_hba *hba = container_of(work, struct st_hba, reset_work); | |
1357 | ||
1358 | stex_do_reset(hba); | |
5a25ba16 JG |
1359 | } |
1360 | ||
1361 | static int stex_biosparam(struct scsi_device *sdev, | |
1362 | struct block_device *bdev, sector_t capacity, int geom[]) | |
1363 | { | |
b4b8bed1 | 1364 | int heads = 255, sectors = 63; |
5a25ba16 JG |
1365 | |
1366 | if (capacity < 0x200000) { | |
1367 | heads = 64; | |
1368 | sectors = 32; | |
1369 | } | |
1370 | ||
b4b8bed1 | 1371 | sector_div(capacity, heads * sectors); |
5a25ba16 JG |
1372 | |
1373 | geom[0] = heads; | |
1374 | geom[1] = sectors; | |
b4b8bed1 | 1375 | geom[2] = capacity; |
5a25ba16 JG |
1376 | |
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static struct scsi_host_template driver_template = { | |
1381 | .module = THIS_MODULE, | |
1382 | .name = DRV_NAME, | |
1383 | .proc_name = DRV_NAME, | |
1384 | .bios_param = stex_biosparam, | |
1385 | .queuecommand = stex_queuecommand, | |
cf355883 | 1386 | .slave_alloc = stex_slave_alloc, |
5a25ba16 JG |
1387 | .slave_configure = stex_slave_config, |
1388 | .slave_destroy = stex_slave_destroy, | |
1389 | .eh_abort_handler = stex_abort, | |
1390 | .eh_host_reset_handler = stex_reset, | |
5a25ba16 | 1391 | .this_id = -1, |
591a3a5f EL |
1392 | }; |
1393 | ||
1394 | static struct pci_device_id stex_pci_tbl[] = { | |
1395 | /* st_shasta */ | |
1396 | { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1397 | st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */ | |
1398 | { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1399 | st_shasta }, /* SuperTrak EX12350 */ | |
1400 | { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1401 | st_shasta }, /* SuperTrak EX4350 */ | |
1402 | { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1403 | st_shasta }, /* SuperTrak EX24350 */ | |
1404 | ||
1405 | /* st_vsc */ | |
1406 | { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc }, | |
1407 | ||
1408 | /* st_yosemite */ | |
0f3f6ee6 | 1409 | { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite }, |
591a3a5f EL |
1410 | |
1411 | /* st_seq */ | |
1412 | { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq }, | |
0f3f6ee6 EL |
1413 | |
1414 | /* st_yel */ | |
1415 | { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel }, | |
1416 | { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel }, | |
591a3a5f EL |
1417 | { } /* terminate list */ |
1418 | }; | |
1419 | ||
1420 | static struct st_card_info stex_card_info[] = { | |
1421 | /* st_shasta */ | |
1422 | { | |
1423 | .max_id = 17, | |
1424 | .max_lun = 8, | |
1425 | .max_channel = 0, | |
1426 | .rq_count = 32, | |
1427 | .rq_size = 1048, | |
1428 | .sts_count = 32, | |
0f3f6ee6 EL |
1429 | .alloc_rq = stex_alloc_req, |
1430 | .map_sg = stex_map_sg, | |
1431 | .send = stex_send_cmd, | |
591a3a5f EL |
1432 | }, |
1433 | ||
1434 | /* st_vsc */ | |
1435 | { | |
1436 | .max_id = 129, | |
1437 | .max_lun = 1, | |
1438 | .max_channel = 0, | |
1439 | .rq_count = 32, | |
1440 | .rq_size = 1048, | |
1441 | .sts_count = 32, | |
0f3f6ee6 EL |
1442 | .alloc_rq = stex_alloc_req, |
1443 | .map_sg = stex_map_sg, | |
1444 | .send = stex_send_cmd, | |
591a3a5f EL |
1445 | }, |
1446 | ||
1447 | /* st_yosemite */ | |
1448 | { | |
1449 | .max_id = 2, | |
1450 | .max_lun = 256, | |
1451 | .max_channel = 0, | |
1452 | .rq_count = 256, | |
1453 | .rq_size = 1048, | |
1454 | .sts_count = 256, | |
0f3f6ee6 EL |
1455 | .alloc_rq = stex_alloc_req, |
1456 | .map_sg = stex_map_sg, | |
1457 | .send = stex_send_cmd, | |
591a3a5f EL |
1458 | }, |
1459 | ||
1460 | /* st_seq */ | |
1461 | { | |
1462 | .max_id = 129, | |
1463 | .max_lun = 1, | |
1464 | .max_channel = 0, | |
1465 | .rq_count = 32, | |
1466 | .rq_size = 1048, | |
1467 | .sts_count = 32, | |
0f3f6ee6 EL |
1468 | .alloc_rq = stex_alloc_req, |
1469 | .map_sg = stex_map_sg, | |
1470 | .send = stex_send_cmd, | |
1471 | }, | |
1472 | ||
1473 | /* st_yel */ | |
1474 | { | |
1475 | .max_id = 129, | |
1476 | .max_lun = 256, | |
1477 | .max_channel = 3, | |
1478 | .rq_count = 801, | |
1479 | .rq_size = 512, | |
1480 | .sts_count = 801, | |
1481 | .alloc_rq = stex_ss_alloc_req, | |
1482 | .map_sg = stex_ss_map_sg, | |
1483 | .send = stex_ss_send_cmd, | |
591a3a5f | 1484 | }, |
5a25ba16 JG |
1485 | }; |
1486 | ||
1487 | static int stex_set_dma_mask(struct pci_dev * pdev) | |
1488 | { | |
1489 | int ret; | |
7cfe99a5 | 1490 | |
6a35528a YH |
1491 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) |
1492 | && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) | |
5a25ba16 | 1493 | return 0; |
284901a9 | 1494 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
5a25ba16 | 1495 | if (!ret) |
284901a9 | 1496 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
5a25ba16 JG |
1497 | return ret; |
1498 | } | |
1499 | ||
99946f81 EL |
1500 | static int stex_request_irq(struct st_hba *hba) |
1501 | { | |
1502 | struct pci_dev *pdev = hba->pdev; | |
1503 | int status; | |
1504 | ||
1505 | if (msi) { | |
1506 | status = pci_enable_msi(pdev); | |
1507 | if (status != 0) | |
1508 | printk(KERN_ERR DRV_NAME | |
1509 | "(%s): error %d setting up MSI\n", | |
1510 | pci_name(pdev), status); | |
1511 | else | |
1512 | hba->msi_enabled = 1; | |
1513 | } else | |
1514 | hba->msi_enabled = 0; | |
1515 | ||
0f3f6ee6 EL |
1516 | status = request_irq(pdev->irq, hba->cardtype == st_yel ? |
1517 | stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba); | |
99946f81 EL |
1518 | |
1519 | if (status != 0) { | |
1520 | if (hba->msi_enabled) | |
1521 | pci_disable_msi(pdev); | |
1522 | } | |
1523 | return status; | |
1524 | } | |
1525 | ||
1526 | static void stex_free_irq(struct st_hba *hba) | |
1527 | { | |
1528 | struct pci_dev *pdev = hba->pdev; | |
1529 | ||
1530 | free_irq(pdev->irq, hba); | |
1531 | if (hba->msi_enabled) | |
1532 | pci_disable_msi(pdev); | |
1533 | } | |
1534 | ||
5a25ba16 JG |
1535 | static int __devinit |
1536 | stex_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
1537 | { | |
1538 | struct st_hba *hba; | |
1539 | struct Scsi_Host *host; | |
591a3a5f | 1540 | const struct st_card_info *ci = NULL; |
0f3f6ee6 | 1541 | u32 sts_offset, cp_offset, scratch_offset; |
5a25ba16 JG |
1542 | int err; |
1543 | ||
1544 | err = pci_enable_device(pdev); | |
1545 | if (err) | |
1546 | return err; | |
1547 | ||
1548 | pci_set_master(pdev); | |
1549 | ||
1550 | host = scsi_host_alloc(&driver_template, sizeof(struct st_hba)); | |
1551 | ||
1552 | if (!host) { | |
1553 | printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n", | |
1554 | pci_name(pdev)); | |
1555 | err = -ENOMEM; | |
1556 | goto out_disable; | |
1557 | } | |
1558 | ||
1559 | hba = (struct st_hba *)host->hostdata; | |
1560 | memset(hba, 0, sizeof(struct st_hba)); | |
1561 | ||
1562 | err = pci_request_regions(pdev, DRV_NAME); | |
1563 | if (err < 0) { | |
1564 | printk(KERN_ERR DRV_NAME "(%s): request regions failed\n", | |
1565 | pci_name(pdev)); | |
1566 | goto out_scsi_host_put; | |
1567 | } | |
1568 | ||
25729a7f | 1569 | hba->mmio_base = pci_ioremap_bar(pdev, 0); |
5a25ba16 JG |
1570 | if ( !hba->mmio_base) { |
1571 | printk(KERN_ERR DRV_NAME "(%s): memory map failed\n", | |
1572 | pci_name(pdev)); | |
1573 | err = -ENOMEM; | |
1574 | goto out_release_regions; | |
1575 | } | |
1576 | ||
1577 | err = stex_set_dma_mask(pdev); | |
1578 | if (err) { | |
1579 | printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n", | |
1580 | pci_name(pdev)); | |
1581 | goto out_iounmap; | |
1582 | } | |
1583 | ||
94e9108b | 1584 | hba->cardtype = (unsigned int) id->driver_data; |
591a3a5f | 1585 | ci = &stex_card_info[hba->cardtype]; |
0f3f6ee6 EL |
1586 | sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size; |
1587 | if (hba->cardtype == st_yel) | |
1588 | sts_offset += (ci->sts_count+1) * sizeof(u32); | |
591a3a5f EL |
1589 | cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg); |
1590 | hba->dma_size = cp_offset + sizeof(struct st_frame); | |
1591 | if (hba->cardtype == st_seq || | |
1592 | (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { | |
1593 | hba->extra_offset = hba->dma_size; | |
1594 | hba->dma_size += ST_ADDITIONAL_MEM; | |
1595 | } | |
5a25ba16 | 1596 | hba->dma_mem = dma_alloc_coherent(&pdev->dev, |
94e9108b | 1597 | hba->dma_size, &hba->dma_handle, GFP_KERNEL); |
5a25ba16 | 1598 | if (!hba->dma_mem) { |
cbacfb5f EL |
1599 | /* Retry minimum coherent mapping for st_seq and st_vsc */ |
1600 | if (hba->cardtype == st_seq || | |
1601 | (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) { | |
1602 | printk(KERN_WARNING DRV_NAME | |
1603 | "(%s): allocating min buffer for controller\n", | |
1604 | pci_name(pdev)); | |
1605 | hba->dma_size = hba->extra_offset | |
1606 | + ST_ADDITIONAL_MEM_MIN; | |
1607 | hba->dma_mem = dma_alloc_coherent(&pdev->dev, | |
1608 | hba->dma_size, &hba->dma_handle, GFP_KERNEL); | |
1609 | } | |
1610 | ||
1611 | if (!hba->dma_mem) { | |
1612 | err = -ENOMEM; | |
1613 | printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n", | |
1614 | pci_name(pdev)); | |
1615 | goto out_iounmap; | |
1616 | } | |
5a25ba16 JG |
1617 | } |
1618 | ||
591a3a5f EL |
1619 | hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL); |
1620 | if (!hba->ccb) { | |
1621 | err = -ENOMEM; | |
1622 | printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n", | |
1623 | pci_name(pdev)); | |
1624 | goto out_pci_free; | |
1625 | } | |
1626 | ||
0f3f6ee6 EL |
1627 | if (hba->cardtype == st_yel) |
1628 | hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset); | |
591a3a5f EL |
1629 | hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset); |
1630 | hba->copy_buffer = hba->dma_mem + cp_offset; | |
1631 | hba->rq_count = ci->rq_count; | |
1632 | hba->rq_size = ci->rq_size; | |
1633 | hba->sts_count = ci->sts_count; | |
0f3f6ee6 EL |
1634 | hba->alloc_rq = ci->alloc_rq; |
1635 | hba->map_sg = ci->map_sg; | |
1636 | hba->send = ci->send; | |
5a25ba16 JG |
1637 | hba->mu_status = MU_STATE_STARTING; |
1638 | ||
0f3f6ee6 EL |
1639 | if (hba->cardtype == st_yel) |
1640 | host->sg_tablesize = 38; | |
1641 | else | |
1642 | host->sg_tablesize = 32; | |
591a3a5f EL |
1643 | host->can_queue = ci->rq_count; |
1644 | host->cmd_per_lun = ci->rq_count; | |
1645 | host->max_id = ci->max_id; | |
1646 | host->max_lun = ci->max_lun; | |
1647 | host->max_channel = ci->max_channel; | |
5a25ba16 JG |
1648 | host->unique_id = host->host_no; |
1649 | host->max_cmd_len = STEX_CDB_LENGTH; | |
1650 | ||
1651 | hba->host = host; | |
1652 | hba->pdev = pdev; | |
9eb46d2a EL |
1653 | init_waitqueue_head(&hba->reset_waitq); |
1654 | ||
1655 | snprintf(hba->work_q_name, sizeof(hba->work_q_name), | |
1656 | "stex_wq_%d", host->host_no); | |
1657 | hba->work_q = create_singlethread_workqueue(hba->work_q_name); | |
1658 | if (!hba->work_q) { | |
1659 | printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n", | |
1660 | pci_name(pdev)); | |
1661 | err = -ENOMEM; | |
1662 | goto out_ccb_free; | |
1663 | } | |
1664 | INIT_WORK(&hba->reset_work, stex_reset_work); | |
5a25ba16 | 1665 | |
99946f81 | 1666 | err = stex_request_irq(hba); |
5a25ba16 JG |
1667 | if (err) { |
1668 | printk(KERN_ERR DRV_NAME "(%s): request irq failed\n", | |
1669 | pci_name(pdev)); | |
9eb46d2a | 1670 | goto out_free_wq; |
5a25ba16 JG |
1671 | } |
1672 | ||
1673 | err = stex_handshake(hba); | |
1674 | if (err) | |
1675 | goto out_free_irq; | |
1676 | ||
529e7a62 | 1677 | err = scsi_init_shared_tag_map(host, host->can_queue); |
deb81d80 | 1678 | if (err) { |
cf355883 EL |
1679 | printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n", |
1680 | pci_name(pdev)); | |
1681 | goto out_free_irq; | |
1682 | } | |
1683 | ||
5a25ba16 JG |
1684 | pci_set_drvdata(pdev, hba); |
1685 | ||
1686 | err = scsi_add_host(host, &pdev->dev); | |
1687 | if (err) { | |
1688 | printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n", | |
1689 | pci_name(pdev)); | |
1690 | goto out_free_irq; | |
1691 | } | |
1692 | ||
1693 | scsi_scan_host(host); | |
1694 | ||
1695 | return 0; | |
1696 | ||
1697 | out_free_irq: | |
99946f81 | 1698 | stex_free_irq(hba); |
9eb46d2a EL |
1699 | out_free_wq: |
1700 | destroy_workqueue(hba->work_q); | |
591a3a5f EL |
1701 | out_ccb_free: |
1702 | kfree(hba->ccb); | |
5a25ba16 | 1703 | out_pci_free: |
94e9108b | 1704 | dma_free_coherent(&pdev->dev, hba->dma_size, |
5a25ba16 JG |
1705 | hba->dma_mem, hba->dma_handle); |
1706 | out_iounmap: | |
1707 | iounmap(hba->mmio_base); | |
1708 | out_release_regions: | |
1709 | pci_release_regions(pdev); | |
1710 | out_scsi_host_put: | |
1711 | scsi_host_put(host); | |
1712 | out_disable: | |
1713 | pci_disable_device(pdev); | |
1714 | ||
1715 | return err; | |
1716 | } | |
1717 | ||
1718 | static void stex_hba_stop(struct st_hba *hba) | |
1719 | { | |
1720 | struct req_msg *req; | |
0f3f6ee6 | 1721 | struct st_msg_header *msg_h; |
5a25ba16 JG |
1722 | unsigned long flags; |
1723 | unsigned long before; | |
cf355883 | 1724 | u16 tag = 0; |
5a25ba16 JG |
1725 | |
1726 | spin_lock_irqsave(hba->host->host_lock, flags); | |
0f3f6ee6 EL |
1727 | req = hba->alloc_rq(hba); |
1728 | if (hba->cardtype == st_yel) { | |
1729 | msg_h = (struct st_msg_header *)req - 1; | |
1730 | memset(msg_h, 0, hba->rq_size); | |
1731 | } else | |
1732 | memset(req, 0, hba->rq_size); | |
5a25ba16 | 1733 | |
0f3f6ee6 | 1734 | if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) { |
fb4f66be EL |
1735 | req->cdb[0] = MGT_CMD; |
1736 | req->cdb[1] = MGT_CMD_SIGNATURE; | |
1737 | req->cdb[2] = CTLR_CONFIG_CMD; | |
1738 | req->cdb[3] = CTLR_SHUTDOWN; | |
1739 | } else { | |
1740 | req->cdb[0] = CONTROLLER_CMD; | |
1741 | req->cdb[1] = CTLR_POWER_STATE_CHANGE; | |
1742 | req->cdb[2] = CTLR_POWER_SAVING; | |
1743 | } | |
5a25ba16 JG |
1744 | |
1745 | hba->ccb[tag].cmd = NULL; | |
1746 | hba->ccb[tag].sg_count = 0; | |
1747 | hba->ccb[tag].sense_bufflen = 0; | |
1748 | hba->ccb[tag].sense_buffer = NULL; | |
f1498161 | 1749 | hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE; |
5a25ba16 | 1750 | |
0f3f6ee6 | 1751 | hba->send(hba, req, tag); |
5a25ba16 JG |
1752 | spin_unlock_irqrestore(hba->host->host_lock, flags); |
1753 | ||
cf355883 EL |
1754 | before = jiffies; |
1755 | while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) { | |
f1498161 EL |
1756 | if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) { |
1757 | hba->ccb[tag].req_type = 0; | |
cf355883 | 1758 | return; |
f1498161 EL |
1759 | } |
1760 | msleep(1); | |
cf355883 | 1761 | } |
5a25ba16 JG |
1762 | } |
1763 | ||
1764 | static void stex_hba_free(struct st_hba *hba) | |
1765 | { | |
99946f81 | 1766 | stex_free_irq(hba); |
5a25ba16 | 1767 | |
9eb46d2a EL |
1768 | destroy_workqueue(hba->work_q); |
1769 | ||
5a25ba16 JG |
1770 | iounmap(hba->mmio_base); |
1771 | ||
1772 | pci_release_regions(hba->pdev); | |
1773 | ||
591a3a5f EL |
1774 | kfree(hba->ccb); |
1775 | ||
94e9108b | 1776 | dma_free_coherent(&hba->pdev->dev, hba->dma_size, |
5a25ba16 JG |
1777 | hba->dma_mem, hba->dma_handle); |
1778 | } | |
1779 | ||
1780 | static void stex_remove(struct pci_dev *pdev) | |
1781 | { | |
1782 | struct st_hba *hba = pci_get_drvdata(pdev); | |
1783 | ||
1784 | scsi_remove_host(hba->host); | |
1785 | ||
1786 | pci_set_drvdata(pdev, NULL); | |
1787 | ||
1788 | stex_hba_stop(hba); | |
1789 | ||
1790 | stex_hba_free(hba); | |
1791 | ||
1792 | scsi_host_put(hba->host); | |
1793 | ||
1794 | pci_disable_device(pdev); | |
1795 | } | |
1796 | ||
1797 | static void stex_shutdown(struct pci_dev *pdev) | |
1798 | { | |
1799 | struct st_hba *hba = pci_get_drvdata(pdev); | |
1800 | ||
1801 | stex_hba_stop(hba); | |
1802 | } | |
1803 | ||
5a25ba16 JG |
1804 | MODULE_DEVICE_TABLE(pci, stex_pci_tbl); |
1805 | ||
1806 | static struct pci_driver stex_pci_driver = { | |
1807 | .name = DRV_NAME, | |
1808 | .id_table = stex_pci_tbl, | |
1809 | .probe = stex_probe, | |
1810 | .remove = __devexit_p(stex_remove), | |
1811 | .shutdown = stex_shutdown, | |
1812 | }; | |
1813 | ||
1814 | static int __init stex_init(void) | |
1815 | { | |
1816 | printk(KERN_INFO DRV_NAME | |
1817 | ": Promise SuperTrak EX Driver version: %s\n", | |
1818 | ST_DRIVER_VERSION); | |
1819 | ||
1820 | return pci_register_driver(&stex_pci_driver); | |
1821 | } | |
1822 | ||
1823 | static void __exit stex_exit(void) | |
1824 | { | |
1825 | pci_unregister_driver(&stex_pci_driver); | |
1826 | } | |
1827 | ||
1828 | module_init(stex_init); | |
1829 | module_exit(stex_exit); |