[mirror_ubuntu-jammy-kernel.git] / drivers / scsi / sun3_scsi.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
 *
 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
 *
 * VME support added by Sam Creasey
 *
 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
 *
 * Adapted from mac_scsinew.c:
 */
/*
 * Generic Macintosh NCR5380 driver
 *
 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
 *
 * derived in part from:
 */
/*
 * Generic Generic NCR5380 driver
 *
 * Copyright 1995, Russell King
 */

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/platform_device.h>

#include <asm/io.h>
#include <asm/dvma.h>

#include <scsi/scsi_host.h>

/* minimum number of bytes to do dma on */
#define DMA_MIN_SIZE                    129

/* Definitions for the core NCR5380 driver. */

#define NCR5380_implementation_fields   /* none */

#define NCR5380_read(reg)               in_8(hostdata->io + (reg))
#define NCR5380_write(reg, value)       out_8(hostdata->io + (reg), value)

#define NCR5380_queue_command           sun3scsi_queue_command
#define NCR5380_host_reset              sun3scsi_host_reset
#define NCR5380_abort                   sun3scsi_abort
#define NCR5380_info                    sun3scsi_info

#define NCR5380_dma_xfer_len            sun3scsi_dma_xfer_len
#define NCR5380_dma_recv_setup          sun3scsi_dma_count
#define NCR5380_dma_send_setup          sun3scsi_dma_count
#define NCR5380_dma_residual            sun3scsi_dma_residual

#include "NCR5380.h"

/* dma regs start at regbase + 8, directly after the NCR regs */
struct sun3_dma_regs {
	unsigned short dma_addr_hi; /* vme only */
	unsigned short dma_addr_lo; /* vme only */
	unsigned short dma_count_hi; /* vme only */
	unsigned short dma_count_lo; /* vme only */
	unsigned short udc_data; /* udc dma data reg (obio only) */
	unsigned short udc_addr; /* uda dma addr reg (obio only) */
	unsigned short fifo_data; /* fifo data reg,
	                           * holds extra byte on odd dma reads
	                           */
	unsigned short fifo_count;
	unsigned short csr; /* control/status reg */
	unsigned short bpack_hi; /* vme only */
	unsigned short bpack_lo; /* vme only */
	unsigned short ivect; /* vme only */
	unsigned short fifo_count_hi; /* vme only */
};

/* ucd chip specific regs - live in dvma space */
struct sun3_udc_regs {
	unsigned short rsel; /* select regs to load */
	unsigned short addr_hi; /* high word of addr */
	unsigned short addr_lo; /* low word */
	unsigned short count; /* words to be xfer'd */
	unsigned short mode_hi; /* high word of channel mode */
	unsigned short mode_lo; /* low word of channel mode */
};

/* addresses of the udc registers */
#define UDC_MODE 0x38
#define UDC_CSR 0x2e /* command/status */
#define UDC_CHN_HI 0x26 /* chain high word */
#define UDC_CHN_LO 0x22 /* chain lo word */
#define UDC_CURA_HI 0x1a /* cur reg A high */
#define UDC_CURA_LO 0x0a /* cur reg A low */
#define UDC_CURB_HI 0x12 /* cur reg B high */
#define UDC_CURB_LO 0x02 /* cur reg B low */
#define UDC_MODE_HI 0x56 /* mode reg high */
#define UDC_MODE_LO 0x52 /* mode reg low */
#define UDC_COUNT 0x32 /* words to xfer */

/* some udc commands */
#define UDC_RESET 0
#define UDC_CHN_START 0xa0 /* start chain */
#define UDC_INT_ENABLE 0x32 /* channel 1 int on */

/* udc mode words */
#define UDC_MODE_HIWORD 0x40
#define UDC_MODE_LSEND 0xc2
#define UDC_MODE_LRECV 0xd2

/* udc reg selections */
#define UDC_RSEL_SEND 0x282
#define UDC_RSEL_RECV 0x182

/* bits in csr reg */
#define CSR_DMA_ACTIVE 0x8000
#define CSR_DMA_CONFLICT 0x4000
#define CSR_DMA_BUSERR 0x2000

#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
#define CSR_DMA_INT 0x100 /* dma interrupt pending */

#define CSR_LEFT 0xc0
#define CSR_LEFT_3 0xc0
#define CSR_LEFT_2 0x80
#define CSR_LEFT_1 0x40
#define CSR_PACK_ENABLE 0x20

#define CSR_DMA_ENABLE 0x10

#define CSR_SEND 0x8 /* 1 = send  0 = recv */
#define CSR_FIFO 0x2 /* reset fifo */
#define CSR_INTR 0x4 /* interrupt enable */
#define CSR_SCSI 0x1

#define VME_DATA24 0x3d00

extern int sun3_map_test(unsigned long, char *);

static int setup_can_queue = -1;
module_param(setup_can_queue, int, 0);
static int setup_cmd_per_lun = -1;
module_param(setup_cmd_per_lun, int, 0);
static int setup_sg_tablesize = -1;
module_param(setup_sg_tablesize, int, 0);
static int setup_hostid = -1;
module_param(setup_hostid, int, 0);

/* ms to wait after hitting dma regs */
#define SUN3_DMA_DELAY 10

/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
#define SUN3_DVMA_BUFSIZE 0xe000

static struct scsi_cmnd *sun3_dma_setup_done;
static volatile struct sun3_dma_regs *dregs;
static struct sun3_udc_regs *udc_regs;
static unsigned char *sun3_dma_orig_addr;
static unsigned long sun3_dma_orig_count;
static int sun3_dma_active;
static unsigned long last_residual;

#ifndef SUN3_SCSI_VME
/* dma controller register access functions */

static inline unsigned short sun3_udc_read(unsigned char reg)
{
	unsigned short ret;

	dregs->udc_addr = UDC_CSR;
	udelay(SUN3_DMA_DELAY);
	ret = dregs->udc_data;
	udelay(SUN3_DMA_DELAY);
	
	return ret;
}

static inline void sun3_udc_write(unsigned short val, unsigned char reg)
{
	dregs->udc_addr = reg;
	udelay(SUN3_DMA_DELAY);
	dregs->udc_data = val;
	udelay(SUN3_DMA_DELAY);
}
#endif

// safe bits for the CSR
#define CSR_GOOD 0x060f

static irqreturn_t scsi_sun3_intr(int irq, void *dev)
{
	struct Scsi_Host *instance = dev;
	unsigned short csr = dregs->csr;
	int handled = 0;

#ifdef SUN3_SCSI_VME
	dregs->csr &= ~CSR_DMA_ENABLE;
#endif

	if(csr & ~CSR_GOOD) {
		if (csr & CSR_DMA_BUSERR)
			shost_printk(KERN_ERR, instance, "bus error in DMA\n");
		if (csr & CSR_DMA_CONFLICT)
			shost_printk(KERN_ERR, instance, "DMA conflict\n");
		handled = 1;
	}

	if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
		NCR5380_intr(irq, dev);
		handled = 1;
	}

	return IRQ_RETVAL(handled);
}

/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
                              unsigned char *data, int count, int write_flag)
{
	void *addr;

	if(sun3_dma_orig_addr != NULL)
		dvma_unmap(sun3_dma_orig_addr);

#ifdef SUN3_SCSI_VME
	addr = (void *)dvma_map_vme((unsigned long) data, count);
#else
	addr = (void *)dvma_map((unsigned long) data, count);
#endif
		
	sun3_dma_orig_addr = addr;
	sun3_dma_orig_count = count;

#ifndef SUN3_SCSI_VME
	dregs->fifo_count = 0;
	sun3_udc_write(UDC_RESET, UDC_CSR);
	
	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
#endif
	
	/* set direction */
	if(write_flag)
		dregs->csr |= CSR_SEND;
	else
		dregs->csr &= ~CSR_SEND;
	
#ifdef SUN3_SCSI_VME
	dregs->csr |= CSR_PACK_ENABLE;

	dregs->dma_addr_hi = ((unsigned long)addr >> 16);
	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);

	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;
	dregs->fifo_count_hi = 0;
	dregs->fifo_count = 0;
#else
	/* byte count for fifo */
	dregs->fifo_count = count;

	sun3_udc_write(UDC_RESET, UDC_CSR);
	
	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
	
	if(dregs->fifo_count != count) { 
		shost_printk(KERN_ERR, hostdata->host,
		             "FIFO mismatch %04x not %04x\n",
		             dregs->fifo_count, (unsigned int) count);
		NCR5380_dprint(NDEBUG_DMA, hostdata->host);
	}

	/* setup udc */
	udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
	udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
	udc_regs->count = count/2; /* count in words */
	udc_regs->mode_hi = UDC_MODE_HIWORD;
	if(write_flag) {
		if(count & 1)
			udc_regs->count++;
		udc_regs->mode_lo = UDC_MODE_LSEND;
		udc_regs->rsel = UDC_RSEL_SEND;
	} else {
		udc_regs->mode_lo = UDC_MODE_LRECV;
		udc_regs->rsel = UDC_RSEL_RECV;
	}
	
	/* announce location of regs block */
	sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
		       UDC_CHN_HI); 

	sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);

	/* set dma master on */
	sun3_udc_write(0xd, UDC_MODE);

	/* interrupt enable */
	sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
#endif
	
       	return count;

}

static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
                              unsigned char *data, int count)
{
	return count;
}

static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
                                          unsigned char *data, int count)
{
	return sun3scsi_dma_setup(hostdata, data, count, 0);
}

static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
                                          unsigned char *data, int count)
{
	return sun3scsi_dma_setup(hostdata, data, count, 1);
}

static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
{
	return last_residual;
}

static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
                                 struct scsi_cmnd *cmd)
{
	int wanted_len = cmd->SCp.this_residual;

	if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request))
		return 0;

	return wanted_len;
}

static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
{
#ifdef SUN3_SCSI_VME
	unsigned short csr;

	csr = dregs->csr;

	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);

	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);

/*	if(!(csr & CSR_DMA_ENABLE))
 *		dregs->csr |= CSR_DMA_ENABLE;
 */
#else
    sun3_udc_write(UDC_CHN_START, UDC_CSR);
#endif
    
    return 0;
}

/* clean up after our dma is done */
static int sun3scsi_dma_finish(int write_flag)
{
	unsigned short __maybe_unused count;
	unsigned short fifo;
	int ret = 0;
	
	sun3_dma_active = 0;

#ifdef SUN3_SCSI_VME
	dregs->csr &= ~CSR_DMA_ENABLE;

	fifo = dregs->fifo_count;
	if (write_flag) {
		if ((fifo > 0) && (fifo < sun3_dma_orig_count))
			fifo++;
	}

	last_residual = fifo;
	/* empty bytes from the fifo which didn't make it */
	if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
		unsigned char *vaddr;

		vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);

		vaddr += (sun3_dma_orig_count - fifo);
		vaddr--;

		switch (dregs->csr & CSR_LEFT) {
		case CSR_LEFT_3:
			*vaddr = (dregs->bpack_lo & 0xff00) >> 8;
			vaddr--;
			fallthrough;

		case CSR_LEFT_2:
			*vaddr = (dregs->bpack_hi & 0x00ff);
			vaddr--;
			fallthrough;

		case CSR_LEFT_1:
			*vaddr = (dregs->bpack_hi & 0xff00) >> 8;
			break;
		}
	}
#else
	// check to empty the fifo on a read
	if(!write_flag) {
		int tmo = 20000; /* .2 sec */
		
		while(1) {
			if(dregs->csr & CSR_FIFO_EMPTY)
				break;

			if(--tmo <= 0) {
				printk("sun3scsi: fifo failed to empty!\n");
				return 1;
			}
			udelay(10);
		}
	}

	dregs->udc_addr = 0x32;
	udelay(SUN3_DMA_DELAY);
	count = 2 * dregs->udc_data;
	udelay(SUN3_DMA_DELAY);

	fifo = dregs->fifo_count;
	last_residual = fifo;

	/* empty bytes from the fifo which didn't make it */
	if((!write_flag) && (count - fifo) == 2) {
		unsigned short data;
		unsigned char *vaddr;

		data = dregs->fifo_data;
		vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
		
		vaddr += (sun3_dma_orig_count - fifo);

		vaddr[-2] = (data & 0xff00) >> 8;
		vaddr[-1] = (data & 0xff);
	}
#endif

	dvma_unmap(sun3_dma_orig_addr);
	sun3_dma_orig_addr = NULL;

#ifdef SUN3_SCSI_VME
	dregs->dma_addr_hi = 0;
	dregs->dma_addr_lo = 0;
	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;

	dregs->fifo_count = 0;
	dregs->fifo_count_hi = 0;

	dregs->csr &= ~CSR_SEND;
/*	dregs->csr |= CSR_DMA_ENABLE; */
#else
	sun3_udc_write(UDC_RESET, UDC_CSR);
	dregs->fifo_count = 0;
	dregs->csr &= ~CSR_SEND;

	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
#endif
	
	sun3_dma_setup_done = NULL;

	return ret;

}
	
#include "NCR5380.c"

#ifdef SUN3_SCSI_VME
#define SUN3_SCSI_NAME          "Sun3 NCR5380 VME SCSI"
#define DRV_MODULE_NAME         "sun3_scsi_vme"
#else
#define SUN3_SCSI_NAME          "Sun3 NCR5380 SCSI"
#define DRV_MODULE_NAME         "sun3_scsi"
#endif

#define PFX                     DRV_MODULE_NAME ": "

static struct scsi_host_template sun3_scsi_template = {
	.module			= THIS_MODULE,
	.proc_name		= DRV_MODULE_NAME,
	.name			= SUN3_SCSI_NAME,
	.info			= sun3scsi_info,
	.queuecommand		= sun3scsi_queue_command,
	.eh_abort_handler	= sun3scsi_abort,
	.eh_host_reset_handler	= sun3scsi_host_reset,
	.can_queue		= 16,
	.this_id		= 7,
	.sg_tablesize		= 1,
	.cmd_per_lun		= 2,
	.dma_boundary		= PAGE_SIZE - 1,
	.cmd_size		= NCR5380_CMD_SIZE,
};

static int __init sun3_scsi_probe(struct platform_device *pdev)
{
	struct Scsi_Host *instance;
	struct NCR5380_hostdata *hostdata;
	int error;
	struct resource *irq, *mem;
	void __iomem *ioaddr;
	int host_flags = 0;
#ifdef SUN3_SCSI_VME
	int i;
#endif

	if (setup_can_queue > 0)
		sun3_scsi_template.can_queue = setup_can_queue;
	if (setup_cmd_per_lun > 0)
		sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
	if (setup_sg_tablesize > 0)
		sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
	if (setup_hostid >= 0)
		sun3_scsi_template.this_id = setup_hostid & 7;

#ifdef SUN3_SCSI_VME
	ioaddr = NULL;
	for (i = 0; i < 2; i++) {
		unsigned char x;

		irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
		if (!irq || !mem)
			break;

		ioaddr = sun3_ioremap(mem->start, resource_size(mem),
		                      SUN3_PAGE_TYPE_VME16);
		dregs = (struct sun3_dma_regs *)(ioaddr + 8);

		if (sun3_map_test((unsigned long)dregs, &x)) {
			unsigned short oldcsr;

			oldcsr = dregs->csr;
			dregs->csr = 0;
			udelay(SUN3_DMA_DELAY);
			if (dregs->csr == 0x1400)
				break;

			dregs->csr = oldcsr;
		}

		iounmap(ioaddr);
		ioaddr = NULL;
	}
	if (!ioaddr)
		return -ENODEV;
#else
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!irq || !mem)
		return -ENODEV;

	ioaddr = ioremap(mem->start, resource_size(mem));
	dregs = (struct sun3_dma_regs *)(ioaddr + 8);

	udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
	if (!udc_regs) {
		pr_err(PFX "couldn't allocate DVMA memory!\n");
		iounmap(ioaddr);
		return -ENOMEM;
	}
#endif

	instance = scsi_host_alloc(&sun3_scsi_template,
	                           sizeof(struct NCR5380_hostdata));
	if (!instance) {
		error = -ENOMEM;
		goto fail_alloc;
	}

	instance->irq = irq->start;

	hostdata = shost_priv(instance);
	hostdata->base = mem->start;
	hostdata->io = ioaddr;

	error = NCR5380_init(instance, host_flags);
	if (error)
		goto fail_init;

	error = request_irq(instance->irq, scsi_sun3_intr, 0,
	                    "NCR5380", instance);
	if (error) {
		pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
		       instance->host_no, instance->irq);
		goto fail_irq;
	}

	dregs->csr = 0;
	udelay(SUN3_DMA_DELAY);
	dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
	udelay(SUN3_DMA_DELAY);
	dregs->fifo_count = 0;
#ifdef SUN3_SCSI_VME
	dregs->fifo_count_hi = 0;
	dregs->dma_addr_hi = 0;
	dregs->dma_addr_lo = 0;
	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;

	dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
#endif

	NCR5380_maybe_reset_bus(instance);

	error = scsi_add_host(instance, NULL);
	if (error)
		goto fail_host;

	platform_set_drvdata(pdev, instance);

	scsi_scan_host(instance);
	return 0;

fail_host:
	free_irq(instance->irq, instance);
fail_irq:
	NCR5380_exit(instance);
fail_init:
	scsi_host_put(instance);
fail_alloc:
	if (udc_regs)
		dvma_free(udc_regs);
	iounmap(ioaddr);
	return error;
}

static int __exit sun3_scsi_remove(struct platform_device *pdev)
{
	struct Scsi_Host *instance = platform_get_drvdata(pdev);
	struct NCR5380_hostdata *hostdata = shost_priv(instance);
	void __iomem *ioaddr = hostdata->io;

	scsi_remove_host(instance);
	free_irq(instance->irq, instance);
	NCR5380_exit(instance);
	scsi_host_put(instance);
	if (udc_regs)
		dvma_free(udc_regs);
	iounmap(ioaddr);
	return 0;
}

static struct platform_driver sun3_scsi_driver = {
	.remove = __exit_p(sun3_scsi_remove),
	.driver = {
		.name	= DRV_MODULE_NAME,
	},
};

module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);

MODULE_ALIAS("platform:" DRV_MODULE_NAME);
MODULE_LICENSE("GPL");
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
1da177e4 LT	2	/*
	3	* Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
	4	*
	5	* Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
	6	*
757f5bad FT	7	* VME support added by Sam Creasey
	8	*
	9	* TODO: modify this driver to support multiple Sun3 SCSI VME boards
	10	*
1da177e4 LT	11	* Adapted from mac_scsinew.c:
	12	*/
	13	/*
	14	* Generic Macintosh NCR5380 driver
	15	*
	16	* Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
	17	*
	18	* derived in part from:
	19	*/
	20	/*
	21	* Generic Generic NCR5380 driver
	22	*
	23	* Copyright 1995, Russell King
1da177e4 LT	24	*/
1da177e4 LT	25
1da177e4	26	#include <linux/types.h>
1da177e4	27	#include <linux/delay.h>
1da177e4	28	#include <linux/module.h>
1da177e4 LT	29	#include <linux/ioport.h>
	30	#include <linux/init.h>
	31	#include <linux/blkdev.h>
0d31f875	32	#include <linux/platform_device.h>
1da177e4 LT	33
1da177e4 LT	34	#include <asm/io.h>
1da177e4	35	#include <asm/dvma.h>
1da177e4	36
1da177e4	37	#include <scsi/scsi_host.h>
1da177e4	38
8dad0c51 FT	39	/* minimum number of bytes to do dma on */
8dad0c51 FT	40	#define DMA_MIN_SIZE 129
1da177e4	41
e63449c4 FT	42	/* Definitions for the core NCR5380 driver. */
e63449c4 FT	43
2231ef87 FT	44	#define NCR5380_implementation_fields /* none */
2231ef87 FT	45
61e1ce58 FT	46	#define NCR5380_read(reg) in_8(hostdata->io + (reg))
61e1ce58 FT	47	#define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
2231ef87 FT	48
2231ef87 FT	49	#define NCR5380_queue_command sun3scsi_queue_command
12e5fc66	50	#define NCR5380_host_reset sun3scsi_host_reset
2231ef87	51	#define NCR5380_abort sun3scsi_abort
2231ef87 FT	52	#define NCR5380_info sun3scsi_info
2231ef87 FT	53
4a98f896 FT	54	#define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
	55	#define NCR5380_dma_recv_setup sun3scsi_dma_count
	56	#define NCR5380_dma_send_setup sun3scsi_dma_count
	57	#define NCR5380_dma_residual sun3scsi_dma_residual
2231ef87 FT	58
	59	#include "NCR5380.h"
	60
14d739f6 FT	61	/* dma regs start at regbase + 8, directly after the NCR regs */
	62	struct sun3_dma_regs {
	63	unsigned short dma_addr_hi; /* vme only */
	64	unsigned short dma_addr_lo; /* vme only */
	65	unsigned short dma_count_hi; /* vme only */
	66	unsigned short dma_count_lo; /* vme only */
	67	unsigned short udc_data; /* udc dma data reg (obio only) */
	68	unsigned short udc_addr; /* uda dma addr reg (obio only) */
	69	unsigned short fifo_data; /* fifo data reg,
	70	* holds extra byte on odd dma reads
	71	*/
	72	unsigned short fifo_count;
	73	unsigned short csr; /* control/status reg */
	74	unsigned short bpack_hi; /* vme only */
	75	unsigned short bpack_lo; /* vme only */
	76	unsigned short ivect; /* vme only */
	77	unsigned short fifo_count_hi; /* vme only */
	78	};
	79
	80	/* ucd chip specific regs - live in dvma space */
	81	struct sun3_udc_regs {
	82	unsigned short rsel; /* select regs to load */
	83	unsigned short addr_hi; /* high word of addr */
	84	unsigned short addr_lo; /* low word */
	85	unsigned short count; /* words to be xfer'd */
	86	unsigned short mode_hi; /* high word of channel mode */
	87	unsigned short mode_lo; /* low word of channel mode */
	88	};
	89
	90	/* addresses of the udc registers */
	91	#define UDC_MODE 0x38
	92	#define UDC_CSR 0x2e /* command/status */
	93	#define UDC_CHN_HI 0x26 /* chain high word */
	94	#define UDC_CHN_LO 0x22 /* chain lo word */
	95	#define UDC_CURA_HI 0x1a /* cur reg A high */
	96	#define UDC_CURA_LO 0x0a /* cur reg A low */
	97	#define UDC_CURB_HI 0x12 /* cur reg B high */
	98	#define UDC_CURB_LO 0x02 /* cur reg B low */
	99	#define UDC_MODE_HI 0x56 /* mode reg high */
	100	#define UDC_MODE_LO 0x52 /* mode reg low */
	101	#define UDC_COUNT 0x32 /* words to xfer */
	102
	103	/* some udc commands */
	104	#define UDC_RESET 0
	105	#define UDC_CHN_START 0xa0 /* start chain */
	106	#define UDC_INT_ENABLE 0x32 /* channel 1 int on */
	107
	108	/* udc mode words */
	109	#define UDC_MODE_HIWORD 0x40
	110	#define UDC_MODE_LSEND 0xc2
	111	#define UDC_MODE_LRECV 0xd2
	112
	113	/* udc reg selections */
	114	#define UDC_RSEL_SEND 0x282
	115	#define UDC_RSEL_RECV 0x182
	116
	117	/* bits in csr reg */
	118	#define CSR_DMA_ACTIVE 0x8000
	119	#define CSR_DMA_CONFLICT 0x4000
	120	#define CSR_DMA_BUSERR 0x2000
	121
	122	#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
	123	#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
	124	#define CSR_DMA_INT 0x100 /* dma interrupt pending */
125
126	#define CSR_LEFT 0xc0
127	#define CSR_LEFT_3 0xc0
128	#define CSR_LEFT_2 0x80
129	#define CSR_LEFT_1 0x40
130	#define CSR_PACK_ENABLE 0x20
131
132	#define CSR_DMA_ENABLE 0x10
133
134	#define CSR_SEND 0x8 /* 1 = send 0 = recv */
135	#define CSR_FIFO 0x2 /* reset fifo */
136	#define CSR_INTR 0x4 /* interrupt enable */
137	#define CSR_SCSI 0x1
138
139	#define VME_DATA24 0x3d00
2231ef87 FT	140
	141	extern int sun3_map_test(unsigned long, char *);
	142
1da177e4 LT	143	static int setup_can_queue = -1;
	144	module_param(setup_can_queue, int, 0);
	145	static int setup_cmd_per_lun = -1;
	146	module_param(setup_cmd_per_lun, int, 0);
	147	static int setup_sg_tablesize = -1;
	148	module_param(setup_sg_tablesize, int, 0);
1da177e4 LT	149	static int setup_hostid = -1;
	150	module_param(setup_hostid, int, 0);
	151
1da177e4 LT	152	/* ms to wait after hitting dma regs */
	153	#define SUN3_DMA_DELAY 10
	154
	155	/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
	156	#define SUN3_DVMA_BUFSIZE 0xe000
	157
2231ef87	158	static struct scsi_cmnd *sun3_dma_setup_done;
1da177e4	159	static volatile struct sun3_dma_regs *dregs;
0d31f875	160	static struct sun3_udc_regs *udc_regs;
d5f7e65d FT	161	static unsigned char *sun3_dma_orig_addr;
	162	static unsigned long sun3_dma_orig_count;
	163	static int sun3_dma_active;
	164	static unsigned long last_residual;
1da177e4	165
757f5bad	166	#ifndef SUN3_SCSI_VME
1da177e4 LT	167	/* dma controller register access functions */
	168
	169	static inline unsigned short sun3_udc_read(unsigned char reg)
	170	{
	171	unsigned short ret;
	172
	173	dregs->udc_addr = UDC_CSR;
	174	udelay(SUN3_DMA_DELAY);
	175	ret = dregs->udc_data;
	176	udelay(SUN3_DMA_DELAY);
	177
	178	return ret;
	179	}
	180
	181	static inline void sun3_udc_write(unsigned short val, unsigned char reg)
	182	{
	183	dregs->udc_addr = reg;
	184	udelay(SUN3_DMA_DELAY);
	185	dregs->udc_data = val;
	186	udelay(SUN3_DMA_DELAY);
	187	}
757f5bad	188	#endif
1da177e4	189
1da177e4 LT	190	// safe bits for the CSR
	191	#define CSR_GOOD 0x060f
	192
cd46140a	193	static irqreturn_t scsi_sun3_intr(int irq, void *dev)
1da177e4	194	{
cd46140a	195	struct Scsi_Host *instance = dev;
1da177e4 LT	196	unsigned short csr = dregs->csr;
	197	int handled = 0;
	198
757f5bad FT	199	#ifdef SUN3_SCSI_VME
	200	dregs->csr &= ~CSR_DMA_ENABLE;
	201	#endif
	202
1da177e4	203	if(csr & ~CSR_GOOD) {
cd46140a FT	204	if (csr & CSR_DMA_BUSERR)
	205	shost_printk(KERN_ERR, instance, "bus error in DMA\n");
	206	if (csr & CSR_DMA_CONFLICT)
	207	shost_printk(KERN_ERR, instance, "DMA conflict\n");
1da177e4 LT	208	handled = 1;
	209	}
	210
	211	if(csr & (CSR_SDB_INT \| CSR_DMA_INT)) {
cd46140a	212	NCR5380_intr(irq, dev);
1da177e4 LT	213	handled = 1;
	214	}
	215
	216	return IRQ_RETVAL(handled);
	217	}
	218
1da177e4	219	/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
4a98f896 FT	220	static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
4a98f896 FT	221	unsigned char *data, int count, int write_flag)
1da177e4	222	{
1da177e4 LT	223	void *addr;
	224
	225	if(sun3_dma_orig_addr != NULL)
	226	dvma_unmap(sun3_dma_orig_addr);
	227
757f5bad FT	228	#ifdef SUN3_SCSI_VME
	229	addr = (void *)dvma_map_vme((unsigned long) data, count);
	230	#else
1da177e4	231	addr = (void *)dvma_map((unsigned long) data, count);
757f5bad	232	#endif
1da177e4 LT	233
	234	sun3_dma_orig_addr = addr;
	235	sun3_dma_orig_count = count;
757f5bad FT	236
757f5bad FT	237	#ifndef SUN3_SCSI_VME
1da177e4 LT	238	dregs->fifo_count = 0;
	239	sun3_udc_write(UDC_RESET, UDC_CSR);
	240
	241	/* reset fifo */
	242	dregs->csr &= ~CSR_FIFO;
	243	dregs->csr \|= CSR_FIFO;
757f5bad	244	#endif
1da177e4 LT	245
	246	/* set direction */
	247	if(write_flag)
	248	dregs->csr \|= CSR_SEND;
	249	else
	250	dregs->csr &= ~CSR_SEND;
	251
757f5bad FT	252	#ifdef SUN3_SCSI_VME
	253	dregs->csr \|= CSR_PACK_ENABLE;
	254
	255	dregs->dma_addr_hi = ((unsigned long)addr >> 16);
	256	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
	257
	258	dregs->dma_count_hi = 0;
	259	dregs->dma_count_lo = 0;
	260	dregs->fifo_count_hi = 0;
	261	dregs->fifo_count = 0;
	262	#else
1da177e4 LT	263	/* byte count for fifo */
	264	dregs->fifo_count = count;
	265
	266	sun3_udc_write(UDC_RESET, UDC_CSR);
	267
	268	/* reset fifo */
	269	dregs->csr &= ~CSR_FIFO;
	270	dregs->csr \|= CSR_FIFO;
	271
	272	if(dregs->fifo_count != count) {
4a98f896 FT	273	shost_printk(KERN_ERR, hostdata->host,
4a98f896 FT	274	"FIFO mismatch %04x not %04x\n",
cd46140a	275	dregs->fifo_count, (unsigned int) count);
4a98f896	276	NCR5380_dprint(NDEBUG_DMA, hostdata->host);
1da177e4 LT	277	}
	278
	279	/* setup udc */
1da177e4 LT	280	udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
1da177e4 LT	281	udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
1da177e4 LT	282	udc_regs->count = count/2; /* count in words */
	283	udc_regs->mode_hi = UDC_MODE_HIWORD;
	284	if(write_flag) {
	285	if(count & 1)
	286	udc_regs->count++;
	287	udc_regs->mode_lo = UDC_MODE_LSEND;
	288	udc_regs->rsel = UDC_RSEL_SEND;
	289	} else {
	290	udc_regs->mode_lo = UDC_MODE_LRECV;
	291	udc_regs->rsel = UDC_RSEL_RECV;
	292	}
	293
	294	/* announce location of regs block */
	295	sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
	296	UDC_CHN_HI);
	297
	298	sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
	299
	300	/* set dma master on */
	301	sun3_udc_write(0xd, UDC_MODE);
	302
	303	/* interrupt enable */
	304	sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
757f5bad	305	#endif
1da177e4 LT	306
	307	return count;
	308
	309	}
	310
4a98f896 FT	311	static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
	312	unsigned char *data, int count)
	313	{
	314	return count;
	315	}
	316
	317	static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
	318	unsigned char *data, int count)
	319	{
	320	return sun3scsi_dma_setup(hostdata, data, count, 0);
	321	}
	322
	323	static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
	324	unsigned char *data, int count)
	325	{
	326	return sun3scsi_dma_setup(hostdata, data, count, 1);
	327	}
	328
	329	static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
1da177e4 LT	330	{
	331	return last_residual;
	332	}
	333
4a98f896 FT	334	static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
4a98f896 FT	335	struct scsi_cmnd *cmd)
1da177e4	336	{
4a98f896 FT	337	int wanted_len = cmd->SCp.this_residual;
4a98f896 FT	338
57292b58	339	if (wanted_len < DMA_MIN_SIZE \|\| blk_rq_is_passthrough(cmd->request))
1da177e4	340	return 0;
e63449c4 FT	341
e63449c4 FT	342	return wanted_len;
1da177e4 LT	343	}
	344
	345	static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
	346	{
757f5bad FT	347	#ifdef SUN3_SCSI_VME
	348	unsigned short csr;
	349
	350	csr = dregs->csr;
	351
	352	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
	353	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
1da177e4	354
757f5bad FT	355	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
	356	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
	357
	358	/* if(!(csr & CSR_DMA_ENABLE))
	359	* dregs->csr \|= CSR_DMA_ENABLE;
	360	*/
	361	#else
1da177e4	362	sun3_udc_write(UDC_CHN_START, UDC_CSR);
757f5bad	363	#endif
1da177e4 LT	364
	365	return 0;
	366	}
	367
	368	/* clean up after our dma is done */
	369	static int sun3scsi_dma_finish(int write_flag)
	370	{
757f5bad	371	unsigned short __maybe_unused count;
1da177e4 LT	372	unsigned short fifo;
	373	int ret = 0;
	374
	375	sun3_dma_active = 0;
757f5bad FT	376
	377	#ifdef SUN3_SCSI_VME
	378	dregs->csr &= ~CSR_DMA_ENABLE;
	379
	380	fifo = dregs->fifo_count;
	381	if (write_flag) {
	382	if ((fifo > 0) && (fifo < sun3_dma_orig_count))
	383	fifo++;
	384	}
	385
	386	last_residual = fifo;
	387	/* empty bytes from the fifo which didn't make it */
	388	if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
	389	unsigned char *vaddr;
	390
	391	vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
	392
	393	vaddr += (sun3_dma_orig_count - fifo);
	394	vaddr--;
	395
	396	switch (dregs->csr & CSR_LEFT) {
	397	case CSR_LEFT_3:
	398	*vaddr = (dregs->bpack_lo & 0xff00) >> 8;
	399	vaddr--;
df561f66	400	fallthrough;
757f5bad FT	401
	402	case CSR_LEFT_2:
	403	*vaddr = (dregs->bpack_hi & 0x00ff);
	404	vaddr--;
df561f66	405	fallthrough;
757f5bad FT	406
	407	case CSR_LEFT_1:
	408	*vaddr = (dregs->bpack_hi & 0xff00) >> 8;
	409	break;
	410	}
	411	}
	412	#else
1da177e4 LT	413	// check to empty the fifo on a read
	414	if(!write_flag) {
	415	int tmo = 20000; /* .2 sec */
	416
	417	while(1) {
	418	if(dregs->csr & CSR_FIFO_EMPTY)
	419	break;
	420
	421	if(--tmo <= 0) {
	422	printk("sun3scsi: fifo failed to empty!\n");
	423	return 1;
	424	}
	425	udelay(10);
	426	}
	427	}
1da177e4	428
cd46140a FT	429	dregs->udc_addr = 0x32;
	430	udelay(SUN3_DMA_DELAY);
	431	count = 2 * dregs->udc_data;
	432	udelay(SUN3_DMA_DELAY);
1da177e4 LT	433
	434	fifo = dregs->fifo_count;
	435	last_residual = fifo;
	436
	437	/* empty bytes from the fifo which didn't make it */
	438	if((!write_flag) && (count - fifo) == 2) {
	439	unsigned short data;
	440	unsigned char *vaddr;
	441
	442	data = dregs->fifo_data;
	443	vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
	444
	445	vaddr += (sun3_dma_orig_count - fifo);
	446
	447	vaddr[-2] = (data & 0xff00) >> 8;
	448	vaddr[-1] = (data & 0xff);
	449	}
757f5bad	450	#endif
1da177e4 LT	451
	452	dvma_unmap(sun3_dma_orig_addr);
	453	sun3_dma_orig_addr = NULL;
757f5bad FT	454
	455	#ifdef SUN3_SCSI_VME
	456	dregs->dma_addr_hi = 0;
	457	dregs->dma_addr_lo = 0;
	458	dregs->dma_count_hi = 0;
	459	dregs->dma_count_lo = 0;
	460
	461	dregs->fifo_count = 0;
	462	dregs->fifo_count_hi = 0;
	463
	464	dregs->csr &= ~CSR_SEND;
	465	/* dregs->csr \|= CSR_DMA_ENABLE; */
	466	#else
1da177e4 LT	467	sun3_udc_write(UDC_RESET, UDC_CSR);
	468	dregs->fifo_count = 0;
	469	dregs->csr &= ~CSR_SEND;
	470
	471	/* reset fifo */
	472	dregs->csr &= ~CSR_FIFO;
	473	dregs->csr \|= CSR_FIFO;
757f5bad	474	#endif
1da177e4 LT	475
	476	sun3_dma_setup_done = NULL;
	477
	478	return ret;
	479
	480	}
	481
e9db3198	482	#include "NCR5380.c"
1da177e4	483
0d31f875 FT	484	#ifdef SUN3_SCSI_VME
	485	#define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
	486	#define DRV_MODULE_NAME "sun3_scsi_vme"
	487	#else
	488	#define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
	489	#define DRV_MODULE_NAME "sun3_scsi"
	490	#endif
	491
	492	#define PFX DRV_MODULE_NAME ": "
	493
	494	static struct scsi_host_template sun3_scsi_template = {
	495	.module = THIS_MODULE,
	496	.proc_name = DRV_MODULE_NAME,
1da177e4	497	.name = SUN3_SCSI_NAME,
1da177e4 LT	498	.info = sun3scsi_info,
1da177e4 LT	499	.queuecommand = sun3scsi_queue_command,
aa2e2cb1	500	.eh_abort_handler = sun3scsi_abort,
12e5fc66	501	.eh_host_reset_handler = sun3scsi_host_reset,
d572f65f	502	.can_queue = 16,
1da177e4	503	.this_id = 7,
79172ab2	504	.sg_tablesize = 1,
d572f65f	505	.cmd_per_lun = 2,
4af14d11	506	.dma_boundary = PAGE_SIZE - 1,
32b26a10	507	.cmd_size = NCR5380_CMD_SIZE,
1da177e4 LT	508	};
1da177e4 LT	509
0d31f875 FT	510	static int __init sun3_scsi_probe(struct platform_device *pdev)
	511	{
	512	struct Scsi_Host *instance;
820682b1	513	struct NCR5380_hostdata *hostdata;
0d31f875 FT	514	int error;
0d31f875 FT	515	struct resource irq, mem;
61e1ce58	516	void __iomem *ioaddr;
ca513fc9	517	int host_flags = 0;
0d31f875 FT	518	#ifdef SUN3_SCSI_VME
	519	int i;
	520	#endif
	521
	522	if (setup_can_queue > 0)
	523	sun3_scsi_template.can_queue = setup_can_queue;
	524	if (setup_cmd_per_lun > 0)
	525	sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
79172ab2	526	if (setup_sg_tablesize > 0)
0d31f875 FT	527	sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
	528	if (setup_hostid >= 0)
	529	sun3_scsi_template.this_id = setup_hostid & 7;
	530
0d31f875 FT	531	#ifdef SUN3_SCSI_VME
	532	ioaddr = NULL;
	533	for (i = 0; i < 2; i++) {
	534	unsigned char x;
	535
	536	irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	537	mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
	538	if (!irq \|\| !mem)
	539	break;
	540
	541	ioaddr = sun3_ioremap(mem->start, resource_size(mem),
	542	SUN3_PAGE_TYPE_VME16);
	543	dregs = (struct sun3_dma_regs *)(ioaddr + 8);
	544
	545	if (sun3_map_test((unsigned long)dregs, &x)) {
	546	unsigned short oldcsr;
	547
	548	oldcsr = dregs->csr;
	549	dregs->csr = 0;
	550	udelay(SUN3_DMA_DELAY);
	551	if (dregs->csr == 0x1400)
	552	break;
	553
	554	dregs->csr = oldcsr;
	555	}
	556
	557	iounmap(ioaddr);
	558	ioaddr = NULL;
	559	}
	560	if (!ioaddr)
	561	return -ENODEV;
	562	#else
	563	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	564	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	565	if (!irq \|\| !mem)
	566	return -ENODEV;
	567
	568	ioaddr = ioremap(mem->start, resource_size(mem));
	569	dregs = (struct sun3_dma_regs *)(ioaddr + 8);
	570
	571	udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
	572	if (!udc_regs) {
	573	pr_err(PFX "couldn't allocate DVMA memory!\n");
	574	iounmap(ioaddr);
	575	return -ENOMEM;
	576	}
	577	#endif
	578
0d31f875 FT	579	instance = scsi_host_alloc(&sun3_scsi_template,
	580	sizeof(struct NCR5380_hostdata));
	581	if (!instance) {
	582	error = -ENOMEM;
	583	goto fail_alloc;
	584	}
0d31f875	585
0d31f875 FT	586	instance->irq = irq->start;
0d31f875 FT	587
820682b1	588	hostdata = shost_priv(instance);
61e1ce58 FT	589	hostdata->base = mem->start;
61e1ce58 FT	590	hostdata->io = ioaddr;
820682b1	591
0ad0eff9 FT	592	error = NCR5380_init(instance, host_flags);
	593	if (error)
	594	goto fail_init;
0d31f875 FT	595
	596	error = request_irq(instance->irq, scsi_sun3_intr, 0,
	597	"NCR5380", instance);
	598	if (error) {
0d31f875 FT	599	pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
	600	instance->host_no, instance->irq);
	601	goto fail_irq;
0d31f875 FT	602	}
	603
	604	dregs->csr = 0;
	605	udelay(SUN3_DMA_DELAY);
	606	dregs->csr = CSR_SCSI \| CSR_FIFO \| CSR_INTR;
	607	udelay(SUN3_DMA_DELAY);
	608	dregs->fifo_count = 0;
	609	#ifdef SUN3_SCSI_VME
	610	dregs->fifo_count_hi = 0;
	611	dregs->dma_addr_hi = 0;
	612	dregs->dma_addr_lo = 0;
	613	dregs->dma_count_hi = 0;
	614	dregs->dma_count_lo = 0;
	615
	616	dregs->ivect = VME_DATA24 \| (instance->irq & 0xff);
	617	#endif
	618
9c3f0e2b	619	NCR5380_maybe_reset_bus(instance);
0d31f875 FT	620
	621	error = scsi_add_host(instance, NULL);
	622	if (error)
	623	goto fail_host;
	624
	625	platform_set_drvdata(pdev, instance);
	626
	627	scsi_scan_host(instance);
	628	return 0;
	629
	630	fail_host:
e4dec680	631	free_irq(instance->irq, instance);
0d31f875 FT	632	fail_irq:
0d31f875 FT	633	NCR5380_exit(instance);
0ad0eff9	634	fail_init:
0d31f875 FT	635	scsi_host_put(instance);
	636	fail_alloc:
	637	if (udc_regs)
	638	dvma_free(udc_regs);
61e1ce58	639	iounmap(ioaddr);
0d31f875 FT	640	return error;
	641	}
	642
	643	static int __exit sun3_scsi_remove(struct platform_device *pdev)
	644	{
	645	struct Scsi_Host *instance = platform_get_drvdata(pdev);
61e1ce58 FT	646	struct NCR5380_hostdata *hostdata = shost_priv(instance);
61e1ce58 FT	647	void __iomem *ioaddr = hostdata->io;
0d31f875 FT	648
0d31f875 FT	649	scsi_remove_host(instance);
e4dec680	650	free_irq(instance->irq, instance);
0d31f875 FT	651	NCR5380_exit(instance);
	652	scsi_host_put(instance);
	653	if (udc_regs)
	654	dvma_free(udc_regs);
61e1ce58	655	iounmap(ioaddr);
0d31f875 FT	656	return 0;
	657	}
	658
	659	static struct platform_driver sun3_scsi_driver = {
	660	.remove = __exit_p(sun3_scsi_remove),
	661	.driver = {
	662	.name = DRV_MODULE_NAME,
0d31f875 FT	663	},
0d31f875 FT	664	};
1da177e4	665
0d31f875	666	module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
1da177e4	667
0d31f875	668	MODULE_ALIAS("platform:" DRV_MODULE_NAME);
1da177e4	669	MODULE_LICENSE("GPL");