[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / sun3_scsi.c

/*
 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
 *
 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
 *
 * VME support added by Sam Creasey
 *
 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
 *
 * Adapted from mac_scsinew.c:
 */
/*
 * Generic Macintosh NCR5380 driver
 *
 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
 *
 * derived in part from:
 */
/*
 * Generic Generic NCR5380 driver
 *
 * Copyright 1995, Russell King
 */

#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/platform_device.h>

#include <asm/io.h>
#include <asm/dvma.h>

#include <scsi/scsi_host.h>

/* minimum number of bytes to do dma on */
#define DMA_MIN_SIZE                    129

/* Definitions for the core NCR5380 driver. */

#define NCR5380_implementation_fields   /* none */

#define NCR5380_read(reg)               in_8(hostdata->io + (reg))
#define NCR5380_write(reg, value)       out_8(hostdata->io + (reg), value)

#define NCR5380_queue_command           sun3scsi_queue_command
#define NCR5380_host_reset              sun3scsi_host_reset
#define NCR5380_abort                   sun3scsi_abort
#define NCR5380_info                    sun3scsi_info

#define NCR5380_dma_xfer_len            sun3scsi_dma_xfer_len
#define NCR5380_dma_recv_setup          sun3scsi_dma_count
#define NCR5380_dma_send_setup          sun3scsi_dma_count
#define NCR5380_dma_residual            sun3scsi_dma_residual

#include "NCR5380.h"

/* dma regs start at regbase + 8, directly after the NCR regs */
struct sun3_dma_regs {
	unsigned short dma_addr_hi; /* vme only */
	unsigned short dma_addr_lo; /* vme only */
	unsigned short dma_count_hi; /* vme only */
	unsigned short dma_count_lo; /* vme only */
	unsigned short udc_data; /* udc dma data reg (obio only) */
	unsigned short udc_addr; /* uda dma addr reg (obio only) */
	unsigned short fifo_data; /* fifo data reg,
	                           * holds extra byte on odd dma reads
	                           */
	unsigned short fifo_count;
	unsigned short csr; /* control/status reg */
	unsigned short bpack_hi; /* vme only */
	unsigned short bpack_lo; /* vme only */
	unsigned short ivect; /* vme only */
	unsigned short fifo_count_hi; /* vme only */
};

/* ucd chip specific regs - live in dvma space */
struct sun3_udc_regs {
	unsigned short rsel; /* select regs to load */
	unsigned short addr_hi; /* high word of addr */
	unsigned short addr_lo; /* low word */
	unsigned short count; /* words to be xfer'd */
	unsigned short mode_hi; /* high word of channel mode */
	unsigned short mode_lo; /* low word of channel mode */
};

/* addresses of the udc registers */
#define UDC_MODE 0x38
#define UDC_CSR 0x2e /* command/status */
#define UDC_CHN_HI 0x26 /* chain high word */
#define UDC_CHN_LO 0x22 /* chain lo word */
#define UDC_CURA_HI 0x1a /* cur reg A high */
#define UDC_CURA_LO 0x0a /* cur reg A low */
#define UDC_CURB_HI 0x12 /* cur reg B high */
#define UDC_CURB_LO 0x02 /* cur reg B low */
#define UDC_MODE_HI 0x56 /* mode reg high */
#define UDC_MODE_LO 0x52 /* mode reg low */
#define UDC_COUNT 0x32 /* words to xfer */

/* some udc commands */
#define UDC_RESET 0
#define UDC_CHN_START 0xa0 /* start chain */
#define UDC_INT_ENABLE 0x32 /* channel 1 int on */

/* udc mode words */
#define UDC_MODE_HIWORD 0x40
#define UDC_MODE_LSEND 0xc2
#define UDC_MODE_LRECV 0xd2

/* udc reg selections */
#define UDC_RSEL_SEND 0x282
#define UDC_RSEL_RECV 0x182

/* bits in csr reg */
#define CSR_DMA_ACTIVE 0x8000
#define CSR_DMA_CONFLICT 0x4000
#define CSR_DMA_BUSERR 0x2000

#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
#define CSR_DMA_INT 0x100 /* dma interrupt pending */

#define CSR_LEFT 0xc0
#define CSR_LEFT_3 0xc0
#define CSR_LEFT_2 0x80
#define CSR_LEFT_1 0x40
#define CSR_PACK_ENABLE 0x20

#define CSR_DMA_ENABLE 0x10

#define CSR_SEND 0x8 /* 1 = send  0 = recv */
#define CSR_FIFO 0x2 /* reset fifo */
#define CSR_INTR 0x4 /* interrupt enable */
#define CSR_SCSI 0x1

#define VME_DATA24 0x3d00

extern int sun3_map_test(unsigned long, char *);

static int setup_can_queue = -1;
module_param(setup_can_queue, int, 0);
static int setup_cmd_per_lun = -1;
module_param(setup_cmd_per_lun, int, 0);
static int setup_sg_tablesize = -1;
module_param(setup_sg_tablesize, int, 0);
static int setup_hostid = -1;
module_param(setup_hostid, int, 0);

/* ms to wait after hitting dma regs */
#define SUN3_DMA_DELAY 10

/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
#define SUN3_DVMA_BUFSIZE 0xe000

static struct scsi_cmnd *sun3_dma_setup_done;
static volatile struct sun3_dma_regs *dregs;
static struct sun3_udc_regs *udc_regs;
static unsigned char *sun3_dma_orig_addr;
static unsigned long sun3_dma_orig_count;
static int sun3_dma_active;
static unsigned long last_residual;

#ifndef SUN3_SCSI_VME
/* dma controller register access functions */

static inline unsigned short sun3_udc_read(unsigned char reg)
{
	unsigned short ret;

	dregs->udc_addr = UDC_CSR;
	udelay(SUN3_DMA_DELAY);
	ret = dregs->udc_data;
	udelay(SUN3_DMA_DELAY);
	
	return ret;
}

static inline void sun3_udc_write(unsigned short val, unsigned char reg)
{
	dregs->udc_addr = reg;
	udelay(SUN3_DMA_DELAY);
	dregs->udc_data = val;
	udelay(SUN3_DMA_DELAY);
}
#endif

// safe bits for the CSR
#define CSR_GOOD 0x060f

static irqreturn_t scsi_sun3_intr(int irq, void *dev)
{
	struct Scsi_Host *instance = dev;
	unsigned short csr = dregs->csr;
	int handled = 0;

#ifdef SUN3_SCSI_VME
	dregs->csr &= ~CSR_DMA_ENABLE;
#endif

	if(csr & ~CSR_GOOD) {
		if (csr & CSR_DMA_BUSERR)
			shost_printk(KERN_ERR, instance, "bus error in DMA\n");
		if (csr & CSR_DMA_CONFLICT)
			shost_printk(KERN_ERR, instance, "DMA conflict\n");
		handled = 1;
	}

	if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
		NCR5380_intr(irq, dev);
		handled = 1;
	}

	return IRQ_RETVAL(handled);
}

/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
                              unsigned char *data, int count, int write_flag)
{
	void *addr;

	if(sun3_dma_orig_addr != NULL)
		dvma_unmap(sun3_dma_orig_addr);

#ifdef SUN3_SCSI_VME
	addr = (void *)dvma_map_vme((unsigned long) data, count);
#else
	addr = (void *)dvma_map((unsigned long) data, count);
#endif
		
	sun3_dma_orig_addr = addr;
	sun3_dma_orig_count = count;

#ifndef SUN3_SCSI_VME
	dregs->fifo_count = 0;
	sun3_udc_write(UDC_RESET, UDC_CSR);
	
	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
#endif
	
	/* set direction */
	if(write_flag)
		dregs->csr |= CSR_SEND;
	else
		dregs->csr &= ~CSR_SEND;
	
#ifdef SUN3_SCSI_VME
	dregs->csr |= CSR_PACK_ENABLE;

	dregs->dma_addr_hi = ((unsigned long)addr >> 16);
	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);

	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;
	dregs->fifo_count_hi = 0;
	dregs->fifo_count = 0;
#else
	/* byte count for fifo */
	dregs->fifo_count = count;

	sun3_udc_write(UDC_RESET, UDC_CSR);
	
	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
	
	if(dregs->fifo_count != count) { 
		shost_printk(KERN_ERR, hostdata->host,
		             "FIFO mismatch %04x not %04x\n",
		             dregs->fifo_count, (unsigned int) count);
		NCR5380_dprint(NDEBUG_DMA, hostdata->host);
	}

	/* setup udc */
	udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
	udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
	udc_regs->count = count/2; /* count in words */
	udc_regs->mode_hi = UDC_MODE_HIWORD;
	if(write_flag) {
		if(count & 1)
			udc_regs->count++;
		udc_regs->mode_lo = UDC_MODE_LSEND;
		udc_regs->rsel = UDC_RSEL_SEND;
	} else {
		udc_regs->mode_lo = UDC_MODE_LRECV;
		udc_regs->rsel = UDC_RSEL_RECV;
	}
	
	/* announce location of regs block */
	sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
		       UDC_CHN_HI); 

	sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);

	/* set dma master on */
	sun3_udc_write(0xd, UDC_MODE);

	/* interrupt enable */
	sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
#endif
	
       	return count;

}

static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
                              unsigned char *data, int count)
{
	return count;
}

static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
                                          unsigned char *data, int count)
{
	return sun3scsi_dma_setup(hostdata, data, count, 0);
}

static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
                                          unsigned char *data, int count)
{
	return sun3scsi_dma_setup(hostdata, data, count, 1);
}

static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
{
	return last_residual;
}

static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
                                 struct scsi_cmnd *cmd)
{
	int wanted_len = cmd->SCp.this_residual;

	if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request))
		return 0;

	return wanted_len;
}

static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
{
#ifdef SUN3_SCSI_VME
	unsigned short csr;

	csr = dregs->csr;

	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);

	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);

/*	if(!(csr & CSR_DMA_ENABLE))
 *		dregs->csr |= CSR_DMA_ENABLE;
 */
#else
    sun3_udc_write(UDC_CHN_START, UDC_CSR);
#endif
    
    return 0;
}

/* clean up after our dma is done */
static int sun3scsi_dma_finish(int write_flag)
{
	unsigned short __maybe_unused count;
	unsigned short fifo;
	int ret = 0;
	
	sun3_dma_active = 0;

#ifdef SUN3_SCSI_VME
	dregs->csr &= ~CSR_DMA_ENABLE;

	fifo = dregs->fifo_count;
	if (write_flag) {
		if ((fifo > 0) && (fifo < sun3_dma_orig_count))
			fifo++;
	}

	last_residual = fifo;
	/* empty bytes from the fifo which didn't make it */
	if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
		unsigned char *vaddr;

		vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);

		vaddr += (sun3_dma_orig_count - fifo);
		vaddr--;

		switch (dregs->csr & CSR_LEFT) {
		case CSR_LEFT_3:
			*vaddr = (dregs->bpack_lo & 0xff00) >> 8;
			vaddr--;

		case CSR_LEFT_2:
			*vaddr = (dregs->bpack_hi & 0x00ff);
			vaddr--;

		case CSR_LEFT_1:
			*vaddr = (dregs->bpack_hi & 0xff00) >> 8;
			break;
		}
	}
#else
	// check to empty the fifo on a read
	if(!write_flag) {
		int tmo = 20000; /* .2 sec */
		
		while(1) {
			if(dregs->csr & CSR_FIFO_EMPTY)
				break;

			if(--tmo <= 0) {
				printk("sun3scsi: fifo failed to empty!\n");
				return 1;
			}
			udelay(10);
		}
	}

	dregs->udc_addr = 0x32;
	udelay(SUN3_DMA_DELAY);
	count = 2 * dregs->udc_data;
	udelay(SUN3_DMA_DELAY);

	fifo = dregs->fifo_count;
	last_residual = fifo;

	/* empty bytes from the fifo which didn't make it */
	if((!write_flag) && (count - fifo) == 2) {
		unsigned short data;
		unsigned char *vaddr;

		data = dregs->fifo_data;
		vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
		
		vaddr += (sun3_dma_orig_count - fifo);

		vaddr[-2] = (data & 0xff00) >> 8;
		vaddr[-1] = (data & 0xff);
	}
#endif

	dvma_unmap(sun3_dma_orig_addr);
	sun3_dma_orig_addr = NULL;

#ifdef SUN3_SCSI_VME
	dregs->dma_addr_hi = 0;
	dregs->dma_addr_lo = 0;
	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;

	dregs->fifo_count = 0;
	dregs->fifo_count_hi = 0;

	dregs->csr &= ~CSR_SEND;
/*	dregs->csr |= CSR_DMA_ENABLE; */
#else
	sun3_udc_write(UDC_RESET, UDC_CSR);
	dregs->fifo_count = 0;
	dregs->csr &= ~CSR_SEND;

	/* reset fifo */
	dregs->csr &= ~CSR_FIFO;
	dregs->csr |= CSR_FIFO;
#endif
	
	sun3_dma_setup_done = NULL;

	return ret;

}
	
#include "NCR5380.c"

#ifdef SUN3_SCSI_VME
#define SUN3_SCSI_NAME          "Sun3 NCR5380 VME SCSI"
#define DRV_MODULE_NAME         "sun3_scsi_vme"
#else
#define SUN3_SCSI_NAME          "Sun3 NCR5380 SCSI"
#define DRV_MODULE_NAME         "sun3_scsi"
#endif

#define PFX                     DRV_MODULE_NAME ": "

static struct scsi_host_template sun3_scsi_template = {
	.module			= THIS_MODULE,
	.proc_name		= DRV_MODULE_NAME,
	.name			= SUN3_SCSI_NAME,
	.info			= sun3scsi_info,
	.queuecommand		= sun3scsi_queue_command,
	.eh_abort_handler	= sun3scsi_abort,
	.eh_host_reset_handler	= sun3scsi_host_reset,
	.can_queue		= 16,
	.this_id		= 7,
	.sg_tablesize		= SG_NONE,
	.cmd_per_lun		= 2,
	.use_clustering		= DISABLE_CLUSTERING,
	.cmd_size		= NCR5380_CMD_SIZE,
};

static int __init sun3_scsi_probe(struct platform_device *pdev)
{
	struct Scsi_Host *instance;
	struct NCR5380_hostdata *hostdata;
	int error;
	struct resource *irq, *mem;
	void __iomem *ioaddr;
	int host_flags = 0;
#ifdef SUN3_SCSI_VME
	int i;
#endif

	if (setup_can_queue > 0)
		sun3_scsi_template.can_queue = setup_can_queue;
	if (setup_cmd_per_lun > 0)
		sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
	if (setup_sg_tablesize >= 0)
		sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
	if (setup_hostid >= 0)
		sun3_scsi_template.this_id = setup_hostid & 7;

#ifdef SUN3_SCSI_VME
	ioaddr = NULL;
	for (i = 0; i < 2; i++) {
		unsigned char x;

		irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
		if (!irq || !mem)
			break;

		ioaddr = sun3_ioremap(mem->start, resource_size(mem),
		                      SUN3_PAGE_TYPE_VME16);
		dregs = (struct sun3_dma_regs *)(ioaddr + 8);

		if (sun3_map_test((unsigned long)dregs, &x)) {
			unsigned short oldcsr;

			oldcsr = dregs->csr;
			dregs->csr = 0;
			udelay(SUN3_DMA_DELAY);
			if (dregs->csr == 0x1400)
				break;

			dregs->csr = oldcsr;
		}

		iounmap(ioaddr);
		ioaddr = NULL;
	}
	if (!ioaddr)
		return -ENODEV;
#else
	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!irq || !mem)
		return -ENODEV;

	ioaddr = ioremap(mem->start, resource_size(mem));
	dregs = (struct sun3_dma_regs *)(ioaddr + 8);

	udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
	if (!udc_regs) {
		pr_err(PFX "couldn't allocate DVMA memory!\n");
		iounmap(ioaddr);
		return -ENOMEM;
	}
#endif

	instance = scsi_host_alloc(&sun3_scsi_template,
	                           sizeof(struct NCR5380_hostdata));
	if (!instance) {
		error = -ENOMEM;
		goto fail_alloc;
	}

	instance->irq = irq->start;

	hostdata = shost_priv(instance);
	hostdata->base = mem->start;
	hostdata->io = ioaddr;

	error = NCR5380_init(instance, host_flags);
	if (error)
		goto fail_init;

	error = request_irq(instance->irq, scsi_sun3_intr, 0,
	                    "NCR5380", instance);
	if (error) {
		pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
		       instance->host_no, instance->irq);
		goto fail_irq;
	}

	dregs->csr = 0;
	udelay(SUN3_DMA_DELAY);
	dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
	udelay(SUN3_DMA_DELAY);
	dregs->fifo_count = 0;
#ifdef SUN3_SCSI_VME
	dregs->fifo_count_hi = 0;
	dregs->dma_addr_hi = 0;
	dregs->dma_addr_lo = 0;
	dregs->dma_count_hi = 0;
	dregs->dma_count_lo = 0;

	dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
#endif

	NCR5380_maybe_reset_bus(instance);

	error = scsi_add_host(instance, NULL);
	if (error)
		goto fail_host;

	platform_set_drvdata(pdev, instance);

	scsi_scan_host(instance);
	return 0;

fail_host:
	free_irq(instance->irq, instance);
fail_irq:
	NCR5380_exit(instance);
fail_init:
	scsi_host_put(instance);
fail_alloc:
	if (udc_regs)
		dvma_free(udc_regs);
	iounmap(ioaddr);
	return error;
}

static int __exit sun3_scsi_remove(struct platform_device *pdev)
{
	struct Scsi_Host *instance = platform_get_drvdata(pdev);
	struct NCR5380_hostdata *hostdata = shost_priv(instance);
	void __iomem *ioaddr = hostdata->io;

	scsi_remove_host(instance);
	free_irq(instance->irq, instance);
	NCR5380_exit(instance);
	scsi_host_put(instance);
	if (udc_regs)
		dvma_free(udc_regs);
	iounmap(ioaddr);
	return 0;
}

static struct platform_driver sun3_scsi_driver = {
	.remove = __exit_p(sun3_scsi_remove),
	.driver = {
		.name	= DRV_MODULE_NAME,
	},
};

module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);

MODULE_ALIAS("platform:" DRV_MODULE_NAME);
MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
	3	*
	4	* Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
	5	*
757f5bad FT	6	* VME support added by Sam Creasey
	7	*
	8	* TODO: modify this driver to support multiple Sun3 SCSI VME boards
	9	*
1da177e4 LT	10	* Adapted from mac_scsinew.c:
	11	*/
	12	/*
	13	* Generic Macintosh NCR5380 driver
	14	*
	15	* Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
	16	*
	17	* derived in part from:
	18	*/
	19	/*
	20	* Generic Generic NCR5380 driver
	21	*
	22	* Copyright 1995, Russell King
1da177e4 LT	23	*/
1da177e4 LT	24
1da177e4	25	#include <linux/types.h>
1da177e4	26	#include <linux/delay.h>
1da177e4	27	#include <linux/module.h>
1da177e4 LT	28	#include <linux/ioport.h>
	29	#include <linux/init.h>
	30	#include <linux/blkdev.h>
0d31f875	31	#include <linux/platform_device.h>
1da177e4 LT	32
1da177e4 LT	33	#include <asm/io.h>
1da177e4	34	#include <asm/dvma.h>
1da177e4	35
1da177e4	36	#include <scsi/scsi_host.h>
1da177e4	37
8dad0c51 FT	38	/* minimum number of bytes to do dma on */
8dad0c51 FT	39	#define DMA_MIN_SIZE 129
1da177e4	40
e63449c4 FT	41	/* Definitions for the core NCR5380 driver. */
e63449c4 FT	42
2231ef87 FT	43	#define NCR5380_implementation_fields /* none */
2231ef87 FT	44
61e1ce58 FT	45	#define NCR5380_read(reg) in_8(hostdata->io + (reg))
61e1ce58 FT	46	#define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
2231ef87 FT	47
2231ef87 FT	48	#define NCR5380_queue_command sun3scsi_queue_command
12e5fc66	49	#define NCR5380_host_reset sun3scsi_host_reset
2231ef87	50	#define NCR5380_abort sun3scsi_abort
2231ef87 FT	51	#define NCR5380_info sun3scsi_info
2231ef87 FT	52
4a98f896 FT	53	#define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
	54	#define NCR5380_dma_recv_setup sun3scsi_dma_count
	55	#define NCR5380_dma_send_setup sun3scsi_dma_count
	56	#define NCR5380_dma_residual sun3scsi_dma_residual
2231ef87 FT	57
	58	#include "NCR5380.h"
	59
14d739f6 FT	60	/* dma regs start at regbase + 8, directly after the NCR regs */
	61	struct sun3_dma_regs {
	62	unsigned short dma_addr_hi; /* vme only */
	63	unsigned short dma_addr_lo; /* vme only */
	64	unsigned short dma_count_hi; /* vme only */
	65	unsigned short dma_count_lo; /* vme only */
	66	unsigned short udc_data; /* udc dma data reg (obio only) */
	67	unsigned short udc_addr; /* uda dma addr reg (obio only) */
	68	unsigned short fifo_data; /* fifo data reg,
	69	* holds extra byte on odd dma reads
	70	*/
	71	unsigned short fifo_count;
	72	unsigned short csr; /* control/status reg */
	73	unsigned short bpack_hi; /* vme only */
	74	unsigned short bpack_lo; /* vme only */
	75	unsigned short ivect; /* vme only */
	76	unsigned short fifo_count_hi; /* vme only */
	77	};
	78
	79	/* ucd chip specific regs - live in dvma space */
	80	struct sun3_udc_regs {
	81	unsigned short rsel; /* select regs to load */
	82	unsigned short addr_hi; /* high word of addr */
	83	unsigned short addr_lo; /* low word */
	84	unsigned short count; /* words to be xfer'd */
	85	unsigned short mode_hi; /* high word of channel mode */
	86	unsigned short mode_lo; /* low word of channel mode */
	87	};
	88
	89	/* addresses of the udc registers */
	90	#define UDC_MODE 0x38
	91	#define UDC_CSR 0x2e /* command/status */
	92	#define UDC_CHN_HI 0x26 /* chain high word */
	93	#define UDC_CHN_LO 0x22 /* chain lo word */
	94	#define UDC_CURA_HI 0x1a /* cur reg A high */
	95	#define UDC_CURA_LO 0x0a /* cur reg A low */
	96	#define UDC_CURB_HI 0x12 /* cur reg B high */
	97	#define UDC_CURB_LO 0x02 /* cur reg B low */
	98	#define UDC_MODE_HI 0x56 /* mode reg high */
	99	#define UDC_MODE_LO 0x52 /* mode reg low */
	100	#define UDC_COUNT 0x32 /* words to xfer */
	101
	102	/* some udc commands */
	103	#define UDC_RESET 0
	104	#define UDC_CHN_START 0xa0 /* start chain */
	105	#define UDC_INT_ENABLE 0x32 /* channel 1 int on */
	106
	107	/* udc mode words */
	108	#define UDC_MODE_HIWORD 0x40
	109	#define UDC_MODE_LSEND 0xc2
	110	#define UDC_MODE_LRECV 0xd2
	111
	112	/* udc reg selections */
	113	#define UDC_RSEL_SEND 0x282
	114	#define UDC_RSEL_RECV 0x182
	115
	116	/* bits in csr reg */
	117	#define CSR_DMA_ACTIVE 0x8000
	118	#define CSR_DMA_CONFLICT 0x4000
	119	#define CSR_DMA_BUSERR 0x2000
	120
	121	#define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
	122	#define CSR_SDB_INT 0x200 /* sbc interrupt pending */
	123	#define CSR_DMA_INT 0x100 /* dma interrupt pending */
124
125	#define CSR_LEFT 0xc0
126	#define CSR_LEFT_3 0xc0
127	#define CSR_LEFT_2 0x80
128	#define CSR_LEFT_1 0x40
129	#define CSR_PACK_ENABLE 0x20
130
131	#define CSR_DMA_ENABLE 0x10
132
133	#define CSR_SEND 0x8 /* 1 = send 0 = recv */
134	#define CSR_FIFO 0x2 /* reset fifo */
135	#define CSR_INTR 0x4 /* interrupt enable */
136	#define CSR_SCSI 0x1
137
138	#define VME_DATA24 0x3d00
2231ef87 FT	139
	140	extern int sun3_map_test(unsigned long, char *);
	141
1da177e4 LT	142	static int setup_can_queue = -1;
	143	module_param(setup_can_queue, int, 0);
	144	static int setup_cmd_per_lun = -1;
	145	module_param(setup_cmd_per_lun, int, 0);
	146	static int setup_sg_tablesize = -1;
	147	module_param(setup_sg_tablesize, int, 0);
1da177e4 LT	148	static int setup_hostid = -1;
	149	module_param(setup_hostid, int, 0);
	150
1da177e4 LT	151	/* ms to wait after hitting dma regs */
	152	#define SUN3_DMA_DELAY 10
	153
	154	/* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
	155	#define SUN3_DVMA_BUFSIZE 0xe000
	156
2231ef87	157	static struct scsi_cmnd *sun3_dma_setup_done;
1da177e4	158	static volatile struct sun3_dma_regs *dregs;
0d31f875	159	static struct sun3_udc_regs *udc_regs;
d5f7e65d FT	160	static unsigned char *sun3_dma_orig_addr;
	161	static unsigned long sun3_dma_orig_count;
	162	static int sun3_dma_active;
	163	static unsigned long last_residual;
1da177e4	164
757f5bad	165	#ifndef SUN3_SCSI_VME
1da177e4 LT	166	/* dma controller register access functions */
	167
	168	static inline unsigned short sun3_udc_read(unsigned char reg)
	169	{
	170	unsigned short ret;
	171
	172	dregs->udc_addr = UDC_CSR;
	173	udelay(SUN3_DMA_DELAY);
	174	ret = dregs->udc_data;
	175	udelay(SUN3_DMA_DELAY);
	176
	177	return ret;
	178	}
	179
	180	static inline void sun3_udc_write(unsigned short val, unsigned char reg)
	181	{
	182	dregs->udc_addr = reg;
	183	udelay(SUN3_DMA_DELAY);
	184	dregs->udc_data = val;
	185	udelay(SUN3_DMA_DELAY);
	186	}
757f5bad	187	#endif
1da177e4	188
1da177e4 LT	189	// safe bits for the CSR
	190	#define CSR_GOOD 0x060f
	191
cd46140a	192	static irqreturn_t scsi_sun3_intr(int irq, void *dev)
1da177e4	193	{
cd46140a	194	struct Scsi_Host *instance = dev;
1da177e4 LT	195	unsigned short csr = dregs->csr;
	196	int handled = 0;
	197
757f5bad FT	198	#ifdef SUN3_SCSI_VME
	199	dregs->csr &= ~CSR_DMA_ENABLE;
	200	#endif
	201
1da177e4	202	if(csr & ~CSR_GOOD) {
cd46140a FT	203	if (csr & CSR_DMA_BUSERR)
	204	shost_printk(KERN_ERR, instance, "bus error in DMA\n");
	205	if (csr & CSR_DMA_CONFLICT)
	206	shost_printk(KERN_ERR, instance, "DMA conflict\n");
1da177e4 LT	207	handled = 1;
	208	}
	209
	210	if(csr & (CSR_SDB_INT \| CSR_DMA_INT)) {
cd46140a	211	NCR5380_intr(irq, dev);
1da177e4 LT	212	handled = 1;
	213	}
	214
	215	return IRQ_RETVAL(handled);
	216	}
	217
1da177e4	218	/* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
4a98f896 FT	219	static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
4a98f896 FT	220	unsigned char *data, int count, int write_flag)
1da177e4	221	{
1da177e4 LT	222	void *addr;
	223
	224	if(sun3_dma_orig_addr != NULL)
	225	dvma_unmap(sun3_dma_orig_addr);
	226
757f5bad FT	227	#ifdef SUN3_SCSI_VME
	228	addr = (void *)dvma_map_vme((unsigned long) data, count);
	229	#else
1da177e4	230	addr = (void *)dvma_map((unsigned long) data, count);
757f5bad	231	#endif
1da177e4 LT	232
	233	sun3_dma_orig_addr = addr;
	234	sun3_dma_orig_count = count;
757f5bad FT	235
757f5bad FT	236	#ifndef SUN3_SCSI_VME
1da177e4 LT	237	dregs->fifo_count = 0;
	238	sun3_udc_write(UDC_RESET, UDC_CSR);
	239
	240	/* reset fifo */
	241	dregs->csr &= ~CSR_FIFO;
	242	dregs->csr \|= CSR_FIFO;
757f5bad	243	#endif
1da177e4 LT	244
	245	/* set direction */
	246	if(write_flag)
	247	dregs->csr \|= CSR_SEND;
	248	else
	249	dregs->csr &= ~CSR_SEND;
	250
757f5bad FT	251	#ifdef SUN3_SCSI_VME
	252	dregs->csr \|= CSR_PACK_ENABLE;
	253
	254	dregs->dma_addr_hi = ((unsigned long)addr >> 16);
	255	dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
	256
	257	dregs->dma_count_hi = 0;
	258	dregs->dma_count_lo = 0;
	259	dregs->fifo_count_hi = 0;
	260	dregs->fifo_count = 0;
	261	#else
1da177e4 LT	262	/* byte count for fifo */
	263	dregs->fifo_count = count;
	264
	265	sun3_udc_write(UDC_RESET, UDC_CSR);
	266
	267	/* reset fifo */
	268	dregs->csr &= ~CSR_FIFO;
	269	dregs->csr \|= CSR_FIFO;
	270
	271	if(dregs->fifo_count != count) {
4a98f896 FT	272	shost_printk(KERN_ERR, hostdata->host,
4a98f896 FT	273	"FIFO mismatch %04x not %04x\n",
cd46140a	274	dregs->fifo_count, (unsigned int) count);
4a98f896	275	NCR5380_dprint(NDEBUG_DMA, hostdata->host);
1da177e4 LT	276	}
	277
	278	/* setup udc */
1da177e4 LT	279	udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
1da177e4 LT	280	udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
1da177e4 LT	281	udc_regs->count = count/2; /* count in words */
	282	udc_regs->mode_hi = UDC_MODE_HIWORD;
	283	if(write_flag) {
	284	if(count & 1)
	285	udc_regs->count++;
	286	udc_regs->mode_lo = UDC_MODE_LSEND;
	287	udc_regs->rsel = UDC_RSEL_SEND;
	288	} else {
	289	udc_regs->mode_lo = UDC_MODE_LRECV;
	290	udc_regs->rsel = UDC_RSEL_RECV;
	291	}
	292
	293	/* announce location of regs block */
	294	sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
	295	UDC_CHN_HI);
	296
	297	sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
	298
	299	/* set dma master on */
	300	sun3_udc_write(0xd, UDC_MODE);
	301
	302	/* interrupt enable */
	303	sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
757f5bad	304	#endif
1da177e4 LT	305
	306	return count;
	307
	308	}
	309
4a98f896 FT	310	static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
	311	unsigned char *data, int count)
	312	{
	313	return count;
	314	}
	315
	316	static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
	317	unsigned char *data, int count)
	318	{
	319	return sun3scsi_dma_setup(hostdata, data, count, 0);
	320	}
	321
	322	static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
	323	unsigned char *data, int count)
	324	{
	325	return sun3scsi_dma_setup(hostdata, data, count, 1);
	326	}
	327
	328	static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
1da177e4 LT	329	{
	330	return last_residual;
	331	}
	332
4a98f896 FT	333	static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
4a98f896 FT	334	struct scsi_cmnd *cmd)
1da177e4	335	{
4a98f896 FT	336	int wanted_len = cmd->SCp.this_residual;
4a98f896 FT	337
57292b58	338	if (wanted_len < DMA_MIN_SIZE \|\| blk_rq_is_passthrough(cmd->request))
1da177e4	339	return 0;
e63449c4 FT	340
e63449c4 FT	341	return wanted_len;
1da177e4 LT	342	}
	343
	344	static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
	345	{
757f5bad FT	346	#ifdef SUN3_SCSI_VME
	347	unsigned short csr;
	348
	349	csr = dregs->csr;
	350
	351	dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
	352	dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
1da177e4	353
757f5bad FT	354	dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
	355	dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
	356
	357	/* if(!(csr & CSR_DMA_ENABLE))
	358	* dregs->csr \|= CSR_DMA_ENABLE;
	359	*/
	360	#else
1da177e4	361	sun3_udc_write(UDC_CHN_START, UDC_CSR);
757f5bad	362	#endif
1da177e4 LT	363
	364	return 0;
	365	}
	366
	367	/* clean up after our dma is done */
	368	static int sun3scsi_dma_finish(int write_flag)
	369	{
757f5bad	370	unsigned short __maybe_unused count;
1da177e4 LT	371	unsigned short fifo;
	372	int ret = 0;
	373
	374	sun3_dma_active = 0;
757f5bad FT	375
	376	#ifdef SUN3_SCSI_VME
	377	dregs->csr &= ~CSR_DMA_ENABLE;
	378
	379	fifo = dregs->fifo_count;
	380	if (write_flag) {
	381	if ((fifo > 0) && (fifo < sun3_dma_orig_count))
	382	fifo++;
	383	}
	384
	385	last_residual = fifo;
	386	/* empty bytes from the fifo which didn't make it */
	387	if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
	388	unsigned char *vaddr;
	389
	390	vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
	391
	392	vaddr += (sun3_dma_orig_count - fifo);
	393	vaddr--;
	394
	395	switch (dregs->csr & CSR_LEFT) {
	396	case CSR_LEFT_3:
	397	*vaddr = (dregs->bpack_lo & 0xff00) >> 8;
	398	vaddr--;
	399
	400	case CSR_LEFT_2:
	401	*vaddr = (dregs->bpack_hi & 0x00ff);
	402	vaddr--;
	403
	404	case CSR_LEFT_1:
	405	*vaddr = (dregs->bpack_hi & 0xff00) >> 8;
	406	break;
	407	}
	408	}
	409	#else
1da177e4 LT	410	// check to empty the fifo on a read
	411	if(!write_flag) {
	412	int tmo = 20000; /* .2 sec */
	413
	414	while(1) {
	415	if(dregs->csr & CSR_FIFO_EMPTY)
	416	break;
	417
	418	if(--tmo <= 0) {
	419	printk("sun3scsi: fifo failed to empty!\n");
	420	return 1;
	421	}
	422	udelay(10);
	423	}
	424	}
1da177e4	425
cd46140a FT	426	dregs->udc_addr = 0x32;
	427	udelay(SUN3_DMA_DELAY);
	428	count = 2 * dregs->udc_data;
	429	udelay(SUN3_DMA_DELAY);
1da177e4 LT	430
	431	fifo = dregs->fifo_count;
	432	last_residual = fifo;
	433
	434	/* empty bytes from the fifo which didn't make it */
	435	if((!write_flag) && (count - fifo) == 2) {
	436	unsigned short data;
	437	unsigned char *vaddr;
	438
	439	data = dregs->fifo_data;
	440	vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
	441
	442	vaddr += (sun3_dma_orig_count - fifo);
	443
	444	vaddr[-2] = (data & 0xff00) >> 8;
	445	vaddr[-1] = (data & 0xff);
	446	}
757f5bad	447	#endif
1da177e4 LT	448
	449	dvma_unmap(sun3_dma_orig_addr);
	450	sun3_dma_orig_addr = NULL;
757f5bad FT	451
	452	#ifdef SUN3_SCSI_VME
	453	dregs->dma_addr_hi = 0;
	454	dregs->dma_addr_lo = 0;
	455	dregs->dma_count_hi = 0;
	456	dregs->dma_count_lo = 0;
	457
	458	dregs->fifo_count = 0;
	459	dregs->fifo_count_hi = 0;
	460
	461	dregs->csr &= ~CSR_SEND;
	462	/* dregs->csr \|= CSR_DMA_ENABLE; */
	463	#else
1da177e4 LT	464	sun3_udc_write(UDC_RESET, UDC_CSR);
	465	dregs->fifo_count = 0;
	466	dregs->csr &= ~CSR_SEND;
	467
	468	/* reset fifo */
	469	dregs->csr &= ~CSR_FIFO;
	470	dregs->csr \|= CSR_FIFO;
757f5bad	471	#endif
1da177e4 LT	472
	473	sun3_dma_setup_done = NULL;
	474
	475	return ret;
	476
	477	}
	478
e9db3198	479	#include "NCR5380.c"
1da177e4	480
0d31f875 FT	481	#ifdef SUN3_SCSI_VME
	482	#define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
	483	#define DRV_MODULE_NAME "sun3_scsi_vme"
	484	#else
	485	#define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
	486	#define DRV_MODULE_NAME "sun3_scsi"
	487	#endif
	488
	489	#define PFX DRV_MODULE_NAME ": "
	490
	491	static struct scsi_host_template sun3_scsi_template = {
	492	.module = THIS_MODULE,
	493	.proc_name = DRV_MODULE_NAME,
1da177e4	494	.name = SUN3_SCSI_NAME,
1da177e4 LT	495	.info = sun3scsi_info,
1da177e4 LT	496	.queuecommand = sun3scsi_queue_command,
aa2e2cb1	497	.eh_abort_handler = sun3scsi_abort,
12e5fc66	498	.eh_host_reset_handler = sun3scsi_host_reset,
d572f65f	499	.can_queue = 16,
1da177e4	500	.this_id = 7,
d572f65f FT	501	.sg_tablesize = SG_NONE,
d572f65f FT	502	.cmd_per_lun = 2,
aa2e2cb1	503	.use_clustering = DISABLE_CLUSTERING,
32b26a10	504	.cmd_size = NCR5380_CMD_SIZE,
1da177e4 LT	505	};
1da177e4 LT	506
0d31f875 FT	507	static int __init sun3_scsi_probe(struct platform_device *pdev)
	508	{
	509	struct Scsi_Host *instance;
820682b1	510	struct NCR5380_hostdata *hostdata;
0d31f875 FT	511	int error;
0d31f875 FT	512	struct resource irq, mem;
61e1ce58	513	void __iomem *ioaddr;
ca513fc9	514	int host_flags = 0;
0d31f875 FT	515	#ifdef SUN3_SCSI_VME
	516	int i;
	517	#endif
	518
	519	if (setup_can_queue > 0)
	520	sun3_scsi_template.can_queue = setup_can_queue;
	521	if (setup_cmd_per_lun > 0)
	522	sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
	523	if (setup_sg_tablesize >= 0)
	524	sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
	525	if (setup_hostid >= 0)
	526	sun3_scsi_template.this_id = setup_hostid & 7;
	527
0d31f875 FT	528	#ifdef SUN3_SCSI_VME
	529	ioaddr = NULL;
	530	for (i = 0; i < 2; i++) {
	531	unsigned char x;
	532
	533	irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	534	mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
	535	if (!irq \|\| !mem)
	536	break;
	537
	538	ioaddr = sun3_ioremap(mem->start, resource_size(mem),
	539	SUN3_PAGE_TYPE_VME16);
	540	dregs = (struct sun3_dma_regs *)(ioaddr + 8);
	541
	542	if (sun3_map_test((unsigned long)dregs, &x)) {
	543	unsigned short oldcsr;
	544
	545	oldcsr = dregs->csr;
	546	dregs->csr = 0;
	547	udelay(SUN3_DMA_DELAY);
	548	if (dregs->csr == 0x1400)
	549	break;
	550
	551	dregs->csr = oldcsr;
	552	}
	553
	554	iounmap(ioaddr);
	555	ioaddr = NULL;
	556	}
	557	if (!ioaddr)
	558	return -ENODEV;
	559	#else
	560	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	561	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	562	if (!irq \|\| !mem)
	563	return -ENODEV;
	564
	565	ioaddr = ioremap(mem->start, resource_size(mem));
	566	dregs = (struct sun3_dma_regs *)(ioaddr + 8);
	567
	568	udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
	569	if (!udc_regs) {
	570	pr_err(PFX "couldn't allocate DVMA memory!\n");
	571	iounmap(ioaddr);
	572	return -ENOMEM;
	573	}
	574	#endif
	575
0d31f875 FT	576	instance = scsi_host_alloc(&sun3_scsi_template,
	577	sizeof(struct NCR5380_hostdata));
	578	if (!instance) {
	579	error = -ENOMEM;
	580	goto fail_alloc;
	581	}
0d31f875	582
0d31f875 FT	583	instance->irq = irq->start;
0d31f875 FT	584
820682b1	585	hostdata = shost_priv(instance);
61e1ce58 FT	586	hostdata->base = mem->start;
61e1ce58 FT	587	hostdata->io = ioaddr;
820682b1	588
0ad0eff9 FT	589	error = NCR5380_init(instance, host_flags);
	590	if (error)
	591	goto fail_init;
0d31f875 FT	592
	593	error = request_irq(instance->irq, scsi_sun3_intr, 0,
	594	"NCR5380", instance);
	595	if (error) {
0d31f875 FT	596	pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
	597	instance->host_no, instance->irq);
	598	goto fail_irq;
0d31f875 FT	599	}
	600
	601	dregs->csr = 0;
	602	udelay(SUN3_DMA_DELAY);
	603	dregs->csr = CSR_SCSI \| CSR_FIFO \| CSR_INTR;
	604	udelay(SUN3_DMA_DELAY);
	605	dregs->fifo_count = 0;
	606	#ifdef SUN3_SCSI_VME
	607	dregs->fifo_count_hi = 0;
	608	dregs->dma_addr_hi = 0;
	609	dregs->dma_addr_lo = 0;
	610	dregs->dma_count_hi = 0;
	611	dregs->dma_count_lo = 0;
	612
	613	dregs->ivect = VME_DATA24 \| (instance->irq & 0xff);
	614	#endif
	615
9c3f0e2b	616	NCR5380_maybe_reset_bus(instance);
0d31f875 FT	617
	618	error = scsi_add_host(instance, NULL);
	619	if (error)
	620	goto fail_host;
	621
	622	platform_set_drvdata(pdev, instance);
	623
	624	scsi_scan_host(instance);
	625	return 0;
	626
	627	fail_host:
e4dec680	628	free_irq(instance->irq, instance);
0d31f875 FT	629	fail_irq:
0d31f875 FT	630	NCR5380_exit(instance);
0ad0eff9	631	fail_init:
0d31f875 FT	632	scsi_host_put(instance);
	633	fail_alloc:
	634	if (udc_regs)
	635	dvma_free(udc_regs);
61e1ce58	636	iounmap(ioaddr);
0d31f875 FT	637	return error;
	638	}
	639
	640	static int __exit sun3_scsi_remove(struct platform_device *pdev)
	641	{
	642	struct Scsi_Host *instance = platform_get_drvdata(pdev);
61e1ce58 FT	643	struct NCR5380_hostdata *hostdata = shost_priv(instance);
61e1ce58 FT	644	void __iomem *ioaddr = hostdata->io;
0d31f875 FT	645
0d31f875 FT	646	scsi_remove_host(instance);
e4dec680	647	free_irq(instance->irq, instance);
0d31f875 FT	648	NCR5380_exit(instance);
	649	scsi_host_put(instance);
	650	if (udc_regs)
	651	dvma_free(udc_regs);
61e1ce58	652	iounmap(ioaddr);
0d31f875 FT	653	return 0;
	654	}
	655
	656	static struct platform_driver sun3_scsi_driver = {
	657	.remove = __exit_p(sun3_scsi_remove),
	658	.driver = {
	659	.name = DRV_MODULE_NAME,
0d31f875 FT	660	},
0d31f875 FT	661	};
1da177e4	662
0d31f875	663	module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
1da177e4	664
0d31f875	665	MODULE_ALIAS("platform:" DRV_MODULE_NAME);
1da177e4	666	MODULE_LICENSE("GPL");